frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

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TARGET_K20D50M/MK20D5.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:
fblanc
Date:
Fri Dec 05 15:42:32 2014 +0000
Revision:
93:9dd889aeda0e
Parent:
87:6213f644d804 
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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UserRevisionLine numberNew contents of line
bogdanm 87:6213f644d804 1 /*
bogdanm 87:6213f644d804 2 ** ###################################################################
bogdanm 87:6213f644d804 3 ** Compilers: ARM Compiler
bogdanm 87:6213f644d804 4 ** Freescale C/C++ for Embedded ARM
bogdanm 87:6213f644d804 5 ** GNU C Compiler
bogdanm 87:6213f644d804 6 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 87:6213f644d804 7 **
bogdanm 87:6213f644d804 8 ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
bogdanm 87:6213f644d804 9 ** K20P32M50SF0RM Rev. 1, Oct 2011
bogdanm 87:6213f644d804 10 ** K20P48M50SF0RM Rev. 1, Oct 2011
bogdanm 87:6213f644d804 11 **
bogdanm 87:6213f644d804 12 ** Version: rev. 2.0, 2012-03-19
bogdanm 87:6213f644d804 13 **
bogdanm 87:6213f644d804 14 ** Abstract:
bogdanm 87:6213f644d804 15 ** CMSIS Peripheral Access Layer for MK20D5
bogdanm 87:6213f644d804 16 **
bogdanm 87:6213f644d804 17 ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
bogdanm 87:6213f644d804 18 **
bogdanm 87:6213f644d804 19 ** http: www.freescale.com
bogdanm 87:6213f644d804 20 ** mail: support@freescale.com
bogdanm 87:6213f644d804 21 **
bogdanm 87:6213f644d804 22 ** Revisions:
bogdanm 87:6213f644d804 23 ** - rev. 1.0 (2011-12-15)
bogdanm 87:6213f644d804 24 ** Initial version
bogdanm 87:6213f644d804 25 ** - rev. 2.0 (2012-03-19)
bogdanm 87:6213f644d804 26 ** PDB Peripheral register structure updated.
bogdanm 87:6213f644d804 27 ** DMA Registers and bits for unsupported DMA channels removed.
bogdanm 87:6213f644d804 28 **
bogdanm 87:6213f644d804 29 ** ###################################################################
bogdanm 87:6213f644d804 30 */
bogdanm 87:6213f644d804 31
bogdanm 87:6213f644d804 32 /**
bogdanm 87:6213f644d804 33 * @file MK20D5.h
bogdanm 87:6213f644d804 34 * @version 2.0
bogdanm 87:6213f644d804 35 * @date 2012-03-19
bogdanm 87:6213f644d804 36 * @brief CMSIS Peripheral Access Layer for MK20D5
bogdanm 87:6213f644d804 37 *
bogdanm 87:6213f644d804 38 * CMSIS Peripheral Access Layer for MK20D5
bogdanm 87:6213f644d804 39 */
bogdanm 87:6213f644d804 40
bogdanm 87:6213f644d804 41 #if !defined(MK20D5_H_)
bogdanm 87:6213f644d804 42 #define MK20D5_H_ /**< Symbol preventing repeated inclusion */
bogdanm 87:6213f644d804 43
bogdanm 87:6213f644d804 44 /** Memory map major version (memory maps with equal major version number are
bogdanm 87:6213f644d804 45 * compatible) */
bogdanm 87:6213f644d804 46 #define MCU_MEM_MAP_VERSION 0x0200u
bogdanm 87:6213f644d804 47 /** Memory map minor version */
bogdanm 87:6213f644d804 48 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
bogdanm 87:6213f644d804 49
bogdanm 87:6213f644d804 50 /**
bogdanm 87:6213f644d804 51 * @brief Macro to access a single bit of a peripheral register (bit band region
bogdanm 87:6213f644d804 52 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
bogdanm 87:6213f644d804 53 * @param Reg Register to access.
bogdanm 87:6213f644d804 54 * @param Bit Bit number to access.
bogdanm 87:6213f644d804 55 * @return Value of the targeted bit in the bit band region.
bogdanm 87:6213f644d804 56 */
bogdanm 87:6213f644d804 57 #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
bogdanm 87:6213f644d804 58
bogdanm 87:6213f644d804 59 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 60 -- Interrupt vector numbers
bogdanm 87:6213f644d804 61 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 62
bogdanm 87:6213f644d804 63 /**
bogdanm 87:6213f644d804 64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
bogdanm 87:6213f644d804 65 * @{
bogdanm 87:6213f644d804 66 */
bogdanm 87:6213f644d804 67
bogdanm 87:6213f644d804 68 /** Interrupt Number Definitions */
bogdanm 87:6213f644d804 69 typedef enum IRQn {
bogdanm 87:6213f644d804 70 /* Core interrupts */
bogdanm 87:6213f644d804 71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
bogdanm 87:6213f644d804 72 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
bogdanm 87:6213f644d804 73 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
bogdanm 87:6213f644d804 74 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
bogdanm 87:6213f644d804 75 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
bogdanm 87:6213f644d804 76 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
bogdanm 87:6213f644d804 77 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
bogdanm 87:6213f644d804 78 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
bogdanm 87:6213f644d804 79
bogdanm 87:6213f644d804 80 /* Device specific interrupts */
bogdanm 87:6213f644d804 81 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
bogdanm 87:6213f644d804 82 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
bogdanm 87:6213f644d804 83 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
bogdanm 87:6213f644d804 84 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
bogdanm 87:6213f644d804 85 DMA_Error_IRQn = 4, /**< DMA error interrupt */
bogdanm 87:6213f644d804 86 Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
bogdanm 87:6213f644d804 87 FTFL_IRQn = 6, /**< FTFL interrupt */
bogdanm 87:6213f644d804 88 Read_Collision_IRQn = 7, /**< Read collision interrupt */
bogdanm 87:6213f644d804 89 LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */
bogdanm 87:6213f644d804 90 LLW_IRQn = 9, /**< Low Leakage Wakeup */
bogdanm 87:6213f644d804 91 Watchdog_IRQn = 10, /**< WDOG interrupt */
bogdanm 87:6213f644d804 92 I2C0_IRQn = 11, /**< I2C0 interrupt */
bogdanm 87:6213f644d804 93 SPI0_IRQn = 12, /**< SPI0 interrupt */
bogdanm 87:6213f644d804 94 I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */
bogdanm 87:6213f644d804 95 I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */
bogdanm 87:6213f644d804 96 UART0_LON_IRQn = 15, /**< UART0 LON interrupt */
bogdanm 87:6213f644d804 97 UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */
bogdanm 87:6213f644d804 98 UART0_ERR_IRQn = 17, /**< UART0 error interrupt */
bogdanm 87:6213f644d804 99 UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */
bogdanm 87:6213f644d804 100 UART1_ERR_IRQn = 19, /**< UART1 error interrupt */
bogdanm 87:6213f644d804 101 UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */
bogdanm 87:6213f644d804 102 UART2_ERR_IRQn = 21, /**< UART2 error interrupt */
bogdanm 87:6213f644d804 103 ADC0_IRQn = 22, /**< ADC0 interrupt */
bogdanm 87:6213f644d804 104 CMP0_IRQn = 23, /**< CMP0 interrupt */
bogdanm 87:6213f644d804 105 CMP1_IRQn = 24, /**< CMP1 interrupt */
bogdanm 87:6213f644d804 106 FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */
bogdanm 87:6213f644d804 107 FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */
bogdanm 87:6213f644d804 108 CMT_IRQn = 27, /**< CMT interrupt */
bogdanm 87:6213f644d804 109 RTC_IRQn = 28, /**< RTC interrupt */
bogdanm 87:6213f644d804 110 RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */
bogdanm 87:6213f644d804 111 PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */
bogdanm 87:6213f644d804 112 PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */
bogdanm 87:6213f644d804 113 PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */
bogdanm 87:6213f644d804 114 PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */
bogdanm 87:6213f644d804 115 PDB0_IRQn = 34, /**< PDB0 interrupt */
bogdanm 87:6213f644d804 116 USB0_IRQn = 35, /**< USB0 interrupt */
bogdanm 87:6213f644d804 117 USBDCD_IRQn = 36, /**< USBDCD interrupt */
bogdanm 87:6213f644d804 118 TSI0_IRQn = 37, /**< TSI0 interrupt */
bogdanm 87:6213f644d804 119 MCG_IRQn = 38, /**< MCG interrupt */
bogdanm 87:6213f644d804 120 LPTimer_IRQn = 39, /**< LPTimer interrupt */
bogdanm 87:6213f644d804 121 PORTA_IRQn = 40, /**< Port A interrupt */
bogdanm 87:6213f644d804 122 PORTB_IRQn = 41, /**< Port B interrupt */
bogdanm 87:6213f644d804 123 PORTC_IRQn = 42, /**< Port C interrupt */
bogdanm 87:6213f644d804 124 PORTD_IRQn = 43, /**< Port D interrupt */
bogdanm 87:6213f644d804 125 PORTE_IRQn = 44, /**< Port E interrupt */
bogdanm 87:6213f644d804 126 SWI_IRQn = 45 /**< Software interrupt */
bogdanm 87:6213f644d804 127 } IRQn_Type;
bogdanm 87:6213f644d804 128
bogdanm 87:6213f644d804 129 /**
bogdanm 87:6213f644d804 130 * @}
bogdanm 87:6213f644d804 131 */ /* end of group Interrupt_vector_numbers */
bogdanm 87:6213f644d804 132
bogdanm 87:6213f644d804 133
bogdanm 87:6213f644d804 134 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 135 -- Cortex M4 Core Configuration
bogdanm 87:6213f644d804 136 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 137
bogdanm 87:6213f644d804 138 /**
bogdanm 87:6213f644d804 139 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
bogdanm 87:6213f644d804 140 * @{
bogdanm 87:6213f644d804 141 */
bogdanm 87:6213f644d804 142
bogdanm 87:6213f644d804 143 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
bogdanm 87:6213f644d804 144 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
bogdanm 87:6213f644d804 145 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
bogdanm 87:6213f644d804 146
bogdanm 87:6213f644d804 147 #include "core_cm4.h" /* Core Peripheral Access Layer */
bogdanm 87:6213f644d804 148 #include "system_MK20D5.h" /* Device specific configuration file */
bogdanm 87:6213f644d804 149
bogdanm 87:6213f644d804 150 /**
bogdanm 87:6213f644d804 151 * @}
bogdanm 87:6213f644d804 152 */ /* end of group Cortex_Core_Configuration */
bogdanm 87:6213f644d804 153
bogdanm 87:6213f644d804 154
bogdanm 87:6213f644d804 155 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 156 -- Device Peripheral Access Layer
bogdanm 87:6213f644d804 157 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 158
bogdanm 87:6213f644d804 159 /**
bogdanm 87:6213f644d804 160 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
bogdanm 87:6213f644d804 161 * @{
bogdanm 87:6213f644d804 162 */
bogdanm 87:6213f644d804 163
bogdanm 87:6213f644d804 164
bogdanm 87:6213f644d804 165 /*
bogdanm 87:6213f644d804 166 ** Start of section using anonymous unions
bogdanm 87:6213f644d804 167 */
bogdanm 87:6213f644d804 168
bogdanm 87:6213f644d804 169 #if defined(__ARMCC_VERSION)
bogdanm 87:6213f644d804 170 #pragma push
bogdanm 87:6213f644d804 171 #pragma anon_unions
bogdanm 87:6213f644d804 172 #elif defined(__CWCC__)
bogdanm 87:6213f644d804 173 #pragma push
bogdanm 87:6213f644d804 174 #pragma cpp_extensions on
bogdanm 87:6213f644d804 175 #elif defined(__GNUC__)
bogdanm 87:6213f644d804 176 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 177 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 87:6213f644d804 178 #pragma language=extended
bogdanm 87:6213f644d804 179 #else
bogdanm 87:6213f644d804 180 #error Not supported compiler type
bogdanm 87:6213f644d804 181 #endif
bogdanm 87:6213f644d804 182
bogdanm 87:6213f644d804 183 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 184 -- ADC Peripheral Access Layer
bogdanm 87:6213f644d804 185 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 186
bogdanm 87:6213f644d804 187 /**
bogdanm 87:6213f644d804 188 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
bogdanm 87:6213f644d804 189 * @{
bogdanm 87:6213f644d804 190 */
bogdanm 87:6213f644d804 191
bogdanm 87:6213f644d804 192 /** ADC - Register Layout Typedef */
bogdanm 87:6213f644d804 193 typedef struct {
bogdanm 87:6213f644d804 194 __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
bogdanm 87:6213f644d804 195 __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
bogdanm 87:6213f644d804 196 __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
bogdanm 87:6213f644d804 197 __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
bogdanm 87:6213f644d804 198 __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
bogdanm 87:6213f644d804 199 __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
bogdanm 87:6213f644d804 200 __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
bogdanm 87:6213f644d804 201 __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
bogdanm 87:6213f644d804 202 __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
bogdanm 87:6213f644d804 203 __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
bogdanm 87:6213f644d804 204 __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
bogdanm 87:6213f644d804 205 __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
bogdanm 87:6213f644d804 206 __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
bogdanm 87:6213f644d804 207 __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
bogdanm 87:6213f644d804 208 __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
bogdanm 87:6213f644d804 209 __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
bogdanm 87:6213f644d804 210 __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
bogdanm 87:6213f644d804 211 __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
bogdanm 87:6213f644d804 212 uint8_t RESERVED_0[4];
bogdanm 87:6213f644d804 213 __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
bogdanm 87:6213f644d804 214 __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
bogdanm 87:6213f644d804 215 __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
bogdanm 87:6213f644d804 216 __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
bogdanm 87:6213f644d804 217 __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
bogdanm 87:6213f644d804 218 __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
bogdanm 87:6213f644d804 219 __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
bogdanm 87:6213f644d804 220 } ADC_Type;
bogdanm 87:6213f644d804 221
bogdanm 87:6213f644d804 222 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 223 -- ADC Register Masks
bogdanm 87:6213f644d804 224 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 225
bogdanm 87:6213f644d804 226 /**
bogdanm 87:6213f644d804 227 * @addtogroup ADC_Register_Masks ADC Register Masks
bogdanm 87:6213f644d804 228 * @{
bogdanm 87:6213f644d804 229 */
bogdanm 87:6213f644d804 230
bogdanm 87:6213f644d804 231 /* SC1 Bit Fields */
bogdanm 87:6213f644d804 232 #define ADC_SC1_ADCH_MASK 0x1Fu
bogdanm 87:6213f644d804 233 #define ADC_SC1_ADCH_SHIFT 0
bogdanm 87:6213f644d804 234 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
bogdanm 87:6213f644d804 235 #define ADC_SC1_DIFF_MASK 0x20u
bogdanm 87:6213f644d804 236 #define ADC_SC1_DIFF_SHIFT 5
bogdanm 87:6213f644d804 237 #define ADC_SC1_AIEN_MASK 0x40u
bogdanm 87:6213f644d804 238 #define ADC_SC1_AIEN_SHIFT 6
bogdanm 87:6213f644d804 239 #define ADC_SC1_COCO_MASK 0x80u
bogdanm 87:6213f644d804 240 #define ADC_SC1_COCO_SHIFT 7
bogdanm 87:6213f644d804 241 /* CFG1 Bit Fields */
bogdanm 87:6213f644d804 242 #define ADC_CFG1_ADICLK_MASK 0x3u
bogdanm 87:6213f644d804 243 #define ADC_CFG1_ADICLK_SHIFT 0
bogdanm 87:6213f644d804 244 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
bogdanm 87:6213f644d804 245 #define ADC_CFG1_MODE_MASK 0xCu
bogdanm 87:6213f644d804 246 #define ADC_CFG1_MODE_SHIFT 2
bogdanm 87:6213f644d804 247 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
bogdanm 87:6213f644d804 248 #define ADC_CFG1_ADLSMP_MASK 0x10u
bogdanm 87:6213f644d804 249 #define ADC_CFG1_ADLSMP_SHIFT 4
bogdanm 87:6213f644d804 250 #define ADC_CFG1_ADIV_MASK 0x60u
bogdanm 87:6213f644d804 251 #define ADC_CFG1_ADIV_SHIFT 5
bogdanm 87:6213f644d804 252 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
bogdanm 87:6213f644d804 253 #define ADC_CFG1_ADLPC_MASK 0x80u
bogdanm 87:6213f644d804 254 #define ADC_CFG1_ADLPC_SHIFT 7
bogdanm 87:6213f644d804 255 /* CFG2 Bit Fields */
bogdanm 87:6213f644d804 256 #define ADC_CFG2_ADLSTS_MASK 0x3u
bogdanm 87:6213f644d804 257 #define ADC_CFG2_ADLSTS_SHIFT 0
bogdanm 87:6213f644d804 258 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
bogdanm 87:6213f644d804 259 #define ADC_CFG2_ADHSC_MASK 0x4u
bogdanm 87:6213f644d804 260 #define ADC_CFG2_ADHSC_SHIFT 2
bogdanm 87:6213f644d804 261 #define ADC_CFG2_ADACKEN_MASK 0x8u
bogdanm 87:6213f644d804 262 #define ADC_CFG2_ADACKEN_SHIFT 3
bogdanm 87:6213f644d804 263 #define ADC_CFG2_MUXSEL_MASK 0x10u
bogdanm 87:6213f644d804 264 #define ADC_CFG2_MUXSEL_SHIFT 4
bogdanm 87:6213f644d804 265 /* R Bit Fields */
bogdanm 87:6213f644d804 266 #define ADC_R_D_MASK 0xFFFFu
bogdanm 87:6213f644d804 267 #define ADC_R_D_SHIFT 0
bogdanm 87:6213f644d804 268 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
bogdanm 87:6213f644d804 269 /* CV1 Bit Fields */
bogdanm 87:6213f644d804 270 #define ADC_CV1_CV_MASK 0xFFFFu
bogdanm 87:6213f644d804 271 #define ADC_CV1_CV_SHIFT 0
bogdanm 87:6213f644d804 272 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
bogdanm 87:6213f644d804 273 /* CV2 Bit Fields */
bogdanm 87:6213f644d804 274 #define ADC_CV2_CV_MASK 0xFFFFu
bogdanm 87:6213f644d804 275 #define ADC_CV2_CV_SHIFT 0
bogdanm 87:6213f644d804 276 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
bogdanm 87:6213f644d804 277 /* SC2 Bit Fields */
bogdanm 87:6213f644d804 278 #define ADC_SC2_REFSEL_MASK 0x3u
bogdanm 87:6213f644d804 279 #define ADC_SC2_REFSEL_SHIFT 0
bogdanm 87:6213f644d804 280 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
bogdanm 87:6213f644d804 281 #define ADC_SC2_DMAEN_MASK 0x4u
bogdanm 87:6213f644d804 282 #define ADC_SC2_DMAEN_SHIFT 2
bogdanm 87:6213f644d804 283 #define ADC_SC2_ACREN_MASK 0x8u
bogdanm 87:6213f644d804 284 #define ADC_SC2_ACREN_SHIFT 3
bogdanm 87:6213f644d804 285 #define ADC_SC2_ACFGT_MASK 0x10u
bogdanm 87:6213f644d804 286 #define ADC_SC2_ACFGT_SHIFT 4
bogdanm 87:6213f644d804 287 #define ADC_SC2_ACFE_MASK 0x20u
bogdanm 87:6213f644d804 288 #define ADC_SC2_ACFE_SHIFT 5
bogdanm 87:6213f644d804 289 #define ADC_SC2_ADTRG_MASK 0x40u
bogdanm 87:6213f644d804 290 #define ADC_SC2_ADTRG_SHIFT 6
bogdanm 87:6213f644d804 291 #define ADC_SC2_ADACT_MASK 0x80u
bogdanm 87:6213f644d804 292 #define ADC_SC2_ADACT_SHIFT 7
bogdanm 87:6213f644d804 293 /* SC3 Bit Fields */
bogdanm 87:6213f644d804 294 #define ADC_SC3_AVGS_MASK 0x3u
bogdanm 87:6213f644d804 295 #define ADC_SC3_AVGS_SHIFT 0
bogdanm 87:6213f644d804 296 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
bogdanm 87:6213f644d804 297 #define ADC_SC3_AVGE_MASK 0x4u
bogdanm 87:6213f644d804 298 #define ADC_SC3_AVGE_SHIFT 2
bogdanm 87:6213f644d804 299 #define ADC_SC3_ADCO_MASK 0x8u
bogdanm 87:6213f644d804 300 #define ADC_SC3_ADCO_SHIFT 3
bogdanm 87:6213f644d804 301 #define ADC_SC3_CALF_MASK 0x40u
bogdanm 87:6213f644d804 302 #define ADC_SC3_CALF_SHIFT 6
bogdanm 87:6213f644d804 303 #define ADC_SC3_CAL_MASK 0x80u
bogdanm 87:6213f644d804 304 #define ADC_SC3_CAL_SHIFT 7
bogdanm 87:6213f644d804 305 /* OFS Bit Fields */
bogdanm 87:6213f644d804 306 #define ADC_OFS_OFS_MASK 0xFFFFu
bogdanm 87:6213f644d804 307 #define ADC_OFS_OFS_SHIFT 0
bogdanm 87:6213f644d804 308 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
bogdanm 87:6213f644d804 309 /* PG Bit Fields */
bogdanm 87:6213f644d804 310 #define ADC_PG_PG_MASK 0xFFFFu
bogdanm 87:6213f644d804 311 #define ADC_PG_PG_SHIFT 0
bogdanm 87:6213f644d804 312 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
bogdanm 87:6213f644d804 313 /* MG Bit Fields */
bogdanm 87:6213f644d804 314 #define ADC_MG_MG_MASK 0xFFFFu
bogdanm 87:6213f644d804 315 #define ADC_MG_MG_SHIFT 0
bogdanm 87:6213f644d804 316 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
bogdanm 87:6213f644d804 317 /* CLPD Bit Fields */
bogdanm 87:6213f644d804 318 #define ADC_CLPD_CLPD_MASK 0x3Fu
bogdanm 87:6213f644d804 319 #define ADC_CLPD_CLPD_SHIFT 0
bogdanm 87:6213f644d804 320 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
bogdanm 87:6213f644d804 321 /* CLPS Bit Fields */
bogdanm 87:6213f644d804 322 #define ADC_CLPS_CLPS_MASK 0x3Fu
bogdanm 87:6213f644d804 323 #define ADC_CLPS_CLPS_SHIFT 0
bogdanm 87:6213f644d804 324 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
bogdanm 87:6213f644d804 325 /* CLP4 Bit Fields */
bogdanm 87:6213f644d804 326 #define ADC_CLP4_CLP4_MASK 0x3FFu
bogdanm 87:6213f644d804 327 #define ADC_CLP4_CLP4_SHIFT 0
bogdanm 87:6213f644d804 328 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
bogdanm 87:6213f644d804 329 /* CLP3 Bit Fields */
bogdanm 87:6213f644d804 330 #define ADC_CLP3_CLP3_MASK 0x1FFu
bogdanm 87:6213f644d804 331 #define ADC_CLP3_CLP3_SHIFT 0
bogdanm 87:6213f644d804 332 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
bogdanm 87:6213f644d804 333 /* CLP2 Bit Fields */
bogdanm 87:6213f644d804 334 #define ADC_CLP2_CLP2_MASK 0xFFu
bogdanm 87:6213f644d804 335 #define ADC_CLP2_CLP2_SHIFT 0
bogdanm 87:6213f644d804 336 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
bogdanm 87:6213f644d804 337 /* CLP1 Bit Fields */
bogdanm 87:6213f644d804 338 #define ADC_CLP1_CLP1_MASK 0x7Fu
bogdanm 87:6213f644d804 339 #define ADC_CLP1_CLP1_SHIFT 0
bogdanm 87:6213f644d804 340 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
bogdanm 87:6213f644d804 341 /* CLP0 Bit Fields */
bogdanm 87:6213f644d804 342 #define ADC_CLP0_CLP0_MASK 0x3Fu
bogdanm 87:6213f644d804 343 #define ADC_CLP0_CLP0_SHIFT 0
bogdanm 87:6213f644d804 344 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
bogdanm 87:6213f644d804 345 /* CLMD Bit Fields */
bogdanm 87:6213f644d804 346 #define ADC_CLMD_CLMD_MASK 0x3Fu
bogdanm 87:6213f644d804 347 #define ADC_CLMD_CLMD_SHIFT 0
bogdanm 87:6213f644d804 348 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
bogdanm 87:6213f644d804 349 /* CLMS Bit Fields */
bogdanm 87:6213f644d804 350 #define ADC_CLMS_CLMS_MASK 0x3Fu
bogdanm 87:6213f644d804 351 #define ADC_CLMS_CLMS_SHIFT 0
bogdanm 87:6213f644d804 352 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
bogdanm 87:6213f644d804 353 /* CLM4 Bit Fields */
bogdanm 87:6213f644d804 354 #define ADC_CLM4_CLM4_MASK 0x3FFu
bogdanm 87:6213f644d804 355 #define ADC_CLM4_CLM4_SHIFT 0
bogdanm 87:6213f644d804 356 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
bogdanm 87:6213f644d804 357 /* CLM3 Bit Fields */
bogdanm 87:6213f644d804 358 #define ADC_CLM3_CLM3_MASK 0x1FFu
bogdanm 87:6213f644d804 359 #define ADC_CLM3_CLM3_SHIFT 0
bogdanm 87:6213f644d804 360 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
bogdanm 87:6213f644d804 361 /* CLM2 Bit Fields */
bogdanm 87:6213f644d804 362 #define ADC_CLM2_CLM2_MASK 0xFFu
bogdanm 87:6213f644d804 363 #define ADC_CLM2_CLM2_SHIFT 0
bogdanm 87:6213f644d804 364 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
bogdanm 87:6213f644d804 365 /* CLM1 Bit Fields */
bogdanm 87:6213f644d804 366 #define ADC_CLM1_CLM1_MASK 0x7Fu
bogdanm 87:6213f644d804 367 #define ADC_CLM1_CLM1_SHIFT 0
bogdanm 87:6213f644d804 368 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
bogdanm 87:6213f644d804 369 /* CLM0 Bit Fields */
bogdanm 87:6213f644d804 370 #define ADC_CLM0_CLM0_MASK 0x3Fu
bogdanm 87:6213f644d804 371 #define ADC_CLM0_CLM0_SHIFT 0
bogdanm 87:6213f644d804 372 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
bogdanm 87:6213f644d804 373
bogdanm 87:6213f644d804 374 /**
bogdanm 87:6213f644d804 375 * @}
bogdanm 87:6213f644d804 376 */ /* end of group ADC_Register_Masks */
bogdanm 87:6213f644d804 377
bogdanm 87:6213f644d804 378
bogdanm 87:6213f644d804 379 /* ADC - Peripheral instance base addresses */
bogdanm 87:6213f644d804 380 /** Peripheral ADC0 base address */
bogdanm 87:6213f644d804 381 #define ADC0_BASE (0x4003B000u)
bogdanm 87:6213f644d804 382 /** Peripheral ADC0 base pointer */
bogdanm 87:6213f644d804 383 #define ADC0 ((ADC_Type *)ADC0_BASE)
bogdanm 87:6213f644d804 384
bogdanm 87:6213f644d804 385 /**
bogdanm 87:6213f644d804 386 * @}
bogdanm 87:6213f644d804 387 */ /* end of group ADC_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 388
bogdanm 87:6213f644d804 389
bogdanm 87:6213f644d804 390 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 391 -- CMP Peripheral Access Layer
bogdanm 87:6213f644d804 392 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 393
bogdanm 87:6213f644d804 394 /**
bogdanm 87:6213f644d804 395 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
bogdanm 87:6213f644d804 396 * @{
bogdanm 87:6213f644d804 397 */
bogdanm 87:6213f644d804 398
bogdanm 87:6213f644d804 399 /** CMP - Register Layout Typedef */
bogdanm 87:6213f644d804 400 typedef struct {
bogdanm 87:6213f644d804 401 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
bogdanm 87:6213f644d804 402 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
bogdanm 87:6213f644d804 403 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
bogdanm 87:6213f644d804 404 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
bogdanm 87:6213f644d804 405 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
bogdanm 87:6213f644d804 406 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
bogdanm 87:6213f644d804 407 } CMP_Type;
bogdanm 87:6213f644d804 408
bogdanm 87:6213f644d804 409 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 410 -- CMP Register Masks
bogdanm 87:6213f644d804 411 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 412
bogdanm 87:6213f644d804 413 /**
bogdanm 87:6213f644d804 414 * @addtogroup CMP_Register_Masks CMP Register Masks
bogdanm 87:6213f644d804 415 * @{
bogdanm 87:6213f644d804 416 */
bogdanm 87:6213f644d804 417
bogdanm 87:6213f644d804 418 /* CR0 Bit Fields */
bogdanm 87:6213f644d804 419 #define CMP_CR0_HYSTCTR_MASK 0x3u
bogdanm 87:6213f644d804 420 #define CMP_CR0_HYSTCTR_SHIFT 0
bogdanm 87:6213f644d804 421 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
bogdanm 87:6213f644d804 422 #define CMP_CR0_FILTER_CNT_MASK 0x70u
bogdanm 87:6213f644d804 423 #define CMP_CR0_FILTER_CNT_SHIFT 4
bogdanm 87:6213f644d804 424 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
bogdanm 87:6213f644d804 425 /* CR1 Bit Fields */
bogdanm 87:6213f644d804 426 #define CMP_CR1_EN_MASK 0x1u
bogdanm 87:6213f644d804 427 #define CMP_CR1_EN_SHIFT 0
bogdanm 87:6213f644d804 428 #define CMP_CR1_OPE_MASK 0x2u
bogdanm 87:6213f644d804 429 #define CMP_CR1_OPE_SHIFT 1
bogdanm 87:6213f644d804 430 #define CMP_CR1_COS_MASK 0x4u
bogdanm 87:6213f644d804 431 #define CMP_CR1_COS_SHIFT 2
bogdanm 87:6213f644d804 432 #define CMP_CR1_INV_MASK 0x8u
bogdanm 87:6213f644d804 433 #define CMP_CR1_INV_SHIFT 3
bogdanm 87:6213f644d804 434 #define CMP_CR1_PMODE_MASK 0x10u
bogdanm 87:6213f644d804 435 #define CMP_CR1_PMODE_SHIFT 4
bogdanm 87:6213f644d804 436 #define CMP_CR1_WE_MASK 0x40u
bogdanm 87:6213f644d804 437 #define CMP_CR1_WE_SHIFT 6
bogdanm 87:6213f644d804 438 #define CMP_CR1_SE_MASK 0x80u
bogdanm 87:6213f644d804 439 #define CMP_CR1_SE_SHIFT 7
bogdanm 87:6213f644d804 440 /* FPR Bit Fields */
bogdanm 87:6213f644d804 441 #define CMP_FPR_FILT_PER_MASK 0xFFu
bogdanm 87:6213f644d804 442 #define CMP_FPR_FILT_PER_SHIFT 0
bogdanm 87:6213f644d804 443 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
bogdanm 87:6213f644d804 444 /* SCR Bit Fields */
bogdanm 87:6213f644d804 445 #define CMP_SCR_COUT_MASK 0x1u
bogdanm 87:6213f644d804 446 #define CMP_SCR_COUT_SHIFT 0
bogdanm 87:6213f644d804 447 #define CMP_SCR_CFF_MASK 0x2u
bogdanm 87:6213f644d804 448 #define CMP_SCR_CFF_SHIFT 1
bogdanm 87:6213f644d804 449 #define CMP_SCR_CFR_MASK 0x4u
bogdanm 87:6213f644d804 450 #define CMP_SCR_CFR_SHIFT 2
bogdanm 87:6213f644d804 451 #define CMP_SCR_IEF_MASK 0x8u
bogdanm 87:6213f644d804 452 #define CMP_SCR_IEF_SHIFT 3
bogdanm 87:6213f644d804 453 #define CMP_SCR_IER_MASK 0x10u
bogdanm 87:6213f644d804 454 #define CMP_SCR_IER_SHIFT 4
bogdanm 87:6213f644d804 455 #define CMP_SCR_DMAEN_MASK 0x40u
bogdanm 87:6213f644d804 456 #define CMP_SCR_DMAEN_SHIFT 6
bogdanm 87:6213f644d804 457 /* DACCR Bit Fields */
bogdanm 87:6213f644d804 458 #define CMP_DACCR_VOSEL_MASK 0x3Fu
bogdanm 87:6213f644d804 459 #define CMP_DACCR_VOSEL_SHIFT 0
bogdanm 87:6213f644d804 460 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
bogdanm 87:6213f644d804 461 #define CMP_DACCR_VRSEL_MASK 0x40u
bogdanm 87:6213f644d804 462 #define CMP_DACCR_VRSEL_SHIFT 6
bogdanm 87:6213f644d804 463 #define CMP_DACCR_DACEN_MASK 0x80u
bogdanm 87:6213f644d804 464 #define CMP_DACCR_DACEN_SHIFT 7
bogdanm 87:6213f644d804 465 /* MUXCR Bit Fields */
bogdanm 87:6213f644d804 466 #define CMP_MUXCR_MSEL_MASK 0x7u
bogdanm 87:6213f644d804 467 #define CMP_MUXCR_MSEL_SHIFT 0
bogdanm 87:6213f644d804 468 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
bogdanm 87:6213f644d804 469 #define CMP_MUXCR_PSEL_MASK 0x38u
bogdanm 87:6213f644d804 470 #define CMP_MUXCR_PSEL_SHIFT 3
bogdanm 87:6213f644d804 471 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
bogdanm 87:6213f644d804 472
bogdanm 87:6213f644d804 473 /**
bogdanm 87:6213f644d804 474 * @}
bogdanm 87:6213f644d804 475 */ /* end of group CMP_Register_Masks */
bogdanm 87:6213f644d804 476
bogdanm 87:6213f644d804 477
bogdanm 87:6213f644d804 478 /* CMP - Peripheral instance base addresses */
bogdanm 87:6213f644d804 479 /** Peripheral CMP0 base address */
bogdanm 87:6213f644d804 480 #define CMP0_BASE (0x40073000u)
bogdanm 87:6213f644d804 481 /** Peripheral CMP0 base pointer */
bogdanm 87:6213f644d804 482 #define CMP0 ((CMP_Type *)CMP0_BASE)
bogdanm 87:6213f644d804 483 /** Peripheral CMP1 base address */
bogdanm 87:6213f644d804 484 #define CMP1_BASE (0x40073008u)
bogdanm 87:6213f644d804 485 /** Peripheral CMP1 base pointer */
bogdanm 87:6213f644d804 486 #define CMP1 ((CMP_Type *)CMP1_BASE)
bogdanm 87:6213f644d804 487
bogdanm 87:6213f644d804 488 /**
bogdanm 87:6213f644d804 489 * @}
bogdanm 87:6213f644d804 490 */ /* end of group CMP_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 491
bogdanm 87:6213f644d804 492
bogdanm 87:6213f644d804 493 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 494 -- CMT Peripheral Access Layer
bogdanm 87:6213f644d804 495 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 496
bogdanm 87:6213f644d804 497 /**
bogdanm 87:6213f644d804 498 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
bogdanm 87:6213f644d804 499 * @{
bogdanm 87:6213f644d804 500 */
bogdanm 87:6213f644d804 501
bogdanm 87:6213f644d804 502 /** CMT - Register Layout Typedef */
bogdanm 87:6213f644d804 503 typedef struct {
bogdanm 87:6213f644d804 504 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
bogdanm 87:6213f644d804 505 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
bogdanm 87:6213f644d804 506 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
bogdanm 87:6213f644d804 507 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
bogdanm 87:6213f644d804 508 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
bogdanm 87:6213f644d804 509 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
bogdanm 87:6213f644d804 510 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
bogdanm 87:6213f644d804 511 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
bogdanm 87:6213f644d804 512 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
bogdanm 87:6213f644d804 513 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
bogdanm 87:6213f644d804 514 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
bogdanm 87:6213f644d804 515 __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
bogdanm 87:6213f644d804 516 } CMT_Type;
bogdanm 87:6213f644d804 517
bogdanm 87:6213f644d804 518 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 519 -- CMT Register Masks
bogdanm 87:6213f644d804 520 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 521
bogdanm 87:6213f644d804 522 /**
bogdanm 87:6213f644d804 523 * @addtogroup CMT_Register_Masks CMT Register Masks
bogdanm 87:6213f644d804 524 * @{
bogdanm 87:6213f644d804 525 */
bogdanm 87:6213f644d804 526
bogdanm 87:6213f644d804 527 /* CGH1 Bit Fields */
bogdanm 87:6213f644d804 528 #define CMT_CGH1_PH_MASK 0xFFu
bogdanm 87:6213f644d804 529 #define CMT_CGH1_PH_SHIFT 0
bogdanm 87:6213f644d804 530 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
bogdanm 87:6213f644d804 531 /* CGL1 Bit Fields */
bogdanm 87:6213f644d804 532 #define CMT_CGL1_PL_MASK 0xFFu
bogdanm 87:6213f644d804 533 #define CMT_CGL1_PL_SHIFT 0
bogdanm 87:6213f644d804 534 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
bogdanm 87:6213f644d804 535 /* CGH2 Bit Fields */
bogdanm 87:6213f644d804 536 #define CMT_CGH2_SH_MASK 0xFFu
bogdanm 87:6213f644d804 537 #define CMT_CGH2_SH_SHIFT 0
bogdanm 87:6213f644d804 538 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
bogdanm 87:6213f644d804 539 /* CGL2 Bit Fields */
bogdanm 87:6213f644d804 540 #define CMT_CGL2_SL_MASK 0xFFu
bogdanm 87:6213f644d804 541 #define CMT_CGL2_SL_SHIFT 0
bogdanm 87:6213f644d804 542 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
bogdanm 87:6213f644d804 543 /* OC Bit Fields */
bogdanm 87:6213f644d804 544 #define CMT_OC_IROPEN_MASK 0x20u
bogdanm 87:6213f644d804 545 #define CMT_OC_IROPEN_SHIFT 5
bogdanm 87:6213f644d804 546 #define CMT_OC_CMTPOL_MASK 0x40u
bogdanm 87:6213f644d804 547 #define CMT_OC_CMTPOL_SHIFT 6
bogdanm 87:6213f644d804 548 #define CMT_OC_IROL_MASK 0x80u
bogdanm 87:6213f644d804 549 #define CMT_OC_IROL_SHIFT 7
bogdanm 87:6213f644d804 550 /* MSC Bit Fields */
bogdanm 87:6213f644d804 551 #define CMT_MSC_MCGEN_MASK 0x1u
bogdanm 87:6213f644d804 552 #define CMT_MSC_MCGEN_SHIFT 0
bogdanm 87:6213f644d804 553 #define CMT_MSC_EOCIE_MASK 0x2u
bogdanm 87:6213f644d804 554 #define CMT_MSC_EOCIE_SHIFT 1
bogdanm 87:6213f644d804 555 #define CMT_MSC_FSK_MASK 0x4u
bogdanm 87:6213f644d804 556 #define CMT_MSC_FSK_SHIFT 2
bogdanm 87:6213f644d804 557 #define CMT_MSC_BASE_MASK 0x8u
bogdanm 87:6213f644d804 558 #define CMT_MSC_BASE_SHIFT 3
bogdanm 87:6213f644d804 559 #define CMT_MSC_EXSPC_MASK 0x10u
bogdanm 87:6213f644d804 560 #define CMT_MSC_EXSPC_SHIFT 4
bogdanm 87:6213f644d804 561 #define CMT_MSC_CMTDIV_MASK 0x60u
bogdanm 87:6213f644d804 562 #define CMT_MSC_CMTDIV_SHIFT 5
bogdanm 87:6213f644d804 563 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
bogdanm 87:6213f644d804 564 #define CMT_MSC_EOCF_MASK 0x80u
bogdanm 87:6213f644d804 565 #define CMT_MSC_EOCF_SHIFT 7
bogdanm 87:6213f644d804 566 /* CMD1 Bit Fields */
bogdanm 87:6213f644d804 567 #define CMT_CMD1_MB_MASK 0xFFu
bogdanm 87:6213f644d804 568 #define CMT_CMD1_MB_SHIFT 0
bogdanm 87:6213f644d804 569 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
bogdanm 87:6213f644d804 570 /* CMD2 Bit Fields */
bogdanm 87:6213f644d804 571 #define CMT_CMD2_MB_MASK 0xFFu
bogdanm 87:6213f644d804 572 #define CMT_CMD2_MB_SHIFT 0
bogdanm 87:6213f644d804 573 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
bogdanm 87:6213f644d804 574 /* CMD3 Bit Fields */
bogdanm 87:6213f644d804 575 #define CMT_CMD3_SB_MASK 0xFFu
bogdanm 87:6213f644d804 576 #define CMT_CMD3_SB_SHIFT 0
bogdanm 87:6213f644d804 577 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
bogdanm 87:6213f644d804 578 /* CMD4 Bit Fields */
bogdanm 87:6213f644d804 579 #define CMT_CMD4_SB_MASK 0xFFu
bogdanm 87:6213f644d804 580 #define CMT_CMD4_SB_SHIFT 0
bogdanm 87:6213f644d804 581 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
bogdanm 87:6213f644d804 582 /* PPS Bit Fields */
bogdanm 87:6213f644d804 583 #define CMT_PPS_PPSDIV_MASK 0xFu
bogdanm 87:6213f644d804 584 #define CMT_PPS_PPSDIV_SHIFT 0
bogdanm 87:6213f644d804 585 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
bogdanm 87:6213f644d804 586 /* DMA Bit Fields */
bogdanm 87:6213f644d804 587 #define CMT_DMA_DMA_MASK 0x1u
bogdanm 87:6213f644d804 588 #define CMT_DMA_DMA_SHIFT 0
bogdanm 87:6213f644d804 589
bogdanm 87:6213f644d804 590 /**
bogdanm 87:6213f644d804 591 * @}
bogdanm 87:6213f644d804 592 */ /* end of group CMT_Register_Masks */
bogdanm 87:6213f644d804 593
bogdanm 87:6213f644d804 594
bogdanm 87:6213f644d804 595 /* CMT - Peripheral instance base addresses */
bogdanm 87:6213f644d804 596 /** Peripheral CMT base address */
bogdanm 87:6213f644d804 597 #define CMT_BASE (0x40062000u)
bogdanm 87:6213f644d804 598 /** Peripheral CMT base pointer */
bogdanm 87:6213f644d804 599 #define CMT ((CMT_Type *)CMT_BASE)
bogdanm 87:6213f644d804 600
bogdanm 87:6213f644d804 601 /**
bogdanm 87:6213f644d804 602 * @}
bogdanm 87:6213f644d804 603 */ /* end of group CMT_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 604
bogdanm 87:6213f644d804 605
bogdanm 87:6213f644d804 606 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 607 -- CRC Peripheral Access Layer
bogdanm 87:6213f644d804 608 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 609
bogdanm 87:6213f644d804 610 /**
bogdanm 87:6213f644d804 611 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
bogdanm 87:6213f644d804 612 * @{
bogdanm 87:6213f644d804 613 */
bogdanm 87:6213f644d804 614
bogdanm 87:6213f644d804 615 /** CRC - Register Layout Typedef */
bogdanm 87:6213f644d804 616 typedef struct {
bogdanm 87:6213f644d804 617 union { /* offset: 0x0 */
bogdanm 87:6213f644d804 618 struct { /* offset: 0x0 */
bogdanm 87:6213f644d804 619 __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
bogdanm 87:6213f644d804 620 __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
bogdanm 87:6213f644d804 621 } ACCESS16BIT;
bogdanm 87:6213f644d804 622 __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
bogdanm 87:6213f644d804 623 struct { /* offset: 0x0 */
bogdanm 87:6213f644d804 624 __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
bogdanm 87:6213f644d804 625 __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
bogdanm 87:6213f644d804 626 __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
bogdanm 87:6213f644d804 627 __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
bogdanm 87:6213f644d804 628 } ACCESS8BIT;
bogdanm 87:6213f644d804 629 };
bogdanm 87:6213f644d804 630 union { /* offset: 0x4 */
bogdanm 87:6213f644d804 631 struct { /* offset: 0x4 */
bogdanm 87:6213f644d804 632 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
bogdanm 87:6213f644d804 633 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
bogdanm 87:6213f644d804 634 } GPOLY_ACCESS16BIT;
bogdanm 87:6213f644d804 635 __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
bogdanm 87:6213f644d804 636 struct { /* offset: 0x4 */
bogdanm 87:6213f644d804 637 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
bogdanm 87:6213f644d804 638 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
bogdanm 87:6213f644d804 639 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
bogdanm 87:6213f644d804 640 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
bogdanm 87:6213f644d804 641 } GPOLY_ACCESS8BIT;
bogdanm 87:6213f644d804 642 };
bogdanm 87:6213f644d804 643 union { /* offset: 0x8 */
bogdanm 87:6213f644d804 644 __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
bogdanm 87:6213f644d804 645 struct { /* offset: 0x8 */
bogdanm 87:6213f644d804 646 uint8_t RESERVED_0[3];
bogdanm 87:6213f644d804 647 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
bogdanm 87:6213f644d804 648 } CTRL_ACCESS8BIT;
bogdanm 87:6213f644d804 649 };
bogdanm 87:6213f644d804 650 } CRC_Type;
bogdanm 87:6213f644d804 651
bogdanm 87:6213f644d804 652 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 653 -- CRC Register Masks
bogdanm 87:6213f644d804 654 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 655
bogdanm 87:6213f644d804 656 /**
bogdanm 87:6213f644d804 657 * @addtogroup CRC_Register_Masks CRC Register Masks
bogdanm 87:6213f644d804 658 * @{
bogdanm 87:6213f644d804 659 */
bogdanm 87:6213f644d804 660
bogdanm 87:6213f644d804 661 /* CRCL Bit Fields */
bogdanm 87:6213f644d804 662 #define CRC_CRCL_CRCL_MASK 0xFFFFu
bogdanm 87:6213f644d804 663 #define CRC_CRCL_CRCL_SHIFT 0
bogdanm 87:6213f644d804 664 #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
bogdanm 87:6213f644d804 665 /* CRCH Bit Fields */
bogdanm 87:6213f644d804 666 #define CRC_CRCH_CRCH_MASK 0xFFFFu
bogdanm 87:6213f644d804 667 #define CRC_CRCH_CRCH_SHIFT 0
bogdanm 87:6213f644d804 668 #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
bogdanm 87:6213f644d804 669 /* CRC Bit Fields */
bogdanm 87:6213f644d804 670 #define CRC_CRC_LL_MASK 0xFFu
bogdanm 87:6213f644d804 671 #define CRC_CRC_LL_SHIFT 0
bogdanm 87:6213f644d804 672 #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
bogdanm 87:6213f644d804 673 #define CRC_CRC_LU_MASK 0xFF00u
bogdanm 87:6213f644d804 674 #define CRC_CRC_LU_SHIFT 8
bogdanm 87:6213f644d804 675 #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
bogdanm 87:6213f644d804 676 #define CRC_CRC_HL_MASK 0xFF0000u
bogdanm 87:6213f644d804 677 #define CRC_CRC_HL_SHIFT 16
bogdanm 87:6213f644d804 678 #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
bogdanm 87:6213f644d804 679 #define CRC_CRC_HU_MASK 0xFF000000u
bogdanm 87:6213f644d804 680 #define CRC_CRC_HU_SHIFT 24
bogdanm 87:6213f644d804 681 #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
bogdanm 87:6213f644d804 682 /* CRCLL Bit Fields */
bogdanm 87:6213f644d804 683 #define CRC_CRCLL_CRCLL_MASK 0xFFu
bogdanm 87:6213f644d804 684 #define CRC_CRCLL_CRCLL_SHIFT 0
bogdanm 87:6213f644d804 685 #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
bogdanm 87:6213f644d804 686 /* CRCLU Bit Fields */
bogdanm 87:6213f644d804 687 #define CRC_CRCLU_CRCLU_MASK 0xFFu
bogdanm 87:6213f644d804 688 #define CRC_CRCLU_CRCLU_SHIFT 0
bogdanm 87:6213f644d804 689 #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
bogdanm 87:6213f644d804 690 /* CRCHL Bit Fields */
bogdanm 87:6213f644d804 691 #define CRC_CRCHL_CRCHL_MASK 0xFFu
bogdanm 87:6213f644d804 692 #define CRC_CRCHL_CRCHL_SHIFT 0
bogdanm 87:6213f644d804 693 #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
bogdanm 87:6213f644d804 694 /* CRCHU Bit Fields */
bogdanm 87:6213f644d804 695 #define CRC_CRCHU_CRCHU_MASK 0xFFu
bogdanm 87:6213f644d804 696 #define CRC_CRCHU_CRCHU_SHIFT 0
bogdanm 87:6213f644d804 697 #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
bogdanm 87:6213f644d804 698 /* GPOLYL Bit Fields */
bogdanm 87:6213f644d804 699 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
bogdanm 87:6213f644d804 700 #define CRC_GPOLYL_GPOLYL_SHIFT 0
bogdanm 87:6213f644d804 701 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
bogdanm 87:6213f644d804 702 /* GPOLYH Bit Fields */
bogdanm 87:6213f644d804 703 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
bogdanm 87:6213f644d804 704 #define CRC_GPOLYH_GPOLYH_SHIFT 0
bogdanm 87:6213f644d804 705 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
bogdanm 87:6213f644d804 706 /* GPOLY Bit Fields */
bogdanm 87:6213f644d804 707 #define CRC_GPOLY_LOW_MASK 0xFFFFu
bogdanm 87:6213f644d804 708 #define CRC_GPOLY_LOW_SHIFT 0
bogdanm 87:6213f644d804 709 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
bogdanm 87:6213f644d804 710 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 711 #define CRC_GPOLY_HIGH_SHIFT 16
bogdanm 87:6213f644d804 712 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
bogdanm 87:6213f644d804 713 /* GPOLYLL Bit Fields */
bogdanm 87:6213f644d804 714 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
bogdanm 87:6213f644d804 715 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
bogdanm 87:6213f644d804 716 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
bogdanm 87:6213f644d804 717 /* GPOLYLU Bit Fields */
bogdanm 87:6213f644d804 718 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
bogdanm 87:6213f644d804 719 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
bogdanm 87:6213f644d804 720 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
bogdanm 87:6213f644d804 721 /* GPOLYHL Bit Fields */
bogdanm 87:6213f644d804 722 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
bogdanm 87:6213f644d804 723 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
bogdanm 87:6213f644d804 724 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
bogdanm 87:6213f644d804 725 /* GPOLYHU Bit Fields */
bogdanm 87:6213f644d804 726 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
bogdanm 87:6213f644d804 727 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
bogdanm 87:6213f644d804 728 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
bogdanm 87:6213f644d804 729 /* CTRL Bit Fields */
bogdanm 87:6213f644d804 730 #define CRC_CTRL_TCRC_MASK 0x1000000u
bogdanm 87:6213f644d804 731 #define CRC_CTRL_TCRC_SHIFT 24
bogdanm 87:6213f644d804 732 #define CRC_CTRL_WAS_MASK 0x2000000u
bogdanm 87:6213f644d804 733 #define CRC_CTRL_WAS_SHIFT 25
bogdanm 87:6213f644d804 734 #define CRC_CTRL_FXOR_MASK 0x4000000u
bogdanm 87:6213f644d804 735 #define CRC_CTRL_FXOR_SHIFT 26
bogdanm 87:6213f644d804 736 #define CRC_CTRL_TOTR_MASK 0x30000000u
bogdanm 87:6213f644d804 737 #define CRC_CTRL_TOTR_SHIFT 28
bogdanm 87:6213f644d804 738 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
bogdanm 87:6213f644d804 739 #define CRC_CTRL_TOT_MASK 0xC0000000u
bogdanm 87:6213f644d804 740 #define CRC_CTRL_TOT_SHIFT 30
bogdanm 87:6213f644d804 741 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
bogdanm 87:6213f644d804 742 /* CTRLHU Bit Fields */
bogdanm 87:6213f644d804 743 #define CRC_CTRLHU_TCRC_MASK 0x1u
bogdanm 87:6213f644d804 744 #define CRC_CTRLHU_TCRC_SHIFT 0
bogdanm 87:6213f644d804 745 #define CRC_CTRLHU_WAS_MASK 0x2u
bogdanm 87:6213f644d804 746 #define CRC_CTRLHU_WAS_SHIFT 1
bogdanm 87:6213f644d804 747 #define CRC_CTRLHU_FXOR_MASK 0x4u
bogdanm 87:6213f644d804 748 #define CRC_CTRLHU_FXOR_SHIFT 2
bogdanm 87:6213f644d804 749 #define CRC_CTRLHU_TOTR_MASK 0x30u
bogdanm 87:6213f644d804 750 #define CRC_CTRLHU_TOTR_SHIFT 4
bogdanm 87:6213f644d804 751 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
bogdanm 87:6213f644d804 752 #define CRC_CTRLHU_TOT_MASK 0xC0u
bogdanm 87:6213f644d804 753 #define CRC_CTRLHU_TOT_SHIFT 6
bogdanm 87:6213f644d804 754 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
bogdanm 87:6213f644d804 755
bogdanm 87:6213f644d804 756 /**
bogdanm 87:6213f644d804 757 * @}
bogdanm 87:6213f644d804 758 */ /* end of group CRC_Register_Masks */
bogdanm 87:6213f644d804 759
bogdanm 87:6213f644d804 760
bogdanm 87:6213f644d804 761 /* CRC - Peripheral instance base addresses */
bogdanm 87:6213f644d804 762 /** Peripheral CRC base address */
bogdanm 87:6213f644d804 763 #define CRC_BASE (0x40032000u)
bogdanm 87:6213f644d804 764 /** Peripheral CRC base pointer */
bogdanm 87:6213f644d804 765 #define CRC0 ((CRC_Type *)CRC_BASE)
bogdanm 87:6213f644d804 766
bogdanm 87:6213f644d804 767 /**
bogdanm 87:6213f644d804 768 * @}
bogdanm 87:6213f644d804 769 */ /* end of group CRC_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 770
bogdanm 87:6213f644d804 771
bogdanm 87:6213f644d804 772 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 773 -- DMA Peripheral Access Layer
bogdanm 87:6213f644d804 774 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 775
bogdanm 87:6213f644d804 776 /**
bogdanm 87:6213f644d804 777 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
bogdanm 87:6213f644d804 778 * @{
bogdanm 87:6213f644d804 779 */
bogdanm 87:6213f644d804 780
bogdanm 87:6213f644d804 781 /** DMA - Register Layout Typedef */
bogdanm 87:6213f644d804 782 typedef struct {
bogdanm 87:6213f644d804 783 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
bogdanm 87:6213f644d804 784 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
bogdanm 87:6213f644d804 785 uint8_t RESERVED_0[4];
bogdanm 87:6213f644d804 786 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
bogdanm 87:6213f644d804 787 uint8_t RESERVED_1[4];
bogdanm 87:6213f644d804 788 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
bogdanm 87:6213f644d804 789 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
bogdanm 87:6213f644d804 790 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
bogdanm 87:6213f644d804 791 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
bogdanm 87:6213f644d804 792 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
bogdanm 87:6213f644d804 793 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
bogdanm 87:6213f644d804 794 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
bogdanm 87:6213f644d804 795 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
bogdanm 87:6213f644d804 796 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
bogdanm 87:6213f644d804 797 uint8_t RESERVED_2[4];
bogdanm 87:6213f644d804 798 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
bogdanm 87:6213f644d804 799 uint8_t RESERVED_3[4];
bogdanm 87:6213f644d804 800 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
bogdanm 87:6213f644d804 801 uint8_t RESERVED_4[4];
bogdanm 87:6213f644d804 802 __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
bogdanm 87:6213f644d804 803 uint8_t RESERVED_5[200];
bogdanm 87:6213f644d804 804 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
bogdanm 87:6213f644d804 805 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
bogdanm 87:6213f644d804 806 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
bogdanm 87:6213f644d804 807 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
bogdanm 87:6213f644d804 808 uint8_t RESERVED_6[3836];
bogdanm 87:6213f644d804 809 struct { /* offset: 0x1000, array step: 0x20 */
bogdanm 87:6213f644d804 810 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
bogdanm 87:6213f644d804 811 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
bogdanm 87:6213f644d804 812 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
bogdanm 87:6213f644d804 813 union { /* offset: 0x1008, array step: 0x20 */
bogdanm 87:6213f644d804 814 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
bogdanm 87:6213f644d804 815 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
bogdanm 87:6213f644d804 816 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
bogdanm 87:6213f644d804 817 };
bogdanm 87:6213f644d804 818 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
bogdanm 87:6213f644d804 819 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
bogdanm 87:6213f644d804 820 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
bogdanm 87:6213f644d804 821 union { /* offset: 0x1016, array step: 0x20 */
bogdanm 87:6213f644d804 822 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
bogdanm 87:6213f644d804 823 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
bogdanm 87:6213f644d804 824 };
bogdanm 87:6213f644d804 825 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
bogdanm 87:6213f644d804 826 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
bogdanm 87:6213f644d804 827 union { /* offset: 0x101E, array step: 0x20 */
bogdanm 87:6213f644d804 828 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
bogdanm 87:6213f644d804 829 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
bogdanm 87:6213f644d804 830 };
bogdanm 87:6213f644d804 831 } TCD[4];
bogdanm 87:6213f644d804 832 } DMA_Type;
bogdanm 87:6213f644d804 833
bogdanm 87:6213f644d804 834 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 835 -- DMA Register Masks
bogdanm 87:6213f644d804 836 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 837
bogdanm 87:6213f644d804 838 /**
bogdanm 87:6213f644d804 839 * @addtogroup DMA_Register_Masks DMA Register Masks
bogdanm 87:6213f644d804 840 * @{
bogdanm 87:6213f644d804 841 */
bogdanm 87:6213f644d804 842
bogdanm 87:6213f644d804 843 /* CR Bit Fields */
bogdanm 87:6213f644d804 844 #define DMA_CR_EDBG_MASK 0x2u
bogdanm 87:6213f644d804 845 #define DMA_CR_EDBG_SHIFT 1
bogdanm 87:6213f644d804 846 #define DMA_CR_ERCA_MASK 0x4u
bogdanm 87:6213f644d804 847 #define DMA_CR_ERCA_SHIFT 2
bogdanm 87:6213f644d804 848 #define DMA_CR_HOE_MASK 0x10u
bogdanm 87:6213f644d804 849 #define DMA_CR_HOE_SHIFT 4
bogdanm 87:6213f644d804 850 #define DMA_CR_HALT_MASK 0x20u
bogdanm 87:6213f644d804 851 #define DMA_CR_HALT_SHIFT 5
bogdanm 87:6213f644d804 852 #define DMA_CR_CLM_MASK 0x40u
bogdanm 87:6213f644d804 853 #define DMA_CR_CLM_SHIFT 6
bogdanm 87:6213f644d804 854 #define DMA_CR_EMLM_MASK 0x80u
bogdanm 87:6213f644d804 855 #define DMA_CR_EMLM_SHIFT 7
bogdanm 87:6213f644d804 856 #define DMA_CR_ECX_MASK 0x10000u
bogdanm 87:6213f644d804 857 #define DMA_CR_ECX_SHIFT 16
bogdanm 87:6213f644d804 858 #define DMA_CR_CX_MASK 0x20000u
bogdanm 87:6213f644d804 859 #define DMA_CR_CX_SHIFT 17
bogdanm 87:6213f644d804 860 /* ES Bit Fields */
bogdanm 87:6213f644d804 861 #define DMA_ES_DBE_MASK 0x1u
bogdanm 87:6213f644d804 862 #define DMA_ES_DBE_SHIFT 0
bogdanm 87:6213f644d804 863 #define DMA_ES_SBE_MASK 0x2u
bogdanm 87:6213f644d804 864 #define DMA_ES_SBE_SHIFT 1
bogdanm 87:6213f644d804 865 #define DMA_ES_SGE_MASK 0x4u
bogdanm 87:6213f644d804 866 #define DMA_ES_SGE_SHIFT 2
bogdanm 87:6213f644d804 867 #define DMA_ES_NCE_MASK 0x8u
bogdanm 87:6213f644d804 868 #define DMA_ES_NCE_SHIFT 3
bogdanm 87:6213f644d804 869 #define DMA_ES_DOE_MASK 0x10u
bogdanm 87:6213f644d804 870 #define DMA_ES_DOE_SHIFT 4
bogdanm 87:6213f644d804 871 #define DMA_ES_DAE_MASK 0x20u
bogdanm 87:6213f644d804 872 #define DMA_ES_DAE_SHIFT 5
bogdanm 87:6213f644d804 873 #define DMA_ES_SOE_MASK 0x40u
bogdanm 87:6213f644d804 874 #define DMA_ES_SOE_SHIFT 6
bogdanm 87:6213f644d804 875 #define DMA_ES_SAE_MASK 0x80u
bogdanm 87:6213f644d804 876 #define DMA_ES_SAE_SHIFT 7
bogdanm 87:6213f644d804 877 #define DMA_ES_ERRCHN_MASK 0xF00u
bogdanm 87:6213f644d804 878 #define DMA_ES_ERRCHN_SHIFT 8
bogdanm 87:6213f644d804 879 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
bogdanm 87:6213f644d804 880 #define DMA_ES_CPE_MASK 0x4000u
bogdanm 87:6213f644d804 881 #define DMA_ES_CPE_SHIFT 14
bogdanm 87:6213f644d804 882 #define DMA_ES_ECX_MASK 0x10000u
bogdanm 87:6213f644d804 883 #define DMA_ES_ECX_SHIFT 16
bogdanm 87:6213f644d804 884 #define DMA_ES_VLD_MASK 0x80000000u
bogdanm 87:6213f644d804 885 #define DMA_ES_VLD_SHIFT 31
bogdanm 87:6213f644d804 886 /* ERQ Bit Fields */
bogdanm 87:6213f644d804 887 #define DMA_ERQ_ERQ0_MASK 0x1u
bogdanm 87:6213f644d804 888 #define DMA_ERQ_ERQ0_SHIFT 0
bogdanm 87:6213f644d804 889 #define DMA_ERQ_ERQ1_MASK 0x2u
bogdanm 87:6213f644d804 890 #define DMA_ERQ_ERQ1_SHIFT 1
bogdanm 87:6213f644d804 891 #define DMA_ERQ_ERQ2_MASK 0x4u
bogdanm 87:6213f644d804 892 #define DMA_ERQ_ERQ2_SHIFT 2
bogdanm 87:6213f644d804 893 #define DMA_ERQ_ERQ3_MASK 0x8u
bogdanm 87:6213f644d804 894 #define DMA_ERQ_ERQ3_SHIFT 3
bogdanm 87:6213f644d804 895 /* EEI Bit Fields */
bogdanm 87:6213f644d804 896 #define DMA_EEI_EEI0_MASK 0x1u
bogdanm 87:6213f644d804 897 #define DMA_EEI_EEI0_SHIFT 0
bogdanm 87:6213f644d804 898 #define DMA_EEI_EEI1_MASK 0x2u
bogdanm 87:6213f644d804 899 #define DMA_EEI_EEI1_SHIFT 1
bogdanm 87:6213f644d804 900 #define DMA_EEI_EEI2_MASK 0x4u
bogdanm 87:6213f644d804 901 #define DMA_EEI_EEI2_SHIFT 2
bogdanm 87:6213f644d804 902 #define DMA_EEI_EEI3_MASK 0x8u
bogdanm 87:6213f644d804 903 #define DMA_EEI_EEI3_SHIFT 3
bogdanm 87:6213f644d804 904 /* CEEI Bit Fields */
bogdanm 87:6213f644d804 905 #define DMA_CEEI_CEEI_MASK 0xFu
bogdanm 87:6213f644d804 906 #define DMA_CEEI_CEEI_SHIFT 0
bogdanm 87:6213f644d804 907 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
bogdanm 87:6213f644d804 908 #define DMA_CEEI_CAEE_MASK 0x40u
bogdanm 87:6213f644d804 909 #define DMA_CEEI_CAEE_SHIFT 6
bogdanm 87:6213f644d804 910 #define DMA_CEEI_NOP_MASK 0x80u
bogdanm 87:6213f644d804 911 #define DMA_CEEI_NOP_SHIFT 7
bogdanm 87:6213f644d804 912 /* SEEI Bit Fields */
bogdanm 87:6213f644d804 913 #define DMA_SEEI_SEEI_MASK 0xFu
bogdanm 87:6213f644d804 914 #define DMA_SEEI_SEEI_SHIFT 0
bogdanm 87:6213f644d804 915 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
bogdanm 87:6213f644d804 916 #define DMA_SEEI_SAEE_MASK 0x40u
bogdanm 87:6213f644d804 917 #define DMA_SEEI_SAEE_SHIFT 6
bogdanm 87:6213f644d804 918 #define DMA_SEEI_NOP_MASK 0x80u
bogdanm 87:6213f644d804 919 #define DMA_SEEI_NOP_SHIFT 7
bogdanm 87:6213f644d804 920 /* CERQ Bit Fields */
bogdanm 87:6213f644d804 921 #define DMA_CERQ_CERQ_MASK 0xFu
bogdanm 87:6213f644d804 922 #define DMA_CERQ_CERQ_SHIFT 0
bogdanm 87:6213f644d804 923 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
bogdanm 87:6213f644d804 924 #define DMA_CERQ_CAER_MASK 0x40u
bogdanm 87:6213f644d804 925 #define DMA_CERQ_CAER_SHIFT 6
bogdanm 87:6213f644d804 926 #define DMA_CERQ_NOP_MASK 0x80u
bogdanm 87:6213f644d804 927 #define DMA_CERQ_NOP_SHIFT 7
bogdanm 87:6213f644d804 928 /* SERQ Bit Fields */
bogdanm 87:6213f644d804 929 #define DMA_SERQ_SERQ_MASK 0xFu
bogdanm 87:6213f644d804 930 #define DMA_SERQ_SERQ_SHIFT 0
bogdanm 87:6213f644d804 931 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
bogdanm 87:6213f644d804 932 #define DMA_SERQ_SAER_MASK 0x40u
bogdanm 87:6213f644d804 933 #define DMA_SERQ_SAER_SHIFT 6
bogdanm 87:6213f644d804 934 #define DMA_SERQ_NOP_MASK 0x80u
bogdanm 87:6213f644d804 935 #define DMA_SERQ_NOP_SHIFT 7
bogdanm 87:6213f644d804 936 /* CDNE Bit Fields */
bogdanm 87:6213f644d804 937 #define DMA_CDNE_CDNE_MASK 0xFu
bogdanm 87:6213f644d804 938 #define DMA_CDNE_CDNE_SHIFT 0
bogdanm 87:6213f644d804 939 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
bogdanm 87:6213f644d804 940 #define DMA_CDNE_CADN_MASK 0x40u
bogdanm 87:6213f644d804 941 #define DMA_CDNE_CADN_SHIFT 6
bogdanm 87:6213f644d804 942 #define DMA_CDNE_NOP_MASK 0x80u
bogdanm 87:6213f644d804 943 #define DMA_CDNE_NOP_SHIFT 7
bogdanm 87:6213f644d804 944 /* SSRT Bit Fields */
bogdanm 87:6213f644d804 945 #define DMA_SSRT_SSRT_MASK 0xFu
bogdanm 87:6213f644d804 946 #define DMA_SSRT_SSRT_SHIFT 0
bogdanm 87:6213f644d804 947 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
bogdanm 87:6213f644d804 948 #define DMA_SSRT_SAST_MASK 0x40u
bogdanm 87:6213f644d804 949 #define DMA_SSRT_SAST_SHIFT 6
bogdanm 87:6213f644d804 950 #define DMA_SSRT_NOP_MASK 0x80u
bogdanm 87:6213f644d804 951 #define DMA_SSRT_NOP_SHIFT 7
bogdanm 87:6213f644d804 952 /* CERR Bit Fields */
bogdanm 87:6213f644d804 953 #define DMA_CERR_CERR_MASK 0xFu
bogdanm 87:6213f644d804 954 #define DMA_CERR_CERR_SHIFT 0
bogdanm 87:6213f644d804 955 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
bogdanm 87:6213f644d804 956 #define DMA_CERR_CAEI_MASK 0x40u
bogdanm 87:6213f644d804 957 #define DMA_CERR_CAEI_SHIFT 6
bogdanm 87:6213f644d804 958 #define DMA_CERR_NOP_MASK 0x80u
bogdanm 87:6213f644d804 959 #define DMA_CERR_NOP_SHIFT 7
bogdanm 87:6213f644d804 960 /* CINT Bit Fields */
bogdanm 87:6213f644d804 961 #define DMA_CINT_CINT_MASK 0xFu
bogdanm 87:6213f644d804 962 #define DMA_CINT_CINT_SHIFT 0
bogdanm 87:6213f644d804 963 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
bogdanm 87:6213f644d804 964 #define DMA_CINT_CAIR_MASK 0x40u
bogdanm 87:6213f644d804 965 #define DMA_CINT_CAIR_SHIFT 6
bogdanm 87:6213f644d804 966 #define DMA_CINT_NOP_MASK 0x80u
bogdanm 87:6213f644d804 967 #define DMA_CINT_NOP_SHIFT 7
bogdanm 87:6213f644d804 968 /* INT Bit Fields */
bogdanm 87:6213f644d804 969 #define DMA_INT_INT0_MASK 0x1u
bogdanm 87:6213f644d804 970 #define DMA_INT_INT0_SHIFT 0
bogdanm 87:6213f644d804 971 #define DMA_INT_INT1_MASK 0x2u
bogdanm 87:6213f644d804 972 #define DMA_INT_INT1_SHIFT 1
bogdanm 87:6213f644d804 973 #define DMA_INT_INT2_MASK 0x4u
bogdanm 87:6213f644d804 974 #define DMA_INT_INT2_SHIFT 2
bogdanm 87:6213f644d804 975 #define DMA_INT_INT3_MASK 0x8u
bogdanm 87:6213f644d804 976 #define DMA_INT_INT3_SHIFT 3
bogdanm 87:6213f644d804 977 /* ERR Bit Fields */
bogdanm 87:6213f644d804 978 #define DMA_ERR_ERR0_MASK 0x1u
bogdanm 87:6213f644d804 979 #define DMA_ERR_ERR0_SHIFT 0
bogdanm 87:6213f644d804 980 #define DMA_ERR_ERR1_MASK 0x2u
bogdanm 87:6213f644d804 981 #define DMA_ERR_ERR1_SHIFT 1
bogdanm 87:6213f644d804 982 #define DMA_ERR_ERR2_MASK 0x4u
bogdanm 87:6213f644d804 983 #define DMA_ERR_ERR2_SHIFT 2
bogdanm 87:6213f644d804 984 #define DMA_ERR_ERR3_MASK 0x8u
bogdanm 87:6213f644d804 985 #define DMA_ERR_ERR3_SHIFT 3
bogdanm 87:6213f644d804 986 /* HRS Bit Fields */
bogdanm 87:6213f644d804 987 #define DMA_HRS_HRS0_MASK 0x1u
bogdanm 87:6213f644d804 988 #define DMA_HRS_HRS0_SHIFT 0
bogdanm 87:6213f644d804 989 #define DMA_HRS_HRS1_MASK 0x2u
bogdanm 87:6213f644d804 990 #define DMA_HRS_HRS1_SHIFT 1
bogdanm 87:6213f644d804 991 #define DMA_HRS_HRS2_MASK 0x4u
bogdanm 87:6213f644d804 992 #define DMA_HRS_HRS2_SHIFT 2
bogdanm 87:6213f644d804 993 #define DMA_HRS_HRS3_MASK 0x8u
bogdanm 87:6213f644d804 994 #define DMA_HRS_HRS3_SHIFT 3
bogdanm 87:6213f644d804 995 /* DCHPRI3 Bit Fields */
bogdanm 87:6213f644d804 996 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
bogdanm 87:6213f644d804 997 #define DMA_DCHPRI3_CHPRI_SHIFT 0
bogdanm 87:6213f644d804 998 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
bogdanm 87:6213f644d804 999 #define DMA_DCHPRI3_DPA_MASK 0x40u
bogdanm 87:6213f644d804 1000 #define DMA_DCHPRI3_DPA_SHIFT 6
bogdanm 87:6213f644d804 1001 #define DMA_DCHPRI3_ECP_MASK 0x80u
bogdanm 87:6213f644d804 1002 #define DMA_DCHPRI3_ECP_SHIFT 7
bogdanm 87:6213f644d804 1003 /* DCHPRI2 Bit Fields */
bogdanm 87:6213f644d804 1004 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
bogdanm 87:6213f644d804 1005 #define DMA_DCHPRI2_CHPRI_SHIFT 0
bogdanm 87:6213f644d804 1006 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
bogdanm 87:6213f644d804 1007 #define DMA_DCHPRI2_DPA_MASK 0x40u
bogdanm 87:6213f644d804 1008 #define DMA_DCHPRI2_DPA_SHIFT 6
bogdanm 87:6213f644d804 1009 #define DMA_DCHPRI2_ECP_MASK 0x80u
bogdanm 87:6213f644d804 1010 #define DMA_DCHPRI2_ECP_SHIFT 7
bogdanm 87:6213f644d804 1011 /* DCHPRI1 Bit Fields */
bogdanm 87:6213f644d804 1012 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
bogdanm 87:6213f644d804 1013 #define DMA_DCHPRI1_CHPRI_SHIFT 0
bogdanm 87:6213f644d804 1014 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
bogdanm 87:6213f644d804 1015 #define DMA_DCHPRI1_DPA_MASK 0x40u
bogdanm 87:6213f644d804 1016 #define DMA_DCHPRI1_DPA_SHIFT 6
bogdanm 87:6213f644d804 1017 #define DMA_DCHPRI1_ECP_MASK 0x80u
bogdanm 87:6213f644d804 1018 #define DMA_DCHPRI1_ECP_SHIFT 7
bogdanm 87:6213f644d804 1019 /* DCHPRI0 Bit Fields */
bogdanm 87:6213f644d804 1020 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
bogdanm 87:6213f644d804 1021 #define DMA_DCHPRI0_CHPRI_SHIFT 0
bogdanm 87:6213f644d804 1022 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
bogdanm 87:6213f644d804 1023 #define DMA_DCHPRI0_DPA_MASK 0x40u
bogdanm 87:6213f644d804 1024 #define DMA_DCHPRI0_DPA_SHIFT 6
bogdanm 87:6213f644d804 1025 #define DMA_DCHPRI0_ECP_MASK 0x80u
bogdanm 87:6213f644d804 1026 #define DMA_DCHPRI0_ECP_SHIFT 7
bogdanm 87:6213f644d804 1027 /* SADDR Bit Fields */
bogdanm 87:6213f644d804 1028 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1029 #define DMA_SADDR_SADDR_SHIFT 0
bogdanm 87:6213f644d804 1030 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
bogdanm 87:6213f644d804 1031 /* SOFF Bit Fields */
bogdanm 87:6213f644d804 1032 #define DMA_SOFF_SOFF_MASK 0xFFFFu
bogdanm 87:6213f644d804 1033 #define DMA_SOFF_SOFF_SHIFT 0
bogdanm 87:6213f644d804 1034 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
bogdanm 87:6213f644d804 1035 /* ATTR Bit Fields */
bogdanm 87:6213f644d804 1036 #define DMA_ATTR_DSIZE_MASK 0x7u
bogdanm 87:6213f644d804 1037 #define DMA_ATTR_DSIZE_SHIFT 0
bogdanm 87:6213f644d804 1038 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
bogdanm 87:6213f644d804 1039 #define DMA_ATTR_DMOD_MASK 0xF8u
bogdanm 87:6213f644d804 1040 #define DMA_ATTR_DMOD_SHIFT 3
bogdanm 87:6213f644d804 1041 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
bogdanm 87:6213f644d804 1042 #define DMA_ATTR_SSIZE_MASK 0x700u
bogdanm 87:6213f644d804 1043 #define DMA_ATTR_SSIZE_SHIFT 8
bogdanm 87:6213f644d804 1044 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
bogdanm 87:6213f644d804 1045 #define DMA_ATTR_SMOD_MASK 0xF800u
bogdanm 87:6213f644d804 1046 #define DMA_ATTR_SMOD_SHIFT 11
bogdanm 87:6213f644d804 1047 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
bogdanm 87:6213f644d804 1048 /* NBYTES_MLNO Bit Fields */
bogdanm 87:6213f644d804 1049 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1050 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
bogdanm 87:6213f644d804 1051 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
bogdanm 87:6213f644d804 1052 /* NBYTES_MLOFFNO Bit Fields */
bogdanm 87:6213f644d804 1053 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
bogdanm 87:6213f644d804 1054 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
bogdanm 87:6213f644d804 1055 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
bogdanm 87:6213f644d804 1056 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
bogdanm 87:6213f644d804 1057 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
bogdanm 87:6213f644d804 1058 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
bogdanm 87:6213f644d804 1059 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
bogdanm 87:6213f644d804 1060 /* NBYTES_MLOFFYES Bit Fields */
bogdanm 87:6213f644d804 1061 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
bogdanm 87:6213f644d804 1062 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
bogdanm 87:6213f644d804 1063 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
bogdanm 87:6213f644d804 1064 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
bogdanm 87:6213f644d804 1065 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
bogdanm 87:6213f644d804 1066 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
bogdanm 87:6213f644d804 1067 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
bogdanm 87:6213f644d804 1068 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
bogdanm 87:6213f644d804 1069 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
bogdanm 87:6213f644d804 1070 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
bogdanm 87:6213f644d804 1071 /* SLAST Bit Fields */
bogdanm 87:6213f644d804 1072 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1073 #define DMA_SLAST_SLAST_SHIFT 0
bogdanm 87:6213f644d804 1074 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
bogdanm 87:6213f644d804 1075 /* DADDR Bit Fields */
bogdanm 87:6213f644d804 1076 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1077 #define DMA_DADDR_DADDR_SHIFT 0
bogdanm 87:6213f644d804 1078 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
bogdanm 87:6213f644d804 1079 /* DOFF Bit Fields */
bogdanm 87:6213f644d804 1080 #define DMA_DOFF_DOFF_MASK 0xFFFFu
bogdanm 87:6213f644d804 1081 #define DMA_DOFF_DOFF_SHIFT 0
bogdanm 87:6213f644d804 1082 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
bogdanm 87:6213f644d804 1083 /* CITER_ELINKNO Bit Fields */
bogdanm 87:6213f644d804 1084 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
bogdanm 87:6213f644d804 1085 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
bogdanm 87:6213f644d804 1086 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
bogdanm 87:6213f644d804 1087 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
bogdanm 87:6213f644d804 1088 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
bogdanm 87:6213f644d804 1089 /* CITER_ELINKYES Bit Fields */
bogdanm 87:6213f644d804 1090 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
bogdanm 87:6213f644d804 1091 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
bogdanm 87:6213f644d804 1092 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
bogdanm 87:6213f644d804 1093 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
bogdanm 87:6213f644d804 1094 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
bogdanm 87:6213f644d804 1095 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
bogdanm 87:6213f644d804 1096 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
bogdanm 87:6213f644d804 1097 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
bogdanm 87:6213f644d804 1098 /* DLAST_SGA Bit Fields */
bogdanm 87:6213f644d804 1099 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1100 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
bogdanm 87:6213f644d804 1101 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
bogdanm 87:6213f644d804 1102 /* CSR Bit Fields */
bogdanm 87:6213f644d804 1103 #define DMA_CSR_START_MASK 0x1u
bogdanm 87:6213f644d804 1104 #define DMA_CSR_START_SHIFT 0
bogdanm 87:6213f644d804 1105 #define DMA_CSR_INTMAJOR_MASK 0x2u
bogdanm 87:6213f644d804 1106 #define DMA_CSR_INTMAJOR_SHIFT 1
bogdanm 87:6213f644d804 1107 #define DMA_CSR_INTHALF_MASK 0x4u
bogdanm 87:6213f644d804 1108 #define DMA_CSR_INTHALF_SHIFT 2
bogdanm 87:6213f644d804 1109 #define DMA_CSR_DREQ_MASK 0x8u
bogdanm 87:6213f644d804 1110 #define DMA_CSR_DREQ_SHIFT 3
bogdanm 87:6213f644d804 1111 #define DMA_CSR_ESG_MASK 0x10u
bogdanm 87:6213f644d804 1112 #define DMA_CSR_ESG_SHIFT 4
bogdanm 87:6213f644d804 1113 #define DMA_CSR_MAJORELINK_MASK 0x20u
bogdanm 87:6213f644d804 1114 #define DMA_CSR_MAJORELINK_SHIFT 5
bogdanm 87:6213f644d804 1115 #define DMA_CSR_ACTIVE_MASK 0x40u
bogdanm 87:6213f644d804 1116 #define DMA_CSR_ACTIVE_SHIFT 6
bogdanm 87:6213f644d804 1117 #define DMA_CSR_DONE_MASK 0x80u
bogdanm 87:6213f644d804 1118 #define DMA_CSR_DONE_SHIFT 7
bogdanm 87:6213f644d804 1119 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
bogdanm 87:6213f644d804 1120 #define DMA_CSR_MAJORLINKCH_SHIFT 8
bogdanm 87:6213f644d804 1121 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
bogdanm 87:6213f644d804 1122 #define DMA_CSR_BWC_MASK 0xC000u
bogdanm 87:6213f644d804 1123 #define DMA_CSR_BWC_SHIFT 14
bogdanm 87:6213f644d804 1124 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
bogdanm 87:6213f644d804 1125 /* BITER_ELINKNO Bit Fields */
bogdanm 87:6213f644d804 1126 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
bogdanm 87:6213f644d804 1127 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
bogdanm 87:6213f644d804 1128 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
bogdanm 87:6213f644d804 1129 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
bogdanm 87:6213f644d804 1130 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
bogdanm 87:6213f644d804 1131 /* BITER_ELINKYES Bit Fields */
bogdanm 87:6213f644d804 1132 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
bogdanm 87:6213f644d804 1133 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
bogdanm 87:6213f644d804 1134 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
bogdanm 87:6213f644d804 1135 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
bogdanm 87:6213f644d804 1136 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
bogdanm 87:6213f644d804 1137 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
bogdanm 87:6213f644d804 1138 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
bogdanm 87:6213f644d804 1139 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
bogdanm 87:6213f644d804 1140
bogdanm 87:6213f644d804 1141 /**
bogdanm 87:6213f644d804 1142 * @}
bogdanm 87:6213f644d804 1143 */ /* end of group DMA_Register_Masks */
bogdanm 87:6213f644d804 1144
bogdanm 87:6213f644d804 1145
bogdanm 87:6213f644d804 1146 /* DMA - Peripheral instance base addresses */
bogdanm 87:6213f644d804 1147 /** Peripheral DMA base address */
bogdanm 87:6213f644d804 1148 #define DMA_BASE (0x40008000u)
bogdanm 87:6213f644d804 1149 /** Peripheral DMA base pointer */
bogdanm 87:6213f644d804 1150 #define DMA0 ((DMA_Type *)DMA_BASE)
bogdanm 87:6213f644d804 1151
bogdanm 87:6213f644d804 1152 /**
bogdanm 87:6213f644d804 1153 * @}
bogdanm 87:6213f644d804 1154 */ /* end of group DMA_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 1155
bogdanm 87:6213f644d804 1156
bogdanm 87:6213f644d804 1157 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1158 -- DMAMUX Peripheral Access Layer
bogdanm 87:6213f644d804 1159 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1160
bogdanm 87:6213f644d804 1161 /**
bogdanm 87:6213f644d804 1162 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
bogdanm 87:6213f644d804 1163 * @{
bogdanm 87:6213f644d804 1164 */
bogdanm 87:6213f644d804 1165
bogdanm 87:6213f644d804 1166 /** DMAMUX - Register Layout Typedef */
bogdanm 87:6213f644d804 1167 typedef struct {
bogdanm 87:6213f644d804 1168 __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
bogdanm 87:6213f644d804 1169 } DMAMUX_Type;
bogdanm 87:6213f644d804 1170
bogdanm 87:6213f644d804 1171 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1172 -- DMAMUX Register Masks
bogdanm 87:6213f644d804 1173 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1174
bogdanm 87:6213f644d804 1175 /**
bogdanm 87:6213f644d804 1176 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
bogdanm 87:6213f644d804 1177 * @{
bogdanm 87:6213f644d804 1178 */
bogdanm 87:6213f644d804 1179
bogdanm 87:6213f644d804 1180 /* CHCFG Bit Fields */
bogdanm 87:6213f644d804 1181 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
bogdanm 87:6213f644d804 1182 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
bogdanm 87:6213f644d804 1183 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
bogdanm 87:6213f644d804 1184 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
bogdanm 87:6213f644d804 1185 #define DMAMUX_CHCFG_TRIG_SHIFT 6
bogdanm 87:6213f644d804 1186 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
bogdanm 87:6213f644d804 1187 #define DMAMUX_CHCFG_ENBL_SHIFT 7
bogdanm 87:6213f644d804 1188
bogdanm 87:6213f644d804 1189 /**
bogdanm 87:6213f644d804 1190 * @}
bogdanm 87:6213f644d804 1191 */ /* end of group DMAMUX_Register_Masks */
bogdanm 87:6213f644d804 1192
bogdanm 87:6213f644d804 1193
bogdanm 87:6213f644d804 1194 /* DMAMUX - Peripheral instance base addresses */
bogdanm 87:6213f644d804 1195 /** Peripheral DMAMUX base address */
bogdanm 87:6213f644d804 1196 #define DMAMUX_BASE (0x40021000u)
bogdanm 87:6213f644d804 1197 /** Peripheral DMAMUX base pointer */
bogdanm 87:6213f644d804 1198 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
bogdanm 87:6213f644d804 1199
bogdanm 87:6213f644d804 1200 /**
bogdanm 87:6213f644d804 1201 * @}
bogdanm 87:6213f644d804 1202 */ /* end of group DMAMUX_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 1203
bogdanm 87:6213f644d804 1204
bogdanm 87:6213f644d804 1205 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1206 -- EWM Peripheral Access Layer
bogdanm 87:6213f644d804 1207 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1208
bogdanm 87:6213f644d804 1209 /**
bogdanm 87:6213f644d804 1210 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
bogdanm 87:6213f644d804 1211 * @{
bogdanm 87:6213f644d804 1212 */
bogdanm 87:6213f644d804 1213
bogdanm 87:6213f644d804 1214 /** EWM - Register Layout Typedef */
bogdanm 87:6213f644d804 1215 typedef struct {
bogdanm 87:6213f644d804 1216 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
bogdanm 87:6213f644d804 1217 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
bogdanm 87:6213f644d804 1218 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
bogdanm 87:6213f644d804 1219 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
bogdanm 87:6213f644d804 1220 } EWM_Type;
bogdanm 87:6213f644d804 1221
bogdanm 87:6213f644d804 1222 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1223 -- EWM Register Masks
bogdanm 87:6213f644d804 1224 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1225
bogdanm 87:6213f644d804 1226 /**
bogdanm 87:6213f644d804 1227 * @addtogroup EWM_Register_Masks EWM Register Masks
bogdanm 87:6213f644d804 1228 * @{
bogdanm 87:6213f644d804 1229 */
bogdanm 87:6213f644d804 1230
bogdanm 87:6213f644d804 1231 /* CTRL Bit Fields */
bogdanm 87:6213f644d804 1232 #define EWM_CTRL_EWMEN_MASK 0x1u
bogdanm 87:6213f644d804 1233 #define EWM_CTRL_EWMEN_SHIFT 0
bogdanm 87:6213f644d804 1234 #define EWM_CTRL_ASSIN_MASK 0x2u
bogdanm 87:6213f644d804 1235 #define EWM_CTRL_ASSIN_SHIFT 1
bogdanm 87:6213f644d804 1236 #define EWM_CTRL_INEN_MASK 0x4u
bogdanm 87:6213f644d804 1237 #define EWM_CTRL_INEN_SHIFT 2
bogdanm 87:6213f644d804 1238 #define EWM_CTRL_INTEN_MASK 0x8u
bogdanm 87:6213f644d804 1239 #define EWM_CTRL_INTEN_SHIFT 3
bogdanm 87:6213f644d804 1240 /* SERV Bit Fields */
bogdanm 87:6213f644d804 1241 #define EWM_SERV_SERVICE_MASK 0xFFu
bogdanm 87:6213f644d804 1242 #define EWM_SERV_SERVICE_SHIFT 0
bogdanm 87:6213f644d804 1243 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
bogdanm 87:6213f644d804 1244 /* CMPL Bit Fields */
bogdanm 87:6213f644d804 1245 #define EWM_CMPL_COMPAREL_MASK 0xFFu
bogdanm 87:6213f644d804 1246 #define EWM_CMPL_COMPAREL_SHIFT 0
bogdanm 87:6213f644d804 1247 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
bogdanm 87:6213f644d804 1248 /* CMPH Bit Fields */
bogdanm 87:6213f644d804 1249 #define EWM_CMPH_COMPAREH_MASK 0xFFu
bogdanm 87:6213f644d804 1250 #define EWM_CMPH_COMPAREH_SHIFT 0
bogdanm 87:6213f644d804 1251 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
bogdanm 87:6213f644d804 1252
bogdanm 87:6213f644d804 1253 /**
bogdanm 87:6213f644d804 1254 * @}
bogdanm 87:6213f644d804 1255 */ /* end of group EWM_Register_Masks */
bogdanm 87:6213f644d804 1256
bogdanm 87:6213f644d804 1257
bogdanm 87:6213f644d804 1258 /* EWM - Peripheral instance base addresses */
bogdanm 87:6213f644d804 1259 /** Peripheral EWM base address */
bogdanm 87:6213f644d804 1260 #define EWM_BASE (0x40061000u)
bogdanm 87:6213f644d804 1261 /** Peripheral EWM base pointer */
bogdanm 87:6213f644d804 1262 #define EWM ((EWM_Type *)EWM_BASE)
bogdanm 87:6213f644d804 1263
bogdanm 87:6213f644d804 1264 /**
bogdanm 87:6213f644d804 1265 * @}
bogdanm 87:6213f644d804 1266 */ /* end of group EWM_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 1267
bogdanm 87:6213f644d804 1268
bogdanm 87:6213f644d804 1269 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1270 -- FMC Peripheral Access Layer
bogdanm 87:6213f644d804 1271 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1272
bogdanm 87:6213f644d804 1273 /**
bogdanm 87:6213f644d804 1274 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
bogdanm 87:6213f644d804 1275 * @{
bogdanm 87:6213f644d804 1276 */
bogdanm 87:6213f644d804 1277
bogdanm 87:6213f644d804 1278 /** FMC - Register Layout Typedef */
bogdanm 87:6213f644d804 1279 typedef struct {
bogdanm 87:6213f644d804 1280 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
bogdanm 87:6213f644d804 1281 __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
bogdanm 87:6213f644d804 1282 uint8_t RESERVED_0[248];
bogdanm 87:6213f644d804 1283 struct { /* offset: 0x100, array step: 0x20 */
bogdanm 87:6213f644d804 1284 __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
bogdanm 87:6213f644d804 1285 uint8_t RESERVED_0[24];
bogdanm 87:6213f644d804 1286 } TAG_WAY[4];
bogdanm 87:6213f644d804 1287 uint8_t RESERVED_1[132];
bogdanm 87:6213f644d804 1288 struct { /* offset: 0x204, array step: 0x8 */
bogdanm 87:6213f644d804 1289 __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
bogdanm 87:6213f644d804 1290 uint8_t RESERVED_0[4];
bogdanm 87:6213f644d804 1291 } DATAW0S[2];
bogdanm 87:6213f644d804 1292 uint8_t RESERVED_2[48];
bogdanm 87:6213f644d804 1293 struct { /* offset: 0x244, array step: 0x8 */
bogdanm 87:6213f644d804 1294 __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
bogdanm 87:6213f644d804 1295 uint8_t RESERVED_0[4];
bogdanm 87:6213f644d804 1296 } DATAW1S[2];
bogdanm 87:6213f644d804 1297 uint8_t RESERVED_3[48];
bogdanm 87:6213f644d804 1298 struct { /* offset: 0x284, array step: 0x8 */
bogdanm 87:6213f644d804 1299 __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
bogdanm 87:6213f644d804 1300 uint8_t RESERVED_0[4];
bogdanm 87:6213f644d804 1301 } DATAW2S[2];
bogdanm 87:6213f644d804 1302 uint8_t RESERVED_4[48];
bogdanm 87:6213f644d804 1303 struct { /* offset: 0x2C4, array step: 0x8 */
bogdanm 87:6213f644d804 1304 __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
bogdanm 87:6213f644d804 1305 uint8_t RESERVED_0[4];
bogdanm 87:6213f644d804 1306 } DATAW3S[2];
bogdanm 87:6213f644d804 1307 } FMC_Type;
bogdanm 87:6213f644d804 1308
bogdanm 87:6213f644d804 1309 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1310 -- FMC Register Masks
bogdanm 87:6213f644d804 1311 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1312
bogdanm 87:6213f644d804 1313 /**
bogdanm 87:6213f644d804 1314 * @addtogroup FMC_Register_Masks FMC Register Masks
bogdanm 87:6213f644d804 1315 * @{
bogdanm 87:6213f644d804 1316 */
bogdanm 87:6213f644d804 1317
bogdanm 87:6213f644d804 1318 /* PFAPR Bit Fields */
bogdanm 87:6213f644d804 1319 #define FMC_PFAPR_M0AP_MASK 0x3u
bogdanm 87:6213f644d804 1320 #define FMC_PFAPR_M0AP_SHIFT 0
bogdanm 87:6213f644d804 1321 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
bogdanm 87:6213f644d804 1322 #define FMC_PFAPR_M1AP_MASK 0xCu
bogdanm 87:6213f644d804 1323 #define FMC_PFAPR_M1AP_SHIFT 2
bogdanm 87:6213f644d804 1324 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
bogdanm 87:6213f644d804 1325 #define FMC_PFAPR_M2AP_MASK 0x30u
bogdanm 87:6213f644d804 1326 #define FMC_PFAPR_M2AP_SHIFT 4
bogdanm 87:6213f644d804 1327 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
bogdanm 87:6213f644d804 1328 #define FMC_PFAPR_M3AP_MASK 0xC0u
bogdanm 87:6213f644d804 1329 #define FMC_PFAPR_M3AP_SHIFT 6
bogdanm 87:6213f644d804 1330 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
bogdanm 87:6213f644d804 1331 #define FMC_PFAPR_M0PFD_MASK 0x10000u
bogdanm 87:6213f644d804 1332 #define FMC_PFAPR_M0PFD_SHIFT 16
bogdanm 87:6213f644d804 1333 #define FMC_PFAPR_M1PFD_MASK 0x20000u
bogdanm 87:6213f644d804 1334 #define FMC_PFAPR_M1PFD_SHIFT 17
bogdanm 87:6213f644d804 1335 #define FMC_PFAPR_M2PFD_MASK 0x40000u
bogdanm 87:6213f644d804 1336 #define FMC_PFAPR_M2PFD_SHIFT 18
bogdanm 87:6213f644d804 1337 #define FMC_PFAPR_M3PFD_MASK 0x80000u
bogdanm 87:6213f644d804 1338 #define FMC_PFAPR_M3PFD_SHIFT 19
bogdanm 87:6213f644d804 1339 /* PFB0CR Bit Fields */
bogdanm 87:6213f644d804 1340 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
bogdanm 87:6213f644d804 1341 #define FMC_PFB0CR_B0SEBE_SHIFT 0
bogdanm 87:6213f644d804 1342 #define FMC_PFB0CR_B0IPE_MASK 0x2u
bogdanm 87:6213f644d804 1343 #define FMC_PFB0CR_B0IPE_SHIFT 1
bogdanm 87:6213f644d804 1344 #define FMC_PFB0CR_B0DPE_MASK 0x4u
bogdanm 87:6213f644d804 1345 #define FMC_PFB0CR_B0DPE_SHIFT 2
bogdanm 87:6213f644d804 1346 #define FMC_PFB0CR_B0ICE_MASK 0x8u
bogdanm 87:6213f644d804 1347 #define FMC_PFB0CR_B0ICE_SHIFT 3
bogdanm 87:6213f644d804 1348 #define FMC_PFB0CR_B0DCE_MASK 0x10u
bogdanm 87:6213f644d804 1349 #define FMC_PFB0CR_B0DCE_SHIFT 4
bogdanm 87:6213f644d804 1350 #define FMC_PFB0CR_CRC_MASK 0xE0u
bogdanm 87:6213f644d804 1351 #define FMC_PFB0CR_CRC_SHIFT 5
bogdanm 87:6213f644d804 1352 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
bogdanm 87:6213f644d804 1353 #define FMC_PFB0CR_B0MW_MASK 0x60000u
bogdanm 87:6213f644d804 1354 #define FMC_PFB0CR_B0MW_SHIFT 17
bogdanm 87:6213f644d804 1355 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
bogdanm 87:6213f644d804 1356 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
bogdanm 87:6213f644d804 1357 #define FMC_PFB0CR_S_B_INV_SHIFT 19
bogdanm 87:6213f644d804 1358 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
bogdanm 87:6213f644d804 1359 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
bogdanm 87:6213f644d804 1360 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
bogdanm 87:6213f644d804 1361 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
bogdanm 87:6213f644d804 1362 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
bogdanm 87:6213f644d804 1363 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
bogdanm 87:6213f644d804 1364 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
bogdanm 87:6213f644d804 1365 #define FMC_PFB0CR_B0RWSC_SHIFT 28
bogdanm 87:6213f644d804 1366 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
bogdanm 87:6213f644d804 1367 /* TAGVD Bit Fields */
bogdanm 87:6213f644d804 1368 #define FMC_TAGVD_valid_MASK 0x1u
bogdanm 87:6213f644d804 1369 #define FMC_TAGVD_valid_SHIFT 0
bogdanm 87:6213f644d804 1370 #define FMC_TAGVD_tag_MASK 0x7FFC0u
bogdanm 87:6213f644d804 1371 #define FMC_TAGVD_tag_SHIFT 6
bogdanm 87:6213f644d804 1372 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
bogdanm 87:6213f644d804 1373 /* DATAW0S Bit Fields */
bogdanm 87:6213f644d804 1374 #define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1375 #define FMC_DATAW0S_data_SHIFT 0
bogdanm 87:6213f644d804 1376 #define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
bogdanm 87:6213f644d804 1377 /* DATAW1S Bit Fields */
bogdanm 87:6213f644d804 1378 #define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1379 #define FMC_DATAW1S_data_SHIFT 0
bogdanm 87:6213f644d804 1380 #define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
bogdanm 87:6213f644d804 1381 /* DATAW2S Bit Fields */
bogdanm 87:6213f644d804 1382 #define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1383 #define FMC_DATAW2S_data_SHIFT 0
bogdanm 87:6213f644d804 1384 #define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
bogdanm 87:6213f644d804 1385 /* DATAW3S Bit Fields */
bogdanm 87:6213f644d804 1386 #define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 1387 #define FMC_DATAW3S_data_SHIFT 0
bogdanm 87:6213f644d804 1388 #define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
bogdanm 87:6213f644d804 1389
bogdanm 87:6213f644d804 1390 /**
bogdanm 87:6213f644d804 1391 * @}
bogdanm 87:6213f644d804 1392 */ /* end of group FMC_Register_Masks */
bogdanm 87:6213f644d804 1393
bogdanm 87:6213f644d804 1394
bogdanm 87:6213f644d804 1395 /* FMC - Peripheral instance base addresses */
bogdanm 87:6213f644d804 1396 /** Peripheral FMC base address */
bogdanm 87:6213f644d804 1397 #define FMC_BASE (0x4001F000u)
bogdanm 87:6213f644d804 1398 /** Peripheral FMC base pointer */
bogdanm 87:6213f644d804 1399 #define FMC ((FMC_Type *)FMC_BASE)
bogdanm 87:6213f644d804 1400
bogdanm 87:6213f644d804 1401 /**
bogdanm 87:6213f644d804 1402 * @}
bogdanm 87:6213f644d804 1403 */ /* end of group FMC_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 1404
bogdanm 87:6213f644d804 1405
bogdanm 87:6213f644d804 1406 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1407 -- FTFL Peripheral Access Layer
bogdanm 87:6213f644d804 1408 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1409
bogdanm 87:6213f644d804 1410 /**
bogdanm 87:6213f644d804 1411 * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
bogdanm 87:6213f644d804 1412 * @{
bogdanm 87:6213f644d804 1413 */
bogdanm 87:6213f644d804 1414
bogdanm 87:6213f644d804 1415 /** FTFL - Register Layout Typedef */
bogdanm 87:6213f644d804 1416 typedef struct {
bogdanm 87:6213f644d804 1417 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
bogdanm 87:6213f644d804 1418 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
bogdanm 87:6213f644d804 1419 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
bogdanm 87:6213f644d804 1420 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
bogdanm 87:6213f644d804 1421 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
bogdanm 87:6213f644d804 1422 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
bogdanm 87:6213f644d804 1423 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
bogdanm 87:6213f644d804 1424 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
bogdanm 87:6213f644d804 1425 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
bogdanm 87:6213f644d804 1426 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
bogdanm 87:6213f644d804 1427 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
bogdanm 87:6213f644d804 1428 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
bogdanm 87:6213f644d804 1429 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
bogdanm 87:6213f644d804 1430 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
bogdanm 87:6213f644d804 1431 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
bogdanm 87:6213f644d804 1432 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
bogdanm 87:6213f644d804 1433 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
bogdanm 87:6213f644d804 1434 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
bogdanm 87:6213f644d804 1435 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
bogdanm 87:6213f644d804 1436 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
bogdanm 87:6213f644d804 1437 uint8_t RESERVED_0[2];
bogdanm 87:6213f644d804 1438 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
bogdanm 87:6213f644d804 1439 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
bogdanm 87:6213f644d804 1440 } FTFL_Type;
bogdanm 87:6213f644d804 1441
bogdanm 87:6213f644d804 1442 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1443 -- FTFL Register Masks
bogdanm 87:6213f644d804 1444 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1445
bogdanm 87:6213f644d804 1446 /**
bogdanm 87:6213f644d804 1447 * @addtogroup FTFL_Register_Masks FTFL Register Masks
bogdanm 87:6213f644d804 1448 * @{
bogdanm 87:6213f644d804 1449 */
bogdanm 87:6213f644d804 1450
bogdanm 87:6213f644d804 1451 /* FSTAT Bit Fields */
bogdanm 87:6213f644d804 1452 #define FTFL_FSTAT_MGSTAT0_MASK 0x1u
bogdanm 87:6213f644d804 1453 #define FTFL_FSTAT_MGSTAT0_SHIFT 0
bogdanm 87:6213f644d804 1454 #define FTFL_FSTAT_FPVIOL_MASK 0x10u
bogdanm 87:6213f644d804 1455 #define FTFL_FSTAT_FPVIOL_SHIFT 4
bogdanm 87:6213f644d804 1456 #define FTFL_FSTAT_ACCERR_MASK 0x20u
bogdanm 87:6213f644d804 1457 #define FTFL_FSTAT_ACCERR_SHIFT 5
bogdanm 87:6213f644d804 1458 #define FTFL_FSTAT_RDCOLERR_MASK 0x40u
bogdanm 87:6213f644d804 1459 #define FTFL_FSTAT_RDCOLERR_SHIFT 6
bogdanm 87:6213f644d804 1460 #define FTFL_FSTAT_CCIF_MASK 0x80u
bogdanm 87:6213f644d804 1461 #define FTFL_FSTAT_CCIF_SHIFT 7
bogdanm 87:6213f644d804 1462 /* FCNFG Bit Fields */
bogdanm 87:6213f644d804 1463 #define FTFL_FCNFG_EEERDY_MASK 0x1u
bogdanm 87:6213f644d804 1464 #define FTFL_FCNFG_EEERDY_SHIFT 0
bogdanm 87:6213f644d804 1465 #define FTFL_FCNFG_RAMRDY_MASK 0x2u
bogdanm 87:6213f644d804 1466 #define FTFL_FCNFG_RAMRDY_SHIFT 1
bogdanm 87:6213f644d804 1467 #define FTFL_FCNFG_PFLSH_MASK 0x4u
bogdanm 87:6213f644d804 1468 #define FTFL_FCNFG_PFLSH_SHIFT 2
bogdanm 87:6213f644d804 1469 #define FTFL_FCNFG_ERSSUSP_MASK 0x10u
bogdanm 87:6213f644d804 1470 #define FTFL_FCNFG_ERSSUSP_SHIFT 4
bogdanm 87:6213f644d804 1471 #define FTFL_FCNFG_ERSAREQ_MASK 0x20u
bogdanm 87:6213f644d804 1472 #define FTFL_FCNFG_ERSAREQ_SHIFT 5
bogdanm 87:6213f644d804 1473 #define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
bogdanm 87:6213f644d804 1474 #define FTFL_FCNFG_RDCOLLIE_SHIFT 6
bogdanm 87:6213f644d804 1475 #define FTFL_FCNFG_CCIE_MASK 0x80u
bogdanm 87:6213f644d804 1476 #define FTFL_FCNFG_CCIE_SHIFT 7
bogdanm 87:6213f644d804 1477 /* FSEC Bit Fields */
bogdanm 87:6213f644d804 1478 #define FTFL_FSEC_SEC_MASK 0x3u
bogdanm 87:6213f644d804 1479 #define FTFL_FSEC_SEC_SHIFT 0
bogdanm 87:6213f644d804 1480 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
bogdanm 87:6213f644d804 1481 #define FTFL_FSEC_FSLACC_MASK 0xCu
bogdanm 87:6213f644d804 1482 #define FTFL_FSEC_FSLACC_SHIFT 2
bogdanm 87:6213f644d804 1483 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
bogdanm 87:6213f644d804 1484 #define FTFL_FSEC_MEEN_MASK 0x30u
bogdanm 87:6213f644d804 1485 #define FTFL_FSEC_MEEN_SHIFT 4
bogdanm 87:6213f644d804 1486 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
bogdanm 87:6213f644d804 1487 #define FTFL_FSEC_KEYEN_MASK 0xC0u
bogdanm 87:6213f644d804 1488 #define FTFL_FSEC_KEYEN_SHIFT 6
bogdanm 87:6213f644d804 1489 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
bogdanm 87:6213f644d804 1490 /* FOPT Bit Fields */
bogdanm 87:6213f644d804 1491 #define FTFL_FOPT_OPT_MASK 0xFFu
bogdanm 87:6213f644d804 1492 #define FTFL_FOPT_OPT_SHIFT 0
bogdanm 87:6213f644d804 1493 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
bogdanm 87:6213f644d804 1494 /* FCCOB3 Bit Fields */
bogdanm 87:6213f644d804 1495 #define FTFL_FCCOB3_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1496 #define FTFL_FCCOB3_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1497 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
bogdanm 87:6213f644d804 1498 /* FCCOB2 Bit Fields */
bogdanm 87:6213f644d804 1499 #define FTFL_FCCOB2_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1500 #define FTFL_FCCOB2_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1501 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
bogdanm 87:6213f644d804 1502 /* FCCOB1 Bit Fields */
bogdanm 87:6213f644d804 1503 #define FTFL_FCCOB1_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1504 #define FTFL_FCCOB1_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1505 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
bogdanm 87:6213f644d804 1506 /* FCCOB0 Bit Fields */
bogdanm 87:6213f644d804 1507 #define FTFL_FCCOB0_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1508 #define FTFL_FCCOB0_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1509 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
bogdanm 87:6213f644d804 1510 /* FCCOB7 Bit Fields */
bogdanm 87:6213f644d804 1511 #define FTFL_FCCOB7_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1512 #define FTFL_FCCOB7_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1513 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
bogdanm 87:6213f644d804 1514 /* FCCOB6 Bit Fields */
bogdanm 87:6213f644d804 1515 #define FTFL_FCCOB6_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1516 #define FTFL_FCCOB6_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1517 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
bogdanm 87:6213f644d804 1518 /* FCCOB5 Bit Fields */
bogdanm 87:6213f644d804 1519 #define FTFL_FCCOB5_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1520 #define FTFL_FCCOB5_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1521 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
bogdanm 87:6213f644d804 1522 /* FCCOB4 Bit Fields */
bogdanm 87:6213f644d804 1523 #define FTFL_FCCOB4_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1524 #define FTFL_FCCOB4_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1525 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
bogdanm 87:6213f644d804 1526 /* FCCOBB Bit Fields */
bogdanm 87:6213f644d804 1527 #define FTFL_FCCOBB_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1528 #define FTFL_FCCOBB_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1529 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
bogdanm 87:6213f644d804 1530 /* FCCOBA Bit Fields */
bogdanm 87:6213f644d804 1531 #define FTFL_FCCOBA_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1532 #define FTFL_FCCOBA_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1533 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
bogdanm 87:6213f644d804 1534 /* FCCOB9 Bit Fields */
bogdanm 87:6213f644d804 1535 #define FTFL_FCCOB9_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1536 #define FTFL_FCCOB9_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1537 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
bogdanm 87:6213f644d804 1538 /* FCCOB8 Bit Fields */
bogdanm 87:6213f644d804 1539 #define FTFL_FCCOB8_CCOBn_MASK 0xFFu
bogdanm 87:6213f644d804 1540 #define FTFL_FCCOB8_CCOBn_SHIFT 0
bogdanm 87:6213f644d804 1541 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
bogdanm 87:6213f644d804 1542 /* FPROT3 Bit Fields */
bogdanm 87:6213f644d804 1543 #define FTFL_FPROT3_PROT_MASK 0xFFu
bogdanm 87:6213f644d804 1544 #define FTFL_FPROT3_PROT_SHIFT 0
bogdanm 87:6213f644d804 1545 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
bogdanm 87:6213f644d804 1546 /* FPROT2 Bit Fields */
bogdanm 87:6213f644d804 1547 #define FTFL_FPROT2_PROT_MASK 0xFFu
bogdanm 87:6213f644d804 1548 #define FTFL_FPROT2_PROT_SHIFT 0
bogdanm 87:6213f644d804 1549 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
bogdanm 87:6213f644d804 1550 /* FPROT1 Bit Fields */
bogdanm 87:6213f644d804 1551 #define FTFL_FPROT1_PROT_MASK 0xFFu
bogdanm 87:6213f644d804 1552 #define FTFL_FPROT1_PROT_SHIFT 0
bogdanm 87:6213f644d804 1553 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
bogdanm 87:6213f644d804 1554 /* FPROT0 Bit Fields */
bogdanm 87:6213f644d804 1555 #define FTFL_FPROT0_PROT_MASK 0xFFu
bogdanm 87:6213f644d804 1556 #define FTFL_FPROT0_PROT_SHIFT 0
bogdanm 87:6213f644d804 1557 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
bogdanm 87:6213f644d804 1558 /* FEPROT Bit Fields */
bogdanm 87:6213f644d804 1559 #define FTFL_FEPROT_EPROT_MASK 0xFFu
bogdanm 87:6213f644d804 1560 #define FTFL_FEPROT_EPROT_SHIFT 0
bogdanm 87:6213f644d804 1561 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
bogdanm 87:6213f644d804 1562 /* FDPROT Bit Fields */
bogdanm 87:6213f644d804 1563 #define FTFL_FDPROT_DPROT_MASK 0xFFu
bogdanm 87:6213f644d804 1564 #define FTFL_FDPROT_DPROT_SHIFT 0
bogdanm 87:6213f644d804 1565 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
bogdanm 87:6213f644d804 1566
bogdanm 87:6213f644d804 1567 /**
bogdanm 87:6213f644d804 1568 * @}
bogdanm 87:6213f644d804 1569 */ /* end of group FTFL_Register_Masks */
bogdanm 87:6213f644d804 1570
bogdanm 87:6213f644d804 1571
bogdanm 87:6213f644d804 1572 /* FTFL - Peripheral instance base addresses */
bogdanm 87:6213f644d804 1573 /** Peripheral FTFL base address */
bogdanm 87:6213f644d804 1574 #define FTFL_BASE (0x40020000u)
bogdanm 87:6213f644d804 1575 /** Peripheral FTFL base pointer */
bogdanm 87:6213f644d804 1576 #define FTFL ((FTFL_Type *)FTFL_BASE)
bogdanm 87:6213f644d804 1577
bogdanm 87:6213f644d804 1578 /**
bogdanm 87:6213f644d804 1579 * @}
bogdanm 87:6213f644d804 1580 */ /* end of group FTFL_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 1581
bogdanm 87:6213f644d804 1582
bogdanm 87:6213f644d804 1583 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1584 -- FTM Peripheral Access Layer
bogdanm 87:6213f644d804 1585 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1586
bogdanm 87:6213f644d804 1587 /**
bogdanm 87:6213f644d804 1588 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
bogdanm 87:6213f644d804 1589 * @{
bogdanm 87:6213f644d804 1590 */
bogdanm 87:6213f644d804 1591
bogdanm 87:6213f644d804 1592 /** FTM - Register Layout Typedef */
bogdanm 87:6213f644d804 1593 typedef struct {
bogdanm 87:6213f644d804 1594 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
bogdanm 87:6213f644d804 1595 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
bogdanm 87:6213f644d804 1596 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
bogdanm 87:6213f644d804 1597 struct { /* offset: 0xC, array step: 0x8 */
bogdanm 87:6213f644d804 1598 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
bogdanm 87:6213f644d804 1599 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
bogdanm 87:6213f644d804 1600 } CONTROLS[8];
bogdanm 87:6213f644d804 1601 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
bogdanm 87:6213f644d804 1602 __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
bogdanm 87:6213f644d804 1603 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
bogdanm 87:6213f644d804 1604 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
bogdanm 87:6213f644d804 1605 __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
bogdanm 87:6213f644d804 1606 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
bogdanm 87:6213f644d804 1607 __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
bogdanm 87:6213f644d804 1608 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
bogdanm 87:6213f644d804 1609 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
bogdanm 87:6213f644d804 1610 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
bogdanm 87:6213f644d804 1611 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
bogdanm 87:6213f644d804 1612 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
bogdanm 87:6213f644d804 1613 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
bogdanm 87:6213f644d804 1614 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
bogdanm 87:6213f644d804 1615 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
bogdanm 87:6213f644d804 1616 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
bogdanm 87:6213f644d804 1617 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
bogdanm 87:6213f644d804 1618 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
bogdanm 87:6213f644d804 1619 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
bogdanm 87:6213f644d804 1620 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
bogdanm 87:6213f644d804 1621 } FTM_Type;
bogdanm 87:6213f644d804 1622
bogdanm 87:6213f644d804 1623 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 1624 -- FTM Register Masks
bogdanm 87:6213f644d804 1625 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 1626
bogdanm 87:6213f644d804 1627 /**
bogdanm 87:6213f644d804 1628 * @addtogroup FTM_Register_Masks FTM Register Masks
bogdanm 87:6213f644d804 1629 * @{
bogdanm 87:6213f644d804 1630 */
bogdanm 87:6213f644d804 1631
bogdanm 87:6213f644d804 1632 /* SC Bit Fields */
bogdanm 87:6213f644d804 1633 #define FTM_SC_PS_MASK 0x7u
bogdanm 87:6213f644d804 1634 #define FTM_SC_PS_SHIFT 0
bogdanm 87:6213f644d804 1635 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
bogdanm 87:6213f644d804 1636 #define FTM_SC_CLKS_MASK 0x18u
bogdanm 87:6213f644d804 1637 #define FTM_SC_CLKS_SHIFT 3
bogdanm 87:6213f644d804 1638 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
bogdanm 87:6213f644d804 1639 #define FTM_SC_CPWMS_MASK 0x20u
bogdanm 87:6213f644d804 1640 #define FTM_SC_CPWMS_SHIFT 5
bogdanm 87:6213f644d804 1641 #define FTM_SC_TOIE_MASK 0x40u
bogdanm 87:6213f644d804 1642 #define FTM_SC_TOIE_SHIFT 6
bogdanm 87:6213f644d804 1643 #define FTM_SC_TOF_MASK 0x80u
bogdanm 87:6213f644d804 1644 #define FTM_SC_TOF_SHIFT 7
bogdanm 87:6213f644d804 1645 /* CNT Bit Fields */
bogdanm 87:6213f644d804 1646 #define FTM_CNT_COUNT_MASK 0xFFFFu
bogdanm 87:6213f644d804 1647 #define FTM_CNT_COUNT_SHIFT 0
bogdanm 87:6213f644d804 1648 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
bogdanm 87:6213f644d804 1649 /* MOD Bit Fields */
bogdanm 87:6213f644d804 1650 #define FTM_MOD_MOD_MASK 0xFFFFu
bogdanm 87:6213f644d804 1651 #define FTM_MOD_MOD_SHIFT 0
bogdanm 87:6213f644d804 1652 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
bogdanm 87:6213f644d804 1653 /* CnSC Bit Fields */
bogdanm 87:6213f644d804 1654 #define FTM_CnSC_DMA_MASK 0x1u
bogdanm 87:6213f644d804 1655 #define FTM_CnSC_DMA_SHIFT 0
bogdanm 87:6213f644d804 1656 #define FTM_CnSC_ELSA_MASK 0x4u
bogdanm 87:6213f644d804 1657 #define FTM_CnSC_ELSA_SHIFT 2
bogdanm 87:6213f644d804 1658 #define FTM_CnSC_ELSB_MASK 0x8u
bogdanm 87:6213f644d804 1659 #define FTM_CnSC_ELSB_SHIFT 3
bogdanm 87:6213f644d804 1660 #define FTM_CnSC_MSA_MASK 0x10u
bogdanm 87:6213f644d804 1661 #define FTM_CnSC_MSA_SHIFT 4
bogdanm 87:6213f644d804 1662 #define FTM_CnSC_MSB_MASK 0x20u
bogdanm 87:6213f644d804 1663 #define FTM_CnSC_MSB_SHIFT 5
bogdanm 87:6213f644d804 1664 #define FTM_CnSC_CHIE_MASK 0x40u
bogdanm 87:6213f644d804 1665 #define FTM_CnSC_CHIE_SHIFT 6
bogdanm 87:6213f644d804 1666 #define FTM_CnSC_CHF_MASK 0x80u
bogdanm 87:6213f644d804 1667 #define FTM_CnSC_CHF_SHIFT 7
bogdanm 87:6213f644d804 1668 /* CnV Bit Fields */
bogdanm 87:6213f644d804 1669 #define FTM_CnV_VAL_MASK 0xFFFFu
bogdanm 87:6213f644d804 1670 #define FTM_CnV_VAL_SHIFT 0
bogdanm 87:6213f644d804 1671 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
bogdanm 87:6213f644d804 1672 /* CNTIN Bit Fields */
bogdanm 87:6213f644d804 1673 #define FTM_CNTIN_INIT_MASK 0xFFFFu
bogdanm 87:6213f644d804 1674 #define FTM_CNTIN_INIT_SHIFT 0
bogdanm 87:6213f644d804 1675 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
bogdanm 87:6213f644d804 1676 /* STATUS Bit Fields */
bogdanm 87:6213f644d804 1677 #define FTM_STATUS_CH0F_MASK 0x1u
bogdanm 87:6213f644d804 1678 #define FTM_STATUS_CH0F_SHIFT 0
bogdanm 87:6213f644d804 1679 #define FTM_STATUS_CH1F_MASK 0x2u
bogdanm 87:6213f644d804 1680 #define FTM_STATUS_CH1F_SHIFT 1
bogdanm 87:6213f644d804 1681 #define FTM_STATUS_CH2F_MASK 0x4u
bogdanm 87:6213f644d804 1682 #define FTM_STATUS_CH2F_SHIFT 2
bogdanm 87:6213f644d804 1683 #define FTM_STATUS_CH3F_MASK 0x8u
bogdanm 87:6213f644d804 1684 #define FTM_STATUS_CH3F_SHIFT 3
bogdanm 87:6213f644d804 1685 #define FTM_STATUS_CH4F_MASK 0x10u
bogdanm 87:6213f644d804 1686 #define FTM_STATUS_CH4F_SHIFT 4
bogdanm 87:6213f644d804 1687 #define FTM_STATUS_CH5F_MASK 0x20u
bogdanm 87:6213f644d804 1688 #define FTM_STATUS_CH5F_SHIFT 5
bogdanm 87:6213f644d804 1689 #define FTM_STATUS_CH6F_MASK 0x40u
bogdanm 87:6213f644d804 1690 #define FTM_STATUS_CH6F_SHIFT 6
bogdanm 87:6213f644d804 1691 #define FTM_STATUS_CH7F_MASK 0x80u
bogdanm 87:6213f644d804 1692 #define FTM_STATUS_CH7F_SHIFT 7
bogdanm 87:6213f644d804 1693 /* MODE Bit Fields */
bogdanm 87:6213f644d804 1694 #define FTM_MODE_FTMEN_MASK 0x1u
bogdanm 87:6213f644d804 1695 #define FTM_MODE_FTMEN_SHIFT 0
bogdanm 87:6213f644d804 1696 #define FTM_MODE_INIT_MASK 0x2u
bogdanm 87:6213f644d804 1697 #define FTM_MODE_INIT_SHIFT 1
bogdanm 87:6213f644d804 1698 #define FTM_MODE_WPDIS_MASK 0x4u
bogdanm 87:6213f644d804 1699 #define FTM_MODE_WPDIS_SHIFT 2
bogdanm 87:6213f644d804 1700 #define FTM_MODE_PWMSYNC_MASK 0x8u
bogdanm 87:6213f644d804 1701 #define FTM_MODE_PWMSYNC_SHIFT 3
bogdanm 87:6213f644d804 1702 #define FTM_MODE_CAPTEST_MASK 0x10u
bogdanm 87:6213f644d804 1703 #define FTM_MODE_CAPTEST_SHIFT 4
bogdanm 87:6213f644d804 1704 #define FTM_MODE_FAULTM_MASK 0x60u
bogdanm 87:6213f644d804 1705 #define FTM_MODE_FAULTM_SHIFT 5
bogdanm 87:6213f644d804 1706 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
bogdanm 87:6213f644d804 1707 #define FTM_MODE_FAULTIE_MASK 0x80u
bogdanm 87:6213f644d804 1708 #define FTM_MODE_FAULTIE_SHIFT 7
bogdanm 87:6213f644d804 1709 /* SYNC Bit Fields */
bogdanm 87:6213f644d804 1710 #define FTM_SYNC_CNTMIN_MASK 0x1u
bogdanm 87:6213f644d804 1711 #define FTM_SYNC_CNTMIN_SHIFT 0
bogdanm 87:6213f644d804 1712 #define FTM_SYNC_CNTMAX_MASK 0x2u
bogdanm 87:6213f644d804 1713 #define FTM_SYNC_CNTMAX_SHIFT 1
bogdanm 87:6213f644d804 1714 #define FTM_SYNC_REINIT_MASK 0x4u
bogdanm 87:6213f644d804 1715 #define FTM_SYNC_REINIT_SHIFT 2
bogdanm 87:6213f644d804 1716 #define FTM_SYNC_SYNCHOM_MASK 0x8u
bogdanm 87:6213f644d804 1717 #define FTM_SYNC_SYNCHOM_SHIFT 3
bogdanm 87:6213f644d804 1718 #define FTM_SYNC_TRIG0_MASK 0x10u
bogdanm 87:6213f644d804 1719 #define FTM_SYNC_TRIG0_SHIFT 4
bogdanm 87:6213f644d804 1720 #define FTM_SYNC_TRIG1_MASK 0x20u
bogdanm 87:6213f644d804 1721 #define FTM_SYNC_TRIG1_SHIFT 5
bogdanm 87:6213f644d804 1722 #define FTM_SYNC_TRIG2_MASK 0x40u
bogdanm 87:6213f644d804 1723 #define FTM_SYNC_TRIG2_SHIFT 6
bogdanm 87:6213f644d804 1724 #define FTM_SYNC_SWSYNC_MASK 0x80u
bogdanm 87:6213f644d804 1725 #define FTM_SYNC_SWSYNC_SHIFT 7
bogdanm 87:6213f644d804 1726 /* OUTINIT Bit Fields */
bogdanm 87:6213f644d804 1727 #define FTM_OUTINIT_CH0OI_MASK 0x1u
bogdanm 87:6213f644d804 1728 #define FTM_OUTINIT_CH0OI_SHIFT 0
bogdanm 87:6213f644d804 1729 #define FTM_OUTINIT_CH1OI_MASK 0x2u
bogdanm 87:6213f644d804 1730 #define FTM_OUTINIT_CH1OI_SHIFT 1
bogdanm 87:6213f644d804 1731 #define FTM_OUTINIT_CH2OI_MASK 0x4u
bogdanm 87:6213f644d804 1732 #define FTM_OUTINIT_CH2OI_SHIFT 2
bogdanm 87:6213f644d804 1733 #define FTM_OUTINIT_CH3OI_MASK 0x8u
bogdanm 87:6213f644d804 1734 #define FTM_OUTINIT_CH3OI_SHIFT 3
bogdanm 87:6213f644d804 1735 #define FTM_OUTINIT_CH4OI_MASK 0x10u
bogdanm 87:6213f644d804 1736 #define FTM_OUTINIT_CH4OI_SHIFT 4
bogdanm 87:6213f644d804 1737 #define FTM_OUTINIT_CH5OI_MASK 0x20u
bogdanm 87:6213f644d804 1738 #define FTM_OUTINIT_CH5OI_SHIFT 5
bogdanm 87:6213f644d804 1739 #define FTM_OUTINIT_CH6OI_MASK 0x40u
bogdanm 87:6213f644d804 1740 #define FTM_OUTINIT_CH6OI_SHIFT 6
bogdanm 87:6213f644d804 1741 #define FTM_OUTINIT_CH7OI_MASK 0x80u
bogdanm 87:6213f644d804 1742 #define FTM_OUTINIT_CH7OI_SHIFT 7
bogdanm 87:6213f644d804 1743 /* OUTMASK Bit Fields */
bogdanm 87:6213f644d804 1744 #define FTM_OUTMASK_CH0OM_MASK 0x1u
bogdanm 87:6213f644d804 1745 #define FTM_OUTMASK_CH0OM_SHIFT 0
bogdanm 87:6213f644d804 1746 #define FTM_OUTMASK_CH1OM_MASK 0x2u
bogdanm 87:6213f644d804 1747 #define FTM_OUTMASK_CH1OM_SHIFT 1
bogdanm 87:6213f644d804 1748 #define FTM_OUTMASK_CH2OM_MASK 0x4u
bogdanm 87:6213f644d804 1749 #define FTM_OUTMASK_CH2OM_SHIFT 2
bogdanm 87:6213f644d804 1750 #define FTM_OUTMASK_CH3OM_MASK 0x8u
bogdanm 87:6213f644d804 1751 #define FTM_OUTMASK_CH3OM_SHIFT 3
bogdanm 87:6213f644d804 1752 #define FTM_OUTMASK_CH4OM_MASK 0x10u
bogdanm 87:6213f644d804 1753 #define FTM_OUTMASK_CH4OM_SHIFT 4
bogdanm 87:6213f644d804 1754 #define FTM_OUTMASK_CH5OM_MASK 0x20u
bogdanm 87:6213f644d804 1755 #define FTM_OUTMASK_CH5OM_SHIFT 5
bogdanm 87:6213f644d804 1756 #define FTM_OUTMASK_CH6OM_MASK 0x40u
bogdanm 87:6213f644d804 1757 #define FTM_OUTMASK_CH6OM_SHIFT 6
bogdanm 87:6213f644d804 1758 #define FTM_OUTMASK_CH7OM_MASK 0x80u
bogdanm 87:6213f644d804 1759 #define FTM_OUTMASK_CH7OM_SHIFT 7
bogdanm 87:6213f644d804 1760 /* COMBINE Bit Fields */
bogdanm 87:6213f644d804 1761 #define FTM_COMBINE_COMBINE0_MASK 0x1u
bogdanm 87:6213f644d804 1762 #define FTM_COMBINE_COMBINE0_SHIFT 0
bogdanm 87:6213f644d804 1763 #define FTM_COMBINE_COMP0_MASK 0x2u
bogdanm 87:6213f644d804 1764 #define FTM_COMBINE_COMP0_SHIFT 1
bogdanm 87:6213f644d804 1765 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
bogdanm 87:6213f644d804 1766 #define FTM_COMBINE_DECAPEN0_SHIFT 2
bogdanm 87:6213f644d804 1767 #define FTM_COMBINE_DECAP0_MASK 0x8u
bogdanm 87:6213f644d804 1768 #define FTM_COMBINE_DECAP0_SHIFT 3
bogdanm 87:6213f644d804 1769 #define FTM_COMBINE_DTEN0_MASK 0x10u
bogdanm 87:6213f644d804 1770 #define FTM_COMBINE_DTEN0_SHIFT 4
bogdanm 87:6213f644d804 1771 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
bogdanm 87:6213f644d804 1772 #define FTM_COMBINE_SYNCEN0_SHIFT 5
bogdanm 87:6213f644d804 1773 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
bogdanm 87:6213f644d804 1774 #define FTM_COMBINE_FAULTEN0_SHIFT 6
bogdanm 87:6213f644d804 1775 #define FTM_COMBINE_COMBINE1_MASK 0x100u
bogdanm 87:6213f644d804 1776 #define FTM_COMBINE_COMBINE1_SHIFT 8
bogdanm 87:6213f644d804 1777 #define FTM_COMBINE_COMP1_MASK 0x200u
bogdanm 87:6213f644d804 1778 #define FTM_COMBINE_COMP1_SHIFT 9
bogdanm 87:6213f644d804 1779 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
bogdanm 87:6213f644d804 1780 #define FTM_COMBINE_DECAPEN1_SHIFT 10
bogdanm 87:6213f644d804 1781 #define FTM_COMBINE_DECAP1_MASK 0x800u
bogdanm 87:6213f644d804 1782 #define FTM_COMBINE_DECAP1_SHIFT 11
bogdanm 87:6213f644d804 1783 #define FTM_COMBINE_DTEN1_MASK 0x1000u
bogdanm 87:6213f644d804 1784 #define FTM_COMBINE_DTEN1_SHIFT 12
bogdanm 87:6213f644d804 1785 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
bogdanm 87:6213f644d804 1786 #define FTM_COMBINE_SYNCEN1_SHIFT 13
bogdanm 87:6213f644d804 1787 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
bogdanm 87:6213f644d804 1788 #define FTM_COMBINE_FAULTEN1_SHIFT 14
bogdanm 87:6213f644d804 1789 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
bogdanm 87:6213f644d804 1790 #define FTM_COMBINE_COMBINE2_SHIFT 16
bogdanm 87:6213f644d804 1791 #define FTM_COMBINE_COMP2_MASK 0x20000u
bogdanm 87:6213f644d804 1792 #define FTM_COMBINE_COMP2_SHIFT 17
bogdanm 87:6213f644d804 1793 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
bogdanm 87:6213f644d804 1794 #define FTM_COMBINE_DECAPEN2_SHIFT 18
bogdanm 87:6213f644d804 1795 #define FTM_COMBINE_DECAP2_MASK 0x80000u
bogdanm 87:6213f644d804 1796 #define FTM_COMBINE_DECAP2_SHIFT 19
bogdanm 87:6213f644d804 1797 #define FTM_COMBINE_DTEN2_MASK 0x100000u
bogdanm 87:6213f644d804 1798 #define FTM_COMBINE_DTEN2_SHIFT 20
bogdanm 87:6213f644d804 1799 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
bogdanm 87:6213f644d804 1800 #define FTM_COMBINE_SYNCEN2_SHIFT 21
bogdanm 87:6213f644d804 1801 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
bogdanm 87:6213f644d804 1802 #define FTM_COMBINE_FAULTEN2_SHIFT 22
bogdanm 87:6213f644d804 1803 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
bogdanm 87:6213f644d804 1804 #define FTM_COMBINE_COMBINE3_SHIFT 24
bogdanm 87:6213f644d804 1805 #define FTM_COMBINE_COMP3_MASK 0x2000000u
bogdanm 87:6213f644d804 1806 #define FTM_COMBINE_COMP3_SHIFT 25
bogdanm 87:6213f644d804 1807 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
bogdanm 87:6213f644d804 1808 #define FTM_COMBINE_DECAPEN3_SHIFT 26
bogdanm 87:6213f644d804 1809 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
bogdanm 87:6213f644d804 1810 #define FTM_COMBINE_DECAP3_SHIFT 27
bogdanm 87:6213f644d804 1811 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
bogdanm 87:6213f644d804 1812 #define FTM_COMBINE_DTEN3_SHIFT 28
bogdanm 87:6213f644d804 1813 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
bogdanm 87:6213f644d804 1814 #define FTM_COMBINE_SYNCEN3_SHIFT 29
bogdanm 87:6213f644d804 1815 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
bogdanm 87:6213f644d804 1816 #define FTM_COMBINE_FAULTEN3_SHIFT 30
bogdanm 87:6213f644d804 1817 /* DEADTIME Bit Fields */
bogdanm 87:6213f644d804 1818 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
bogdanm 87:6213f644d804 1819 #define FTM_DEADTIME_DTVAL_SHIFT 0
bogdanm 87:6213f644d804 1820 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
bogdanm 87:6213f644d804 1821 #define FTM_DEADTIME_DTPS_MASK 0xC0u
bogdanm 87:6213f644d804 1822 #define FTM_DEADTIME_DTPS_SHIFT 6
bogdanm 87:6213f644d804 1823 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
bogdanm 87:6213f644d804 1824 /* EXTTRIG Bit Fields */
bogdanm 87:6213f644d804 1825 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
bogdanm 87:6213f644d804 1826 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
bogdanm 87:6213f644d804 1827 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
bogdanm 87:6213f644d804 1828 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
bogdanm 87:6213f644d804 1829 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
bogdanm 87:6213f644d804 1830 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
bogdanm 87:6213f644d804 1831 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
bogdanm 87:6213f644d804 1832 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
bogdanm 87:6213f644d804 1833 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
bogdanm 87:6213f644d804 1834 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
bogdanm 87:6213f644d804 1835 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
bogdanm 87:6213f644d804 1836 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
bogdanm 87:6213f644d804 1837 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
bogdanm 87:6213f644d804 1838 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
bogdanm 87:6213f644d804 1839 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
bogdanm 87:6213f644d804 1840 #define FTM_EXTTRIG_TRIGF_SHIFT 7
bogdanm 87:6213f644d804 1841 /* POL Bit Fields */
bogdanm 87:6213f644d804 1842 #define FTM_POL_POL0_MASK 0x1u
bogdanm 87:6213f644d804 1843 #define FTM_POL_POL0_SHIFT 0
bogdanm 87:6213f644d804 1844 #define FTM_POL_POL1_MASK 0x2u
bogdanm 87:6213f644d804 1845 #define FTM_POL_POL1_SHIFT 1
bogdanm 87:6213f644d804 1846 #define FTM_POL_POL2_MASK 0x4u
bogdanm 87:6213f644d804 1847 #define FTM_POL_POL2_SHIFT 2
bogdanm 87:6213f644d804 1848 #define FTM_POL_POL3_MASK 0x8u
bogdanm 87:6213f644d804 1849 #define FTM_POL_POL3_SHIFT 3
bogdanm 87:6213f644d804 1850 #define FTM_POL_POL4_MASK 0x10u
bogdanm 87:6213f644d804 1851 #define FTM_POL_POL4_SHIFT 4
bogdanm 87:6213f644d804 1852 #define FTM_POL_POL5_MASK 0x20u
bogdanm 87:6213f644d804 1853 #define FTM_POL_POL5_SHIFT 5
bogdanm 87:6213f644d804 1854 #define FTM_POL_POL6_MASK 0x40u
bogdanm 87:6213f644d804 1855 #define FTM_POL_POL6_SHIFT 6
bogdanm 87:6213f644d804 1856 #define FTM_POL_POL7_MASK 0x80u
bogdanm 87:6213f644d804 1857 #define FTM_POL_POL7_SHIFT 7
bogdanm 87:6213f644d804 1858 /* FMS Bit Fields */
bogdanm 87:6213f644d804 1859 #define FTM_FMS_FAULTF0_MASK 0x1u
bogdanm 87:6213f644d804 1860 #define FTM_FMS_FAULTF0_SHIFT 0
bogdanm 87:6213f644d804 1861 #define FTM_FMS_FAULTF1_MASK 0x2u
bogdanm 87:6213f644d804 1862 #define FTM_FMS_FAULTF1_SHIFT 1
bogdanm 87:6213f644d804 1863 #define FTM_FMS_FAULTF2_MASK 0x4u
bogdanm 87:6213f644d804 1864 #define FTM_FMS_FAULTF2_SHIFT 2
bogdanm 87:6213f644d804 1865 #define FTM_FMS_FAULTF3_MASK 0x8u
bogdanm 87:6213f644d804 1866 #define FTM_FMS_FAULTF3_SHIFT 3
bogdanm 87:6213f644d804 1867 #define FTM_FMS_FAULTIN_MASK 0x20u
bogdanm 87:6213f644d804 1868 #define FTM_FMS_FAULTIN_SHIFT 5
bogdanm 87:6213f644d804 1869 #define FTM_FMS_WPEN_MASK 0x40u
bogdanm 87:6213f644d804 1870 #define FTM_FMS_WPEN_SHIFT 6
bogdanm 87:6213f644d804 1871 #define FTM_FMS_FAULTF_MASK 0x80u
bogdanm 87:6213f644d804 1872 #define FTM_FMS_FAULTF_SHIFT 7
bogdanm 87:6213f644d804 1873 /* FILTER Bit Fields */
bogdanm 87:6213f644d804 1874 #define FTM_FILTER_CH0FVAL_MASK 0xFu
bogdanm 87:6213f644d804 1875 #define FTM_FILTER_CH0FVAL_SHIFT 0
bogdanm 87:6213f644d804 1876 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
bogdanm 87:6213f644d804 1877 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
bogdanm 87:6213f644d804 1878 #define FTM_FILTER_CH1FVAL_SHIFT 4
bogdanm 87:6213f644d804 1879 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
bogdanm 87:6213f644d804 1880 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
bogdanm 87:6213f644d804 1881 #define FTM_FILTER_CH2FVAL_SHIFT 8
bogdanm 87:6213f644d804 1882 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
bogdanm 87:6213f644d804 1883 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
bogdanm 87:6213f644d804 1884 #define FTM_FILTER_CH3FVAL_SHIFT 12
bogdanm 87:6213f644d804 1885 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
bogdanm 87:6213f644d804 1886 /* FLTCTRL Bit Fields */
bogdanm 87:6213f644d804 1887 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
bogdanm 87:6213f644d804 1888 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
bogdanm 87:6213f644d804 1889 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
bogdanm 87:6213f644d804 1890 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
bogdanm 87:6213f644d804 1891 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
bogdanm 87:6213f644d804 1892 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
bogdanm 87:6213f644d804 1893 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
bogdanm 87:6213f644d804 1894 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
bogdanm 87:6213f644d804 1895 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
bogdanm 87:6213f644d804 1896 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
bogdanm 87:6213f644d804 1897 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
bogdanm 87:6213f644d804 1898 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
bogdanm 87:6213f644d804 1899 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
bogdanm 87:6213f644d804 1900 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
bogdanm 87:6213f644d804 1901 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
bogdanm 87:6213f644d804 1902 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
bogdanm 87:6213f644d804 1903 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
bogdanm 87:6213f644d804 1904 #define FTM_FLTCTRL_FFVAL_SHIFT 8
bogdanm 87:6213f644d804 1905 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
bogdanm 87:6213f644d804 1906 /* QDCTRL Bit Fields */
bogdanm 87:6213f644d804 1907 #define FTM_QDCTRL_QUADEN_MASK 0x1u
bogdanm 87:6213f644d804 1908 #define FTM_QDCTRL_QUADEN_SHIFT 0
bogdanm 87:6213f644d804 1909 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
bogdanm 87:6213f644d804 1910 #define FTM_QDCTRL_TOFDIR_SHIFT 1
bogdanm 87:6213f644d804 1911 #define FTM_QDCTRL_QUADIR_MASK 0x4u
bogdanm 87:6213f644d804 1912 #define FTM_QDCTRL_QUADIR_SHIFT 2
bogdanm 87:6213f644d804 1913 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
bogdanm 87:6213f644d804 1914 #define FTM_QDCTRL_QUADMODE_SHIFT 3
bogdanm 87:6213f644d804 1915 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
bogdanm 87:6213f644d804 1916 #define FTM_QDCTRL_PHBPOL_SHIFT 4
bogdanm 87:6213f644d804 1917 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
bogdanm 87:6213f644d804 1918 #define FTM_QDCTRL_PHAPOL_SHIFT 5
bogdanm 87:6213f644d804 1919 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
bogdanm 87:6213f644d804 1920 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
bogdanm 87:6213f644d804 1921 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
bogdanm 87:6213f644d804 1922 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
bogdanm 87:6213f644d804 1923 /* CONF Bit Fields */
bogdanm 87:6213f644d804 1924 #define FTM_CONF_NUMTOF_MASK 0x1Fu
bogdanm 87:6213f644d804 1925 #define FTM_CONF_NUMTOF_SHIFT 0
bogdanm 87:6213f644d804 1926 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
bogdanm 87:6213f644d804 1927 #define FTM_CONF_BDMMODE_MASK 0xC0u
bogdanm 87:6213f644d804 1928 #define FTM_CONF_BDMMODE_SHIFT 6
bogdanm 87:6213f644d804 1929 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
bogdanm 87:6213f644d804 1930 #define FTM_CONF_GTBEEN_MASK 0x200u
bogdanm 87:6213f644d804 1931 #define FTM_CONF_GTBEEN_SHIFT 9
bogdanm 87:6213f644d804 1932 #define FTM_CONF_GTBEOUT_MASK 0x400u
bogdanm 87:6213f644d804 1933 #define FTM_CONF_GTBEOUT_SHIFT 10
bogdanm 87:6213f644d804 1934 /* FLTPOL Bit Fields */
bogdanm 87:6213f644d804 1935 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
bogdanm 87:6213f644d804 1936 #define FTM_FLTPOL_FLT0POL_SHIFT 0
bogdanm 87:6213f644d804 1937 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
bogdanm 87:6213f644d804 1938 #define FTM_FLTPOL_FLT1POL_SHIFT 1
bogdanm 87:6213f644d804 1939 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
bogdanm 87:6213f644d804 1940 #define FTM_FLTPOL_FLT2POL_SHIFT 2
bogdanm 87:6213f644d804 1941 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
bogdanm 87:6213f644d804 1942 #define FTM_FLTPOL_FLT3POL_SHIFT 3
bogdanm 87:6213f644d804 1943 /* SYNCONF Bit Fields */
bogdanm 87:6213f644d804 1944 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
bogdanm 87:6213f644d804 1945 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
bogdanm 87:6213f644d804 1946 #define FTM_SYNCONF_CNTINC_MASK 0x4u
bogdanm 87:6213f644d804 1947 #define FTM_SYNCONF_CNTINC_SHIFT 2
bogdanm 87:6213f644d804 1948 #define FTM_SYNCONF_INVC_MASK 0x10u
bogdanm 87:6213f644d804 1949 #define FTM_SYNCONF_INVC_SHIFT 4
bogdanm 87:6213f644d804 1950 #define FTM_SYNCONF_SWOC_MASK 0x20u
bogdanm 87:6213f644d804 1951 #define FTM_SYNCONF_SWOC_SHIFT 5
bogdanm 87:6213f644d804 1952 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
bogdanm 87:6213f644d804 1953 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
bogdanm 87:6213f644d804 1954 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
bogdanm 87:6213f644d804 1955 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
bogdanm 87:6213f644d804 1956 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
bogdanm 87:6213f644d804 1957 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
bogdanm 87:6213f644d804 1958 #define FTM_SYNCONF_SWOM_MASK 0x400u
bogdanm 87:6213f644d804 1959 #define FTM_SYNCONF_SWOM_SHIFT 10
bogdanm 87:6213f644d804 1960 #define FTM_SYNCONF_SWINVC_MASK 0x800u
bogdanm 87:6213f644d804 1961 #define FTM_SYNCONF_SWINVC_SHIFT 11
bogdanm 87:6213f644d804 1962 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
bogdanm 87:6213f644d804 1963 #define FTM_SYNCONF_SWSOC_SHIFT 12
bogdanm 87:6213f644d804 1964 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
bogdanm 87:6213f644d804 1965 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
bogdanm 87:6213f644d804 1966 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
bogdanm 87:6213f644d804 1967 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
bogdanm 87:6213f644d804 1968 #define FTM_SYNCONF_HWOM_MASK 0x40000u
bogdanm 87:6213f644d804 1969 #define FTM_SYNCONF_HWOM_SHIFT 18
bogdanm 87:6213f644d804 1970 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
bogdanm 87:6213f644d804 1971 #define FTM_SYNCONF_HWINVC_SHIFT 19
bogdanm 87:6213f644d804 1972 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
bogdanm 87:6213f644d804 1973 #define FTM_SYNCONF_HWSOC_SHIFT 20
bogdanm 87:6213f644d804 1974 /* INVCTRL Bit Fields */
bogdanm 87:6213f644d804 1975 #define FTM_INVCTRL_INV0EN_MASK 0x1u
bogdanm 87:6213f644d804 1976 #define FTM_INVCTRL_INV0EN_SHIFT 0
bogdanm 87:6213f644d804 1977 #define FTM_INVCTRL_INV1EN_MASK 0x2u
bogdanm 87:6213f644d804 1978 #define FTM_INVCTRL_INV1EN_SHIFT 1
bogdanm 87:6213f644d804 1979 #define FTM_INVCTRL_INV2EN_MASK 0x4u
bogdanm 87:6213f644d804 1980 #define FTM_INVCTRL_INV2EN_SHIFT 2
bogdanm 87:6213f644d804 1981 #define FTM_INVCTRL_INV3EN_MASK 0x8u
bogdanm 87:6213f644d804 1982 #define FTM_INVCTRL_INV3EN_SHIFT 3
bogdanm 87:6213f644d804 1983 /* SWOCTRL Bit Fields */
bogdanm 87:6213f644d804 1984 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
bogdanm 87:6213f644d804 1985 #define FTM_SWOCTRL_CH0OC_SHIFT 0
bogdanm 87:6213f644d804 1986 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
bogdanm 87:6213f644d804 1987 #define FTM_SWOCTRL_CH1OC_SHIFT 1
bogdanm 87:6213f644d804 1988 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
bogdanm 87:6213f644d804 1989 #define FTM_SWOCTRL_CH2OC_SHIFT 2
bogdanm 87:6213f644d804 1990 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
bogdanm 87:6213f644d804 1991 #define FTM_SWOCTRL_CH3OC_SHIFT 3
bogdanm 87:6213f644d804 1992 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
bogdanm 87:6213f644d804 1993 #define FTM_SWOCTRL_CH4OC_SHIFT 4
bogdanm 87:6213f644d804 1994 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
bogdanm 87:6213f644d804 1995 #define FTM_SWOCTRL_CH5OC_SHIFT 5
bogdanm 87:6213f644d804 1996 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
bogdanm 87:6213f644d804 1997 #define FTM_SWOCTRL_CH6OC_SHIFT 6
bogdanm 87:6213f644d804 1998 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
bogdanm 87:6213f644d804 1999 #define FTM_SWOCTRL_CH7OC_SHIFT 7
bogdanm 87:6213f644d804 2000 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
bogdanm 87:6213f644d804 2001 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
bogdanm 87:6213f644d804 2002 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
bogdanm 87:6213f644d804 2003 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
bogdanm 87:6213f644d804 2004 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
bogdanm 87:6213f644d804 2005 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
bogdanm 87:6213f644d804 2006 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
bogdanm 87:6213f644d804 2007 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
bogdanm 87:6213f644d804 2008 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
bogdanm 87:6213f644d804 2009 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
bogdanm 87:6213f644d804 2010 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
bogdanm 87:6213f644d804 2011 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
bogdanm 87:6213f644d804 2012 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
bogdanm 87:6213f644d804 2013 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
bogdanm 87:6213f644d804 2014 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
bogdanm 87:6213f644d804 2015 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
bogdanm 87:6213f644d804 2016 /* PWMLOAD Bit Fields */
bogdanm 87:6213f644d804 2017 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
bogdanm 87:6213f644d804 2018 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
bogdanm 87:6213f644d804 2019 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
bogdanm 87:6213f644d804 2020 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
bogdanm 87:6213f644d804 2021 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
bogdanm 87:6213f644d804 2022 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
bogdanm 87:6213f644d804 2023 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
bogdanm 87:6213f644d804 2024 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
bogdanm 87:6213f644d804 2025 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
bogdanm 87:6213f644d804 2026 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
bogdanm 87:6213f644d804 2027 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
bogdanm 87:6213f644d804 2028 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
bogdanm 87:6213f644d804 2029 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
bogdanm 87:6213f644d804 2030 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
bogdanm 87:6213f644d804 2031 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
bogdanm 87:6213f644d804 2032 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
bogdanm 87:6213f644d804 2033 #define FTM_PWMLOAD_LDOK_MASK 0x200u
bogdanm 87:6213f644d804 2034 #define FTM_PWMLOAD_LDOK_SHIFT 9
bogdanm 87:6213f644d804 2035
bogdanm 87:6213f644d804 2036 /**
bogdanm 87:6213f644d804 2037 * @}
bogdanm 87:6213f644d804 2038 */ /* end of group FTM_Register_Masks */
bogdanm 87:6213f644d804 2039
bogdanm 87:6213f644d804 2040
bogdanm 87:6213f644d804 2041 /* FTM - Peripheral instance base addresses */
bogdanm 87:6213f644d804 2042 /** Peripheral FTM0 base address */
bogdanm 87:6213f644d804 2043 #define FTM0_BASE (0x40038000u)
bogdanm 87:6213f644d804 2044 /** Peripheral FTM0 base pointer */
bogdanm 87:6213f644d804 2045 #define FTM0 ((FTM_Type *)FTM0_BASE)
bogdanm 87:6213f644d804 2046 /** Peripheral FTM1 base address */
bogdanm 87:6213f644d804 2047 #define FTM1_BASE (0x40039000u)
bogdanm 87:6213f644d804 2048 /** Peripheral FTM1 base pointer */
bogdanm 87:6213f644d804 2049 #define FTM1 ((FTM_Type *)FTM1_BASE)
bogdanm 87:6213f644d804 2050
bogdanm 87:6213f644d804 2051 /**
bogdanm 87:6213f644d804 2052 * @}
bogdanm 87:6213f644d804 2053 */ /* end of group FTM_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 2054
bogdanm 87:6213f644d804 2055
bogdanm 87:6213f644d804 2056 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2057 -- GPIO Peripheral Access Layer
bogdanm 87:6213f644d804 2058 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2059
bogdanm 87:6213f644d804 2060 /**
bogdanm 87:6213f644d804 2061 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
bogdanm 87:6213f644d804 2062 * @{
bogdanm 87:6213f644d804 2063 */
bogdanm 87:6213f644d804 2064
bogdanm 87:6213f644d804 2065 /** GPIO - Register Layout Typedef */
bogdanm 87:6213f644d804 2066 typedef struct {
bogdanm 87:6213f644d804 2067 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 87:6213f644d804 2068 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 87:6213f644d804 2069 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 87:6213f644d804 2070 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 87:6213f644d804 2071 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 87:6213f644d804 2072 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 87:6213f644d804 2073 } GPIO_Type;
bogdanm 87:6213f644d804 2074
bogdanm 87:6213f644d804 2075 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2076 -- GPIO Register Masks
bogdanm 87:6213f644d804 2077 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2078
bogdanm 87:6213f644d804 2079 /**
bogdanm 87:6213f644d804 2080 * @addtogroup GPIO_Register_Masks GPIO Register Masks
bogdanm 87:6213f644d804 2081 * @{
bogdanm 87:6213f644d804 2082 */
bogdanm 87:6213f644d804 2083
bogdanm 87:6213f644d804 2084 /* PDOR Bit Fields */
bogdanm 87:6213f644d804 2085 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2086 #define GPIO_PDOR_PDO_SHIFT 0
bogdanm 87:6213f644d804 2087 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
bogdanm 87:6213f644d804 2088 /* PSOR Bit Fields */
bogdanm 87:6213f644d804 2089 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2090 #define GPIO_PSOR_PTSO_SHIFT 0
bogdanm 87:6213f644d804 2091 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
bogdanm 87:6213f644d804 2092 /* PCOR Bit Fields */
bogdanm 87:6213f644d804 2093 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2094 #define GPIO_PCOR_PTCO_SHIFT 0
bogdanm 87:6213f644d804 2095 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
bogdanm 87:6213f644d804 2096 /* PTOR Bit Fields */
bogdanm 87:6213f644d804 2097 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2098 #define GPIO_PTOR_PTTO_SHIFT 0
bogdanm 87:6213f644d804 2099 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
bogdanm 87:6213f644d804 2100 /* PDIR Bit Fields */
bogdanm 87:6213f644d804 2101 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2102 #define GPIO_PDIR_PDI_SHIFT 0
bogdanm 87:6213f644d804 2103 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
bogdanm 87:6213f644d804 2104 /* PDDR Bit Fields */
bogdanm 87:6213f644d804 2105 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2106 #define GPIO_PDDR_PDD_SHIFT 0
bogdanm 87:6213f644d804 2107 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
bogdanm 87:6213f644d804 2108
bogdanm 87:6213f644d804 2109 /**
bogdanm 87:6213f644d804 2110 * @}
bogdanm 87:6213f644d804 2111 */ /* end of group GPIO_Register_Masks */
bogdanm 87:6213f644d804 2112
bogdanm 87:6213f644d804 2113
bogdanm 87:6213f644d804 2114 /* GPIO - Peripheral instance base addresses */
bogdanm 87:6213f644d804 2115 /** Peripheral PTA base address */
bogdanm 87:6213f644d804 2116 #define PTA_BASE (0x400FF000u)
bogdanm 87:6213f644d804 2117 /** Peripheral PTA base pointer */
bogdanm 87:6213f644d804 2118 #define PTA ((GPIO_Type *)PTA_BASE)
bogdanm 87:6213f644d804 2119 /** Peripheral PTB base address */
bogdanm 87:6213f644d804 2120 #define PTB_BASE (0x400FF040u)
bogdanm 87:6213f644d804 2121 /** Peripheral PTB base pointer */
bogdanm 87:6213f644d804 2122 #define PTB ((GPIO_Type *)PTB_BASE)
bogdanm 87:6213f644d804 2123 /** Peripheral PTC base address */
bogdanm 87:6213f644d804 2124 #define PTC_BASE (0x400FF080u)
bogdanm 87:6213f644d804 2125 /** Peripheral PTC base pointer */
bogdanm 87:6213f644d804 2126 #define PTC ((GPIO_Type *)PTC_BASE)
bogdanm 87:6213f644d804 2127 /** Peripheral PTD base address */
bogdanm 87:6213f644d804 2128 #define PTD_BASE (0x400FF0C0u)
bogdanm 87:6213f644d804 2129 /** Peripheral PTD base pointer */
bogdanm 87:6213f644d804 2130 #define PTD ((GPIO_Type *)PTD_BASE)
bogdanm 87:6213f644d804 2131 /** Peripheral PTE base address */
bogdanm 87:6213f644d804 2132 #define PTE_BASE (0x400FF100u)
bogdanm 87:6213f644d804 2133 /** Peripheral PTE base pointer */
bogdanm 87:6213f644d804 2134 #define PTE ((GPIO_Type *)PTE_BASE)
bogdanm 87:6213f644d804 2135
bogdanm 87:6213f644d804 2136 /**
bogdanm 87:6213f644d804 2137 * @}
bogdanm 87:6213f644d804 2138 */ /* end of group GPIO_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 2139
bogdanm 87:6213f644d804 2140
bogdanm 87:6213f644d804 2141 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2142 -- I2C Peripheral Access Layer
bogdanm 87:6213f644d804 2143 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2144
bogdanm 87:6213f644d804 2145 /**
bogdanm 87:6213f644d804 2146 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
bogdanm 87:6213f644d804 2147 * @{
bogdanm 87:6213f644d804 2148 */
bogdanm 87:6213f644d804 2149
bogdanm 87:6213f644d804 2150 /** I2C - Register Layout Typedef */
bogdanm 87:6213f644d804 2151 typedef struct {
bogdanm 87:6213f644d804 2152 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
bogdanm 87:6213f644d804 2153 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
bogdanm 87:6213f644d804 2154 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
bogdanm 87:6213f644d804 2155 __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
bogdanm 87:6213f644d804 2156 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
bogdanm 87:6213f644d804 2157 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
bogdanm 87:6213f644d804 2158 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
bogdanm 87:6213f644d804 2159 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
bogdanm 87:6213f644d804 2160 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
bogdanm 87:6213f644d804 2161 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
bogdanm 87:6213f644d804 2162 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
bogdanm 87:6213f644d804 2163 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
bogdanm 87:6213f644d804 2164 } I2C_Type;
bogdanm 87:6213f644d804 2165
bogdanm 87:6213f644d804 2166 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2167 -- I2C Register Masks
bogdanm 87:6213f644d804 2168 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2169
bogdanm 87:6213f644d804 2170 /**
bogdanm 87:6213f644d804 2171 * @addtogroup I2C_Register_Masks I2C Register Masks
bogdanm 87:6213f644d804 2172 * @{
bogdanm 87:6213f644d804 2173 */
bogdanm 87:6213f644d804 2174
bogdanm 87:6213f644d804 2175 /* A1 Bit Fields */
bogdanm 87:6213f644d804 2176 #define I2C_A1_AD_MASK 0xFEu
bogdanm 87:6213f644d804 2177 #define I2C_A1_AD_SHIFT 1
bogdanm 87:6213f644d804 2178 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
bogdanm 87:6213f644d804 2179 /* F Bit Fields */
bogdanm 87:6213f644d804 2180 #define I2C_F_ICR_MASK 0x3Fu
bogdanm 87:6213f644d804 2181 #define I2C_F_ICR_SHIFT 0
bogdanm 87:6213f644d804 2182 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
bogdanm 87:6213f644d804 2183 #define I2C_F_MULT_MASK 0xC0u
bogdanm 87:6213f644d804 2184 #define I2C_F_MULT_SHIFT 6
bogdanm 87:6213f644d804 2185 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
bogdanm 87:6213f644d804 2186 /* C1 Bit Fields */
bogdanm 87:6213f644d804 2187 #define I2C_C1_DMAEN_MASK 0x1u
bogdanm 87:6213f644d804 2188 #define I2C_C1_DMAEN_SHIFT 0
bogdanm 87:6213f644d804 2189 #define I2C_C1_WUEN_MASK 0x2u
bogdanm 87:6213f644d804 2190 #define I2C_C1_WUEN_SHIFT 1
bogdanm 87:6213f644d804 2191 #define I2C_C1_RSTA_MASK 0x4u
bogdanm 87:6213f644d804 2192 #define I2C_C1_RSTA_SHIFT 2
bogdanm 87:6213f644d804 2193 #define I2C_C1_TXAK_MASK 0x8u
bogdanm 87:6213f644d804 2194 #define I2C_C1_TXAK_SHIFT 3
bogdanm 87:6213f644d804 2195 #define I2C_C1_TX_MASK 0x10u
bogdanm 87:6213f644d804 2196 #define I2C_C1_TX_SHIFT 4
bogdanm 87:6213f644d804 2197 #define I2C_C1_MST_MASK 0x20u
bogdanm 87:6213f644d804 2198 #define I2C_C1_MST_SHIFT 5
bogdanm 87:6213f644d804 2199 #define I2C_C1_IICIE_MASK 0x40u
bogdanm 87:6213f644d804 2200 #define I2C_C1_IICIE_SHIFT 6
bogdanm 87:6213f644d804 2201 #define I2C_C1_IICEN_MASK 0x80u
bogdanm 87:6213f644d804 2202 #define I2C_C1_IICEN_SHIFT 7
bogdanm 87:6213f644d804 2203 /* S Bit Fields */
bogdanm 87:6213f644d804 2204 #define I2C_S_RXAK_MASK 0x1u
bogdanm 87:6213f644d804 2205 #define I2C_S_RXAK_SHIFT 0
bogdanm 87:6213f644d804 2206 #define I2C_S_IICIF_MASK 0x2u
bogdanm 87:6213f644d804 2207 #define I2C_S_IICIF_SHIFT 1
bogdanm 87:6213f644d804 2208 #define I2C_S_SRW_MASK 0x4u
bogdanm 87:6213f644d804 2209 #define I2C_S_SRW_SHIFT 2
bogdanm 87:6213f644d804 2210 #define I2C_S_RAM_MASK 0x8u
bogdanm 87:6213f644d804 2211 #define I2C_S_RAM_SHIFT 3
bogdanm 87:6213f644d804 2212 #define I2C_S_ARBL_MASK 0x10u
bogdanm 87:6213f644d804 2213 #define I2C_S_ARBL_SHIFT 4
bogdanm 87:6213f644d804 2214 #define I2C_S_BUSY_MASK 0x20u
bogdanm 87:6213f644d804 2215 #define I2C_S_BUSY_SHIFT 5
bogdanm 87:6213f644d804 2216 #define I2C_S_IAAS_MASK 0x40u
bogdanm 87:6213f644d804 2217 #define I2C_S_IAAS_SHIFT 6
bogdanm 87:6213f644d804 2218 #define I2C_S_TCF_MASK 0x80u
bogdanm 87:6213f644d804 2219 #define I2C_S_TCF_SHIFT 7
bogdanm 87:6213f644d804 2220 /* D Bit Fields */
bogdanm 87:6213f644d804 2221 #define I2C_D_DATA_MASK 0xFFu
bogdanm 87:6213f644d804 2222 #define I2C_D_DATA_SHIFT 0
bogdanm 87:6213f644d804 2223 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
bogdanm 87:6213f644d804 2224 /* C2 Bit Fields */
bogdanm 87:6213f644d804 2225 #define I2C_C2_AD_MASK 0x7u
bogdanm 87:6213f644d804 2226 #define I2C_C2_AD_SHIFT 0
bogdanm 87:6213f644d804 2227 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
bogdanm 87:6213f644d804 2228 #define I2C_C2_RMEN_MASK 0x8u
bogdanm 87:6213f644d804 2229 #define I2C_C2_RMEN_SHIFT 3
bogdanm 87:6213f644d804 2230 #define I2C_C2_SBRC_MASK 0x10u
bogdanm 87:6213f644d804 2231 #define I2C_C2_SBRC_SHIFT 4
bogdanm 87:6213f644d804 2232 #define I2C_C2_HDRS_MASK 0x20u
bogdanm 87:6213f644d804 2233 #define I2C_C2_HDRS_SHIFT 5
bogdanm 87:6213f644d804 2234 #define I2C_C2_ADEXT_MASK 0x40u
bogdanm 87:6213f644d804 2235 #define I2C_C2_ADEXT_SHIFT 6
bogdanm 87:6213f644d804 2236 #define I2C_C2_GCAEN_MASK 0x80u
bogdanm 87:6213f644d804 2237 #define I2C_C2_GCAEN_SHIFT 7
bogdanm 87:6213f644d804 2238 /* FLT Bit Fields */
bogdanm 87:6213f644d804 2239 #define I2C_FLT_FLT_MASK 0x1Fu
bogdanm 87:6213f644d804 2240 #define I2C_FLT_FLT_SHIFT 0
bogdanm 87:6213f644d804 2241 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
bogdanm 87:6213f644d804 2242 /* RA Bit Fields */
bogdanm 87:6213f644d804 2243 #define I2C_RA_RAD_MASK 0xFEu
bogdanm 87:6213f644d804 2244 #define I2C_RA_RAD_SHIFT 1
bogdanm 87:6213f644d804 2245 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
bogdanm 87:6213f644d804 2246 /* SMB Bit Fields */
bogdanm 87:6213f644d804 2247 #define I2C_SMB_SHTF2IE_MASK 0x1u
bogdanm 87:6213f644d804 2248 #define I2C_SMB_SHTF2IE_SHIFT 0
bogdanm 87:6213f644d804 2249 #define I2C_SMB_SHTF2_MASK 0x2u
bogdanm 87:6213f644d804 2250 #define I2C_SMB_SHTF2_SHIFT 1
bogdanm 87:6213f644d804 2251 #define I2C_SMB_SHTF1_MASK 0x4u
bogdanm 87:6213f644d804 2252 #define I2C_SMB_SHTF1_SHIFT 2
bogdanm 87:6213f644d804 2253 #define I2C_SMB_SLTF_MASK 0x8u
bogdanm 87:6213f644d804 2254 #define I2C_SMB_SLTF_SHIFT 3
bogdanm 87:6213f644d804 2255 #define I2C_SMB_TCKSEL_MASK 0x10u
bogdanm 87:6213f644d804 2256 #define I2C_SMB_TCKSEL_SHIFT 4
bogdanm 87:6213f644d804 2257 #define I2C_SMB_SIICAEN_MASK 0x20u
bogdanm 87:6213f644d804 2258 #define I2C_SMB_SIICAEN_SHIFT 5
bogdanm 87:6213f644d804 2259 #define I2C_SMB_ALERTEN_MASK 0x40u
bogdanm 87:6213f644d804 2260 #define I2C_SMB_ALERTEN_SHIFT 6
bogdanm 87:6213f644d804 2261 #define I2C_SMB_FACK_MASK 0x80u
bogdanm 87:6213f644d804 2262 #define I2C_SMB_FACK_SHIFT 7
bogdanm 87:6213f644d804 2263 /* A2 Bit Fields */
bogdanm 87:6213f644d804 2264 #define I2C_A2_SAD_MASK 0xFEu
bogdanm 87:6213f644d804 2265 #define I2C_A2_SAD_SHIFT 1
bogdanm 87:6213f644d804 2266 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
bogdanm 87:6213f644d804 2267 /* SLTH Bit Fields */
bogdanm 87:6213f644d804 2268 #define I2C_SLTH_SSLT_MASK 0xFFu
bogdanm 87:6213f644d804 2269 #define I2C_SLTH_SSLT_SHIFT 0
bogdanm 87:6213f644d804 2270 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
bogdanm 87:6213f644d804 2271 /* SLTL Bit Fields */
bogdanm 87:6213f644d804 2272 #define I2C_SLTL_SSLT_MASK 0xFFu
bogdanm 87:6213f644d804 2273 #define I2C_SLTL_SSLT_SHIFT 0
bogdanm 87:6213f644d804 2274 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
bogdanm 87:6213f644d804 2275
bogdanm 87:6213f644d804 2276 /**
bogdanm 87:6213f644d804 2277 * @}
bogdanm 87:6213f644d804 2278 */ /* end of group I2C_Register_Masks */
bogdanm 87:6213f644d804 2279
bogdanm 87:6213f644d804 2280
bogdanm 87:6213f644d804 2281 /* I2C - Peripheral instance base addresses */
bogdanm 87:6213f644d804 2282 /** Peripheral I2C0 base address */
bogdanm 87:6213f644d804 2283 #define I2C0_BASE (0x40066000u)
bogdanm 87:6213f644d804 2284 /** Peripheral I2C0 base pointer */
bogdanm 87:6213f644d804 2285 #define I2C0 ((I2C_Type *)I2C0_BASE)
bogdanm 87:6213f644d804 2286
bogdanm 87:6213f644d804 2287 /**
bogdanm 87:6213f644d804 2288 * @}
bogdanm 87:6213f644d804 2289 */ /* end of group I2C_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 2290
bogdanm 87:6213f644d804 2291
bogdanm 87:6213f644d804 2292 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2293 -- I2S Peripheral Access Layer
bogdanm 87:6213f644d804 2294 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2295
bogdanm 87:6213f644d804 2296 /**
bogdanm 87:6213f644d804 2297 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
bogdanm 87:6213f644d804 2298 * @{
bogdanm 87:6213f644d804 2299 */
bogdanm 87:6213f644d804 2300
bogdanm 87:6213f644d804 2301 /** I2S - Register Layout Typedef */
bogdanm 87:6213f644d804 2302 typedef struct {
bogdanm 87:6213f644d804 2303 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
bogdanm 87:6213f644d804 2304 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
bogdanm 87:6213f644d804 2305 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
bogdanm 87:6213f644d804 2306 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
bogdanm 87:6213f644d804 2307 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
bogdanm 87:6213f644d804 2308 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
bogdanm 87:6213f644d804 2309 uint8_t RESERVED_0[8];
bogdanm 87:6213f644d804 2310 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
bogdanm 87:6213f644d804 2311 uint8_t RESERVED_1[24];
bogdanm 87:6213f644d804 2312 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
bogdanm 87:6213f644d804 2313 uint8_t RESERVED_2[24];
bogdanm 87:6213f644d804 2314 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
bogdanm 87:6213f644d804 2315 uint8_t RESERVED_3[28];
bogdanm 87:6213f644d804 2316 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
bogdanm 87:6213f644d804 2317 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
bogdanm 87:6213f644d804 2318 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
bogdanm 87:6213f644d804 2319 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
bogdanm 87:6213f644d804 2320 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
bogdanm 87:6213f644d804 2321 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
bogdanm 87:6213f644d804 2322 uint8_t RESERVED_4[8];
bogdanm 87:6213f644d804 2323 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
bogdanm 87:6213f644d804 2324 uint8_t RESERVED_5[24];
bogdanm 87:6213f644d804 2325 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
bogdanm 87:6213f644d804 2326 uint8_t RESERVED_6[24];
bogdanm 87:6213f644d804 2327 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
bogdanm 87:6213f644d804 2328 uint8_t RESERVED_7[28];
bogdanm 87:6213f644d804 2329 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
bogdanm 87:6213f644d804 2330 __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
bogdanm 87:6213f644d804 2331 } I2S_Type;
bogdanm 87:6213f644d804 2332
bogdanm 87:6213f644d804 2333 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2334 -- I2S Register Masks
bogdanm 87:6213f644d804 2335 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2336
bogdanm 87:6213f644d804 2337 /**
bogdanm 87:6213f644d804 2338 * @addtogroup I2S_Register_Masks I2S Register Masks
bogdanm 87:6213f644d804 2339 * @{
bogdanm 87:6213f644d804 2340 */
bogdanm 87:6213f644d804 2341
bogdanm 87:6213f644d804 2342 /* TCSR Bit Fields */
bogdanm 87:6213f644d804 2343 #define I2S_TCSR_FRDE_MASK 0x1u
bogdanm 87:6213f644d804 2344 #define I2S_TCSR_FRDE_SHIFT 0
bogdanm 87:6213f644d804 2345 #define I2S_TCSR_FWDE_MASK 0x2u
bogdanm 87:6213f644d804 2346 #define I2S_TCSR_FWDE_SHIFT 1
bogdanm 87:6213f644d804 2347 #define I2S_TCSR_FRIE_MASK 0x100u
bogdanm 87:6213f644d804 2348 #define I2S_TCSR_FRIE_SHIFT 8
bogdanm 87:6213f644d804 2349 #define I2S_TCSR_FWIE_MASK 0x200u
bogdanm 87:6213f644d804 2350 #define I2S_TCSR_FWIE_SHIFT 9
bogdanm 87:6213f644d804 2351 #define I2S_TCSR_FEIE_MASK 0x400u
bogdanm 87:6213f644d804 2352 #define I2S_TCSR_FEIE_SHIFT 10
bogdanm 87:6213f644d804 2353 #define I2S_TCSR_SEIE_MASK 0x800u
bogdanm 87:6213f644d804 2354 #define I2S_TCSR_SEIE_SHIFT 11
bogdanm 87:6213f644d804 2355 #define I2S_TCSR_WSIE_MASK 0x1000u
bogdanm 87:6213f644d804 2356 #define I2S_TCSR_WSIE_SHIFT 12
bogdanm 87:6213f644d804 2357 #define I2S_TCSR_FRF_MASK 0x10000u
bogdanm 87:6213f644d804 2358 #define I2S_TCSR_FRF_SHIFT 16
bogdanm 87:6213f644d804 2359 #define I2S_TCSR_FWF_MASK 0x20000u
bogdanm 87:6213f644d804 2360 #define I2S_TCSR_FWF_SHIFT 17
bogdanm 87:6213f644d804 2361 #define I2S_TCSR_FEF_MASK 0x40000u
bogdanm 87:6213f644d804 2362 #define I2S_TCSR_FEF_SHIFT 18
bogdanm 87:6213f644d804 2363 #define I2S_TCSR_SEF_MASK 0x80000u
bogdanm 87:6213f644d804 2364 #define I2S_TCSR_SEF_SHIFT 19
bogdanm 87:6213f644d804 2365 #define I2S_TCSR_WSF_MASK 0x100000u
bogdanm 87:6213f644d804 2366 #define I2S_TCSR_WSF_SHIFT 20
bogdanm 87:6213f644d804 2367 #define I2S_TCSR_SR_MASK 0x1000000u
bogdanm 87:6213f644d804 2368 #define I2S_TCSR_SR_SHIFT 24
bogdanm 87:6213f644d804 2369 #define I2S_TCSR_FR_MASK 0x2000000u
bogdanm 87:6213f644d804 2370 #define I2S_TCSR_FR_SHIFT 25
bogdanm 87:6213f644d804 2371 #define I2S_TCSR_BCE_MASK 0x10000000u
bogdanm 87:6213f644d804 2372 #define I2S_TCSR_BCE_SHIFT 28
bogdanm 87:6213f644d804 2373 #define I2S_TCSR_DBGE_MASK 0x20000000u
bogdanm 87:6213f644d804 2374 #define I2S_TCSR_DBGE_SHIFT 29
bogdanm 87:6213f644d804 2375 #define I2S_TCSR_STOPE_MASK 0x40000000u
bogdanm 87:6213f644d804 2376 #define I2S_TCSR_STOPE_SHIFT 30
bogdanm 87:6213f644d804 2377 #define I2S_TCSR_TE_MASK 0x80000000u
bogdanm 87:6213f644d804 2378 #define I2S_TCSR_TE_SHIFT 31
bogdanm 87:6213f644d804 2379 /* TCR1 Bit Fields */
bogdanm 87:6213f644d804 2380 #define I2S_TCR1_TFW_MASK 0x7u
bogdanm 87:6213f644d804 2381 #define I2S_TCR1_TFW_SHIFT 0
bogdanm 87:6213f644d804 2382 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
bogdanm 87:6213f644d804 2383 /* TCR2 Bit Fields */
bogdanm 87:6213f644d804 2384 #define I2S_TCR2_DIV_MASK 0xFFu
bogdanm 87:6213f644d804 2385 #define I2S_TCR2_DIV_SHIFT 0
bogdanm 87:6213f644d804 2386 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
bogdanm 87:6213f644d804 2387 #define I2S_TCR2_BCD_MASK 0x1000000u
bogdanm 87:6213f644d804 2388 #define I2S_TCR2_BCD_SHIFT 24
bogdanm 87:6213f644d804 2389 #define I2S_TCR2_BCP_MASK 0x2000000u
bogdanm 87:6213f644d804 2390 #define I2S_TCR2_BCP_SHIFT 25
bogdanm 87:6213f644d804 2391 #define I2S_TCR2_MSEL_MASK 0xC000000u
bogdanm 87:6213f644d804 2392 #define I2S_TCR2_MSEL_SHIFT 26
bogdanm 87:6213f644d804 2393 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
bogdanm 87:6213f644d804 2394 #define I2S_TCR2_BCI_MASK 0x10000000u
bogdanm 87:6213f644d804 2395 #define I2S_TCR2_BCI_SHIFT 28
bogdanm 87:6213f644d804 2396 #define I2S_TCR2_BCS_MASK 0x20000000u
bogdanm 87:6213f644d804 2397 #define I2S_TCR2_BCS_SHIFT 29
bogdanm 87:6213f644d804 2398 #define I2S_TCR2_SYNC_MASK 0xC0000000u
bogdanm 87:6213f644d804 2399 #define I2S_TCR2_SYNC_SHIFT 30
bogdanm 87:6213f644d804 2400 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
bogdanm 87:6213f644d804 2401 /* TCR3 Bit Fields */
bogdanm 87:6213f644d804 2402 #define I2S_TCR3_WDFL_MASK 0x1Fu
bogdanm 87:6213f644d804 2403 #define I2S_TCR3_WDFL_SHIFT 0
bogdanm 87:6213f644d804 2404 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
bogdanm 87:6213f644d804 2405 #define I2S_TCR3_TCE_MASK 0x30000u
bogdanm 87:6213f644d804 2406 #define I2S_TCR3_TCE_SHIFT 16
bogdanm 87:6213f644d804 2407 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
bogdanm 87:6213f644d804 2408 /* TCR4 Bit Fields */
bogdanm 87:6213f644d804 2409 #define I2S_TCR4_FSD_MASK 0x1u
bogdanm 87:6213f644d804 2410 #define I2S_TCR4_FSD_SHIFT 0
bogdanm 87:6213f644d804 2411 #define I2S_TCR4_FSP_MASK 0x2u
bogdanm 87:6213f644d804 2412 #define I2S_TCR4_FSP_SHIFT 1
bogdanm 87:6213f644d804 2413 #define I2S_TCR4_FSE_MASK 0x8u
bogdanm 87:6213f644d804 2414 #define I2S_TCR4_FSE_SHIFT 3
bogdanm 87:6213f644d804 2415 #define I2S_TCR4_MF_MASK 0x10u
bogdanm 87:6213f644d804 2416 #define I2S_TCR4_MF_SHIFT 4
bogdanm 87:6213f644d804 2417 #define I2S_TCR4_SYWD_MASK 0x1F00u
bogdanm 87:6213f644d804 2418 #define I2S_TCR4_SYWD_SHIFT 8
bogdanm 87:6213f644d804 2419 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
bogdanm 87:6213f644d804 2420 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
bogdanm 87:6213f644d804 2421 #define I2S_TCR4_FRSZ_SHIFT 16
bogdanm 87:6213f644d804 2422 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
bogdanm 87:6213f644d804 2423 /* TCR5 Bit Fields */
bogdanm 87:6213f644d804 2424 #define I2S_TCR5_FBT_MASK 0x1F00u
bogdanm 87:6213f644d804 2425 #define I2S_TCR5_FBT_SHIFT 8
bogdanm 87:6213f644d804 2426 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
bogdanm 87:6213f644d804 2427 #define I2S_TCR5_W0W_MASK 0x1F0000u
bogdanm 87:6213f644d804 2428 #define I2S_TCR5_W0W_SHIFT 16
bogdanm 87:6213f644d804 2429 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
bogdanm 87:6213f644d804 2430 #define I2S_TCR5_WNW_MASK 0x1F000000u
bogdanm 87:6213f644d804 2431 #define I2S_TCR5_WNW_SHIFT 24
bogdanm 87:6213f644d804 2432 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
bogdanm 87:6213f644d804 2433 /* TDR Bit Fields */
bogdanm 87:6213f644d804 2434 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2435 #define I2S_TDR_TDR_SHIFT 0
bogdanm 87:6213f644d804 2436 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
bogdanm 87:6213f644d804 2437 /* TFR Bit Fields */
bogdanm 87:6213f644d804 2438 #define I2S_TFR_RFP_MASK 0xFu
bogdanm 87:6213f644d804 2439 #define I2S_TFR_RFP_SHIFT 0
bogdanm 87:6213f644d804 2440 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
bogdanm 87:6213f644d804 2441 #define I2S_TFR_WFP_MASK 0xF0000u
bogdanm 87:6213f644d804 2442 #define I2S_TFR_WFP_SHIFT 16
bogdanm 87:6213f644d804 2443 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
bogdanm 87:6213f644d804 2444 /* TMR Bit Fields */
bogdanm 87:6213f644d804 2445 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2446 #define I2S_TMR_TWM_SHIFT 0
bogdanm 87:6213f644d804 2447 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
bogdanm 87:6213f644d804 2448 /* RCSR Bit Fields */
bogdanm 87:6213f644d804 2449 #define I2S_RCSR_FRDE_MASK 0x1u
bogdanm 87:6213f644d804 2450 #define I2S_RCSR_FRDE_SHIFT 0
bogdanm 87:6213f644d804 2451 #define I2S_RCSR_FWDE_MASK 0x2u
bogdanm 87:6213f644d804 2452 #define I2S_RCSR_FWDE_SHIFT 1
bogdanm 87:6213f644d804 2453 #define I2S_RCSR_FRIE_MASK 0x100u
bogdanm 87:6213f644d804 2454 #define I2S_RCSR_FRIE_SHIFT 8
bogdanm 87:6213f644d804 2455 #define I2S_RCSR_FWIE_MASK 0x200u
bogdanm 87:6213f644d804 2456 #define I2S_RCSR_FWIE_SHIFT 9
bogdanm 87:6213f644d804 2457 #define I2S_RCSR_FEIE_MASK 0x400u
bogdanm 87:6213f644d804 2458 #define I2S_RCSR_FEIE_SHIFT 10
bogdanm 87:6213f644d804 2459 #define I2S_RCSR_SEIE_MASK 0x800u
bogdanm 87:6213f644d804 2460 #define I2S_RCSR_SEIE_SHIFT 11
bogdanm 87:6213f644d804 2461 #define I2S_RCSR_WSIE_MASK 0x1000u
bogdanm 87:6213f644d804 2462 #define I2S_RCSR_WSIE_SHIFT 12
bogdanm 87:6213f644d804 2463 #define I2S_RCSR_FRF_MASK 0x10000u
bogdanm 87:6213f644d804 2464 #define I2S_RCSR_FRF_SHIFT 16
bogdanm 87:6213f644d804 2465 #define I2S_RCSR_FWF_MASK 0x20000u
bogdanm 87:6213f644d804 2466 #define I2S_RCSR_FWF_SHIFT 17
bogdanm 87:6213f644d804 2467 #define I2S_RCSR_FEF_MASK 0x40000u
bogdanm 87:6213f644d804 2468 #define I2S_RCSR_FEF_SHIFT 18
bogdanm 87:6213f644d804 2469 #define I2S_RCSR_SEF_MASK 0x80000u
bogdanm 87:6213f644d804 2470 #define I2S_RCSR_SEF_SHIFT 19
bogdanm 87:6213f644d804 2471 #define I2S_RCSR_WSF_MASK 0x100000u
bogdanm 87:6213f644d804 2472 #define I2S_RCSR_WSF_SHIFT 20
bogdanm 87:6213f644d804 2473 #define I2S_RCSR_SR_MASK 0x1000000u
bogdanm 87:6213f644d804 2474 #define I2S_RCSR_SR_SHIFT 24
bogdanm 87:6213f644d804 2475 #define I2S_RCSR_FR_MASK 0x2000000u
bogdanm 87:6213f644d804 2476 #define I2S_RCSR_FR_SHIFT 25
bogdanm 87:6213f644d804 2477 #define I2S_RCSR_BCE_MASK 0x10000000u
bogdanm 87:6213f644d804 2478 #define I2S_RCSR_BCE_SHIFT 28
bogdanm 87:6213f644d804 2479 #define I2S_RCSR_DBGE_MASK 0x20000000u
bogdanm 87:6213f644d804 2480 #define I2S_RCSR_DBGE_SHIFT 29
bogdanm 87:6213f644d804 2481 #define I2S_RCSR_STOPE_MASK 0x40000000u
bogdanm 87:6213f644d804 2482 #define I2S_RCSR_STOPE_SHIFT 30
bogdanm 87:6213f644d804 2483 #define I2S_RCSR_RE_MASK 0x80000000u
bogdanm 87:6213f644d804 2484 #define I2S_RCSR_RE_SHIFT 31
bogdanm 87:6213f644d804 2485 /* RCR1 Bit Fields */
bogdanm 87:6213f644d804 2486 #define I2S_RCR1_RFW_MASK 0x7u
bogdanm 87:6213f644d804 2487 #define I2S_RCR1_RFW_SHIFT 0
bogdanm 87:6213f644d804 2488 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
bogdanm 87:6213f644d804 2489 /* RCR2 Bit Fields */
bogdanm 87:6213f644d804 2490 #define I2S_RCR2_DIV_MASK 0xFFu
bogdanm 87:6213f644d804 2491 #define I2S_RCR2_DIV_SHIFT 0
bogdanm 87:6213f644d804 2492 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
bogdanm 87:6213f644d804 2493 #define I2S_RCR2_BCD_MASK 0x1000000u
bogdanm 87:6213f644d804 2494 #define I2S_RCR2_BCD_SHIFT 24
bogdanm 87:6213f644d804 2495 #define I2S_RCR2_BCP_MASK 0x2000000u
bogdanm 87:6213f644d804 2496 #define I2S_RCR2_BCP_SHIFT 25
bogdanm 87:6213f644d804 2497 #define I2S_RCR2_MSEL_MASK 0xC000000u
bogdanm 87:6213f644d804 2498 #define I2S_RCR2_MSEL_SHIFT 26
bogdanm 87:6213f644d804 2499 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
bogdanm 87:6213f644d804 2500 #define I2S_RCR2_BCI_MASK 0x10000000u
bogdanm 87:6213f644d804 2501 #define I2S_RCR2_BCI_SHIFT 28
bogdanm 87:6213f644d804 2502 #define I2S_RCR2_BCS_MASK 0x20000000u
bogdanm 87:6213f644d804 2503 #define I2S_RCR2_BCS_SHIFT 29
bogdanm 87:6213f644d804 2504 #define I2S_RCR2_SYNC_MASK 0xC0000000u
bogdanm 87:6213f644d804 2505 #define I2S_RCR2_SYNC_SHIFT 30
bogdanm 87:6213f644d804 2506 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
bogdanm 87:6213f644d804 2507 /* RCR3 Bit Fields */
bogdanm 87:6213f644d804 2508 #define I2S_RCR3_WDFL_MASK 0x1Fu
bogdanm 87:6213f644d804 2509 #define I2S_RCR3_WDFL_SHIFT 0
bogdanm 87:6213f644d804 2510 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
bogdanm 87:6213f644d804 2511 #define I2S_RCR3_RCE_MASK 0x30000u
bogdanm 87:6213f644d804 2512 #define I2S_RCR3_RCE_SHIFT 16
bogdanm 87:6213f644d804 2513 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
bogdanm 87:6213f644d804 2514 /* RCR4 Bit Fields */
bogdanm 87:6213f644d804 2515 #define I2S_RCR4_FSD_MASK 0x1u
bogdanm 87:6213f644d804 2516 #define I2S_RCR4_FSD_SHIFT 0
bogdanm 87:6213f644d804 2517 #define I2S_RCR4_FSP_MASK 0x2u
bogdanm 87:6213f644d804 2518 #define I2S_RCR4_FSP_SHIFT 1
bogdanm 87:6213f644d804 2519 #define I2S_RCR4_FSE_MASK 0x8u
bogdanm 87:6213f644d804 2520 #define I2S_RCR4_FSE_SHIFT 3
bogdanm 87:6213f644d804 2521 #define I2S_RCR4_MF_MASK 0x10u
bogdanm 87:6213f644d804 2522 #define I2S_RCR4_MF_SHIFT 4
bogdanm 87:6213f644d804 2523 #define I2S_RCR4_SYWD_MASK 0x1F00u
bogdanm 87:6213f644d804 2524 #define I2S_RCR4_SYWD_SHIFT 8
bogdanm 87:6213f644d804 2525 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
bogdanm 87:6213f644d804 2526 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
bogdanm 87:6213f644d804 2527 #define I2S_RCR4_FRSZ_SHIFT 16
bogdanm 87:6213f644d804 2528 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
bogdanm 87:6213f644d804 2529 /* RCR5 Bit Fields */
bogdanm 87:6213f644d804 2530 #define I2S_RCR5_FBT_MASK 0x1F00u
bogdanm 87:6213f644d804 2531 #define I2S_RCR5_FBT_SHIFT 8
bogdanm 87:6213f644d804 2532 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
bogdanm 87:6213f644d804 2533 #define I2S_RCR5_W0W_MASK 0x1F0000u
bogdanm 87:6213f644d804 2534 #define I2S_RCR5_W0W_SHIFT 16
bogdanm 87:6213f644d804 2535 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
bogdanm 87:6213f644d804 2536 #define I2S_RCR5_WNW_MASK 0x1F000000u
bogdanm 87:6213f644d804 2537 #define I2S_RCR5_WNW_SHIFT 24
bogdanm 87:6213f644d804 2538 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
bogdanm 87:6213f644d804 2539 /* RDR Bit Fields */
bogdanm 87:6213f644d804 2540 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2541 #define I2S_RDR_RDR_SHIFT 0
bogdanm 87:6213f644d804 2542 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
bogdanm 87:6213f644d804 2543 /* RFR Bit Fields */
bogdanm 87:6213f644d804 2544 #define I2S_RFR_RFP_MASK 0xFu
bogdanm 87:6213f644d804 2545 #define I2S_RFR_RFP_SHIFT 0
bogdanm 87:6213f644d804 2546 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
bogdanm 87:6213f644d804 2547 #define I2S_RFR_WFP_MASK 0xF0000u
bogdanm 87:6213f644d804 2548 #define I2S_RFR_WFP_SHIFT 16
bogdanm 87:6213f644d804 2549 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
bogdanm 87:6213f644d804 2550 /* RMR Bit Fields */
bogdanm 87:6213f644d804 2551 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 2552 #define I2S_RMR_RWM_SHIFT 0
bogdanm 87:6213f644d804 2553 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
bogdanm 87:6213f644d804 2554 /* MCR Bit Fields */
bogdanm 87:6213f644d804 2555 #define I2S_MCR_MICS_MASK 0x3000000u
bogdanm 87:6213f644d804 2556 #define I2S_MCR_MICS_SHIFT 24
bogdanm 87:6213f644d804 2557 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
bogdanm 87:6213f644d804 2558 #define I2S_MCR_MOE_MASK 0x40000000u
bogdanm 87:6213f644d804 2559 #define I2S_MCR_MOE_SHIFT 30
bogdanm 87:6213f644d804 2560 #define I2S_MCR_DUF_MASK 0x80000000u
bogdanm 87:6213f644d804 2561 #define I2S_MCR_DUF_SHIFT 31
bogdanm 87:6213f644d804 2562 /* MDR Bit Fields */
bogdanm 87:6213f644d804 2563 #define I2S_MDR_DIVIDE_MASK 0xFFFu
bogdanm 87:6213f644d804 2564 #define I2S_MDR_DIVIDE_SHIFT 0
bogdanm 87:6213f644d804 2565 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
bogdanm 87:6213f644d804 2566 #define I2S_MDR_FRACT_MASK 0xFF000u
bogdanm 87:6213f644d804 2567 #define I2S_MDR_FRACT_SHIFT 12
bogdanm 87:6213f644d804 2568 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
bogdanm 87:6213f644d804 2569
bogdanm 87:6213f644d804 2570 /**
bogdanm 87:6213f644d804 2571 * @}
bogdanm 87:6213f644d804 2572 */ /* end of group I2S_Register_Masks */
bogdanm 87:6213f644d804 2573
bogdanm 87:6213f644d804 2574
bogdanm 87:6213f644d804 2575 /* I2S - Peripheral instance base addresses */
bogdanm 87:6213f644d804 2576 /** Peripheral I2S0 base address */
bogdanm 87:6213f644d804 2577 #define I2S0_BASE (0x4002F000u)
bogdanm 87:6213f644d804 2578 /** Peripheral I2S0 base pointer */
bogdanm 87:6213f644d804 2579 #define I2S0 ((I2S_Type *)I2S0_BASE)
bogdanm 87:6213f644d804 2580
bogdanm 87:6213f644d804 2581 /**
bogdanm 87:6213f644d804 2582 * @}
bogdanm 87:6213f644d804 2583 */ /* end of group I2S_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 2584
bogdanm 87:6213f644d804 2585
bogdanm 87:6213f644d804 2586 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2587 -- LLWU Peripheral Access Layer
bogdanm 87:6213f644d804 2588 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2589
bogdanm 87:6213f644d804 2590 /**
bogdanm 87:6213f644d804 2591 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
bogdanm 87:6213f644d804 2592 * @{
bogdanm 87:6213f644d804 2593 */
bogdanm 87:6213f644d804 2594
bogdanm 87:6213f644d804 2595 /** LLWU - Register Layout Typedef */
bogdanm 87:6213f644d804 2596 typedef struct {
bogdanm 87:6213f644d804 2597 __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
bogdanm 87:6213f644d804 2598 __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
bogdanm 87:6213f644d804 2599 __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
bogdanm 87:6213f644d804 2600 __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
bogdanm 87:6213f644d804 2601 __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
bogdanm 87:6213f644d804 2602 __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
bogdanm 87:6213f644d804 2603 __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
bogdanm 87:6213f644d804 2604 __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
bogdanm 87:6213f644d804 2605 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
bogdanm 87:6213f644d804 2606 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
bogdanm 87:6213f644d804 2607 __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
bogdanm 87:6213f644d804 2608 } LLWU_Type;
bogdanm 87:6213f644d804 2609
bogdanm 87:6213f644d804 2610 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2611 -- LLWU Register Masks
bogdanm 87:6213f644d804 2612 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2613
bogdanm 87:6213f644d804 2614 /**
bogdanm 87:6213f644d804 2615 * @addtogroup LLWU_Register_Masks LLWU Register Masks
bogdanm 87:6213f644d804 2616 * @{
bogdanm 87:6213f644d804 2617 */
bogdanm 87:6213f644d804 2618
bogdanm 87:6213f644d804 2619 /* PE1 Bit Fields */
bogdanm 87:6213f644d804 2620 #define LLWU_PE1_WUPE0_MASK 0x3u
bogdanm 87:6213f644d804 2621 #define LLWU_PE1_WUPE0_SHIFT 0
bogdanm 87:6213f644d804 2622 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
bogdanm 87:6213f644d804 2623 #define LLWU_PE1_WUPE1_MASK 0xCu
bogdanm 87:6213f644d804 2624 #define LLWU_PE1_WUPE1_SHIFT 2
bogdanm 87:6213f644d804 2625 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
bogdanm 87:6213f644d804 2626 #define LLWU_PE1_WUPE2_MASK 0x30u
bogdanm 87:6213f644d804 2627 #define LLWU_PE1_WUPE2_SHIFT 4
bogdanm 87:6213f644d804 2628 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
bogdanm 87:6213f644d804 2629 #define LLWU_PE1_WUPE3_MASK 0xC0u
bogdanm 87:6213f644d804 2630 #define LLWU_PE1_WUPE3_SHIFT 6
bogdanm 87:6213f644d804 2631 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
bogdanm 87:6213f644d804 2632 /* PE2 Bit Fields */
bogdanm 87:6213f644d804 2633 #define LLWU_PE2_WUPE4_MASK 0x3u
bogdanm 87:6213f644d804 2634 #define LLWU_PE2_WUPE4_SHIFT 0
bogdanm 87:6213f644d804 2635 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
bogdanm 87:6213f644d804 2636 #define LLWU_PE2_WUPE5_MASK 0xCu
bogdanm 87:6213f644d804 2637 #define LLWU_PE2_WUPE5_SHIFT 2
bogdanm 87:6213f644d804 2638 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
bogdanm 87:6213f644d804 2639 #define LLWU_PE2_WUPE6_MASK 0x30u
bogdanm 87:6213f644d804 2640 #define LLWU_PE2_WUPE6_SHIFT 4
bogdanm 87:6213f644d804 2641 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
bogdanm 87:6213f644d804 2642 #define LLWU_PE2_WUPE7_MASK 0xC0u
bogdanm 87:6213f644d804 2643 #define LLWU_PE2_WUPE7_SHIFT 6
bogdanm 87:6213f644d804 2644 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
bogdanm 87:6213f644d804 2645 /* PE3 Bit Fields */
bogdanm 87:6213f644d804 2646 #define LLWU_PE3_WUPE8_MASK 0x3u
bogdanm 87:6213f644d804 2647 #define LLWU_PE3_WUPE8_SHIFT 0
bogdanm 87:6213f644d804 2648 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
bogdanm 87:6213f644d804 2649 #define LLWU_PE3_WUPE9_MASK 0xCu
bogdanm 87:6213f644d804 2650 #define LLWU_PE3_WUPE9_SHIFT 2
bogdanm 87:6213f644d804 2651 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
bogdanm 87:6213f644d804 2652 #define LLWU_PE3_WUPE10_MASK 0x30u
bogdanm 87:6213f644d804 2653 #define LLWU_PE3_WUPE10_SHIFT 4
bogdanm 87:6213f644d804 2654 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
bogdanm 87:6213f644d804 2655 #define LLWU_PE3_WUPE11_MASK 0xC0u
bogdanm 87:6213f644d804 2656 #define LLWU_PE3_WUPE11_SHIFT 6
bogdanm 87:6213f644d804 2657 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
bogdanm 87:6213f644d804 2658 /* PE4 Bit Fields */
bogdanm 87:6213f644d804 2659 #define LLWU_PE4_WUPE12_MASK 0x3u
bogdanm 87:6213f644d804 2660 #define LLWU_PE4_WUPE12_SHIFT 0
bogdanm 87:6213f644d804 2661 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
bogdanm 87:6213f644d804 2662 #define LLWU_PE4_WUPE13_MASK 0xCu
bogdanm 87:6213f644d804 2663 #define LLWU_PE4_WUPE13_SHIFT 2
bogdanm 87:6213f644d804 2664 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
bogdanm 87:6213f644d804 2665 #define LLWU_PE4_WUPE14_MASK 0x30u
bogdanm 87:6213f644d804 2666 #define LLWU_PE4_WUPE14_SHIFT 4
bogdanm 87:6213f644d804 2667 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
bogdanm 87:6213f644d804 2668 #define LLWU_PE4_WUPE15_MASK 0xC0u
bogdanm 87:6213f644d804 2669 #define LLWU_PE4_WUPE15_SHIFT 6
bogdanm 87:6213f644d804 2670 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
bogdanm 87:6213f644d804 2671 /* ME Bit Fields */
bogdanm 87:6213f644d804 2672 #define LLWU_ME_WUME0_MASK 0x1u
bogdanm 87:6213f644d804 2673 #define LLWU_ME_WUME0_SHIFT 0
bogdanm 87:6213f644d804 2674 #define LLWU_ME_WUME1_MASK 0x2u
bogdanm 87:6213f644d804 2675 #define LLWU_ME_WUME1_SHIFT 1
bogdanm 87:6213f644d804 2676 #define LLWU_ME_WUME2_MASK 0x4u
bogdanm 87:6213f644d804 2677 #define LLWU_ME_WUME2_SHIFT 2
bogdanm 87:6213f644d804 2678 #define LLWU_ME_WUME3_MASK 0x8u
bogdanm 87:6213f644d804 2679 #define LLWU_ME_WUME3_SHIFT 3
bogdanm 87:6213f644d804 2680 #define LLWU_ME_WUME4_MASK 0x10u
bogdanm 87:6213f644d804 2681 #define LLWU_ME_WUME4_SHIFT 4
bogdanm 87:6213f644d804 2682 #define LLWU_ME_WUME5_MASK 0x20u
bogdanm 87:6213f644d804 2683 #define LLWU_ME_WUME5_SHIFT 5
bogdanm 87:6213f644d804 2684 #define LLWU_ME_WUME6_MASK 0x40u
bogdanm 87:6213f644d804 2685 #define LLWU_ME_WUME6_SHIFT 6
bogdanm 87:6213f644d804 2686 #define LLWU_ME_WUME7_MASK 0x80u
bogdanm 87:6213f644d804 2687 #define LLWU_ME_WUME7_SHIFT 7
bogdanm 87:6213f644d804 2688 /* F1 Bit Fields */
bogdanm 87:6213f644d804 2689 #define LLWU_F1_WUF0_MASK 0x1u
bogdanm 87:6213f644d804 2690 #define LLWU_F1_WUF0_SHIFT 0
bogdanm 87:6213f644d804 2691 #define LLWU_F1_WUF1_MASK 0x2u
bogdanm 87:6213f644d804 2692 #define LLWU_F1_WUF1_SHIFT 1
bogdanm 87:6213f644d804 2693 #define LLWU_F1_WUF2_MASK 0x4u
bogdanm 87:6213f644d804 2694 #define LLWU_F1_WUF2_SHIFT 2
bogdanm 87:6213f644d804 2695 #define LLWU_F1_WUF3_MASK 0x8u
bogdanm 87:6213f644d804 2696 #define LLWU_F1_WUF3_SHIFT 3
bogdanm 87:6213f644d804 2697 #define LLWU_F1_WUF4_MASK 0x10u
bogdanm 87:6213f644d804 2698 #define LLWU_F1_WUF4_SHIFT 4
bogdanm 87:6213f644d804 2699 #define LLWU_F1_WUF5_MASK 0x20u
bogdanm 87:6213f644d804 2700 #define LLWU_F1_WUF5_SHIFT 5
bogdanm 87:6213f644d804 2701 #define LLWU_F1_WUF6_MASK 0x40u
bogdanm 87:6213f644d804 2702 #define LLWU_F1_WUF6_SHIFT 6
bogdanm 87:6213f644d804 2703 #define LLWU_F1_WUF7_MASK 0x80u
bogdanm 87:6213f644d804 2704 #define LLWU_F1_WUF7_SHIFT 7
bogdanm 87:6213f644d804 2705 /* F2 Bit Fields */
bogdanm 87:6213f644d804 2706 #define LLWU_F2_WUF8_MASK 0x1u
bogdanm 87:6213f644d804 2707 #define LLWU_F2_WUF8_SHIFT 0
bogdanm 87:6213f644d804 2708 #define LLWU_F2_WUF9_MASK 0x2u
bogdanm 87:6213f644d804 2709 #define LLWU_F2_WUF9_SHIFT 1
bogdanm 87:6213f644d804 2710 #define LLWU_F2_WUF10_MASK 0x4u
bogdanm 87:6213f644d804 2711 #define LLWU_F2_WUF10_SHIFT 2
bogdanm 87:6213f644d804 2712 #define LLWU_F2_WUF11_MASK 0x8u
bogdanm 87:6213f644d804 2713 #define LLWU_F2_WUF11_SHIFT 3
bogdanm 87:6213f644d804 2714 #define LLWU_F2_WUF12_MASK 0x10u
bogdanm 87:6213f644d804 2715 #define LLWU_F2_WUF12_SHIFT 4
bogdanm 87:6213f644d804 2716 #define LLWU_F2_WUF13_MASK 0x20u
bogdanm 87:6213f644d804 2717 #define LLWU_F2_WUF13_SHIFT 5
bogdanm 87:6213f644d804 2718 #define LLWU_F2_WUF14_MASK 0x40u
bogdanm 87:6213f644d804 2719 #define LLWU_F2_WUF14_SHIFT 6
bogdanm 87:6213f644d804 2720 #define LLWU_F2_WUF15_MASK 0x80u
bogdanm 87:6213f644d804 2721 #define LLWU_F2_WUF15_SHIFT 7
bogdanm 87:6213f644d804 2722 /* F3 Bit Fields */
bogdanm 87:6213f644d804 2723 #define LLWU_F3_MWUF0_MASK 0x1u
bogdanm 87:6213f644d804 2724 #define LLWU_F3_MWUF0_SHIFT 0
bogdanm 87:6213f644d804 2725 #define LLWU_F3_MWUF1_MASK 0x2u
bogdanm 87:6213f644d804 2726 #define LLWU_F3_MWUF1_SHIFT 1
bogdanm 87:6213f644d804 2727 #define LLWU_F3_MWUF2_MASK 0x4u
bogdanm 87:6213f644d804 2728 #define LLWU_F3_MWUF2_SHIFT 2
bogdanm 87:6213f644d804 2729 #define LLWU_F3_MWUF3_MASK 0x8u
bogdanm 87:6213f644d804 2730 #define LLWU_F3_MWUF3_SHIFT 3
bogdanm 87:6213f644d804 2731 #define LLWU_F3_MWUF4_MASK 0x10u
bogdanm 87:6213f644d804 2732 #define LLWU_F3_MWUF4_SHIFT 4
bogdanm 87:6213f644d804 2733 #define LLWU_F3_MWUF5_MASK 0x20u
bogdanm 87:6213f644d804 2734 #define LLWU_F3_MWUF5_SHIFT 5
bogdanm 87:6213f644d804 2735 #define LLWU_F3_MWUF6_MASK 0x40u
bogdanm 87:6213f644d804 2736 #define LLWU_F3_MWUF6_SHIFT 6
bogdanm 87:6213f644d804 2737 #define LLWU_F3_MWUF7_MASK 0x80u
bogdanm 87:6213f644d804 2738 #define LLWU_F3_MWUF7_SHIFT 7
bogdanm 87:6213f644d804 2739 /* FILT1 Bit Fields */
bogdanm 87:6213f644d804 2740 #define LLWU_FILT1_FILTSEL_MASK 0xFu
bogdanm 87:6213f644d804 2741 #define LLWU_FILT1_FILTSEL_SHIFT 0
bogdanm 87:6213f644d804 2742 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
bogdanm 87:6213f644d804 2743 #define LLWU_FILT1_FILTE_MASK 0x60u
bogdanm 87:6213f644d804 2744 #define LLWU_FILT1_FILTE_SHIFT 5
bogdanm 87:6213f644d804 2745 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
bogdanm 87:6213f644d804 2746 #define LLWU_FILT1_FILTF_MASK 0x80u
bogdanm 87:6213f644d804 2747 #define LLWU_FILT1_FILTF_SHIFT 7
bogdanm 87:6213f644d804 2748 /* FILT2 Bit Fields */
bogdanm 87:6213f644d804 2749 #define LLWU_FILT2_FILTSEL_MASK 0xFu
bogdanm 87:6213f644d804 2750 #define LLWU_FILT2_FILTSEL_SHIFT 0
bogdanm 87:6213f644d804 2751 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
bogdanm 87:6213f644d804 2752 #define LLWU_FILT2_FILTE_MASK 0x60u
bogdanm 87:6213f644d804 2753 #define LLWU_FILT2_FILTE_SHIFT 5
bogdanm 87:6213f644d804 2754 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
bogdanm 87:6213f644d804 2755 #define LLWU_FILT2_FILTF_MASK 0x80u
bogdanm 87:6213f644d804 2756 #define LLWU_FILT2_FILTF_SHIFT 7
bogdanm 87:6213f644d804 2757 /* RST Bit Fields */
bogdanm 87:6213f644d804 2758 #define LLWU_RST_RSTFILT_MASK 0x1u
bogdanm 87:6213f644d804 2759 #define LLWU_RST_RSTFILT_SHIFT 0
bogdanm 87:6213f644d804 2760 #define LLWU_RST_LLRSTE_MASK 0x2u
bogdanm 87:6213f644d804 2761 #define LLWU_RST_LLRSTE_SHIFT 1
bogdanm 87:6213f644d804 2762
bogdanm 87:6213f644d804 2763 /**
bogdanm 87:6213f644d804 2764 * @}
bogdanm 87:6213f644d804 2765 */ /* end of group LLWU_Register_Masks */
bogdanm 87:6213f644d804 2766
bogdanm 87:6213f644d804 2767
bogdanm 87:6213f644d804 2768 /* LLWU - Peripheral instance base addresses */
bogdanm 87:6213f644d804 2769 /** Peripheral LLWU base address */
bogdanm 87:6213f644d804 2770 #define LLWU_BASE (0x4007C000u)
bogdanm 87:6213f644d804 2771 /** Peripheral LLWU base pointer */
bogdanm 87:6213f644d804 2772 #define LLWU ((LLWU_Type *)LLWU_BASE)
bogdanm 87:6213f644d804 2773
bogdanm 87:6213f644d804 2774 /**
bogdanm 87:6213f644d804 2775 * @}
bogdanm 87:6213f644d804 2776 */ /* end of group LLWU_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 2777
bogdanm 87:6213f644d804 2778
bogdanm 87:6213f644d804 2779 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2780 -- LPTMR Peripheral Access Layer
bogdanm 87:6213f644d804 2781 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2782
bogdanm 87:6213f644d804 2783 /**
bogdanm 87:6213f644d804 2784 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
bogdanm 87:6213f644d804 2785 * @{
bogdanm 87:6213f644d804 2786 */
bogdanm 87:6213f644d804 2787
bogdanm 87:6213f644d804 2788 /** LPTMR - Register Layout Typedef */
bogdanm 87:6213f644d804 2789 typedef struct {
bogdanm 87:6213f644d804 2790 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
bogdanm 87:6213f644d804 2791 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
bogdanm 87:6213f644d804 2792 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
bogdanm 87:6213f644d804 2793 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
bogdanm 87:6213f644d804 2794 } LPTMR_Type;
bogdanm 87:6213f644d804 2795
bogdanm 87:6213f644d804 2796 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2797 -- LPTMR Register Masks
bogdanm 87:6213f644d804 2798 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2799
bogdanm 87:6213f644d804 2800 /**
bogdanm 87:6213f644d804 2801 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
bogdanm 87:6213f644d804 2802 * @{
bogdanm 87:6213f644d804 2803 */
bogdanm 87:6213f644d804 2804
bogdanm 87:6213f644d804 2805 /* CSR Bit Fields */
bogdanm 87:6213f644d804 2806 #define LPTMR_CSR_TEN_MASK 0x1u
bogdanm 87:6213f644d804 2807 #define LPTMR_CSR_TEN_SHIFT 0
bogdanm 87:6213f644d804 2808 #define LPTMR_CSR_TMS_MASK 0x2u
bogdanm 87:6213f644d804 2809 #define LPTMR_CSR_TMS_SHIFT 1
bogdanm 87:6213f644d804 2810 #define LPTMR_CSR_TFC_MASK 0x4u
bogdanm 87:6213f644d804 2811 #define LPTMR_CSR_TFC_SHIFT 2
bogdanm 87:6213f644d804 2812 #define LPTMR_CSR_TPP_MASK 0x8u
bogdanm 87:6213f644d804 2813 #define LPTMR_CSR_TPP_SHIFT 3
bogdanm 87:6213f644d804 2814 #define LPTMR_CSR_TPS_MASK 0x30u
bogdanm 87:6213f644d804 2815 #define LPTMR_CSR_TPS_SHIFT 4
bogdanm 87:6213f644d804 2816 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
bogdanm 87:6213f644d804 2817 #define LPTMR_CSR_TIE_MASK 0x40u
bogdanm 87:6213f644d804 2818 #define LPTMR_CSR_TIE_SHIFT 6
bogdanm 87:6213f644d804 2819 #define LPTMR_CSR_TCF_MASK 0x80u
bogdanm 87:6213f644d804 2820 #define LPTMR_CSR_TCF_SHIFT 7
bogdanm 87:6213f644d804 2821 /* PSR Bit Fields */
bogdanm 87:6213f644d804 2822 #define LPTMR_PSR_PCS_MASK 0x3u
bogdanm 87:6213f644d804 2823 #define LPTMR_PSR_PCS_SHIFT 0
bogdanm 87:6213f644d804 2824 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
bogdanm 87:6213f644d804 2825 #define LPTMR_PSR_PBYP_MASK 0x4u
bogdanm 87:6213f644d804 2826 #define LPTMR_PSR_PBYP_SHIFT 2
bogdanm 87:6213f644d804 2827 #define LPTMR_PSR_PRESCALE_MASK 0x78u
bogdanm 87:6213f644d804 2828 #define LPTMR_PSR_PRESCALE_SHIFT 3
bogdanm 87:6213f644d804 2829 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
bogdanm 87:6213f644d804 2830 /* CMR Bit Fields */
bogdanm 87:6213f644d804 2831 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
bogdanm 87:6213f644d804 2832 #define LPTMR_CMR_COMPARE_SHIFT 0
bogdanm 87:6213f644d804 2833 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
bogdanm 87:6213f644d804 2834 /* CNR Bit Fields */
bogdanm 87:6213f644d804 2835 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
bogdanm 87:6213f644d804 2836 #define LPTMR_CNR_COUNTER_SHIFT 0
bogdanm 87:6213f644d804 2837 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
bogdanm 87:6213f644d804 2838
bogdanm 87:6213f644d804 2839 /**
bogdanm 87:6213f644d804 2840 * @}
bogdanm 87:6213f644d804 2841 */ /* end of group LPTMR_Register_Masks */
bogdanm 87:6213f644d804 2842
bogdanm 87:6213f644d804 2843
bogdanm 87:6213f644d804 2844 /* LPTMR - Peripheral instance base addresses */
bogdanm 87:6213f644d804 2845 /** Peripheral LPTMR0 base address */
bogdanm 87:6213f644d804 2846 #define LPTMR0_BASE (0x40040000u)
bogdanm 87:6213f644d804 2847 /** Peripheral LPTMR0 base pointer */
bogdanm 87:6213f644d804 2848 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
bogdanm 87:6213f644d804 2849
bogdanm 87:6213f644d804 2850 /**
bogdanm 87:6213f644d804 2851 * @}
bogdanm 87:6213f644d804 2852 */ /* end of group LPTMR_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 2853
bogdanm 87:6213f644d804 2854
bogdanm 87:6213f644d804 2855 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2856 -- MCG Peripheral Access Layer
bogdanm 87:6213f644d804 2857 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2858
bogdanm 87:6213f644d804 2859 /**
bogdanm 87:6213f644d804 2860 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
bogdanm 87:6213f644d804 2861 * @{
bogdanm 87:6213f644d804 2862 */
bogdanm 87:6213f644d804 2863
bogdanm 87:6213f644d804 2864 /** MCG - Register Layout Typedef */
bogdanm 87:6213f644d804 2865 typedef struct {
bogdanm 87:6213f644d804 2866 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
bogdanm 87:6213f644d804 2867 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
bogdanm 87:6213f644d804 2868 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
bogdanm 87:6213f644d804 2869 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
bogdanm 87:6213f644d804 2870 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
bogdanm 87:6213f644d804 2871 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
bogdanm 87:6213f644d804 2872 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
bogdanm 87:6213f644d804 2873 uint8_t RESERVED_0[1];
bogdanm 87:6213f644d804 2874 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
bogdanm 87:6213f644d804 2875 uint8_t RESERVED_1[1];
bogdanm 87:6213f644d804 2876 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
bogdanm 87:6213f644d804 2877 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
bogdanm 87:6213f644d804 2878 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
bogdanm 87:6213f644d804 2879 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
bogdanm 87:6213f644d804 2880 } MCG_Type;
bogdanm 87:6213f644d804 2881
bogdanm 87:6213f644d804 2882 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 2883 -- MCG Register Masks
bogdanm 87:6213f644d804 2884 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 2885
bogdanm 87:6213f644d804 2886 /**
bogdanm 87:6213f644d804 2887 * @addtogroup MCG_Register_Masks MCG Register Masks
bogdanm 87:6213f644d804 2888 * @{
bogdanm 87:6213f644d804 2889 */
bogdanm 87:6213f644d804 2890
bogdanm 87:6213f644d804 2891 /* C1 Bit Fields */
bogdanm 87:6213f644d804 2892 #define MCG_C1_IREFSTEN_MASK 0x1u
bogdanm 87:6213f644d804 2893 #define MCG_C1_IREFSTEN_SHIFT 0
bogdanm 87:6213f644d804 2894 #define MCG_C1_IRCLKEN_MASK 0x2u
bogdanm 87:6213f644d804 2895 #define MCG_C1_IRCLKEN_SHIFT 1
bogdanm 87:6213f644d804 2896 #define MCG_C1_IREFS_MASK 0x4u
bogdanm 87:6213f644d804 2897 #define MCG_C1_IREFS_SHIFT 2
bogdanm 87:6213f644d804 2898 #define MCG_C1_FRDIV_MASK 0x38u
bogdanm 87:6213f644d804 2899 #define MCG_C1_FRDIV_SHIFT 3
bogdanm 87:6213f644d804 2900 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
bogdanm 87:6213f644d804 2901 #define MCG_C1_CLKS_MASK 0xC0u
bogdanm 87:6213f644d804 2902 #define MCG_C1_CLKS_SHIFT 6
bogdanm 87:6213f644d804 2903 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
bogdanm 87:6213f644d804 2904 /* C2 Bit Fields */
bogdanm 87:6213f644d804 2905 #define MCG_C2_IRCS_MASK 0x1u
bogdanm 87:6213f644d804 2906 #define MCG_C2_IRCS_SHIFT 0
bogdanm 87:6213f644d804 2907 #define MCG_C2_LP_MASK 0x2u
bogdanm 87:6213f644d804 2908 #define MCG_C2_LP_SHIFT 1
bogdanm 87:6213f644d804 2909 #define MCG_C2_EREFS0_MASK 0x4u
bogdanm 87:6213f644d804 2910 #define MCG_C2_EREFS0_SHIFT 2
bogdanm 87:6213f644d804 2911 #define MCG_C2_HGO0_MASK 0x8u
bogdanm 87:6213f644d804 2912 #define MCG_C2_HGO0_SHIFT 3
bogdanm 87:6213f644d804 2913 #define MCG_C2_RANGE0_MASK 0x30u
bogdanm 87:6213f644d804 2914 #define MCG_C2_RANGE0_SHIFT 4
bogdanm 87:6213f644d804 2915 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
bogdanm 87:6213f644d804 2916 #define MCG_C2_LOCRE0_MASK 0x80u
bogdanm 87:6213f644d804 2917 #define MCG_C2_LOCRE0_SHIFT 7
bogdanm 87:6213f644d804 2918 /* C3 Bit Fields */
bogdanm 87:6213f644d804 2919 #define MCG_C3_SCTRIM_MASK 0xFFu
bogdanm 87:6213f644d804 2920 #define MCG_C3_SCTRIM_SHIFT 0
bogdanm 87:6213f644d804 2921 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
bogdanm 87:6213f644d804 2922 /* C4 Bit Fields */
bogdanm 87:6213f644d804 2923 #define MCG_C4_SCFTRIM_MASK 0x1u
bogdanm 87:6213f644d804 2924 #define MCG_C4_SCFTRIM_SHIFT 0
bogdanm 87:6213f644d804 2925 #define MCG_C4_FCTRIM_MASK 0x1Eu
bogdanm 87:6213f644d804 2926 #define MCG_C4_FCTRIM_SHIFT 1
bogdanm 87:6213f644d804 2927 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
bogdanm 87:6213f644d804 2928 #define MCG_C4_DRST_DRS_MASK 0x60u
bogdanm 87:6213f644d804 2929 #define MCG_C4_DRST_DRS_SHIFT 5
bogdanm 87:6213f644d804 2930 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
bogdanm 87:6213f644d804 2931 #define MCG_C4_DMX32_MASK 0x80u
bogdanm 87:6213f644d804 2932 #define MCG_C4_DMX32_SHIFT 7
bogdanm 87:6213f644d804 2933 /* C5 Bit Fields */
bogdanm 87:6213f644d804 2934 #define MCG_C5_PRDIV0_MASK 0x1Fu
bogdanm 87:6213f644d804 2935 #define MCG_C5_PRDIV0_SHIFT 0
bogdanm 87:6213f644d804 2936 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
bogdanm 87:6213f644d804 2937 #define MCG_C5_PLLSTEN0_MASK 0x20u
bogdanm 87:6213f644d804 2938 #define MCG_C5_PLLSTEN0_SHIFT 5
bogdanm 87:6213f644d804 2939 #define MCG_C5_PLLCLKEN0_MASK 0x40u
bogdanm 87:6213f644d804 2940 #define MCG_C5_PLLCLKEN0_SHIFT 6
bogdanm 87:6213f644d804 2941 /* C6 Bit Fields */
bogdanm 87:6213f644d804 2942 #define MCG_C6_VDIV0_MASK 0x1Fu
bogdanm 87:6213f644d804 2943 #define MCG_C6_VDIV0_SHIFT 0
bogdanm 87:6213f644d804 2944 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
bogdanm 87:6213f644d804 2945 #define MCG_C6_CME0_MASK 0x20u
bogdanm 87:6213f644d804 2946 #define MCG_C6_CME0_SHIFT 5
bogdanm 87:6213f644d804 2947 #define MCG_C6_PLLS_MASK 0x40u
bogdanm 87:6213f644d804 2948 #define MCG_C6_PLLS_SHIFT 6
bogdanm 87:6213f644d804 2949 #define MCG_C6_LOLIE0_MASK 0x80u
bogdanm 87:6213f644d804 2950 #define MCG_C6_LOLIE0_SHIFT 7
bogdanm 87:6213f644d804 2951 /* S Bit Fields */
bogdanm 87:6213f644d804 2952 #define MCG_S_IRCST_MASK 0x1u
bogdanm 87:6213f644d804 2953 #define MCG_S_IRCST_SHIFT 0
bogdanm 87:6213f644d804 2954 #define MCG_S_OSCINIT0_MASK 0x2u
bogdanm 87:6213f644d804 2955 #define MCG_S_OSCINIT0_SHIFT 1
bogdanm 87:6213f644d804 2956 #define MCG_S_CLKST_MASK 0xCu
bogdanm 87:6213f644d804 2957 #define MCG_S_CLKST_SHIFT 2
bogdanm 87:6213f644d804 2958 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
bogdanm 87:6213f644d804 2959 #define MCG_S_IREFST_MASK 0x10u
bogdanm 87:6213f644d804 2960 #define MCG_S_IREFST_SHIFT 4
bogdanm 87:6213f644d804 2961 #define MCG_S_PLLST_MASK 0x20u
bogdanm 87:6213f644d804 2962 #define MCG_S_PLLST_SHIFT 5
bogdanm 87:6213f644d804 2963 #define MCG_S_LOCK0_MASK 0x40u
bogdanm 87:6213f644d804 2964 #define MCG_S_LOCK0_SHIFT 6
bogdanm 87:6213f644d804 2965 #define MCG_S_LOLS0_MASK 0x80u
bogdanm 87:6213f644d804 2966 #define MCG_S_LOLS0_SHIFT 7
bogdanm 87:6213f644d804 2967 /* SC Bit Fields */
bogdanm 87:6213f644d804 2968 #define MCG_SC_LOCS0_MASK 0x1u
bogdanm 87:6213f644d804 2969 #define MCG_SC_LOCS0_SHIFT 0
bogdanm 87:6213f644d804 2970 #define MCG_SC_FCRDIV_MASK 0xEu
bogdanm 87:6213f644d804 2971 #define MCG_SC_FCRDIV_SHIFT 1
bogdanm 87:6213f644d804 2972 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
bogdanm 87:6213f644d804 2973 #define MCG_SC_FLTPRSRV_MASK 0x10u
bogdanm 87:6213f644d804 2974 #define MCG_SC_FLTPRSRV_SHIFT 4
bogdanm 87:6213f644d804 2975 #define MCG_SC_ATMF_MASK 0x20u
bogdanm 87:6213f644d804 2976 #define MCG_SC_ATMF_SHIFT 5
bogdanm 87:6213f644d804 2977 #define MCG_SC_ATMS_MASK 0x40u
bogdanm 87:6213f644d804 2978 #define MCG_SC_ATMS_SHIFT 6
bogdanm 87:6213f644d804 2979 #define MCG_SC_ATME_MASK 0x80u
bogdanm 87:6213f644d804 2980 #define MCG_SC_ATME_SHIFT 7
bogdanm 87:6213f644d804 2981 /* ATCVH Bit Fields */
bogdanm 87:6213f644d804 2982 #define MCG_ATCVH_ATCVH_MASK 0xFFu
bogdanm 87:6213f644d804 2983 #define MCG_ATCVH_ATCVH_SHIFT 0
bogdanm 87:6213f644d804 2984 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
bogdanm 87:6213f644d804 2985 /* ATCVL Bit Fields */
bogdanm 87:6213f644d804 2986 #define MCG_ATCVL_ATCVL_MASK 0xFFu
bogdanm 87:6213f644d804 2987 #define MCG_ATCVL_ATCVL_SHIFT 0
bogdanm 87:6213f644d804 2988 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
bogdanm 87:6213f644d804 2989 /* C7 Bit Fields */
bogdanm 87:6213f644d804 2990 #define MCG_C7_OSCSEL_MASK 0x1u
bogdanm 87:6213f644d804 2991 #define MCG_C7_OSCSEL_SHIFT 0
bogdanm 87:6213f644d804 2992 /* C8 Bit Fields */
bogdanm 87:6213f644d804 2993 #define MCG_C8_LOCS1_MASK 0x1u
bogdanm 87:6213f644d804 2994 #define MCG_C8_LOCS1_SHIFT 0
bogdanm 87:6213f644d804 2995 #define MCG_C8_CME1_MASK 0x20u
bogdanm 87:6213f644d804 2996 #define MCG_C8_CME1_SHIFT 5
bogdanm 87:6213f644d804 2997 #define MCG_C8_LOLRE_MASK 0x40u
bogdanm 87:6213f644d804 2998 #define MCG_C8_LOLRE_SHIFT 6
bogdanm 87:6213f644d804 2999 #define MCG_C8_LOCRE1_MASK 0x80u
bogdanm 87:6213f644d804 3000 #define MCG_C8_LOCRE1_SHIFT 7
bogdanm 87:6213f644d804 3001
bogdanm 87:6213f644d804 3002 /**
bogdanm 87:6213f644d804 3003 * @}
bogdanm 87:6213f644d804 3004 */ /* end of group MCG_Register_Masks */
bogdanm 87:6213f644d804 3005
bogdanm 87:6213f644d804 3006
bogdanm 87:6213f644d804 3007 /* MCG - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3008 /** Peripheral MCG base address */
bogdanm 87:6213f644d804 3009 #define MCG_BASE (0x40064000u)
bogdanm 87:6213f644d804 3010 /** Peripheral MCG base pointer */
bogdanm 87:6213f644d804 3011 #define MCG ((MCG_Type *)MCG_BASE)
bogdanm 87:6213f644d804 3012
bogdanm 87:6213f644d804 3013 /**
bogdanm 87:6213f644d804 3014 * @}
bogdanm 87:6213f644d804 3015 */ /* end of group MCG_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3016
bogdanm 87:6213f644d804 3017
bogdanm 87:6213f644d804 3018 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3019 -- NV Peripheral Access Layer
bogdanm 87:6213f644d804 3020 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3021
bogdanm 87:6213f644d804 3022 /**
bogdanm 87:6213f644d804 3023 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
bogdanm 87:6213f644d804 3024 * @{
bogdanm 87:6213f644d804 3025 */
bogdanm 87:6213f644d804 3026
bogdanm 87:6213f644d804 3027 /** NV - Register Layout Typedef */
bogdanm 87:6213f644d804 3028 typedef struct {
bogdanm 87:6213f644d804 3029 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
bogdanm 87:6213f644d804 3030 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
bogdanm 87:6213f644d804 3031 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
bogdanm 87:6213f644d804 3032 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
bogdanm 87:6213f644d804 3033 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
bogdanm 87:6213f644d804 3034 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
bogdanm 87:6213f644d804 3035 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
bogdanm 87:6213f644d804 3036 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
bogdanm 87:6213f644d804 3037 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
bogdanm 87:6213f644d804 3038 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
bogdanm 87:6213f644d804 3039 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
bogdanm 87:6213f644d804 3040 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
bogdanm 87:6213f644d804 3041 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
bogdanm 87:6213f644d804 3042 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
bogdanm 87:6213f644d804 3043 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
bogdanm 87:6213f644d804 3044 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
bogdanm 87:6213f644d804 3045 } NV_Type;
bogdanm 87:6213f644d804 3046
bogdanm 87:6213f644d804 3047 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3048 -- NV Register Masks
bogdanm 87:6213f644d804 3049 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3050
bogdanm 87:6213f644d804 3051 /**
bogdanm 87:6213f644d804 3052 * @addtogroup NV_Register_Masks NV Register Masks
bogdanm 87:6213f644d804 3053 * @{
bogdanm 87:6213f644d804 3054 */
bogdanm 87:6213f644d804 3055
bogdanm 87:6213f644d804 3056 /* BACKKEY3 Bit Fields */
bogdanm 87:6213f644d804 3057 #define NV_BACKKEY3_KEY_MASK 0xFFu
bogdanm 87:6213f644d804 3058 #define NV_BACKKEY3_KEY_SHIFT 0
bogdanm 87:6213f644d804 3059 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
bogdanm 87:6213f644d804 3060 /* BACKKEY2 Bit Fields */
bogdanm 87:6213f644d804 3061 #define NV_BACKKEY2_KEY_MASK 0xFFu
bogdanm 87:6213f644d804 3062 #define NV_BACKKEY2_KEY_SHIFT 0
bogdanm 87:6213f644d804 3063 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
bogdanm 87:6213f644d804 3064 /* BACKKEY1 Bit Fields */
bogdanm 87:6213f644d804 3065 #define NV_BACKKEY1_KEY_MASK 0xFFu
bogdanm 87:6213f644d804 3066 #define NV_BACKKEY1_KEY_SHIFT 0
bogdanm 87:6213f644d804 3067 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
bogdanm 87:6213f644d804 3068 /* BACKKEY0 Bit Fields */
bogdanm 87:6213f644d804 3069 #define NV_BACKKEY0_KEY_MASK 0xFFu
bogdanm 87:6213f644d804 3070 #define NV_BACKKEY0_KEY_SHIFT 0
bogdanm 87:6213f644d804 3071 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
bogdanm 87:6213f644d804 3072 /* BACKKEY7 Bit Fields */
bogdanm 87:6213f644d804 3073 #define NV_BACKKEY7_KEY_MASK 0xFFu
bogdanm 87:6213f644d804 3074 #define NV_BACKKEY7_KEY_SHIFT 0
bogdanm 87:6213f644d804 3075 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
bogdanm 87:6213f644d804 3076 /* BACKKEY6 Bit Fields */
bogdanm 87:6213f644d804 3077 #define NV_BACKKEY6_KEY_MASK 0xFFu
bogdanm 87:6213f644d804 3078 #define NV_BACKKEY6_KEY_SHIFT 0
bogdanm 87:6213f644d804 3079 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
bogdanm 87:6213f644d804 3080 /* BACKKEY5 Bit Fields */
bogdanm 87:6213f644d804 3081 #define NV_BACKKEY5_KEY_MASK 0xFFu
bogdanm 87:6213f644d804 3082 #define NV_BACKKEY5_KEY_SHIFT 0
bogdanm 87:6213f644d804 3083 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
bogdanm 87:6213f644d804 3084 /* BACKKEY4 Bit Fields */
bogdanm 87:6213f644d804 3085 #define NV_BACKKEY4_KEY_MASK 0xFFu
bogdanm 87:6213f644d804 3086 #define NV_BACKKEY4_KEY_SHIFT 0
bogdanm 87:6213f644d804 3087 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
bogdanm 87:6213f644d804 3088 /* FPROT3 Bit Fields */
bogdanm 87:6213f644d804 3089 #define NV_FPROT3_PROT_MASK 0xFFu
bogdanm 87:6213f644d804 3090 #define NV_FPROT3_PROT_SHIFT 0
bogdanm 87:6213f644d804 3091 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
bogdanm 87:6213f644d804 3092 /* FPROT2 Bit Fields */
bogdanm 87:6213f644d804 3093 #define NV_FPROT2_PROT_MASK 0xFFu
bogdanm 87:6213f644d804 3094 #define NV_FPROT2_PROT_SHIFT 0
bogdanm 87:6213f644d804 3095 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
bogdanm 87:6213f644d804 3096 /* FPROT1 Bit Fields */
bogdanm 87:6213f644d804 3097 #define NV_FPROT1_PROT_MASK 0xFFu
bogdanm 87:6213f644d804 3098 #define NV_FPROT1_PROT_SHIFT 0
bogdanm 87:6213f644d804 3099 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
bogdanm 87:6213f644d804 3100 /* FPROT0 Bit Fields */
bogdanm 87:6213f644d804 3101 #define NV_FPROT0_PROT_MASK 0xFFu
bogdanm 87:6213f644d804 3102 #define NV_FPROT0_PROT_SHIFT 0
bogdanm 87:6213f644d804 3103 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
bogdanm 87:6213f644d804 3104 /* FSEC Bit Fields */
bogdanm 87:6213f644d804 3105 #define NV_FSEC_SEC_MASK 0x3u
bogdanm 87:6213f644d804 3106 #define NV_FSEC_SEC_SHIFT 0
bogdanm 87:6213f644d804 3107 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
bogdanm 87:6213f644d804 3108 #define NV_FSEC_FSLACC_MASK 0xCu
bogdanm 87:6213f644d804 3109 #define NV_FSEC_FSLACC_SHIFT 2
bogdanm 87:6213f644d804 3110 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
bogdanm 87:6213f644d804 3111 #define NV_FSEC_MEEN_MASK 0x30u
bogdanm 87:6213f644d804 3112 #define NV_FSEC_MEEN_SHIFT 4
bogdanm 87:6213f644d804 3113 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
bogdanm 87:6213f644d804 3114 #define NV_FSEC_KEYEN_MASK 0xC0u
bogdanm 87:6213f644d804 3115 #define NV_FSEC_KEYEN_SHIFT 6
bogdanm 87:6213f644d804 3116 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
bogdanm 87:6213f644d804 3117 /* FOPT Bit Fields */
bogdanm 87:6213f644d804 3118 #define NV_FOPT_LPBOOT_MASK 0x1u
bogdanm 87:6213f644d804 3119 #define NV_FOPT_LPBOOT_SHIFT 0
bogdanm 87:6213f644d804 3120 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
bogdanm 87:6213f644d804 3121 #define NV_FOPT_EZPORT_DIS_SHIFT 1
bogdanm 87:6213f644d804 3122 /* FEPROT Bit Fields */
bogdanm 87:6213f644d804 3123 #define NV_FEPROT_EPROT_MASK 0xFFu
bogdanm 87:6213f644d804 3124 #define NV_FEPROT_EPROT_SHIFT 0
bogdanm 87:6213f644d804 3125 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
bogdanm 87:6213f644d804 3126 /* FDPROT Bit Fields */
bogdanm 87:6213f644d804 3127 #define NV_FDPROT_DPROT_MASK 0xFFu
bogdanm 87:6213f644d804 3128 #define NV_FDPROT_DPROT_SHIFT 0
bogdanm 87:6213f644d804 3129 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
bogdanm 87:6213f644d804 3130
bogdanm 87:6213f644d804 3131 /**
bogdanm 87:6213f644d804 3132 * @}
bogdanm 87:6213f644d804 3133 */ /* end of group NV_Register_Masks */
bogdanm 87:6213f644d804 3134
bogdanm 87:6213f644d804 3135
bogdanm 87:6213f644d804 3136 /* NV - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3137 /** Peripheral FTFL_FlashConfig base address */
bogdanm 87:6213f644d804 3138 #define FTFL_FlashConfig_BASE (0x400u)
bogdanm 87:6213f644d804 3139 /** Peripheral FTFL_FlashConfig base pointer */
bogdanm 87:6213f644d804 3140 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
bogdanm 87:6213f644d804 3141
bogdanm 87:6213f644d804 3142 /**
bogdanm 87:6213f644d804 3143 * @}
bogdanm 87:6213f644d804 3144 */ /* end of group NV_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3145
bogdanm 87:6213f644d804 3146
bogdanm 87:6213f644d804 3147 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3148 -- OSC Peripheral Access Layer
bogdanm 87:6213f644d804 3149 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3150
bogdanm 87:6213f644d804 3151 /**
bogdanm 87:6213f644d804 3152 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
bogdanm 87:6213f644d804 3153 * @{
bogdanm 87:6213f644d804 3154 */
bogdanm 87:6213f644d804 3155
bogdanm 87:6213f644d804 3156 /** OSC - Register Layout Typedef */
bogdanm 87:6213f644d804 3157 typedef struct {
bogdanm 87:6213f644d804 3158 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
bogdanm 87:6213f644d804 3159 } OSC_Type;
bogdanm 87:6213f644d804 3160
bogdanm 87:6213f644d804 3161 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3162 -- OSC Register Masks
bogdanm 87:6213f644d804 3163 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3164
bogdanm 87:6213f644d804 3165 /**
bogdanm 87:6213f644d804 3166 * @addtogroup OSC_Register_Masks OSC Register Masks
bogdanm 87:6213f644d804 3167 * @{
bogdanm 87:6213f644d804 3168 */
bogdanm 87:6213f644d804 3169
bogdanm 87:6213f644d804 3170 /* CR Bit Fields */
bogdanm 87:6213f644d804 3171 #define OSC_CR_SC16P_MASK 0x1u
bogdanm 87:6213f644d804 3172 #define OSC_CR_SC16P_SHIFT 0
bogdanm 87:6213f644d804 3173 #define OSC_CR_SC8P_MASK 0x2u
bogdanm 87:6213f644d804 3174 #define OSC_CR_SC8P_SHIFT 1
bogdanm 87:6213f644d804 3175 #define OSC_CR_SC4P_MASK 0x4u
bogdanm 87:6213f644d804 3176 #define OSC_CR_SC4P_SHIFT 2
bogdanm 87:6213f644d804 3177 #define OSC_CR_SC2P_MASK 0x8u
bogdanm 87:6213f644d804 3178 #define OSC_CR_SC2P_SHIFT 3
bogdanm 87:6213f644d804 3179 #define OSC_CR_EREFSTEN_MASK 0x20u
bogdanm 87:6213f644d804 3180 #define OSC_CR_EREFSTEN_SHIFT 5
bogdanm 87:6213f644d804 3181 #define OSC_CR_ERCLKEN_MASK 0x80u
bogdanm 87:6213f644d804 3182 #define OSC_CR_ERCLKEN_SHIFT 7
bogdanm 87:6213f644d804 3183
bogdanm 87:6213f644d804 3184 /**
bogdanm 87:6213f644d804 3185 * @}
bogdanm 87:6213f644d804 3186 */ /* end of group OSC_Register_Masks */
bogdanm 87:6213f644d804 3187
bogdanm 87:6213f644d804 3188
bogdanm 87:6213f644d804 3189 /* OSC - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3190 /** Peripheral OSC0 base address */
bogdanm 87:6213f644d804 3191 #define OSC0_BASE (0x40065000u)
bogdanm 87:6213f644d804 3192 /** Peripheral OSC0 base pointer */
bogdanm 87:6213f644d804 3193 #define OSC0 ((OSC_Type *)OSC0_BASE)
bogdanm 87:6213f644d804 3194
bogdanm 87:6213f644d804 3195 /**
bogdanm 87:6213f644d804 3196 * @}
bogdanm 87:6213f644d804 3197 */ /* end of group OSC_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3198
bogdanm 87:6213f644d804 3199
bogdanm 87:6213f644d804 3200 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3201 -- PDB Peripheral Access Layer
bogdanm 87:6213f644d804 3202 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3203
bogdanm 87:6213f644d804 3204 /**
bogdanm 87:6213f644d804 3205 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
bogdanm 87:6213f644d804 3206 * @{
bogdanm 87:6213f644d804 3207 */
bogdanm 87:6213f644d804 3208
bogdanm 87:6213f644d804 3209 /** PDB - Register Layout Typedef */
bogdanm 87:6213f644d804 3210 typedef struct {
bogdanm 87:6213f644d804 3211 __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
bogdanm 87:6213f644d804 3212 __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
bogdanm 87:6213f644d804 3213 __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
bogdanm 87:6213f644d804 3214 __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
bogdanm 87:6213f644d804 3215 struct { /* offset: 0x10, array step: 0x10 */
bogdanm 87:6213f644d804 3216 __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
bogdanm 87:6213f644d804 3217 __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
bogdanm 87:6213f644d804 3218 __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
bogdanm 87:6213f644d804 3219 } CH[1];
bogdanm 87:6213f644d804 3220 uint8_t RESERVED_0[368];
bogdanm 87:6213f644d804 3221 __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
bogdanm 87:6213f644d804 3222 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
bogdanm 87:6213f644d804 3223 } PDB_Type;
bogdanm 87:6213f644d804 3224
bogdanm 87:6213f644d804 3225 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3226 -- PDB Register Masks
bogdanm 87:6213f644d804 3227 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3228
bogdanm 87:6213f644d804 3229 /**
bogdanm 87:6213f644d804 3230 * @addtogroup PDB_Register_Masks PDB Register Masks
bogdanm 87:6213f644d804 3231 * @{
bogdanm 87:6213f644d804 3232 */
bogdanm 87:6213f644d804 3233
bogdanm 87:6213f644d804 3234 /* SC Bit Fields */
bogdanm 87:6213f644d804 3235 #define PDB_SC_LDOK_MASK 0x1u
bogdanm 87:6213f644d804 3236 #define PDB_SC_LDOK_SHIFT 0
bogdanm 87:6213f644d804 3237 #define PDB_SC_CONT_MASK 0x2u
bogdanm 87:6213f644d804 3238 #define PDB_SC_CONT_SHIFT 1
bogdanm 87:6213f644d804 3239 #define PDB_SC_MULT_MASK 0xCu
bogdanm 87:6213f644d804 3240 #define PDB_SC_MULT_SHIFT 2
bogdanm 87:6213f644d804 3241 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
bogdanm 87:6213f644d804 3242 #define PDB_SC_PDBIE_MASK 0x20u
bogdanm 87:6213f644d804 3243 #define PDB_SC_PDBIE_SHIFT 5
bogdanm 87:6213f644d804 3244 #define PDB_SC_PDBIF_MASK 0x40u
bogdanm 87:6213f644d804 3245 #define PDB_SC_PDBIF_SHIFT 6
bogdanm 87:6213f644d804 3246 #define PDB_SC_PDBEN_MASK 0x80u
bogdanm 87:6213f644d804 3247 #define PDB_SC_PDBEN_SHIFT 7
bogdanm 87:6213f644d804 3248 #define PDB_SC_TRGSEL_MASK 0xF00u
bogdanm 87:6213f644d804 3249 #define PDB_SC_TRGSEL_SHIFT 8
bogdanm 87:6213f644d804 3250 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
bogdanm 87:6213f644d804 3251 #define PDB_SC_PRESCALER_MASK 0x7000u
bogdanm 87:6213f644d804 3252 #define PDB_SC_PRESCALER_SHIFT 12
bogdanm 87:6213f644d804 3253 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
bogdanm 87:6213f644d804 3254 #define PDB_SC_DMAEN_MASK 0x8000u
bogdanm 87:6213f644d804 3255 #define PDB_SC_DMAEN_SHIFT 15
bogdanm 87:6213f644d804 3256 #define PDB_SC_SWTRIG_MASK 0x10000u
bogdanm 87:6213f644d804 3257 #define PDB_SC_SWTRIG_SHIFT 16
bogdanm 87:6213f644d804 3258 #define PDB_SC_PDBEIE_MASK 0x20000u
bogdanm 87:6213f644d804 3259 #define PDB_SC_PDBEIE_SHIFT 17
bogdanm 87:6213f644d804 3260 #define PDB_SC_LDMOD_MASK 0xC0000u
bogdanm 87:6213f644d804 3261 #define PDB_SC_LDMOD_SHIFT 18
bogdanm 87:6213f644d804 3262 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
bogdanm 87:6213f644d804 3263 /* MOD Bit Fields */
bogdanm 87:6213f644d804 3264 #define PDB_MOD_MOD_MASK 0xFFFFu
bogdanm 87:6213f644d804 3265 #define PDB_MOD_MOD_SHIFT 0
bogdanm 87:6213f644d804 3266 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
bogdanm 87:6213f644d804 3267 /* CNT Bit Fields */
bogdanm 87:6213f644d804 3268 #define PDB_CNT_CNT_MASK 0xFFFFu
bogdanm 87:6213f644d804 3269 #define PDB_CNT_CNT_SHIFT 0
bogdanm 87:6213f644d804 3270 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
bogdanm 87:6213f644d804 3271 /* IDLY Bit Fields */
bogdanm 87:6213f644d804 3272 #define PDB_IDLY_IDLY_MASK 0xFFFFu
bogdanm 87:6213f644d804 3273 #define PDB_IDLY_IDLY_SHIFT 0
bogdanm 87:6213f644d804 3274 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
bogdanm 87:6213f644d804 3275 /* C1 Bit Fields */
bogdanm 87:6213f644d804 3276 #define PDB_C1_EN_MASK 0xFFu
bogdanm 87:6213f644d804 3277 #define PDB_C1_EN_SHIFT 0
bogdanm 87:6213f644d804 3278 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
bogdanm 87:6213f644d804 3279 #define PDB_C1_TOS_MASK 0xFF00u
bogdanm 87:6213f644d804 3280 #define PDB_C1_TOS_SHIFT 8
bogdanm 87:6213f644d804 3281 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
bogdanm 87:6213f644d804 3282 #define PDB_C1_BB_MASK 0xFF0000u
bogdanm 87:6213f644d804 3283 #define PDB_C1_BB_SHIFT 16
bogdanm 87:6213f644d804 3284 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
bogdanm 87:6213f644d804 3285 /* S Bit Fields */
bogdanm 87:6213f644d804 3286 #define PDB_S_ERR_MASK 0xFFu
bogdanm 87:6213f644d804 3287 #define PDB_S_ERR_SHIFT 0
bogdanm 87:6213f644d804 3288 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
bogdanm 87:6213f644d804 3289 #define PDB_S_CF_MASK 0xFF0000u
bogdanm 87:6213f644d804 3290 #define PDB_S_CF_SHIFT 16
bogdanm 87:6213f644d804 3291 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
bogdanm 87:6213f644d804 3292 /* DLY Bit Fields */
bogdanm 87:6213f644d804 3293 #define PDB_DLY_DLY_MASK 0xFFFFu
bogdanm 87:6213f644d804 3294 #define PDB_DLY_DLY_SHIFT 0
bogdanm 87:6213f644d804 3295 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
bogdanm 87:6213f644d804 3296 /* POEN Bit Fields */
bogdanm 87:6213f644d804 3297 #define PDB_POEN_POEN_MASK 0xFFu
bogdanm 87:6213f644d804 3298 #define PDB_POEN_POEN_SHIFT 0
bogdanm 87:6213f644d804 3299 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
bogdanm 87:6213f644d804 3300 /* PODLY Bit Fields */
bogdanm 87:6213f644d804 3301 #define PDB_PODLY_DLY2_MASK 0xFFFFu
bogdanm 87:6213f644d804 3302 #define PDB_PODLY_DLY2_SHIFT 0
bogdanm 87:6213f644d804 3303 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
bogdanm 87:6213f644d804 3304 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 3305 #define PDB_PODLY_DLY1_SHIFT 16
bogdanm 87:6213f644d804 3306 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
bogdanm 87:6213f644d804 3307
bogdanm 87:6213f644d804 3308 /**
bogdanm 87:6213f644d804 3309 * @}
bogdanm 87:6213f644d804 3310 */ /* end of group PDB_Register_Masks */
bogdanm 87:6213f644d804 3311
bogdanm 87:6213f644d804 3312
bogdanm 87:6213f644d804 3313 /* PDB - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3314 /** Peripheral PDB0 base address */
bogdanm 87:6213f644d804 3315 #define PDB0_BASE (0x40036000u)
bogdanm 87:6213f644d804 3316 /** Peripheral PDB0 base pointer */
bogdanm 87:6213f644d804 3317 #define PDB0 ((PDB_Type *)PDB0_BASE)
bogdanm 87:6213f644d804 3318
bogdanm 87:6213f644d804 3319 /**
bogdanm 87:6213f644d804 3320 * @}
bogdanm 87:6213f644d804 3321 */ /* end of group PDB_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3322
bogdanm 87:6213f644d804 3323
bogdanm 87:6213f644d804 3324 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3325 -- PIT Peripheral Access Layer
bogdanm 87:6213f644d804 3326 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3327
bogdanm 87:6213f644d804 3328 /**
bogdanm 87:6213f644d804 3329 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
bogdanm 87:6213f644d804 3330 * @{
bogdanm 87:6213f644d804 3331 */
bogdanm 87:6213f644d804 3332
bogdanm 87:6213f644d804 3333 /** PIT - Register Layout Typedef */
bogdanm 87:6213f644d804 3334 typedef struct {
bogdanm 87:6213f644d804 3335 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
bogdanm 87:6213f644d804 3336 uint8_t RESERVED_0[252];
bogdanm 87:6213f644d804 3337 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 87:6213f644d804 3338 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
bogdanm 87:6213f644d804 3339 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
bogdanm 87:6213f644d804 3340 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
bogdanm 87:6213f644d804 3341 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
bogdanm 87:6213f644d804 3342 } CHANNEL[4];
bogdanm 87:6213f644d804 3343 } PIT_Type;
bogdanm 87:6213f644d804 3344
bogdanm 87:6213f644d804 3345 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3346 -- PIT Register Masks
bogdanm 87:6213f644d804 3347 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3348
bogdanm 87:6213f644d804 3349 /**
bogdanm 87:6213f644d804 3350 * @addtogroup PIT_Register_Masks PIT Register Masks
bogdanm 87:6213f644d804 3351 * @{
bogdanm 87:6213f644d804 3352 */
bogdanm 87:6213f644d804 3353
bogdanm 87:6213f644d804 3354 /* MCR Bit Fields */
bogdanm 87:6213f644d804 3355 #define PIT_MCR_FRZ_MASK 0x1u
bogdanm 87:6213f644d804 3356 #define PIT_MCR_FRZ_SHIFT 0
bogdanm 87:6213f644d804 3357 #define PIT_MCR_MDIS_MASK 0x2u
bogdanm 87:6213f644d804 3358 #define PIT_MCR_MDIS_SHIFT 1
bogdanm 87:6213f644d804 3359 /* LDVAL Bit Fields */
bogdanm 87:6213f644d804 3360 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 3361 #define PIT_LDVAL_TSV_SHIFT 0
bogdanm 87:6213f644d804 3362 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
bogdanm 87:6213f644d804 3363 /* CVAL Bit Fields */
bogdanm 87:6213f644d804 3364 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 3365 #define PIT_CVAL_TVL_SHIFT 0
bogdanm 87:6213f644d804 3366 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
bogdanm 87:6213f644d804 3367 /* TCTRL Bit Fields */
bogdanm 87:6213f644d804 3368 #define PIT_TCTRL_TEN_MASK 0x1u
bogdanm 87:6213f644d804 3369 #define PIT_TCTRL_TEN_SHIFT 0
bogdanm 87:6213f644d804 3370 #define PIT_TCTRL_TIE_MASK 0x2u
bogdanm 87:6213f644d804 3371 #define PIT_TCTRL_TIE_SHIFT 1
bogdanm 87:6213f644d804 3372 /* TFLG Bit Fields */
bogdanm 87:6213f644d804 3373 #define PIT_TFLG_TIF_MASK 0x1u
bogdanm 87:6213f644d804 3374 #define PIT_TFLG_TIF_SHIFT 0
bogdanm 87:6213f644d804 3375
bogdanm 87:6213f644d804 3376 /**
bogdanm 87:6213f644d804 3377 * @}
bogdanm 87:6213f644d804 3378 */ /* end of group PIT_Register_Masks */
bogdanm 87:6213f644d804 3379
bogdanm 87:6213f644d804 3380
bogdanm 87:6213f644d804 3381 /* PIT - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3382 /** Peripheral PIT base address */
bogdanm 87:6213f644d804 3383 #define PIT_BASE (0x40037000u)
bogdanm 87:6213f644d804 3384 /** Peripheral PIT base pointer */
bogdanm 87:6213f644d804 3385 #define PIT ((PIT_Type *)PIT_BASE)
bogdanm 87:6213f644d804 3386
bogdanm 87:6213f644d804 3387 /**
bogdanm 87:6213f644d804 3388 * @}
bogdanm 87:6213f644d804 3389 */ /* end of group PIT_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3390
bogdanm 87:6213f644d804 3391
bogdanm 87:6213f644d804 3392 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3393 -- PMC Peripheral Access Layer
bogdanm 87:6213f644d804 3394 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3395
bogdanm 87:6213f644d804 3396 /**
bogdanm 87:6213f644d804 3397 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
bogdanm 87:6213f644d804 3398 * @{
bogdanm 87:6213f644d804 3399 */
bogdanm 87:6213f644d804 3400
bogdanm 87:6213f644d804 3401 /** PMC - Register Layout Typedef */
bogdanm 87:6213f644d804 3402 typedef struct {
bogdanm 87:6213f644d804 3403 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
bogdanm 87:6213f644d804 3404 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
bogdanm 87:6213f644d804 3405 __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
bogdanm 87:6213f644d804 3406 } PMC_Type;
bogdanm 87:6213f644d804 3407
bogdanm 87:6213f644d804 3408 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3409 -- PMC Register Masks
bogdanm 87:6213f644d804 3410 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3411
bogdanm 87:6213f644d804 3412 /**
bogdanm 87:6213f644d804 3413 * @addtogroup PMC_Register_Masks PMC Register Masks
bogdanm 87:6213f644d804 3414 * @{
bogdanm 87:6213f644d804 3415 */
bogdanm 87:6213f644d804 3416
bogdanm 87:6213f644d804 3417 /* LVDSC1 Bit Fields */
bogdanm 87:6213f644d804 3418 #define PMC_LVDSC1_LVDV_MASK 0x3u
bogdanm 87:6213f644d804 3419 #define PMC_LVDSC1_LVDV_SHIFT 0
bogdanm 87:6213f644d804 3420 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
bogdanm 87:6213f644d804 3421 #define PMC_LVDSC1_LVDRE_MASK 0x10u
bogdanm 87:6213f644d804 3422 #define PMC_LVDSC1_LVDRE_SHIFT 4
bogdanm 87:6213f644d804 3423 #define PMC_LVDSC1_LVDIE_MASK 0x20u
bogdanm 87:6213f644d804 3424 #define PMC_LVDSC1_LVDIE_SHIFT 5
bogdanm 87:6213f644d804 3425 #define PMC_LVDSC1_LVDACK_MASK 0x40u
bogdanm 87:6213f644d804 3426 #define PMC_LVDSC1_LVDACK_SHIFT 6
bogdanm 87:6213f644d804 3427 #define PMC_LVDSC1_LVDF_MASK 0x80u
bogdanm 87:6213f644d804 3428 #define PMC_LVDSC1_LVDF_SHIFT 7
bogdanm 87:6213f644d804 3429 /* LVDSC2 Bit Fields */
bogdanm 87:6213f644d804 3430 #define PMC_LVDSC2_LVWV_MASK 0x3u
bogdanm 87:6213f644d804 3431 #define PMC_LVDSC2_LVWV_SHIFT 0
bogdanm 87:6213f644d804 3432 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
bogdanm 87:6213f644d804 3433 #define PMC_LVDSC2_LVWIE_MASK 0x20u
bogdanm 87:6213f644d804 3434 #define PMC_LVDSC2_LVWIE_SHIFT 5
bogdanm 87:6213f644d804 3435 #define PMC_LVDSC2_LVWACK_MASK 0x40u
bogdanm 87:6213f644d804 3436 #define PMC_LVDSC2_LVWACK_SHIFT 6
bogdanm 87:6213f644d804 3437 #define PMC_LVDSC2_LVWF_MASK 0x80u
bogdanm 87:6213f644d804 3438 #define PMC_LVDSC2_LVWF_SHIFT 7
bogdanm 87:6213f644d804 3439 /* REGSC Bit Fields */
bogdanm 87:6213f644d804 3440 #define PMC_REGSC_BGBE_MASK 0x1u
bogdanm 87:6213f644d804 3441 #define PMC_REGSC_BGBE_SHIFT 0
bogdanm 87:6213f644d804 3442 #define PMC_REGSC_REGONS_MASK 0x4u
bogdanm 87:6213f644d804 3443 #define PMC_REGSC_REGONS_SHIFT 2
bogdanm 87:6213f644d804 3444 #define PMC_REGSC_ACKISO_MASK 0x8u
bogdanm 87:6213f644d804 3445 #define PMC_REGSC_ACKISO_SHIFT 3
bogdanm 87:6213f644d804 3446
bogdanm 87:6213f644d804 3447 /**
bogdanm 87:6213f644d804 3448 * @}
bogdanm 87:6213f644d804 3449 */ /* end of group PMC_Register_Masks */
bogdanm 87:6213f644d804 3450
bogdanm 87:6213f644d804 3451
bogdanm 87:6213f644d804 3452 /* PMC - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3453 /** Peripheral PMC base address */
bogdanm 87:6213f644d804 3454 #define PMC_BASE (0x4007D000u)
bogdanm 87:6213f644d804 3455 /** Peripheral PMC base pointer */
bogdanm 87:6213f644d804 3456 #define PMC ((PMC_Type *)PMC_BASE)
bogdanm 87:6213f644d804 3457
bogdanm 87:6213f644d804 3458 /**
bogdanm 87:6213f644d804 3459 * @}
bogdanm 87:6213f644d804 3460 */ /* end of group PMC_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3461
bogdanm 87:6213f644d804 3462
bogdanm 87:6213f644d804 3463 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3464 -- PORT Peripheral Access Layer
bogdanm 87:6213f644d804 3465 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3466
bogdanm 87:6213f644d804 3467 /**
bogdanm 87:6213f644d804 3468 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
bogdanm 87:6213f644d804 3469 * @{
bogdanm 87:6213f644d804 3470 */
bogdanm 87:6213f644d804 3471
bogdanm 87:6213f644d804 3472 /** PORT - Register Layout Typedef */
bogdanm 87:6213f644d804 3473 typedef struct {
bogdanm 87:6213f644d804 3474 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
bogdanm 87:6213f644d804 3475 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
bogdanm 87:6213f644d804 3476 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
bogdanm 87:6213f644d804 3477 uint8_t RESERVED_0[24];
bogdanm 87:6213f644d804 3478 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
bogdanm 87:6213f644d804 3479 uint8_t RESERVED_1[28];
bogdanm 87:6213f644d804 3480 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
bogdanm 87:6213f644d804 3481 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
bogdanm 87:6213f644d804 3482 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
bogdanm 87:6213f644d804 3483 } PORT_Type;
bogdanm 87:6213f644d804 3484
bogdanm 87:6213f644d804 3485 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3486 -- PORT Register Masks
bogdanm 87:6213f644d804 3487 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3488
bogdanm 87:6213f644d804 3489 /**
bogdanm 87:6213f644d804 3490 * @addtogroup PORT_Register_Masks PORT Register Masks
bogdanm 87:6213f644d804 3491 * @{
bogdanm 87:6213f644d804 3492 */
bogdanm 87:6213f644d804 3493
bogdanm 87:6213f644d804 3494 /* PCR Bit Fields */
bogdanm 87:6213f644d804 3495 #define PORT_PCR_PS_MASK 0x1u
bogdanm 87:6213f644d804 3496 #define PORT_PCR_PS_SHIFT 0
bogdanm 87:6213f644d804 3497 #define PORT_PCR_PE_MASK 0x2u
bogdanm 87:6213f644d804 3498 #define PORT_PCR_PE_SHIFT 1
bogdanm 87:6213f644d804 3499 #define PORT_PCR_SRE_MASK 0x4u
bogdanm 87:6213f644d804 3500 #define PORT_PCR_SRE_SHIFT 2
bogdanm 87:6213f644d804 3501 #define PORT_PCR_PFE_MASK 0x10u
bogdanm 87:6213f644d804 3502 #define PORT_PCR_PFE_SHIFT 4
bogdanm 87:6213f644d804 3503 #define PORT_PCR_ODE_MASK 0x20u
bogdanm 87:6213f644d804 3504 #define PORT_PCR_ODE_SHIFT 5
bogdanm 87:6213f644d804 3505 #define PORT_PCR_DSE_MASK 0x40u
bogdanm 87:6213f644d804 3506 #define PORT_PCR_DSE_SHIFT 6
bogdanm 87:6213f644d804 3507 #define PORT_PCR_MUX_MASK 0x700u
bogdanm 87:6213f644d804 3508 #define PORT_PCR_MUX_SHIFT 8
bogdanm 87:6213f644d804 3509 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
bogdanm 87:6213f644d804 3510 #define PORT_PCR_LK_MASK 0x8000u
bogdanm 87:6213f644d804 3511 #define PORT_PCR_LK_SHIFT 15
bogdanm 87:6213f644d804 3512 #define PORT_PCR_IRQC_MASK 0xF0000u
bogdanm 87:6213f644d804 3513 #define PORT_PCR_IRQC_SHIFT 16
bogdanm 87:6213f644d804 3514 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
bogdanm 87:6213f644d804 3515 #define PORT_PCR_ISF_MASK 0x1000000u
bogdanm 87:6213f644d804 3516 #define PORT_PCR_ISF_SHIFT 24
bogdanm 87:6213f644d804 3517 /* GPCLR Bit Fields */
bogdanm 87:6213f644d804 3518 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
bogdanm 87:6213f644d804 3519 #define PORT_GPCLR_GPWD_SHIFT 0
bogdanm 87:6213f644d804 3520 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
bogdanm 87:6213f644d804 3521 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 3522 #define PORT_GPCLR_GPWE_SHIFT 16
bogdanm 87:6213f644d804 3523 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
bogdanm 87:6213f644d804 3524 /* GPCHR Bit Fields */
bogdanm 87:6213f644d804 3525 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
bogdanm 87:6213f644d804 3526 #define PORT_GPCHR_GPWD_SHIFT 0
bogdanm 87:6213f644d804 3527 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
bogdanm 87:6213f644d804 3528 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 3529 #define PORT_GPCHR_GPWE_SHIFT 16
bogdanm 87:6213f644d804 3530 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
bogdanm 87:6213f644d804 3531 /* ISFR Bit Fields */
bogdanm 87:6213f644d804 3532 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 3533 #define PORT_ISFR_ISF_SHIFT 0
bogdanm 87:6213f644d804 3534 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
bogdanm 87:6213f644d804 3535 /* DFER Bit Fields */
bogdanm 87:6213f644d804 3536 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 3537 #define PORT_DFER_DFE_SHIFT 0
bogdanm 87:6213f644d804 3538 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
bogdanm 87:6213f644d804 3539 /* DFCR Bit Fields */
bogdanm 87:6213f644d804 3540 #define PORT_DFCR_CS_MASK 0x1u
bogdanm 87:6213f644d804 3541 #define PORT_DFCR_CS_SHIFT 0
bogdanm 87:6213f644d804 3542 /* DFWR Bit Fields */
bogdanm 87:6213f644d804 3543 #define PORT_DFWR_FILT_MASK 0x1Fu
bogdanm 87:6213f644d804 3544 #define PORT_DFWR_FILT_SHIFT 0
bogdanm 87:6213f644d804 3545 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
bogdanm 87:6213f644d804 3546
bogdanm 87:6213f644d804 3547 /**
bogdanm 87:6213f644d804 3548 * @}
bogdanm 87:6213f644d804 3549 */ /* end of group PORT_Register_Masks */
bogdanm 87:6213f644d804 3550
bogdanm 87:6213f644d804 3551
bogdanm 87:6213f644d804 3552 /* PORT - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3553 /** Peripheral PORTA base address */
bogdanm 87:6213f644d804 3554 #define PORTA_BASE (0x40049000u)
bogdanm 87:6213f644d804 3555 /** Peripheral PORTA base pointer */
bogdanm 87:6213f644d804 3556 #define PORTA ((PORT_Type *)PORTA_BASE)
bogdanm 87:6213f644d804 3557 /** Peripheral PORTB base address */
bogdanm 87:6213f644d804 3558 #define PORTB_BASE (0x4004A000u)
bogdanm 87:6213f644d804 3559 /** Peripheral PORTB base pointer */
bogdanm 87:6213f644d804 3560 #define PORTB ((PORT_Type *)PORTB_BASE)
bogdanm 87:6213f644d804 3561 /** Peripheral PORTC base address */
bogdanm 87:6213f644d804 3562 #define PORTC_BASE (0x4004B000u)
bogdanm 87:6213f644d804 3563 /** Peripheral PORTC base pointer */
bogdanm 87:6213f644d804 3564 #define PORTC ((PORT_Type *)PORTC_BASE)
bogdanm 87:6213f644d804 3565 /** Peripheral PORTD base address */
bogdanm 87:6213f644d804 3566 #define PORTD_BASE (0x4004C000u)
bogdanm 87:6213f644d804 3567 /** Peripheral PORTD base pointer */
bogdanm 87:6213f644d804 3568 #define PORTD ((PORT_Type *)PORTD_BASE)
bogdanm 87:6213f644d804 3569 /** Peripheral PORTE base address */
bogdanm 87:6213f644d804 3570 #define PORTE_BASE (0x4004D000u)
bogdanm 87:6213f644d804 3571 /** Peripheral PORTE base pointer */
bogdanm 87:6213f644d804 3572 #define PORTE ((PORT_Type *)PORTE_BASE)
bogdanm 87:6213f644d804 3573
bogdanm 87:6213f644d804 3574 /**
bogdanm 87:6213f644d804 3575 * @}
bogdanm 87:6213f644d804 3576 */ /* end of group PORT_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3577
bogdanm 87:6213f644d804 3578
bogdanm 87:6213f644d804 3579 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3580 -- RCM Peripheral Access Layer
bogdanm 87:6213f644d804 3581 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3582
bogdanm 87:6213f644d804 3583 /**
bogdanm 87:6213f644d804 3584 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
bogdanm 87:6213f644d804 3585 * @{
bogdanm 87:6213f644d804 3586 */
bogdanm 87:6213f644d804 3587
bogdanm 87:6213f644d804 3588 /** RCM - Register Layout Typedef */
bogdanm 87:6213f644d804 3589 typedef struct {
bogdanm 87:6213f644d804 3590 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
bogdanm 87:6213f644d804 3591 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
bogdanm 87:6213f644d804 3592 uint8_t RESERVED_0[2];
bogdanm 87:6213f644d804 3593 __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
bogdanm 87:6213f644d804 3594 __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
bogdanm 87:6213f644d804 3595 uint8_t RESERVED_1[1];
bogdanm 87:6213f644d804 3596 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
bogdanm 87:6213f644d804 3597 } RCM_Type;
bogdanm 87:6213f644d804 3598
bogdanm 87:6213f644d804 3599 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3600 -- RCM Register Masks
bogdanm 87:6213f644d804 3601 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3602
bogdanm 87:6213f644d804 3603 /**
bogdanm 87:6213f644d804 3604 * @addtogroup RCM_Register_Masks RCM Register Masks
bogdanm 87:6213f644d804 3605 * @{
bogdanm 87:6213f644d804 3606 */
bogdanm 87:6213f644d804 3607
bogdanm 87:6213f644d804 3608 /* SRS0 Bit Fields */
bogdanm 87:6213f644d804 3609 #define RCM_SRS0_WAKEUP_MASK 0x1u
bogdanm 87:6213f644d804 3610 #define RCM_SRS0_WAKEUP_SHIFT 0
bogdanm 87:6213f644d804 3611 #define RCM_SRS0_LVD_MASK 0x2u
bogdanm 87:6213f644d804 3612 #define RCM_SRS0_LVD_SHIFT 1
bogdanm 87:6213f644d804 3613 #define RCM_SRS0_LOC_MASK 0x4u
bogdanm 87:6213f644d804 3614 #define RCM_SRS0_LOC_SHIFT 2
bogdanm 87:6213f644d804 3615 #define RCM_SRS0_LOL_MASK 0x8u
bogdanm 87:6213f644d804 3616 #define RCM_SRS0_LOL_SHIFT 3
bogdanm 87:6213f644d804 3617 #define RCM_SRS0_WDOG_MASK 0x20u
bogdanm 87:6213f644d804 3618 #define RCM_SRS0_WDOG_SHIFT 5
bogdanm 87:6213f644d804 3619 #define RCM_SRS0_PIN_MASK 0x40u
bogdanm 87:6213f644d804 3620 #define RCM_SRS0_PIN_SHIFT 6
bogdanm 87:6213f644d804 3621 #define RCM_SRS0_POR_MASK 0x80u
bogdanm 87:6213f644d804 3622 #define RCM_SRS0_POR_SHIFT 7
bogdanm 87:6213f644d804 3623 /* SRS1 Bit Fields */
bogdanm 87:6213f644d804 3624 #define RCM_SRS1_JTAG_MASK 0x1u
bogdanm 87:6213f644d804 3625 #define RCM_SRS1_JTAG_SHIFT 0
bogdanm 87:6213f644d804 3626 #define RCM_SRS1_LOCKUP_MASK 0x2u
bogdanm 87:6213f644d804 3627 #define RCM_SRS1_LOCKUP_SHIFT 1
bogdanm 87:6213f644d804 3628 #define RCM_SRS1_SW_MASK 0x4u
bogdanm 87:6213f644d804 3629 #define RCM_SRS1_SW_SHIFT 2
bogdanm 87:6213f644d804 3630 #define RCM_SRS1_MDM_AP_MASK 0x8u
bogdanm 87:6213f644d804 3631 #define RCM_SRS1_MDM_AP_SHIFT 3
bogdanm 87:6213f644d804 3632 #define RCM_SRS1_EZPT_MASK 0x10u
bogdanm 87:6213f644d804 3633 #define RCM_SRS1_EZPT_SHIFT 4
bogdanm 87:6213f644d804 3634 #define RCM_SRS1_SACKERR_MASK 0x20u
bogdanm 87:6213f644d804 3635 #define RCM_SRS1_SACKERR_SHIFT 5
bogdanm 87:6213f644d804 3636 /* RPFC Bit Fields */
bogdanm 87:6213f644d804 3637 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
bogdanm 87:6213f644d804 3638 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
bogdanm 87:6213f644d804 3639 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
bogdanm 87:6213f644d804 3640 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
bogdanm 87:6213f644d804 3641 #define RCM_RPFC_RSTFLTSS_SHIFT 2
bogdanm 87:6213f644d804 3642 /* RPFW Bit Fields */
bogdanm 87:6213f644d804 3643 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
bogdanm 87:6213f644d804 3644 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
bogdanm 87:6213f644d804 3645 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
bogdanm 87:6213f644d804 3646 /* MR Bit Fields */
bogdanm 87:6213f644d804 3647 #define RCM_MR_EZP_MS_MASK 0x2u
bogdanm 87:6213f644d804 3648 #define RCM_MR_EZP_MS_SHIFT 1
bogdanm 87:6213f644d804 3649
bogdanm 87:6213f644d804 3650 /**
bogdanm 87:6213f644d804 3651 * @}
bogdanm 87:6213f644d804 3652 */ /* end of group RCM_Register_Masks */
bogdanm 87:6213f644d804 3653
bogdanm 87:6213f644d804 3654
bogdanm 87:6213f644d804 3655 /* RCM - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3656 /** Peripheral RCM base address */
bogdanm 87:6213f644d804 3657 #define RCM_BASE (0x4007F000u)
bogdanm 87:6213f644d804 3658 /** Peripheral RCM base pointer */
bogdanm 87:6213f644d804 3659 #define RCM ((RCM_Type *)RCM_BASE)
bogdanm 87:6213f644d804 3660
bogdanm 87:6213f644d804 3661 /**
bogdanm 87:6213f644d804 3662 * @}
bogdanm 87:6213f644d804 3663 */ /* end of group RCM_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3664
bogdanm 87:6213f644d804 3665
bogdanm 87:6213f644d804 3666 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3667 -- RFSYS Peripheral Access Layer
bogdanm 87:6213f644d804 3668 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3669
bogdanm 87:6213f644d804 3670 /**
bogdanm 87:6213f644d804 3671 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
bogdanm 87:6213f644d804 3672 * @{
bogdanm 87:6213f644d804 3673 */
bogdanm 87:6213f644d804 3674
bogdanm 87:6213f644d804 3675 /** RFSYS - Register Layout Typedef */
bogdanm 87:6213f644d804 3676 typedef struct {
bogdanm 87:6213f644d804 3677 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
bogdanm 87:6213f644d804 3678 } RFSYS_Type;
bogdanm 87:6213f644d804 3679
bogdanm 87:6213f644d804 3680 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3681 -- RFSYS Register Masks
bogdanm 87:6213f644d804 3682 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3683
bogdanm 87:6213f644d804 3684 /**
bogdanm 87:6213f644d804 3685 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
bogdanm 87:6213f644d804 3686 * @{
bogdanm 87:6213f644d804 3687 */
bogdanm 87:6213f644d804 3688
bogdanm 87:6213f644d804 3689 /* REG Bit Fields */
bogdanm 87:6213f644d804 3690 #define RFSYS_REG_LL_MASK 0xFFu
bogdanm 87:6213f644d804 3691 #define RFSYS_REG_LL_SHIFT 0
bogdanm 87:6213f644d804 3692 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
bogdanm 87:6213f644d804 3693 #define RFSYS_REG_LH_MASK 0xFF00u
bogdanm 87:6213f644d804 3694 #define RFSYS_REG_LH_SHIFT 8
bogdanm 87:6213f644d804 3695 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
bogdanm 87:6213f644d804 3696 #define RFSYS_REG_HL_MASK 0xFF0000u
bogdanm 87:6213f644d804 3697 #define RFSYS_REG_HL_SHIFT 16
bogdanm 87:6213f644d804 3698 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
bogdanm 87:6213f644d804 3699 #define RFSYS_REG_HH_MASK 0xFF000000u
bogdanm 87:6213f644d804 3700 #define RFSYS_REG_HH_SHIFT 24
bogdanm 87:6213f644d804 3701 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
bogdanm 87:6213f644d804 3702
bogdanm 87:6213f644d804 3703 /**
bogdanm 87:6213f644d804 3704 * @}
bogdanm 87:6213f644d804 3705 */ /* end of group RFSYS_Register_Masks */
bogdanm 87:6213f644d804 3706
bogdanm 87:6213f644d804 3707
bogdanm 87:6213f644d804 3708 /* RFSYS - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3709 /** Peripheral RFSYS base address */
bogdanm 87:6213f644d804 3710 #define RFSYS_BASE (0x40041000u)
bogdanm 87:6213f644d804 3711 /** Peripheral RFSYS base pointer */
bogdanm 87:6213f644d804 3712 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
bogdanm 87:6213f644d804 3713
bogdanm 87:6213f644d804 3714 /**
bogdanm 87:6213f644d804 3715 * @}
bogdanm 87:6213f644d804 3716 */ /* end of group RFSYS_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3717
bogdanm 87:6213f644d804 3718
bogdanm 87:6213f644d804 3719 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3720 -- RFVBAT Peripheral Access Layer
bogdanm 87:6213f644d804 3721 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3722
bogdanm 87:6213f644d804 3723 /**
bogdanm 87:6213f644d804 3724 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
bogdanm 87:6213f644d804 3725 * @{
bogdanm 87:6213f644d804 3726 */
bogdanm 87:6213f644d804 3727
bogdanm 87:6213f644d804 3728 /** RFVBAT - Register Layout Typedef */
bogdanm 87:6213f644d804 3729 typedef struct {
bogdanm 87:6213f644d804 3730 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
bogdanm 87:6213f644d804 3731 } RFVBAT_Type;
bogdanm 87:6213f644d804 3732
bogdanm 87:6213f644d804 3733 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3734 -- RFVBAT Register Masks
bogdanm 87:6213f644d804 3735 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3736
bogdanm 87:6213f644d804 3737 /**
bogdanm 87:6213f644d804 3738 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
bogdanm 87:6213f644d804 3739 * @{
bogdanm 87:6213f644d804 3740 */
bogdanm 87:6213f644d804 3741
bogdanm 87:6213f644d804 3742 /* REG Bit Fields */
bogdanm 87:6213f644d804 3743 #define RFVBAT_REG_LL_MASK 0xFFu
bogdanm 87:6213f644d804 3744 #define RFVBAT_REG_LL_SHIFT 0
bogdanm 87:6213f644d804 3745 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
bogdanm 87:6213f644d804 3746 #define RFVBAT_REG_LH_MASK 0xFF00u
bogdanm 87:6213f644d804 3747 #define RFVBAT_REG_LH_SHIFT 8
bogdanm 87:6213f644d804 3748 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
bogdanm 87:6213f644d804 3749 #define RFVBAT_REG_HL_MASK 0xFF0000u
bogdanm 87:6213f644d804 3750 #define RFVBAT_REG_HL_SHIFT 16
bogdanm 87:6213f644d804 3751 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
bogdanm 87:6213f644d804 3752 #define RFVBAT_REG_HH_MASK 0xFF000000u
bogdanm 87:6213f644d804 3753 #define RFVBAT_REG_HH_SHIFT 24
bogdanm 87:6213f644d804 3754 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
bogdanm 87:6213f644d804 3755
bogdanm 87:6213f644d804 3756 /**
bogdanm 87:6213f644d804 3757 * @}
bogdanm 87:6213f644d804 3758 */ /* end of group RFVBAT_Register_Masks */
bogdanm 87:6213f644d804 3759
bogdanm 87:6213f644d804 3760
bogdanm 87:6213f644d804 3761 /* RFVBAT - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3762 /** Peripheral RFVBAT base address */
bogdanm 87:6213f644d804 3763 #define RFVBAT_BASE (0x4003E000u)
bogdanm 87:6213f644d804 3764 /** Peripheral RFVBAT base pointer */
bogdanm 87:6213f644d804 3765 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
bogdanm 87:6213f644d804 3766
bogdanm 87:6213f644d804 3767 /**
bogdanm 87:6213f644d804 3768 * @}
bogdanm 87:6213f644d804 3769 */ /* end of group RFVBAT_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3770
bogdanm 87:6213f644d804 3771
bogdanm 87:6213f644d804 3772 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3773 -- RTC Peripheral Access Layer
bogdanm 87:6213f644d804 3774 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3775
bogdanm 87:6213f644d804 3776 /**
bogdanm 87:6213f644d804 3777 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
bogdanm 87:6213f644d804 3778 * @{
bogdanm 87:6213f644d804 3779 */
bogdanm 87:6213f644d804 3780
bogdanm 87:6213f644d804 3781 /** RTC - Register Layout Typedef */
bogdanm 87:6213f644d804 3782 typedef struct {
bogdanm 87:6213f644d804 3783 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
bogdanm 87:6213f644d804 3784 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
bogdanm 87:6213f644d804 3785 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
bogdanm 87:6213f644d804 3786 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
bogdanm 87:6213f644d804 3787 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
bogdanm 87:6213f644d804 3788 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
bogdanm 87:6213f644d804 3789 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
bogdanm 87:6213f644d804 3790 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
bogdanm 87:6213f644d804 3791 uint8_t RESERVED_0[2016];
bogdanm 87:6213f644d804 3792 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
bogdanm 87:6213f644d804 3793 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
bogdanm 87:6213f644d804 3794 } RTC_Type;
bogdanm 87:6213f644d804 3795
bogdanm 87:6213f644d804 3796 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3797 -- RTC Register Masks
bogdanm 87:6213f644d804 3798 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3799
bogdanm 87:6213f644d804 3800 /**
bogdanm 87:6213f644d804 3801 * @addtogroup RTC_Register_Masks RTC Register Masks
bogdanm 87:6213f644d804 3802 * @{
bogdanm 87:6213f644d804 3803 */
bogdanm 87:6213f644d804 3804
bogdanm 87:6213f644d804 3805 /* TSR Bit Fields */
bogdanm 87:6213f644d804 3806 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 3807 #define RTC_TSR_TSR_SHIFT 0
bogdanm 87:6213f644d804 3808 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
bogdanm 87:6213f644d804 3809 /* TPR Bit Fields */
bogdanm 87:6213f644d804 3810 #define RTC_TPR_TPR_MASK 0xFFFFu
bogdanm 87:6213f644d804 3811 #define RTC_TPR_TPR_SHIFT 0
bogdanm 87:6213f644d804 3812 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
bogdanm 87:6213f644d804 3813 /* TAR Bit Fields */
bogdanm 87:6213f644d804 3814 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 3815 #define RTC_TAR_TAR_SHIFT 0
bogdanm 87:6213f644d804 3816 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
bogdanm 87:6213f644d804 3817 /* TCR Bit Fields */
bogdanm 87:6213f644d804 3818 #define RTC_TCR_TCR_MASK 0xFFu
bogdanm 87:6213f644d804 3819 #define RTC_TCR_TCR_SHIFT 0
bogdanm 87:6213f644d804 3820 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
bogdanm 87:6213f644d804 3821 #define RTC_TCR_CIR_MASK 0xFF00u
bogdanm 87:6213f644d804 3822 #define RTC_TCR_CIR_SHIFT 8
bogdanm 87:6213f644d804 3823 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
bogdanm 87:6213f644d804 3824 #define RTC_TCR_TCV_MASK 0xFF0000u
bogdanm 87:6213f644d804 3825 #define RTC_TCR_TCV_SHIFT 16
bogdanm 87:6213f644d804 3826 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
bogdanm 87:6213f644d804 3827 #define RTC_TCR_CIC_MASK 0xFF000000u
bogdanm 87:6213f644d804 3828 #define RTC_TCR_CIC_SHIFT 24
bogdanm 87:6213f644d804 3829 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
bogdanm 87:6213f644d804 3830 /* CR Bit Fields */
bogdanm 87:6213f644d804 3831 #define RTC_CR_SWR_MASK 0x1u
bogdanm 87:6213f644d804 3832 #define RTC_CR_SWR_SHIFT 0
bogdanm 87:6213f644d804 3833 #define RTC_CR_WPE_MASK 0x2u
bogdanm 87:6213f644d804 3834 #define RTC_CR_WPE_SHIFT 1
bogdanm 87:6213f644d804 3835 #define RTC_CR_SUP_MASK 0x4u
bogdanm 87:6213f644d804 3836 #define RTC_CR_SUP_SHIFT 2
bogdanm 87:6213f644d804 3837 #define RTC_CR_UM_MASK 0x8u
bogdanm 87:6213f644d804 3838 #define RTC_CR_UM_SHIFT 3
bogdanm 87:6213f644d804 3839 #define RTC_CR_OSCE_MASK 0x100u
bogdanm 87:6213f644d804 3840 #define RTC_CR_OSCE_SHIFT 8
bogdanm 87:6213f644d804 3841 #define RTC_CR_CLKO_MASK 0x200u
bogdanm 87:6213f644d804 3842 #define RTC_CR_CLKO_SHIFT 9
bogdanm 87:6213f644d804 3843 #define RTC_CR_SC16P_MASK 0x400u
bogdanm 87:6213f644d804 3844 #define RTC_CR_SC16P_SHIFT 10
bogdanm 87:6213f644d804 3845 #define RTC_CR_SC8P_MASK 0x800u
bogdanm 87:6213f644d804 3846 #define RTC_CR_SC8P_SHIFT 11
bogdanm 87:6213f644d804 3847 #define RTC_CR_SC4P_MASK 0x1000u
bogdanm 87:6213f644d804 3848 #define RTC_CR_SC4P_SHIFT 12
bogdanm 87:6213f644d804 3849 #define RTC_CR_SC2P_MASK 0x2000u
bogdanm 87:6213f644d804 3850 #define RTC_CR_SC2P_SHIFT 13
bogdanm 87:6213f644d804 3851 /* SR Bit Fields */
bogdanm 87:6213f644d804 3852 #define RTC_SR_TIF_MASK 0x1u
bogdanm 87:6213f644d804 3853 #define RTC_SR_TIF_SHIFT 0
bogdanm 87:6213f644d804 3854 #define RTC_SR_TOF_MASK 0x2u
bogdanm 87:6213f644d804 3855 #define RTC_SR_TOF_SHIFT 1
bogdanm 87:6213f644d804 3856 #define RTC_SR_TAF_MASK 0x4u
bogdanm 87:6213f644d804 3857 #define RTC_SR_TAF_SHIFT 2
bogdanm 87:6213f644d804 3858 #define RTC_SR_TCE_MASK 0x10u
bogdanm 87:6213f644d804 3859 #define RTC_SR_TCE_SHIFT 4
bogdanm 87:6213f644d804 3860 /* LR Bit Fields */
bogdanm 87:6213f644d804 3861 #define RTC_LR_TCL_MASK 0x8u
bogdanm 87:6213f644d804 3862 #define RTC_LR_TCL_SHIFT 3
bogdanm 87:6213f644d804 3863 #define RTC_LR_CRL_MASK 0x10u
bogdanm 87:6213f644d804 3864 #define RTC_LR_CRL_SHIFT 4
bogdanm 87:6213f644d804 3865 #define RTC_LR_SRL_MASK 0x20u
bogdanm 87:6213f644d804 3866 #define RTC_LR_SRL_SHIFT 5
bogdanm 87:6213f644d804 3867 #define RTC_LR_LRL_MASK 0x40u
bogdanm 87:6213f644d804 3868 #define RTC_LR_LRL_SHIFT 6
bogdanm 87:6213f644d804 3869 /* IER Bit Fields */
bogdanm 87:6213f644d804 3870 #define RTC_IER_TIIE_MASK 0x1u
bogdanm 87:6213f644d804 3871 #define RTC_IER_TIIE_SHIFT 0
bogdanm 87:6213f644d804 3872 #define RTC_IER_TOIE_MASK 0x2u
bogdanm 87:6213f644d804 3873 #define RTC_IER_TOIE_SHIFT 1
bogdanm 87:6213f644d804 3874 #define RTC_IER_TAIE_MASK 0x4u
bogdanm 87:6213f644d804 3875 #define RTC_IER_TAIE_SHIFT 2
bogdanm 87:6213f644d804 3876 #define RTC_IER_TSIE_MASK 0x10u
bogdanm 87:6213f644d804 3877 #define RTC_IER_TSIE_SHIFT 4
bogdanm 87:6213f644d804 3878 /* WAR Bit Fields */
bogdanm 87:6213f644d804 3879 #define RTC_WAR_TSRW_MASK 0x1u
bogdanm 87:6213f644d804 3880 #define RTC_WAR_TSRW_SHIFT 0
bogdanm 87:6213f644d804 3881 #define RTC_WAR_TPRW_MASK 0x2u
bogdanm 87:6213f644d804 3882 #define RTC_WAR_TPRW_SHIFT 1
bogdanm 87:6213f644d804 3883 #define RTC_WAR_TARW_MASK 0x4u
bogdanm 87:6213f644d804 3884 #define RTC_WAR_TARW_SHIFT 2
bogdanm 87:6213f644d804 3885 #define RTC_WAR_TCRW_MASK 0x8u
bogdanm 87:6213f644d804 3886 #define RTC_WAR_TCRW_SHIFT 3
bogdanm 87:6213f644d804 3887 #define RTC_WAR_CRW_MASK 0x10u
bogdanm 87:6213f644d804 3888 #define RTC_WAR_CRW_SHIFT 4
bogdanm 87:6213f644d804 3889 #define RTC_WAR_SRW_MASK 0x20u
bogdanm 87:6213f644d804 3890 #define RTC_WAR_SRW_SHIFT 5
bogdanm 87:6213f644d804 3891 #define RTC_WAR_LRW_MASK 0x40u
bogdanm 87:6213f644d804 3892 #define RTC_WAR_LRW_SHIFT 6
bogdanm 87:6213f644d804 3893 #define RTC_WAR_IERW_MASK 0x80u
bogdanm 87:6213f644d804 3894 #define RTC_WAR_IERW_SHIFT 7
bogdanm 87:6213f644d804 3895 /* RAR Bit Fields */
bogdanm 87:6213f644d804 3896 #define RTC_RAR_TSRR_MASK 0x1u
bogdanm 87:6213f644d804 3897 #define RTC_RAR_TSRR_SHIFT 0
bogdanm 87:6213f644d804 3898 #define RTC_RAR_TPRR_MASK 0x2u
bogdanm 87:6213f644d804 3899 #define RTC_RAR_TPRR_SHIFT 1
bogdanm 87:6213f644d804 3900 #define RTC_RAR_TARR_MASK 0x4u
bogdanm 87:6213f644d804 3901 #define RTC_RAR_TARR_SHIFT 2
bogdanm 87:6213f644d804 3902 #define RTC_RAR_TCRR_MASK 0x8u
bogdanm 87:6213f644d804 3903 #define RTC_RAR_TCRR_SHIFT 3
bogdanm 87:6213f644d804 3904 #define RTC_RAR_CRR_MASK 0x10u
bogdanm 87:6213f644d804 3905 #define RTC_RAR_CRR_SHIFT 4
bogdanm 87:6213f644d804 3906 #define RTC_RAR_SRR_MASK 0x20u
bogdanm 87:6213f644d804 3907 #define RTC_RAR_SRR_SHIFT 5
bogdanm 87:6213f644d804 3908 #define RTC_RAR_LRR_MASK 0x40u
bogdanm 87:6213f644d804 3909 #define RTC_RAR_LRR_SHIFT 6
bogdanm 87:6213f644d804 3910 #define RTC_RAR_IERR_MASK 0x80u
bogdanm 87:6213f644d804 3911 #define RTC_RAR_IERR_SHIFT 7
bogdanm 87:6213f644d804 3912
bogdanm 87:6213f644d804 3913 /**
bogdanm 87:6213f644d804 3914 * @}
bogdanm 87:6213f644d804 3915 */ /* end of group RTC_Register_Masks */
bogdanm 87:6213f644d804 3916
bogdanm 87:6213f644d804 3917
bogdanm 87:6213f644d804 3918 /* RTC - Peripheral instance base addresses */
bogdanm 87:6213f644d804 3919 /** Peripheral RTC base address */
bogdanm 87:6213f644d804 3920 #define RTC_BASE (0x4003D000u)
bogdanm 87:6213f644d804 3921 /** Peripheral RTC base pointer */
bogdanm 87:6213f644d804 3922 #define RTC ((RTC_Type *)RTC_BASE)
bogdanm 87:6213f644d804 3923
bogdanm 87:6213f644d804 3924 /**
bogdanm 87:6213f644d804 3925 * @}
bogdanm 87:6213f644d804 3926 */ /* end of group RTC_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 3927
bogdanm 87:6213f644d804 3928
bogdanm 87:6213f644d804 3929 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3930 -- SIM Peripheral Access Layer
bogdanm 87:6213f644d804 3931 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3932
bogdanm 87:6213f644d804 3933 /**
bogdanm 87:6213f644d804 3934 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
bogdanm 87:6213f644d804 3935 * @{
bogdanm 87:6213f644d804 3936 */
bogdanm 87:6213f644d804 3937
bogdanm 87:6213f644d804 3938 /** SIM - Register Layout Typedef */
bogdanm 87:6213f644d804 3939 typedef struct {
bogdanm 87:6213f644d804 3940 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
bogdanm 87:6213f644d804 3941 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
bogdanm 87:6213f644d804 3942 uint8_t RESERVED_0[4092];
bogdanm 87:6213f644d804 3943 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
bogdanm 87:6213f644d804 3944 uint8_t RESERVED_1[4];
bogdanm 87:6213f644d804 3945 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
bogdanm 87:6213f644d804 3946 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
bogdanm 87:6213f644d804 3947 uint8_t RESERVED_2[4];
bogdanm 87:6213f644d804 3948 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
bogdanm 87:6213f644d804 3949 uint8_t RESERVED_3[8];
bogdanm 87:6213f644d804 3950 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
bogdanm 87:6213f644d804 3951 uint8_t RESERVED_4[12];
bogdanm 87:6213f644d804 3952 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
bogdanm 87:6213f644d804 3953 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
bogdanm 87:6213f644d804 3954 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
bogdanm 87:6213f644d804 3955 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
bogdanm 87:6213f644d804 3956 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
bogdanm 87:6213f644d804 3957 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
bogdanm 87:6213f644d804 3958 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
bogdanm 87:6213f644d804 3959 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
bogdanm 87:6213f644d804 3960 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
bogdanm 87:6213f644d804 3961 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
bogdanm 87:6213f644d804 3962 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
bogdanm 87:6213f644d804 3963 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
bogdanm 87:6213f644d804 3964 } SIM_Type;
bogdanm 87:6213f644d804 3965
bogdanm 87:6213f644d804 3966 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 3967 -- SIM Register Masks
bogdanm 87:6213f644d804 3968 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 3969
bogdanm 87:6213f644d804 3970 /**
bogdanm 87:6213f644d804 3971 * @addtogroup SIM_Register_Masks SIM Register Masks
bogdanm 87:6213f644d804 3972 * @{
bogdanm 87:6213f644d804 3973 */
bogdanm 87:6213f644d804 3974
bogdanm 87:6213f644d804 3975 /* SOPT1 Bit Fields */
bogdanm 87:6213f644d804 3976 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
bogdanm 87:6213f644d804 3977 #define SIM_SOPT1_RAMSIZE_SHIFT 12
bogdanm 87:6213f644d804 3978 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
bogdanm 87:6213f644d804 3979 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
bogdanm 87:6213f644d804 3980 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
bogdanm 87:6213f644d804 3981 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
bogdanm 87:6213f644d804 3982 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
bogdanm 87:6213f644d804 3983 #define SIM_SOPT1_USBVSTBY_SHIFT 29
bogdanm 87:6213f644d804 3984 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
bogdanm 87:6213f644d804 3985 #define SIM_SOPT1_USBSSTBY_SHIFT 30
bogdanm 87:6213f644d804 3986 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
bogdanm 87:6213f644d804 3987 #define SIM_SOPT1_USBREGEN_SHIFT 31
bogdanm 87:6213f644d804 3988 /* SOPT1CFG Bit Fields */
bogdanm 87:6213f644d804 3989 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
bogdanm 87:6213f644d804 3990 #define SIM_SOPT1CFG_URWE_SHIFT 24
bogdanm 87:6213f644d804 3991 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
bogdanm 87:6213f644d804 3992 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
bogdanm 87:6213f644d804 3993 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
bogdanm 87:6213f644d804 3994 #define SIM_SOPT1CFG_USSWE_SHIFT 26
bogdanm 87:6213f644d804 3995 /* SOPT2 Bit Fields */
bogdanm 87:6213f644d804 3996 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
bogdanm 87:6213f644d804 3997 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
bogdanm 87:6213f644d804 3998 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
bogdanm 87:6213f644d804 3999 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
bogdanm 87:6213f644d804 4000 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
bogdanm 87:6213f644d804 4001 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
bogdanm 87:6213f644d804 4002 #define SIM_SOPT2_PTD7PAD_SHIFT 11
bogdanm 87:6213f644d804 4003 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
bogdanm 87:6213f644d804 4004 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
bogdanm 87:6213f644d804 4005 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
bogdanm 87:6213f644d804 4006 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
bogdanm 87:6213f644d804 4007 #define SIM_SOPT2_USBSRC_MASK 0x40000u
bogdanm 87:6213f644d804 4008 #define SIM_SOPT2_USBSRC_SHIFT 18
bogdanm 87:6213f644d804 4009 /* SOPT4 Bit Fields */
bogdanm 87:6213f644d804 4010 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
bogdanm 87:6213f644d804 4011 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
bogdanm 87:6213f644d804 4012 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
bogdanm 87:6213f644d804 4013 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
bogdanm 87:6213f644d804 4014 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
bogdanm 87:6213f644d804 4015 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
bogdanm 87:6213f644d804 4016 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
bogdanm 87:6213f644d804 4017 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
bogdanm 87:6213f644d804 4018 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
bogdanm 87:6213f644d804 4019 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
bogdanm 87:6213f644d804 4020 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
bogdanm 87:6213f644d804 4021 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
bogdanm 87:6213f644d804 4022 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
bogdanm 87:6213f644d804 4023 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
bogdanm 87:6213f644d804 4024 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
bogdanm 87:6213f644d804 4025 /* SOPT5 Bit Fields */
bogdanm 87:6213f644d804 4026 #define SIM_SOPT5_UART0TXSRC_MASK 0x1u
bogdanm 87:6213f644d804 4027 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
bogdanm 87:6213f644d804 4028 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
bogdanm 87:6213f644d804 4029 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
bogdanm 87:6213f644d804 4030 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
bogdanm 87:6213f644d804 4031 #define SIM_SOPT5_UART1TXSRC_MASK 0x10u
bogdanm 87:6213f644d804 4032 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
bogdanm 87:6213f644d804 4033 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
bogdanm 87:6213f644d804 4034 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
bogdanm 87:6213f644d804 4035 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
bogdanm 87:6213f644d804 4036 /* SOPT7 Bit Fields */
bogdanm 87:6213f644d804 4037 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
bogdanm 87:6213f644d804 4038 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
bogdanm 87:6213f644d804 4039 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
bogdanm 87:6213f644d804 4040 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
bogdanm 87:6213f644d804 4041 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
bogdanm 87:6213f644d804 4042 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
bogdanm 87:6213f644d804 4043 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
bogdanm 87:6213f644d804 4044 /* SDID Bit Fields */
bogdanm 87:6213f644d804 4045 #define SIM_SDID_PINID_MASK 0xFu
bogdanm 87:6213f644d804 4046 #define SIM_SDID_PINID_SHIFT 0
bogdanm 87:6213f644d804 4047 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
bogdanm 87:6213f644d804 4048 #define SIM_SDID_FAMID_MASK 0x70u
bogdanm 87:6213f644d804 4049 #define SIM_SDID_FAMID_SHIFT 4
bogdanm 87:6213f644d804 4050 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
bogdanm 87:6213f644d804 4051 #define SIM_SDID_REVID_MASK 0xF000u
bogdanm 87:6213f644d804 4052 #define SIM_SDID_REVID_SHIFT 12
bogdanm 87:6213f644d804 4053 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
bogdanm 87:6213f644d804 4054 /* SCGC4 Bit Fields */
bogdanm 87:6213f644d804 4055 #define SIM_SCGC4_EWM_MASK 0x2u
bogdanm 87:6213f644d804 4056 #define SIM_SCGC4_EWM_SHIFT 1
bogdanm 87:6213f644d804 4057 #define SIM_SCGC4_CMT_MASK 0x4u
bogdanm 87:6213f644d804 4058 #define SIM_SCGC4_CMT_SHIFT 2
bogdanm 87:6213f644d804 4059 #define SIM_SCGC4_I2C0_MASK 0x40u
bogdanm 87:6213f644d804 4060 #define SIM_SCGC4_I2C0_SHIFT 6
bogdanm 87:6213f644d804 4061 #define SIM_SCGC4_UART0_MASK 0x400u
bogdanm 87:6213f644d804 4062 #define SIM_SCGC4_UART0_SHIFT 10
bogdanm 87:6213f644d804 4063 #define SIM_SCGC4_UART1_MASK 0x800u
bogdanm 87:6213f644d804 4064 #define SIM_SCGC4_UART1_SHIFT 11
bogdanm 87:6213f644d804 4065 #define SIM_SCGC4_UART2_MASK 0x1000u
bogdanm 87:6213f644d804 4066 #define SIM_SCGC4_UART2_SHIFT 12
bogdanm 87:6213f644d804 4067 #define SIM_SCGC4_USBOTG_MASK 0x40000u
bogdanm 87:6213f644d804 4068 #define SIM_SCGC4_USBOTG_SHIFT 18
bogdanm 87:6213f644d804 4069 #define SIM_SCGC4_CMP_MASK 0x80000u
bogdanm 87:6213f644d804 4070 #define SIM_SCGC4_CMP_SHIFT 19
bogdanm 87:6213f644d804 4071 #define SIM_SCGC4_VREF_MASK 0x100000u
bogdanm 87:6213f644d804 4072 #define SIM_SCGC4_VREF_SHIFT 20
bogdanm 87:6213f644d804 4073 /* SCGC5 Bit Fields */
bogdanm 87:6213f644d804 4074 #define SIM_SCGC5_LPTIMER_MASK 0x1u
bogdanm 87:6213f644d804 4075 #define SIM_SCGC5_LPTIMER_SHIFT 0
bogdanm 87:6213f644d804 4076 #define SIM_SCGC5_TSI_MASK 0x20u
bogdanm 87:6213f644d804 4077 #define SIM_SCGC5_TSI_SHIFT 5
bogdanm 87:6213f644d804 4078 #define SIM_SCGC5_PORTA_MASK 0x200u
bogdanm 87:6213f644d804 4079 #define SIM_SCGC5_PORTA_SHIFT 9
bogdanm 87:6213f644d804 4080 #define SIM_SCGC5_PORTB_MASK 0x400u
bogdanm 87:6213f644d804 4081 #define SIM_SCGC5_PORTB_SHIFT 10
bogdanm 87:6213f644d804 4082 #define SIM_SCGC5_PORTC_MASK 0x800u
bogdanm 87:6213f644d804 4083 #define SIM_SCGC5_PORTC_SHIFT 11
bogdanm 87:6213f644d804 4084 #define SIM_SCGC5_PORTD_MASK 0x1000u
bogdanm 87:6213f644d804 4085 #define SIM_SCGC5_PORTD_SHIFT 12
bogdanm 87:6213f644d804 4086 #define SIM_SCGC5_PORTE_MASK 0x2000u
bogdanm 87:6213f644d804 4087 #define SIM_SCGC5_PORTE_SHIFT 13
bogdanm 87:6213f644d804 4088 /* SCGC6 Bit Fields */
bogdanm 87:6213f644d804 4089 #define SIM_SCGC6_FTFL_MASK 0x1u
bogdanm 87:6213f644d804 4090 #define SIM_SCGC6_FTFL_SHIFT 0
bogdanm 87:6213f644d804 4091 #define SIM_SCGC6_DMAMUX_MASK 0x2u
bogdanm 87:6213f644d804 4092 #define SIM_SCGC6_DMAMUX_SHIFT 1
bogdanm 87:6213f644d804 4093 #define SIM_SCGC6_SPI0_MASK 0x1000u
bogdanm 87:6213f644d804 4094 #define SIM_SCGC6_SPI0_SHIFT 12
bogdanm 87:6213f644d804 4095 #define SIM_SCGC6_I2S_MASK 0x8000u
bogdanm 87:6213f644d804 4096 #define SIM_SCGC6_I2S_SHIFT 15
bogdanm 87:6213f644d804 4097 #define SIM_SCGC6_CRC_MASK 0x40000u
bogdanm 87:6213f644d804 4098 #define SIM_SCGC6_CRC_SHIFT 18
bogdanm 87:6213f644d804 4099 #define SIM_SCGC6_USBDCD_MASK 0x200000u
bogdanm 87:6213f644d804 4100 #define SIM_SCGC6_USBDCD_SHIFT 21
bogdanm 87:6213f644d804 4101 #define SIM_SCGC6_PDB_MASK 0x400000u
bogdanm 87:6213f644d804 4102 #define SIM_SCGC6_PDB_SHIFT 22
bogdanm 87:6213f644d804 4103 #define SIM_SCGC6_PIT_MASK 0x800000u
bogdanm 87:6213f644d804 4104 #define SIM_SCGC6_PIT_SHIFT 23
bogdanm 87:6213f644d804 4105 #define SIM_SCGC6_FTM0_MASK 0x1000000u
bogdanm 87:6213f644d804 4106 #define SIM_SCGC6_FTM0_SHIFT 24
bogdanm 87:6213f644d804 4107 #define SIM_SCGC6_FTM1_MASK 0x2000000u
bogdanm 87:6213f644d804 4108 #define SIM_SCGC6_FTM1_SHIFT 25
bogdanm 87:6213f644d804 4109 #define SIM_SCGC6_ADC0_MASK 0x8000000u
bogdanm 87:6213f644d804 4110 #define SIM_SCGC6_ADC0_SHIFT 27
bogdanm 87:6213f644d804 4111 #define SIM_SCGC6_RTC_MASK 0x20000000u
bogdanm 87:6213f644d804 4112 #define SIM_SCGC6_RTC_SHIFT 29
bogdanm 87:6213f644d804 4113 /* SCGC7 Bit Fields */
bogdanm 87:6213f644d804 4114 #define SIM_SCGC7_DMA_MASK 0x2u
bogdanm 87:6213f644d804 4115 #define SIM_SCGC7_DMA_SHIFT 1
bogdanm 87:6213f644d804 4116 /* CLKDIV1 Bit Fields */
bogdanm 87:6213f644d804 4117 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
bogdanm 87:6213f644d804 4118 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
bogdanm 87:6213f644d804 4119 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
bogdanm 87:6213f644d804 4120 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
bogdanm 87:6213f644d804 4121 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
bogdanm 87:6213f644d804 4122 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
bogdanm 87:6213f644d804 4123 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
bogdanm 87:6213f644d804 4124 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
bogdanm 87:6213f644d804 4125 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
bogdanm 87:6213f644d804 4126 /* CLKDIV2 Bit Fields */
bogdanm 87:6213f644d804 4127 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
bogdanm 87:6213f644d804 4128 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
bogdanm 87:6213f644d804 4129 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
bogdanm 87:6213f644d804 4130 #define SIM_CLKDIV2_USBDIV_SHIFT 1
bogdanm 87:6213f644d804 4131 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
bogdanm 87:6213f644d804 4132 /* FCFG1 Bit Fields */
bogdanm 87:6213f644d804 4133 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
bogdanm 87:6213f644d804 4134 #define SIM_FCFG1_FLASHDIS_SHIFT 0
bogdanm 87:6213f644d804 4135 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
bogdanm 87:6213f644d804 4136 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
bogdanm 87:6213f644d804 4137 #define SIM_FCFG1_DEPART_MASK 0xF00u
bogdanm 87:6213f644d804 4138 #define SIM_FCFG1_DEPART_SHIFT 8
bogdanm 87:6213f644d804 4139 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
bogdanm 87:6213f644d804 4140 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
bogdanm 87:6213f644d804 4141 #define SIM_FCFG1_EESIZE_SHIFT 16
bogdanm 87:6213f644d804 4142 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
bogdanm 87:6213f644d804 4143 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
bogdanm 87:6213f644d804 4144 #define SIM_FCFG1_PFSIZE_SHIFT 24
bogdanm 87:6213f644d804 4145 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
bogdanm 87:6213f644d804 4146 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
bogdanm 87:6213f644d804 4147 #define SIM_FCFG1_NVMSIZE_SHIFT 28
bogdanm 87:6213f644d804 4148 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
bogdanm 87:6213f644d804 4149 /* FCFG2 Bit Fields */
bogdanm 87:6213f644d804 4150 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
bogdanm 87:6213f644d804 4151 #define SIM_FCFG2_MAXADDR1_SHIFT 16
bogdanm 87:6213f644d804 4152 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
bogdanm 87:6213f644d804 4153 #define SIM_FCFG2_PFLSH_MASK 0x800000u
bogdanm 87:6213f644d804 4154 #define SIM_FCFG2_PFLSH_SHIFT 23
bogdanm 87:6213f644d804 4155 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
bogdanm 87:6213f644d804 4156 #define SIM_FCFG2_MAXADDR0_SHIFT 24
bogdanm 87:6213f644d804 4157 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
bogdanm 87:6213f644d804 4158 /* UIDH Bit Fields */
bogdanm 87:6213f644d804 4159 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4160 #define SIM_UIDH_UID_SHIFT 0
bogdanm 87:6213f644d804 4161 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
bogdanm 87:6213f644d804 4162 /* UIDMH Bit Fields */
bogdanm 87:6213f644d804 4163 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4164 #define SIM_UIDMH_UID_SHIFT 0
bogdanm 87:6213f644d804 4165 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
bogdanm 87:6213f644d804 4166 /* UIDML Bit Fields */
bogdanm 87:6213f644d804 4167 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4168 #define SIM_UIDML_UID_SHIFT 0
bogdanm 87:6213f644d804 4169 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
bogdanm 87:6213f644d804 4170 /* UIDL Bit Fields */
bogdanm 87:6213f644d804 4171 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4172 #define SIM_UIDL_UID_SHIFT 0
bogdanm 87:6213f644d804 4173 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
bogdanm 87:6213f644d804 4174
bogdanm 87:6213f644d804 4175 /**
bogdanm 87:6213f644d804 4176 * @}
bogdanm 87:6213f644d804 4177 */ /* end of group SIM_Register_Masks */
bogdanm 87:6213f644d804 4178
bogdanm 87:6213f644d804 4179
bogdanm 87:6213f644d804 4180 /* SIM - Peripheral instance base addresses */
bogdanm 87:6213f644d804 4181 /** Peripheral SIM base address */
bogdanm 87:6213f644d804 4182 #define SIM_BASE (0x40047000u)
bogdanm 87:6213f644d804 4183 /** Peripheral SIM base pointer */
bogdanm 87:6213f644d804 4184 #define SIM ((SIM_Type *)SIM_BASE)
bogdanm 87:6213f644d804 4185
bogdanm 87:6213f644d804 4186 /**
bogdanm 87:6213f644d804 4187 * @}
bogdanm 87:6213f644d804 4188 */ /* end of group SIM_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 4189
bogdanm 87:6213f644d804 4190
bogdanm 87:6213f644d804 4191 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 4192 -- SMC Peripheral Access Layer
bogdanm 87:6213f644d804 4193 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 4194
bogdanm 87:6213f644d804 4195 /**
bogdanm 87:6213f644d804 4196 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
bogdanm 87:6213f644d804 4197 * @{
bogdanm 87:6213f644d804 4198 */
bogdanm 87:6213f644d804 4199
bogdanm 87:6213f644d804 4200 /** SMC - Register Layout Typedef */
bogdanm 87:6213f644d804 4201 typedef struct {
bogdanm 87:6213f644d804 4202 __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
bogdanm 87:6213f644d804 4203 __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
bogdanm 87:6213f644d804 4204 __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
bogdanm 87:6213f644d804 4205 __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
bogdanm 87:6213f644d804 4206 } SMC_Type;
bogdanm 87:6213f644d804 4207
bogdanm 87:6213f644d804 4208 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 4209 -- SMC Register Masks
bogdanm 87:6213f644d804 4210 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 4211
bogdanm 87:6213f644d804 4212 /**
bogdanm 87:6213f644d804 4213 * @addtogroup SMC_Register_Masks SMC Register Masks
bogdanm 87:6213f644d804 4214 * @{
bogdanm 87:6213f644d804 4215 */
bogdanm 87:6213f644d804 4216
bogdanm 87:6213f644d804 4217 /* PMPROT Bit Fields */
bogdanm 87:6213f644d804 4218 #define SMC_PMPROT_AVLLS_MASK 0x2u
bogdanm 87:6213f644d804 4219 #define SMC_PMPROT_AVLLS_SHIFT 1
bogdanm 87:6213f644d804 4220 #define SMC_PMPROT_ALLS_MASK 0x8u
bogdanm 87:6213f644d804 4221 #define SMC_PMPROT_ALLS_SHIFT 3
bogdanm 87:6213f644d804 4222 #define SMC_PMPROT_AVLP_MASK 0x20u
bogdanm 87:6213f644d804 4223 #define SMC_PMPROT_AVLP_SHIFT 5
bogdanm 87:6213f644d804 4224 /* PMCTRL Bit Fields */
bogdanm 87:6213f644d804 4225 #define SMC_PMCTRL_STOPM_MASK 0x7u
bogdanm 87:6213f644d804 4226 #define SMC_PMCTRL_STOPM_SHIFT 0
bogdanm 87:6213f644d804 4227 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
bogdanm 87:6213f644d804 4228 #define SMC_PMCTRL_STOPA_MASK 0x8u
bogdanm 87:6213f644d804 4229 #define SMC_PMCTRL_STOPA_SHIFT 3
bogdanm 87:6213f644d804 4230 #define SMC_PMCTRL_RUNM_MASK 0x60u
bogdanm 87:6213f644d804 4231 #define SMC_PMCTRL_RUNM_SHIFT 5
bogdanm 87:6213f644d804 4232 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
bogdanm 87:6213f644d804 4233 #define SMC_PMCTRL_LPWUI_MASK 0x80u
bogdanm 87:6213f644d804 4234 #define SMC_PMCTRL_LPWUI_SHIFT 7
bogdanm 87:6213f644d804 4235 /* VLLSCTRL Bit Fields */
bogdanm 87:6213f644d804 4236 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
bogdanm 87:6213f644d804 4237 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
bogdanm 87:6213f644d804 4238 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
bogdanm 87:6213f644d804 4239 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
bogdanm 87:6213f644d804 4240 #define SMC_VLLSCTRL_PORPO_SHIFT 5
bogdanm 87:6213f644d804 4241 /* PMSTAT Bit Fields */
bogdanm 87:6213f644d804 4242 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
bogdanm 87:6213f644d804 4243 #define SMC_PMSTAT_PMSTAT_SHIFT 0
bogdanm 87:6213f644d804 4244 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
bogdanm 87:6213f644d804 4245
bogdanm 87:6213f644d804 4246 /**
bogdanm 87:6213f644d804 4247 * @}
bogdanm 87:6213f644d804 4248 */ /* end of group SMC_Register_Masks */
bogdanm 87:6213f644d804 4249
bogdanm 87:6213f644d804 4250
bogdanm 87:6213f644d804 4251 /* SMC - Peripheral instance base addresses */
bogdanm 87:6213f644d804 4252 /** Peripheral SMC base address */
bogdanm 87:6213f644d804 4253 #define SMC_BASE (0x4007E000u)
bogdanm 87:6213f644d804 4254 /** Peripheral SMC base pointer */
bogdanm 87:6213f644d804 4255 #define SMC ((SMC_Type *)SMC_BASE)
bogdanm 87:6213f644d804 4256
bogdanm 87:6213f644d804 4257 /**
bogdanm 87:6213f644d804 4258 * @}
bogdanm 87:6213f644d804 4259 */ /* end of group SMC_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 4260
bogdanm 87:6213f644d804 4261
bogdanm 87:6213f644d804 4262 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 4263 -- SPI Peripheral Access Layer
bogdanm 87:6213f644d804 4264 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 4265
bogdanm 87:6213f644d804 4266 /**
bogdanm 87:6213f644d804 4267 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
bogdanm 87:6213f644d804 4268 * @{
bogdanm 87:6213f644d804 4269 */
bogdanm 87:6213f644d804 4270
bogdanm 87:6213f644d804 4271 /** SPI - Register Layout Typedef */
bogdanm 87:6213f644d804 4272 typedef struct {
bogdanm 87:6213f644d804 4273 __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
bogdanm 87:6213f644d804 4274 uint8_t RESERVED_0[4];
bogdanm 87:6213f644d804 4275 __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
bogdanm 87:6213f644d804 4276 union { /* offset: 0xC */
bogdanm 87:6213f644d804 4277 __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
bogdanm 87:6213f644d804 4278 __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
bogdanm 87:6213f644d804 4279 };
bogdanm 87:6213f644d804 4280 uint8_t RESERVED_1[24];
bogdanm 87:6213f644d804 4281 __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
bogdanm 87:6213f644d804 4282 __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
bogdanm 87:6213f644d804 4283 union { /* offset: 0x34 */
bogdanm 87:6213f644d804 4284 __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
bogdanm 87:6213f644d804 4285 __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
bogdanm 87:6213f644d804 4286 };
bogdanm 87:6213f644d804 4287 __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
bogdanm 87:6213f644d804 4288 __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
bogdanm 87:6213f644d804 4289 __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
bogdanm 87:6213f644d804 4290 __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
bogdanm 87:6213f644d804 4291 __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
bogdanm 87:6213f644d804 4292 uint8_t RESERVED_2[48];
bogdanm 87:6213f644d804 4293 __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
bogdanm 87:6213f644d804 4294 __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
bogdanm 87:6213f644d804 4295 __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
bogdanm 87:6213f644d804 4296 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
bogdanm 87:6213f644d804 4297 } SPI_Type;
bogdanm 87:6213f644d804 4298
bogdanm 87:6213f644d804 4299 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 4300 -- SPI Register Masks
bogdanm 87:6213f644d804 4301 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 4302
bogdanm 87:6213f644d804 4303 /**
bogdanm 87:6213f644d804 4304 * @addtogroup SPI_Register_Masks SPI Register Masks
bogdanm 87:6213f644d804 4305 * @{
bogdanm 87:6213f644d804 4306 */
bogdanm 87:6213f644d804 4307
bogdanm 87:6213f644d804 4308 /* MCR Bit Fields */
bogdanm 87:6213f644d804 4309 #define SPI_MCR_HALT_MASK 0x1u
bogdanm 87:6213f644d804 4310 #define SPI_MCR_HALT_SHIFT 0
bogdanm 87:6213f644d804 4311 #define SPI_MCR_SMPL_PT_MASK 0x300u
bogdanm 87:6213f644d804 4312 #define SPI_MCR_SMPL_PT_SHIFT 8
bogdanm 87:6213f644d804 4313 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
bogdanm 87:6213f644d804 4314 #define SPI_MCR_CLR_RXF_MASK 0x400u
bogdanm 87:6213f644d804 4315 #define SPI_MCR_CLR_RXF_SHIFT 10
bogdanm 87:6213f644d804 4316 #define SPI_MCR_CLR_TXF_MASK 0x800u
bogdanm 87:6213f644d804 4317 #define SPI_MCR_CLR_TXF_SHIFT 11
bogdanm 87:6213f644d804 4318 #define SPI_MCR_DIS_RXF_MASK 0x1000u
bogdanm 87:6213f644d804 4319 #define SPI_MCR_DIS_RXF_SHIFT 12
bogdanm 87:6213f644d804 4320 #define SPI_MCR_DIS_TXF_MASK 0x2000u
bogdanm 87:6213f644d804 4321 #define SPI_MCR_DIS_TXF_SHIFT 13
bogdanm 87:6213f644d804 4322 #define SPI_MCR_MDIS_MASK 0x4000u
bogdanm 87:6213f644d804 4323 #define SPI_MCR_MDIS_SHIFT 14
bogdanm 87:6213f644d804 4324 #define SPI_MCR_DOZE_MASK 0x8000u
bogdanm 87:6213f644d804 4325 #define SPI_MCR_DOZE_SHIFT 15
bogdanm 87:6213f644d804 4326 #define SPI_MCR_PCSIS_MASK 0x3F0000u
bogdanm 87:6213f644d804 4327 #define SPI_MCR_PCSIS_SHIFT 16
bogdanm 87:6213f644d804 4328 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
bogdanm 87:6213f644d804 4329 #define SPI_MCR_ROOE_MASK 0x1000000u
bogdanm 87:6213f644d804 4330 #define SPI_MCR_ROOE_SHIFT 24
bogdanm 87:6213f644d804 4331 #define SPI_MCR_PCSSE_MASK 0x2000000u
bogdanm 87:6213f644d804 4332 #define SPI_MCR_PCSSE_SHIFT 25
bogdanm 87:6213f644d804 4333 #define SPI_MCR_MTFE_MASK 0x4000000u
bogdanm 87:6213f644d804 4334 #define SPI_MCR_MTFE_SHIFT 26
bogdanm 87:6213f644d804 4335 #define SPI_MCR_FRZ_MASK 0x8000000u
bogdanm 87:6213f644d804 4336 #define SPI_MCR_FRZ_SHIFT 27
bogdanm 87:6213f644d804 4337 #define SPI_MCR_DCONF_MASK 0x30000000u
bogdanm 87:6213f644d804 4338 #define SPI_MCR_DCONF_SHIFT 28
bogdanm 87:6213f644d804 4339 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
bogdanm 87:6213f644d804 4340 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
bogdanm 87:6213f644d804 4341 #define SPI_MCR_CONT_SCKE_SHIFT 30
bogdanm 87:6213f644d804 4342 #define SPI_MCR_MSTR_MASK 0x80000000u
bogdanm 87:6213f644d804 4343 #define SPI_MCR_MSTR_SHIFT 31
bogdanm 87:6213f644d804 4344 /* TCR Bit Fields */
bogdanm 87:6213f644d804 4345 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4346 #define SPI_TCR_SPI_TCNT_SHIFT 16
bogdanm 87:6213f644d804 4347 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
bogdanm 87:6213f644d804 4348 /* CTAR Bit Fields */
bogdanm 87:6213f644d804 4349 #define SPI_CTAR_BR_MASK 0xFu
bogdanm 87:6213f644d804 4350 #define SPI_CTAR_BR_SHIFT 0
bogdanm 87:6213f644d804 4351 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
bogdanm 87:6213f644d804 4352 #define SPI_CTAR_DT_MASK 0xF0u
bogdanm 87:6213f644d804 4353 #define SPI_CTAR_DT_SHIFT 4
bogdanm 87:6213f644d804 4354 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
bogdanm 87:6213f644d804 4355 #define SPI_CTAR_ASC_MASK 0xF00u
bogdanm 87:6213f644d804 4356 #define SPI_CTAR_ASC_SHIFT 8
bogdanm 87:6213f644d804 4357 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
bogdanm 87:6213f644d804 4358 #define SPI_CTAR_CSSCK_MASK 0xF000u
bogdanm 87:6213f644d804 4359 #define SPI_CTAR_CSSCK_SHIFT 12
bogdanm 87:6213f644d804 4360 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
bogdanm 87:6213f644d804 4361 #define SPI_CTAR_PBR_MASK 0x30000u
bogdanm 87:6213f644d804 4362 #define SPI_CTAR_PBR_SHIFT 16
bogdanm 87:6213f644d804 4363 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
bogdanm 87:6213f644d804 4364 #define SPI_CTAR_PDT_MASK 0xC0000u
bogdanm 87:6213f644d804 4365 #define SPI_CTAR_PDT_SHIFT 18
bogdanm 87:6213f644d804 4366 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
bogdanm 87:6213f644d804 4367 #define SPI_CTAR_PASC_MASK 0x300000u
bogdanm 87:6213f644d804 4368 #define SPI_CTAR_PASC_SHIFT 20
bogdanm 87:6213f644d804 4369 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
bogdanm 87:6213f644d804 4370 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
bogdanm 87:6213f644d804 4371 #define SPI_CTAR_PCSSCK_SHIFT 22
bogdanm 87:6213f644d804 4372 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
bogdanm 87:6213f644d804 4373 #define SPI_CTAR_LSBFE_MASK 0x1000000u
bogdanm 87:6213f644d804 4374 #define SPI_CTAR_LSBFE_SHIFT 24
bogdanm 87:6213f644d804 4375 #define SPI_CTAR_CPHA_MASK 0x2000000u
bogdanm 87:6213f644d804 4376 #define SPI_CTAR_CPHA_SHIFT 25
bogdanm 87:6213f644d804 4377 #define SPI_CTAR_CPOL_MASK 0x4000000u
bogdanm 87:6213f644d804 4378 #define SPI_CTAR_CPOL_SHIFT 26
bogdanm 87:6213f644d804 4379 #define SPI_CTAR_FMSZ_MASK 0x78000000u
bogdanm 87:6213f644d804 4380 #define SPI_CTAR_FMSZ_SHIFT 27
bogdanm 87:6213f644d804 4381 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
bogdanm 87:6213f644d804 4382 #define SPI_CTAR_DBR_MASK 0x80000000u
bogdanm 87:6213f644d804 4383 #define SPI_CTAR_DBR_SHIFT 31
bogdanm 87:6213f644d804 4384 /* CTAR_SLAVE Bit Fields */
bogdanm 87:6213f644d804 4385 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
bogdanm 87:6213f644d804 4386 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
bogdanm 87:6213f644d804 4387 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
bogdanm 87:6213f644d804 4388 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
bogdanm 87:6213f644d804 4389 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
bogdanm 87:6213f644d804 4390 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
bogdanm 87:6213f644d804 4391 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
bogdanm 87:6213f644d804 4392 /* SR Bit Fields */
bogdanm 87:6213f644d804 4393 #define SPI_SR_POPNXTPTR_MASK 0xFu
bogdanm 87:6213f644d804 4394 #define SPI_SR_POPNXTPTR_SHIFT 0
bogdanm 87:6213f644d804 4395 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
bogdanm 87:6213f644d804 4396 #define SPI_SR_RXCTR_MASK 0xF0u
bogdanm 87:6213f644d804 4397 #define SPI_SR_RXCTR_SHIFT 4
bogdanm 87:6213f644d804 4398 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
bogdanm 87:6213f644d804 4399 #define SPI_SR_TXNXTPTR_MASK 0xF00u
bogdanm 87:6213f644d804 4400 #define SPI_SR_TXNXTPTR_SHIFT 8
bogdanm 87:6213f644d804 4401 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
bogdanm 87:6213f644d804 4402 #define SPI_SR_TXCTR_MASK 0xF000u
bogdanm 87:6213f644d804 4403 #define SPI_SR_TXCTR_SHIFT 12
bogdanm 87:6213f644d804 4404 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
bogdanm 87:6213f644d804 4405 #define SPI_SR_RFDF_MASK 0x20000u
bogdanm 87:6213f644d804 4406 #define SPI_SR_RFDF_SHIFT 17
bogdanm 87:6213f644d804 4407 #define SPI_SR_RFOF_MASK 0x80000u
bogdanm 87:6213f644d804 4408 #define SPI_SR_RFOF_SHIFT 19
bogdanm 87:6213f644d804 4409 #define SPI_SR_TFFF_MASK 0x2000000u
bogdanm 87:6213f644d804 4410 #define SPI_SR_TFFF_SHIFT 25
bogdanm 87:6213f644d804 4411 #define SPI_SR_TFUF_MASK 0x8000000u
bogdanm 87:6213f644d804 4412 #define SPI_SR_TFUF_SHIFT 27
bogdanm 87:6213f644d804 4413 #define SPI_SR_EOQF_MASK 0x10000000u
bogdanm 87:6213f644d804 4414 #define SPI_SR_EOQF_SHIFT 28
bogdanm 87:6213f644d804 4415 #define SPI_SR_TXRXS_MASK 0x40000000u
bogdanm 87:6213f644d804 4416 #define SPI_SR_TXRXS_SHIFT 30
bogdanm 87:6213f644d804 4417 #define SPI_SR_TCF_MASK 0x80000000u
bogdanm 87:6213f644d804 4418 #define SPI_SR_TCF_SHIFT 31
bogdanm 87:6213f644d804 4419 /* RSER Bit Fields */
bogdanm 87:6213f644d804 4420 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
bogdanm 87:6213f644d804 4421 #define SPI_RSER_RFDF_DIRS_SHIFT 16
bogdanm 87:6213f644d804 4422 #define SPI_RSER_RFDF_RE_MASK 0x20000u
bogdanm 87:6213f644d804 4423 #define SPI_RSER_RFDF_RE_SHIFT 17
bogdanm 87:6213f644d804 4424 #define SPI_RSER_RFOF_RE_MASK 0x80000u
bogdanm 87:6213f644d804 4425 #define SPI_RSER_RFOF_RE_SHIFT 19
bogdanm 87:6213f644d804 4426 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
bogdanm 87:6213f644d804 4427 #define SPI_RSER_TFFF_DIRS_SHIFT 24
bogdanm 87:6213f644d804 4428 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
bogdanm 87:6213f644d804 4429 #define SPI_RSER_TFFF_RE_SHIFT 25
bogdanm 87:6213f644d804 4430 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
bogdanm 87:6213f644d804 4431 #define SPI_RSER_TFUF_RE_SHIFT 27
bogdanm 87:6213f644d804 4432 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
bogdanm 87:6213f644d804 4433 #define SPI_RSER_EOQF_RE_SHIFT 28
bogdanm 87:6213f644d804 4434 #define SPI_RSER_TCF_RE_MASK 0x80000000u
bogdanm 87:6213f644d804 4435 #define SPI_RSER_TCF_RE_SHIFT 31
bogdanm 87:6213f644d804 4436 /* PUSHR Bit Fields */
bogdanm 87:6213f644d804 4437 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
bogdanm 87:6213f644d804 4438 #define SPI_PUSHR_TXDATA_SHIFT 0
bogdanm 87:6213f644d804 4439 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
bogdanm 87:6213f644d804 4440 #define SPI_PUSHR_PCS_MASK 0x3F0000u
bogdanm 87:6213f644d804 4441 #define SPI_PUSHR_PCS_SHIFT 16
bogdanm 87:6213f644d804 4442 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
bogdanm 87:6213f644d804 4443 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
bogdanm 87:6213f644d804 4444 #define SPI_PUSHR_CTCNT_SHIFT 26
bogdanm 87:6213f644d804 4445 #define SPI_PUSHR_EOQ_MASK 0x8000000u
bogdanm 87:6213f644d804 4446 #define SPI_PUSHR_EOQ_SHIFT 27
bogdanm 87:6213f644d804 4447 #define SPI_PUSHR_CTAS_MASK 0x70000000u
bogdanm 87:6213f644d804 4448 #define SPI_PUSHR_CTAS_SHIFT 28
bogdanm 87:6213f644d804 4449 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
bogdanm 87:6213f644d804 4450 #define SPI_PUSHR_CONT_MASK 0x80000000u
bogdanm 87:6213f644d804 4451 #define SPI_PUSHR_CONT_SHIFT 31
bogdanm 87:6213f644d804 4452 /* PUSHR_SLAVE Bit Fields */
bogdanm 87:6213f644d804 4453 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4454 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
bogdanm 87:6213f644d804 4455 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
bogdanm 87:6213f644d804 4456 /* POPR Bit Fields */
bogdanm 87:6213f644d804 4457 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4458 #define SPI_POPR_RXDATA_SHIFT 0
bogdanm 87:6213f644d804 4459 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
bogdanm 87:6213f644d804 4460 /* TXFR0 Bit Fields */
bogdanm 87:6213f644d804 4461 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
bogdanm 87:6213f644d804 4462 #define SPI_TXFR0_TXDATA_SHIFT 0
bogdanm 87:6213f644d804 4463 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
bogdanm 87:6213f644d804 4464 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4465 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
bogdanm 87:6213f644d804 4466 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
bogdanm 87:6213f644d804 4467 /* TXFR1 Bit Fields */
bogdanm 87:6213f644d804 4468 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
bogdanm 87:6213f644d804 4469 #define SPI_TXFR1_TXDATA_SHIFT 0
bogdanm 87:6213f644d804 4470 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
bogdanm 87:6213f644d804 4471 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4472 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
bogdanm 87:6213f644d804 4473 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
bogdanm 87:6213f644d804 4474 /* TXFR2 Bit Fields */
bogdanm 87:6213f644d804 4475 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
bogdanm 87:6213f644d804 4476 #define SPI_TXFR2_TXDATA_SHIFT 0
bogdanm 87:6213f644d804 4477 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
bogdanm 87:6213f644d804 4478 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4479 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
bogdanm 87:6213f644d804 4480 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
bogdanm 87:6213f644d804 4481 /* TXFR3 Bit Fields */
bogdanm 87:6213f644d804 4482 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
bogdanm 87:6213f644d804 4483 #define SPI_TXFR3_TXDATA_SHIFT 0
bogdanm 87:6213f644d804 4484 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
bogdanm 87:6213f644d804 4485 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4486 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
bogdanm 87:6213f644d804 4487 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
bogdanm 87:6213f644d804 4488 /* RXFR0 Bit Fields */
bogdanm 87:6213f644d804 4489 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4490 #define SPI_RXFR0_RXDATA_SHIFT 0
bogdanm 87:6213f644d804 4491 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
bogdanm 87:6213f644d804 4492 /* RXFR1 Bit Fields */
bogdanm 87:6213f644d804 4493 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4494 #define SPI_RXFR1_RXDATA_SHIFT 0
bogdanm 87:6213f644d804 4495 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
bogdanm 87:6213f644d804 4496 /* RXFR2 Bit Fields */
bogdanm 87:6213f644d804 4497 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4498 #define SPI_RXFR2_RXDATA_SHIFT 0
bogdanm 87:6213f644d804 4499 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
bogdanm 87:6213f644d804 4500 /* RXFR3 Bit Fields */
bogdanm 87:6213f644d804 4501 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
bogdanm 87:6213f644d804 4502 #define SPI_RXFR3_RXDATA_SHIFT 0
bogdanm 87:6213f644d804 4503 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
bogdanm 87:6213f644d804 4504
bogdanm 87:6213f644d804 4505 /**
bogdanm 87:6213f644d804 4506 * @}
bogdanm 87:6213f644d804 4507 */ /* end of group SPI_Register_Masks */
bogdanm 87:6213f644d804 4508
bogdanm 87:6213f644d804 4509
bogdanm 87:6213f644d804 4510 /* SPI - Peripheral instance base addresses */
bogdanm 87:6213f644d804 4511 /** Peripheral SPI0 base address */
bogdanm 87:6213f644d804 4512 #define SPI0_BASE (0x4002C000u)
bogdanm 87:6213f644d804 4513 /** Peripheral SPI0 base pointer */
bogdanm 87:6213f644d804 4514 #define SPI0 ((SPI_Type *)SPI0_BASE)
bogdanm 87:6213f644d804 4515
bogdanm 87:6213f644d804 4516 /**
bogdanm 87:6213f644d804 4517 * @}
bogdanm 87:6213f644d804 4518 */ /* end of group SPI_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 4519
bogdanm 87:6213f644d804 4520
bogdanm 87:6213f644d804 4521 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 4522 -- TSI Peripheral Access Layer
bogdanm 87:6213f644d804 4523 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 4524
bogdanm 87:6213f644d804 4525 /**
bogdanm 87:6213f644d804 4526 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
bogdanm 87:6213f644d804 4527 * @{
bogdanm 87:6213f644d804 4528 */
bogdanm 87:6213f644d804 4529
bogdanm 87:6213f644d804 4530 /** TSI - Register Layout Typedef */
bogdanm 87:6213f644d804 4531 typedef struct {
bogdanm 87:6213f644d804 4532 __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
bogdanm 87:6213f644d804 4533 __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
bogdanm 87:6213f644d804 4534 __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
bogdanm 87:6213f644d804 4535 __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
bogdanm 87:6213f644d804 4536 uint8_t RESERVED_0[240];
bogdanm 87:6213f644d804 4537 __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
bogdanm 87:6213f644d804 4538 __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
bogdanm 87:6213f644d804 4539 __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
bogdanm 87:6213f644d804 4540 __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
bogdanm 87:6213f644d804 4541 __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
bogdanm 87:6213f644d804 4542 __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
bogdanm 87:6213f644d804 4543 __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
bogdanm 87:6213f644d804 4544 __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
bogdanm 87:6213f644d804 4545 __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
bogdanm 87:6213f644d804 4546 } TSI_Type;
bogdanm 87:6213f644d804 4547
bogdanm 87:6213f644d804 4548 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 4549 -- TSI Register Masks
bogdanm 87:6213f644d804 4550 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 4551
bogdanm 87:6213f644d804 4552 /**
bogdanm 87:6213f644d804 4553 * @addtogroup TSI_Register_Masks TSI Register Masks
bogdanm 87:6213f644d804 4554 * @{
bogdanm 87:6213f644d804 4555 */
bogdanm 87:6213f644d804 4556
bogdanm 87:6213f644d804 4557 /* GENCS Bit Fields */
bogdanm 87:6213f644d804 4558 #define TSI_GENCS_STPE_MASK 0x1u
bogdanm 87:6213f644d804 4559 #define TSI_GENCS_STPE_SHIFT 0
bogdanm 87:6213f644d804 4560 #define TSI_GENCS_STM_MASK 0x2u
bogdanm 87:6213f644d804 4561 #define TSI_GENCS_STM_SHIFT 1
bogdanm 87:6213f644d804 4562 #define TSI_GENCS_ESOR_MASK 0x10u
bogdanm 87:6213f644d804 4563 #define TSI_GENCS_ESOR_SHIFT 4
bogdanm 87:6213f644d804 4564 #define TSI_GENCS_ERIE_MASK 0x20u
bogdanm 87:6213f644d804 4565 #define TSI_GENCS_ERIE_SHIFT 5
bogdanm 87:6213f644d804 4566 #define TSI_GENCS_TSIIE_MASK 0x40u
bogdanm 87:6213f644d804 4567 #define TSI_GENCS_TSIIE_SHIFT 6
bogdanm 87:6213f644d804 4568 #define TSI_GENCS_TSIEN_MASK 0x80u
bogdanm 87:6213f644d804 4569 #define TSI_GENCS_TSIEN_SHIFT 7
bogdanm 87:6213f644d804 4570 #define TSI_GENCS_SWTS_MASK 0x100u
bogdanm 87:6213f644d804 4571 #define TSI_GENCS_SWTS_SHIFT 8
bogdanm 87:6213f644d804 4572 #define TSI_GENCS_SCNIP_MASK 0x200u
bogdanm 87:6213f644d804 4573 #define TSI_GENCS_SCNIP_SHIFT 9
bogdanm 87:6213f644d804 4574 #define TSI_GENCS_OVRF_MASK 0x1000u
bogdanm 87:6213f644d804 4575 #define TSI_GENCS_OVRF_SHIFT 12
bogdanm 87:6213f644d804 4576 #define TSI_GENCS_EXTERF_MASK 0x2000u
bogdanm 87:6213f644d804 4577 #define TSI_GENCS_EXTERF_SHIFT 13
bogdanm 87:6213f644d804 4578 #define TSI_GENCS_OUTRGF_MASK 0x4000u
bogdanm 87:6213f644d804 4579 #define TSI_GENCS_OUTRGF_SHIFT 14
bogdanm 87:6213f644d804 4580 #define TSI_GENCS_EOSF_MASK 0x8000u
bogdanm 87:6213f644d804 4581 #define TSI_GENCS_EOSF_SHIFT 15
bogdanm 87:6213f644d804 4582 #define TSI_GENCS_PS_MASK 0x70000u
bogdanm 87:6213f644d804 4583 #define TSI_GENCS_PS_SHIFT 16
bogdanm 87:6213f644d804 4584 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
bogdanm 87:6213f644d804 4585 #define TSI_GENCS_NSCN_MASK 0xF80000u
bogdanm 87:6213f644d804 4586 #define TSI_GENCS_NSCN_SHIFT 19
bogdanm 87:6213f644d804 4587 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
bogdanm 87:6213f644d804 4588 #define TSI_GENCS_LPSCNITV_MASK 0xF000000u
bogdanm 87:6213f644d804 4589 #define TSI_GENCS_LPSCNITV_SHIFT 24
bogdanm 87:6213f644d804 4590 #define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
bogdanm 87:6213f644d804 4591 #define TSI_GENCS_LPCLKS_MASK 0x10000000u
bogdanm 87:6213f644d804 4592 #define TSI_GENCS_LPCLKS_SHIFT 28
bogdanm 87:6213f644d804 4593 /* SCANC Bit Fields */
bogdanm 87:6213f644d804 4594 #define TSI_SCANC_AMPSC_MASK 0x7u
bogdanm 87:6213f644d804 4595 #define TSI_SCANC_AMPSC_SHIFT 0
bogdanm 87:6213f644d804 4596 #define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
bogdanm 87:6213f644d804 4597 #define TSI_SCANC_AMCLKS_MASK 0x18u
bogdanm 87:6213f644d804 4598 #define TSI_SCANC_AMCLKS_SHIFT 3
bogdanm 87:6213f644d804 4599 #define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
bogdanm 87:6213f644d804 4600 #define TSI_SCANC_SMOD_MASK 0xFF00u
bogdanm 87:6213f644d804 4601 #define TSI_SCANC_SMOD_SHIFT 8
bogdanm 87:6213f644d804 4602 #define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
bogdanm 87:6213f644d804 4603 #define TSI_SCANC_EXTCHRG_MASK 0xF0000u
bogdanm 87:6213f644d804 4604 #define TSI_SCANC_EXTCHRG_SHIFT 16
bogdanm 87:6213f644d804 4605 #define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
bogdanm 87:6213f644d804 4606 #define TSI_SCANC_REFCHRG_MASK 0xF000000u
bogdanm 87:6213f644d804 4607 #define TSI_SCANC_REFCHRG_SHIFT 24
bogdanm 87:6213f644d804 4608 #define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
bogdanm 87:6213f644d804 4609 /* PEN Bit Fields */
bogdanm 87:6213f644d804 4610 #define TSI_PEN_PEN0_MASK 0x1u
bogdanm 87:6213f644d804 4611 #define TSI_PEN_PEN0_SHIFT 0
bogdanm 87:6213f644d804 4612 #define TSI_PEN_PEN1_MASK 0x2u
bogdanm 87:6213f644d804 4613 #define TSI_PEN_PEN1_SHIFT 1
bogdanm 87:6213f644d804 4614 #define TSI_PEN_PEN2_MASK 0x4u
bogdanm 87:6213f644d804 4615 #define TSI_PEN_PEN2_SHIFT 2
bogdanm 87:6213f644d804 4616 #define TSI_PEN_PEN3_MASK 0x8u
bogdanm 87:6213f644d804 4617 #define TSI_PEN_PEN3_SHIFT 3
bogdanm 87:6213f644d804 4618 #define TSI_PEN_PEN4_MASK 0x10u
bogdanm 87:6213f644d804 4619 #define TSI_PEN_PEN4_SHIFT 4
bogdanm 87:6213f644d804 4620 #define TSI_PEN_PEN5_MASK 0x20u
bogdanm 87:6213f644d804 4621 #define TSI_PEN_PEN5_SHIFT 5
bogdanm 87:6213f644d804 4622 #define TSI_PEN_PEN6_MASK 0x40u
bogdanm 87:6213f644d804 4623 #define TSI_PEN_PEN6_SHIFT 6
bogdanm 87:6213f644d804 4624 #define TSI_PEN_PEN7_MASK 0x80u
bogdanm 87:6213f644d804 4625 #define TSI_PEN_PEN7_SHIFT 7
bogdanm 87:6213f644d804 4626 #define TSI_PEN_PEN8_MASK 0x100u
bogdanm 87:6213f644d804 4627 #define TSI_PEN_PEN8_SHIFT 8
bogdanm 87:6213f644d804 4628 #define TSI_PEN_PEN9_MASK 0x200u
bogdanm 87:6213f644d804 4629 #define TSI_PEN_PEN9_SHIFT 9
bogdanm 87:6213f644d804 4630 #define TSI_PEN_PEN10_MASK 0x400u
bogdanm 87:6213f644d804 4631 #define TSI_PEN_PEN10_SHIFT 10
bogdanm 87:6213f644d804 4632 #define TSI_PEN_PEN11_MASK 0x800u
bogdanm 87:6213f644d804 4633 #define TSI_PEN_PEN11_SHIFT 11
bogdanm 87:6213f644d804 4634 #define TSI_PEN_PEN12_MASK 0x1000u
bogdanm 87:6213f644d804 4635 #define TSI_PEN_PEN12_SHIFT 12
bogdanm 87:6213f644d804 4636 #define TSI_PEN_PEN13_MASK 0x2000u
bogdanm 87:6213f644d804 4637 #define TSI_PEN_PEN13_SHIFT 13
bogdanm 87:6213f644d804 4638 #define TSI_PEN_PEN14_MASK 0x4000u
bogdanm 87:6213f644d804 4639 #define TSI_PEN_PEN14_SHIFT 14
bogdanm 87:6213f644d804 4640 #define TSI_PEN_PEN15_MASK 0x8000u
bogdanm 87:6213f644d804 4641 #define TSI_PEN_PEN15_SHIFT 15
bogdanm 87:6213f644d804 4642 #define TSI_PEN_LPSP_MASK 0xF0000u
bogdanm 87:6213f644d804 4643 #define TSI_PEN_LPSP_SHIFT 16
bogdanm 87:6213f644d804 4644 #define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
bogdanm 87:6213f644d804 4645 /* WUCNTR Bit Fields */
bogdanm 87:6213f644d804 4646 #define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
bogdanm 87:6213f644d804 4647 #define TSI_WUCNTR_WUCNT_SHIFT 0
bogdanm 87:6213f644d804 4648 #define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
bogdanm 87:6213f644d804 4649 /* CNTR1 Bit Fields */
bogdanm 87:6213f644d804 4650 #define TSI_CNTR1_CTN1_MASK 0xFFFFu
bogdanm 87:6213f644d804 4651 #define TSI_CNTR1_CTN1_SHIFT 0
bogdanm 87:6213f644d804 4652 #define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
bogdanm 87:6213f644d804 4653 #define TSI_CNTR1_CTN_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4654 #define TSI_CNTR1_CTN_SHIFT 16
bogdanm 87:6213f644d804 4655 #define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
bogdanm 87:6213f644d804 4656 /* CNTR3 Bit Fields */
bogdanm 87:6213f644d804 4657 #define TSI_CNTR3_CTN1_MASK 0xFFFFu
bogdanm 87:6213f644d804 4658 #define TSI_CNTR3_CTN1_SHIFT 0
bogdanm 87:6213f644d804 4659 #define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
bogdanm 87:6213f644d804 4660 #define TSI_CNTR3_CTN_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4661 #define TSI_CNTR3_CTN_SHIFT 16
bogdanm 87:6213f644d804 4662 #define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
bogdanm 87:6213f644d804 4663 /* CNTR5 Bit Fields */
bogdanm 87:6213f644d804 4664 #define TSI_CNTR5_CTN1_MASK 0xFFFFu
bogdanm 87:6213f644d804 4665 #define TSI_CNTR5_CTN1_SHIFT 0
bogdanm 87:6213f644d804 4666 #define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
bogdanm 87:6213f644d804 4667 #define TSI_CNTR5_CTN_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4668 #define TSI_CNTR5_CTN_SHIFT 16
bogdanm 87:6213f644d804 4669 #define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
bogdanm 87:6213f644d804 4670 /* CNTR7 Bit Fields */
bogdanm 87:6213f644d804 4671 #define TSI_CNTR7_CTN1_MASK 0xFFFFu
bogdanm 87:6213f644d804 4672 #define TSI_CNTR7_CTN1_SHIFT 0
bogdanm 87:6213f644d804 4673 #define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
bogdanm 87:6213f644d804 4674 #define TSI_CNTR7_CTN_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4675 #define TSI_CNTR7_CTN_SHIFT 16
bogdanm 87:6213f644d804 4676 #define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
bogdanm 87:6213f644d804 4677 /* CNTR9 Bit Fields */
bogdanm 87:6213f644d804 4678 #define TSI_CNTR9_CTN1_MASK 0xFFFFu
bogdanm 87:6213f644d804 4679 #define TSI_CNTR9_CTN1_SHIFT 0
bogdanm 87:6213f644d804 4680 #define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
bogdanm 87:6213f644d804 4681 #define TSI_CNTR9_CTN_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4682 #define TSI_CNTR9_CTN_SHIFT 16
bogdanm 87:6213f644d804 4683 #define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
bogdanm 87:6213f644d804 4684 /* CNTR11 Bit Fields */
bogdanm 87:6213f644d804 4685 #define TSI_CNTR11_CTN1_MASK 0xFFFFu
bogdanm 87:6213f644d804 4686 #define TSI_CNTR11_CTN1_SHIFT 0
bogdanm 87:6213f644d804 4687 #define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
bogdanm 87:6213f644d804 4688 #define TSI_CNTR11_CTN_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4689 #define TSI_CNTR11_CTN_SHIFT 16
bogdanm 87:6213f644d804 4690 #define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
bogdanm 87:6213f644d804 4691 /* CNTR13 Bit Fields */
bogdanm 87:6213f644d804 4692 #define TSI_CNTR13_CTN1_MASK 0xFFFFu
bogdanm 87:6213f644d804 4693 #define TSI_CNTR13_CTN1_SHIFT 0
bogdanm 87:6213f644d804 4694 #define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
bogdanm 87:6213f644d804 4695 #define TSI_CNTR13_CTN_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4696 #define TSI_CNTR13_CTN_SHIFT 16
bogdanm 87:6213f644d804 4697 #define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
bogdanm 87:6213f644d804 4698 /* CNTR15 Bit Fields */
bogdanm 87:6213f644d804 4699 #define TSI_CNTR15_CTN1_MASK 0xFFFFu
bogdanm 87:6213f644d804 4700 #define TSI_CNTR15_CTN1_SHIFT 0
bogdanm 87:6213f644d804 4701 #define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
bogdanm 87:6213f644d804 4702 #define TSI_CNTR15_CTN_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4703 #define TSI_CNTR15_CTN_SHIFT 16
bogdanm 87:6213f644d804 4704 #define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
bogdanm 87:6213f644d804 4705 /* THRESHOLD Bit Fields */
bogdanm 87:6213f644d804 4706 #define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
bogdanm 87:6213f644d804 4707 #define TSI_THRESHOLD_HTHH_SHIFT 0
bogdanm 87:6213f644d804 4708 #define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
bogdanm 87:6213f644d804 4709 #define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
bogdanm 87:6213f644d804 4710 #define TSI_THRESHOLD_LTHH_SHIFT 16
bogdanm 87:6213f644d804 4711 #define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
bogdanm 87:6213f644d804 4712
bogdanm 87:6213f644d804 4713 /**
bogdanm 87:6213f644d804 4714 * @}
bogdanm 87:6213f644d804 4715 */ /* end of group TSI_Register_Masks */
bogdanm 87:6213f644d804 4716
bogdanm 87:6213f644d804 4717
bogdanm 87:6213f644d804 4718 /* TSI - Peripheral instance base addresses */
bogdanm 87:6213f644d804 4719 /** Peripheral TSI0 base address */
bogdanm 87:6213f644d804 4720 #define TSI0_BASE (0x40045000u)
bogdanm 87:6213f644d804 4721 /** Peripheral TSI0 base pointer */
bogdanm 87:6213f644d804 4722 #define TSI0 ((TSI_Type *)TSI0_BASE)
bogdanm 87:6213f644d804 4723
bogdanm 87:6213f644d804 4724 /**
bogdanm 87:6213f644d804 4725 * @}
bogdanm 87:6213f644d804 4726 */ /* end of group TSI_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 4727
bogdanm 87:6213f644d804 4728
bogdanm 87:6213f644d804 4729 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 4730 -- UART Peripheral Access Layer
bogdanm 87:6213f644d804 4731 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 4732
bogdanm 87:6213f644d804 4733 /**
bogdanm 87:6213f644d804 4734 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
bogdanm 87:6213f644d804 4735 * @{
bogdanm 87:6213f644d804 4736 */
bogdanm 87:6213f644d804 4737
bogdanm 87:6213f644d804 4738 /** UART - Register Layout Typedef */
bogdanm 87:6213f644d804 4739 typedef struct {
bogdanm 87:6213f644d804 4740 __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
bogdanm 87:6213f644d804 4741 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
bogdanm 87:6213f644d804 4742 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 87:6213f644d804 4743 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 87:6213f644d804 4744 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 87:6213f644d804 4745 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 87:6213f644d804 4746 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 87:6213f644d804 4747 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 87:6213f644d804 4748 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
bogdanm 87:6213f644d804 4749 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
bogdanm 87:6213f644d804 4750 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
bogdanm 87:6213f644d804 4751 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
bogdanm 87:6213f644d804 4752 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
bogdanm 87:6213f644d804 4753 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
bogdanm 87:6213f644d804 4754 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
bogdanm 87:6213f644d804 4755 uint8_t RESERVED_0[1];
bogdanm 87:6213f644d804 4756 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
bogdanm 87:6213f644d804 4757 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
bogdanm 87:6213f644d804 4758 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
bogdanm 87:6213f644d804 4759 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
bogdanm 87:6213f644d804 4760 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
bogdanm 87:6213f644d804 4761 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
bogdanm 87:6213f644d804 4762 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
bogdanm 87:6213f644d804 4763 uint8_t RESERVED_1[1];
bogdanm 87:6213f644d804 4764 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
bogdanm 87:6213f644d804 4765 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
bogdanm 87:6213f644d804 4766 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
bogdanm 87:6213f644d804 4767 union { /* offset: 0x1B */
bogdanm 87:6213f644d804 4768 __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
bogdanm 87:6213f644d804 4769 __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
bogdanm 87:6213f644d804 4770 };
bogdanm 87:6213f644d804 4771 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
bogdanm 87:6213f644d804 4772 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
bogdanm 87:6213f644d804 4773 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
bogdanm 87:6213f644d804 4774 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
bogdanm 87:6213f644d804 4775 uint8_t RESERVED_2[1];
bogdanm 87:6213f644d804 4776 __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
bogdanm 87:6213f644d804 4777 __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
bogdanm 87:6213f644d804 4778 __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
bogdanm 87:6213f644d804 4779 __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
bogdanm 87:6213f644d804 4780 __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
bogdanm 87:6213f644d804 4781 __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
bogdanm 87:6213f644d804 4782 __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
bogdanm 87:6213f644d804 4783 __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
bogdanm 87:6213f644d804 4784 __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
bogdanm 87:6213f644d804 4785 __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
bogdanm 87:6213f644d804 4786 __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
bogdanm 87:6213f644d804 4787 __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
bogdanm 87:6213f644d804 4788 __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
bogdanm 87:6213f644d804 4789 __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
bogdanm 87:6213f644d804 4790 __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
bogdanm 87:6213f644d804 4791 __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
bogdanm 87:6213f644d804 4792 __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
bogdanm 87:6213f644d804 4793 } UART_Type;
bogdanm 87:6213f644d804 4794
bogdanm 87:6213f644d804 4795 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 4796 -- UART Register Masks
bogdanm 87:6213f644d804 4797 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 4798
bogdanm 87:6213f644d804 4799 /**
bogdanm 87:6213f644d804 4800 * @addtogroup UART_Register_Masks UART Register Masks
bogdanm 87:6213f644d804 4801 * @{
bogdanm 87:6213f644d804 4802 */
bogdanm 87:6213f644d804 4803
bogdanm 87:6213f644d804 4804 /* BDH Bit Fields */
bogdanm 87:6213f644d804 4805 #define UART_BDH_SBR_MASK 0x1Fu
bogdanm 87:6213f644d804 4806 #define UART_BDH_SBR_SHIFT 0
bogdanm 87:6213f644d804 4807 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
bogdanm 87:6213f644d804 4808 #define UART_BDH_RXEDGIE_MASK 0x40u
bogdanm 87:6213f644d804 4809 #define UART_BDH_RXEDGIE_SHIFT 6
bogdanm 87:6213f644d804 4810 #define UART_BDH_LBKDIE_MASK 0x80u
bogdanm 87:6213f644d804 4811 #define UART_BDH_LBKDIE_SHIFT 7
bogdanm 87:6213f644d804 4812 /* BDL Bit Fields */
bogdanm 87:6213f644d804 4813 #define UART_BDL_SBR_MASK 0xFFu
bogdanm 87:6213f644d804 4814 #define UART_BDL_SBR_SHIFT 0
bogdanm 87:6213f644d804 4815 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
bogdanm 87:6213f644d804 4816 /* C1 Bit Fields */
bogdanm 87:6213f644d804 4817 #define UART_C1_PT_MASK 0x1u
bogdanm 87:6213f644d804 4818 #define UART_C1_PT_SHIFT 0
bogdanm 87:6213f644d804 4819 #define UART_C1_PE_MASK 0x2u
bogdanm 87:6213f644d804 4820 #define UART_C1_PE_SHIFT 1
bogdanm 87:6213f644d804 4821 #define UART_C1_ILT_MASK 0x4u
bogdanm 87:6213f644d804 4822 #define UART_C1_ILT_SHIFT 2
bogdanm 87:6213f644d804 4823 #define UART_C1_WAKE_MASK 0x8u
bogdanm 87:6213f644d804 4824 #define UART_C1_WAKE_SHIFT 3
bogdanm 87:6213f644d804 4825 #define UART_C1_M_MASK 0x10u
bogdanm 87:6213f644d804 4826 #define UART_C1_M_SHIFT 4
bogdanm 87:6213f644d804 4827 #define UART_C1_RSRC_MASK 0x20u
bogdanm 87:6213f644d804 4828 #define UART_C1_RSRC_SHIFT 5
bogdanm 87:6213f644d804 4829 #define UART_C1_UARTSWAI_MASK 0x40u
bogdanm 87:6213f644d804 4830 #define UART_C1_UARTSWAI_SHIFT 6
bogdanm 87:6213f644d804 4831 #define UART_C1_LOOPS_MASK 0x80u
bogdanm 87:6213f644d804 4832 #define UART_C1_LOOPS_SHIFT 7
bogdanm 87:6213f644d804 4833 /* C2 Bit Fields */
bogdanm 87:6213f644d804 4834 #define UART_C2_SBK_MASK 0x1u
bogdanm 87:6213f644d804 4835 #define UART_C2_SBK_SHIFT 0
bogdanm 87:6213f644d804 4836 #define UART_C2_RWU_MASK 0x2u
bogdanm 87:6213f644d804 4837 #define UART_C2_RWU_SHIFT 1
bogdanm 87:6213f644d804 4838 #define UART_C2_RE_MASK 0x4u
bogdanm 87:6213f644d804 4839 #define UART_C2_RE_SHIFT 2
bogdanm 87:6213f644d804 4840 #define UART_C2_TE_MASK 0x8u
bogdanm 87:6213f644d804 4841 #define UART_C2_TE_SHIFT 3
bogdanm 87:6213f644d804 4842 #define UART_C2_ILIE_MASK 0x10u
bogdanm 87:6213f644d804 4843 #define UART_C2_ILIE_SHIFT 4
bogdanm 87:6213f644d804 4844 #define UART_C2_RIE_MASK 0x20u
bogdanm 87:6213f644d804 4845 #define UART_C2_RIE_SHIFT 5
bogdanm 87:6213f644d804 4846 #define UART_C2_TCIE_MASK 0x40u
bogdanm 87:6213f644d804 4847 #define UART_C2_TCIE_SHIFT 6
bogdanm 87:6213f644d804 4848 #define UART_C2_TIE_MASK 0x80u
bogdanm 87:6213f644d804 4849 #define UART_C2_TIE_SHIFT 7
bogdanm 87:6213f644d804 4850 /* S1 Bit Fields */
bogdanm 87:6213f644d804 4851 #define UART_S1_PF_MASK 0x1u
bogdanm 87:6213f644d804 4852 #define UART_S1_PF_SHIFT 0
bogdanm 87:6213f644d804 4853 #define UART_S1_FE_MASK 0x2u
bogdanm 87:6213f644d804 4854 #define UART_S1_FE_SHIFT 1
bogdanm 87:6213f644d804 4855 #define UART_S1_NF_MASK 0x4u
bogdanm 87:6213f644d804 4856 #define UART_S1_NF_SHIFT 2
bogdanm 87:6213f644d804 4857 #define UART_S1_OR_MASK 0x8u
bogdanm 87:6213f644d804 4858 #define UART_S1_OR_SHIFT 3
bogdanm 87:6213f644d804 4859 #define UART_S1_IDLE_MASK 0x10u
bogdanm 87:6213f644d804 4860 #define UART_S1_IDLE_SHIFT 4
bogdanm 87:6213f644d804 4861 #define UART_S1_RDRF_MASK 0x20u
bogdanm 87:6213f644d804 4862 #define UART_S1_RDRF_SHIFT 5
bogdanm 87:6213f644d804 4863 #define UART_S1_TC_MASK 0x40u
bogdanm 87:6213f644d804 4864 #define UART_S1_TC_SHIFT 6
bogdanm 87:6213f644d804 4865 #define UART_S1_TDRE_MASK 0x80u
bogdanm 87:6213f644d804 4866 #define UART_S1_TDRE_SHIFT 7
bogdanm 87:6213f644d804 4867 /* S2 Bit Fields */
bogdanm 87:6213f644d804 4868 #define UART_S2_RAF_MASK 0x1u
bogdanm 87:6213f644d804 4869 #define UART_S2_RAF_SHIFT 0
bogdanm 87:6213f644d804 4870 #define UART_S2_LBKDE_MASK 0x2u
bogdanm 87:6213f644d804 4871 #define UART_S2_LBKDE_SHIFT 1
bogdanm 87:6213f644d804 4872 #define UART_S2_BRK13_MASK 0x4u
bogdanm 87:6213f644d804 4873 #define UART_S2_BRK13_SHIFT 2
bogdanm 87:6213f644d804 4874 #define UART_S2_RWUID_MASK 0x8u
bogdanm 87:6213f644d804 4875 #define UART_S2_RWUID_SHIFT 3
bogdanm 87:6213f644d804 4876 #define UART_S2_RXINV_MASK 0x10u
bogdanm 87:6213f644d804 4877 #define UART_S2_RXINV_SHIFT 4
bogdanm 87:6213f644d804 4878 #define UART_S2_MSBF_MASK 0x20u
bogdanm 87:6213f644d804 4879 #define UART_S2_MSBF_SHIFT 5
bogdanm 87:6213f644d804 4880 #define UART_S2_RXEDGIF_MASK 0x40u
bogdanm 87:6213f644d804 4881 #define UART_S2_RXEDGIF_SHIFT 6
bogdanm 87:6213f644d804 4882 #define UART_S2_LBKDIF_MASK 0x80u
bogdanm 87:6213f644d804 4883 #define UART_S2_LBKDIF_SHIFT 7
bogdanm 87:6213f644d804 4884 /* C3 Bit Fields */
bogdanm 87:6213f644d804 4885 #define UART_C3_PEIE_MASK 0x1u
bogdanm 87:6213f644d804 4886 #define UART_C3_PEIE_SHIFT 0
bogdanm 87:6213f644d804 4887 #define UART_C3_FEIE_MASK 0x2u
bogdanm 87:6213f644d804 4888 #define UART_C3_FEIE_SHIFT 1
bogdanm 87:6213f644d804 4889 #define UART_C3_NEIE_MASK 0x4u
bogdanm 87:6213f644d804 4890 #define UART_C3_NEIE_SHIFT 2
bogdanm 87:6213f644d804 4891 #define UART_C3_ORIE_MASK 0x8u
bogdanm 87:6213f644d804 4892 #define UART_C3_ORIE_SHIFT 3
bogdanm 87:6213f644d804 4893 #define UART_C3_TXINV_MASK 0x10u
bogdanm 87:6213f644d804 4894 #define UART_C3_TXINV_SHIFT 4
bogdanm 87:6213f644d804 4895 #define UART_C3_TXDIR_MASK 0x20u
bogdanm 87:6213f644d804 4896 #define UART_C3_TXDIR_SHIFT 5
bogdanm 87:6213f644d804 4897 #define UART_C3_T8_MASK 0x40u
bogdanm 87:6213f644d804 4898 #define UART_C3_T8_SHIFT 6
bogdanm 87:6213f644d804 4899 #define UART_C3_R8_MASK 0x80u
bogdanm 87:6213f644d804 4900 #define UART_C3_R8_SHIFT 7
bogdanm 87:6213f644d804 4901 /* D Bit Fields */
bogdanm 87:6213f644d804 4902 #define UART_D_RT_MASK 0xFFu
bogdanm 87:6213f644d804 4903 #define UART_D_RT_SHIFT 0
bogdanm 87:6213f644d804 4904 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
bogdanm 87:6213f644d804 4905 /* MA1 Bit Fields */
bogdanm 87:6213f644d804 4906 #define UART_MA1_MA_MASK 0xFFu
bogdanm 87:6213f644d804 4907 #define UART_MA1_MA_SHIFT 0
bogdanm 87:6213f644d804 4908 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
bogdanm 87:6213f644d804 4909 /* MA2 Bit Fields */
bogdanm 87:6213f644d804 4910 #define UART_MA2_MA_MASK 0xFFu
bogdanm 87:6213f644d804 4911 #define UART_MA2_MA_SHIFT 0
bogdanm 87:6213f644d804 4912 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
bogdanm 87:6213f644d804 4913 /* C4 Bit Fields */
bogdanm 87:6213f644d804 4914 #define UART_C4_BRFA_MASK 0x1Fu
bogdanm 87:6213f644d804 4915 #define UART_C4_BRFA_SHIFT 0
bogdanm 87:6213f644d804 4916 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
bogdanm 87:6213f644d804 4917 #define UART_C4_M10_MASK 0x20u
bogdanm 87:6213f644d804 4918 #define UART_C4_M10_SHIFT 5
bogdanm 87:6213f644d804 4919 #define UART_C4_MAEN2_MASK 0x40u
bogdanm 87:6213f644d804 4920 #define UART_C4_MAEN2_SHIFT 6
bogdanm 87:6213f644d804 4921 #define UART_C4_MAEN1_MASK 0x80u
bogdanm 87:6213f644d804 4922 #define UART_C4_MAEN1_SHIFT 7
bogdanm 87:6213f644d804 4923 /* C5 Bit Fields */
bogdanm 87:6213f644d804 4924 #define UART_C5_RDMAS_MASK 0x20u
bogdanm 87:6213f644d804 4925 #define UART_C5_RDMAS_SHIFT 5
bogdanm 87:6213f644d804 4926 #define UART_C5_TDMAS_MASK 0x80u
bogdanm 87:6213f644d804 4927 #define UART_C5_TDMAS_SHIFT 7
bogdanm 87:6213f644d804 4928 /* ED Bit Fields */
bogdanm 87:6213f644d804 4929 #define UART_ED_PARITYE_MASK 0x40u
bogdanm 87:6213f644d804 4930 #define UART_ED_PARITYE_SHIFT 6
bogdanm 87:6213f644d804 4931 #define UART_ED_NOISY_MASK 0x80u
bogdanm 87:6213f644d804 4932 #define UART_ED_NOISY_SHIFT 7
bogdanm 87:6213f644d804 4933 /* MODEM Bit Fields */
bogdanm 87:6213f644d804 4934 #define UART_MODEM_TXCTSE_MASK 0x1u
bogdanm 87:6213f644d804 4935 #define UART_MODEM_TXCTSE_SHIFT 0
bogdanm 87:6213f644d804 4936 #define UART_MODEM_TXRTSE_MASK 0x2u
bogdanm 87:6213f644d804 4937 #define UART_MODEM_TXRTSE_SHIFT 1
bogdanm 87:6213f644d804 4938 #define UART_MODEM_TXRTSPOL_MASK 0x4u
bogdanm 87:6213f644d804 4939 #define UART_MODEM_TXRTSPOL_SHIFT 2
bogdanm 87:6213f644d804 4940 #define UART_MODEM_RXRTSE_MASK 0x8u
bogdanm 87:6213f644d804 4941 #define UART_MODEM_RXRTSE_SHIFT 3
bogdanm 87:6213f644d804 4942 /* IR Bit Fields */
bogdanm 87:6213f644d804 4943 #define UART_IR_TNP_MASK 0x3u
bogdanm 87:6213f644d804 4944 #define UART_IR_TNP_SHIFT 0
bogdanm 87:6213f644d804 4945 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
bogdanm 87:6213f644d804 4946 #define UART_IR_IREN_MASK 0x4u
bogdanm 87:6213f644d804 4947 #define UART_IR_IREN_SHIFT 2
bogdanm 87:6213f644d804 4948 /* PFIFO Bit Fields */
bogdanm 87:6213f644d804 4949 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
bogdanm 87:6213f644d804 4950 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
bogdanm 87:6213f644d804 4951 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
bogdanm 87:6213f644d804 4952 #define UART_PFIFO_RXFE_MASK 0x8u
bogdanm 87:6213f644d804 4953 #define UART_PFIFO_RXFE_SHIFT 3
bogdanm 87:6213f644d804 4954 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
bogdanm 87:6213f644d804 4955 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
bogdanm 87:6213f644d804 4956 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
bogdanm 87:6213f644d804 4957 #define UART_PFIFO_TXFE_MASK 0x80u
bogdanm 87:6213f644d804 4958 #define UART_PFIFO_TXFE_SHIFT 7
bogdanm 87:6213f644d804 4959 /* CFIFO Bit Fields */
bogdanm 87:6213f644d804 4960 #define UART_CFIFO_RXUFE_MASK 0x1u
bogdanm 87:6213f644d804 4961 #define UART_CFIFO_RXUFE_SHIFT 0
bogdanm 87:6213f644d804 4962 #define UART_CFIFO_TXOFE_MASK 0x2u
bogdanm 87:6213f644d804 4963 #define UART_CFIFO_TXOFE_SHIFT 1
bogdanm 87:6213f644d804 4964 #define UART_CFIFO_RXFLUSH_MASK 0x40u
bogdanm 87:6213f644d804 4965 #define UART_CFIFO_RXFLUSH_SHIFT 6
bogdanm 87:6213f644d804 4966 #define UART_CFIFO_TXFLUSH_MASK 0x80u
bogdanm 87:6213f644d804 4967 #define UART_CFIFO_TXFLUSH_SHIFT 7
bogdanm 87:6213f644d804 4968 /* SFIFO Bit Fields */
bogdanm 87:6213f644d804 4969 #define UART_SFIFO_RXUF_MASK 0x1u
bogdanm 87:6213f644d804 4970 #define UART_SFIFO_RXUF_SHIFT 0
bogdanm 87:6213f644d804 4971 #define UART_SFIFO_TXOF_MASK 0x2u
bogdanm 87:6213f644d804 4972 #define UART_SFIFO_TXOF_SHIFT 1
bogdanm 87:6213f644d804 4973 #define UART_SFIFO_RXEMPT_MASK 0x40u
bogdanm 87:6213f644d804 4974 #define UART_SFIFO_RXEMPT_SHIFT 6
bogdanm 87:6213f644d804 4975 #define UART_SFIFO_TXEMPT_MASK 0x80u
bogdanm 87:6213f644d804 4976 #define UART_SFIFO_TXEMPT_SHIFT 7
bogdanm 87:6213f644d804 4977 /* TWFIFO Bit Fields */
bogdanm 87:6213f644d804 4978 #define UART_TWFIFO_TXWATER_MASK 0xFFu
bogdanm 87:6213f644d804 4979 #define UART_TWFIFO_TXWATER_SHIFT 0
bogdanm 87:6213f644d804 4980 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
bogdanm 87:6213f644d804 4981 /* TCFIFO Bit Fields */
bogdanm 87:6213f644d804 4982 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
bogdanm 87:6213f644d804 4983 #define UART_TCFIFO_TXCOUNT_SHIFT 0
bogdanm 87:6213f644d804 4984 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
bogdanm 87:6213f644d804 4985 /* RWFIFO Bit Fields */
bogdanm 87:6213f644d804 4986 #define UART_RWFIFO_RXWATER_MASK 0xFFu
bogdanm 87:6213f644d804 4987 #define UART_RWFIFO_RXWATER_SHIFT 0
bogdanm 87:6213f644d804 4988 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
bogdanm 87:6213f644d804 4989 /* RCFIFO Bit Fields */
bogdanm 87:6213f644d804 4990 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
bogdanm 87:6213f644d804 4991 #define UART_RCFIFO_RXCOUNT_SHIFT 0
bogdanm 87:6213f644d804 4992 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
bogdanm 87:6213f644d804 4993 /* C7816 Bit Fields */
bogdanm 87:6213f644d804 4994 #define UART_C7816_ISO_7816E_MASK 0x1u
bogdanm 87:6213f644d804 4995 #define UART_C7816_ISO_7816E_SHIFT 0
bogdanm 87:6213f644d804 4996 #define UART_C7816_TTYPE_MASK 0x2u
bogdanm 87:6213f644d804 4997 #define UART_C7816_TTYPE_SHIFT 1
bogdanm 87:6213f644d804 4998 #define UART_C7816_INIT_MASK 0x4u
bogdanm 87:6213f644d804 4999 #define UART_C7816_INIT_SHIFT 2
bogdanm 87:6213f644d804 5000 #define UART_C7816_ANACK_MASK 0x8u
bogdanm 87:6213f644d804 5001 #define UART_C7816_ANACK_SHIFT 3
bogdanm 87:6213f644d804 5002 #define UART_C7816_ONACK_MASK 0x10u
bogdanm 87:6213f644d804 5003 #define UART_C7816_ONACK_SHIFT 4
bogdanm 87:6213f644d804 5004 /* IE7816 Bit Fields */
bogdanm 87:6213f644d804 5005 #define UART_IE7816_RXTE_MASK 0x1u
bogdanm 87:6213f644d804 5006 #define UART_IE7816_RXTE_SHIFT 0
bogdanm 87:6213f644d804 5007 #define UART_IE7816_TXTE_MASK 0x2u
bogdanm 87:6213f644d804 5008 #define UART_IE7816_TXTE_SHIFT 1
bogdanm 87:6213f644d804 5009 #define UART_IE7816_GTVE_MASK 0x4u
bogdanm 87:6213f644d804 5010 #define UART_IE7816_GTVE_SHIFT 2
bogdanm 87:6213f644d804 5011 #define UART_IE7816_INITDE_MASK 0x10u
bogdanm 87:6213f644d804 5012 #define UART_IE7816_INITDE_SHIFT 4
bogdanm 87:6213f644d804 5013 #define UART_IE7816_BWTE_MASK 0x20u
bogdanm 87:6213f644d804 5014 #define UART_IE7816_BWTE_SHIFT 5
bogdanm 87:6213f644d804 5015 #define UART_IE7816_CWTE_MASK 0x40u
bogdanm 87:6213f644d804 5016 #define UART_IE7816_CWTE_SHIFT 6
bogdanm 87:6213f644d804 5017 #define UART_IE7816_WTE_MASK 0x80u
bogdanm 87:6213f644d804 5018 #define UART_IE7816_WTE_SHIFT 7
bogdanm 87:6213f644d804 5019 /* IS7816 Bit Fields */
bogdanm 87:6213f644d804 5020 #define UART_IS7816_RXT_MASK 0x1u
bogdanm 87:6213f644d804 5021 #define UART_IS7816_RXT_SHIFT 0
bogdanm 87:6213f644d804 5022 #define UART_IS7816_TXT_MASK 0x2u
bogdanm 87:6213f644d804 5023 #define UART_IS7816_TXT_SHIFT 1
bogdanm 87:6213f644d804 5024 #define UART_IS7816_GTV_MASK 0x4u
bogdanm 87:6213f644d804 5025 #define UART_IS7816_GTV_SHIFT 2
bogdanm 87:6213f644d804 5026 #define UART_IS7816_INITD_MASK 0x10u
bogdanm 87:6213f644d804 5027 #define UART_IS7816_INITD_SHIFT 4
bogdanm 87:6213f644d804 5028 #define UART_IS7816_BWT_MASK 0x20u
bogdanm 87:6213f644d804 5029 #define UART_IS7816_BWT_SHIFT 5
bogdanm 87:6213f644d804 5030 #define UART_IS7816_CWT_MASK 0x40u
bogdanm 87:6213f644d804 5031 #define UART_IS7816_CWT_SHIFT 6
bogdanm 87:6213f644d804 5032 #define UART_IS7816_WT_MASK 0x80u
bogdanm 87:6213f644d804 5033 #define UART_IS7816_WT_SHIFT 7
bogdanm 87:6213f644d804 5034 /* WP7816_T_TYPE0 Bit Fields */
bogdanm 87:6213f644d804 5035 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
bogdanm 87:6213f644d804 5036 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
bogdanm 87:6213f644d804 5037 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
bogdanm 87:6213f644d804 5038 /* WP7816_T_TYPE1 Bit Fields */
bogdanm 87:6213f644d804 5039 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
bogdanm 87:6213f644d804 5040 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
bogdanm 87:6213f644d804 5041 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
bogdanm 87:6213f644d804 5042 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
bogdanm 87:6213f644d804 5043 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
bogdanm 87:6213f644d804 5044 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
bogdanm 87:6213f644d804 5045 /* WN7816 Bit Fields */
bogdanm 87:6213f644d804 5046 #define UART_WN7816_GTN_MASK 0xFFu
bogdanm 87:6213f644d804 5047 #define UART_WN7816_GTN_SHIFT 0
bogdanm 87:6213f644d804 5048 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
bogdanm 87:6213f644d804 5049 /* WF7816 Bit Fields */
bogdanm 87:6213f644d804 5050 #define UART_WF7816_GTFD_MASK 0xFFu
bogdanm 87:6213f644d804 5051 #define UART_WF7816_GTFD_SHIFT 0
bogdanm 87:6213f644d804 5052 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
bogdanm 87:6213f644d804 5053 /* ET7816 Bit Fields */
bogdanm 87:6213f644d804 5054 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
bogdanm 87:6213f644d804 5055 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
bogdanm 87:6213f644d804 5056 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
bogdanm 87:6213f644d804 5057 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
bogdanm 87:6213f644d804 5058 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
bogdanm 87:6213f644d804 5059 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
bogdanm 87:6213f644d804 5060 /* TL7816 Bit Fields */
bogdanm 87:6213f644d804 5061 #define UART_TL7816_TLEN_MASK 0xFFu
bogdanm 87:6213f644d804 5062 #define UART_TL7816_TLEN_SHIFT 0
bogdanm 87:6213f644d804 5063 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
bogdanm 87:6213f644d804 5064 /* C6 Bit Fields */
bogdanm 87:6213f644d804 5065 #define UART_C6_CP_MASK 0x10u
bogdanm 87:6213f644d804 5066 #define UART_C6_CP_SHIFT 4
bogdanm 87:6213f644d804 5067 #define UART_C6_CE_MASK 0x20u
bogdanm 87:6213f644d804 5068 #define UART_C6_CE_SHIFT 5
bogdanm 87:6213f644d804 5069 #define UART_C6_TX709_MASK 0x40u
bogdanm 87:6213f644d804 5070 #define UART_C6_TX709_SHIFT 6
bogdanm 87:6213f644d804 5071 #define UART_C6_EN709_MASK 0x80u
bogdanm 87:6213f644d804 5072 #define UART_C6_EN709_SHIFT 7
bogdanm 87:6213f644d804 5073 /* PCTH Bit Fields */
bogdanm 87:6213f644d804 5074 #define UART_PCTH_PCTH_MASK 0xFFu
bogdanm 87:6213f644d804 5075 #define UART_PCTH_PCTH_SHIFT 0
bogdanm 87:6213f644d804 5076 #define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
bogdanm 87:6213f644d804 5077 /* PCTL Bit Fields */
bogdanm 87:6213f644d804 5078 #define UART_PCTL_PCTL_MASK 0xFFu
bogdanm 87:6213f644d804 5079 #define UART_PCTL_PCTL_SHIFT 0
bogdanm 87:6213f644d804 5080 #define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
bogdanm 87:6213f644d804 5081 /* B1T Bit Fields */
bogdanm 87:6213f644d804 5082 #define UART_B1T_B1T_MASK 0xFFu
bogdanm 87:6213f644d804 5083 #define UART_B1T_B1T_SHIFT 0
bogdanm 87:6213f644d804 5084 #define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
bogdanm 87:6213f644d804 5085 /* SDTH Bit Fields */
bogdanm 87:6213f644d804 5086 #define UART_SDTH_SDTH_MASK 0xFFu
bogdanm 87:6213f644d804 5087 #define UART_SDTH_SDTH_SHIFT 0
bogdanm 87:6213f644d804 5088 #define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
bogdanm 87:6213f644d804 5089 /* SDTL Bit Fields */
bogdanm 87:6213f644d804 5090 #define UART_SDTL_SDTL_MASK 0xFFu
bogdanm 87:6213f644d804 5091 #define UART_SDTL_SDTL_SHIFT 0
bogdanm 87:6213f644d804 5092 #define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
bogdanm 87:6213f644d804 5093 /* PRE Bit Fields */
bogdanm 87:6213f644d804 5094 #define UART_PRE_PREAMBLE_MASK 0xFFu
bogdanm 87:6213f644d804 5095 #define UART_PRE_PREAMBLE_SHIFT 0
bogdanm 87:6213f644d804 5096 #define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
bogdanm 87:6213f644d804 5097 /* TPL Bit Fields */
bogdanm 87:6213f644d804 5098 #define UART_TPL_TPL_MASK 0xFFu
bogdanm 87:6213f644d804 5099 #define UART_TPL_TPL_SHIFT 0
bogdanm 87:6213f644d804 5100 #define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
bogdanm 87:6213f644d804 5101 /* IE Bit Fields */
bogdanm 87:6213f644d804 5102 #define UART_IE_TXFIE_MASK 0x1u
bogdanm 87:6213f644d804 5103 #define UART_IE_TXFIE_SHIFT 0
bogdanm 87:6213f644d804 5104 #define UART_IE_PSIE_MASK 0x2u
bogdanm 87:6213f644d804 5105 #define UART_IE_PSIE_SHIFT 1
bogdanm 87:6213f644d804 5106 #define UART_IE_PCTEIE_MASK 0x4u
bogdanm 87:6213f644d804 5107 #define UART_IE_PCTEIE_SHIFT 2
bogdanm 87:6213f644d804 5108 #define UART_IE_PTXIE_MASK 0x8u
bogdanm 87:6213f644d804 5109 #define UART_IE_PTXIE_SHIFT 3
bogdanm 87:6213f644d804 5110 #define UART_IE_PRXIE_MASK 0x10u
bogdanm 87:6213f644d804 5111 #define UART_IE_PRXIE_SHIFT 4
bogdanm 87:6213f644d804 5112 #define UART_IE_ISDIE_MASK 0x20u
bogdanm 87:6213f644d804 5113 #define UART_IE_ISDIE_SHIFT 5
bogdanm 87:6213f644d804 5114 #define UART_IE_WBEIE_MASK 0x40u
bogdanm 87:6213f644d804 5115 #define UART_IE_WBEIE_SHIFT 6
bogdanm 87:6213f644d804 5116 /* WB Bit Fields */
bogdanm 87:6213f644d804 5117 #define UART_WB_WBASE_MASK 0xFFu
bogdanm 87:6213f644d804 5118 #define UART_WB_WBASE_SHIFT 0
bogdanm 87:6213f644d804 5119 #define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
bogdanm 87:6213f644d804 5120 /* S3 Bit Fields */
bogdanm 87:6213f644d804 5121 #define UART_S3_TXFF_MASK 0x1u
bogdanm 87:6213f644d804 5122 #define UART_S3_TXFF_SHIFT 0
bogdanm 87:6213f644d804 5123 #define UART_S3_PSF_MASK 0x2u
bogdanm 87:6213f644d804 5124 #define UART_S3_PSF_SHIFT 1
bogdanm 87:6213f644d804 5125 #define UART_S3_PCTEF_MASK 0x4u
bogdanm 87:6213f644d804 5126 #define UART_S3_PCTEF_SHIFT 2
bogdanm 87:6213f644d804 5127 #define UART_S3_PTXF_MASK 0x8u
bogdanm 87:6213f644d804 5128 #define UART_S3_PTXF_SHIFT 3
bogdanm 87:6213f644d804 5129 #define UART_S3_PRXF_MASK 0x10u
bogdanm 87:6213f644d804 5130 #define UART_S3_PRXF_SHIFT 4
bogdanm 87:6213f644d804 5131 #define UART_S3_ISD_MASK 0x20u
bogdanm 87:6213f644d804 5132 #define UART_S3_ISD_SHIFT 5
bogdanm 87:6213f644d804 5133 #define UART_S3_WBEF_MASK 0x40u
bogdanm 87:6213f644d804 5134 #define UART_S3_WBEF_SHIFT 6
bogdanm 87:6213f644d804 5135 #define UART_S3_PEF_MASK 0x80u
bogdanm 87:6213f644d804 5136 #define UART_S3_PEF_SHIFT 7
bogdanm 87:6213f644d804 5137 /* S4 Bit Fields */
bogdanm 87:6213f644d804 5138 #define UART_S4_FE_MASK 0x1u
bogdanm 87:6213f644d804 5139 #define UART_S4_FE_SHIFT 0
bogdanm 87:6213f644d804 5140 #define UART_S4_ILCV_MASK 0x2u
bogdanm 87:6213f644d804 5141 #define UART_S4_ILCV_SHIFT 1
bogdanm 87:6213f644d804 5142 #define UART_S4_CDET_MASK 0xCu
bogdanm 87:6213f644d804 5143 #define UART_S4_CDET_SHIFT 2
bogdanm 87:6213f644d804 5144 #define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
bogdanm 87:6213f644d804 5145 #define UART_S4_INITF_MASK 0x10u
bogdanm 87:6213f644d804 5146 #define UART_S4_INITF_SHIFT 4
bogdanm 87:6213f644d804 5147 /* RPL Bit Fields */
bogdanm 87:6213f644d804 5148 #define UART_RPL_RPL_MASK 0xFFu
bogdanm 87:6213f644d804 5149 #define UART_RPL_RPL_SHIFT 0
bogdanm 87:6213f644d804 5150 #define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
bogdanm 87:6213f644d804 5151 /* RPREL Bit Fields */
bogdanm 87:6213f644d804 5152 #define UART_RPREL_RPREL_MASK 0xFFu
bogdanm 87:6213f644d804 5153 #define UART_RPREL_RPREL_SHIFT 0
bogdanm 87:6213f644d804 5154 #define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
bogdanm 87:6213f644d804 5155 /* CPW Bit Fields */
bogdanm 87:6213f644d804 5156 #define UART_CPW_CPW_MASK 0xFFu
bogdanm 87:6213f644d804 5157 #define UART_CPW_CPW_SHIFT 0
bogdanm 87:6213f644d804 5158 #define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
bogdanm 87:6213f644d804 5159 /* RIDT Bit Fields */
bogdanm 87:6213f644d804 5160 #define UART_RIDT_RIDT_MASK 0xFFu
bogdanm 87:6213f644d804 5161 #define UART_RIDT_RIDT_SHIFT 0
bogdanm 87:6213f644d804 5162 #define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
bogdanm 87:6213f644d804 5163 /* TIDT Bit Fields */
bogdanm 87:6213f644d804 5164 #define UART_TIDT_TIDT_MASK 0xFFu
bogdanm 87:6213f644d804 5165 #define UART_TIDT_TIDT_SHIFT 0
bogdanm 87:6213f644d804 5166 #define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
bogdanm 87:6213f644d804 5167
bogdanm 87:6213f644d804 5168 /**
bogdanm 87:6213f644d804 5169 * @}
bogdanm 87:6213f644d804 5170 */ /* end of group UART_Register_Masks */
bogdanm 87:6213f644d804 5171
bogdanm 87:6213f644d804 5172
bogdanm 87:6213f644d804 5173 /* UART - Peripheral instance base addresses */
bogdanm 87:6213f644d804 5174 /** Peripheral UART0 base address */
bogdanm 87:6213f644d804 5175 #define UART0_BASE (0x4006A000u)
bogdanm 87:6213f644d804 5176 /** Peripheral UART0 base pointer */
bogdanm 87:6213f644d804 5177 #define UART0 ((UART_Type *)UART0_BASE)
bogdanm 87:6213f644d804 5178 /** Peripheral UART1 base address */
bogdanm 87:6213f644d804 5179 #define UART1_BASE (0x4006B000u)
bogdanm 87:6213f644d804 5180 /** Peripheral UART1 base pointer */
bogdanm 87:6213f644d804 5181 #define UART1 ((UART_Type *)UART1_BASE)
bogdanm 87:6213f644d804 5182 /** Peripheral UART2 base address */
bogdanm 87:6213f644d804 5183 #define UART2_BASE (0x4006C000u)
bogdanm 87:6213f644d804 5184 /** Peripheral UART2 base pointer */
bogdanm 87:6213f644d804 5185 #define UART2 ((UART_Type *)UART2_BASE)
bogdanm 87:6213f644d804 5186
bogdanm 87:6213f644d804 5187 /**
bogdanm 87:6213f644d804 5188 * @}
bogdanm 87:6213f644d804 5189 */ /* end of group UART_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 5190
bogdanm 87:6213f644d804 5191
bogdanm 87:6213f644d804 5192 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5193 -- USB Peripheral Access Layer
bogdanm 87:6213f644d804 5194 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5195
bogdanm 87:6213f644d804 5196 /**
bogdanm 87:6213f644d804 5197 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
bogdanm 87:6213f644d804 5198 * @{
bogdanm 87:6213f644d804 5199 */
bogdanm 87:6213f644d804 5200
bogdanm 87:6213f644d804 5201 /** USB - Register Layout Typedef */
bogdanm 87:6213f644d804 5202 typedef struct {
bogdanm 87:6213f644d804 5203 __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
bogdanm 87:6213f644d804 5204 uint8_t RESERVED_0[3];
bogdanm 87:6213f644d804 5205 __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
bogdanm 87:6213f644d804 5206 uint8_t RESERVED_1[3];
bogdanm 87:6213f644d804 5207 __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
bogdanm 87:6213f644d804 5208 uint8_t RESERVED_2[3];
bogdanm 87:6213f644d804 5209 __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
bogdanm 87:6213f644d804 5210 uint8_t RESERVED_3[3];
bogdanm 87:6213f644d804 5211 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
bogdanm 87:6213f644d804 5212 uint8_t RESERVED_4[3];
bogdanm 87:6213f644d804 5213 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
bogdanm 87:6213f644d804 5214 uint8_t RESERVED_5[3];
bogdanm 87:6213f644d804 5215 __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
bogdanm 87:6213f644d804 5216 uint8_t RESERVED_6[3];
bogdanm 87:6213f644d804 5217 __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
bogdanm 87:6213f644d804 5218 uint8_t RESERVED_7[99];
bogdanm 87:6213f644d804 5219 __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
bogdanm 87:6213f644d804 5220 uint8_t RESERVED_8[3];
bogdanm 87:6213f644d804 5221 __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
bogdanm 87:6213f644d804 5222 uint8_t RESERVED_9[3];
bogdanm 87:6213f644d804 5223 __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
bogdanm 87:6213f644d804 5224 uint8_t RESERVED_10[3];
bogdanm 87:6213f644d804 5225 __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
bogdanm 87:6213f644d804 5226 uint8_t RESERVED_11[3];
bogdanm 87:6213f644d804 5227 __I uint8_t STAT; /**< Status Register, offset: 0x90 */
bogdanm 87:6213f644d804 5228 uint8_t RESERVED_12[3];
bogdanm 87:6213f644d804 5229 __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
bogdanm 87:6213f644d804 5230 uint8_t RESERVED_13[3];
bogdanm 87:6213f644d804 5231 __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
bogdanm 87:6213f644d804 5232 uint8_t RESERVED_14[3];
bogdanm 87:6213f644d804 5233 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
bogdanm 87:6213f644d804 5234 uint8_t RESERVED_15[3];
bogdanm 87:6213f644d804 5235 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
bogdanm 87:6213f644d804 5236 uint8_t RESERVED_16[3];
bogdanm 87:6213f644d804 5237 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
bogdanm 87:6213f644d804 5238 uint8_t RESERVED_17[3];
bogdanm 87:6213f644d804 5239 __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
bogdanm 87:6213f644d804 5240 uint8_t RESERVED_18[3];
bogdanm 87:6213f644d804 5241 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
bogdanm 87:6213f644d804 5242 uint8_t RESERVED_19[3];
bogdanm 87:6213f644d804 5243 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
bogdanm 87:6213f644d804 5244 uint8_t RESERVED_20[3];
bogdanm 87:6213f644d804 5245 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
bogdanm 87:6213f644d804 5246 uint8_t RESERVED_21[11];
bogdanm 87:6213f644d804 5247 struct { /* offset: 0xC0, array step: 0x4 */
bogdanm 87:6213f644d804 5248 __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
bogdanm 87:6213f644d804 5249 uint8_t RESERVED_0[3];
bogdanm 87:6213f644d804 5250 } ENDPOINT[16];
bogdanm 87:6213f644d804 5251 __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
bogdanm 87:6213f644d804 5252 uint8_t RESERVED_22[3];
bogdanm 87:6213f644d804 5253 __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
bogdanm 87:6213f644d804 5254 uint8_t RESERVED_23[3];
bogdanm 87:6213f644d804 5255 __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
bogdanm 87:6213f644d804 5256 uint8_t RESERVED_24[3];
bogdanm 87:6213f644d804 5257 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
bogdanm 87:6213f644d804 5258 uint8_t RESERVED_25[7];
bogdanm 87:6213f644d804 5259 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
bogdanm 87:6213f644d804 5260 } USB_Type;
bogdanm 87:6213f644d804 5261
bogdanm 87:6213f644d804 5262 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5263 -- USB Register Masks
bogdanm 87:6213f644d804 5264 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5265
bogdanm 87:6213f644d804 5266 /**
bogdanm 87:6213f644d804 5267 * @addtogroup USB_Register_Masks USB Register Masks
bogdanm 87:6213f644d804 5268 * @{
bogdanm 87:6213f644d804 5269 */
bogdanm 87:6213f644d804 5270
bogdanm 87:6213f644d804 5271 /* PERID Bit Fields */
bogdanm 87:6213f644d804 5272 #define USB_PERID_ID_MASK 0x3Fu
bogdanm 87:6213f644d804 5273 #define USB_PERID_ID_SHIFT 0
bogdanm 87:6213f644d804 5274 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
bogdanm 87:6213f644d804 5275 /* IDCOMP Bit Fields */
bogdanm 87:6213f644d804 5276 #define USB_IDCOMP_NID_MASK 0x3Fu
bogdanm 87:6213f644d804 5277 #define USB_IDCOMP_NID_SHIFT 0
bogdanm 87:6213f644d804 5278 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
bogdanm 87:6213f644d804 5279 /* REV Bit Fields */
bogdanm 87:6213f644d804 5280 #define USB_REV_REV_MASK 0xFFu
bogdanm 87:6213f644d804 5281 #define USB_REV_REV_SHIFT 0
bogdanm 87:6213f644d804 5282 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
bogdanm 87:6213f644d804 5283 /* ADDINFO Bit Fields */
bogdanm 87:6213f644d804 5284 #define USB_ADDINFO_IEHOST_MASK 0x1u
bogdanm 87:6213f644d804 5285 #define USB_ADDINFO_IEHOST_SHIFT 0
bogdanm 87:6213f644d804 5286 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
bogdanm 87:6213f644d804 5287 #define USB_ADDINFO_IRQNUM_SHIFT 3
bogdanm 87:6213f644d804 5288 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
bogdanm 87:6213f644d804 5289 /* OTGISTAT Bit Fields */
bogdanm 87:6213f644d804 5290 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
bogdanm 87:6213f644d804 5291 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
bogdanm 87:6213f644d804 5292 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
bogdanm 87:6213f644d804 5293 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
bogdanm 87:6213f644d804 5294 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
bogdanm 87:6213f644d804 5295 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
bogdanm 87:6213f644d804 5296 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
bogdanm 87:6213f644d804 5297 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
bogdanm 87:6213f644d804 5298 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
bogdanm 87:6213f644d804 5299 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
bogdanm 87:6213f644d804 5300 #define USB_OTGISTAT_IDCHG_MASK 0x80u
bogdanm 87:6213f644d804 5301 #define USB_OTGISTAT_IDCHG_SHIFT 7
bogdanm 87:6213f644d804 5302 /* OTGICR Bit Fields */
bogdanm 87:6213f644d804 5303 #define USB_OTGICR_AVBUSEN_MASK 0x1u
bogdanm 87:6213f644d804 5304 #define USB_OTGICR_AVBUSEN_SHIFT 0
bogdanm 87:6213f644d804 5305 #define USB_OTGICR_BSESSEN_MASK 0x4u
bogdanm 87:6213f644d804 5306 #define USB_OTGICR_BSESSEN_SHIFT 2
bogdanm 87:6213f644d804 5307 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
bogdanm 87:6213f644d804 5308 #define USB_OTGICR_SESSVLDEN_SHIFT 3
bogdanm 87:6213f644d804 5309 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
bogdanm 87:6213f644d804 5310 #define USB_OTGICR_LINESTATEEN_SHIFT 5
bogdanm 87:6213f644d804 5311 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
bogdanm 87:6213f644d804 5312 #define USB_OTGICR_ONEMSECEN_SHIFT 6
bogdanm 87:6213f644d804 5313 #define USB_OTGICR_IDEN_MASK 0x80u
bogdanm 87:6213f644d804 5314 #define USB_OTGICR_IDEN_SHIFT 7
bogdanm 87:6213f644d804 5315 /* OTGSTAT Bit Fields */
bogdanm 87:6213f644d804 5316 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
bogdanm 87:6213f644d804 5317 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
bogdanm 87:6213f644d804 5318 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
bogdanm 87:6213f644d804 5319 #define USB_OTGSTAT_BSESSEND_SHIFT 2
bogdanm 87:6213f644d804 5320 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
bogdanm 87:6213f644d804 5321 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
bogdanm 87:6213f644d804 5322 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
bogdanm 87:6213f644d804 5323 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
bogdanm 87:6213f644d804 5324 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
bogdanm 87:6213f644d804 5325 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
bogdanm 87:6213f644d804 5326 #define USB_OTGSTAT_ID_MASK 0x80u
bogdanm 87:6213f644d804 5327 #define USB_OTGSTAT_ID_SHIFT 7
bogdanm 87:6213f644d804 5328 /* OTGCTL Bit Fields */
bogdanm 87:6213f644d804 5329 #define USB_OTGCTL_OTGEN_MASK 0x4u
bogdanm 87:6213f644d804 5330 #define USB_OTGCTL_OTGEN_SHIFT 2
bogdanm 87:6213f644d804 5331 #define USB_OTGCTL_DMLOW_MASK 0x10u
bogdanm 87:6213f644d804 5332 #define USB_OTGCTL_DMLOW_SHIFT 4
bogdanm 87:6213f644d804 5333 #define USB_OTGCTL_DPLOW_MASK 0x20u
bogdanm 87:6213f644d804 5334 #define USB_OTGCTL_DPLOW_SHIFT 5
bogdanm 87:6213f644d804 5335 #define USB_OTGCTL_DPHIGH_MASK 0x80u
bogdanm 87:6213f644d804 5336 #define USB_OTGCTL_DPHIGH_SHIFT 7
bogdanm 87:6213f644d804 5337 /* ISTAT Bit Fields */
bogdanm 87:6213f644d804 5338 #define USB_ISTAT_USBRST_MASK 0x1u
bogdanm 87:6213f644d804 5339 #define USB_ISTAT_USBRST_SHIFT 0
bogdanm 87:6213f644d804 5340 #define USB_ISTAT_ERROR_MASK 0x2u
bogdanm 87:6213f644d804 5341 #define USB_ISTAT_ERROR_SHIFT 1
bogdanm 87:6213f644d804 5342 #define USB_ISTAT_SOFTOK_MASK 0x4u
bogdanm 87:6213f644d804 5343 #define USB_ISTAT_SOFTOK_SHIFT 2
bogdanm 87:6213f644d804 5344 #define USB_ISTAT_TOKDNE_MASK 0x8u
bogdanm 87:6213f644d804 5345 #define USB_ISTAT_TOKDNE_SHIFT 3
bogdanm 87:6213f644d804 5346 #define USB_ISTAT_SLEEP_MASK 0x10u
bogdanm 87:6213f644d804 5347 #define USB_ISTAT_SLEEP_SHIFT 4
bogdanm 87:6213f644d804 5348 #define USB_ISTAT_RESUME_MASK 0x20u
bogdanm 87:6213f644d804 5349 #define USB_ISTAT_RESUME_SHIFT 5
bogdanm 87:6213f644d804 5350 #define USB_ISTAT_ATTACH_MASK 0x40u
bogdanm 87:6213f644d804 5351 #define USB_ISTAT_ATTACH_SHIFT 6
bogdanm 87:6213f644d804 5352 #define USB_ISTAT_STALL_MASK 0x80u
bogdanm 87:6213f644d804 5353 #define USB_ISTAT_STALL_SHIFT 7
bogdanm 87:6213f644d804 5354 /* INTEN Bit Fields */
bogdanm 87:6213f644d804 5355 #define USB_INTEN_USBRSTEN_MASK 0x1u
bogdanm 87:6213f644d804 5356 #define USB_INTEN_USBRSTEN_SHIFT 0
bogdanm 87:6213f644d804 5357 #define USB_INTEN_ERROREN_MASK 0x2u
bogdanm 87:6213f644d804 5358 #define USB_INTEN_ERROREN_SHIFT 1
bogdanm 87:6213f644d804 5359 #define USB_INTEN_SOFTOKEN_MASK 0x4u
bogdanm 87:6213f644d804 5360 #define USB_INTEN_SOFTOKEN_SHIFT 2
bogdanm 87:6213f644d804 5361 #define USB_INTEN_TOKDNEEN_MASK 0x8u
bogdanm 87:6213f644d804 5362 #define USB_INTEN_TOKDNEEN_SHIFT 3
bogdanm 87:6213f644d804 5363 #define USB_INTEN_SLEEPEN_MASK 0x10u
bogdanm 87:6213f644d804 5364 #define USB_INTEN_SLEEPEN_SHIFT 4
bogdanm 87:6213f644d804 5365 #define USB_INTEN_RESUMEEN_MASK 0x20u
bogdanm 87:6213f644d804 5366 #define USB_INTEN_RESUMEEN_SHIFT 5
bogdanm 87:6213f644d804 5367 #define USB_INTEN_ATTACHEN_MASK 0x40u
bogdanm 87:6213f644d804 5368 #define USB_INTEN_ATTACHEN_SHIFT 6
bogdanm 87:6213f644d804 5369 #define USB_INTEN_STALLEN_MASK 0x80u
bogdanm 87:6213f644d804 5370 #define USB_INTEN_STALLEN_SHIFT 7
bogdanm 87:6213f644d804 5371 /* ERRSTAT Bit Fields */
bogdanm 87:6213f644d804 5372 #define USB_ERRSTAT_PIDERR_MASK 0x1u
bogdanm 87:6213f644d804 5373 #define USB_ERRSTAT_PIDERR_SHIFT 0
bogdanm 87:6213f644d804 5374 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
bogdanm 87:6213f644d804 5375 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
bogdanm 87:6213f644d804 5376 #define USB_ERRSTAT_CRC16_MASK 0x4u
bogdanm 87:6213f644d804 5377 #define USB_ERRSTAT_CRC16_SHIFT 2
bogdanm 87:6213f644d804 5378 #define USB_ERRSTAT_DFN8_MASK 0x8u
bogdanm 87:6213f644d804 5379 #define USB_ERRSTAT_DFN8_SHIFT 3
bogdanm 87:6213f644d804 5380 #define USB_ERRSTAT_BTOERR_MASK 0x10u
bogdanm 87:6213f644d804 5381 #define USB_ERRSTAT_BTOERR_SHIFT 4
bogdanm 87:6213f644d804 5382 #define USB_ERRSTAT_DMAERR_MASK 0x20u
bogdanm 87:6213f644d804 5383 #define USB_ERRSTAT_DMAERR_SHIFT 5
bogdanm 87:6213f644d804 5384 #define USB_ERRSTAT_BTSERR_MASK 0x80u
bogdanm 87:6213f644d804 5385 #define USB_ERRSTAT_BTSERR_SHIFT 7
bogdanm 87:6213f644d804 5386 /* ERREN Bit Fields */
bogdanm 87:6213f644d804 5387 #define USB_ERREN_PIDERREN_MASK 0x1u
bogdanm 87:6213f644d804 5388 #define USB_ERREN_PIDERREN_SHIFT 0
bogdanm 87:6213f644d804 5389 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
bogdanm 87:6213f644d804 5390 #define USB_ERREN_CRC5EOFEN_SHIFT 1
bogdanm 87:6213f644d804 5391 #define USB_ERREN_CRC16EN_MASK 0x4u
bogdanm 87:6213f644d804 5392 #define USB_ERREN_CRC16EN_SHIFT 2
bogdanm 87:6213f644d804 5393 #define USB_ERREN_DFN8EN_MASK 0x8u
bogdanm 87:6213f644d804 5394 #define USB_ERREN_DFN8EN_SHIFT 3
bogdanm 87:6213f644d804 5395 #define USB_ERREN_BTOERREN_MASK 0x10u
bogdanm 87:6213f644d804 5396 #define USB_ERREN_BTOERREN_SHIFT 4
bogdanm 87:6213f644d804 5397 #define USB_ERREN_DMAERREN_MASK 0x20u
bogdanm 87:6213f644d804 5398 #define USB_ERREN_DMAERREN_SHIFT 5
bogdanm 87:6213f644d804 5399 #define USB_ERREN_BTSERREN_MASK 0x80u
bogdanm 87:6213f644d804 5400 #define USB_ERREN_BTSERREN_SHIFT 7
bogdanm 87:6213f644d804 5401 /* STAT Bit Fields */
bogdanm 87:6213f644d804 5402 #define USB_STAT_ODD_MASK 0x4u
bogdanm 87:6213f644d804 5403 #define USB_STAT_ODD_SHIFT 2
bogdanm 87:6213f644d804 5404 #define USB_STAT_TX_MASK 0x8u
bogdanm 87:6213f644d804 5405 #define USB_STAT_TX_SHIFT 3
bogdanm 87:6213f644d804 5406 #define USB_STAT_ENDP_MASK 0xF0u
bogdanm 87:6213f644d804 5407 #define USB_STAT_ENDP_SHIFT 4
bogdanm 87:6213f644d804 5408 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
bogdanm 87:6213f644d804 5409 /* CTL Bit Fields */
bogdanm 87:6213f644d804 5410 #define USB_CTL_USBENSOFEN_MASK 0x1u
bogdanm 87:6213f644d804 5411 #define USB_CTL_USBENSOFEN_SHIFT 0
bogdanm 87:6213f644d804 5412 #define USB_CTL_ODDRST_MASK 0x2u
bogdanm 87:6213f644d804 5413 #define USB_CTL_ODDRST_SHIFT 1
bogdanm 87:6213f644d804 5414 #define USB_CTL_RESUME_MASK 0x4u
bogdanm 87:6213f644d804 5415 #define USB_CTL_RESUME_SHIFT 2
bogdanm 87:6213f644d804 5416 #define USB_CTL_HOSTMODEEN_MASK 0x8u
bogdanm 87:6213f644d804 5417 #define USB_CTL_HOSTMODEEN_SHIFT 3
bogdanm 87:6213f644d804 5418 #define USB_CTL_RESET_MASK 0x10u
bogdanm 87:6213f644d804 5419 #define USB_CTL_RESET_SHIFT 4
bogdanm 87:6213f644d804 5420 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
bogdanm 87:6213f644d804 5421 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
bogdanm 87:6213f644d804 5422 #define USB_CTL_SE0_MASK 0x40u
bogdanm 87:6213f644d804 5423 #define USB_CTL_SE0_SHIFT 6
bogdanm 87:6213f644d804 5424 #define USB_CTL_JSTATE_MASK 0x80u
bogdanm 87:6213f644d804 5425 #define USB_CTL_JSTATE_SHIFT 7
bogdanm 87:6213f644d804 5426 /* ADDR Bit Fields */
bogdanm 87:6213f644d804 5427 #define USB_ADDR_ADDR_MASK 0x7Fu
bogdanm 87:6213f644d804 5428 #define USB_ADDR_ADDR_SHIFT 0
bogdanm 87:6213f644d804 5429 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
bogdanm 87:6213f644d804 5430 #define USB_ADDR_LSEN_MASK 0x80u
bogdanm 87:6213f644d804 5431 #define USB_ADDR_LSEN_SHIFT 7
bogdanm 87:6213f644d804 5432 /* BDTPAGE1 Bit Fields */
bogdanm 87:6213f644d804 5433 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
bogdanm 87:6213f644d804 5434 #define USB_BDTPAGE1_BDTBA_SHIFT 1
bogdanm 87:6213f644d804 5435 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
bogdanm 87:6213f644d804 5436 /* FRMNUML Bit Fields */
bogdanm 87:6213f644d804 5437 #define USB_FRMNUML_FRM_MASK 0xFFu
bogdanm 87:6213f644d804 5438 #define USB_FRMNUML_FRM_SHIFT 0
bogdanm 87:6213f644d804 5439 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
bogdanm 87:6213f644d804 5440 /* FRMNUMH Bit Fields */
bogdanm 87:6213f644d804 5441 #define USB_FRMNUMH_FRM_MASK 0x7u
bogdanm 87:6213f644d804 5442 #define USB_FRMNUMH_FRM_SHIFT 0
bogdanm 87:6213f644d804 5443 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
bogdanm 87:6213f644d804 5444 /* TOKEN Bit Fields */
bogdanm 87:6213f644d804 5445 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
bogdanm 87:6213f644d804 5446 #define USB_TOKEN_TOKENENDPT_SHIFT 0
bogdanm 87:6213f644d804 5447 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
bogdanm 87:6213f644d804 5448 #define USB_TOKEN_TOKENPID_MASK 0xF0u
bogdanm 87:6213f644d804 5449 #define USB_TOKEN_TOKENPID_SHIFT 4
bogdanm 87:6213f644d804 5450 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
bogdanm 87:6213f644d804 5451 /* SOFTHLD Bit Fields */
bogdanm 87:6213f644d804 5452 #define USB_SOFTHLD_CNT_MASK 0xFFu
bogdanm 87:6213f644d804 5453 #define USB_SOFTHLD_CNT_SHIFT 0
bogdanm 87:6213f644d804 5454 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
bogdanm 87:6213f644d804 5455 /* BDTPAGE2 Bit Fields */
bogdanm 87:6213f644d804 5456 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
bogdanm 87:6213f644d804 5457 #define USB_BDTPAGE2_BDTBA_SHIFT 0
bogdanm 87:6213f644d804 5458 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
bogdanm 87:6213f644d804 5459 /* BDTPAGE3 Bit Fields */
bogdanm 87:6213f644d804 5460 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
bogdanm 87:6213f644d804 5461 #define USB_BDTPAGE3_BDTBA_SHIFT 0
bogdanm 87:6213f644d804 5462 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
bogdanm 87:6213f644d804 5463 /* ENDPT Bit Fields */
bogdanm 87:6213f644d804 5464 #define USB_ENDPT_EPHSHK_MASK 0x1u
bogdanm 87:6213f644d804 5465 #define USB_ENDPT_EPHSHK_SHIFT 0
bogdanm 87:6213f644d804 5466 #define USB_ENDPT_EPSTALL_MASK 0x2u
bogdanm 87:6213f644d804 5467 #define USB_ENDPT_EPSTALL_SHIFT 1
bogdanm 87:6213f644d804 5468 #define USB_ENDPT_EPTXEN_MASK 0x4u
bogdanm 87:6213f644d804 5469 #define USB_ENDPT_EPTXEN_SHIFT 2
bogdanm 87:6213f644d804 5470 #define USB_ENDPT_EPRXEN_MASK 0x8u
bogdanm 87:6213f644d804 5471 #define USB_ENDPT_EPRXEN_SHIFT 3
bogdanm 87:6213f644d804 5472 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
bogdanm 87:6213f644d804 5473 #define USB_ENDPT_EPCTLDIS_SHIFT 4
bogdanm 87:6213f644d804 5474 #define USB_ENDPT_RETRYDIS_MASK 0x40u
bogdanm 87:6213f644d804 5475 #define USB_ENDPT_RETRYDIS_SHIFT 6
bogdanm 87:6213f644d804 5476 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
bogdanm 87:6213f644d804 5477 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
bogdanm 87:6213f644d804 5478 /* USBCTRL Bit Fields */
bogdanm 87:6213f644d804 5479 #define USB_USBCTRL_PDE_MASK 0x40u
bogdanm 87:6213f644d804 5480 #define USB_USBCTRL_PDE_SHIFT 6
bogdanm 87:6213f644d804 5481 #define USB_USBCTRL_SUSP_MASK 0x80u
bogdanm 87:6213f644d804 5482 #define USB_USBCTRL_SUSP_SHIFT 7
bogdanm 87:6213f644d804 5483 /* OBSERVE Bit Fields */
bogdanm 87:6213f644d804 5484 #define USB_OBSERVE_DMPD_MASK 0x10u
bogdanm 87:6213f644d804 5485 #define USB_OBSERVE_DMPD_SHIFT 4
bogdanm 87:6213f644d804 5486 #define USB_OBSERVE_DPPD_MASK 0x40u
bogdanm 87:6213f644d804 5487 #define USB_OBSERVE_DPPD_SHIFT 6
bogdanm 87:6213f644d804 5488 #define USB_OBSERVE_DPPU_MASK 0x80u
bogdanm 87:6213f644d804 5489 #define USB_OBSERVE_DPPU_SHIFT 7
bogdanm 87:6213f644d804 5490 /* CONTROL Bit Fields */
bogdanm 87:6213f644d804 5491 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
bogdanm 87:6213f644d804 5492 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
bogdanm 87:6213f644d804 5493 /* USBTRC0 Bit Fields */
bogdanm 87:6213f644d804 5494 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
bogdanm 87:6213f644d804 5495 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
bogdanm 87:6213f644d804 5496 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
bogdanm 87:6213f644d804 5497 #define USB_USBTRC0_SYNC_DET_SHIFT 1
bogdanm 87:6213f644d804 5498 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
bogdanm 87:6213f644d804 5499 #define USB_USBTRC0_USBRESMEN_SHIFT 5
bogdanm 87:6213f644d804 5500 #define USB_USBTRC0_USBRESET_MASK 0x80u
bogdanm 87:6213f644d804 5501 #define USB_USBTRC0_USBRESET_SHIFT 7
bogdanm 87:6213f644d804 5502 /* USBFRMADJUST Bit Fields */
bogdanm 87:6213f644d804 5503 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
bogdanm 87:6213f644d804 5504 #define USB_USBFRMADJUST_ADJ_SHIFT 0
bogdanm 87:6213f644d804 5505 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
bogdanm 87:6213f644d804 5506
bogdanm 87:6213f644d804 5507 /**
bogdanm 87:6213f644d804 5508 * @}
bogdanm 87:6213f644d804 5509 */ /* end of group USB_Register_Masks */
bogdanm 87:6213f644d804 5510
bogdanm 87:6213f644d804 5511
bogdanm 87:6213f644d804 5512 /* USB - Peripheral instance base addresses */
bogdanm 87:6213f644d804 5513 /** Peripheral USB0 base address */
bogdanm 87:6213f644d804 5514 #define USB0_BASE (0x40072000u)
bogdanm 87:6213f644d804 5515 /** Peripheral USB0 base pointer */
bogdanm 87:6213f644d804 5516 #define USB0 ((USB_Type *)USB0_BASE)
bogdanm 87:6213f644d804 5517
bogdanm 87:6213f644d804 5518 /**
bogdanm 87:6213f644d804 5519 * @}
bogdanm 87:6213f644d804 5520 */ /* end of group USB_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 5521
bogdanm 87:6213f644d804 5522
bogdanm 87:6213f644d804 5523 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5524 -- USBDCD Peripheral Access Layer
bogdanm 87:6213f644d804 5525 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5526
bogdanm 87:6213f644d804 5527 /**
bogdanm 87:6213f644d804 5528 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
bogdanm 87:6213f644d804 5529 * @{
bogdanm 87:6213f644d804 5530 */
bogdanm 87:6213f644d804 5531
bogdanm 87:6213f644d804 5532 /** USBDCD - Register Layout Typedef */
bogdanm 87:6213f644d804 5533 typedef struct {
bogdanm 87:6213f644d804 5534 __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
bogdanm 87:6213f644d804 5535 __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
bogdanm 87:6213f644d804 5536 __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
bogdanm 87:6213f644d804 5537 uint8_t RESERVED_0[4];
bogdanm 87:6213f644d804 5538 __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
bogdanm 87:6213f644d804 5539 __IO uint32_t TIMER1; /**< , offset: 0x14 */
bogdanm 87:6213f644d804 5540 __IO uint32_t TIMER2; /**< , offset: 0x18 */
bogdanm 87:6213f644d804 5541 } USBDCD_Type;
bogdanm 87:6213f644d804 5542
bogdanm 87:6213f644d804 5543 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5544 -- USBDCD Register Masks
bogdanm 87:6213f644d804 5545 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5546
bogdanm 87:6213f644d804 5547 /**
bogdanm 87:6213f644d804 5548 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
bogdanm 87:6213f644d804 5549 * @{
bogdanm 87:6213f644d804 5550 */
bogdanm 87:6213f644d804 5551
bogdanm 87:6213f644d804 5552 /* CONTROL Bit Fields */
bogdanm 87:6213f644d804 5553 #define USBDCD_CONTROL_IACK_MASK 0x1u
bogdanm 87:6213f644d804 5554 #define USBDCD_CONTROL_IACK_SHIFT 0
bogdanm 87:6213f644d804 5555 #define USBDCD_CONTROL_IF_MASK 0x100u
bogdanm 87:6213f644d804 5556 #define USBDCD_CONTROL_IF_SHIFT 8
bogdanm 87:6213f644d804 5557 #define USBDCD_CONTROL_IE_MASK 0x10000u
bogdanm 87:6213f644d804 5558 #define USBDCD_CONTROL_IE_SHIFT 16
bogdanm 87:6213f644d804 5559 #define USBDCD_CONTROL_START_MASK 0x1000000u
bogdanm 87:6213f644d804 5560 #define USBDCD_CONTROL_START_SHIFT 24
bogdanm 87:6213f644d804 5561 #define USBDCD_CONTROL_SR_MASK 0x2000000u
bogdanm 87:6213f644d804 5562 #define USBDCD_CONTROL_SR_SHIFT 25
bogdanm 87:6213f644d804 5563 /* CLOCK Bit Fields */
bogdanm 87:6213f644d804 5564 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
bogdanm 87:6213f644d804 5565 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
bogdanm 87:6213f644d804 5566 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
bogdanm 87:6213f644d804 5567 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
bogdanm 87:6213f644d804 5568 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
bogdanm 87:6213f644d804 5569 /* STATUS Bit Fields */
bogdanm 87:6213f644d804 5570 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
bogdanm 87:6213f644d804 5571 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
bogdanm 87:6213f644d804 5572 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
bogdanm 87:6213f644d804 5573 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
bogdanm 87:6213f644d804 5574 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
bogdanm 87:6213f644d804 5575 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
bogdanm 87:6213f644d804 5576 #define USBDCD_STATUS_ERR_MASK 0x100000u
bogdanm 87:6213f644d804 5577 #define USBDCD_STATUS_ERR_SHIFT 20
bogdanm 87:6213f644d804 5578 #define USBDCD_STATUS_TO_MASK 0x200000u
bogdanm 87:6213f644d804 5579 #define USBDCD_STATUS_TO_SHIFT 21
bogdanm 87:6213f644d804 5580 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
bogdanm 87:6213f644d804 5581 #define USBDCD_STATUS_ACTIVE_SHIFT 22
bogdanm 87:6213f644d804 5582 /* TIMER0 Bit Fields */
bogdanm 87:6213f644d804 5583 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
bogdanm 87:6213f644d804 5584 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
bogdanm 87:6213f644d804 5585 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
bogdanm 87:6213f644d804 5586 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
bogdanm 87:6213f644d804 5587 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
bogdanm 87:6213f644d804 5588 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
bogdanm 87:6213f644d804 5589 /* TIMER1 Bit Fields */
bogdanm 87:6213f644d804 5590 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
bogdanm 87:6213f644d804 5591 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
bogdanm 87:6213f644d804 5592 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
bogdanm 87:6213f644d804 5593 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
bogdanm 87:6213f644d804 5594 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
bogdanm 87:6213f644d804 5595 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
bogdanm 87:6213f644d804 5596 /* TIMER2 Bit Fields */
bogdanm 87:6213f644d804 5597 #define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
bogdanm 87:6213f644d804 5598 #define USBDCD_TIMER2_CHECK_DM_SHIFT 0
bogdanm 87:6213f644d804 5599 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
bogdanm 87:6213f644d804 5600 #define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
bogdanm 87:6213f644d804 5601 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
bogdanm 87:6213f644d804 5602 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
bogdanm 87:6213f644d804 5603
bogdanm 87:6213f644d804 5604 /**
bogdanm 87:6213f644d804 5605 * @}
bogdanm 87:6213f644d804 5606 */ /* end of group USBDCD_Register_Masks */
bogdanm 87:6213f644d804 5607
bogdanm 87:6213f644d804 5608
bogdanm 87:6213f644d804 5609 /* USBDCD - Peripheral instance base addresses */
bogdanm 87:6213f644d804 5610 /** Peripheral USBDCD base address */
bogdanm 87:6213f644d804 5611 #define USBDCD_BASE (0x40035000u)
bogdanm 87:6213f644d804 5612 /** Peripheral USBDCD base pointer */
bogdanm 87:6213f644d804 5613 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
bogdanm 87:6213f644d804 5614
bogdanm 87:6213f644d804 5615 /**
bogdanm 87:6213f644d804 5616 * @}
bogdanm 87:6213f644d804 5617 */ /* end of group USBDCD_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 5618
bogdanm 87:6213f644d804 5619
bogdanm 87:6213f644d804 5620 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5621 -- VREF Peripheral Access Layer
bogdanm 87:6213f644d804 5622 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5623
bogdanm 87:6213f644d804 5624 /**
bogdanm 87:6213f644d804 5625 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
bogdanm 87:6213f644d804 5626 * @{
bogdanm 87:6213f644d804 5627 */
bogdanm 87:6213f644d804 5628
bogdanm 87:6213f644d804 5629 /** VREF - Register Layout Typedef */
bogdanm 87:6213f644d804 5630 typedef struct {
bogdanm 87:6213f644d804 5631 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
bogdanm 87:6213f644d804 5632 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
bogdanm 87:6213f644d804 5633 } VREF_Type;
bogdanm 87:6213f644d804 5634
bogdanm 87:6213f644d804 5635 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5636 -- VREF Register Masks
bogdanm 87:6213f644d804 5637 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5638
bogdanm 87:6213f644d804 5639 /**
bogdanm 87:6213f644d804 5640 * @addtogroup VREF_Register_Masks VREF Register Masks
bogdanm 87:6213f644d804 5641 * @{
bogdanm 87:6213f644d804 5642 */
bogdanm 87:6213f644d804 5643
bogdanm 87:6213f644d804 5644 /* TRM Bit Fields */
bogdanm 87:6213f644d804 5645 #define VREF_TRM_TRIM_MASK 0x3Fu
bogdanm 87:6213f644d804 5646 #define VREF_TRM_TRIM_SHIFT 0
bogdanm 87:6213f644d804 5647 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
bogdanm 87:6213f644d804 5648 #define VREF_TRM_CHOPEN_MASK 0x40u
bogdanm 87:6213f644d804 5649 #define VREF_TRM_CHOPEN_SHIFT 6
bogdanm 87:6213f644d804 5650 /* SC Bit Fields */
bogdanm 87:6213f644d804 5651 #define VREF_SC_MODE_LV_MASK 0x3u
bogdanm 87:6213f644d804 5652 #define VREF_SC_MODE_LV_SHIFT 0
bogdanm 87:6213f644d804 5653 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
bogdanm 87:6213f644d804 5654 #define VREF_SC_VREFST_MASK 0x4u
bogdanm 87:6213f644d804 5655 #define VREF_SC_VREFST_SHIFT 2
bogdanm 87:6213f644d804 5656 #define VREF_SC_REGEN_MASK 0x40u
bogdanm 87:6213f644d804 5657 #define VREF_SC_REGEN_SHIFT 6
bogdanm 87:6213f644d804 5658 #define VREF_SC_VREFEN_MASK 0x80u
bogdanm 87:6213f644d804 5659 #define VREF_SC_VREFEN_SHIFT 7
bogdanm 87:6213f644d804 5660
bogdanm 87:6213f644d804 5661 /**
bogdanm 87:6213f644d804 5662 * @}
bogdanm 87:6213f644d804 5663 */ /* end of group VREF_Register_Masks */
bogdanm 87:6213f644d804 5664
bogdanm 87:6213f644d804 5665
bogdanm 87:6213f644d804 5666 /* VREF - Peripheral instance base addresses */
bogdanm 87:6213f644d804 5667 /** Peripheral VREF base address */
bogdanm 87:6213f644d804 5668 #define VREF_BASE (0x40074000u)
bogdanm 87:6213f644d804 5669 /** Peripheral VREF base pointer */
bogdanm 87:6213f644d804 5670 #define VREF ((VREF_Type *)VREF_BASE)
bogdanm 87:6213f644d804 5671
bogdanm 87:6213f644d804 5672 /**
bogdanm 87:6213f644d804 5673 * @}
bogdanm 87:6213f644d804 5674 */ /* end of group VREF_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 5675
bogdanm 87:6213f644d804 5676
bogdanm 87:6213f644d804 5677 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5678 -- WDOG Peripheral Access Layer
bogdanm 87:6213f644d804 5679 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5680
bogdanm 87:6213f644d804 5681 /**
bogdanm 87:6213f644d804 5682 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
bogdanm 87:6213f644d804 5683 * @{
bogdanm 87:6213f644d804 5684 */
bogdanm 87:6213f644d804 5685
bogdanm 87:6213f644d804 5686 /** WDOG - Register Layout Typedef */
bogdanm 87:6213f644d804 5687 typedef struct {
bogdanm 87:6213f644d804 5688 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
bogdanm 87:6213f644d804 5689 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
bogdanm 87:6213f644d804 5690 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
bogdanm 87:6213f644d804 5691 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
bogdanm 87:6213f644d804 5692 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
bogdanm 87:6213f644d804 5693 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
bogdanm 87:6213f644d804 5694 __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
bogdanm 87:6213f644d804 5695 __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
bogdanm 87:6213f644d804 5696 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
bogdanm 87:6213f644d804 5697 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
bogdanm 87:6213f644d804 5698 __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
bogdanm 87:6213f644d804 5699 __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
bogdanm 87:6213f644d804 5700 } WDOG_Type;
bogdanm 87:6213f644d804 5701
bogdanm 87:6213f644d804 5702 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5703 -- WDOG Register Masks
bogdanm 87:6213f644d804 5704 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5705
bogdanm 87:6213f644d804 5706 /**
bogdanm 87:6213f644d804 5707 * @addtogroup WDOG_Register_Masks WDOG Register Masks
bogdanm 87:6213f644d804 5708 * @{
bogdanm 87:6213f644d804 5709 */
bogdanm 87:6213f644d804 5710
bogdanm 87:6213f644d804 5711 /* STCTRLH Bit Fields */
bogdanm 87:6213f644d804 5712 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
bogdanm 87:6213f644d804 5713 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
bogdanm 87:6213f644d804 5714 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
bogdanm 87:6213f644d804 5715 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
bogdanm 87:6213f644d804 5716 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
bogdanm 87:6213f644d804 5717 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
bogdanm 87:6213f644d804 5718 #define WDOG_STCTRLH_WINEN_MASK 0x8u
bogdanm 87:6213f644d804 5719 #define WDOG_STCTRLH_WINEN_SHIFT 3
bogdanm 87:6213f644d804 5720 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
bogdanm 87:6213f644d804 5721 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
bogdanm 87:6213f644d804 5722 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
bogdanm 87:6213f644d804 5723 #define WDOG_STCTRLH_DBGEN_SHIFT 5
bogdanm 87:6213f644d804 5724 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
bogdanm 87:6213f644d804 5725 #define WDOG_STCTRLH_STOPEN_SHIFT 6
bogdanm 87:6213f644d804 5726 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
bogdanm 87:6213f644d804 5727 #define WDOG_STCTRLH_WAITEN_SHIFT 7
bogdanm 87:6213f644d804 5728 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
bogdanm 87:6213f644d804 5729 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
bogdanm 87:6213f644d804 5730 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
bogdanm 87:6213f644d804 5731 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
bogdanm 87:6213f644d804 5732 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
bogdanm 87:6213f644d804 5733 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
bogdanm 87:6213f644d804 5734 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
bogdanm 87:6213f644d804 5735 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
bogdanm 87:6213f644d804 5736 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
bogdanm 87:6213f644d804 5737 /* STCTRLL Bit Fields */
bogdanm 87:6213f644d804 5738 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
bogdanm 87:6213f644d804 5739 #define WDOG_STCTRLL_INTFLG_SHIFT 15
bogdanm 87:6213f644d804 5740 /* TOVALH Bit Fields */
bogdanm 87:6213f644d804 5741 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
bogdanm 87:6213f644d804 5742 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
bogdanm 87:6213f644d804 5743 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
bogdanm 87:6213f644d804 5744 /* TOVALL Bit Fields */
bogdanm 87:6213f644d804 5745 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
bogdanm 87:6213f644d804 5746 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
bogdanm 87:6213f644d804 5747 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
bogdanm 87:6213f644d804 5748 /* WINH Bit Fields */
bogdanm 87:6213f644d804 5749 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
bogdanm 87:6213f644d804 5750 #define WDOG_WINH_WINHIGH_SHIFT 0
bogdanm 87:6213f644d804 5751 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
bogdanm 87:6213f644d804 5752 /* WINL Bit Fields */
bogdanm 87:6213f644d804 5753 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
bogdanm 87:6213f644d804 5754 #define WDOG_WINL_WINLOW_SHIFT 0
bogdanm 87:6213f644d804 5755 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
bogdanm 87:6213f644d804 5756 /* REFRESH Bit Fields */
bogdanm 87:6213f644d804 5757 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
bogdanm 87:6213f644d804 5758 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
bogdanm 87:6213f644d804 5759 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
bogdanm 87:6213f644d804 5760 /* UNLOCK Bit Fields */
bogdanm 87:6213f644d804 5761 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
bogdanm 87:6213f644d804 5762 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
bogdanm 87:6213f644d804 5763 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
bogdanm 87:6213f644d804 5764 /* TMROUTH Bit Fields */
bogdanm 87:6213f644d804 5765 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
bogdanm 87:6213f644d804 5766 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
bogdanm 87:6213f644d804 5767 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
bogdanm 87:6213f644d804 5768 /* TMROUTL Bit Fields */
bogdanm 87:6213f644d804 5769 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
bogdanm 87:6213f644d804 5770 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
bogdanm 87:6213f644d804 5771 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
bogdanm 87:6213f644d804 5772 /* RSTCNT Bit Fields */
bogdanm 87:6213f644d804 5773 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
bogdanm 87:6213f644d804 5774 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
bogdanm 87:6213f644d804 5775 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
bogdanm 87:6213f644d804 5776 /* PRESC Bit Fields */
bogdanm 87:6213f644d804 5777 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
bogdanm 87:6213f644d804 5778 #define WDOG_PRESC_PRESCVAL_SHIFT 8
bogdanm 87:6213f644d804 5779 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
bogdanm 87:6213f644d804 5780
bogdanm 87:6213f644d804 5781 /**
bogdanm 87:6213f644d804 5782 * @}
bogdanm 87:6213f644d804 5783 */ /* end of group WDOG_Register_Masks */
bogdanm 87:6213f644d804 5784
bogdanm 87:6213f644d804 5785
bogdanm 87:6213f644d804 5786 /* WDOG - Peripheral instance base addresses */
bogdanm 87:6213f644d804 5787 /** Peripheral WDOG base address */
bogdanm 87:6213f644d804 5788 #define WDOG_BASE (0x40052000u)
bogdanm 87:6213f644d804 5789 /** Peripheral WDOG base pointer */
bogdanm 87:6213f644d804 5790 #define WDOG ((WDOG_Type *)WDOG_BASE)
bogdanm 87:6213f644d804 5791
bogdanm 87:6213f644d804 5792 /**
bogdanm 87:6213f644d804 5793 * @}
bogdanm 87:6213f644d804 5794 */ /* end of group WDOG_Peripheral_Access_Layer */
bogdanm 87:6213f644d804 5795
bogdanm 87:6213f644d804 5796
bogdanm 87:6213f644d804 5797 /*
bogdanm 87:6213f644d804 5798 ** End of section using anonymous unions
bogdanm 87:6213f644d804 5799 */
bogdanm 87:6213f644d804 5800
bogdanm 87:6213f644d804 5801 #if defined(__ARMCC_VERSION)
bogdanm 87:6213f644d804 5802 #pragma pop
bogdanm 87:6213f644d804 5803 #elif defined(__CWCC__)
bogdanm 87:6213f644d804 5804 #pragma pop
bogdanm 87:6213f644d804 5805 #elif defined(__GNUC__)
bogdanm 87:6213f644d804 5806 /* leave anonymous unions enabled */
bogdanm 87:6213f644d804 5807 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 87:6213f644d804 5808 #pragma language=default
bogdanm 87:6213f644d804 5809 #else
bogdanm 87:6213f644d804 5810 #error Not supported compiler type
bogdanm 87:6213f644d804 5811 #endif
bogdanm 87:6213f644d804 5812
bogdanm 87:6213f644d804 5813 /**
bogdanm 87:6213f644d804 5814 * @}
bogdanm 87:6213f644d804 5815 */ /* end of group Peripheral_access_layer */
bogdanm 87:6213f644d804 5816
bogdanm 87:6213f644d804 5817
bogdanm 87:6213f644d804 5818 /* ----------------------------------------------------------------------------
bogdanm 87:6213f644d804 5819 -- Backward Compatibility
bogdanm 87:6213f644d804 5820 ---------------------------------------------------------------------------- */
bogdanm 87:6213f644d804 5821
bogdanm 87:6213f644d804 5822 /**
bogdanm 87:6213f644d804 5823 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
bogdanm 87:6213f644d804 5824 * @{
bogdanm 87:6213f644d804 5825 */
bogdanm 87:6213f644d804 5826
bogdanm 87:6213f644d804 5827 /* No backward compatibility issues. */
bogdanm 87:6213f644d804 5828
bogdanm 87:6213f644d804 5829 /**
bogdanm 87:6213f644d804 5830 * @}
bogdanm 87:6213f644d804 5831 */ /* end of group Backward_Compatibility_Symbols */
bogdanm 87:6213f644d804 5832
bogdanm 87:6213f644d804 5833
bogdanm 87:6213f644d804 5834 #endif /* #if !defined(MK20D5_H_) */
bogdanm 87:6213f644d804 5835
bogdanm 87:6213f644d804 5836 /* MK20D5.h, eof. */