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/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_RZ_A1H/rspi_iobitmask.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : rspi_iobitmask.h
bogdanm 92:4fc01daae5a5 25 * $Rev: 1114 $
bogdanm 92:4fc01daae5a5 26 * $Date:: 2014-07-09 14:56:39 +0900#$
bogdanm 92:4fc01daae5a5 27 * Description : Renesas Serial Peripheral Interface register define header
bogdanm 92:4fc01daae5a5 28 *******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef RSPI_IOBITMASK_H
bogdanm 92:4fc01daae5a5 30 #define RSPI_IOBITMASK_H
bogdanm 92:4fc01daae5a5 31
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 /* ==== Mask values for IO registers ==== */
bogdanm 92:4fc01daae5a5 34 #define RSPIn_SPCR_MODFEN (0x04u)
bogdanm 92:4fc01daae5a5 35 #define RSPIn_SPCR_MSTR (0x08u)
bogdanm 92:4fc01daae5a5 36 #define RSPIn_SPCR_SPEIE (0x10u)
bogdanm 92:4fc01daae5a5 37 #define RSPIn_SPCR_SPTIE (0x20u)
bogdanm 92:4fc01daae5a5 38 #define RSPIn_SPCR_SPE (0x40u)
bogdanm 92:4fc01daae5a5 39 #define RSPIn_SPCR_SPRIE (0x80u)
bogdanm 92:4fc01daae5a5 40
bogdanm 92:4fc01daae5a5 41 #define RSPIn_SSLP_SSL0P (0x01u)
bogdanm 92:4fc01daae5a5 42
bogdanm 92:4fc01daae5a5 43 #define RSPIn_SPPCR_SPLP (0x01u)
bogdanm 92:4fc01daae5a5 44 #define RSPIn_SPPCR_MOIFV (0x10u)
bogdanm 92:4fc01daae5a5 45 #define RSPIn_SPPCR_MOIFE (0x20u)
bogdanm 92:4fc01daae5a5 46
bogdanm 92:4fc01daae5a5 47 #define RSPIn_SPSR_OVRF (0x01u)
bogdanm 92:4fc01daae5a5 48 #define RSPIn_SPSR_MODF (0x04u)
bogdanm 92:4fc01daae5a5 49 #define RSPIn_SPSR_SPTEF (0x20u)
bogdanm 92:4fc01daae5a5 50 #define RSPIn_SPSR_TEND (0x40u)
bogdanm 92:4fc01daae5a5 51 #define RSPIn_SPSR_SPRF (0x80u)
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 #define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL)
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 #define RSPIn_SPDR_UINT16 (0xFFFFu)
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 #define RSPIn_SPDR_UINT8 (0xFFu)
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 #define RSPIn_SPSCR_SPSLN (0x03u)
bogdanm 92:4fc01daae5a5 60
bogdanm 92:4fc01daae5a5 61 #define RSPIn_SPSSR_SPCP (0x03u)
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 #define RSPIn_SPBR_SPR (0xFFu)
bogdanm 92:4fc01daae5a5 64
bogdanm 92:4fc01daae5a5 65 #define RSPIn_SPDCR_SPLW (0x60u)
bogdanm 92:4fc01daae5a5 66 #define RSPIn_SPDCR_TXDMY (0x80u)
bogdanm 92:4fc01daae5a5 67
bogdanm 92:4fc01daae5a5 68 #define RSPIn_SPCKD_SCKDL (0x07u)
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 #define RSPIn_SSLND_SLNDL (0x07u)
bogdanm 92:4fc01daae5a5 71
bogdanm 92:4fc01daae5a5 72 #define RSPIn_SPND_SPNDL (0x07u)
bogdanm 92:4fc01daae5a5 73
bogdanm 92:4fc01daae5a5 74 #define RSPIn_SPCMD0_CPHA (0x0001u)
bogdanm 92:4fc01daae5a5 75 #define RSPIn_SPCMD0_CPOL (0x0002u)
bogdanm 92:4fc01daae5a5 76 #define RSPIn_SPCMD0_BRDV (0x000Cu)
bogdanm 92:4fc01daae5a5 77 #define RSPIn_SPCMD0_SSLKP (0x0080u)
bogdanm 92:4fc01daae5a5 78 #define RSPIn_SPCMD0_SPB (0x0F00u)
bogdanm 92:4fc01daae5a5 79 #define RSPIn_SPCMD0_LSBF (0x1000u)
bogdanm 92:4fc01daae5a5 80 #define RSPIn_SPCMD0_SPNDEN (0x2000u)
bogdanm 92:4fc01daae5a5 81 #define RSPIn_SPCMD0_SLNDEN (0x4000u)
bogdanm 92:4fc01daae5a5 82 #define RSPIn_SPCMD0_SCKDEN (0x8000u)
bogdanm 92:4fc01daae5a5 83
bogdanm 92:4fc01daae5a5 84 #define RSPIn_SPCMD1_CPHA (0x0001u)
bogdanm 92:4fc01daae5a5 85 #define RSPIn_SPCMD1_CPOL (0x0002u)
bogdanm 92:4fc01daae5a5 86 #define RSPIn_SPCMD1_BRDV (0x000Cu)
bogdanm 92:4fc01daae5a5 87 #define RSPIn_SPCMD1_SSLKP (0x0080u)
bogdanm 92:4fc01daae5a5 88 #define RSPIn_SPCMD1_SPB (0x0F00u)
bogdanm 92:4fc01daae5a5 89 #define RSPIn_SPCMD1_LSBF (0x1000u)
bogdanm 92:4fc01daae5a5 90 #define RSPIn_SPCMD1_SPNDEN (0x2000u)
bogdanm 92:4fc01daae5a5 91 #define RSPIn_SPCMD1_SLNDEN (0x4000u)
bogdanm 92:4fc01daae5a5 92 #define RSPIn_SPCMD1_SCKDEN (0x8000u)
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 #define RSPIn_SPCMD2_CPHA (0x0001u)
bogdanm 92:4fc01daae5a5 95 #define RSPIn_SPCMD2_CPOL (0x0002u)
bogdanm 92:4fc01daae5a5 96 #define RSPIn_SPCMD2_BRDV (0x000Cu)
bogdanm 92:4fc01daae5a5 97 #define RSPIn_SPCMD2_SSLKP (0x0080u)
bogdanm 92:4fc01daae5a5 98 #define RSPIn_SPCMD2_SPB (0x0F00u)
bogdanm 92:4fc01daae5a5 99 #define RSPIn_SPCMD2_LSBF (0x1000u)
bogdanm 92:4fc01daae5a5 100 #define RSPIn_SPCMD2_SPNDEN (0x2000u)
bogdanm 92:4fc01daae5a5 101 #define RSPIn_SPCMD2_SLNDEN (0x4000u)
bogdanm 92:4fc01daae5a5 102 #define RSPIn_SPCMD2_SCKDEN (0x8000u)
bogdanm 92:4fc01daae5a5 103
bogdanm 92:4fc01daae5a5 104 #define RSPIn_SPCMD3_CPHA (0x0001u)
bogdanm 92:4fc01daae5a5 105 #define RSPIn_SPCMD3_CPOL (0x0002u)
bogdanm 92:4fc01daae5a5 106 #define RSPIn_SPCMD3_BRDV (0x000Cu)
bogdanm 92:4fc01daae5a5 107 #define RSPIn_SPCMD3_SSLKP (0x0080u)
bogdanm 92:4fc01daae5a5 108 #define RSPIn_SPCMD3_SPB (0x0F00u)
bogdanm 92:4fc01daae5a5 109 #define RSPIn_SPCMD3_LSBF (0x1000u)
bogdanm 92:4fc01daae5a5 110 #define RSPIn_SPCMD3_SPNDEN (0x2000u)
bogdanm 92:4fc01daae5a5 111 #define RSPIn_SPCMD3_SLNDEN (0x4000u)
bogdanm 92:4fc01daae5a5 112 #define RSPIn_SPCMD3_SCKDEN (0x8000u)
bogdanm 92:4fc01daae5a5 113
bogdanm 92:4fc01daae5a5 114 #define RSPIn_SPBFCR_RXTRG (0x07u)
bogdanm 92:4fc01daae5a5 115 #define RSPIn_SPBFCR_TXTRG (0x30u)
bogdanm 92:4fc01daae5a5 116 #define RSPIn_SPBFCR_RXRST (0x40u)
bogdanm 92:4fc01daae5a5 117 #define RSPIn_SPBFCR_TXRST (0x80u)
bogdanm 92:4fc01daae5a5 118
bogdanm 92:4fc01daae5a5 119 #define RSPIn_SPBFDR_R (0x003Fu)
bogdanm 92:4fc01daae5a5 120 #define RSPIn_SPBFDR_T (0x0F00u)
bogdanm 92:4fc01daae5a5 121
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 /* ==== Shift values for IO registers ==== */
bogdanm 92:4fc01daae5a5 124 #define RSPIn_SPCR_MODFEN_SHIFT (2u)
bogdanm 92:4fc01daae5a5 125 #define RSPIn_SPCR_MSTR_SHIFT (3u)
bogdanm 92:4fc01daae5a5 126 #define RSPIn_SPCR_SPEIE_SHIFT (4u)
bogdanm 92:4fc01daae5a5 127 #define RSPIn_SPCR_SPTIE_SHIFT (5u)
bogdanm 92:4fc01daae5a5 128 #define RSPIn_SPCR_SPE_SHIFT (6u)
bogdanm 92:4fc01daae5a5 129 #define RSPIn_SPCR_SPRIE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 #define RSPIn_SSLP_SSL0P_SHIFT (0u)
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133 #define RSPIn_SPPCR_SPLP_SHIFT (0u)
bogdanm 92:4fc01daae5a5 134 #define RSPIn_SPPCR_MOIFV_SHIFT (4u)
bogdanm 92:4fc01daae5a5 135 #define RSPIn_SPPCR_MOIFE_SHIFT (5u)
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 #define RSPIn_SPSR_OVRF_SHIFT (0u)
bogdanm 92:4fc01daae5a5 138 #define RSPIn_SPSR_MODF_SHIFT (2u)
bogdanm 92:4fc01daae5a5 139 #define RSPIn_SPSR_SPTEF_SHIFT (5u)
bogdanm 92:4fc01daae5a5 140 #define RSPIn_SPSR_TEND_SHIFT (6u)
bogdanm 92:4fc01daae5a5 141 #define RSPIn_SPSR_SPRF_SHIFT (7u)
bogdanm 92:4fc01daae5a5 142
bogdanm 92:4fc01daae5a5 143 #define RSPIn_SPDR_UINT32_SHIFT (0u)
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 #define RSPIn_SPDR_UINT16_SHIFT (0u)
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 #define RSPIn_SPDR_UINT8_SHIFT (0u)
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 #define RSPIn_SPSCR_SPSLN_SHIFT (0u)
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 #define RSPIn_SPSSR_SPCP_SHIFT (0u)
bogdanm 92:4fc01daae5a5 152
bogdanm 92:4fc01daae5a5 153 #define RSPIn_SPBR_SPR_SHIFT (0u)
bogdanm 92:4fc01daae5a5 154
bogdanm 92:4fc01daae5a5 155 #define RSPIn_SPDCR_SPLW_SHIFT (5u)
bogdanm 92:4fc01daae5a5 156 #define RSPIn_SPDCR_TXDMY_SHIFT (7u)
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 #define RSPIn_SPCKD_SCKDL_SHIFT (0u)
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 #define RSPIn_SSLND_SLNDL_SHIFT (0u)
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 #define RSPIn_SPND_SPNDL_SHIFT (0u)
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 #define RSPIn_SPCMD0_CPHA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 165 #define RSPIn_SPCMD0_CPOL_SHIFT (1u)
bogdanm 92:4fc01daae5a5 166 #define RSPIn_SPCMD0_BRDV_SHIFT (2u)
bogdanm 92:4fc01daae5a5 167 #define RSPIn_SPCMD0_SSLKP_SHIFT (7u)
bogdanm 92:4fc01daae5a5 168 #define RSPIn_SPCMD0_SPB_SHIFT (8u)
bogdanm 92:4fc01daae5a5 169 #define RSPIn_SPCMD0_LSBF_SHIFT (12u)
bogdanm 92:4fc01daae5a5 170 #define RSPIn_SPCMD0_SPNDEN_SHIFT (13u)
bogdanm 92:4fc01daae5a5 171 #define RSPIn_SPCMD0_SLNDEN_SHIFT (14u)
bogdanm 92:4fc01daae5a5 172 #define RSPIn_SPCMD0_SCKDEN_SHIFT (15u)
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174 #define RSPIn_SPCMD1_CPHA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 175 #define RSPIn_SPCMD1_CPOL_SHIFT (1u)
bogdanm 92:4fc01daae5a5 176 #define RSPIn_SPCMD1_BRDV_SHIFT (2u)
bogdanm 92:4fc01daae5a5 177 #define RSPIn_SPCMD1_SSLKP_SHIFT (7u)
bogdanm 92:4fc01daae5a5 178 #define RSPIn_SPCMD1_SPB_SHIFT (8u)
bogdanm 92:4fc01daae5a5 179 #define RSPIn_SPCMD1_LSBF_SHIFT (12u)
bogdanm 92:4fc01daae5a5 180 #define RSPIn_SPCMD1_SPNDEN_SHIFT (13u)
bogdanm 92:4fc01daae5a5 181 #define RSPIn_SPCMD1_SLNDEN_SHIFT (14u)
bogdanm 92:4fc01daae5a5 182 #define RSPIn_SPCMD1_SCKDEN_SHIFT (15u)
bogdanm 92:4fc01daae5a5 183
bogdanm 92:4fc01daae5a5 184 #define RSPIn_SPCMD2_CPHA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 185 #define RSPIn_SPCMD2_CPOL_SHIFT (1u)
bogdanm 92:4fc01daae5a5 186 #define RSPIn_SPCMD2_BRDV_SHIFT (2u)
bogdanm 92:4fc01daae5a5 187 #define RSPIn_SPCMD2_SSLKP_SHIFT (7u)
bogdanm 92:4fc01daae5a5 188 #define RSPIn_SPCMD2_SPB_SHIFT (8u)
bogdanm 92:4fc01daae5a5 189 #define RSPIn_SPCMD2_LSBF_SHIFT (12u)
bogdanm 92:4fc01daae5a5 190 #define RSPIn_SPCMD2_SPNDEN_SHIFT (13u)
bogdanm 92:4fc01daae5a5 191 #define RSPIn_SPCMD2_SLNDEN_SHIFT (14u)
bogdanm 92:4fc01daae5a5 192 #define RSPIn_SPCMD2_SCKDEN_SHIFT (15u)
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194 #define RSPIn_SPCMD3_CPHA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 195 #define RSPIn_SPCMD3_CPOL_SHIFT (1u)
bogdanm 92:4fc01daae5a5 196 #define RSPIn_SPCMD3_BRDV_SHIFT (2u)
bogdanm 92:4fc01daae5a5 197 #define RSPIn_SPCMD3_SSLKP_SHIFT (7u)
bogdanm 92:4fc01daae5a5 198 #define RSPIn_SPCMD3_SPB_SHIFT (8u)
bogdanm 92:4fc01daae5a5 199 #define RSPIn_SPCMD3_LSBF_SHIFT (12u)
bogdanm 92:4fc01daae5a5 200 #define RSPIn_SPCMD3_SPNDEN_SHIFT (13u)
bogdanm 92:4fc01daae5a5 201 #define RSPIn_SPCMD3_SLNDEN_SHIFT (14u)
bogdanm 92:4fc01daae5a5 202 #define RSPIn_SPCMD3_SCKDEN_SHIFT (15u)
bogdanm 92:4fc01daae5a5 203
bogdanm 92:4fc01daae5a5 204 #define RSPIn_SPBFCR_RXTRG_SHIFT (0u)
bogdanm 92:4fc01daae5a5 205 #define RSPIn_SPBFCR_TXTRG_SHIFT (4u)
bogdanm 92:4fc01daae5a5 206 #define RSPIn_SPBFCR_RXRST_SHIFT (6u)
bogdanm 92:4fc01daae5a5 207 #define RSPIn_SPBFCR_TXRST_SHIFT (7u)
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 #define RSPIn_SPBFDR_R_SHIFT (0u)
bogdanm 92:4fc01daae5a5 210 #define RSPIn_SPBFDR_T_SHIFT (8u)
bogdanm 92:4fc01daae5a5 211
bogdanm 92:4fc01daae5a5 212
bogdanm 92:4fc01daae5a5 213 #endif /* RSPI_IOBITMASK_H */
bogdanm 92:4fc01daae5a5 214
bogdanm 92:4fc01daae5a5 215 /* End of File */