frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_MTS_MDOT_F405RG/stm32f405xx.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f405xx.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V2.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 * This file contains:
bogdanm 92:4fc01daae5a5 10 * - Data structures and the address mapping for all peripherals
bogdanm 92:4fc01daae5a5 11 * - Peripheral's registers declarations and bits definition
bogdanm 92:4fc01daae5a5 12 * - Macros to access peripheral’s registers hardware
bogdanm 92:4fc01daae5a5 13 *
bogdanm 92:4fc01daae5a5 14 ******************************************************************************
bogdanm 92:4fc01daae5a5 15 * @attention
bogdanm 92:4fc01daae5a5 16 *
bogdanm 92:4fc01daae5a5 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 18 *
bogdanm 92:4fc01daae5a5 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 20 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 22 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 25 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 27 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 28 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 29 *
bogdanm 92:4fc01daae5a5 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 40 *
bogdanm 92:4fc01daae5a5 41 ******************************************************************************
bogdanm 92:4fc01daae5a5 42 */
bogdanm 92:4fc01daae5a5 43
bogdanm 92:4fc01daae5a5 44 /** @addtogroup CMSIS
bogdanm 92:4fc01daae5a5 45 * @{
bogdanm 92:4fc01daae5a5 46 */
bogdanm 92:4fc01daae5a5 47
bogdanm 92:4fc01daae5a5 48 /** @addtogroup stm32f405xx
bogdanm 92:4fc01daae5a5 49 * @{
bogdanm 92:4fc01daae5a5 50 */
bogdanm 92:4fc01daae5a5 51
bogdanm 92:4fc01daae5a5 52 #ifndef __STM32F405xx_H
bogdanm 92:4fc01daae5a5 53 #define __STM32F405xx_H
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 56 extern "C" {
bogdanm 92:4fc01daae5a5 57 #endif /* __cplusplus */
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59
bogdanm 92:4fc01daae5a5 60 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 92:4fc01daae5a5 61 * @{
bogdanm 92:4fc01daae5a5 62 */
bogdanm 92:4fc01daae5a5 63
bogdanm 92:4fc01daae5a5 64 /**
bogdanm 92:4fc01daae5a5 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm 92:4fc01daae5a5 66 */
bogdanm 92:4fc01daae5a5 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
bogdanm 92:4fc01daae5a5 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
bogdanm 92:4fc01daae5a5 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
bogdanm 92:4fc01daae5a5 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 92:4fc01daae5a5 71 #define __FPU_PRESENT 1 /*!< FPU present */
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 /**
bogdanm 92:4fc01daae5a5 74 * @}
bogdanm 92:4fc01daae5a5 75 */
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 92:4fc01daae5a5 78 * @{
bogdanm 92:4fc01daae5a5 79 */
bogdanm 92:4fc01daae5a5 80
bogdanm 92:4fc01daae5a5 81 /**
bogdanm 92:4fc01daae5a5 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
bogdanm 92:4fc01daae5a5 83 * in @ref Library_configuration_section
bogdanm 92:4fc01daae5a5 84 */
bogdanm 92:4fc01daae5a5 85 typedef enum
bogdanm 92:4fc01daae5a5 86 {
bogdanm 92:4fc01daae5a5 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
bogdanm 92:4fc01daae5a5 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 92:4fc01daae5a5 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 92:4fc01daae5a5 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 92:4fc01daae5a5 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 92:4fc01daae5a5 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 92:4fc01daae5a5 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 92:4fc01daae5a5 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 92:4fc01daae5a5 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 92:4fc01daae5a5 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
bogdanm 92:4fc01daae5a5 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 92:4fc01daae5a5 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 92:4fc01daae5a5 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
bogdanm 92:4fc01daae5a5 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
bogdanm 92:4fc01daae5a5 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 92:4fc01daae5a5 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 92:4fc01daae5a5 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 92:4fc01daae5a5 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 92:4fc01daae5a5 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
bogdanm 92:4fc01daae5a5 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 92:4fc01daae5a5 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 92:4fc01daae5a5 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
bogdanm 92:4fc01daae5a5 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
bogdanm 92:4fc01daae5a5 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
bogdanm 92:4fc01daae5a5 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
bogdanm 92:4fc01daae5a5 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
bogdanm 92:4fc01daae5a5 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
bogdanm 92:4fc01daae5a5 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
bogdanm 92:4fc01daae5a5 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
bogdanm 92:4fc01daae5a5 116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
bogdanm 92:4fc01daae5a5 117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
bogdanm 92:4fc01daae5a5 118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 92:4fc01daae5a5 119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 92:4fc01daae5a5 120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 92:4fc01daae5a5 121 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
bogdanm 92:4fc01daae5a5 122 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
bogdanm 92:4fc01daae5a5 123 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
bogdanm 92:4fc01daae5a5 124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 92:4fc01daae5a5 125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 92:4fc01daae5a5 126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 92:4fc01daae5a5 127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 92:4fc01daae5a5 128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 92:4fc01daae5a5 129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 92:4fc01daae5a5 130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 92:4fc01daae5a5 131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 92:4fc01daae5a5 132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 92:4fc01daae5a5 133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 92:4fc01daae5a5 134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 92:4fc01daae5a5 135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 92:4fc01daae5a5 136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 92:4fc01daae5a5 137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 92:4fc01daae5a5 138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
bogdanm 92:4fc01daae5a5 139 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
bogdanm 92:4fc01daae5a5 140 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
bogdanm 92:4fc01daae5a5 141 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
bogdanm 92:4fc01daae5a5 142 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
bogdanm 92:4fc01daae5a5 143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
bogdanm 92:4fc01daae5a5 144 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
bogdanm 92:4fc01daae5a5 145 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
bogdanm 92:4fc01daae5a5 146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
bogdanm 92:4fc01daae5a5 147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 92:4fc01daae5a5 148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 92:4fc01daae5a5 149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
bogdanm 92:4fc01daae5a5 150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 92:4fc01daae5a5 151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
bogdanm 92:4fc01daae5a5 152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
bogdanm 92:4fc01daae5a5 153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
bogdanm 92:4fc01daae5a5 154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
bogdanm 92:4fc01daae5a5 155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
bogdanm 92:4fc01daae5a5 156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
bogdanm 92:4fc01daae5a5 157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
bogdanm 92:4fc01daae5a5 158 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
bogdanm 92:4fc01daae5a5 159 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
bogdanm 92:4fc01daae5a5 160 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
bogdanm 92:4fc01daae5a5 161 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
bogdanm 92:4fc01daae5a5 162 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
bogdanm 92:4fc01daae5a5 163 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
bogdanm 92:4fc01daae5a5 164 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
bogdanm 92:4fc01daae5a5 165 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
bogdanm 92:4fc01daae5a5 166 USART6_IRQn = 71, /*!< USART6 global interrupt */
bogdanm 92:4fc01daae5a5 167 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
bogdanm 92:4fc01daae5a5 168 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
bogdanm 92:4fc01daae5a5 169 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
bogdanm 92:4fc01daae5a5 170 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
bogdanm 92:4fc01daae5a5 171 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
bogdanm 92:4fc01daae5a5 172 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
bogdanm 92:4fc01daae5a5 173 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
bogdanm 92:4fc01daae5a5 174 FPU_IRQn = 81 /*!< FPU global interrupt */
bogdanm 92:4fc01daae5a5 175 } IRQn_Type;
bogdanm 92:4fc01daae5a5 176
bogdanm 92:4fc01daae5a5 177 /**
bogdanm 92:4fc01daae5a5 178 * @}
bogdanm 92:4fc01daae5a5 179 */
bogdanm 92:4fc01daae5a5 180
bogdanm 92:4fc01daae5a5 181 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 92:4fc01daae5a5 182 #include "system_stm32f4xx.h"
bogdanm 92:4fc01daae5a5 183 #include <stdint.h>
bogdanm 92:4fc01daae5a5 184
bogdanm 92:4fc01daae5a5 185 /** @addtogroup Peripheral_registers_structures
bogdanm 92:4fc01daae5a5 186 * @{
bogdanm 92:4fc01daae5a5 187 */
bogdanm 92:4fc01daae5a5 188
bogdanm 92:4fc01daae5a5 189 /**
bogdanm 92:4fc01daae5a5 190 * @brief Analog to Digital Converter
bogdanm 92:4fc01daae5a5 191 */
bogdanm 92:4fc01daae5a5 192
bogdanm 92:4fc01daae5a5 193 typedef struct
bogdanm 92:4fc01daae5a5 194 {
bogdanm 92:4fc01daae5a5 195 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 196 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 197 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 198 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 199 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 200 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 201 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 202 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 203 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 204 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 205 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 206 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 207 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 208 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 209 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
bogdanm 92:4fc01daae5a5 210 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
bogdanm 92:4fc01daae5a5 211 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 212 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 213 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 214 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
bogdanm 92:4fc01daae5a5 215 } ADC_TypeDef;
bogdanm 92:4fc01daae5a5 216
bogdanm 92:4fc01daae5a5 217 typedef struct
bogdanm 92:4fc01daae5a5 218 {
bogdanm 92:4fc01daae5a5 219 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
bogdanm 92:4fc01daae5a5 220 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
bogdanm 92:4fc01daae5a5 221 __IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm 92:4fc01daae5a5 222 AND triple modes, Address offset: ADC1 base address + 0x308 */
bogdanm 92:4fc01daae5a5 223 } ADC_Common_TypeDef;
bogdanm 92:4fc01daae5a5 224
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226 /**
bogdanm 92:4fc01daae5a5 227 * @brief Controller Area Network TxMailBox
bogdanm 92:4fc01daae5a5 228 */
bogdanm 92:4fc01daae5a5 229
bogdanm 92:4fc01daae5a5 230 typedef struct
bogdanm 92:4fc01daae5a5 231 {
bogdanm 92:4fc01daae5a5 232 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
bogdanm 92:4fc01daae5a5 233 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
bogdanm 92:4fc01daae5a5 234 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
bogdanm 92:4fc01daae5a5 235 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
bogdanm 92:4fc01daae5a5 236 } CAN_TxMailBox_TypeDef;
bogdanm 92:4fc01daae5a5 237
bogdanm 92:4fc01daae5a5 238 /**
bogdanm 92:4fc01daae5a5 239 * @brief Controller Area Network FIFOMailBox
bogdanm 92:4fc01daae5a5 240 */
bogdanm 92:4fc01daae5a5 241
bogdanm 92:4fc01daae5a5 242 typedef struct
bogdanm 92:4fc01daae5a5 243 {
bogdanm 92:4fc01daae5a5 244 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
bogdanm 92:4fc01daae5a5 245 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
bogdanm 92:4fc01daae5a5 246 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
bogdanm 92:4fc01daae5a5 247 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
bogdanm 92:4fc01daae5a5 248 } CAN_FIFOMailBox_TypeDef;
bogdanm 92:4fc01daae5a5 249
bogdanm 92:4fc01daae5a5 250 /**
bogdanm 92:4fc01daae5a5 251 * @brief Controller Area Network FilterRegister
bogdanm 92:4fc01daae5a5 252 */
bogdanm 92:4fc01daae5a5 253
bogdanm 92:4fc01daae5a5 254 typedef struct
bogdanm 92:4fc01daae5a5 255 {
bogdanm 92:4fc01daae5a5 256 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
bogdanm 92:4fc01daae5a5 257 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
bogdanm 92:4fc01daae5a5 258 } CAN_FilterRegister_TypeDef;
bogdanm 92:4fc01daae5a5 259
bogdanm 92:4fc01daae5a5 260 /**
bogdanm 92:4fc01daae5a5 261 * @brief Controller Area Network
bogdanm 92:4fc01daae5a5 262 */
bogdanm 92:4fc01daae5a5 263
bogdanm 92:4fc01daae5a5 264 typedef struct
bogdanm 92:4fc01daae5a5 265 {
bogdanm 92:4fc01daae5a5 266 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 267 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 268 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 269 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 270 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 271 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 272 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 273 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 274 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
bogdanm 92:4fc01daae5a5 275 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
bogdanm 92:4fc01daae5a5 276 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
bogdanm 92:4fc01daae5a5 277 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
bogdanm 92:4fc01daae5a5 278 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
bogdanm 92:4fc01daae5a5 279 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
bogdanm 92:4fc01daae5a5 280 uint32_t RESERVED2; /*!< Reserved, 0x208 */
bogdanm 92:4fc01daae5a5 281 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
bogdanm 92:4fc01daae5a5 282 uint32_t RESERVED3; /*!< Reserved, 0x210 */
bogdanm 92:4fc01daae5a5 283 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
bogdanm 92:4fc01daae5a5 284 uint32_t RESERVED4; /*!< Reserved, 0x218 */
bogdanm 92:4fc01daae5a5 285 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
bogdanm 92:4fc01daae5a5 286 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
bogdanm 92:4fc01daae5a5 287 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
bogdanm 92:4fc01daae5a5 288 } CAN_TypeDef;
bogdanm 92:4fc01daae5a5 289
bogdanm 92:4fc01daae5a5 290 /**
bogdanm 92:4fc01daae5a5 291 * @brief CRC calculation unit
bogdanm 92:4fc01daae5a5 292 */
bogdanm 92:4fc01daae5a5 293
bogdanm 92:4fc01daae5a5 294 typedef struct
bogdanm 92:4fc01daae5a5 295 {
bogdanm 92:4fc01daae5a5 296 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 297 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 298 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 92:4fc01daae5a5 299 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 92:4fc01daae5a5 300 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 301 } CRC_TypeDef;
bogdanm 92:4fc01daae5a5 302
bogdanm 92:4fc01daae5a5 303 /**
bogdanm 92:4fc01daae5a5 304 * @brief Digital to Analog Converter
bogdanm 92:4fc01daae5a5 305 */
bogdanm 92:4fc01daae5a5 306
bogdanm 92:4fc01daae5a5 307 typedef struct
bogdanm 92:4fc01daae5a5 308 {
bogdanm 92:4fc01daae5a5 309 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 310 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 311 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 312 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 313 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 314 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 315 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 316 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 317 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 318 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 319 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 320 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 321 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 322 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 323 } DAC_TypeDef;
bogdanm 92:4fc01daae5a5 324
bogdanm 92:4fc01daae5a5 325 /**
bogdanm 92:4fc01daae5a5 326 * @brief Debug MCU
bogdanm 92:4fc01daae5a5 327 */
bogdanm 92:4fc01daae5a5 328
bogdanm 92:4fc01daae5a5 329 typedef struct
bogdanm 92:4fc01daae5a5 330 {
bogdanm 92:4fc01daae5a5 331 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 332 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 333 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 334 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 335 }DBGMCU_TypeDef;
bogdanm 92:4fc01daae5a5 336
bogdanm 92:4fc01daae5a5 337
bogdanm 92:4fc01daae5a5 338 /**
bogdanm 92:4fc01daae5a5 339 * @brief DMA Controller
bogdanm 92:4fc01daae5a5 340 */
bogdanm 92:4fc01daae5a5 341
bogdanm 92:4fc01daae5a5 342 typedef struct
bogdanm 92:4fc01daae5a5 343 {
bogdanm 92:4fc01daae5a5 344 __IO uint32_t CR; /*!< DMA stream x configuration register */
bogdanm 92:4fc01daae5a5 345 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
bogdanm 92:4fc01daae5a5 346 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
bogdanm 92:4fc01daae5a5 347 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
bogdanm 92:4fc01daae5a5 348 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
bogdanm 92:4fc01daae5a5 349 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
bogdanm 92:4fc01daae5a5 350 } DMA_Stream_TypeDef;
bogdanm 92:4fc01daae5a5 351
bogdanm 92:4fc01daae5a5 352 typedef struct
bogdanm 92:4fc01daae5a5 353 {
bogdanm 92:4fc01daae5a5 354 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 355 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 356 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 357 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 358 } DMA_TypeDef;
bogdanm 92:4fc01daae5a5 359
bogdanm 92:4fc01daae5a5 360
bogdanm 92:4fc01daae5a5 361 /**
bogdanm 92:4fc01daae5a5 362 * @brief External Interrupt/Event Controller
bogdanm 92:4fc01daae5a5 363 */
bogdanm 92:4fc01daae5a5 364
bogdanm 92:4fc01daae5a5 365 typedef struct
bogdanm 92:4fc01daae5a5 366 {
bogdanm 92:4fc01daae5a5 367 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 368 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 369 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 370 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 371 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 372 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 373 } EXTI_TypeDef;
bogdanm 92:4fc01daae5a5 374
bogdanm 92:4fc01daae5a5 375 /**
bogdanm 92:4fc01daae5a5 376 * @brief FLASH Registers
bogdanm 92:4fc01daae5a5 377 */
bogdanm 92:4fc01daae5a5 378
bogdanm 92:4fc01daae5a5 379 typedef struct
bogdanm 92:4fc01daae5a5 380 {
bogdanm 92:4fc01daae5a5 381 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 382 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 383 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 384 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 385 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 386 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 387 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 388 } FLASH_TypeDef;
bogdanm 92:4fc01daae5a5 389
bogdanm 92:4fc01daae5a5 390
bogdanm 92:4fc01daae5a5 391 /**
bogdanm 92:4fc01daae5a5 392 * @brief Flexible Static Memory Controller
bogdanm 92:4fc01daae5a5 393 */
bogdanm 92:4fc01daae5a5 394
bogdanm 92:4fc01daae5a5 395 typedef struct
bogdanm 92:4fc01daae5a5 396 {
bogdanm 92:4fc01daae5a5 397 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
bogdanm 92:4fc01daae5a5 398 } FSMC_Bank1_TypeDef;
bogdanm 92:4fc01daae5a5 399
bogdanm 92:4fc01daae5a5 400 /**
bogdanm 92:4fc01daae5a5 401 * @brief Flexible Static Memory Controller Bank1E
bogdanm 92:4fc01daae5a5 402 */
bogdanm 92:4fc01daae5a5 403
bogdanm 92:4fc01daae5a5 404 typedef struct
bogdanm 92:4fc01daae5a5 405 {
bogdanm 92:4fc01daae5a5 406 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
bogdanm 92:4fc01daae5a5 407 } FSMC_Bank1E_TypeDef;
bogdanm 92:4fc01daae5a5 408
bogdanm 92:4fc01daae5a5 409 /**
bogdanm 92:4fc01daae5a5 410 * @brief Flexible Static Memory Controller Bank2
bogdanm 92:4fc01daae5a5 411 */
bogdanm 92:4fc01daae5a5 412
bogdanm 92:4fc01daae5a5 413 typedef struct
bogdanm 92:4fc01daae5a5 414 {
bogdanm 92:4fc01daae5a5 415 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
bogdanm 92:4fc01daae5a5 416 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
bogdanm 92:4fc01daae5a5 417 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
bogdanm 92:4fc01daae5a5 418 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
bogdanm 92:4fc01daae5a5 419 uint32_t RESERVED0; /*!< Reserved, 0x70 */
bogdanm 92:4fc01daae5a5 420 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
bogdanm 92:4fc01daae5a5 421 uint32_t RESERVED1; /*!< Reserved, 0x78 */
bogdanm 92:4fc01daae5a5 422 uint32_t RESERVED2; /*!< Reserved, 0x7C */
bogdanm 92:4fc01daae5a5 423 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
bogdanm 92:4fc01daae5a5 424 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
bogdanm 92:4fc01daae5a5 425 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
bogdanm 92:4fc01daae5a5 426 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
bogdanm 92:4fc01daae5a5 427 uint32_t RESERVED3; /*!< Reserved, 0x90 */
bogdanm 92:4fc01daae5a5 428 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
bogdanm 92:4fc01daae5a5 429 } FSMC_Bank2_3_TypeDef;
bogdanm 92:4fc01daae5a5 430
bogdanm 92:4fc01daae5a5 431 /**
bogdanm 92:4fc01daae5a5 432 * @brief Flexible Static Memory Controller Bank4
bogdanm 92:4fc01daae5a5 433 */
bogdanm 92:4fc01daae5a5 434
bogdanm 92:4fc01daae5a5 435 typedef struct
bogdanm 92:4fc01daae5a5 436 {
bogdanm 92:4fc01daae5a5 437 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
bogdanm 92:4fc01daae5a5 438 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
bogdanm 92:4fc01daae5a5 439 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
bogdanm 92:4fc01daae5a5 440 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
bogdanm 92:4fc01daae5a5 441 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
bogdanm 92:4fc01daae5a5 442 } FSMC_Bank4_TypeDef;
bogdanm 92:4fc01daae5a5 443
bogdanm 92:4fc01daae5a5 444
bogdanm 92:4fc01daae5a5 445 /**
bogdanm 92:4fc01daae5a5 446 * @brief General Purpose I/O
bogdanm 92:4fc01daae5a5 447 */
bogdanm 92:4fc01daae5a5 448
bogdanm 92:4fc01daae5a5 449 typedef struct
bogdanm 92:4fc01daae5a5 450 {
bogdanm 92:4fc01daae5a5 451 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 452 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 453 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 454 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 455 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 456 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 457 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 458 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
bogdanm 92:4fc01daae5a5 459 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 460 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
bogdanm 92:4fc01daae5a5 461 } GPIO_TypeDef;
bogdanm 92:4fc01daae5a5 462
bogdanm 92:4fc01daae5a5 463 /**
bogdanm 92:4fc01daae5a5 464 * @brief System configuration controller
bogdanm 92:4fc01daae5a5 465 */
bogdanm 92:4fc01daae5a5 466
bogdanm 92:4fc01daae5a5 467 typedef struct
bogdanm 92:4fc01daae5a5 468 {
bogdanm 92:4fc01daae5a5 469 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 470 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 471 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
bogdanm 92:4fc01daae5a5 472 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
bogdanm 92:4fc01daae5a5 473 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 474 } SYSCFG_TypeDef;
bogdanm 92:4fc01daae5a5 475
bogdanm 92:4fc01daae5a5 476 /**
bogdanm 92:4fc01daae5a5 477 * @brief Inter-integrated Circuit Interface
bogdanm 92:4fc01daae5a5 478 */
bogdanm 92:4fc01daae5a5 479
bogdanm 92:4fc01daae5a5 480 typedef struct
bogdanm 92:4fc01daae5a5 481 {
bogdanm 92:4fc01daae5a5 482 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 483 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 484 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 485 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 486 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 487 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 488 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 489 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 490 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 491 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 492 } I2C_TypeDef;
bogdanm 92:4fc01daae5a5 493
bogdanm 92:4fc01daae5a5 494 /**
bogdanm 92:4fc01daae5a5 495 * @brief Independent WATCHDOG
bogdanm 92:4fc01daae5a5 496 */
bogdanm 92:4fc01daae5a5 497
bogdanm 92:4fc01daae5a5 498 typedef struct
bogdanm 92:4fc01daae5a5 499 {
bogdanm 92:4fc01daae5a5 500 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 501 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 502 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 503 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 504 } IWDG_TypeDef;
bogdanm 92:4fc01daae5a5 505
bogdanm 92:4fc01daae5a5 506 /**
bogdanm 92:4fc01daae5a5 507 * @brief Power Control
bogdanm 92:4fc01daae5a5 508 */
bogdanm 92:4fc01daae5a5 509
bogdanm 92:4fc01daae5a5 510 typedef struct
bogdanm 92:4fc01daae5a5 511 {
bogdanm 92:4fc01daae5a5 512 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 513 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 514 } PWR_TypeDef;
bogdanm 92:4fc01daae5a5 515
bogdanm 92:4fc01daae5a5 516 /**
bogdanm 92:4fc01daae5a5 517 * @brief Reset and Clock Control
bogdanm 92:4fc01daae5a5 518 */
bogdanm 92:4fc01daae5a5 519
bogdanm 92:4fc01daae5a5 520 typedef struct
bogdanm 92:4fc01daae5a5 521 {
bogdanm 92:4fc01daae5a5 522 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 523 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 524 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 525 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 526 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 527 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 528 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 529 uint32_t RESERVED0; /*!< Reserved, 0x1C */
bogdanm 92:4fc01daae5a5 530 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 531 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 532 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
bogdanm 92:4fc01daae5a5 533 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 534 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 535 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
bogdanm 92:4fc01daae5a5 536 uint32_t RESERVED2; /*!< Reserved, 0x3C */
bogdanm 92:4fc01daae5a5 537 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 538 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 539 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
bogdanm 92:4fc01daae5a5 540 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
bogdanm 92:4fc01daae5a5 541 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
bogdanm 92:4fc01daae5a5 542 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
bogdanm 92:4fc01daae5a5 543 uint32_t RESERVED4; /*!< Reserved, 0x5C */
bogdanm 92:4fc01daae5a5 544 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
bogdanm 92:4fc01daae5a5 545 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
bogdanm 92:4fc01daae5a5 546 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
bogdanm 92:4fc01daae5a5 547 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
bogdanm 92:4fc01daae5a5 548 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
bogdanm 92:4fc01daae5a5 549 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
bogdanm 92:4fc01daae5a5 550 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
bogdanm 92:4fc01daae5a5 551 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
bogdanm 92:4fc01daae5a5 552
bogdanm 92:4fc01daae5a5 553 } RCC_TypeDef;
bogdanm 92:4fc01daae5a5 554
bogdanm 92:4fc01daae5a5 555 /**
bogdanm 92:4fc01daae5a5 556 * @brief Real-Time Clock
bogdanm 92:4fc01daae5a5 557 */
bogdanm 92:4fc01daae5a5 558
bogdanm 92:4fc01daae5a5 559 typedef struct
bogdanm 92:4fc01daae5a5 560 {
bogdanm 92:4fc01daae5a5 561 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 562 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 563 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 564 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 565 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 566 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 567 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 568 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 569 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 570 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 571 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 572 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 573 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 574 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 575 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 92:4fc01daae5a5 576 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 92:4fc01daae5a5 577 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 578 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 579 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 580 uint32_t RESERVED7; /*!< Reserved, 0x4C */
bogdanm 92:4fc01daae5a5 581 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
bogdanm 92:4fc01daae5a5 582 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 92:4fc01daae5a5 583 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 92:4fc01daae5a5 584 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 92:4fc01daae5a5 585 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 92:4fc01daae5a5 586 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
bogdanm 92:4fc01daae5a5 587 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
bogdanm 92:4fc01daae5a5 588 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
bogdanm 92:4fc01daae5a5 589 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
bogdanm 92:4fc01daae5a5 590 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
bogdanm 92:4fc01daae5a5 591 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
bogdanm 92:4fc01daae5a5 592 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
bogdanm 92:4fc01daae5a5 593 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
bogdanm 92:4fc01daae5a5 594 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
bogdanm 92:4fc01daae5a5 595 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
bogdanm 92:4fc01daae5a5 596 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
bogdanm 92:4fc01daae5a5 597 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
bogdanm 92:4fc01daae5a5 598 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
bogdanm 92:4fc01daae5a5 599 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
bogdanm 92:4fc01daae5a5 600 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
bogdanm 92:4fc01daae5a5 601 } RTC_TypeDef;
bogdanm 92:4fc01daae5a5 602
bogdanm 92:4fc01daae5a5 603
bogdanm 92:4fc01daae5a5 604 /**
bogdanm 92:4fc01daae5a5 605 * @brief SD host Interface
bogdanm 92:4fc01daae5a5 606 */
bogdanm 92:4fc01daae5a5 607
bogdanm 92:4fc01daae5a5 608 typedef struct
bogdanm 92:4fc01daae5a5 609 {
bogdanm 92:4fc01daae5a5 610 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 611 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 612 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 613 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 614 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 615 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 616 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 617 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 618 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 619 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 620 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 621 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 622 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 623 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 624 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
bogdanm 92:4fc01daae5a5 625 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
bogdanm 92:4fc01daae5a5 626 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
bogdanm 92:4fc01daae5a5 627 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 628 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
bogdanm 92:4fc01daae5a5 629 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
bogdanm 92:4fc01daae5a5 630 } SDIO_TypeDef;
bogdanm 92:4fc01daae5a5 631
bogdanm 92:4fc01daae5a5 632 /**
bogdanm 92:4fc01daae5a5 633 * @brief Serial Peripheral Interface
bogdanm 92:4fc01daae5a5 634 */
bogdanm 92:4fc01daae5a5 635
bogdanm 92:4fc01daae5a5 636 typedef struct
bogdanm 92:4fc01daae5a5 637 {
bogdanm 92:4fc01daae5a5 638 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 639 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 640 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 641 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 642 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 643 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 644 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 645 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 646 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 647 } SPI_TypeDef;
bogdanm 92:4fc01daae5a5 648
bogdanm 92:4fc01daae5a5 649 /**
bogdanm 92:4fc01daae5a5 650 * @brief TIM
bogdanm 92:4fc01daae5a5 651 */
bogdanm 92:4fc01daae5a5 652
bogdanm 92:4fc01daae5a5 653 typedef struct
bogdanm 92:4fc01daae5a5 654 {
bogdanm 92:4fc01daae5a5 655 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 656 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 657 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 658 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 659 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 660 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 661 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 662 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 663 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 664 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 665 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 666 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 667 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 668 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 669 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 92:4fc01daae5a5 670 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 92:4fc01daae5a5 671 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 672 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 673 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 674 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
bogdanm 92:4fc01daae5a5 675 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 92:4fc01daae5a5 676 } TIM_TypeDef;
bogdanm 92:4fc01daae5a5 677
bogdanm 92:4fc01daae5a5 678 /**
bogdanm 92:4fc01daae5a5 679 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 92:4fc01daae5a5 680 */
bogdanm 92:4fc01daae5a5 681
bogdanm 92:4fc01daae5a5 682 typedef struct
bogdanm 92:4fc01daae5a5 683 {
bogdanm 92:4fc01daae5a5 684 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 685 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 686 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 687 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 688 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 689 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 690 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 691 } USART_TypeDef;
bogdanm 92:4fc01daae5a5 692
bogdanm 92:4fc01daae5a5 693 /**
bogdanm 92:4fc01daae5a5 694 * @brief Window WATCHDOG
bogdanm 92:4fc01daae5a5 695 */
bogdanm 92:4fc01daae5a5 696
bogdanm 92:4fc01daae5a5 697 typedef struct
bogdanm 92:4fc01daae5a5 698 {
bogdanm 92:4fc01daae5a5 699 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 700 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 701 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 702 } WWDG_TypeDef;
bogdanm 92:4fc01daae5a5 703
bogdanm 92:4fc01daae5a5 704
bogdanm 92:4fc01daae5a5 705 /**
bogdanm 92:4fc01daae5a5 706 * @brief RNG
bogdanm 92:4fc01daae5a5 707 */
bogdanm 92:4fc01daae5a5 708
bogdanm 92:4fc01daae5a5 709 typedef struct
bogdanm 92:4fc01daae5a5 710 {
bogdanm 92:4fc01daae5a5 711 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 712 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 713 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 714 } RNG_TypeDef;
bogdanm 92:4fc01daae5a5 715
bogdanm 92:4fc01daae5a5 716
bogdanm 92:4fc01daae5a5 717
bogdanm 92:4fc01daae5a5 718 /**
bogdanm 92:4fc01daae5a5 719 * @brief __USB_OTG_Core_register
bogdanm 92:4fc01daae5a5 720 */
bogdanm 92:4fc01daae5a5 721 typedef struct
bogdanm 92:4fc01daae5a5 722 {
bogdanm 92:4fc01daae5a5 723 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
bogdanm 92:4fc01daae5a5 724 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
bogdanm 92:4fc01daae5a5 725 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
bogdanm 92:4fc01daae5a5 726 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
bogdanm 92:4fc01daae5a5 727 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
bogdanm 92:4fc01daae5a5 728 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
bogdanm 92:4fc01daae5a5 729 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
bogdanm 92:4fc01daae5a5 730 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
bogdanm 92:4fc01daae5a5 731 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
bogdanm 92:4fc01daae5a5 732 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
bogdanm 92:4fc01daae5a5 733 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
bogdanm 92:4fc01daae5a5 734 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
bogdanm 92:4fc01daae5a5 735 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
bogdanm 92:4fc01daae5a5 736 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
bogdanm 92:4fc01daae5a5 737 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
bogdanm 92:4fc01daae5a5 738 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
bogdanm 92:4fc01daae5a5 739 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
bogdanm 92:4fc01daae5a5 740 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
bogdanm 92:4fc01daae5a5 741 }
bogdanm 92:4fc01daae5a5 742 USB_OTG_GlobalTypeDef;
bogdanm 92:4fc01daae5a5 743
bogdanm 92:4fc01daae5a5 744
bogdanm 92:4fc01daae5a5 745
bogdanm 92:4fc01daae5a5 746 /**
bogdanm 92:4fc01daae5a5 747 * @brief __device_Registers
bogdanm 92:4fc01daae5a5 748 */
bogdanm 92:4fc01daae5a5 749 typedef struct
bogdanm 92:4fc01daae5a5 750 {
bogdanm 92:4fc01daae5a5 751 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
bogdanm 92:4fc01daae5a5 752 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
bogdanm 92:4fc01daae5a5 753 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
bogdanm 92:4fc01daae5a5 754 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
bogdanm 92:4fc01daae5a5 755 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
bogdanm 92:4fc01daae5a5 756 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
bogdanm 92:4fc01daae5a5 757 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
bogdanm 92:4fc01daae5a5 758 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
bogdanm 92:4fc01daae5a5 759 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
bogdanm 92:4fc01daae5a5 760 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
bogdanm 92:4fc01daae5a5 761 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
bogdanm 92:4fc01daae5a5 762 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
bogdanm 92:4fc01daae5a5 763 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
bogdanm 92:4fc01daae5a5 764 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
bogdanm 92:4fc01daae5a5 765 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
bogdanm 92:4fc01daae5a5 766 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
bogdanm 92:4fc01daae5a5 767 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
bogdanm 92:4fc01daae5a5 768 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
bogdanm 92:4fc01daae5a5 769 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
bogdanm 92:4fc01daae5a5 770 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
bogdanm 92:4fc01daae5a5 771 }
bogdanm 92:4fc01daae5a5 772 USB_OTG_DeviceTypeDef;
bogdanm 92:4fc01daae5a5 773
bogdanm 92:4fc01daae5a5 774
bogdanm 92:4fc01daae5a5 775 /**
bogdanm 92:4fc01daae5a5 776 * @brief __IN_Endpoint-Specific_Register
bogdanm 92:4fc01daae5a5 777 */
bogdanm 92:4fc01daae5a5 778 typedef struct
bogdanm 92:4fc01daae5a5 779 {
bogdanm 92:4fc01daae5a5 780 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
bogdanm 92:4fc01daae5a5 781 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
bogdanm 92:4fc01daae5a5 782 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
bogdanm 92:4fc01daae5a5 783 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
bogdanm 92:4fc01daae5a5 784 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
bogdanm 92:4fc01daae5a5 785 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
bogdanm 92:4fc01daae5a5 786 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
bogdanm 92:4fc01daae5a5 787 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
bogdanm 92:4fc01daae5a5 788 }
bogdanm 92:4fc01daae5a5 789 USB_OTG_INEndpointTypeDef;
bogdanm 92:4fc01daae5a5 790
bogdanm 92:4fc01daae5a5 791
bogdanm 92:4fc01daae5a5 792 /**
bogdanm 92:4fc01daae5a5 793 * @brief __OUT_Endpoint-Specific_Registers
bogdanm 92:4fc01daae5a5 794 */
bogdanm 92:4fc01daae5a5 795 typedef struct
bogdanm 92:4fc01daae5a5 796 {
bogdanm 92:4fc01daae5a5 797 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
bogdanm 92:4fc01daae5a5 798 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
bogdanm 92:4fc01daae5a5 799 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
bogdanm 92:4fc01daae5a5 800 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
bogdanm 92:4fc01daae5a5 801 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
bogdanm 92:4fc01daae5a5 802 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
bogdanm 92:4fc01daae5a5 803 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
bogdanm 92:4fc01daae5a5 804 }
bogdanm 92:4fc01daae5a5 805 USB_OTG_OUTEndpointTypeDef;
bogdanm 92:4fc01daae5a5 806
bogdanm 92:4fc01daae5a5 807
bogdanm 92:4fc01daae5a5 808 /**
bogdanm 92:4fc01daae5a5 809 * @brief __Host_Mode_Register_Structures
bogdanm 92:4fc01daae5a5 810 */
bogdanm 92:4fc01daae5a5 811 typedef struct
bogdanm 92:4fc01daae5a5 812 {
bogdanm 92:4fc01daae5a5 813 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
bogdanm 92:4fc01daae5a5 814 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
bogdanm 92:4fc01daae5a5 815 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
bogdanm 92:4fc01daae5a5 816 uint32_t Reserved40C; /* Reserved 40Ch*/
bogdanm 92:4fc01daae5a5 817 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
bogdanm 92:4fc01daae5a5 818 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
bogdanm 92:4fc01daae5a5 819 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
bogdanm 92:4fc01daae5a5 820 }
bogdanm 92:4fc01daae5a5 821 USB_OTG_HostTypeDef;
bogdanm 92:4fc01daae5a5 822
bogdanm 92:4fc01daae5a5 823
bogdanm 92:4fc01daae5a5 824 /**
bogdanm 92:4fc01daae5a5 825 * @brief __Host_Channel_Specific_Registers
bogdanm 92:4fc01daae5a5 826 */
bogdanm 92:4fc01daae5a5 827 typedef struct
bogdanm 92:4fc01daae5a5 828 {
bogdanm 92:4fc01daae5a5 829 __IO uint32_t HCCHAR;
bogdanm 92:4fc01daae5a5 830 __IO uint32_t HCSPLT;
bogdanm 92:4fc01daae5a5 831 __IO uint32_t HCINT;
bogdanm 92:4fc01daae5a5 832 __IO uint32_t HCINTMSK;
bogdanm 92:4fc01daae5a5 833 __IO uint32_t HCTSIZ;
bogdanm 92:4fc01daae5a5 834 __IO uint32_t HCDMA;
bogdanm 92:4fc01daae5a5 835 uint32_t Reserved[2];
bogdanm 92:4fc01daae5a5 836 }
bogdanm 92:4fc01daae5a5 837 USB_OTG_HostChannelTypeDef;
bogdanm 92:4fc01daae5a5 838
bogdanm 92:4fc01daae5a5 839
bogdanm 92:4fc01daae5a5 840 /**
bogdanm 92:4fc01daae5a5 841 * @brief Peripheral_memory_map
bogdanm 92:4fc01daae5a5 842 */
bogdanm 92:4fc01daae5a5 843 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
bogdanm 92:4fc01daae5a5 844 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
bogdanm 92:4fc01daae5a5 845 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
bogdanm 92:4fc01daae5a5 846 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
bogdanm 92:4fc01daae5a5 847 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
bogdanm 92:4fc01daae5a5 848 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 92:4fc01daae5a5 849 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
bogdanm 92:4fc01daae5a5 850 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
bogdanm 92:4fc01daae5a5 851 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
bogdanm 92:4fc01daae5a5 852 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
bogdanm 92:4fc01daae5a5 853 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
bogdanm 92:4fc01daae5a5 854 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
bogdanm 92:4fc01daae5a5 855 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
bogdanm 92:4fc01daae5a5 856 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
bogdanm 92:4fc01daae5a5 857 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
bogdanm 92:4fc01daae5a5 858 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
bogdanm 92:4fc01daae5a5 859
bogdanm 92:4fc01daae5a5 860 /* Legacy defines */
bogdanm 92:4fc01daae5a5 861 #define SRAM_BASE SRAM1_BASE
bogdanm 92:4fc01daae5a5 862 #define SRAM_BB_BASE SRAM1_BB_BASE
bogdanm 92:4fc01daae5a5 863
bogdanm 92:4fc01daae5a5 864
bogdanm 92:4fc01daae5a5 865 /*!< Peripheral memory map */
bogdanm 92:4fc01daae5a5 866 #define APB1PERIPH_BASE PERIPH_BASE
bogdanm 92:4fc01daae5a5 867 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm 92:4fc01daae5a5 868 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 92:4fc01daae5a5 869 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm 92:4fc01daae5a5 870
bogdanm 92:4fc01daae5a5 871 /*!< APB1 peripherals */
bogdanm 92:4fc01daae5a5 872 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
bogdanm 92:4fc01daae5a5 873 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
bogdanm 92:4fc01daae5a5 874 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
bogdanm 92:4fc01daae5a5 875 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
bogdanm 92:4fc01daae5a5 876 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
bogdanm 92:4fc01daae5a5 877 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
bogdanm 92:4fc01daae5a5 878 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
bogdanm 92:4fc01daae5a5 879 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
bogdanm 92:4fc01daae5a5 880 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
bogdanm 92:4fc01daae5a5 881 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
bogdanm 92:4fc01daae5a5 882 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
bogdanm 92:4fc01daae5a5 883 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
bogdanm 92:4fc01daae5a5 884 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
bogdanm 92:4fc01daae5a5 885 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
bogdanm 92:4fc01daae5a5 886 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
bogdanm 92:4fc01daae5a5 887 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
bogdanm 92:4fc01daae5a5 888 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
bogdanm 92:4fc01daae5a5 889 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
bogdanm 92:4fc01daae5a5 890 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
bogdanm 92:4fc01daae5a5 891 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
bogdanm 92:4fc01daae5a5 892 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
bogdanm 92:4fc01daae5a5 893 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
bogdanm 92:4fc01daae5a5 894 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
bogdanm 92:4fc01daae5a5 895 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
bogdanm 92:4fc01daae5a5 896 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
bogdanm 92:4fc01daae5a5 897 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
bogdanm 92:4fc01daae5a5 898 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
bogdanm 92:4fc01daae5a5 899
bogdanm 92:4fc01daae5a5 900 /*!< APB2 peripherals */
bogdanm 92:4fc01daae5a5 901 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
bogdanm 92:4fc01daae5a5 902 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
bogdanm 92:4fc01daae5a5 903 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
bogdanm 92:4fc01daae5a5 904 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
bogdanm 92:4fc01daae5a5 905 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
bogdanm 92:4fc01daae5a5 906 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
bogdanm 92:4fc01daae5a5 907 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
bogdanm 92:4fc01daae5a5 908 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
bogdanm 92:4fc01daae5a5 909 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
bogdanm 92:4fc01daae5a5 910 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
bogdanm 92:4fc01daae5a5 911 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
bogdanm 92:4fc01daae5a5 912 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
bogdanm 92:4fc01daae5a5 913 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
bogdanm 92:4fc01daae5a5 914 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
bogdanm 92:4fc01daae5a5 915 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
bogdanm 92:4fc01daae5a5 916
bogdanm 92:4fc01daae5a5 917 /*!< AHB1 peripherals */
bogdanm 92:4fc01daae5a5 918 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
bogdanm 92:4fc01daae5a5 919 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
bogdanm 92:4fc01daae5a5 920 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
bogdanm 92:4fc01daae5a5 921 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
bogdanm 92:4fc01daae5a5 922 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
bogdanm 92:4fc01daae5a5 923 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
bogdanm 92:4fc01daae5a5 924 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
bogdanm 92:4fc01daae5a5 925 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
bogdanm 92:4fc01daae5a5 926 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
bogdanm 92:4fc01daae5a5 927 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
bogdanm 92:4fc01daae5a5 928 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
bogdanm 92:4fc01daae5a5 929 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
bogdanm 92:4fc01daae5a5 930 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
bogdanm 92:4fc01daae5a5 931 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
bogdanm 92:4fc01daae5a5 932 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
bogdanm 92:4fc01daae5a5 933 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
bogdanm 92:4fc01daae5a5 934 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
bogdanm 92:4fc01daae5a5 935 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
bogdanm 92:4fc01daae5a5 936 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
bogdanm 92:4fc01daae5a5 937 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
bogdanm 92:4fc01daae5a5 938 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
bogdanm 92:4fc01daae5a5 939 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
bogdanm 92:4fc01daae5a5 940 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
bogdanm 92:4fc01daae5a5 941 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
bogdanm 92:4fc01daae5a5 942 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
bogdanm 92:4fc01daae5a5 943 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
bogdanm 92:4fc01daae5a5 944 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
bogdanm 92:4fc01daae5a5 945 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
bogdanm 92:4fc01daae5a5 946 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
bogdanm 92:4fc01daae5a5 947 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
bogdanm 92:4fc01daae5a5 948
bogdanm 92:4fc01daae5a5 949 /*!< AHB2 peripherals */
bogdanm 92:4fc01daae5a5 950 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
bogdanm 92:4fc01daae5a5 951
bogdanm 92:4fc01daae5a5 952 /*!< FSMC Bankx registers base address */
bogdanm 92:4fc01daae5a5 953 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
bogdanm 92:4fc01daae5a5 954 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
bogdanm 92:4fc01daae5a5 955 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
bogdanm 92:4fc01daae5a5 956 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
bogdanm 92:4fc01daae5a5 957
bogdanm 92:4fc01daae5a5 958 /* Debug MCU registers base address */
bogdanm 92:4fc01daae5a5 959 #define DBGMCU_BASE ((uint32_t )0xE0042000)
bogdanm 92:4fc01daae5a5 960
bogdanm 92:4fc01daae5a5 961 /*!< USB registers base address */
bogdanm 92:4fc01daae5a5 962 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
bogdanm 92:4fc01daae5a5 963 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
bogdanm 92:4fc01daae5a5 964
bogdanm 92:4fc01daae5a5 965 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
bogdanm 92:4fc01daae5a5 966 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
bogdanm 92:4fc01daae5a5 967 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
bogdanm 92:4fc01daae5a5 968 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
bogdanm 92:4fc01daae5a5 969 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
bogdanm 92:4fc01daae5a5 970 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
bogdanm 92:4fc01daae5a5 971 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
bogdanm 92:4fc01daae5a5 972 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
bogdanm 92:4fc01daae5a5 973 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
bogdanm 92:4fc01daae5a5 974 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
bogdanm 92:4fc01daae5a5 975 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
bogdanm 92:4fc01daae5a5 976 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
bogdanm 92:4fc01daae5a5 977
bogdanm 92:4fc01daae5a5 978 /**
bogdanm 92:4fc01daae5a5 979 * @}
bogdanm 92:4fc01daae5a5 980 */
bogdanm 92:4fc01daae5a5 981
bogdanm 92:4fc01daae5a5 982 /** @addtogroup Peripheral_declaration
bogdanm 92:4fc01daae5a5 983 * @{
bogdanm 92:4fc01daae5a5 984 */
bogdanm 92:4fc01daae5a5 985 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 92:4fc01daae5a5 986 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 92:4fc01daae5a5 987 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm 92:4fc01daae5a5 988 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
bogdanm 92:4fc01daae5a5 989 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 92:4fc01daae5a5 990 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 92:4fc01daae5a5 991 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
bogdanm 92:4fc01daae5a5 992 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
bogdanm 92:4fc01daae5a5 993 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm 92:4fc01daae5a5 994 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 92:4fc01daae5a5 995 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 92:4fc01daae5a5 996 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 92:4fc01daae5a5 997 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
bogdanm 92:4fc01daae5a5 998 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 92:4fc01daae5a5 999 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm 92:4fc01daae5a5 1000 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
bogdanm 92:4fc01daae5a5 1001 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 92:4fc01daae5a5 1002 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 92:4fc01daae5a5 1003 #define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm 92:4fc01daae5a5 1004 #define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm 92:4fc01daae5a5 1005 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 92:4fc01daae5a5 1006 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 92:4fc01daae5a5 1007 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm 92:4fc01daae5a5 1008 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm 92:4fc01daae5a5 1009 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
bogdanm 92:4fc01daae5a5 1010 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 92:4fc01daae5a5 1011 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 92:4fc01daae5a5 1012 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 92:4fc01daae5a5 1013 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm 92:4fc01daae5a5 1014 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 92:4fc01daae5a5 1015 #define USART6 ((USART_TypeDef *) USART6_BASE)
bogdanm 92:4fc01daae5a5 1016 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm 92:4fc01daae5a5 1017 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 92:4fc01daae5a5 1018 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm 92:4fc01daae5a5 1019 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm 92:4fc01daae5a5 1020 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
bogdanm 92:4fc01daae5a5 1021 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 92:4fc01daae5a5 1022 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 92:4fc01daae5a5 1023 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 92:4fc01daae5a5 1024 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
bogdanm 92:4fc01daae5a5 1025 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
bogdanm 92:4fc01daae5a5 1026 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
bogdanm 92:4fc01daae5a5 1027 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 92:4fc01daae5a5 1028 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 92:4fc01daae5a5 1029 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 92:4fc01daae5a5 1030 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 92:4fc01daae5a5 1031 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 92:4fc01daae5a5 1032 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 92:4fc01daae5a5 1033 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
bogdanm 92:4fc01daae5a5 1034 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm 92:4fc01daae5a5 1035 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
bogdanm 92:4fc01daae5a5 1036 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 92:4fc01daae5a5 1037 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 92:4fc01daae5a5 1038 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 92:4fc01daae5a5 1039 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 92:4fc01daae5a5 1040 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
bogdanm 92:4fc01daae5a5 1041 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
bogdanm 92:4fc01daae5a5 1042 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
bogdanm 92:4fc01daae5a5 1043 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
bogdanm 92:4fc01daae5a5 1044 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
bogdanm 92:4fc01daae5a5 1045 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
bogdanm 92:4fc01daae5a5 1046 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
bogdanm 92:4fc01daae5a5 1047 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
bogdanm 92:4fc01daae5a5 1048 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm 92:4fc01daae5a5 1049 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
bogdanm 92:4fc01daae5a5 1050 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
bogdanm 92:4fc01daae5a5 1051 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
bogdanm 92:4fc01daae5a5 1052 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
bogdanm 92:4fc01daae5a5 1053 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
bogdanm 92:4fc01daae5a5 1054 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
bogdanm 92:4fc01daae5a5 1055 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
bogdanm 92:4fc01daae5a5 1056 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
bogdanm 92:4fc01daae5a5 1057 #define RNG ((RNG_TypeDef *) RNG_BASE)
bogdanm 92:4fc01daae5a5 1058 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
bogdanm 92:4fc01daae5a5 1059 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
bogdanm 92:4fc01daae5a5 1060 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
bogdanm 92:4fc01daae5a5 1061 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
bogdanm 92:4fc01daae5a5 1062
bogdanm 92:4fc01daae5a5 1063 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 92:4fc01daae5a5 1064
bogdanm 92:4fc01daae5a5 1065 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
bogdanm 92:4fc01daae5a5 1066 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
bogdanm 92:4fc01daae5a5 1067
bogdanm 92:4fc01daae5a5 1068 /**
bogdanm 92:4fc01daae5a5 1069 * @}
bogdanm 92:4fc01daae5a5 1070 */
bogdanm 92:4fc01daae5a5 1071
bogdanm 92:4fc01daae5a5 1072 /** @addtogroup Exported_constants
bogdanm 92:4fc01daae5a5 1073 * @{
bogdanm 92:4fc01daae5a5 1074 */
bogdanm 92:4fc01daae5a5 1075
bogdanm 92:4fc01daae5a5 1076 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 92:4fc01daae5a5 1077 * @{
bogdanm 92:4fc01daae5a5 1078 */
bogdanm 92:4fc01daae5a5 1079
bogdanm 92:4fc01daae5a5 1080 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1081 /* Peripheral Registers_Bits_Definition */
bogdanm 92:4fc01daae5a5 1082 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1083
bogdanm 92:4fc01daae5a5 1084 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1085 /* */
bogdanm 92:4fc01daae5a5 1086 /* Analog to Digital Converter */
bogdanm 92:4fc01daae5a5 1087 /* */
bogdanm 92:4fc01daae5a5 1088 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1089 /******************** Bit definition for ADC_SR register ********************/
bogdanm 92:4fc01daae5a5 1090 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
bogdanm 92:4fc01daae5a5 1091 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
bogdanm 92:4fc01daae5a5 1092 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
bogdanm 92:4fc01daae5a5 1093 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
bogdanm 92:4fc01daae5a5 1094 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
bogdanm 92:4fc01daae5a5 1095 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
bogdanm 92:4fc01daae5a5 1096
bogdanm 92:4fc01daae5a5 1097 /******************* Bit definition for ADC_CR1 register ********************/
bogdanm 92:4fc01daae5a5 1098 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
bogdanm 92:4fc01daae5a5 1099 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1100 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1101 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1102 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1103 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1104 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
bogdanm 92:4fc01daae5a5 1105 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
bogdanm 92:4fc01daae5a5 1106 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
bogdanm 92:4fc01daae5a5 1107 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
bogdanm 92:4fc01daae5a5 1108 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
bogdanm 92:4fc01daae5a5 1109 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
bogdanm 92:4fc01daae5a5 1110 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
bogdanm 92:4fc01daae5a5 1111 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
bogdanm 92:4fc01daae5a5 1112 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
bogdanm 92:4fc01daae5a5 1113 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1114 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1115 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1116 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
bogdanm 92:4fc01daae5a5 1117 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
bogdanm 92:4fc01daae5a5 1118 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
bogdanm 92:4fc01daae5a5 1119 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1120 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1121 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
bogdanm 92:4fc01daae5a5 1122
bogdanm 92:4fc01daae5a5 1123 /******************* Bit definition for ADC_CR2 register ********************/
bogdanm 92:4fc01daae5a5 1124 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
bogdanm 92:4fc01daae5a5 1125 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
bogdanm 92:4fc01daae5a5 1126 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
bogdanm 92:4fc01daae5a5 1127 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
bogdanm 92:4fc01daae5a5 1128 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
bogdanm 92:4fc01daae5a5 1129 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
bogdanm 92:4fc01daae5a5 1130 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
bogdanm 92:4fc01daae5a5 1131 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1132 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1133 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1134 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1135 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
bogdanm 92:4fc01daae5a5 1136 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1137 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1138 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
bogdanm 92:4fc01daae5a5 1139 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
bogdanm 92:4fc01daae5a5 1140 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1141 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1142 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1143 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1144 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
bogdanm 92:4fc01daae5a5 1145 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1146 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1147 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
bogdanm 92:4fc01daae5a5 1148
bogdanm 92:4fc01daae5a5 1149 /****************** Bit definition for ADC_SMPR1 register *******************/
bogdanm 92:4fc01daae5a5 1150 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
bogdanm 92:4fc01daae5a5 1151 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1152 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1153 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1154 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
bogdanm 92:4fc01daae5a5 1155 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1156 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1157 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1158 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
bogdanm 92:4fc01daae5a5 1159 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1160 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1161 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1162 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
bogdanm 92:4fc01daae5a5 1163 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1164 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1165 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1166 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
bogdanm 92:4fc01daae5a5 1167 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1168 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1169 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1170 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
bogdanm 92:4fc01daae5a5 1171 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1172 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1173 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1174 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
bogdanm 92:4fc01daae5a5 1175 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1176 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1177 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1178 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
bogdanm 92:4fc01daae5a5 1179 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1180 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1181 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1182 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
bogdanm 92:4fc01daae5a5 1183 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1184 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1185 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1186
bogdanm 92:4fc01daae5a5 1187 /****************** Bit definition for ADC_SMPR2 register *******************/
bogdanm 92:4fc01daae5a5 1188 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
bogdanm 92:4fc01daae5a5 1189 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1190 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1191 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1192 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
bogdanm 92:4fc01daae5a5 1193 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1194 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1195 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1196 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
bogdanm 92:4fc01daae5a5 1197 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1198 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1199 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1200 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
bogdanm 92:4fc01daae5a5 1201 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1202 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1203 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1204 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
bogdanm 92:4fc01daae5a5 1205 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1206 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1207 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1208 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
bogdanm 92:4fc01daae5a5 1209 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1210 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1211 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1212 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
bogdanm 92:4fc01daae5a5 1213 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1214 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1215 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1216 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
bogdanm 92:4fc01daae5a5 1217 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1218 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1219 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1220 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
bogdanm 92:4fc01daae5a5 1221 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1222 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1223 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1224 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
bogdanm 92:4fc01daae5a5 1225 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1226 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1227 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1228
bogdanm 92:4fc01daae5a5 1229 /****************** Bit definition for ADC_JOFR1 register *******************/
bogdanm 92:4fc01daae5a5 1230 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
bogdanm 92:4fc01daae5a5 1231
bogdanm 92:4fc01daae5a5 1232 /****************** Bit definition for ADC_JOFR2 register *******************/
bogdanm 92:4fc01daae5a5 1233 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
bogdanm 92:4fc01daae5a5 1234
bogdanm 92:4fc01daae5a5 1235 /****************** Bit definition for ADC_JOFR3 register *******************/
bogdanm 92:4fc01daae5a5 1236 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
bogdanm 92:4fc01daae5a5 1237
bogdanm 92:4fc01daae5a5 1238 /****************** Bit definition for ADC_JOFR4 register *******************/
bogdanm 92:4fc01daae5a5 1239 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
bogdanm 92:4fc01daae5a5 1240
bogdanm 92:4fc01daae5a5 1241 /******************* Bit definition for ADC_HTR register ********************/
bogdanm 92:4fc01daae5a5 1242 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
bogdanm 92:4fc01daae5a5 1243
bogdanm 92:4fc01daae5a5 1244 /******************* Bit definition for ADC_LTR register ********************/
bogdanm 92:4fc01daae5a5 1245 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
bogdanm 92:4fc01daae5a5 1246
bogdanm 92:4fc01daae5a5 1247 /******************* Bit definition for ADC_SQR1 register *******************/
bogdanm 92:4fc01daae5a5 1248 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1249 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1250 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1251 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1252 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1253 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1254 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1255 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1256 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1257 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1258 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1259 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1260 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1261 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1262 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1263 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1264 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1265 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1266 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1267 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1268 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1269 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1270 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1271 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1272 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
bogdanm 92:4fc01daae5a5 1273 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1274 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1275 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1276 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1277
bogdanm 92:4fc01daae5a5 1278 /******************* Bit definition for ADC_SQR2 register *******************/
bogdanm 92:4fc01daae5a5 1279 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1280 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1281 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1282 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1283 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1284 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1285 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1286 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1287 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1288 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1289 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1290 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1291 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1292 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1293 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1294 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1295 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1296 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1297 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1298 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1299 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1300 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1301 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1302 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1303 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1304 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1305 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1306 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1307 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1308 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1309 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1310 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1311 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1312 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1313 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1314 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1315
bogdanm 92:4fc01daae5a5 1316 /******************* Bit definition for ADC_SQR3 register *******************/
bogdanm 92:4fc01daae5a5 1317 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1318 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1319 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1320 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1321 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1322 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1323 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1324 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1325 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1326 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1327 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1328 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1329 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1330 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1331 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1332 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1333 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1334 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1335 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1336 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1337 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1338 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1339 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1340 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1341 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1342 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1343 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1344 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1345 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1346 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1347 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
bogdanm 92:4fc01daae5a5 1348 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1349 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1350 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1351 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1352 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1353
bogdanm 92:4fc01daae5a5 1354 /******************* Bit definition for ADC_JSQR register *******************/
bogdanm 92:4fc01daae5a5 1355 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
bogdanm 92:4fc01daae5a5 1356 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1357 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1358 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1359 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1360 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1361 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
bogdanm 92:4fc01daae5a5 1362 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1363 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1364 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1365 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1366 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1367 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
bogdanm 92:4fc01daae5a5 1368 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1369 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1370 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1371 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1372 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1373 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
bogdanm 92:4fc01daae5a5 1374 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1375 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1376 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1377 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1378 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1379 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
bogdanm 92:4fc01daae5a5 1380 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1381 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1382
bogdanm 92:4fc01daae5a5 1383 /******************* Bit definition for ADC_JDR1 register *******************/
bogdanm 92:4fc01daae5a5 1384 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 92:4fc01daae5a5 1385
bogdanm 92:4fc01daae5a5 1386 /******************* Bit definition for ADC_JDR2 register *******************/
bogdanm 92:4fc01daae5a5 1387 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 92:4fc01daae5a5 1388
bogdanm 92:4fc01daae5a5 1389 /******************* Bit definition for ADC_JDR3 register *******************/
bogdanm 92:4fc01daae5a5 1390 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 92:4fc01daae5a5 1391
bogdanm 92:4fc01daae5a5 1392 /******************* Bit definition for ADC_JDR4 register *******************/
bogdanm 92:4fc01daae5a5 1393 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 92:4fc01daae5a5 1394
bogdanm 92:4fc01daae5a5 1395 /******************** Bit definition for ADC_DR register ********************/
bogdanm 92:4fc01daae5a5 1396 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
bogdanm 92:4fc01daae5a5 1397 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
bogdanm 92:4fc01daae5a5 1398
bogdanm 92:4fc01daae5a5 1399 /******************* Bit definition for ADC_CSR register ********************/
bogdanm 92:4fc01daae5a5 1400 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
bogdanm 92:4fc01daae5a5 1401 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
bogdanm 92:4fc01daae5a5 1402 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
bogdanm 92:4fc01daae5a5 1403 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
bogdanm 92:4fc01daae5a5 1404 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
bogdanm 92:4fc01daae5a5 1405 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
bogdanm 92:4fc01daae5a5 1406 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
bogdanm 92:4fc01daae5a5 1407 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
bogdanm 92:4fc01daae5a5 1408 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
bogdanm 92:4fc01daae5a5 1409 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
bogdanm 92:4fc01daae5a5 1410 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
bogdanm 92:4fc01daae5a5 1411 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
bogdanm 92:4fc01daae5a5 1412 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
bogdanm 92:4fc01daae5a5 1413 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
bogdanm 92:4fc01daae5a5 1414 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
bogdanm 92:4fc01daae5a5 1415 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
bogdanm 92:4fc01daae5a5 1416 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
bogdanm 92:4fc01daae5a5 1417 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
bogdanm 92:4fc01daae5a5 1418
bogdanm 92:4fc01daae5a5 1419 /******************* Bit definition for ADC_CCR register ********************/
bogdanm 92:4fc01daae5a5 1420 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
bogdanm 92:4fc01daae5a5 1421 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1422 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1423 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1424 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1425 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1426 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
bogdanm 92:4fc01daae5a5 1427 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1428 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1429 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1430 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1431 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
bogdanm 92:4fc01daae5a5 1432 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
bogdanm 92:4fc01daae5a5 1433 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1434 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1435 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
bogdanm 92:4fc01daae5a5 1436 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1437 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1438 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
bogdanm 92:4fc01daae5a5 1439 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
bogdanm 92:4fc01daae5a5 1440
bogdanm 92:4fc01daae5a5 1441 /******************* Bit definition for ADC_CDR register ********************/
bogdanm 92:4fc01daae5a5 1442 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
bogdanm 92:4fc01daae5a5 1443 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
bogdanm 92:4fc01daae5a5 1444
bogdanm 92:4fc01daae5a5 1445 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1446 /* */
bogdanm 92:4fc01daae5a5 1447 /* Controller Area Network */
bogdanm 92:4fc01daae5a5 1448 /* */
bogdanm 92:4fc01daae5a5 1449 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1450 /*!<CAN control and status registers */
bogdanm 92:4fc01daae5a5 1451 /******************* Bit definition for CAN_MCR register ********************/
bogdanm 92:4fc01daae5a5 1452 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
bogdanm 92:4fc01daae5a5 1453 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
bogdanm 92:4fc01daae5a5 1454 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
bogdanm 92:4fc01daae5a5 1455 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
bogdanm 92:4fc01daae5a5 1456 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
bogdanm 92:4fc01daae5a5 1457 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
bogdanm 92:4fc01daae5a5 1458 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
bogdanm 92:4fc01daae5a5 1459 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
bogdanm 92:4fc01daae5a5 1460 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
bogdanm 92:4fc01daae5a5 1461 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
bogdanm 92:4fc01daae5a5 1462 /******************* Bit definition for CAN_MSR register ********************/
bogdanm 92:4fc01daae5a5 1463 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
bogdanm 92:4fc01daae5a5 1464 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
bogdanm 92:4fc01daae5a5 1465 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
bogdanm 92:4fc01daae5a5 1466 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
bogdanm 92:4fc01daae5a5 1467 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
bogdanm 92:4fc01daae5a5 1468 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
bogdanm 92:4fc01daae5a5 1469 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
bogdanm 92:4fc01daae5a5 1470 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
bogdanm 92:4fc01daae5a5 1471 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
bogdanm 92:4fc01daae5a5 1472
bogdanm 92:4fc01daae5a5 1473 /******************* Bit definition for CAN_TSR register ********************/
bogdanm 92:4fc01daae5a5 1474 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
bogdanm 92:4fc01daae5a5 1475 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
bogdanm 92:4fc01daae5a5 1476 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
bogdanm 92:4fc01daae5a5 1477 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
bogdanm 92:4fc01daae5a5 1478 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
bogdanm 92:4fc01daae5a5 1479 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
bogdanm 92:4fc01daae5a5 1480 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
bogdanm 92:4fc01daae5a5 1481 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
bogdanm 92:4fc01daae5a5 1482 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
bogdanm 92:4fc01daae5a5 1483 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
bogdanm 92:4fc01daae5a5 1484 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
bogdanm 92:4fc01daae5a5 1485 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
bogdanm 92:4fc01daae5a5 1486 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
bogdanm 92:4fc01daae5a5 1487 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
bogdanm 92:4fc01daae5a5 1488 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
bogdanm 92:4fc01daae5a5 1489 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
bogdanm 92:4fc01daae5a5 1490
bogdanm 92:4fc01daae5a5 1491 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
bogdanm 92:4fc01daae5a5 1492 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
bogdanm 92:4fc01daae5a5 1493 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
bogdanm 92:4fc01daae5a5 1494 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
bogdanm 92:4fc01daae5a5 1495
bogdanm 92:4fc01daae5a5 1496 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
bogdanm 92:4fc01daae5a5 1497 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
bogdanm 92:4fc01daae5a5 1498 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
bogdanm 92:4fc01daae5a5 1499 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
bogdanm 92:4fc01daae5a5 1500
bogdanm 92:4fc01daae5a5 1501 /******************* Bit definition for CAN_RF0R register *******************/
bogdanm 92:4fc01daae5a5 1502 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
bogdanm 92:4fc01daae5a5 1503 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
bogdanm 92:4fc01daae5a5 1504 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
bogdanm 92:4fc01daae5a5 1505 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
bogdanm 92:4fc01daae5a5 1506
bogdanm 92:4fc01daae5a5 1507 /******************* Bit definition for CAN_RF1R register *******************/
bogdanm 92:4fc01daae5a5 1508 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
bogdanm 92:4fc01daae5a5 1509 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
bogdanm 92:4fc01daae5a5 1510 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
bogdanm 92:4fc01daae5a5 1511 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
bogdanm 92:4fc01daae5a5 1512
bogdanm 92:4fc01daae5a5 1513 /******************** Bit definition for CAN_IER register *******************/
bogdanm 92:4fc01daae5a5 1514 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
bogdanm 92:4fc01daae5a5 1515 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 92:4fc01daae5a5 1516 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
bogdanm 92:4fc01daae5a5 1517 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
bogdanm 92:4fc01daae5a5 1518 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 92:4fc01daae5a5 1519 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
bogdanm 92:4fc01daae5a5 1520 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
bogdanm 92:4fc01daae5a5 1521 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
bogdanm 92:4fc01daae5a5 1522 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
bogdanm 92:4fc01daae5a5 1523 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
bogdanm 92:4fc01daae5a5 1524 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
bogdanm 92:4fc01daae5a5 1525 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
bogdanm 92:4fc01daae5a5 1526 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
bogdanm 92:4fc01daae5a5 1527 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
bogdanm 92:4fc01daae5a5 1528 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
bogdanm 92:4fc01daae5a5 1529 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
bogdanm 92:4fc01daae5a5 1530 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
bogdanm 92:4fc01daae5a5 1531 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
bogdanm 92:4fc01daae5a5 1532 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
bogdanm 92:4fc01daae5a5 1533
bogdanm 92:4fc01daae5a5 1534
bogdanm 92:4fc01daae5a5 1535 /******************** Bit definition for CAN_ESR register *******************/
bogdanm 92:4fc01daae5a5 1536 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
bogdanm 92:4fc01daae5a5 1537 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
bogdanm 92:4fc01daae5a5 1538 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
bogdanm 92:4fc01daae5a5 1539
bogdanm 92:4fc01daae5a5 1540 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
bogdanm 92:4fc01daae5a5 1541 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1542 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1543 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1544
bogdanm 92:4fc01daae5a5 1545 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
bogdanm 92:4fc01daae5a5 1546 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
bogdanm 92:4fc01daae5a5 1547
bogdanm 92:4fc01daae5a5 1548 /******************* Bit definition for CAN_BTR register ********************/
bogdanm 92:4fc01daae5a5 1549 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
bogdanm 92:4fc01daae5a5 1550 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
bogdanm 92:4fc01daae5a5 1551 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1552 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1553 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1554 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1555 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
bogdanm 92:4fc01daae5a5 1556 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1557 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1558 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1559 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
bogdanm 92:4fc01daae5a5 1560 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 1561 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1562 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
bogdanm 92:4fc01daae5a5 1563 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
bogdanm 92:4fc01daae5a5 1564
bogdanm 92:4fc01daae5a5 1565
bogdanm 92:4fc01daae5a5 1566 /*!<Mailbox registers */
bogdanm 92:4fc01daae5a5 1567 /****************** Bit definition for CAN_TI0R register ********************/
bogdanm 92:4fc01daae5a5 1568 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 92:4fc01daae5a5 1569 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 92:4fc01daae5a5 1570 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 92:4fc01daae5a5 1571 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 92:4fc01daae5a5 1572 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1573
bogdanm 92:4fc01daae5a5 1574 /****************** Bit definition for CAN_TDT0R register *******************/
bogdanm 92:4fc01daae5a5 1575 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 92:4fc01daae5a5 1576 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 92:4fc01daae5a5 1577 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1578
bogdanm 92:4fc01daae5a5 1579 /****************** Bit definition for CAN_TDL0R register *******************/
bogdanm 92:4fc01daae5a5 1580 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 92:4fc01daae5a5 1581 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 92:4fc01daae5a5 1582 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 92:4fc01daae5a5 1583 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1584
bogdanm 92:4fc01daae5a5 1585 /****************** Bit definition for CAN_TDH0R register *******************/
bogdanm 92:4fc01daae5a5 1586 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 92:4fc01daae5a5 1587 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 92:4fc01daae5a5 1588 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 92:4fc01daae5a5 1589 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1590
bogdanm 92:4fc01daae5a5 1591 /******************* Bit definition for CAN_TI1R register *******************/
bogdanm 92:4fc01daae5a5 1592 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 92:4fc01daae5a5 1593 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 92:4fc01daae5a5 1594 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 92:4fc01daae5a5 1595 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 92:4fc01daae5a5 1596 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1597
bogdanm 92:4fc01daae5a5 1598 /******************* Bit definition for CAN_TDT1R register ******************/
bogdanm 92:4fc01daae5a5 1599 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 92:4fc01daae5a5 1600 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 92:4fc01daae5a5 1601 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1602
bogdanm 92:4fc01daae5a5 1603 /******************* Bit definition for CAN_TDL1R register ******************/
bogdanm 92:4fc01daae5a5 1604 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 92:4fc01daae5a5 1605 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 92:4fc01daae5a5 1606 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 92:4fc01daae5a5 1607 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1608
bogdanm 92:4fc01daae5a5 1609 /******************* Bit definition for CAN_TDH1R register ******************/
bogdanm 92:4fc01daae5a5 1610 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 92:4fc01daae5a5 1611 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 92:4fc01daae5a5 1612 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 92:4fc01daae5a5 1613 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1614
bogdanm 92:4fc01daae5a5 1615 /******************* Bit definition for CAN_TI2R register *******************/
bogdanm 92:4fc01daae5a5 1616 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 92:4fc01daae5a5 1617 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 92:4fc01daae5a5 1618 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 92:4fc01daae5a5 1619 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 92:4fc01daae5a5 1620 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1621
bogdanm 92:4fc01daae5a5 1622 /******************* Bit definition for CAN_TDT2R register ******************/
bogdanm 92:4fc01daae5a5 1623 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 92:4fc01daae5a5 1624 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 92:4fc01daae5a5 1625 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1626
bogdanm 92:4fc01daae5a5 1627 /******************* Bit definition for CAN_TDL2R register ******************/
bogdanm 92:4fc01daae5a5 1628 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 92:4fc01daae5a5 1629 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 92:4fc01daae5a5 1630 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 92:4fc01daae5a5 1631 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1632
bogdanm 92:4fc01daae5a5 1633 /******************* Bit definition for CAN_TDH2R register ******************/
bogdanm 92:4fc01daae5a5 1634 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 92:4fc01daae5a5 1635 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 92:4fc01daae5a5 1636 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 92:4fc01daae5a5 1637 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1638
bogdanm 92:4fc01daae5a5 1639 /******************* Bit definition for CAN_RI0R register *******************/
bogdanm 92:4fc01daae5a5 1640 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 92:4fc01daae5a5 1641 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 92:4fc01daae5a5 1642 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 92:4fc01daae5a5 1643 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1644
bogdanm 92:4fc01daae5a5 1645 /******************* Bit definition for CAN_RDT0R register ******************/
bogdanm 92:4fc01daae5a5 1646 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 92:4fc01daae5a5 1647 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 92:4fc01daae5a5 1648 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1649
bogdanm 92:4fc01daae5a5 1650 /******************* Bit definition for CAN_RDL0R register ******************/
bogdanm 92:4fc01daae5a5 1651 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 92:4fc01daae5a5 1652 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 92:4fc01daae5a5 1653 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 92:4fc01daae5a5 1654 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1655
bogdanm 92:4fc01daae5a5 1656 /******************* Bit definition for CAN_RDH0R register ******************/
bogdanm 92:4fc01daae5a5 1657 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 92:4fc01daae5a5 1658 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 92:4fc01daae5a5 1659 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 92:4fc01daae5a5 1660 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1661
bogdanm 92:4fc01daae5a5 1662 /******************* Bit definition for CAN_RI1R register *******************/
bogdanm 92:4fc01daae5a5 1663 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 92:4fc01daae5a5 1664 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 92:4fc01daae5a5 1665 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 92:4fc01daae5a5 1666 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1667
bogdanm 92:4fc01daae5a5 1668 /******************* Bit definition for CAN_RDT1R register ******************/
bogdanm 92:4fc01daae5a5 1669 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 92:4fc01daae5a5 1670 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 92:4fc01daae5a5 1671 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1672
bogdanm 92:4fc01daae5a5 1673 /******************* Bit definition for CAN_RDL1R register ******************/
bogdanm 92:4fc01daae5a5 1674 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 92:4fc01daae5a5 1675 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 92:4fc01daae5a5 1676 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 92:4fc01daae5a5 1677 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1678
bogdanm 92:4fc01daae5a5 1679 /******************* Bit definition for CAN_RDH1R register ******************/
bogdanm 92:4fc01daae5a5 1680 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 92:4fc01daae5a5 1681 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 92:4fc01daae5a5 1682 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 92:4fc01daae5a5 1683 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1684
bogdanm 92:4fc01daae5a5 1685 /*!<CAN filter registers */
bogdanm 92:4fc01daae5a5 1686 /******************* Bit definition for CAN_FMR register ********************/
bogdanm 92:4fc01daae5a5 1687 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
bogdanm 92:4fc01daae5a5 1688 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
bogdanm 92:4fc01daae5a5 1689
bogdanm 92:4fc01daae5a5 1690 /******************* Bit definition for CAN_FM1R register *******************/
bogdanm 92:4fc01daae5a5 1691 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
bogdanm 92:4fc01daae5a5 1692 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
bogdanm 92:4fc01daae5a5 1693 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
bogdanm 92:4fc01daae5a5 1694 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
bogdanm 92:4fc01daae5a5 1695 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
bogdanm 92:4fc01daae5a5 1696 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
bogdanm 92:4fc01daae5a5 1697 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
bogdanm 92:4fc01daae5a5 1698 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
bogdanm 92:4fc01daae5a5 1699 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
bogdanm 92:4fc01daae5a5 1700 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
bogdanm 92:4fc01daae5a5 1701 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
bogdanm 92:4fc01daae5a5 1702 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
bogdanm 92:4fc01daae5a5 1703 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
bogdanm 92:4fc01daae5a5 1704 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
bogdanm 92:4fc01daae5a5 1705 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
bogdanm 92:4fc01daae5a5 1706
bogdanm 92:4fc01daae5a5 1707 /******************* Bit definition for CAN_FS1R register *******************/
bogdanm 92:4fc01daae5a5 1708 #define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
bogdanm 92:4fc01daae5a5 1709 #define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
bogdanm 92:4fc01daae5a5 1710 #define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
bogdanm 92:4fc01daae5a5 1711 #define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
bogdanm 92:4fc01daae5a5 1712 #define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
bogdanm 92:4fc01daae5a5 1713 #define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
bogdanm 92:4fc01daae5a5 1714 #define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
bogdanm 92:4fc01daae5a5 1715 #define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
bogdanm 92:4fc01daae5a5 1716 #define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
bogdanm 92:4fc01daae5a5 1717 #define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
bogdanm 92:4fc01daae5a5 1718 #define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
bogdanm 92:4fc01daae5a5 1719 #define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
bogdanm 92:4fc01daae5a5 1720 #define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
bogdanm 92:4fc01daae5a5 1721 #define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
bogdanm 92:4fc01daae5a5 1722 #define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
bogdanm 92:4fc01daae5a5 1723
bogdanm 92:4fc01daae5a5 1724 /****************** Bit definition for CAN_FFA1R register *******************/
bogdanm 92:4fc01daae5a5 1725 #define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
bogdanm 92:4fc01daae5a5 1726 #define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
bogdanm 92:4fc01daae5a5 1727 #define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
bogdanm 92:4fc01daae5a5 1728 #define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
bogdanm 92:4fc01daae5a5 1729 #define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
bogdanm 92:4fc01daae5a5 1730 #define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
bogdanm 92:4fc01daae5a5 1731 #define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
bogdanm 92:4fc01daae5a5 1732 #define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
bogdanm 92:4fc01daae5a5 1733 #define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
bogdanm 92:4fc01daae5a5 1734 #define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
bogdanm 92:4fc01daae5a5 1735 #define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
bogdanm 92:4fc01daae5a5 1736 #define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
bogdanm 92:4fc01daae5a5 1737 #define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
bogdanm 92:4fc01daae5a5 1738 #define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
bogdanm 92:4fc01daae5a5 1739 #define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
bogdanm 92:4fc01daae5a5 1740
bogdanm 92:4fc01daae5a5 1741 /******************* Bit definition for CAN_FA1R register *******************/
bogdanm 92:4fc01daae5a5 1742 #define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
bogdanm 92:4fc01daae5a5 1743 #define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
bogdanm 92:4fc01daae5a5 1744 #define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
bogdanm 92:4fc01daae5a5 1745 #define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
bogdanm 92:4fc01daae5a5 1746 #define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
bogdanm 92:4fc01daae5a5 1747 #define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
bogdanm 92:4fc01daae5a5 1748 #define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
bogdanm 92:4fc01daae5a5 1749 #define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
bogdanm 92:4fc01daae5a5 1750 #define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
bogdanm 92:4fc01daae5a5 1751 #define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
bogdanm 92:4fc01daae5a5 1752 #define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
bogdanm 92:4fc01daae5a5 1753 #define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
bogdanm 92:4fc01daae5a5 1754 #define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
bogdanm 92:4fc01daae5a5 1755 #define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
bogdanm 92:4fc01daae5a5 1756 #define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
bogdanm 92:4fc01daae5a5 1757
bogdanm 92:4fc01daae5a5 1758 /******************* Bit definition for CAN_F0R1 register *******************/
bogdanm 92:4fc01daae5a5 1759 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 1760 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 1761 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 1762 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 1763 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 1764 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 1765 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 1766 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 1767 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 1768 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 1769 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 1770 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 1771 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 1772 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 1773 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 1774 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 1775 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 1776 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 1777 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 1778 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 1779 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 1780 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 1781 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 1782 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 1783 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 1784 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 1785 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 1786 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 1787 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 1788 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 1789 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 1790 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1791
bogdanm 92:4fc01daae5a5 1792 /******************* Bit definition for CAN_F1R1 register *******************/
bogdanm 92:4fc01daae5a5 1793 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 1794 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 1795 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 1796 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 1797 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 1798 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 1799 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 1800 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 1801 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 1802 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 1803 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 1804 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 1805 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 1806 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 1807 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 1808 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 1809 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 1810 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 1811 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 1812 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 1813 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 1814 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 1815 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 1816 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 1817 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 1818 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 1819 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 1820 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 1821 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 1822 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 1823 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 1824 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1825
bogdanm 92:4fc01daae5a5 1826 /******************* Bit definition for CAN_F2R1 register *******************/
bogdanm 92:4fc01daae5a5 1827 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 1828 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 1829 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 1830 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 1831 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 1832 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 1833 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 1834 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 1835 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 1836 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 1837 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 1838 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 1839 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 1840 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 1841 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 1842 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 1843 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 1844 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 1845 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 1846 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 1847 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 1848 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 1849 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 1850 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 1851 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 1852 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 1853 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 1854 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 1855 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 1856 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 1857 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 1858 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1859
bogdanm 92:4fc01daae5a5 1860 /******************* Bit definition for CAN_F3R1 register *******************/
bogdanm 92:4fc01daae5a5 1861 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 1862 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 1863 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 1864 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 1865 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 1866 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 1867 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 1868 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 1869 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 1870 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 1871 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 1872 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 1873 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 1874 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 1875 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 1876 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 1877 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 1878 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 1879 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 1880 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 1881 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 1882 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 1883 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 1884 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 1885 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 1886 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 1887 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 1888 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 1889 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 1890 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 1891 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 1892 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1893
bogdanm 92:4fc01daae5a5 1894 /******************* Bit definition for CAN_F4R1 register *******************/
bogdanm 92:4fc01daae5a5 1895 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 1896 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 1897 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 1898 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 1899 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 1900 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 1901 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 1902 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 1903 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 1904 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 1905 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 1906 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 1907 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 1908 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 1909 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 1910 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 1911 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 1912 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 1913 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 1914 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 1915 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 1916 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 1917 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 1918 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 1919 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 1920 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 1921 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 1922 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 1923 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 1924 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 1925 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 1926 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1927
bogdanm 92:4fc01daae5a5 1928 /******************* Bit definition for CAN_F5R1 register *******************/
bogdanm 92:4fc01daae5a5 1929 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 1930 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 1931 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 1932 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 1933 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 1934 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 1935 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 1936 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 1937 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 1938 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 1939 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 1940 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 1941 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 1942 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 1943 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 1944 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 1945 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 1946 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 1947 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 1948 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 1949 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 1950 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 1951 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 1952 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 1953 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 1954 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 1955 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 1956 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 1957 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 1958 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 1959 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 1960 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1961
bogdanm 92:4fc01daae5a5 1962 /******************* Bit definition for CAN_F6R1 register *******************/
bogdanm 92:4fc01daae5a5 1963 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 1964 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 1965 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 1966 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 1967 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 1968 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 1969 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 1970 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 1971 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 1972 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 1973 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 1974 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 1975 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 1976 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 1977 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 1978 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 1979 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 1980 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 1981 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 1982 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 1983 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 1984 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 1985 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 1986 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 1987 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 1988 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 1989 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 1990 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 1991 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 1992 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 1993 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 1994 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1995
bogdanm 92:4fc01daae5a5 1996 /******************* Bit definition for CAN_F7R1 register *******************/
bogdanm 92:4fc01daae5a5 1997 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 1998 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 1999 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2000 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2001 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2002 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2003 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2004 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2005 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2006 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2007 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2008 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2009 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2010 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2011 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2012 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2013 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2014 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2015 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2016 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2017 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2018 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2019 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2020 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2021 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2022 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2023 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2024 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2025 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2026 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2027 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2028 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2029
bogdanm 92:4fc01daae5a5 2030 /******************* Bit definition for CAN_F8R1 register *******************/
bogdanm 92:4fc01daae5a5 2031 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2032 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2033 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2034 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2035 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2036 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2037 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2038 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2039 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2040 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2041 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2042 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2043 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2044 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2045 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2046 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2047 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2048 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2049 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2050 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2051 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2052 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2053 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2054 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2055 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2056 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2057 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2058 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2059 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2060 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2061 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2062 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2063
bogdanm 92:4fc01daae5a5 2064 /******************* Bit definition for CAN_F9R1 register *******************/
bogdanm 92:4fc01daae5a5 2065 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2066 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2067 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2068 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2069 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2070 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2071 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2072 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2073 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2074 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2075 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2076 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2077 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2078 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2079 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2080 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2081 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2082 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2083 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2084 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2085 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2086 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2087 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2088 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2089 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2090 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2091 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2092 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2093 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2094 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2095 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2096 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2097
bogdanm 92:4fc01daae5a5 2098 /******************* Bit definition for CAN_F10R1 register ******************/
bogdanm 92:4fc01daae5a5 2099 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2100 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2101 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2102 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2103 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2104 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2105 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2106 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2107 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2108 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2109 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2110 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2111 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2112 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2113 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2114 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2115 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2116 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2117 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2118 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2119 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2120 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2121 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2122 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2123 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2124 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2125 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2126 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2127 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2128 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2129 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2130 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2131
bogdanm 92:4fc01daae5a5 2132 /******************* Bit definition for CAN_F11R1 register ******************/
bogdanm 92:4fc01daae5a5 2133 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2134 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2135 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2136 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2137 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2138 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2139 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2140 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2141 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2142 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2143 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2144 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2145 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2146 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2147 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2148 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2149 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2150 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2151 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2152 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2153 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2154 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2155 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2156 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2157 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2158 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2159 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2160 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2161 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2162 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2163 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2164 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2165
bogdanm 92:4fc01daae5a5 2166 /******************* Bit definition for CAN_F12R1 register ******************/
bogdanm 92:4fc01daae5a5 2167 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2168 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2169 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2170 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2171 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2172 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2173 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2174 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2175 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2176 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2177 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2178 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2179 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2180 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2181 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2182 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2183 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2184 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2185 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2186 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2187 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2188 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2189 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2190 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2191 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2192 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2193 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2194 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2195 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2196 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2197 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2198 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2199
bogdanm 92:4fc01daae5a5 2200 /******************* Bit definition for CAN_F13R1 register ******************/
bogdanm 92:4fc01daae5a5 2201 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2202 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2203 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2204 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2205 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2206 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2207 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2208 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2209 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2210 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2211 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2212 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2213 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2214 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2215 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2216 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2217 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2218 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2219 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2220 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2221 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2222 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2223 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2224 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2225 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2226 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2227 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2228 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2229 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2230 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2231 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2232 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2233
bogdanm 92:4fc01daae5a5 2234 /******************* Bit definition for CAN_F0R2 register *******************/
bogdanm 92:4fc01daae5a5 2235 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2236 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2237 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2238 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2239 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2240 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2241 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2242 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2243 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2244 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2245 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2246 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2247 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2248 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2249 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2250 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2251 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2252 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2253 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2254 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2255 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2256 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2257 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2258 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2259 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2260 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2261 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2262 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2263 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2264 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2265 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2266 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2267
bogdanm 92:4fc01daae5a5 2268 /******************* Bit definition for CAN_F1R2 register *******************/
bogdanm 92:4fc01daae5a5 2269 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2270 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2271 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2272 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2273 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2274 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2275 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2276 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2277 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2278 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2279 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2280 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2281 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2282 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2283 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2284 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2285 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2286 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2287 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2288 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2289 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2290 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2291 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2292 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2293 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2294 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2295 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2296 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2297 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2298 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2299 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2300 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2301
bogdanm 92:4fc01daae5a5 2302 /******************* Bit definition for CAN_F2R2 register *******************/
bogdanm 92:4fc01daae5a5 2303 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2304 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2305 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2306 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2307 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2308 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2309 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2310 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2311 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2312 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2313 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2314 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2315 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2316 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2317 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2318 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2319 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2320 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2321 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2322 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2323 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2324 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2325 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2326 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2327 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2328 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2329 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2330 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2331 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2332 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2333 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2334 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2335
bogdanm 92:4fc01daae5a5 2336 /******************* Bit definition for CAN_F3R2 register *******************/
bogdanm 92:4fc01daae5a5 2337 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2338 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2339 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2340 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2341 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2342 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2343 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2344 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2345 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2346 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2347 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2348 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2349 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2350 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2351 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2352 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2353 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2354 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2355 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2356 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2357 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2358 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2359 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2360 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2361 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2362 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2363 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2364 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2365 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2366 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2367 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2368 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2369
bogdanm 92:4fc01daae5a5 2370 /******************* Bit definition for CAN_F4R2 register *******************/
bogdanm 92:4fc01daae5a5 2371 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2372 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2373 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2374 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2375 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2376 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2377 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2378 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2379 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2380 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2381 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2382 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2383 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2384 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2385 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2386 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2387 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2388 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2389 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2390 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2391 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2392 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2393 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2394 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2395 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2396 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2397 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2398 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2399 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2400 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2401 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2402 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2403
bogdanm 92:4fc01daae5a5 2404 /******************* Bit definition for CAN_F5R2 register *******************/
bogdanm 92:4fc01daae5a5 2405 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2406 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2407 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2408 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2409 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2410 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2411 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2412 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2413 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2414 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2415 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2416 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2417 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2418 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2419 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2420 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2421 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2422 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2423 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2424 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2425 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2426 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2427 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2428 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2429 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2430 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2431 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2432 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2433 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2434 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2435 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2436 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2437
bogdanm 92:4fc01daae5a5 2438 /******************* Bit definition for CAN_F6R2 register *******************/
bogdanm 92:4fc01daae5a5 2439 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2440 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2441 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2442 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2443 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2444 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2445 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2446 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2447 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2448 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2449 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2450 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2451 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2452 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2453 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2454 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2455 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2456 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2457 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2458 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2459 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2460 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2461 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2462 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2463 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2464 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2465 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2466 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2467 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2468 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2469 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2470 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2471
bogdanm 92:4fc01daae5a5 2472 /******************* Bit definition for CAN_F7R2 register *******************/
bogdanm 92:4fc01daae5a5 2473 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2474 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2475 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2476 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2477 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2478 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2479 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2480 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2481 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2482 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2483 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2484 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2485 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2486 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2487 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2488 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2489 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2490 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2491 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2492 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2493 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2494 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2495 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2496 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2497 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2498 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2499 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2500 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2501 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2502 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2503 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2504 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2505
bogdanm 92:4fc01daae5a5 2506 /******************* Bit definition for CAN_F8R2 register *******************/
bogdanm 92:4fc01daae5a5 2507 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2508 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2509 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2510 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2511 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2512 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2513 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2514 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2515 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2516 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2517 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2518 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2519 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2520 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2521 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2522 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2523 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2524 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2525 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2526 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2527 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2528 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2529 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2530 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2531 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2532 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2533 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2534 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2535 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2536 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2537 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2538 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2539
bogdanm 92:4fc01daae5a5 2540 /******************* Bit definition for CAN_F9R2 register *******************/
bogdanm 92:4fc01daae5a5 2541 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2542 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2543 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2544 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2545 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2546 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2547 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2548 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2549 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2550 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2551 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2552 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2553 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2554 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2555 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2556 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2557 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2558 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2559 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2560 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2561 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2562 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2563 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2564 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2565 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2566 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2567 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2568 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2569 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2570 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2571 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2572 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2573
bogdanm 92:4fc01daae5a5 2574 /******************* Bit definition for CAN_F10R2 register ******************/
bogdanm 92:4fc01daae5a5 2575 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2576 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2577 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2578 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2579 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2580 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2581 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2582 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2583 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2584 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2585 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2586 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2587 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2588 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2589 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2590 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2591 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2592 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2593 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2594 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2595 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2596 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2597 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2598 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2599 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2600 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2601 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2602 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2603 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2604 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2605 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2606 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2607
bogdanm 92:4fc01daae5a5 2608 /******************* Bit definition for CAN_F11R2 register ******************/
bogdanm 92:4fc01daae5a5 2609 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2610 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2611 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2612 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2613 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2614 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2615 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2616 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2617 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2618 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2619 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2620 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2621 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2622 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2623 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2624 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2625 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2626 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2627 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2628 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2629 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2630 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2631 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2632 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2633 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2634 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2635 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2636 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2637 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2638 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2639 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2640 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2641
bogdanm 92:4fc01daae5a5 2642 /******************* Bit definition for CAN_F12R2 register ******************/
bogdanm 92:4fc01daae5a5 2643 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2644 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2645 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2646 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2647 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2648 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2649 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2650 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2651 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2652 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2653 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2654 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2655 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2656 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2657 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2658 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2659 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2660 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2661 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2662 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2663 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2664 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2665 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2666 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2667 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2668 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2669 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2670 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2671 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2672 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2673 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2674 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2675
bogdanm 92:4fc01daae5a5 2676 /******************* Bit definition for CAN_F13R2 register ******************/
bogdanm 92:4fc01daae5a5 2677 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 92:4fc01daae5a5 2678 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 92:4fc01daae5a5 2679 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 92:4fc01daae5a5 2680 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 92:4fc01daae5a5 2681 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 92:4fc01daae5a5 2682 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 92:4fc01daae5a5 2683 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 92:4fc01daae5a5 2684 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 92:4fc01daae5a5 2685 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 92:4fc01daae5a5 2686 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 92:4fc01daae5a5 2687 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 92:4fc01daae5a5 2688 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 92:4fc01daae5a5 2689 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 92:4fc01daae5a5 2690 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 92:4fc01daae5a5 2691 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 92:4fc01daae5a5 2692 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 92:4fc01daae5a5 2693 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 92:4fc01daae5a5 2694 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 92:4fc01daae5a5 2695 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 92:4fc01daae5a5 2696 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 92:4fc01daae5a5 2697 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 92:4fc01daae5a5 2698 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 92:4fc01daae5a5 2699 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 92:4fc01daae5a5 2700 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 92:4fc01daae5a5 2701 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 92:4fc01daae5a5 2702 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 92:4fc01daae5a5 2703 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 92:4fc01daae5a5 2704 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 92:4fc01daae5a5 2705 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 92:4fc01daae5a5 2706 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 92:4fc01daae5a5 2707 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 92:4fc01daae5a5 2708 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2709
bogdanm 92:4fc01daae5a5 2710 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2711 /* */
bogdanm 92:4fc01daae5a5 2712 /* CRC calculation unit */
bogdanm 92:4fc01daae5a5 2713 /* */
bogdanm 92:4fc01daae5a5 2714 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2715 /******************* Bit definition for CRC_DR register *********************/
bogdanm 92:4fc01daae5a5 2716 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 92:4fc01daae5a5 2717
bogdanm 92:4fc01daae5a5 2718
bogdanm 92:4fc01daae5a5 2719 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 92:4fc01daae5a5 2720 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
bogdanm 92:4fc01daae5a5 2721
bogdanm 92:4fc01daae5a5 2722
bogdanm 92:4fc01daae5a5 2723 /******************** Bit definition for CRC_CR register ********************/
bogdanm 92:4fc01daae5a5 2724 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
bogdanm 92:4fc01daae5a5 2725
bogdanm 92:4fc01daae5a5 2726
bogdanm 92:4fc01daae5a5 2727 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2728 /* */
bogdanm 92:4fc01daae5a5 2729 /* Digital to Analog Converter */
bogdanm 92:4fc01daae5a5 2730 /* */
bogdanm 92:4fc01daae5a5 2731 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2732 /******************** Bit definition for DAC_CR register ********************/
bogdanm 92:4fc01daae5a5 2733 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
bogdanm 92:4fc01daae5a5 2734 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
bogdanm 92:4fc01daae5a5 2735 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
bogdanm 92:4fc01daae5a5 2736
bogdanm 92:4fc01daae5a5 2737 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
bogdanm 92:4fc01daae5a5 2738 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2739 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2740 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 2741
bogdanm 92:4fc01daae5a5 2742 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
bogdanm 92:4fc01daae5a5 2743 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2744 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2745
bogdanm 92:4fc01daae5a5 2746 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
bogdanm 92:4fc01daae5a5 2747 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2748 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2749 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 2750 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 2751
bogdanm 92:4fc01daae5a5 2752 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
bogdanm 92:4fc01daae5a5 2753 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
bogdanm 92:4fc01daae5a5 2754 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
bogdanm 92:4fc01daae5a5 2755 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
bogdanm 92:4fc01daae5a5 2756
bogdanm 92:4fc01daae5a5 2757 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
bogdanm 92:4fc01daae5a5 2758 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2759 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2760 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 2761
bogdanm 92:4fc01daae5a5 2762 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
bogdanm 92:4fc01daae5a5 2763 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2764 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2765
bogdanm 92:4fc01daae5a5 2766 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
bogdanm 92:4fc01daae5a5 2767 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2768 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2769 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 2770 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 2771
bogdanm 92:4fc01daae5a5 2772 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
bogdanm 92:4fc01daae5a5 2773
bogdanm 92:4fc01daae5a5 2774 /***************** Bit definition for DAC_SWTRIGR register ******************/
bogdanm 92:4fc01daae5a5 2775 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
bogdanm 92:4fc01daae5a5 2776 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
bogdanm 92:4fc01daae5a5 2777
bogdanm 92:4fc01daae5a5 2778 /***************** Bit definition for DAC_DHR12R1 register ******************/
bogdanm 92:4fc01daae5a5 2779 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2780
bogdanm 92:4fc01daae5a5 2781 /***************** Bit definition for DAC_DHR12L1 register ******************/
bogdanm 92:4fc01daae5a5 2782 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
bogdanm 92:4fc01daae5a5 2783
bogdanm 92:4fc01daae5a5 2784 /****************** Bit definition for DAC_DHR8R1 register ******************/
bogdanm 92:4fc01daae5a5 2785 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2786
bogdanm 92:4fc01daae5a5 2787 /***************** Bit definition for DAC_DHR12R2 register ******************/
bogdanm 92:4fc01daae5a5 2788 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2789
bogdanm 92:4fc01daae5a5 2790 /***************** Bit definition for DAC_DHR12L2 register ******************/
bogdanm 92:4fc01daae5a5 2791 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
bogdanm 92:4fc01daae5a5 2792
bogdanm 92:4fc01daae5a5 2793 /****************** Bit definition for DAC_DHR8R2 register ******************/
bogdanm 92:4fc01daae5a5 2794 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2795
bogdanm 92:4fc01daae5a5 2796 /***************** Bit definition for DAC_DHR12RD register ******************/
bogdanm 92:4fc01daae5a5 2797 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2798 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2799
bogdanm 92:4fc01daae5a5 2800 /***************** Bit definition for DAC_DHR12LD register ******************/
bogdanm 92:4fc01daae5a5 2801 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
bogdanm 92:4fc01daae5a5 2802 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
bogdanm 92:4fc01daae5a5 2803
bogdanm 92:4fc01daae5a5 2804 /****************** Bit definition for DAC_DHR8RD register ******************/
bogdanm 92:4fc01daae5a5 2805 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2806 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2807
bogdanm 92:4fc01daae5a5 2808 /******************* Bit definition for DAC_DOR1 register *******************/
bogdanm 92:4fc01daae5a5 2809 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
bogdanm 92:4fc01daae5a5 2810
bogdanm 92:4fc01daae5a5 2811 /******************* Bit definition for DAC_DOR2 register *******************/
bogdanm 92:4fc01daae5a5 2812 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
bogdanm 92:4fc01daae5a5 2813
bogdanm 92:4fc01daae5a5 2814 /******************** Bit definition for DAC_SR register ********************/
bogdanm 92:4fc01daae5a5 2815 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
bogdanm 92:4fc01daae5a5 2816 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
bogdanm 92:4fc01daae5a5 2817
bogdanm 92:4fc01daae5a5 2818 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2819 /* */
bogdanm 92:4fc01daae5a5 2820 /* Debug MCU */
bogdanm 92:4fc01daae5a5 2821 /* */
bogdanm 92:4fc01daae5a5 2822 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2823
bogdanm 92:4fc01daae5a5 2824 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2825 /* */
bogdanm 92:4fc01daae5a5 2826 /* DMA Controller */
bogdanm 92:4fc01daae5a5 2827 /* */
bogdanm 92:4fc01daae5a5 2828 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2829 /******************** Bits definition for DMA_SxCR register *****************/
bogdanm 92:4fc01daae5a5 2830 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
bogdanm 92:4fc01daae5a5 2831 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 2832 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 2833 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 2834 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
bogdanm 92:4fc01daae5a5 2835 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 2836 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 2837 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
bogdanm 92:4fc01daae5a5 2838 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 2839 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 2840 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 2841 #define DMA_SxCR_CT ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 2842 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 2843 #define DMA_SxCR_PL ((uint32_t)0x00030000)
bogdanm 92:4fc01daae5a5 2844 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 2845 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 2846 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 2847 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
bogdanm 92:4fc01daae5a5 2848 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 2849 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 2850 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
bogdanm 92:4fc01daae5a5 2851 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 2852 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 2853 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 2854 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 2855 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 2856 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
bogdanm 92:4fc01daae5a5 2857 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 2858 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 2859 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 2860 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 2861 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 2862 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 2863 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 2864 #define DMA_SxCR_EN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 2865
bogdanm 92:4fc01daae5a5 2866 /******************** Bits definition for DMA_SxCNDTR register **************/
bogdanm 92:4fc01daae5a5 2867 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
bogdanm 92:4fc01daae5a5 2868 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 2869 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 2870 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 2871 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 2872 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 2873 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 2874 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 2875 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 2876 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 2877 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 2878 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 2879 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 2880 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 2881 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 2882 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 2883 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 2884
bogdanm 92:4fc01daae5a5 2885 /******************** Bits definition for DMA_SxFCR register ****************/
bogdanm 92:4fc01daae5a5 2886 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 2887 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
bogdanm 92:4fc01daae5a5 2888 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 2889 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 2890 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 2891 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 2892 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
bogdanm 92:4fc01daae5a5 2893 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 2894 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 2895
bogdanm 92:4fc01daae5a5 2896 /******************** Bits definition for DMA_LISR register *****************/
bogdanm 92:4fc01daae5a5 2897 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 2898 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 2899 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 2900 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 2901 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 2902 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 2903 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 2904 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 2905 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 2906 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 2907 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 2908 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 2909 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 2910 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 2911 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 2912 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 2913 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 2914 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 2915 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 2916 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 2917
bogdanm 92:4fc01daae5a5 2918 /******************** Bits definition for DMA_HISR register *****************/
bogdanm 92:4fc01daae5a5 2919 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 2920 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 2921 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 2922 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 2923 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 2924 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 2925 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 2926 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 2927 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 2928 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 2929 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 2930 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 2931 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 2932 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 2933 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 2934 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 2935 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 2936 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 2937 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 2938 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 2939
bogdanm 92:4fc01daae5a5 2940 /******************** Bits definition for DMA_LIFCR register ****************/
bogdanm 92:4fc01daae5a5 2941 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 2942 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 2943 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 2944 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 2945 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 2946 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 2947 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 2948 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 2949 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 2950 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 2951 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 2952 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 2953 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 2954 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 2955 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 2956 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 2957 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 2958 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 2959 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 2960 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 2961
bogdanm 92:4fc01daae5a5 2962 /******************** Bits definition for DMA_HIFCR register ****************/
bogdanm 92:4fc01daae5a5 2963 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 2964 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 2965 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 2966 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 2967 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 2968 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 2969 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 2970 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 2971 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 2972 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 2973 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 2974 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 2975 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 2976 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 2977 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 2978 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 2979 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 2980 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 2981 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 2982 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 2983
bogdanm 92:4fc01daae5a5 2984
bogdanm 92:4fc01daae5a5 2985 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2986 /* */
bogdanm 92:4fc01daae5a5 2987 /* External Interrupt/Event Controller */
bogdanm 92:4fc01daae5a5 2988 /* */
bogdanm 92:4fc01daae5a5 2989 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2990 /******************* Bit definition for EXTI_IMR register *******************/
bogdanm 92:4fc01daae5a5 2991 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 92:4fc01daae5a5 2992 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 92:4fc01daae5a5 2993 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 92:4fc01daae5a5 2994 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 92:4fc01daae5a5 2995 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 92:4fc01daae5a5 2996 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 92:4fc01daae5a5 2997 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 92:4fc01daae5a5 2998 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 92:4fc01daae5a5 2999 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 92:4fc01daae5a5 3000 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 92:4fc01daae5a5 3001 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 92:4fc01daae5a5 3002 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 92:4fc01daae5a5 3003 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 92:4fc01daae5a5 3004 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 92:4fc01daae5a5 3005 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 92:4fc01daae5a5 3006 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 92:4fc01daae5a5 3007 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 92:4fc01daae5a5 3008 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 92:4fc01daae5a5 3009 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 92:4fc01daae5a5 3010 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 92:4fc01daae5a5 3011
bogdanm 92:4fc01daae5a5 3012 /******************* Bit definition for EXTI_EMR register *******************/
bogdanm 92:4fc01daae5a5 3013 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 92:4fc01daae5a5 3014 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 92:4fc01daae5a5 3015 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 92:4fc01daae5a5 3016 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 92:4fc01daae5a5 3017 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 92:4fc01daae5a5 3018 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 92:4fc01daae5a5 3019 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 92:4fc01daae5a5 3020 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 92:4fc01daae5a5 3021 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 92:4fc01daae5a5 3022 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 92:4fc01daae5a5 3023 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 92:4fc01daae5a5 3024 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 92:4fc01daae5a5 3025 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 92:4fc01daae5a5 3026 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 92:4fc01daae5a5 3027 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 92:4fc01daae5a5 3028 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 92:4fc01daae5a5 3029 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 92:4fc01daae5a5 3030 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 92:4fc01daae5a5 3031 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 92:4fc01daae5a5 3032 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 92:4fc01daae5a5 3033
bogdanm 92:4fc01daae5a5 3034 /****************** Bit definition for EXTI_RTSR register *******************/
bogdanm 92:4fc01daae5a5 3035 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 92:4fc01daae5a5 3036 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 92:4fc01daae5a5 3037 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 92:4fc01daae5a5 3038 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 92:4fc01daae5a5 3039 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 92:4fc01daae5a5 3040 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 92:4fc01daae5a5 3041 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 92:4fc01daae5a5 3042 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 92:4fc01daae5a5 3043 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 92:4fc01daae5a5 3044 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 92:4fc01daae5a5 3045 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 92:4fc01daae5a5 3046 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 92:4fc01daae5a5 3047 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 92:4fc01daae5a5 3048 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 92:4fc01daae5a5 3049 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 92:4fc01daae5a5 3050 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 92:4fc01daae5a5 3051 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 92:4fc01daae5a5 3052 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 92:4fc01daae5a5 3053 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
bogdanm 92:4fc01daae5a5 3054 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 92:4fc01daae5a5 3055
bogdanm 92:4fc01daae5a5 3056 /****************** Bit definition for EXTI_FTSR register *******************/
bogdanm 92:4fc01daae5a5 3057 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 92:4fc01daae5a5 3058 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 92:4fc01daae5a5 3059 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 92:4fc01daae5a5 3060 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 92:4fc01daae5a5 3061 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 92:4fc01daae5a5 3062 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 92:4fc01daae5a5 3063 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 92:4fc01daae5a5 3064 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 92:4fc01daae5a5 3065 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 92:4fc01daae5a5 3066 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 92:4fc01daae5a5 3067 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 92:4fc01daae5a5 3068 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 92:4fc01daae5a5 3069 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 92:4fc01daae5a5 3070 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 92:4fc01daae5a5 3071 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 92:4fc01daae5a5 3072 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 92:4fc01daae5a5 3073 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 92:4fc01daae5a5 3074 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 92:4fc01daae5a5 3075 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
bogdanm 92:4fc01daae5a5 3076 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 92:4fc01daae5a5 3077
bogdanm 92:4fc01daae5a5 3078 /****************** Bit definition for EXTI_SWIER register ******************/
bogdanm 92:4fc01daae5a5 3079 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 92:4fc01daae5a5 3080 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 92:4fc01daae5a5 3081 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 92:4fc01daae5a5 3082 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 92:4fc01daae5a5 3083 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 92:4fc01daae5a5 3084 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 92:4fc01daae5a5 3085 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 92:4fc01daae5a5 3086 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 92:4fc01daae5a5 3087 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 92:4fc01daae5a5 3088 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 92:4fc01daae5a5 3089 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 92:4fc01daae5a5 3090 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 92:4fc01daae5a5 3091 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 92:4fc01daae5a5 3092 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 92:4fc01daae5a5 3093 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 92:4fc01daae5a5 3094 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 92:4fc01daae5a5 3095 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 92:4fc01daae5a5 3096 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 92:4fc01daae5a5 3097 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
bogdanm 92:4fc01daae5a5 3098 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 92:4fc01daae5a5 3099
bogdanm 92:4fc01daae5a5 3100 /******************* Bit definition for EXTI_PR register ********************/
bogdanm 92:4fc01daae5a5 3101 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
bogdanm 92:4fc01daae5a5 3102 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
bogdanm 92:4fc01daae5a5 3103 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
bogdanm 92:4fc01daae5a5 3104 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
bogdanm 92:4fc01daae5a5 3105 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
bogdanm 92:4fc01daae5a5 3106 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
bogdanm 92:4fc01daae5a5 3107 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
bogdanm 92:4fc01daae5a5 3108 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
bogdanm 92:4fc01daae5a5 3109 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
bogdanm 92:4fc01daae5a5 3110 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
bogdanm 92:4fc01daae5a5 3111 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
bogdanm 92:4fc01daae5a5 3112 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
bogdanm 92:4fc01daae5a5 3113 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
bogdanm 92:4fc01daae5a5 3114 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
bogdanm 92:4fc01daae5a5 3115 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
bogdanm 92:4fc01daae5a5 3116 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
bogdanm 92:4fc01daae5a5 3117 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
bogdanm 92:4fc01daae5a5 3118 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
bogdanm 92:4fc01daae5a5 3119 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
bogdanm 92:4fc01daae5a5 3120 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
bogdanm 92:4fc01daae5a5 3121
bogdanm 92:4fc01daae5a5 3122 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3123 /* */
bogdanm 92:4fc01daae5a5 3124 /* FLASH */
bogdanm 92:4fc01daae5a5 3125 /* */
bogdanm 92:4fc01daae5a5 3126 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3127 /******************* Bits definition for FLASH_ACR register *****************/
bogdanm 92:4fc01daae5a5 3128 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
bogdanm 92:4fc01daae5a5 3129 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 3130 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 3131 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 3132 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
bogdanm 92:4fc01daae5a5 3133 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 3134 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
bogdanm 92:4fc01daae5a5 3135 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
bogdanm 92:4fc01daae5a5 3136 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
bogdanm 92:4fc01daae5a5 3137
bogdanm 92:4fc01daae5a5 3138 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 3139 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 3140 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 3141 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 3142 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 3143 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
bogdanm 92:4fc01daae5a5 3144 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
bogdanm 92:4fc01daae5a5 3145
bogdanm 92:4fc01daae5a5 3146 /******************* Bits definition for FLASH_SR register ******************/
bogdanm 92:4fc01daae5a5 3147 #define FLASH_SR_EOP ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 3148 #define FLASH_SR_SOP ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 3149 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 3150 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 3151 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 3152 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 3153 #define FLASH_SR_BSY ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 3154
bogdanm 92:4fc01daae5a5 3155 /******************* Bits definition for FLASH_CR register ******************/
bogdanm 92:4fc01daae5a5 3156 #define FLASH_CR_PG ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 3157 #define FLASH_CR_SER ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 3158 #define FLASH_CR_MER ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 3159 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
bogdanm 92:4fc01daae5a5 3160 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 3161 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 3162 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 3163 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 3164 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 3165 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
bogdanm 92:4fc01daae5a5 3166 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 3167 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 3168 #define FLASH_CR_STRT ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 3169 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 3170 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 3171
bogdanm 92:4fc01daae5a5 3172 /******************* Bits definition for FLASH_OPTCR register ***************/
bogdanm 92:4fc01daae5a5 3173 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 3174 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 3175 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 3176 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 3177 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
bogdanm 92:4fc01daae5a5 3178
bogdanm 92:4fc01daae5a5 3179 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 3180 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 3181 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 3182 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
bogdanm 92:4fc01daae5a5 3183 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 3184 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 3185 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 3186 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 3187 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 3188 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 3189 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 3190 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 3191 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
bogdanm 92:4fc01daae5a5 3192 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 3193 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 3194 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 3195 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 3196 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 3197 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 3198 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 3199 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 3200 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 3201 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 3202 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 3203 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 3204
bogdanm 92:4fc01daae5a5 3205 /****************** Bits definition for FLASH_OPTCR1 register ***************/
bogdanm 92:4fc01daae5a5 3206 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
bogdanm 92:4fc01daae5a5 3207 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 3208 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 3209 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 3210 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 3211 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 3212 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 3213 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 3214 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 3215 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 3216 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 3217 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 3218 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 3219
bogdanm 92:4fc01daae5a5 3220 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3221 /* */
bogdanm 92:4fc01daae5a5 3222 /* Flexible Static Memory Controller */
bogdanm 92:4fc01daae5a5 3223 /* */
bogdanm 92:4fc01daae5a5 3224 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3225 /****************** Bit definition for FSMC_BCR1 register *******************/
bogdanm 92:4fc01daae5a5 3226 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 92:4fc01daae5a5 3227 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 92:4fc01daae5a5 3228
bogdanm 92:4fc01daae5a5 3229 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 92:4fc01daae5a5 3230 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3231 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3232
bogdanm 92:4fc01daae5a5 3233 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 92:4fc01daae5a5 3234 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3235 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3236
bogdanm 92:4fc01daae5a5 3237 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 92:4fc01daae5a5 3238 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 92:4fc01daae5a5 3239 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 92:4fc01daae5a5 3240 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 92:4fc01daae5a5 3241 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 92:4fc01daae5a5 3242 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 92:4fc01daae5a5 3243 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 92:4fc01daae5a5 3244 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 92:4fc01daae5a5 3245 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 92:4fc01daae5a5 3246 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 92:4fc01daae5a5 3247
bogdanm 92:4fc01daae5a5 3248 /****************** Bit definition for FSMC_BCR2 register *******************/
bogdanm 92:4fc01daae5a5 3249 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 92:4fc01daae5a5 3250 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 92:4fc01daae5a5 3251
bogdanm 92:4fc01daae5a5 3252 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 92:4fc01daae5a5 3253 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3254 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3255
bogdanm 92:4fc01daae5a5 3256 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 92:4fc01daae5a5 3257 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3258 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3259
bogdanm 92:4fc01daae5a5 3260 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 92:4fc01daae5a5 3261 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 92:4fc01daae5a5 3262 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 92:4fc01daae5a5 3263 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 92:4fc01daae5a5 3264 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 92:4fc01daae5a5 3265 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 92:4fc01daae5a5 3266 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 92:4fc01daae5a5 3267 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 92:4fc01daae5a5 3268 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 92:4fc01daae5a5 3269 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 92:4fc01daae5a5 3270
bogdanm 92:4fc01daae5a5 3271 /****************** Bit definition for FSMC_BCR3 register *******************/
bogdanm 92:4fc01daae5a5 3272 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 92:4fc01daae5a5 3273 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 92:4fc01daae5a5 3274
bogdanm 92:4fc01daae5a5 3275 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 92:4fc01daae5a5 3276 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3277 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3278
bogdanm 92:4fc01daae5a5 3279 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 92:4fc01daae5a5 3280 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3281 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3282
bogdanm 92:4fc01daae5a5 3283 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 92:4fc01daae5a5 3284 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 92:4fc01daae5a5 3285 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 92:4fc01daae5a5 3286 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 92:4fc01daae5a5 3287 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 92:4fc01daae5a5 3288 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 92:4fc01daae5a5 3289 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 92:4fc01daae5a5 3290 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 92:4fc01daae5a5 3291 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 92:4fc01daae5a5 3292 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 92:4fc01daae5a5 3293
bogdanm 92:4fc01daae5a5 3294 /****************** Bit definition for FSMC_BCR4 register *******************/
bogdanm 92:4fc01daae5a5 3295 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 92:4fc01daae5a5 3296 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 92:4fc01daae5a5 3297
bogdanm 92:4fc01daae5a5 3298 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 92:4fc01daae5a5 3299 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3300 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3301
bogdanm 92:4fc01daae5a5 3302 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 92:4fc01daae5a5 3303 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3304 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3305
bogdanm 92:4fc01daae5a5 3306 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 92:4fc01daae5a5 3307 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 92:4fc01daae5a5 3308 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 92:4fc01daae5a5 3309 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 92:4fc01daae5a5 3310 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 92:4fc01daae5a5 3311 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 92:4fc01daae5a5 3312 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 92:4fc01daae5a5 3313 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 92:4fc01daae5a5 3314 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 92:4fc01daae5a5 3315 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 92:4fc01daae5a5 3316
bogdanm 92:4fc01daae5a5 3317 /****************** Bit definition for FSMC_BTR1 register ******************/
bogdanm 92:4fc01daae5a5 3318 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 92:4fc01daae5a5 3319 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3320 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3321 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3322 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3323
bogdanm 92:4fc01daae5a5 3324 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 92:4fc01daae5a5 3325 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3326 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3327 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3328 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3329
bogdanm 92:4fc01daae5a5 3330 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 92:4fc01daae5a5 3331 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3332 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3333 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3334 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3335
bogdanm 92:4fc01daae5a5 3336 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 92:4fc01daae5a5 3337 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3338 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3339 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3340 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3341
bogdanm 92:4fc01daae5a5 3342 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 92:4fc01daae5a5 3343 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3344 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3345 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3346 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3347
bogdanm 92:4fc01daae5a5 3348 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 92:4fc01daae5a5 3349 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3350 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3351 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3352 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3353
bogdanm 92:4fc01daae5a5 3354 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 92:4fc01daae5a5 3355 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3356 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3357
bogdanm 92:4fc01daae5a5 3358 /****************** Bit definition for FSMC_BTR2 register *******************/
bogdanm 92:4fc01daae5a5 3359 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 92:4fc01daae5a5 3360 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3361 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3362 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3363 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3364
bogdanm 92:4fc01daae5a5 3365 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 92:4fc01daae5a5 3366 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3367 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3368 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3369 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3370
bogdanm 92:4fc01daae5a5 3371 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 92:4fc01daae5a5 3372 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3373 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3374 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3375 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3376
bogdanm 92:4fc01daae5a5 3377 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 92:4fc01daae5a5 3378 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3379 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3380 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3381 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3382
bogdanm 92:4fc01daae5a5 3383 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 92:4fc01daae5a5 3384 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3385 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3386 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3387 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3388
bogdanm 92:4fc01daae5a5 3389 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 92:4fc01daae5a5 3390 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3391 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3392 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3393 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3394
bogdanm 92:4fc01daae5a5 3395 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 92:4fc01daae5a5 3396 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3397 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3398
bogdanm 92:4fc01daae5a5 3399 /******************* Bit definition for FSMC_BTR3 register *******************/
bogdanm 92:4fc01daae5a5 3400 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 92:4fc01daae5a5 3401 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3402 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3403 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3404 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3405
bogdanm 92:4fc01daae5a5 3406 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 92:4fc01daae5a5 3407 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3408 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3409 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3410 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3411
bogdanm 92:4fc01daae5a5 3412 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 92:4fc01daae5a5 3413 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3414 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3415 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3416 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3417
bogdanm 92:4fc01daae5a5 3418 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 92:4fc01daae5a5 3419 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3420 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3421 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3422 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3423
bogdanm 92:4fc01daae5a5 3424 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 92:4fc01daae5a5 3425 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3426 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3427 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3428 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3429
bogdanm 92:4fc01daae5a5 3430 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 92:4fc01daae5a5 3431 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3432 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3433 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3434 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3435
bogdanm 92:4fc01daae5a5 3436 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 92:4fc01daae5a5 3437 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3438 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3439
bogdanm 92:4fc01daae5a5 3440 /****************** Bit definition for FSMC_BTR4 register *******************/
bogdanm 92:4fc01daae5a5 3441 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 92:4fc01daae5a5 3442 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3443 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3444 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3445 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3446
bogdanm 92:4fc01daae5a5 3447 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 92:4fc01daae5a5 3448 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3449 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3450 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3451 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3452
bogdanm 92:4fc01daae5a5 3453 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 92:4fc01daae5a5 3454 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3455 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3456 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3457 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3458
bogdanm 92:4fc01daae5a5 3459 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 92:4fc01daae5a5 3460 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3461 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3462 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3463 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3464
bogdanm 92:4fc01daae5a5 3465 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 92:4fc01daae5a5 3466 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3467 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3468 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3469 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3470
bogdanm 92:4fc01daae5a5 3471 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 92:4fc01daae5a5 3472 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3473 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3474 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3475 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3476
bogdanm 92:4fc01daae5a5 3477 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 92:4fc01daae5a5 3478 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3479 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3480
bogdanm 92:4fc01daae5a5 3481 /****************** Bit definition for FSMC_BWTR1 register ******************/
bogdanm 92:4fc01daae5a5 3482 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 92:4fc01daae5a5 3483 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3484 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3485 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3486 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3487
bogdanm 92:4fc01daae5a5 3488 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 92:4fc01daae5a5 3489 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3490 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3491 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3492 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3493
bogdanm 92:4fc01daae5a5 3494 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 92:4fc01daae5a5 3495 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3496 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3497 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3498 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3499
bogdanm 92:4fc01daae5a5 3500 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 92:4fc01daae5a5 3501 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3502 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3503 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3504 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3505
bogdanm 92:4fc01daae5a5 3506 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 92:4fc01daae5a5 3507 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3508 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3509 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3510 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3511
bogdanm 92:4fc01daae5a5 3512 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 92:4fc01daae5a5 3513 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3514 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3515
bogdanm 92:4fc01daae5a5 3516 /****************** Bit definition for FSMC_BWTR2 register ******************/
bogdanm 92:4fc01daae5a5 3517 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 92:4fc01daae5a5 3518 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3519 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3520 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3521 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3522
bogdanm 92:4fc01daae5a5 3523 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 92:4fc01daae5a5 3524 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3525 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3526 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3527 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3528
bogdanm 92:4fc01daae5a5 3529 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 92:4fc01daae5a5 3530 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3531 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3532 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3533 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3534
bogdanm 92:4fc01daae5a5 3535 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 92:4fc01daae5a5 3536 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3537 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
bogdanm 92:4fc01daae5a5 3538 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3539 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3540
bogdanm 92:4fc01daae5a5 3541 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 92:4fc01daae5a5 3542 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3543 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3544 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3545 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3546
bogdanm 92:4fc01daae5a5 3547 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 92:4fc01daae5a5 3548 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3549 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3550
bogdanm 92:4fc01daae5a5 3551 /****************** Bit definition for FSMC_BWTR3 register ******************/
bogdanm 92:4fc01daae5a5 3552 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 92:4fc01daae5a5 3553 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3554 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3555 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3556 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3557
bogdanm 92:4fc01daae5a5 3558 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 92:4fc01daae5a5 3559 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3560 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3561 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3562 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3563
bogdanm 92:4fc01daae5a5 3564 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 92:4fc01daae5a5 3565 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3566 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3567 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3568 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3569
bogdanm 92:4fc01daae5a5 3570 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 92:4fc01daae5a5 3571 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3572 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3573 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3574 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3575
bogdanm 92:4fc01daae5a5 3576 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 92:4fc01daae5a5 3577 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3578 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3579 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3580 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3581
bogdanm 92:4fc01daae5a5 3582 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 92:4fc01daae5a5 3583 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3584 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3585
bogdanm 92:4fc01daae5a5 3586 /****************** Bit definition for FSMC_BWTR4 register ******************/
bogdanm 92:4fc01daae5a5 3587 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 92:4fc01daae5a5 3588 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3589 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3590 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3591 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3592
bogdanm 92:4fc01daae5a5 3593 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 92:4fc01daae5a5 3594 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3595 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3596 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3597 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3598
bogdanm 92:4fc01daae5a5 3599 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 92:4fc01daae5a5 3600 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3601 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3602 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3603 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3604
bogdanm 92:4fc01daae5a5 3605 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 92:4fc01daae5a5 3606 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3607 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3608 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3609 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3610
bogdanm 92:4fc01daae5a5 3611 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 92:4fc01daae5a5 3612 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3613 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3614 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3615 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3616
bogdanm 92:4fc01daae5a5 3617 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 92:4fc01daae5a5 3618 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3619 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3620
bogdanm 92:4fc01daae5a5 3621 /****************** Bit definition for FSMC_PCR2 register *******************/
bogdanm 92:4fc01daae5a5 3622 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 92:4fc01daae5a5 3623 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 92:4fc01daae5a5 3624 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 92:4fc01daae5a5 3625
bogdanm 92:4fc01daae5a5 3626 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 92:4fc01daae5a5 3627 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3628 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3629
bogdanm 92:4fc01daae5a5 3630 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 92:4fc01daae5a5 3631
bogdanm 92:4fc01daae5a5 3632 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 92:4fc01daae5a5 3633 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3634 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3635 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3636 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3637
bogdanm 92:4fc01daae5a5 3638 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 92:4fc01daae5a5 3639 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3640 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3641 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3642 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3643
bogdanm 92:4fc01daae5a5 3644 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
bogdanm 92:4fc01daae5a5 3645 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3646 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3647 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3648
bogdanm 92:4fc01daae5a5 3649 /****************** Bit definition for FSMC_PCR3 register *******************/
bogdanm 92:4fc01daae5a5 3650 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 92:4fc01daae5a5 3651 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 92:4fc01daae5a5 3652 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 92:4fc01daae5a5 3653
bogdanm 92:4fc01daae5a5 3654 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 92:4fc01daae5a5 3655 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3656 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3657
bogdanm 92:4fc01daae5a5 3658 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 92:4fc01daae5a5 3659
bogdanm 92:4fc01daae5a5 3660 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 92:4fc01daae5a5 3661 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3662 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3663 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3664 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3665
bogdanm 92:4fc01daae5a5 3666 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 92:4fc01daae5a5 3667 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3668 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3669 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3670 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3671
bogdanm 92:4fc01daae5a5 3672 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
bogdanm 92:4fc01daae5a5 3673 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3674 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3675 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3676
bogdanm 92:4fc01daae5a5 3677 /****************** Bit definition for FSMC_PCR4 register *******************/
bogdanm 92:4fc01daae5a5 3678 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 92:4fc01daae5a5 3679 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 92:4fc01daae5a5 3680 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 92:4fc01daae5a5 3681
bogdanm 92:4fc01daae5a5 3682 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 92:4fc01daae5a5 3683 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3684 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3685
bogdanm 92:4fc01daae5a5 3686 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 92:4fc01daae5a5 3687
bogdanm 92:4fc01daae5a5 3688 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 92:4fc01daae5a5 3689 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3690 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3691 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3692 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3693
bogdanm 92:4fc01daae5a5 3694 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 92:4fc01daae5a5 3695 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3696 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3697 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3698 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3699
bogdanm 92:4fc01daae5a5 3700 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
bogdanm 92:4fc01daae5a5 3701 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3702 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3703 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3704
bogdanm 92:4fc01daae5a5 3705 /******************* Bit definition for FSMC_SR2 register *******************/
bogdanm 92:4fc01daae5a5 3706 #define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 92:4fc01daae5a5 3707 #define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
bogdanm 92:4fc01daae5a5 3708 #define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 92:4fc01daae5a5 3709 #define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 92:4fc01daae5a5 3710 #define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 92:4fc01daae5a5 3711 #define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 92:4fc01daae5a5 3712 #define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
bogdanm 92:4fc01daae5a5 3713
bogdanm 92:4fc01daae5a5 3714 /******************* Bit definition for FSMC_SR3 register *******************/
bogdanm 92:4fc01daae5a5 3715 #define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 92:4fc01daae5a5 3716 #define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
bogdanm 92:4fc01daae5a5 3717 #define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 92:4fc01daae5a5 3718 #define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 92:4fc01daae5a5 3719 #define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 92:4fc01daae5a5 3720 #define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 92:4fc01daae5a5 3721 #define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
bogdanm 92:4fc01daae5a5 3722
bogdanm 92:4fc01daae5a5 3723 /******************* Bit definition for FSMC_SR4 register *******************/
bogdanm 92:4fc01daae5a5 3724 #define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 92:4fc01daae5a5 3725 #define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
bogdanm 92:4fc01daae5a5 3726 #define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 92:4fc01daae5a5 3727 #define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 92:4fc01daae5a5 3728 #define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 92:4fc01daae5a5 3729 #define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 92:4fc01daae5a5 3730 #define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
bogdanm 92:4fc01daae5a5 3731
bogdanm 92:4fc01daae5a5 3732 /****************** Bit definition for FSMC_PMEM2 register ******************/
bogdanm 92:4fc01daae5a5 3733 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
bogdanm 92:4fc01daae5a5 3734 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3735 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3736 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3737 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3738 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3739 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3740 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3741 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3742
bogdanm 92:4fc01daae5a5 3743 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
bogdanm 92:4fc01daae5a5 3744 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3745 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3746 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3747 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3748 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3749 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3750 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3751 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3752
bogdanm 92:4fc01daae5a5 3753 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
bogdanm 92:4fc01daae5a5 3754 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3755 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3756 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3757 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3758 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3759 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3760 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3761 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3762
bogdanm 92:4fc01daae5a5 3763 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
bogdanm 92:4fc01daae5a5 3764 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3765 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3766 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3767 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3768 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3769 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3770 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3771 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3772
bogdanm 92:4fc01daae5a5 3773 /****************** Bit definition for FSMC_PMEM3 register ******************/
bogdanm 92:4fc01daae5a5 3774 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
bogdanm 92:4fc01daae5a5 3775 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3776 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3777 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3778 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3779 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3780 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3781 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3782 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3783
bogdanm 92:4fc01daae5a5 3784 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
bogdanm 92:4fc01daae5a5 3785 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3786 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3787 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3788 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3789 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3790 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3791 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3792 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3793
bogdanm 92:4fc01daae5a5 3794 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
bogdanm 92:4fc01daae5a5 3795 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3796 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3797 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3798 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3799 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3800 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3801 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3802 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3803
bogdanm 92:4fc01daae5a5 3804 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
bogdanm 92:4fc01daae5a5 3805 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3806 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3807 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3808 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3809 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3810 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3811 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3812 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3813
bogdanm 92:4fc01daae5a5 3814 /****************** Bit definition for FSMC_PMEM4 register ******************/
bogdanm 92:4fc01daae5a5 3815 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
bogdanm 92:4fc01daae5a5 3816 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3817 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3818 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3819 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3820 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3821 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3822 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3823 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3824
bogdanm 92:4fc01daae5a5 3825 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
bogdanm 92:4fc01daae5a5 3826 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3827 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3828 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3829 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3830 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3831 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3832 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3833 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3834
bogdanm 92:4fc01daae5a5 3835 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
bogdanm 92:4fc01daae5a5 3836 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3837 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3838 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3839 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3840 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3841 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3842 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3843 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3844
bogdanm 92:4fc01daae5a5 3845 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
bogdanm 92:4fc01daae5a5 3846 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3847 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3848 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3849 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3850 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3851 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3852 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3853 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3854
bogdanm 92:4fc01daae5a5 3855 /****************** Bit definition for FSMC_PATT2 register ******************/
bogdanm 92:4fc01daae5a5 3856 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
bogdanm 92:4fc01daae5a5 3857 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3858 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3859 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3860 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3861 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3862 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3863 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3864 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3865
bogdanm 92:4fc01daae5a5 3866 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
bogdanm 92:4fc01daae5a5 3867 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3868 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3869 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3870 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3871 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3872 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3873 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3874 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3875
bogdanm 92:4fc01daae5a5 3876 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
bogdanm 92:4fc01daae5a5 3877 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3878 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3879 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3880 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3881 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3882 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3883 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3884 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3885
bogdanm 92:4fc01daae5a5 3886 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
bogdanm 92:4fc01daae5a5 3887 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3888 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3889 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3890 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3891 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3892 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3893 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3894 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3895
bogdanm 92:4fc01daae5a5 3896 /****************** Bit definition for FSMC_PATT3 register ******************/
bogdanm 92:4fc01daae5a5 3897 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
bogdanm 92:4fc01daae5a5 3898 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3899 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3900 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3901 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3902 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3903 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3904 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3905 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3906
bogdanm 92:4fc01daae5a5 3907 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
bogdanm 92:4fc01daae5a5 3908 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3909 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3910 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3911 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3912 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3913 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3914 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3915 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3916
bogdanm 92:4fc01daae5a5 3917 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
bogdanm 92:4fc01daae5a5 3918 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3919 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3920 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3921 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3922 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3923 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3924 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3925 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3926
bogdanm 92:4fc01daae5a5 3927 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
bogdanm 92:4fc01daae5a5 3928 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3929 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3930 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3931 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3932 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3933 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3934 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3935 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3936
bogdanm 92:4fc01daae5a5 3937 /****************** Bit definition for FSMC_PATT4 register ******************/
bogdanm 92:4fc01daae5a5 3938 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
bogdanm 92:4fc01daae5a5 3939 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3940 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3941 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3942 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3943 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3944 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3945 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3946 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3947
bogdanm 92:4fc01daae5a5 3948 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
bogdanm 92:4fc01daae5a5 3949 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3950 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3951 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3952 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3953 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3954 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3955 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3956 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3957
bogdanm 92:4fc01daae5a5 3958 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
bogdanm 92:4fc01daae5a5 3959 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3960 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3961 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3962 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3963 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3964 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3965 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3966 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3967
bogdanm 92:4fc01daae5a5 3968 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
bogdanm 92:4fc01daae5a5 3969 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3970 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3971 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3972 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3973 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3974 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3975 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3976 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3977
bogdanm 92:4fc01daae5a5 3978 /****************** Bit definition for FSMC_PIO4 register *******************/
bogdanm 92:4fc01daae5a5 3979 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
bogdanm 92:4fc01daae5a5 3980 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3981 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3982 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3983 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3984 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3985 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3986 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3987 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3988
bogdanm 92:4fc01daae5a5 3989 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
bogdanm 92:4fc01daae5a5 3990 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 3991 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3992 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3993 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 3994 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 3995 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 3996 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 3997 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3998
bogdanm 92:4fc01daae5a5 3999 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
bogdanm 92:4fc01daae5a5 4000 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 4001 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 4002 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 4003 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 4004 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 4005 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 4006 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 4007 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 4008
bogdanm 92:4fc01daae5a5 4009 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
bogdanm 92:4fc01daae5a5 4010 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 4011 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 4012 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 4013 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 4014 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 4015 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 4016 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 4017 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 4018
bogdanm 92:4fc01daae5a5 4019 /****************** Bit definition for FSMC_ECCR2 register ******************/
bogdanm 92:4fc01daae5a5 4020 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
bogdanm 92:4fc01daae5a5 4021
bogdanm 92:4fc01daae5a5 4022 /****************** Bit definition for FSMC_ECCR3 register ******************/
bogdanm 92:4fc01daae5a5 4023 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
bogdanm 92:4fc01daae5a5 4024
bogdanm 92:4fc01daae5a5 4025 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4026 /* */
bogdanm 92:4fc01daae5a5 4027 /* General Purpose I/O */
bogdanm 92:4fc01daae5a5 4028 /* */
bogdanm 92:4fc01daae5a5 4029 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4030 /****************** Bits definition for GPIO_MODER register *****************/
bogdanm 92:4fc01daae5a5 4031 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm 92:4fc01daae5a5 4032 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4033 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4034
bogdanm 92:4fc01daae5a5 4035 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm 92:4fc01daae5a5 4036 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4037 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4038
bogdanm 92:4fc01daae5a5 4039 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 4040 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4041 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4042
bogdanm 92:4fc01daae5a5 4043 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm 92:4fc01daae5a5 4044 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4045 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4046
bogdanm 92:4fc01daae5a5 4047 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm 92:4fc01daae5a5 4048 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4049 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4050
bogdanm 92:4fc01daae5a5 4051 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm 92:4fc01daae5a5 4052 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4053 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4054
bogdanm 92:4fc01daae5a5 4055 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm 92:4fc01daae5a5 4056 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4057 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4058
bogdanm 92:4fc01daae5a5 4059 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm 92:4fc01daae5a5 4060 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4061 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4062
bogdanm 92:4fc01daae5a5 4063 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm 92:4fc01daae5a5 4064 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4065 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4066
bogdanm 92:4fc01daae5a5 4067 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm 92:4fc01daae5a5 4068 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4069 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4070
bogdanm 92:4fc01daae5a5 4071 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm 92:4fc01daae5a5 4072 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4073 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4074
bogdanm 92:4fc01daae5a5 4075 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm 92:4fc01daae5a5 4076 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4077 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4078
bogdanm 92:4fc01daae5a5 4079 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm 92:4fc01daae5a5 4080 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 4081 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4082
bogdanm 92:4fc01daae5a5 4083 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm 92:4fc01daae5a5 4084 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4085 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 4086
bogdanm 92:4fc01daae5a5 4087 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm 92:4fc01daae5a5 4088 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4089 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4090
bogdanm 92:4fc01daae5a5 4091 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm 92:4fc01daae5a5 4092 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4093 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 4094
bogdanm 92:4fc01daae5a5 4095 /****************** Bits definition for GPIO_OTYPER register ****************/
bogdanm 92:4fc01daae5a5 4096 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4097 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4098 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4099 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4100 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4101 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4102 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4103 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4104 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4105 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4106 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4107 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4108 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4109 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4110 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4111 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4112
bogdanm 92:4fc01daae5a5 4113 /****************** Bits definition for GPIO_OSPEEDR register ***************/
bogdanm 92:4fc01daae5a5 4114 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm 92:4fc01daae5a5 4115 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4116 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4117
bogdanm 92:4fc01daae5a5 4118 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm 92:4fc01daae5a5 4119 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4120 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4121
bogdanm 92:4fc01daae5a5 4122 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 4123 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4124 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4125
bogdanm 92:4fc01daae5a5 4126 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm 92:4fc01daae5a5 4127 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4128 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4129
bogdanm 92:4fc01daae5a5 4130 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm 92:4fc01daae5a5 4131 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4132 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4133
bogdanm 92:4fc01daae5a5 4134 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm 92:4fc01daae5a5 4135 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4136 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4137
bogdanm 92:4fc01daae5a5 4138 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm 92:4fc01daae5a5 4139 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4140 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4141
bogdanm 92:4fc01daae5a5 4142 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm 92:4fc01daae5a5 4143 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4144 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4145
bogdanm 92:4fc01daae5a5 4146 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm 92:4fc01daae5a5 4147 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4148 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4149
bogdanm 92:4fc01daae5a5 4150 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm 92:4fc01daae5a5 4151 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4152 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4153
bogdanm 92:4fc01daae5a5 4154 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm 92:4fc01daae5a5 4155 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4156 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4157
bogdanm 92:4fc01daae5a5 4158 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm 92:4fc01daae5a5 4159 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4160 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4161
bogdanm 92:4fc01daae5a5 4162 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm 92:4fc01daae5a5 4163 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 4164 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4165
bogdanm 92:4fc01daae5a5 4166 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm 92:4fc01daae5a5 4167 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4168 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 4169
bogdanm 92:4fc01daae5a5 4170 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm 92:4fc01daae5a5 4171 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4172 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4173
bogdanm 92:4fc01daae5a5 4174 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm 92:4fc01daae5a5 4175 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4176 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 4177
bogdanm 92:4fc01daae5a5 4178 /****************** Bits definition for GPIO_PUPDR register *****************/
bogdanm 92:4fc01daae5a5 4179 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm 92:4fc01daae5a5 4180 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4181 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4182
bogdanm 92:4fc01daae5a5 4183 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm 92:4fc01daae5a5 4184 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4185 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4186
bogdanm 92:4fc01daae5a5 4187 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 4188 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4189 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4190
bogdanm 92:4fc01daae5a5 4191 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm 92:4fc01daae5a5 4192 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4193 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4194
bogdanm 92:4fc01daae5a5 4195 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm 92:4fc01daae5a5 4196 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4197 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4198
bogdanm 92:4fc01daae5a5 4199 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm 92:4fc01daae5a5 4200 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4201 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4202
bogdanm 92:4fc01daae5a5 4203 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm 92:4fc01daae5a5 4204 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4205 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4206
bogdanm 92:4fc01daae5a5 4207 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm 92:4fc01daae5a5 4208 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4209 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4210
bogdanm 92:4fc01daae5a5 4211 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm 92:4fc01daae5a5 4212 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4213 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4214
bogdanm 92:4fc01daae5a5 4215 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm 92:4fc01daae5a5 4216 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4217 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4218
bogdanm 92:4fc01daae5a5 4219 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm 92:4fc01daae5a5 4220 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4221 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4222
bogdanm 92:4fc01daae5a5 4223 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm 92:4fc01daae5a5 4224 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4225 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4226
bogdanm 92:4fc01daae5a5 4227 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm 92:4fc01daae5a5 4228 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 4229 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4230
bogdanm 92:4fc01daae5a5 4231 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm 92:4fc01daae5a5 4232 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4233 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 4234
bogdanm 92:4fc01daae5a5 4235 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm 92:4fc01daae5a5 4236 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4237 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4238
bogdanm 92:4fc01daae5a5 4239 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm 92:4fc01daae5a5 4240 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4241 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 4242
bogdanm 92:4fc01daae5a5 4243 /****************** Bits definition for GPIO_IDR register *******************/
bogdanm 92:4fc01daae5a5 4244 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4245 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4246 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4247 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4248 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4249 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4250 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4251 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4252 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4253 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4254 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4255 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4256 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4257 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4258 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4259 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4260 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 4261 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
bogdanm 92:4fc01daae5a5 4262 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
bogdanm 92:4fc01daae5a5 4263 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
bogdanm 92:4fc01daae5a5 4264 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
bogdanm 92:4fc01daae5a5 4265 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
bogdanm 92:4fc01daae5a5 4266 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
bogdanm 92:4fc01daae5a5 4267 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
bogdanm 92:4fc01daae5a5 4268 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
bogdanm 92:4fc01daae5a5 4269 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
bogdanm 92:4fc01daae5a5 4270 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
bogdanm 92:4fc01daae5a5 4271 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
bogdanm 92:4fc01daae5a5 4272 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
bogdanm 92:4fc01daae5a5 4273 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
bogdanm 92:4fc01daae5a5 4274 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
bogdanm 92:4fc01daae5a5 4275 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
bogdanm 92:4fc01daae5a5 4276 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
bogdanm 92:4fc01daae5a5 4277
bogdanm 92:4fc01daae5a5 4278 /****************** Bits definition for GPIO_ODR register *******************/
bogdanm 92:4fc01daae5a5 4279 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4280 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4281 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4282 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4283 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4284 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4285 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4286 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4287 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4288 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4289 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4290 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4291 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4292 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4293 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4294 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4295 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 4296 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
bogdanm 92:4fc01daae5a5 4297 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
bogdanm 92:4fc01daae5a5 4298 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
bogdanm 92:4fc01daae5a5 4299 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
bogdanm 92:4fc01daae5a5 4300 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
bogdanm 92:4fc01daae5a5 4301 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
bogdanm 92:4fc01daae5a5 4302 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
bogdanm 92:4fc01daae5a5 4303 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
bogdanm 92:4fc01daae5a5 4304 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
bogdanm 92:4fc01daae5a5 4305 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
bogdanm 92:4fc01daae5a5 4306 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
bogdanm 92:4fc01daae5a5 4307 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
bogdanm 92:4fc01daae5a5 4308 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
bogdanm 92:4fc01daae5a5 4309 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
bogdanm 92:4fc01daae5a5 4310 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
bogdanm 92:4fc01daae5a5 4311 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
bogdanm 92:4fc01daae5a5 4312
bogdanm 92:4fc01daae5a5 4313 /****************** Bits definition for GPIO_BSRR register ******************/
bogdanm 92:4fc01daae5a5 4314 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4315 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4316 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4317 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4318 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4319 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4320 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4321 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4322 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4323 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4324 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4325 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4326 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4327 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4328 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4329 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4330 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4331 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4332 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4333 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4334 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4335 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4336 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4337 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4338 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 4339 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4340 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4341 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 4342 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4343 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4344 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4345 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 4346
bogdanm 92:4fc01daae5a5 4347 /****************** Bit definition for GPIO_LCKR register *********************/
bogdanm 92:4fc01daae5a5 4348 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4349 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4350 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4351 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4352 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4353 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4354 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4355 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4356 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4357 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4358 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4359 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4360 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4361 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4362 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4363 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4364 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4365
bogdanm 92:4fc01daae5a5 4366 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4367 /* */
bogdanm 92:4fc01daae5a5 4368 /* Inter-integrated Circuit Interface */
bogdanm 92:4fc01daae5a5 4369 /* */
bogdanm 92:4fc01daae5a5 4370 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4371 /******************* Bit definition for I2C_CR1 register ********************/
bogdanm 92:4fc01daae5a5 4372 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
bogdanm 92:4fc01daae5a5 4373 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
bogdanm 92:4fc01daae5a5 4374 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
bogdanm 92:4fc01daae5a5 4375 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
bogdanm 92:4fc01daae5a5 4376 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
bogdanm 92:4fc01daae5a5 4377 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
bogdanm 92:4fc01daae5a5 4378 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
bogdanm 92:4fc01daae5a5 4379 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
bogdanm 92:4fc01daae5a5 4380 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
bogdanm 92:4fc01daae5a5 4381 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
bogdanm 92:4fc01daae5a5 4382 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
bogdanm 92:4fc01daae5a5 4383 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
bogdanm 92:4fc01daae5a5 4384 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
bogdanm 92:4fc01daae5a5 4385 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
bogdanm 92:4fc01daae5a5 4386
bogdanm 92:4fc01daae5a5 4387 /******************* Bit definition for I2C_CR2 register ********************/
bogdanm 92:4fc01daae5a5 4388 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
bogdanm 92:4fc01daae5a5 4389 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 4390 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 4391 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 4392 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 4393 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 4394 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 4395
bogdanm 92:4fc01daae5a5 4396 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
bogdanm 92:4fc01daae5a5 4397 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
bogdanm 92:4fc01daae5a5 4398 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
bogdanm 92:4fc01daae5a5 4399 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
bogdanm 92:4fc01daae5a5 4400 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
bogdanm 92:4fc01daae5a5 4401
bogdanm 92:4fc01daae5a5 4402 /******************* Bit definition for I2C_OAR1 register *******************/
bogdanm 92:4fc01daae5a5 4403 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
bogdanm 92:4fc01daae5a5 4404 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
bogdanm 92:4fc01daae5a5 4405
bogdanm 92:4fc01daae5a5 4406 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 4407 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 4408 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 4409 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 4410 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 4411 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 4412 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 4413 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 4414 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
bogdanm 92:4fc01daae5a5 4415 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
bogdanm 92:4fc01daae5a5 4416
bogdanm 92:4fc01daae5a5 4417 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
bogdanm 92:4fc01daae5a5 4418
bogdanm 92:4fc01daae5a5 4419 /******************* Bit definition for I2C_OAR2 register *******************/
bogdanm 92:4fc01daae5a5 4420 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
bogdanm 92:4fc01daae5a5 4421 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
bogdanm 92:4fc01daae5a5 4422
bogdanm 92:4fc01daae5a5 4423 /******************** Bit definition for I2C_DR register ********************/
bogdanm 92:4fc01daae5a5 4424 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
bogdanm 92:4fc01daae5a5 4425
bogdanm 92:4fc01daae5a5 4426 /******************* Bit definition for I2C_SR1 register ********************/
bogdanm 92:4fc01daae5a5 4427 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
bogdanm 92:4fc01daae5a5 4428 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
bogdanm 92:4fc01daae5a5 4429 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
bogdanm 92:4fc01daae5a5 4430 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
bogdanm 92:4fc01daae5a5 4431 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
bogdanm 92:4fc01daae5a5 4432 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
bogdanm 92:4fc01daae5a5 4433 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
bogdanm 92:4fc01daae5a5 4434 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
bogdanm 92:4fc01daae5a5 4435 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
bogdanm 92:4fc01daae5a5 4436 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
bogdanm 92:4fc01daae5a5 4437 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
bogdanm 92:4fc01daae5a5 4438 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
bogdanm 92:4fc01daae5a5 4439 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
bogdanm 92:4fc01daae5a5 4440 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
bogdanm 92:4fc01daae5a5 4441
bogdanm 92:4fc01daae5a5 4442 /******************* Bit definition for I2C_SR2 register ********************/
bogdanm 92:4fc01daae5a5 4443 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
bogdanm 92:4fc01daae5a5 4444 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
bogdanm 92:4fc01daae5a5 4445 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
bogdanm 92:4fc01daae5a5 4446 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
bogdanm 92:4fc01daae5a5 4447 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
bogdanm 92:4fc01daae5a5 4448 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
bogdanm 92:4fc01daae5a5 4449 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
bogdanm 92:4fc01daae5a5 4450 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
bogdanm 92:4fc01daae5a5 4451
bogdanm 92:4fc01daae5a5 4452 /******************* Bit definition for I2C_CCR register ********************/
bogdanm 92:4fc01daae5a5 4453 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
bogdanm 92:4fc01daae5a5 4454 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
bogdanm 92:4fc01daae5a5 4455 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
bogdanm 92:4fc01daae5a5 4456
bogdanm 92:4fc01daae5a5 4457 /****************** Bit definition for I2C_TRISE register *******************/
bogdanm 92:4fc01daae5a5 4458 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
bogdanm 92:4fc01daae5a5 4459
bogdanm 92:4fc01daae5a5 4460 /****************** Bit definition for I2C_FLTR register *******************/
bogdanm 92:4fc01daae5a5 4461 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
bogdanm 92:4fc01daae5a5 4462 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
bogdanm 92:4fc01daae5a5 4463
bogdanm 92:4fc01daae5a5 4464 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4465 /* */
bogdanm 92:4fc01daae5a5 4466 /* Independent WATCHDOG */
bogdanm 92:4fc01daae5a5 4467 /* */
bogdanm 92:4fc01daae5a5 4468 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4469 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 92:4fc01daae5a5 4470 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
bogdanm 92:4fc01daae5a5 4471
bogdanm 92:4fc01daae5a5 4472 /******************* Bit definition for IWDG_PR register ********************/
bogdanm 92:4fc01daae5a5 4473 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
bogdanm 92:4fc01daae5a5 4474 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 4475 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 4476 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 4477
bogdanm 92:4fc01daae5a5 4478 /******************* Bit definition for IWDG_RLR register *******************/
bogdanm 92:4fc01daae5a5 4479 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
bogdanm 92:4fc01daae5a5 4480
bogdanm 92:4fc01daae5a5 4481 /******************* Bit definition for IWDG_SR register ********************/
bogdanm 92:4fc01daae5a5 4482 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
bogdanm 92:4fc01daae5a5 4483 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
bogdanm 92:4fc01daae5a5 4484
bogdanm 92:4fc01daae5a5 4485
bogdanm 92:4fc01daae5a5 4486 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4487 /* */
bogdanm 92:4fc01daae5a5 4488 /* Power Control */
bogdanm 92:4fc01daae5a5 4489 /* */
bogdanm 92:4fc01daae5a5 4490 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4491 /******************** Bit definition for PWR_CR register ********************/
bogdanm 92:4fc01daae5a5 4492 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
bogdanm 92:4fc01daae5a5 4493 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
bogdanm 92:4fc01daae5a5 4494 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
bogdanm 92:4fc01daae5a5 4495 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
bogdanm 92:4fc01daae5a5 4496 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
bogdanm 92:4fc01daae5a5 4497
bogdanm 92:4fc01daae5a5 4498 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 92:4fc01daae5a5 4499 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 4500 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 4501 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 4502
bogdanm 92:4fc01daae5a5 4503 /*!< PVD level configuration */
bogdanm 92:4fc01daae5a5 4504 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
bogdanm 92:4fc01daae5a5 4505 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
bogdanm 92:4fc01daae5a5 4506 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
bogdanm 92:4fc01daae5a5 4507 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
bogdanm 92:4fc01daae5a5 4508 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
bogdanm 92:4fc01daae5a5 4509 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
bogdanm 92:4fc01daae5a5 4510 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
bogdanm 92:4fc01daae5a5 4511 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
bogdanm 92:4fc01daae5a5 4512
bogdanm 92:4fc01daae5a5 4513 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
bogdanm 92:4fc01daae5a5 4514 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
bogdanm 92:4fc01daae5a5 4515 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
bogdanm 92:4fc01daae5a5 4516 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 4517 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 4518
bogdanm 92:4fc01daae5a5 4519 /* Legacy define */
bogdanm 92:4fc01daae5a5 4520 #define PWR_CR_PMODE PWR_CR_VOS
bogdanm 92:4fc01daae5a5 4521
bogdanm 92:4fc01daae5a5 4522 /******************* Bit definition for PWR_CSR register ********************/
bogdanm 92:4fc01daae5a5 4523 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
bogdanm 92:4fc01daae5a5 4524 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
bogdanm 92:4fc01daae5a5 4525 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
bogdanm 92:4fc01daae5a5 4526 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
bogdanm 92:4fc01daae5a5 4527 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
bogdanm 92:4fc01daae5a5 4528 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
bogdanm 92:4fc01daae5a5 4529 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
bogdanm 92:4fc01daae5a5 4530
bogdanm 92:4fc01daae5a5 4531 /* Legacy define */
bogdanm 92:4fc01daae5a5 4532 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
bogdanm 92:4fc01daae5a5 4533
bogdanm 92:4fc01daae5a5 4534 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4535 /* */
bogdanm 92:4fc01daae5a5 4536 /* Reset and Clock Control */
bogdanm 92:4fc01daae5a5 4537 /* */
bogdanm 92:4fc01daae5a5 4538 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4539 /******************** Bit definition for RCC_CR register ********************/
bogdanm 92:4fc01daae5a5 4540 #define RCC_CR_HSION ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4541 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4542
bogdanm 92:4fc01daae5a5 4543 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
bogdanm 92:4fc01daae5a5 4544 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
bogdanm 92:4fc01daae5a5 4545 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
bogdanm 92:4fc01daae5a5 4546 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
bogdanm 92:4fc01daae5a5 4547 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
bogdanm 92:4fc01daae5a5 4548 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
bogdanm 92:4fc01daae5a5 4549
bogdanm 92:4fc01daae5a5 4550 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
bogdanm 92:4fc01daae5a5 4551 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
bogdanm 92:4fc01daae5a5 4552 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
bogdanm 92:4fc01daae5a5 4553 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
bogdanm 92:4fc01daae5a5 4554 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
bogdanm 92:4fc01daae5a5 4555 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
bogdanm 92:4fc01daae5a5 4556 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
bogdanm 92:4fc01daae5a5 4557 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
bogdanm 92:4fc01daae5a5 4558 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
bogdanm 92:4fc01daae5a5 4559
bogdanm 92:4fc01daae5a5 4560 #define RCC_CR_HSEON ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4561 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4562 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4563 #define RCC_CR_CSSON ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4564 #define RCC_CR_PLLON ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 4565 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4566 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4567 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 4568
bogdanm 92:4fc01daae5a5 4569 /******************** Bit definition for RCC_PLLCFGR register ***************/
bogdanm 92:4fc01daae5a5 4570 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
bogdanm 92:4fc01daae5a5 4571 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4572 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4573 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4574 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4575 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4576 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4577
bogdanm 92:4fc01daae5a5 4578 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
bogdanm 92:4fc01daae5a5 4579 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4580 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4581 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4582 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4583 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4584 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4585 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4586 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4587 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4588
bogdanm 92:4fc01daae5a5 4589 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
bogdanm 92:4fc01daae5a5 4590 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4591 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4592
bogdanm 92:4fc01daae5a5 4593 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4594 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4595 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 4596
bogdanm 92:4fc01daae5a5 4597 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
bogdanm 92:4fc01daae5a5 4598 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 4599 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4600 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4601 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 4602
bogdanm 92:4fc01daae5a5 4603 /******************** Bit definition for RCC_CFGR register ******************/
bogdanm 92:4fc01daae5a5 4604 /*!< SW configuration */
bogdanm 92:4fc01daae5a5 4605 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 92:4fc01daae5a5 4606 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 4607 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 4608
bogdanm 92:4fc01daae5a5 4609 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
bogdanm 92:4fc01daae5a5 4610 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
bogdanm 92:4fc01daae5a5 4611 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
bogdanm 92:4fc01daae5a5 4612
bogdanm 92:4fc01daae5a5 4613 /*!< SWS configuration */
bogdanm 92:4fc01daae5a5 4614 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 92:4fc01daae5a5 4615 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 4616 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 4617
bogdanm 92:4fc01daae5a5 4618 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
bogdanm 92:4fc01daae5a5 4619 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
bogdanm 92:4fc01daae5a5 4620 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
bogdanm 92:4fc01daae5a5 4621
bogdanm 92:4fc01daae5a5 4622 /*!< HPRE configuration */
bogdanm 92:4fc01daae5a5 4623 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 92:4fc01daae5a5 4624 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 4625 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 4626 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 4627 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 92:4fc01daae5a5 4628
bogdanm 92:4fc01daae5a5 4629 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 92:4fc01daae5a5 4630 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 92:4fc01daae5a5 4631 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 92:4fc01daae5a5 4632 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 92:4fc01daae5a5 4633 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 92:4fc01daae5a5 4634 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 92:4fc01daae5a5 4635 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 92:4fc01daae5a5 4636 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 92:4fc01daae5a5 4637 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 92:4fc01daae5a5 4638
bogdanm 92:4fc01daae5a5 4639 /*!< PPRE1 configuration */
bogdanm 92:4fc01daae5a5 4640 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
bogdanm 92:4fc01daae5a5 4641 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 4642 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 4643 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 4644
bogdanm 92:4fc01daae5a5 4645 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 92:4fc01daae5a5 4646 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
bogdanm 92:4fc01daae5a5 4647 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
bogdanm 92:4fc01daae5a5 4648 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
bogdanm 92:4fc01daae5a5 4649 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
bogdanm 92:4fc01daae5a5 4650
bogdanm 92:4fc01daae5a5 4651 /*!< PPRE2 configuration */
bogdanm 92:4fc01daae5a5 4652 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
bogdanm 92:4fc01daae5a5 4653 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 4654 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 4655 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 4656
bogdanm 92:4fc01daae5a5 4657 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 92:4fc01daae5a5 4658 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
bogdanm 92:4fc01daae5a5 4659 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
bogdanm 92:4fc01daae5a5 4660 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
bogdanm 92:4fc01daae5a5 4661 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
bogdanm 92:4fc01daae5a5 4662
bogdanm 92:4fc01daae5a5 4663 /*!< RTCPRE configuration */
bogdanm 92:4fc01daae5a5 4664 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
bogdanm 92:4fc01daae5a5 4665 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4666 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4667 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4668 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4669 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4670
bogdanm 92:4fc01daae5a5 4671 /*!< MCO1 configuration */
bogdanm 92:4fc01daae5a5 4672 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
bogdanm 92:4fc01daae5a5 4673 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4674 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4675
bogdanm 92:4fc01daae5a5 4676 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4677
bogdanm 92:4fc01daae5a5 4678 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
bogdanm 92:4fc01daae5a5 4679 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 4680 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4681 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4682
bogdanm 92:4fc01daae5a5 4683 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
bogdanm 92:4fc01daae5a5 4684 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 4685 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4686 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4687
bogdanm 92:4fc01daae5a5 4688 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
bogdanm 92:4fc01daae5a5 4689 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4690 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 4691
bogdanm 92:4fc01daae5a5 4692 /******************** Bit definition for RCC_CIR register *******************/
bogdanm 92:4fc01daae5a5 4693 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4694 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4695 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4696 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4697 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4698 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4699
bogdanm 92:4fc01daae5a5 4700 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4701 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4702 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4703 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4704 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4705 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4706 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4707
bogdanm 92:4fc01daae5a5 4708 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4709 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4710 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4711 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4712 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4713 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4714
bogdanm 92:4fc01daae5a5 4715 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4716
bogdanm 92:4fc01daae5a5 4717 /******************** Bit definition for RCC_AHB1RSTR register **************/
bogdanm 92:4fc01daae5a5 4718 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4719 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4720 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4721 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4722 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4723 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4724 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4725 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4726 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4727 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4728 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4729 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4730 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4731
bogdanm 92:4fc01daae5a5 4732 /******************** Bit definition for RCC_AHB2RSTR register **************/
bogdanm 92:4fc01daae5a5 4733 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4734 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4735
bogdanm 92:4fc01daae5a5 4736 /******************** Bit definition for RCC_AHB3RSTR register **************/
bogdanm 92:4fc01daae5a5 4737
bogdanm 92:4fc01daae5a5 4738 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4739
bogdanm 92:4fc01daae5a5 4740 /******************** Bit definition for RCC_APB1RSTR register **************/
bogdanm 92:4fc01daae5a5 4741 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4742 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4743 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4744 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4745 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4746 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4747 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4748 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4749 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4750 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4751 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4752 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4753 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4754 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4755 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4756 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4757 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4758 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4759 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4760 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4761 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4762 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4763 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4764
bogdanm 92:4fc01daae5a5 4765 /******************** Bit definition for RCC_APB2RSTR register **************/
bogdanm 92:4fc01daae5a5 4766 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4767 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4768 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4769 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4770 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4771 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4772 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4773 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4774 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4775 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4776 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4777
bogdanm 92:4fc01daae5a5 4778 /* Old SPI1RST bit definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 4779 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
bogdanm 92:4fc01daae5a5 4780
bogdanm 92:4fc01daae5a5 4781 /******************** Bit definition for RCC_AHB1ENR register ***************/
bogdanm 92:4fc01daae5a5 4782 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4783 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4784 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4785 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4786 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4787 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4788 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4789 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4790 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4791 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4792 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4793 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4794 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4795 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4796
bogdanm 92:4fc01daae5a5 4797 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4798 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4799
bogdanm 92:4fc01daae5a5 4800 /******************** Bit definition for RCC_AHB2ENR register ***************/
bogdanm 92:4fc01daae5a5 4801 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4802 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4803
bogdanm 92:4fc01daae5a5 4804 /******************** Bit definition for RCC_AHB3ENR register ***************/
bogdanm 92:4fc01daae5a5 4805
bogdanm 92:4fc01daae5a5 4806 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4807
bogdanm 92:4fc01daae5a5 4808 /******************** Bit definition for RCC_APB1ENR register ***************/
bogdanm 92:4fc01daae5a5 4809 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4810 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4811 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4812 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4813 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4814 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4815 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4816 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4817 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4818 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4819 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4820 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4821 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4822 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4823 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4824 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4825 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4826 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4827 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4828 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4829 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4830 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4831 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4832
bogdanm 92:4fc01daae5a5 4833 /******************** Bit definition for RCC_APB2ENR register ***************/
bogdanm 92:4fc01daae5a5 4834 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4835 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4836 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4837 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4838 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4839 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4840 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4841 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4842 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4843 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4844 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4845 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4846 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4847 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4848 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4849
bogdanm 92:4fc01daae5a5 4850 /******************** Bit definition for RCC_AHB1LPENR register *************/
bogdanm 92:4fc01daae5a5 4851 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4852 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4853 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4854 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4855 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4856 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4857 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4858 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4859 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4860 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4861 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4862 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4863 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4864 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4865 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4866 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4867 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4868 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4869 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4870
bogdanm 92:4fc01daae5a5 4871 /******************** Bit definition for RCC_AHB2LPENR register *************/
bogdanm 92:4fc01daae5a5 4872 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4873 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4874
bogdanm 92:4fc01daae5a5 4875 /******************** Bit definition for RCC_AHB3LPENR register *************/
bogdanm 92:4fc01daae5a5 4876
bogdanm 92:4fc01daae5a5 4877 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4878
bogdanm 92:4fc01daae5a5 4879 /******************** Bit definition for RCC_APB1LPENR register *************/
bogdanm 92:4fc01daae5a5 4880 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4881 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4882 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4883 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4884 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4885 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4886 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4887 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4888 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4889 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4890 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4891 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4892 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4893 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4894 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4895 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4896 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4897 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4898 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 4899 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4900 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4901 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4902 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4903
bogdanm 92:4fc01daae5a5 4904 /******************** Bit definition for RCC_APB2LPENR register *************/
bogdanm 92:4fc01daae5a5 4905 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4906 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4907 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 4908 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4909 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4910 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4911 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4912 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4913 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4914 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4915 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4916 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4917 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4918
bogdanm 92:4fc01daae5a5 4919 /******************** Bit definition for RCC_BDCR register ******************/
bogdanm 92:4fc01daae5a5 4920 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4921 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4922 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4923
bogdanm 92:4fc01daae5a5 4924 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
bogdanm 92:4fc01daae5a5 4925 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4926 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4927
bogdanm 92:4fc01daae5a5 4928 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 4929 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4930
bogdanm 92:4fc01daae5a5 4931 /******************** Bit definition for RCC_CSR register *******************/
bogdanm 92:4fc01daae5a5 4932 #define RCC_CSR_LSION ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4933 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4934 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 4935 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 4936 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 4937 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 4938 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4939 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4940 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4941 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 4942
bogdanm 92:4fc01daae5a5 4943 /******************** Bit definition for RCC_SSCGR register *****************/
bogdanm 92:4fc01daae5a5 4944 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
bogdanm 92:4fc01daae5a5 4945 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
bogdanm 92:4fc01daae5a5 4946 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4947 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 4948
bogdanm 92:4fc01daae5a5 4949 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
bogdanm 92:4fc01daae5a5 4950 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
bogdanm 92:4fc01daae5a5 4951 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4952 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 4953 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 4954 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 4955 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 4956 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 4957 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4958 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 4959 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 4960
bogdanm 92:4fc01daae5a5 4961 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
bogdanm 92:4fc01daae5a5 4962 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 4963 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 4964 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 4965
bogdanm 92:4fc01daae5a5 4966 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4967 /* */
bogdanm 92:4fc01daae5a5 4968 /* RNG */
bogdanm 92:4fc01daae5a5 4969 /* */
bogdanm 92:4fc01daae5a5 4970 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4971 /******************** Bits definition for RNG_CR register *******************/
bogdanm 92:4fc01daae5a5 4972 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4973 #define RNG_CR_IE ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 4974
bogdanm 92:4fc01daae5a5 4975 /******************** Bits definition for RNG_SR register *******************/
bogdanm 92:4fc01daae5a5 4976 #define RNG_SR_DRDY ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 4977 #define RNG_SR_CECS ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 4978 #define RNG_SR_SECS ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 4979 #define RNG_SR_CEIS ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 4980 #define RNG_SR_SEIS ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 4981
bogdanm 92:4fc01daae5a5 4982 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4983 /* */
bogdanm 92:4fc01daae5a5 4984 /* Real-Time Clock (RTC) */
bogdanm 92:4fc01daae5a5 4985 /* */
bogdanm 92:4fc01daae5a5 4986 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4987 /******************** Bits definition for RTC_TR register *******************/
bogdanm 92:4fc01daae5a5 4988 #define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 4989 #define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm 92:4fc01daae5a5 4990 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 4991 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 4992 #define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm 92:4fc01daae5a5 4993 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 4994 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 4995 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 4996 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 4997 #define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm 92:4fc01daae5a5 4998 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 4999 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5000 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5001 #define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm 92:4fc01daae5a5 5002 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5003 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5004 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5005 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5006 #define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm 92:4fc01daae5a5 5007 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5008 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5009 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 5010 #define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm 92:4fc01daae5a5 5011 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5012 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5013 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5014 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5015
bogdanm 92:4fc01daae5a5 5016 /******************** Bits definition for RTC_DR register *******************/
bogdanm 92:4fc01daae5a5 5017 #define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm 92:4fc01daae5a5 5018 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 5019 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 5020 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 5021 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 5022 #define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm 92:4fc01daae5a5 5023 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 5024 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 5025 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 5026 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 5027 #define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm 92:4fc01daae5a5 5028 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5029 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5030 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 5031 #define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 5032 #define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm 92:4fc01daae5a5 5033 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5034 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5035 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5036 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5037 #define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 5038 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5039 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5040 #define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm 92:4fc01daae5a5 5041 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5042 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5043 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5044 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5045
bogdanm 92:4fc01daae5a5 5046 /******************** Bits definition for RTC_CR register *******************/
bogdanm 92:4fc01daae5a5 5047 #define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 5048 #define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm 92:4fc01daae5a5 5049 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 5050 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 5051 #define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 5052 #define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 5053 #define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 5054 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 5055 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 5056 #define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 5057 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5058 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5059 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 5060 #define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5061 #define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5062 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5063 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5064 #define RTC_CR_DCE ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 5065 #define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 5066 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5067 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5068 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5069 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm 92:4fc01daae5a5 5070 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5071 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5072 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5073
bogdanm 92:4fc01daae5a5 5074 /******************** Bits definition for RTC_ISR register ******************/
bogdanm 92:4fc01daae5a5 5075 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 5076 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5077 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5078 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 5079 #define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5080 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5081 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5082 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5083 #define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 5084 #define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 5085 #define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5086 #define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5087 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5088 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5089 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5090 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5091
bogdanm 92:4fc01daae5a5 5092 /******************** Bits definition for RTC_PRER register *****************/
bogdanm 92:4fc01daae5a5 5093 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm 92:4fc01daae5a5 5094 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
bogdanm 92:4fc01daae5a5 5095
bogdanm 92:4fc01daae5a5 5096 /******************** Bits definition for RTC_WUTR register *****************/
bogdanm 92:4fc01daae5a5 5097 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm 92:4fc01daae5a5 5098
bogdanm 92:4fc01daae5a5 5099 /******************** Bits definition for RTC_CALIBR register ***************/
bogdanm 92:4fc01daae5a5 5100 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 5101 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
bogdanm 92:4fc01daae5a5 5102
bogdanm 92:4fc01daae5a5 5103 /******************** Bits definition for RTC_ALRMAR register ***************/
bogdanm 92:4fc01daae5a5 5104 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 5105 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 5106 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm 92:4fc01daae5a5 5107 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 5108 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 5109 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm 92:4fc01daae5a5 5110 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 5111 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 5112 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 5113 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 5114 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 5115 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 5116 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm 92:4fc01daae5a5 5117 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 5118 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 5119 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm 92:4fc01daae5a5 5120 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 5121 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 5122 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 5123 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 5124 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 5125 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm 92:4fc01daae5a5 5126 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 5127 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5128 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5129 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm 92:4fc01daae5a5 5130 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5131 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5132 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5133 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5134 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 5135 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm 92:4fc01daae5a5 5136 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5137 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5138 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 5139 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm 92:4fc01daae5a5 5140 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5141 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5142 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5143 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5144
bogdanm 92:4fc01daae5a5 5145 /******************** Bits definition for RTC_ALRMBR register ***************/
bogdanm 92:4fc01daae5a5 5146 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 5147 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm 92:4fc01daae5a5 5148 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm 92:4fc01daae5a5 5149 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 5150 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 5151 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm 92:4fc01daae5a5 5152 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 5153 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 5154 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 5155 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 5156 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 5157 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 5158 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm 92:4fc01daae5a5 5159 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 5160 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 5161 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm 92:4fc01daae5a5 5162 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 5163 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 5164 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 5165 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 5166 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 5167 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm 92:4fc01daae5a5 5168 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 5169 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5170 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5171 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm 92:4fc01daae5a5 5172 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5173 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5174 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5175 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5176 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 5177 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm 92:4fc01daae5a5 5178 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5179 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5180 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 5181 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm 92:4fc01daae5a5 5182 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5183 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5184 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5185 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5186
bogdanm 92:4fc01daae5a5 5187 /******************** Bits definition for RTC_WPR register ******************/
bogdanm 92:4fc01daae5a5 5188 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm 92:4fc01daae5a5 5189
bogdanm 92:4fc01daae5a5 5190 /******************** Bits definition for RTC_SSR register ******************/
bogdanm 92:4fc01daae5a5 5191 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm 92:4fc01daae5a5 5192
bogdanm 92:4fc01daae5a5 5193 /******************** Bits definition for RTC_SHIFTR register ***************/
bogdanm 92:4fc01daae5a5 5194 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm 92:4fc01daae5a5 5195 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 5196
bogdanm 92:4fc01daae5a5 5197 /******************** Bits definition for RTC_TSTR register *****************/
bogdanm 92:4fc01daae5a5 5198 #define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 5199 #define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm 92:4fc01daae5a5 5200 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 5201 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 5202 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm 92:4fc01daae5a5 5203 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 5204 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 5205 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 5206 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 5207 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm 92:4fc01daae5a5 5208 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 5209 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5210 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5211 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm 92:4fc01daae5a5 5212 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5213 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5214 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5215 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5216 #define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm 92:4fc01daae5a5 5217 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5218 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5219 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 5220 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm 92:4fc01daae5a5 5221 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5222 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5223 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5224 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5225
bogdanm 92:4fc01daae5a5 5226 /******************** Bits definition for RTC_TSDR register *****************/
bogdanm 92:4fc01daae5a5 5227 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm 92:4fc01daae5a5 5228 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5229 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5230 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 5231 #define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 5232 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm 92:4fc01daae5a5 5233 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5234 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5235 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5236 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5237 #define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 5238 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5239 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5240 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm 92:4fc01daae5a5 5241 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5242 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5243 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5244 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5245
bogdanm 92:4fc01daae5a5 5246 /******************** Bits definition for RTC_TSSSR register ****************/
bogdanm 92:4fc01daae5a5 5247 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm 92:4fc01daae5a5 5248
bogdanm 92:4fc01daae5a5 5249 /******************** Bits definition for RTC_CAL register *****************/
bogdanm 92:4fc01daae5a5 5250 #define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 5251 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5252 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5253 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm 92:4fc01daae5a5 5254 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5255 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5256 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5257 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5258 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5259 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 5260 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 5261 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 5262 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5263
bogdanm 92:4fc01daae5a5 5264 /******************** Bits definition for RTC_TAFCR register ****************/
bogdanm 92:4fc01daae5a5 5265 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 5266 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 5267 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 5268 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 5269 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm 92:4fc01daae5a5 5270 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 5271 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 5272 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm 92:4fc01daae5a5 5273 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 5274 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 5275 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm 92:4fc01daae5a5 5276 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 5277 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 5278 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 5279 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 5280 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 5281 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 5282 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5283 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5284 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5285
bogdanm 92:4fc01daae5a5 5286 /******************** Bits definition for RTC_ALRMASSR register *************/
bogdanm 92:4fc01daae5a5 5287 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 92:4fc01daae5a5 5288 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 5289 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 5290 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 5291 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 5292 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm 92:4fc01daae5a5 5293
bogdanm 92:4fc01daae5a5 5294 /******************** Bits definition for RTC_ALRMBSSR register *************/
bogdanm 92:4fc01daae5a5 5295 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 92:4fc01daae5a5 5296 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 5297 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 5298 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 5299 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 5300 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm 92:4fc01daae5a5 5301
bogdanm 92:4fc01daae5a5 5302 /******************** Bits definition for RTC_BKP0R register ****************/
bogdanm 92:4fc01daae5a5 5303 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5304
bogdanm 92:4fc01daae5a5 5305 /******************** Bits definition for RTC_BKP1R register ****************/
bogdanm 92:4fc01daae5a5 5306 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5307
bogdanm 92:4fc01daae5a5 5308 /******************** Bits definition for RTC_BKP2R register ****************/
bogdanm 92:4fc01daae5a5 5309 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5310
bogdanm 92:4fc01daae5a5 5311 /******************** Bits definition for RTC_BKP3R register ****************/
bogdanm 92:4fc01daae5a5 5312 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5313
bogdanm 92:4fc01daae5a5 5314 /******************** Bits definition for RTC_BKP4R register ****************/
bogdanm 92:4fc01daae5a5 5315 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5316
bogdanm 92:4fc01daae5a5 5317 /******************** Bits definition for RTC_BKP5R register ****************/
bogdanm 92:4fc01daae5a5 5318 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5319
bogdanm 92:4fc01daae5a5 5320 /******************** Bits definition for RTC_BKP6R register ****************/
bogdanm 92:4fc01daae5a5 5321 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5322
bogdanm 92:4fc01daae5a5 5323 /******************** Bits definition for RTC_BKP7R register ****************/
bogdanm 92:4fc01daae5a5 5324 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5325
bogdanm 92:4fc01daae5a5 5326 /******************** Bits definition for RTC_BKP8R register ****************/
bogdanm 92:4fc01daae5a5 5327 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5328
bogdanm 92:4fc01daae5a5 5329 /******************** Bits definition for RTC_BKP9R register ****************/
bogdanm 92:4fc01daae5a5 5330 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5331
bogdanm 92:4fc01daae5a5 5332 /******************** Bits definition for RTC_BKP10R register ***************/
bogdanm 92:4fc01daae5a5 5333 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5334
bogdanm 92:4fc01daae5a5 5335 /******************** Bits definition for RTC_BKP11R register ***************/
bogdanm 92:4fc01daae5a5 5336 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5337
bogdanm 92:4fc01daae5a5 5338 /******************** Bits definition for RTC_BKP12R register ***************/
bogdanm 92:4fc01daae5a5 5339 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5340
bogdanm 92:4fc01daae5a5 5341 /******************** Bits definition for RTC_BKP13R register ***************/
bogdanm 92:4fc01daae5a5 5342 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5343
bogdanm 92:4fc01daae5a5 5344 /******************** Bits definition for RTC_BKP14R register ***************/
bogdanm 92:4fc01daae5a5 5345 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5346
bogdanm 92:4fc01daae5a5 5347 /******************** Bits definition for RTC_BKP15R register ***************/
bogdanm 92:4fc01daae5a5 5348 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5349
bogdanm 92:4fc01daae5a5 5350 /******************** Bits definition for RTC_BKP16R register ***************/
bogdanm 92:4fc01daae5a5 5351 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5352
bogdanm 92:4fc01daae5a5 5353 /******************** Bits definition for RTC_BKP17R register ***************/
bogdanm 92:4fc01daae5a5 5354 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5355
bogdanm 92:4fc01daae5a5 5356 /******************** Bits definition for RTC_BKP18R register ***************/
bogdanm 92:4fc01daae5a5 5357 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5358
bogdanm 92:4fc01daae5a5 5359 /******************** Bits definition for RTC_BKP19R register ***************/
bogdanm 92:4fc01daae5a5 5360 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 5361
bogdanm 92:4fc01daae5a5 5362
bogdanm 92:4fc01daae5a5 5363
bogdanm 92:4fc01daae5a5 5364 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5365 /* */
bogdanm 92:4fc01daae5a5 5366 /* SD host Interface */
bogdanm 92:4fc01daae5a5 5367 /* */
bogdanm 92:4fc01daae5a5 5368 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5369 /****************** Bit definition for SDIO_POWER register ******************/
bogdanm 92:4fc01daae5a5 5370 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
bogdanm 92:4fc01daae5a5 5371 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5372 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5373
bogdanm 92:4fc01daae5a5 5374 /****************** Bit definition for SDIO_CLKCR register ******************/
bogdanm 92:4fc01daae5a5 5375 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
bogdanm 92:4fc01daae5a5 5376 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
bogdanm 92:4fc01daae5a5 5377 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
bogdanm 92:4fc01daae5a5 5378 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
bogdanm 92:4fc01daae5a5 5379
bogdanm 92:4fc01daae5a5 5380 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
bogdanm 92:4fc01daae5a5 5381 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5382 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5383
bogdanm 92:4fc01daae5a5 5384 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
bogdanm 92:4fc01daae5a5 5385 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
bogdanm 92:4fc01daae5a5 5386
bogdanm 92:4fc01daae5a5 5387 /******************* Bit definition for SDIO_ARG register *******************/
bogdanm 92:4fc01daae5a5 5388 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
bogdanm 92:4fc01daae5a5 5389
bogdanm 92:4fc01daae5a5 5390 /******************* Bit definition for SDIO_CMD register *******************/
bogdanm 92:4fc01daae5a5 5391 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
bogdanm 92:4fc01daae5a5 5392
bogdanm 92:4fc01daae5a5 5393 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
bogdanm 92:4fc01daae5a5 5394 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 5395 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 5396
bogdanm 92:4fc01daae5a5 5397 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
bogdanm 92:4fc01daae5a5 5398 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
bogdanm 92:4fc01daae5a5 5399 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
bogdanm 92:4fc01daae5a5 5400 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
bogdanm 92:4fc01daae5a5 5401 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
bogdanm 92:4fc01daae5a5 5402 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
bogdanm 92:4fc01daae5a5 5403 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
bogdanm 92:4fc01daae5a5 5404
bogdanm 92:4fc01daae5a5 5405 /***************** Bit definition for SDIO_RESPCMD register *****************/
bogdanm 92:4fc01daae5a5 5406 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
bogdanm 92:4fc01daae5a5 5407
bogdanm 92:4fc01daae5a5 5408 /****************** Bit definition for SDIO_RESP0 register ******************/
bogdanm 92:4fc01daae5a5 5409 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 92:4fc01daae5a5 5410
bogdanm 92:4fc01daae5a5 5411 /****************** Bit definition for SDIO_RESP1 register ******************/
bogdanm 92:4fc01daae5a5 5412 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 92:4fc01daae5a5 5413
bogdanm 92:4fc01daae5a5 5414 /****************** Bit definition for SDIO_RESP2 register ******************/
bogdanm 92:4fc01daae5a5 5415 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 92:4fc01daae5a5 5416
bogdanm 92:4fc01daae5a5 5417 /****************** Bit definition for SDIO_RESP3 register ******************/
bogdanm 92:4fc01daae5a5 5418 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 92:4fc01daae5a5 5419
bogdanm 92:4fc01daae5a5 5420 /****************** Bit definition for SDIO_RESP4 register ******************/
bogdanm 92:4fc01daae5a5 5421 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 92:4fc01daae5a5 5422
bogdanm 92:4fc01daae5a5 5423 /****************** Bit definition for SDIO_DTIMER register *****************/
bogdanm 92:4fc01daae5a5 5424 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
bogdanm 92:4fc01daae5a5 5425
bogdanm 92:4fc01daae5a5 5426 /****************** Bit definition for SDIO_DLEN register *******************/
bogdanm 92:4fc01daae5a5 5427 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
bogdanm 92:4fc01daae5a5 5428
bogdanm 92:4fc01daae5a5 5429 /****************** Bit definition for SDIO_DCTRL register ******************/
bogdanm 92:4fc01daae5a5 5430 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
bogdanm 92:4fc01daae5a5 5431 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
bogdanm 92:4fc01daae5a5 5432 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
bogdanm 92:4fc01daae5a5 5433 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
bogdanm 92:4fc01daae5a5 5434
bogdanm 92:4fc01daae5a5 5435 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
bogdanm 92:4fc01daae5a5 5436 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5437 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5438 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 5439 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 5440
bogdanm 92:4fc01daae5a5 5441 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
bogdanm 92:4fc01daae5a5 5442 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
bogdanm 92:4fc01daae5a5 5443 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
bogdanm 92:4fc01daae5a5 5444 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
bogdanm 92:4fc01daae5a5 5445
bogdanm 92:4fc01daae5a5 5446 /****************** Bit definition for SDIO_DCOUNT register *****************/
bogdanm 92:4fc01daae5a5 5447 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
bogdanm 92:4fc01daae5a5 5448
bogdanm 92:4fc01daae5a5 5449 /****************** Bit definition for SDIO_STA register ********************/
bogdanm 92:4fc01daae5a5 5450 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
bogdanm 92:4fc01daae5a5 5451 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
bogdanm 92:4fc01daae5a5 5452 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
bogdanm 92:4fc01daae5a5 5453 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
bogdanm 92:4fc01daae5a5 5454 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
bogdanm 92:4fc01daae5a5 5455 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
bogdanm 92:4fc01daae5a5 5456 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
bogdanm 92:4fc01daae5a5 5457 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
bogdanm 92:4fc01daae5a5 5458 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
bogdanm 92:4fc01daae5a5 5459 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
bogdanm 92:4fc01daae5a5 5460 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
bogdanm 92:4fc01daae5a5 5461 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
bogdanm 92:4fc01daae5a5 5462 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
bogdanm 92:4fc01daae5a5 5463 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
bogdanm 92:4fc01daae5a5 5464 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
bogdanm 92:4fc01daae5a5 5465 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
bogdanm 92:4fc01daae5a5 5466 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
bogdanm 92:4fc01daae5a5 5467 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
bogdanm 92:4fc01daae5a5 5468 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
bogdanm 92:4fc01daae5a5 5469 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
bogdanm 92:4fc01daae5a5 5470 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
bogdanm 92:4fc01daae5a5 5471 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
bogdanm 92:4fc01daae5a5 5472 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
bogdanm 92:4fc01daae5a5 5473 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
bogdanm 92:4fc01daae5a5 5474
bogdanm 92:4fc01daae5a5 5475 /******************* Bit definition for SDIO_ICR register *******************/
bogdanm 92:4fc01daae5a5 5476 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
bogdanm 92:4fc01daae5a5 5477 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
bogdanm 92:4fc01daae5a5 5478 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
bogdanm 92:4fc01daae5a5 5479 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
bogdanm 92:4fc01daae5a5 5480 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
bogdanm 92:4fc01daae5a5 5481 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
bogdanm 92:4fc01daae5a5 5482 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
bogdanm 92:4fc01daae5a5 5483 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
bogdanm 92:4fc01daae5a5 5484 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
bogdanm 92:4fc01daae5a5 5485 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
bogdanm 92:4fc01daae5a5 5486 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
bogdanm 92:4fc01daae5a5 5487 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
bogdanm 92:4fc01daae5a5 5488 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
bogdanm 92:4fc01daae5a5 5489
bogdanm 92:4fc01daae5a5 5490 /****************** Bit definition for SDIO_MASK register *******************/
bogdanm 92:4fc01daae5a5 5491 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
bogdanm 92:4fc01daae5a5 5492 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
bogdanm 92:4fc01daae5a5 5493 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
bogdanm 92:4fc01daae5a5 5494 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
bogdanm 92:4fc01daae5a5 5495 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
bogdanm 92:4fc01daae5a5 5496 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
bogdanm 92:4fc01daae5a5 5497 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
bogdanm 92:4fc01daae5a5 5498 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
bogdanm 92:4fc01daae5a5 5499 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
bogdanm 92:4fc01daae5a5 5500 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
bogdanm 92:4fc01daae5a5 5501 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
bogdanm 92:4fc01daae5a5 5502 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
bogdanm 92:4fc01daae5a5 5503 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
bogdanm 92:4fc01daae5a5 5504 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
bogdanm 92:4fc01daae5a5 5505 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
bogdanm 92:4fc01daae5a5 5506 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
bogdanm 92:4fc01daae5a5 5507 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
bogdanm 92:4fc01daae5a5 5508 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
bogdanm 92:4fc01daae5a5 5509 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
bogdanm 92:4fc01daae5a5 5510 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
bogdanm 92:4fc01daae5a5 5511 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
bogdanm 92:4fc01daae5a5 5512 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
bogdanm 92:4fc01daae5a5 5513 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
bogdanm 92:4fc01daae5a5 5514 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
bogdanm 92:4fc01daae5a5 5515
bogdanm 92:4fc01daae5a5 5516 /***************** Bit definition for SDIO_FIFOCNT register *****************/
bogdanm 92:4fc01daae5a5 5517 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
bogdanm 92:4fc01daae5a5 5518
bogdanm 92:4fc01daae5a5 5519 /****************** Bit definition for SDIO_FIFO register *******************/
bogdanm 92:4fc01daae5a5 5520 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
bogdanm 92:4fc01daae5a5 5521
bogdanm 92:4fc01daae5a5 5522 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5523 /* */
bogdanm 92:4fc01daae5a5 5524 /* Serial Peripheral Interface */
bogdanm 92:4fc01daae5a5 5525 /* */
bogdanm 92:4fc01daae5a5 5526 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5527 /******************* Bit definition for SPI_CR1 register ********************/
bogdanm 92:4fc01daae5a5 5528 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
bogdanm 92:4fc01daae5a5 5529 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
bogdanm 92:4fc01daae5a5 5530 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
bogdanm 92:4fc01daae5a5 5531
bogdanm 92:4fc01daae5a5 5532 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
bogdanm 92:4fc01daae5a5 5533 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5534 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5535 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 5536
bogdanm 92:4fc01daae5a5 5537 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
bogdanm 92:4fc01daae5a5 5538 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
bogdanm 92:4fc01daae5a5 5539 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
bogdanm 92:4fc01daae5a5 5540 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
bogdanm 92:4fc01daae5a5 5541 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
bogdanm 92:4fc01daae5a5 5542 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
bogdanm 92:4fc01daae5a5 5543 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
bogdanm 92:4fc01daae5a5 5544 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
bogdanm 92:4fc01daae5a5 5545 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
bogdanm 92:4fc01daae5a5 5546 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
bogdanm 92:4fc01daae5a5 5547
bogdanm 92:4fc01daae5a5 5548 /******************* Bit definition for SPI_CR2 register ********************/
bogdanm 92:4fc01daae5a5 5549 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
bogdanm 92:4fc01daae5a5 5550 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
bogdanm 92:4fc01daae5a5 5551 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
bogdanm 92:4fc01daae5a5 5552 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
bogdanm 92:4fc01daae5a5 5553 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
bogdanm 92:4fc01daae5a5 5554 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
bogdanm 92:4fc01daae5a5 5555 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
bogdanm 92:4fc01daae5a5 5556
bogdanm 92:4fc01daae5a5 5557 /******************** Bit definition for SPI_SR register ********************/
bogdanm 92:4fc01daae5a5 5558 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
bogdanm 92:4fc01daae5a5 5559 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
bogdanm 92:4fc01daae5a5 5560 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
bogdanm 92:4fc01daae5a5 5561 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
bogdanm 92:4fc01daae5a5 5562 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
bogdanm 92:4fc01daae5a5 5563 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
bogdanm 92:4fc01daae5a5 5564 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
bogdanm 92:4fc01daae5a5 5565 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
bogdanm 92:4fc01daae5a5 5566 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
bogdanm 92:4fc01daae5a5 5567
bogdanm 92:4fc01daae5a5 5568 /******************** Bit definition for SPI_DR register ********************/
bogdanm 92:4fc01daae5a5 5569 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
bogdanm 92:4fc01daae5a5 5570
bogdanm 92:4fc01daae5a5 5571 /******************* Bit definition for SPI_CRCPR register ******************/
bogdanm 92:4fc01daae5a5 5572 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
bogdanm 92:4fc01daae5a5 5573
bogdanm 92:4fc01daae5a5 5574 /****************** Bit definition for SPI_RXCRCR register ******************/
bogdanm 92:4fc01daae5a5 5575 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
bogdanm 92:4fc01daae5a5 5576
bogdanm 92:4fc01daae5a5 5577 /****************** Bit definition for SPI_TXCRCR register ******************/
bogdanm 92:4fc01daae5a5 5578 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
bogdanm 92:4fc01daae5a5 5579
bogdanm 92:4fc01daae5a5 5580 /****************** Bit definition for SPI_I2SCFGR register *****************/
bogdanm 92:4fc01daae5a5 5581 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
bogdanm 92:4fc01daae5a5 5582
bogdanm 92:4fc01daae5a5 5583 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
bogdanm 92:4fc01daae5a5 5584 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5585 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5586
bogdanm 92:4fc01daae5a5 5587 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
bogdanm 92:4fc01daae5a5 5588
bogdanm 92:4fc01daae5a5 5589 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
bogdanm 92:4fc01daae5a5 5590 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5591 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5592
bogdanm 92:4fc01daae5a5 5593 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
bogdanm 92:4fc01daae5a5 5594
bogdanm 92:4fc01daae5a5 5595 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
bogdanm 92:4fc01daae5a5 5596 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5597 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5598
bogdanm 92:4fc01daae5a5 5599 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
bogdanm 92:4fc01daae5a5 5600 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
bogdanm 92:4fc01daae5a5 5601
bogdanm 92:4fc01daae5a5 5602 /****************** Bit definition for SPI_I2SPR register *******************/
bogdanm 92:4fc01daae5a5 5603 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
bogdanm 92:4fc01daae5a5 5604 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
bogdanm 92:4fc01daae5a5 5605 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
bogdanm 92:4fc01daae5a5 5606
bogdanm 92:4fc01daae5a5 5607 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5608 /* */
bogdanm 92:4fc01daae5a5 5609 /* SYSCFG */
bogdanm 92:4fc01daae5a5 5610 /* */
bogdanm 92:4fc01daae5a5 5611 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5612 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
bogdanm 92:4fc01daae5a5 5613 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
bogdanm 92:4fc01daae5a5 5614 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 5615 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 5616 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 5617
bogdanm 92:4fc01daae5a5 5618 /****************** Bit definition for SYSCFG_PMC register ******************/
bogdanm 92:4fc01daae5a5 5619 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
bogdanm 92:4fc01daae5a5 5620 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 5621 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
bogdanm 92:4fc01daae5a5 5622
bogdanm 92:4fc01daae5a5 5623 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
bogdanm 92:4fc01daae5a5 5624 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
bogdanm 92:4fc01daae5a5 5625 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
bogdanm 92:4fc01daae5a5 5626 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
bogdanm 92:4fc01daae5a5 5627 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
bogdanm 92:4fc01daae5a5 5628 /**
bogdanm 92:4fc01daae5a5 5629 * @brief EXTI0 configuration
bogdanm 92:4fc01daae5a5 5630 */
bogdanm 92:4fc01daae5a5 5631 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
bogdanm 92:4fc01daae5a5 5632 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
bogdanm 92:4fc01daae5a5 5633 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
bogdanm 92:4fc01daae5a5 5634 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
bogdanm 92:4fc01daae5a5 5635 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
bogdanm 92:4fc01daae5a5 5636 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
bogdanm 92:4fc01daae5a5 5637 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
bogdanm 92:4fc01daae5a5 5638 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
bogdanm 92:4fc01daae5a5 5639 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
bogdanm 92:4fc01daae5a5 5640
bogdanm 92:4fc01daae5a5 5641 /**
bogdanm 92:4fc01daae5a5 5642 * @brief EXTI1 configuration
bogdanm 92:4fc01daae5a5 5643 */
bogdanm 92:4fc01daae5a5 5644 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
bogdanm 92:4fc01daae5a5 5645 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
bogdanm 92:4fc01daae5a5 5646 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
bogdanm 92:4fc01daae5a5 5647 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
bogdanm 92:4fc01daae5a5 5648 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
bogdanm 92:4fc01daae5a5 5649 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
bogdanm 92:4fc01daae5a5 5650 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
bogdanm 92:4fc01daae5a5 5651 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
bogdanm 92:4fc01daae5a5 5652 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
bogdanm 92:4fc01daae5a5 5653
bogdanm 92:4fc01daae5a5 5654 /**
bogdanm 92:4fc01daae5a5 5655 * @brief EXTI2 configuration
bogdanm 92:4fc01daae5a5 5656 */
bogdanm 92:4fc01daae5a5 5657 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
bogdanm 92:4fc01daae5a5 5658 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
bogdanm 92:4fc01daae5a5 5659 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
bogdanm 92:4fc01daae5a5 5660 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
bogdanm 92:4fc01daae5a5 5661 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
bogdanm 92:4fc01daae5a5 5662 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
bogdanm 92:4fc01daae5a5 5663 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
bogdanm 92:4fc01daae5a5 5664 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
bogdanm 92:4fc01daae5a5 5665 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
bogdanm 92:4fc01daae5a5 5666
bogdanm 92:4fc01daae5a5 5667 /**
bogdanm 92:4fc01daae5a5 5668 * @brief EXTI3 configuration
bogdanm 92:4fc01daae5a5 5669 */
bogdanm 92:4fc01daae5a5 5670 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
bogdanm 92:4fc01daae5a5 5671 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
bogdanm 92:4fc01daae5a5 5672 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
bogdanm 92:4fc01daae5a5 5673 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
bogdanm 92:4fc01daae5a5 5674 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
bogdanm 92:4fc01daae5a5 5675 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
bogdanm 92:4fc01daae5a5 5676 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
bogdanm 92:4fc01daae5a5 5677 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
bogdanm 92:4fc01daae5a5 5678 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
bogdanm 92:4fc01daae5a5 5679
bogdanm 92:4fc01daae5a5 5680 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
bogdanm 92:4fc01daae5a5 5681 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
bogdanm 92:4fc01daae5a5 5682 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
bogdanm 92:4fc01daae5a5 5683 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
bogdanm 92:4fc01daae5a5 5684 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
bogdanm 92:4fc01daae5a5 5685 /**
bogdanm 92:4fc01daae5a5 5686 * @brief EXTI4 configuration
bogdanm 92:4fc01daae5a5 5687 */
bogdanm 92:4fc01daae5a5 5688 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
bogdanm 92:4fc01daae5a5 5689 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
bogdanm 92:4fc01daae5a5 5690 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
bogdanm 92:4fc01daae5a5 5691 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
bogdanm 92:4fc01daae5a5 5692 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
bogdanm 92:4fc01daae5a5 5693 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
bogdanm 92:4fc01daae5a5 5694 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
bogdanm 92:4fc01daae5a5 5695 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
bogdanm 92:4fc01daae5a5 5696 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
bogdanm 92:4fc01daae5a5 5697
bogdanm 92:4fc01daae5a5 5698 /**
bogdanm 92:4fc01daae5a5 5699 * @brief EXTI5 configuration
bogdanm 92:4fc01daae5a5 5700 */
bogdanm 92:4fc01daae5a5 5701 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
bogdanm 92:4fc01daae5a5 5702 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
bogdanm 92:4fc01daae5a5 5703 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
bogdanm 92:4fc01daae5a5 5704 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
bogdanm 92:4fc01daae5a5 5705 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
bogdanm 92:4fc01daae5a5 5706 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
bogdanm 92:4fc01daae5a5 5707 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
bogdanm 92:4fc01daae5a5 5708 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
bogdanm 92:4fc01daae5a5 5709 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
bogdanm 92:4fc01daae5a5 5710
bogdanm 92:4fc01daae5a5 5711 /**
bogdanm 92:4fc01daae5a5 5712 * @brief EXTI6 configuration
bogdanm 92:4fc01daae5a5 5713 */
bogdanm 92:4fc01daae5a5 5714 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
bogdanm 92:4fc01daae5a5 5715 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
bogdanm 92:4fc01daae5a5 5716 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
bogdanm 92:4fc01daae5a5 5717 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
bogdanm 92:4fc01daae5a5 5718 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
bogdanm 92:4fc01daae5a5 5719 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
bogdanm 92:4fc01daae5a5 5720 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
bogdanm 92:4fc01daae5a5 5721 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
bogdanm 92:4fc01daae5a5 5722 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
bogdanm 92:4fc01daae5a5 5723
bogdanm 92:4fc01daae5a5 5724 /**
bogdanm 92:4fc01daae5a5 5725 * @brief EXTI7 configuration
bogdanm 92:4fc01daae5a5 5726 */
bogdanm 92:4fc01daae5a5 5727 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
bogdanm 92:4fc01daae5a5 5728 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
bogdanm 92:4fc01daae5a5 5729 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
bogdanm 92:4fc01daae5a5 5730 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
bogdanm 92:4fc01daae5a5 5731 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
bogdanm 92:4fc01daae5a5 5732 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
bogdanm 92:4fc01daae5a5 5733 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
bogdanm 92:4fc01daae5a5 5734 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
bogdanm 92:4fc01daae5a5 5735 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
bogdanm 92:4fc01daae5a5 5736
bogdanm 92:4fc01daae5a5 5737
bogdanm 92:4fc01daae5a5 5738 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
bogdanm 92:4fc01daae5a5 5739 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
bogdanm 92:4fc01daae5a5 5740 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
bogdanm 92:4fc01daae5a5 5741 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
bogdanm 92:4fc01daae5a5 5742 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
bogdanm 92:4fc01daae5a5 5743
bogdanm 92:4fc01daae5a5 5744 /**
bogdanm 92:4fc01daae5a5 5745 * @brief EXTI8 configuration
bogdanm 92:4fc01daae5a5 5746 */
bogdanm 92:4fc01daae5a5 5747 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
bogdanm 92:4fc01daae5a5 5748 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
bogdanm 92:4fc01daae5a5 5749 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
bogdanm 92:4fc01daae5a5 5750 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
bogdanm 92:4fc01daae5a5 5751 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
bogdanm 92:4fc01daae5a5 5752 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
bogdanm 92:4fc01daae5a5 5753 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
bogdanm 92:4fc01daae5a5 5754 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
bogdanm 92:4fc01daae5a5 5755 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
bogdanm 92:4fc01daae5a5 5756
bogdanm 92:4fc01daae5a5 5757 /**
bogdanm 92:4fc01daae5a5 5758 * @brief EXTI9 configuration
bogdanm 92:4fc01daae5a5 5759 */
bogdanm 92:4fc01daae5a5 5760 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
bogdanm 92:4fc01daae5a5 5761 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
bogdanm 92:4fc01daae5a5 5762 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
bogdanm 92:4fc01daae5a5 5763 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
bogdanm 92:4fc01daae5a5 5764 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
bogdanm 92:4fc01daae5a5 5765 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
bogdanm 92:4fc01daae5a5 5766 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
bogdanm 92:4fc01daae5a5 5767 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
bogdanm 92:4fc01daae5a5 5768 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
bogdanm 92:4fc01daae5a5 5769
bogdanm 92:4fc01daae5a5 5770 /**
bogdanm 92:4fc01daae5a5 5771 * @brief EXTI10 configuration
bogdanm 92:4fc01daae5a5 5772 */
bogdanm 92:4fc01daae5a5 5773 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
bogdanm 92:4fc01daae5a5 5774 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
bogdanm 92:4fc01daae5a5 5775 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
bogdanm 92:4fc01daae5a5 5776 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
bogdanm 92:4fc01daae5a5 5777 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
bogdanm 92:4fc01daae5a5 5778 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
bogdanm 92:4fc01daae5a5 5779 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
bogdanm 92:4fc01daae5a5 5780 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
bogdanm 92:4fc01daae5a5 5781 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
bogdanm 92:4fc01daae5a5 5782
bogdanm 92:4fc01daae5a5 5783 /**
bogdanm 92:4fc01daae5a5 5784 * @brief EXTI11 configuration
bogdanm 92:4fc01daae5a5 5785 */
bogdanm 92:4fc01daae5a5 5786 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
bogdanm 92:4fc01daae5a5 5787 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
bogdanm 92:4fc01daae5a5 5788 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
bogdanm 92:4fc01daae5a5 5789 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
bogdanm 92:4fc01daae5a5 5790 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
bogdanm 92:4fc01daae5a5 5791 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
bogdanm 92:4fc01daae5a5 5792 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
bogdanm 92:4fc01daae5a5 5793 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
bogdanm 92:4fc01daae5a5 5794 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
bogdanm 92:4fc01daae5a5 5795
bogdanm 92:4fc01daae5a5 5796 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
bogdanm 92:4fc01daae5a5 5797 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
bogdanm 92:4fc01daae5a5 5798 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
bogdanm 92:4fc01daae5a5 5799 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
bogdanm 92:4fc01daae5a5 5800 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
bogdanm 92:4fc01daae5a5 5801 /**
bogdanm 92:4fc01daae5a5 5802 * @brief EXTI12 configuration
bogdanm 92:4fc01daae5a5 5803 */
bogdanm 92:4fc01daae5a5 5804 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
bogdanm 92:4fc01daae5a5 5805 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
bogdanm 92:4fc01daae5a5 5806 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
bogdanm 92:4fc01daae5a5 5807 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
bogdanm 92:4fc01daae5a5 5808 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
bogdanm 92:4fc01daae5a5 5809 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
bogdanm 92:4fc01daae5a5 5810 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
bogdanm 92:4fc01daae5a5 5811 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
bogdanm 92:4fc01daae5a5 5812
bogdanm 92:4fc01daae5a5 5813 /**
bogdanm 92:4fc01daae5a5 5814 * @brief EXTI13 configuration
bogdanm 92:4fc01daae5a5 5815 */
bogdanm 92:4fc01daae5a5 5816 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
bogdanm 92:4fc01daae5a5 5817 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
bogdanm 92:4fc01daae5a5 5818 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
bogdanm 92:4fc01daae5a5 5819 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
bogdanm 92:4fc01daae5a5 5820 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
bogdanm 92:4fc01daae5a5 5821 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
bogdanm 92:4fc01daae5a5 5822 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
bogdanm 92:4fc01daae5a5 5823 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
bogdanm 92:4fc01daae5a5 5824
bogdanm 92:4fc01daae5a5 5825 /**
bogdanm 92:4fc01daae5a5 5826 * @brief EXTI14 configuration
bogdanm 92:4fc01daae5a5 5827 */
bogdanm 92:4fc01daae5a5 5828 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
bogdanm 92:4fc01daae5a5 5829 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
bogdanm 92:4fc01daae5a5 5830 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
bogdanm 92:4fc01daae5a5 5831 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
bogdanm 92:4fc01daae5a5 5832 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
bogdanm 92:4fc01daae5a5 5833 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
bogdanm 92:4fc01daae5a5 5834 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
bogdanm 92:4fc01daae5a5 5835 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
bogdanm 92:4fc01daae5a5 5836
bogdanm 92:4fc01daae5a5 5837 /**
bogdanm 92:4fc01daae5a5 5838 * @brief EXTI15 configuration
bogdanm 92:4fc01daae5a5 5839 */
bogdanm 92:4fc01daae5a5 5840 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
bogdanm 92:4fc01daae5a5 5841 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
bogdanm 92:4fc01daae5a5 5842 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
bogdanm 92:4fc01daae5a5 5843 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
bogdanm 92:4fc01daae5a5 5844 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
bogdanm 92:4fc01daae5a5 5845 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
bogdanm 92:4fc01daae5a5 5846 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
bogdanm 92:4fc01daae5a5 5847 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
bogdanm 92:4fc01daae5a5 5848
bogdanm 92:4fc01daae5a5 5849 /****************** Bit definition for SYSCFG_CMPCR register ****************/
bogdanm 92:4fc01daae5a5 5850 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
bogdanm 92:4fc01daae5a5 5851 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
bogdanm 92:4fc01daae5a5 5852
bogdanm 92:4fc01daae5a5 5853 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5854 /* */
bogdanm 92:4fc01daae5a5 5855 /* TIM */
bogdanm 92:4fc01daae5a5 5856 /* */
bogdanm 92:4fc01daae5a5 5857 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5858 /******************* Bit definition for TIM_CR1 register ********************/
bogdanm 92:4fc01daae5a5 5859 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
bogdanm 92:4fc01daae5a5 5860 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
bogdanm 92:4fc01daae5a5 5861 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
bogdanm 92:4fc01daae5a5 5862 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
bogdanm 92:4fc01daae5a5 5863 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
bogdanm 92:4fc01daae5a5 5864
bogdanm 92:4fc01daae5a5 5865 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 92:4fc01daae5a5 5866 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5867 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5868
bogdanm 92:4fc01daae5a5 5869 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
bogdanm 92:4fc01daae5a5 5870
bogdanm 92:4fc01daae5a5 5871 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
bogdanm 92:4fc01daae5a5 5872 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5873 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5874
bogdanm 92:4fc01daae5a5 5875 /******************* Bit definition for TIM_CR2 register ********************/
bogdanm 92:4fc01daae5a5 5876 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
bogdanm 92:4fc01daae5a5 5877 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
bogdanm 92:4fc01daae5a5 5878 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
bogdanm 92:4fc01daae5a5 5879
bogdanm 92:4fc01daae5a5 5880 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 92:4fc01daae5a5 5881 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5882 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5883 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 5884
bogdanm 92:4fc01daae5a5 5885 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
bogdanm 92:4fc01daae5a5 5886 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
bogdanm 92:4fc01daae5a5 5887 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
bogdanm 92:4fc01daae5a5 5888 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
bogdanm 92:4fc01daae5a5 5889 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
bogdanm 92:4fc01daae5a5 5890 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
bogdanm 92:4fc01daae5a5 5891 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
bogdanm 92:4fc01daae5a5 5892 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 92:4fc01daae5a5 5893
bogdanm 92:4fc01daae5a5 5894 /******************* Bit definition for TIM_SMCR register *******************/
bogdanm 92:4fc01daae5a5 5895 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
bogdanm 92:4fc01daae5a5 5896 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5897 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5898 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 5899
bogdanm 92:4fc01daae5a5 5900 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
bogdanm 92:4fc01daae5a5 5901 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5902 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5903 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 5904
bogdanm 92:4fc01daae5a5 5905 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
bogdanm 92:4fc01daae5a5 5906
bogdanm 92:4fc01daae5a5 5907 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
bogdanm 92:4fc01daae5a5 5908 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5909 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5910 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 5911 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 5912
bogdanm 92:4fc01daae5a5 5913 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
bogdanm 92:4fc01daae5a5 5914 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5915 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5916
bogdanm 92:4fc01daae5a5 5917 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
bogdanm 92:4fc01daae5a5 5918 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
bogdanm 92:4fc01daae5a5 5919
bogdanm 92:4fc01daae5a5 5920 /******************* Bit definition for TIM_DIER register *******************/
bogdanm 92:4fc01daae5a5 5921 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
bogdanm 92:4fc01daae5a5 5922 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
bogdanm 92:4fc01daae5a5 5923 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
bogdanm 92:4fc01daae5a5 5924 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
bogdanm 92:4fc01daae5a5 5925 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
bogdanm 92:4fc01daae5a5 5926 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
bogdanm 92:4fc01daae5a5 5927 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
bogdanm 92:4fc01daae5a5 5928 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
bogdanm 92:4fc01daae5a5 5929 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
bogdanm 92:4fc01daae5a5 5930 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
bogdanm 92:4fc01daae5a5 5931 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
bogdanm 92:4fc01daae5a5 5932 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
bogdanm 92:4fc01daae5a5 5933 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
bogdanm 92:4fc01daae5a5 5934 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
bogdanm 92:4fc01daae5a5 5935 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
bogdanm 92:4fc01daae5a5 5936
bogdanm 92:4fc01daae5a5 5937 /******************** Bit definition for TIM_SR register ********************/
bogdanm 92:4fc01daae5a5 5938 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
bogdanm 92:4fc01daae5a5 5939 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
bogdanm 92:4fc01daae5a5 5940 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
bogdanm 92:4fc01daae5a5 5941 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
bogdanm 92:4fc01daae5a5 5942 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
bogdanm 92:4fc01daae5a5 5943 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
bogdanm 92:4fc01daae5a5 5944 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
bogdanm 92:4fc01daae5a5 5945 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
bogdanm 92:4fc01daae5a5 5946 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
bogdanm 92:4fc01daae5a5 5947 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
bogdanm 92:4fc01daae5a5 5948 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
bogdanm 92:4fc01daae5a5 5949 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 92:4fc01daae5a5 5950
bogdanm 92:4fc01daae5a5 5951 /******************* Bit definition for TIM_EGR register ********************/
bogdanm 92:4fc01daae5a5 5952 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
bogdanm 92:4fc01daae5a5 5953 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
bogdanm 92:4fc01daae5a5 5954 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
bogdanm 92:4fc01daae5a5 5955 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
bogdanm 92:4fc01daae5a5 5956 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
bogdanm 92:4fc01daae5a5 5957 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
bogdanm 92:4fc01daae5a5 5958 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
bogdanm 92:4fc01daae5a5 5959 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
bogdanm 92:4fc01daae5a5 5960
bogdanm 92:4fc01daae5a5 5961 /****************** Bit definition for TIM_CCMR1 register *******************/
bogdanm 92:4fc01daae5a5 5962 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 92:4fc01daae5a5 5963 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5964 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5965
bogdanm 92:4fc01daae5a5 5966 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
bogdanm 92:4fc01daae5a5 5967 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
bogdanm 92:4fc01daae5a5 5968
bogdanm 92:4fc01daae5a5 5969 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 92:4fc01daae5a5 5970 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5971 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5972 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 5973
bogdanm 92:4fc01daae5a5 5974 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
bogdanm 92:4fc01daae5a5 5975
bogdanm 92:4fc01daae5a5 5976 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 92:4fc01daae5a5 5977 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5978 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5979
bogdanm 92:4fc01daae5a5 5980 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
bogdanm 92:4fc01daae5a5 5981 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
bogdanm 92:4fc01daae5a5 5982
bogdanm 92:4fc01daae5a5 5983 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 92:4fc01daae5a5 5984 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5985 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5986 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 5987
bogdanm 92:4fc01daae5a5 5988 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
bogdanm 92:4fc01daae5a5 5989
bogdanm 92:4fc01daae5a5 5990 /*----------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 5991
bogdanm 92:4fc01daae5a5 5992 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 92:4fc01daae5a5 5993 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5994 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5995
bogdanm 92:4fc01daae5a5 5996 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 92:4fc01daae5a5 5997 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 5998 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5999 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6000 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6001
bogdanm 92:4fc01daae5a5 6002 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 92:4fc01daae5a5 6003 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6004 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6005
bogdanm 92:4fc01daae5a5 6006 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 92:4fc01daae5a5 6007 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6008 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6009 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6010 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6011
bogdanm 92:4fc01daae5a5 6012 /****************** Bit definition for TIM_CCMR2 register *******************/
bogdanm 92:4fc01daae5a5 6013 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 92:4fc01daae5a5 6014 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6015 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6016
bogdanm 92:4fc01daae5a5 6017 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
bogdanm 92:4fc01daae5a5 6018 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
bogdanm 92:4fc01daae5a5 6019
bogdanm 92:4fc01daae5a5 6020 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 92:4fc01daae5a5 6021 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6022 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6023 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6024
bogdanm 92:4fc01daae5a5 6025 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
bogdanm 92:4fc01daae5a5 6026
bogdanm 92:4fc01daae5a5 6027 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 92:4fc01daae5a5 6028 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6029 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6030
bogdanm 92:4fc01daae5a5 6031 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
bogdanm 92:4fc01daae5a5 6032 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
bogdanm 92:4fc01daae5a5 6033
bogdanm 92:4fc01daae5a5 6034 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 92:4fc01daae5a5 6035 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6036 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6037 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6038
bogdanm 92:4fc01daae5a5 6039 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
bogdanm 92:4fc01daae5a5 6040
bogdanm 92:4fc01daae5a5 6041 /*----------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 6042
bogdanm 92:4fc01daae5a5 6043 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 92:4fc01daae5a5 6044 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6045 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6046
bogdanm 92:4fc01daae5a5 6047 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 92:4fc01daae5a5 6048 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6049 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6050 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6051 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6052
bogdanm 92:4fc01daae5a5 6053 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 92:4fc01daae5a5 6054 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6055 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6056
bogdanm 92:4fc01daae5a5 6057 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 92:4fc01daae5a5 6058 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6059 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6060 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6061 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6062
bogdanm 92:4fc01daae5a5 6063 /******************* Bit definition for TIM_CCER register *******************/
bogdanm 92:4fc01daae5a5 6064 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
bogdanm 92:4fc01daae5a5 6065 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
bogdanm 92:4fc01daae5a5 6066 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
bogdanm 92:4fc01daae5a5 6067 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
bogdanm 92:4fc01daae5a5 6068 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
bogdanm 92:4fc01daae5a5 6069 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
bogdanm 92:4fc01daae5a5 6070 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
bogdanm 92:4fc01daae5a5 6071 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
bogdanm 92:4fc01daae5a5 6072 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
bogdanm 92:4fc01daae5a5 6073 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
bogdanm 92:4fc01daae5a5 6074 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
bogdanm 92:4fc01daae5a5 6075 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
bogdanm 92:4fc01daae5a5 6076 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
bogdanm 92:4fc01daae5a5 6077 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
bogdanm 92:4fc01daae5a5 6078 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 92:4fc01daae5a5 6079
bogdanm 92:4fc01daae5a5 6080 /******************* Bit definition for TIM_CNT register ********************/
bogdanm 92:4fc01daae5a5 6081 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
bogdanm 92:4fc01daae5a5 6082
bogdanm 92:4fc01daae5a5 6083 /******************* Bit definition for TIM_PSC register ********************/
bogdanm 92:4fc01daae5a5 6084 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
bogdanm 92:4fc01daae5a5 6085
bogdanm 92:4fc01daae5a5 6086 /******************* Bit definition for TIM_ARR register ********************/
bogdanm 92:4fc01daae5a5 6087 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
bogdanm 92:4fc01daae5a5 6088
bogdanm 92:4fc01daae5a5 6089 /******************* Bit definition for TIM_RCR register ********************/
bogdanm 92:4fc01daae5a5 6090 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
bogdanm 92:4fc01daae5a5 6091
bogdanm 92:4fc01daae5a5 6092 /******************* Bit definition for TIM_CCR1 register *******************/
bogdanm 92:4fc01daae5a5 6093 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
bogdanm 92:4fc01daae5a5 6094
bogdanm 92:4fc01daae5a5 6095 /******************* Bit definition for TIM_CCR2 register *******************/
bogdanm 92:4fc01daae5a5 6096 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
bogdanm 92:4fc01daae5a5 6097
bogdanm 92:4fc01daae5a5 6098 /******************* Bit definition for TIM_CCR3 register *******************/
bogdanm 92:4fc01daae5a5 6099 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
bogdanm 92:4fc01daae5a5 6100
bogdanm 92:4fc01daae5a5 6101 /******************* Bit definition for TIM_CCR4 register *******************/
bogdanm 92:4fc01daae5a5 6102 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
bogdanm 92:4fc01daae5a5 6103
bogdanm 92:4fc01daae5a5 6104 /******************* Bit definition for TIM_BDTR register *******************/
bogdanm 92:4fc01daae5a5 6105 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 92:4fc01daae5a5 6106 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6107 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6108 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6109 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6110 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6111 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6112 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6113 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 6114
bogdanm 92:4fc01daae5a5 6115 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
bogdanm 92:4fc01daae5a5 6116 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6117 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6118
bogdanm 92:4fc01daae5a5 6119 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
bogdanm 92:4fc01daae5a5 6120 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
bogdanm 92:4fc01daae5a5 6121 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
bogdanm 92:4fc01daae5a5 6122 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
bogdanm 92:4fc01daae5a5 6123 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
bogdanm 92:4fc01daae5a5 6124 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
bogdanm 92:4fc01daae5a5 6125
bogdanm 92:4fc01daae5a5 6126 /******************* Bit definition for TIM_DCR register ********************/
bogdanm 92:4fc01daae5a5 6127 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
bogdanm 92:4fc01daae5a5 6128 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6129 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6130 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6131 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6132 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6133
bogdanm 92:4fc01daae5a5 6134 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
bogdanm 92:4fc01daae5a5 6135 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6136 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6137 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6138 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6139 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6140
bogdanm 92:4fc01daae5a5 6141 /******************* Bit definition for TIM_DMAR register *******************/
bogdanm 92:4fc01daae5a5 6142 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
bogdanm 92:4fc01daae5a5 6143
bogdanm 92:4fc01daae5a5 6144 /******************* Bit definition for TIM_OR register *********************/
bogdanm 92:4fc01daae5a5 6145 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
bogdanm 92:4fc01daae5a5 6146 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6147 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6148 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
bogdanm 92:4fc01daae5a5 6149 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6150 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6151
bogdanm 92:4fc01daae5a5 6152
bogdanm 92:4fc01daae5a5 6153 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6154 /* */
bogdanm 92:4fc01daae5a5 6155 /* Universal Synchronous Asynchronous Receiver Transmitter */
bogdanm 92:4fc01daae5a5 6156 /* */
bogdanm 92:4fc01daae5a5 6157 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6158 /******************* Bit definition for USART_SR register *******************/
bogdanm 92:4fc01daae5a5 6159 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
bogdanm 92:4fc01daae5a5 6160 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
bogdanm 92:4fc01daae5a5 6161 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
bogdanm 92:4fc01daae5a5 6162 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
bogdanm 92:4fc01daae5a5 6163 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
bogdanm 92:4fc01daae5a5 6164 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
bogdanm 92:4fc01daae5a5 6165 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
bogdanm 92:4fc01daae5a5 6166 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
bogdanm 92:4fc01daae5a5 6167 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
bogdanm 92:4fc01daae5a5 6168 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
bogdanm 92:4fc01daae5a5 6169
bogdanm 92:4fc01daae5a5 6170 /******************* Bit definition for USART_DR register *******************/
bogdanm 92:4fc01daae5a5 6171 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
bogdanm 92:4fc01daae5a5 6172
bogdanm 92:4fc01daae5a5 6173 /****************** Bit definition for USART_BRR register *******************/
bogdanm 92:4fc01daae5a5 6174 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
bogdanm 92:4fc01daae5a5 6175 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
bogdanm 92:4fc01daae5a5 6176
bogdanm 92:4fc01daae5a5 6177 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 92:4fc01daae5a5 6178 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
bogdanm 92:4fc01daae5a5 6179 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
bogdanm 92:4fc01daae5a5 6180 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
bogdanm 92:4fc01daae5a5 6181 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
bogdanm 92:4fc01daae5a5 6182 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
bogdanm 92:4fc01daae5a5 6183 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
bogdanm 92:4fc01daae5a5 6184 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
bogdanm 92:4fc01daae5a5 6185 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
bogdanm 92:4fc01daae5a5 6186 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
bogdanm 92:4fc01daae5a5 6187 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
bogdanm 92:4fc01daae5a5 6188 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
bogdanm 92:4fc01daae5a5 6189 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
bogdanm 92:4fc01daae5a5 6190 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
bogdanm 92:4fc01daae5a5 6191 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
bogdanm 92:4fc01daae5a5 6192 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
bogdanm 92:4fc01daae5a5 6193
bogdanm 92:4fc01daae5a5 6194 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 92:4fc01daae5a5 6195 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
bogdanm 92:4fc01daae5a5 6196 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
bogdanm 92:4fc01daae5a5 6197 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
bogdanm 92:4fc01daae5a5 6198 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
bogdanm 92:4fc01daae5a5 6199 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
bogdanm 92:4fc01daae5a5 6200 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
bogdanm 92:4fc01daae5a5 6201 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
bogdanm 92:4fc01daae5a5 6202
bogdanm 92:4fc01daae5a5 6203 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
bogdanm 92:4fc01daae5a5 6204 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6205 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6206
bogdanm 92:4fc01daae5a5 6207 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
bogdanm 92:4fc01daae5a5 6208
bogdanm 92:4fc01daae5a5 6209 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 92:4fc01daae5a5 6210 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
bogdanm 92:4fc01daae5a5 6211 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
bogdanm 92:4fc01daae5a5 6212 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
bogdanm 92:4fc01daae5a5 6213 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
bogdanm 92:4fc01daae5a5 6214 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
bogdanm 92:4fc01daae5a5 6215 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
bogdanm 92:4fc01daae5a5 6216 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
bogdanm 92:4fc01daae5a5 6217 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
bogdanm 92:4fc01daae5a5 6218 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
bogdanm 92:4fc01daae5a5 6219 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
bogdanm 92:4fc01daae5a5 6220 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
bogdanm 92:4fc01daae5a5 6221 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
bogdanm 92:4fc01daae5a5 6222
bogdanm 92:4fc01daae5a5 6223 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 92:4fc01daae5a5 6224 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
bogdanm 92:4fc01daae5a5 6225 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6226 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6227 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6228 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6229 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6230 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6231 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6232 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 6233
bogdanm 92:4fc01daae5a5 6234 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
bogdanm 92:4fc01daae5a5 6235
bogdanm 92:4fc01daae5a5 6236 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6237 /* */
bogdanm 92:4fc01daae5a5 6238 /* Window WATCHDOG */
bogdanm 92:4fc01daae5a5 6239 /* */
bogdanm 92:4fc01daae5a5 6240 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6241 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 92:4fc01daae5a5 6242 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 92:4fc01daae5a5 6243 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6244 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6245 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6246 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6247 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6248 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6249 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6250
bogdanm 92:4fc01daae5a5 6251 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
bogdanm 92:4fc01daae5a5 6252
bogdanm 92:4fc01daae5a5 6253 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 92:4fc01daae5a5 6254 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
bogdanm 92:4fc01daae5a5 6255 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6256 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6257 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6258 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6259 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6260 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6261 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6262
bogdanm 92:4fc01daae5a5 6263 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
bogdanm 92:4fc01daae5a5 6264 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6265 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6266
bogdanm 92:4fc01daae5a5 6267 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
bogdanm 92:4fc01daae5a5 6268
bogdanm 92:4fc01daae5a5 6269 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 92:4fc01daae5a5 6270 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
bogdanm 92:4fc01daae5a5 6271
bogdanm 92:4fc01daae5a5 6272
bogdanm 92:4fc01daae5a5 6273 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6274 /* */
bogdanm 92:4fc01daae5a5 6275 /* DBG */
bogdanm 92:4fc01daae5a5 6276 /* */
bogdanm 92:4fc01daae5a5 6277 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6278 /******************** Bit definition for DBGMCU_IDCODE register *************/
bogdanm 92:4fc01daae5a5 6279 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
bogdanm 92:4fc01daae5a5 6280 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm 92:4fc01daae5a5 6281
bogdanm 92:4fc01daae5a5 6282 /******************** Bit definition for DBGMCU_CR register *****************/
bogdanm 92:4fc01daae5a5 6283 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 6284 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 6285 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 6286 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 6287
bogdanm 92:4fc01daae5a5 6288 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm 92:4fc01daae5a5 6289 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6290 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6291
bogdanm 92:4fc01daae5a5 6292 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
bogdanm 92:4fc01daae5a5 6293 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 6294 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 6295 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 6296 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 6297 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 6298 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 6299 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 6300 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 6301 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 6302 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 6303 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 6304 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 6305 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 6306 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 6307 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 6308 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 6309 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 6310 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 6311 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
bogdanm 92:4fc01daae5a5 6312
bogdanm 92:4fc01daae5a5 6313 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
bogdanm 92:4fc01daae5a5 6314 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 6315 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 6316 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 6317 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 6318 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 6319
bogdanm 92:4fc01daae5a5 6320 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6321 /* */
bogdanm 92:4fc01daae5a5 6322 /* USB_OTG */
bogdanm 92:4fc01daae5a5 6323 /* */
bogdanm 92:4fc01daae5a5 6324 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6325 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
bogdanm 92:4fc01daae5a5 6326 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
bogdanm 92:4fc01daae5a5 6327 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
bogdanm 92:4fc01daae5a5 6328 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
bogdanm 92:4fc01daae5a5 6329 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
bogdanm 92:4fc01daae5a5 6330 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
bogdanm 92:4fc01daae5a5 6331 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
bogdanm 92:4fc01daae5a5 6332 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
bogdanm 92:4fc01daae5a5 6333 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
bogdanm 92:4fc01daae5a5 6334 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
bogdanm 92:4fc01daae5a5 6335 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
bogdanm 92:4fc01daae5a5 6336
bogdanm 92:4fc01daae5a5 6337 /******************** Bit definition forUSB_OTG_HCFG register ********************/
bogdanm 92:4fc01daae5a5 6338
bogdanm 92:4fc01daae5a5 6339 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
bogdanm 92:4fc01daae5a5 6340 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6341 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6342 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
bogdanm 92:4fc01daae5a5 6343
bogdanm 92:4fc01daae5a5 6344 /******************** Bit definition forUSB_OTG_DCFG register ********************/
bogdanm 92:4fc01daae5a5 6345
bogdanm 92:4fc01daae5a5 6346 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
bogdanm 92:4fc01daae5a5 6347 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6348 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6349 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
bogdanm 92:4fc01daae5a5 6350
bogdanm 92:4fc01daae5a5 6351 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
bogdanm 92:4fc01daae5a5 6352 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6353 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6354 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6355 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6356 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6357 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6358 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6359
bogdanm 92:4fc01daae5a5 6360 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
bogdanm 92:4fc01daae5a5 6361 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6362 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6363
bogdanm 92:4fc01daae5a5 6364 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
bogdanm 92:4fc01daae5a5 6365 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6366 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6367
bogdanm 92:4fc01daae5a5 6368 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
bogdanm 92:4fc01daae5a5 6369 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
bogdanm 92:4fc01daae5a5 6370 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
bogdanm 92:4fc01daae5a5 6371 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
bogdanm 92:4fc01daae5a5 6372
bogdanm 92:4fc01daae5a5 6373 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
bogdanm 92:4fc01daae5a5 6374 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
bogdanm 92:4fc01daae5a5 6375 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
bogdanm 92:4fc01daae5a5 6376 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
bogdanm 92:4fc01daae5a5 6377 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
bogdanm 92:4fc01daae5a5 6378 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
bogdanm 92:4fc01daae5a5 6379 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
bogdanm 92:4fc01daae5a5 6380
bogdanm 92:4fc01daae5a5 6381 /******************** Bit definition forUSB_OTG_DCTL register ********************/
bogdanm 92:4fc01daae5a5 6382 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
bogdanm 92:4fc01daae5a5 6383 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
bogdanm 92:4fc01daae5a5 6384 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
bogdanm 92:4fc01daae5a5 6385 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
bogdanm 92:4fc01daae5a5 6386
bogdanm 92:4fc01daae5a5 6387 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
bogdanm 92:4fc01daae5a5 6388 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6389 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6390 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6391 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
bogdanm 92:4fc01daae5a5 6392 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
bogdanm 92:4fc01daae5a5 6393 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
bogdanm 92:4fc01daae5a5 6394 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
bogdanm 92:4fc01daae5a5 6395 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
bogdanm 92:4fc01daae5a5 6396
bogdanm 92:4fc01daae5a5 6397 /******************** Bit definition forUSB_OTG_HFIR register ********************/
bogdanm 92:4fc01daae5a5 6398 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
bogdanm 92:4fc01daae5a5 6399
bogdanm 92:4fc01daae5a5 6400 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
bogdanm 92:4fc01daae5a5 6401 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
bogdanm 92:4fc01daae5a5 6402 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
bogdanm 92:4fc01daae5a5 6403
bogdanm 92:4fc01daae5a5 6404 /******************** Bit definition forUSB_OTG_DSTS register ********************/
bogdanm 92:4fc01daae5a5 6405 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
bogdanm 92:4fc01daae5a5 6406
bogdanm 92:4fc01daae5a5 6407 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
bogdanm 92:4fc01daae5a5 6408 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6409 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6410 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
bogdanm 92:4fc01daae5a5 6411 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
bogdanm 92:4fc01daae5a5 6412
bogdanm 92:4fc01daae5a5 6413 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
bogdanm 92:4fc01daae5a5 6414 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
bogdanm 92:4fc01daae5a5 6415
bogdanm 92:4fc01daae5a5 6416 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
bogdanm 92:4fc01daae5a5 6417 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6418 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6419 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6420 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6421 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
bogdanm 92:4fc01daae5a5 6422 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
bogdanm 92:4fc01daae5a5 6423 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
bogdanm 92:4fc01daae5a5 6424
bogdanm 92:4fc01daae5a5 6425 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
bogdanm 92:4fc01daae5a5 6426
bogdanm 92:4fc01daae5a5 6427 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
bogdanm 92:4fc01daae5a5 6428 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6429 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6430 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6431 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
bogdanm 92:4fc01daae5a5 6432 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
bogdanm 92:4fc01daae5a5 6433 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
bogdanm 92:4fc01daae5a5 6434
bogdanm 92:4fc01daae5a5 6435 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
bogdanm 92:4fc01daae5a5 6436 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6437 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6438 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6439 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6440 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
bogdanm 92:4fc01daae5a5 6441 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
bogdanm 92:4fc01daae5a5 6442 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
bogdanm 92:4fc01daae5a5 6443 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
bogdanm 92:4fc01daae5a5 6444 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
bogdanm 92:4fc01daae5a5 6445 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
bogdanm 92:4fc01daae5a5 6446 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
bogdanm 92:4fc01daae5a5 6447 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
bogdanm 92:4fc01daae5a5 6448 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
bogdanm 92:4fc01daae5a5 6449 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
bogdanm 92:4fc01daae5a5 6450 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
bogdanm 92:4fc01daae5a5 6451 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
bogdanm 92:4fc01daae5a5 6452 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
bogdanm 92:4fc01daae5a5 6453
bogdanm 92:4fc01daae5a5 6454 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
bogdanm 92:4fc01daae5a5 6455 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
bogdanm 92:4fc01daae5a5 6456 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
bogdanm 92:4fc01daae5a5 6457 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
bogdanm 92:4fc01daae5a5 6458 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
bogdanm 92:4fc01daae5a5 6459 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
bogdanm 92:4fc01daae5a5 6460
bogdanm 92:4fc01daae5a5 6461 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
bogdanm 92:4fc01daae5a5 6462 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6463 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6464 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6465 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6466 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6467 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
bogdanm 92:4fc01daae5a5 6468 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
bogdanm 92:4fc01daae5a5 6469
bogdanm 92:4fc01daae5a5 6470 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
bogdanm 92:4fc01daae5a5 6471 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 92:4fc01daae5a5 6472 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 92:4fc01daae5a5 6473 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
bogdanm 92:4fc01daae5a5 6474 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 92:4fc01daae5a5 6475 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 92:4fc01daae5a5 6476 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 92:4fc01daae5a5 6477 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
bogdanm 92:4fc01daae5a5 6478 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 92:4fc01daae5a5 6479
bogdanm 92:4fc01daae5a5 6480 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
bogdanm 92:4fc01daae5a5 6481 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
bogdanm 92:4fc01daae5a5 6482
bogdanm 92:4fc01daae5a5 6483 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
bogdanm 92:4fc01daae5a5 6484 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6485 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6486 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6487 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6488 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6489 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6490 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6491 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 6492
bogdanm 92:4fc01daae5a5 6493 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
bogdanm 92:4fc01daae5a5 6494 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6495 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6496 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6497 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6498 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6499 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6500 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6501 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 6502
bogdanm 92:4fc01daae5a5 6503 /******************** Bit definition forUSB_OTG_HAINT register ********************/
bogdanm 92:4fc01daae5a5 6504 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
bogdanm 92:4fc01daae5a5 6505
bogdanm 92:4fc01daae5a5 6506 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
bogdanm 92:4fc01daae5a5 6507 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 92:4fc01daae5a5 6508 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 92:4fc01daae5a5 6509 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
bogdanm 92:4fc01daae5a5 6510 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
bogdanm 92:4fc01daae5a5 6511 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
bogdanm 92:4fc01daae5a5 6512 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
bogdanm 92:4fc01daae5a5 6513 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 92:4fc01daae5a5 6514
bogdanm 92:4fc01daae5a5 6515 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
bogdanm 92:4fc01daae5a5 6516 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
bogdanm 92:4fc01daae5a5 6517 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
bogdanm 92:4fc01daae5a5 6518 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
bogdanm 92:4fc01daae5a5 6519 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
bogdanm 92:4fc01daae5a5 6520 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
bogdanm 92:4fc01daae5a5 6521 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
bogdanm 92:4fc01daae5a5 6522 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
bogdanm 92:4fc01daae5a5 6523 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
bogdanm 92:4fc01daae5a5 6524 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
bogdanm 92:4fc01daae5a5 6525 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
bogdanm 92:4fc01daae5a5 6526 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
bogdanm 92:4fc01daae5a5 6527 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
bogdanm 92:4fc01daae5a5 6528 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
bogdanm 92:4fc01daae5a5 6529 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
bogdanm 92:4fc01daae5a5 6530 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
bogdanm 92:4fc01daae5a5 6531 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
bogdanm 92:4fc01daae5a5 6532 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
bogdanm 92:4fc01daae5a5 6533 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
bogdanm 92:4fc01daae5a5 6534 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
bogdanm 92:4fc01daae5a5 6535 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
bogdanm 92:4fc01daae5a5 6536 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
bogdanm 92:4fc01daae5a5 6537 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
bogdanm 92:4fc01daae5a5 6538 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
bogdanm 92:4fc01daae5a5 6539 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
bogdanm 92:4fc01daae5a5 6540 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
bogdanm 92:4fc01daae5a5 6541 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
bogdanm 92:4fc01daae5a5 6542
bogdanm 92:4fc01daae5a5 6543 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
bogdanm 92:4fc01daae5a5 6544 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
bogdanm 92:4fc01daae5a5 6545 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
bogdanm 92:4fc01daae5a5 6546 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
bogdanm 92:4fc01daae5a5 6547 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
bogdanm 92:4fc01daae5a5 6548 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
bogdanm 92:4fc01daae5a5 6549 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
bogdanm 92:4fc01daae5a5 6550 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
bogdanm 92:4fc01daae5a5 6551 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
bogdanm 92:4fc01daae5a5 6552 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
bogdanm 92:4fc01daae5a5 6553 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
bogdanm 92:4fc01daae5a5 6554 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
bogdanm 92:4fc01daae5a5 6555 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
bogdanm 92:4fc01daae5a5 6556 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
bogdanm 92:4fc01daae5a5 6557 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
bogdanm 92:4fc01daae5a5 6558 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
bogdanm 92:4fc01daae5a5 6559 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
bogdanm 92:4fc01daae5a5 6560 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
bogdanm 92:4fc01daae5a5 6561 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
bogdanm 92:4fc01daae5a5 6562 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
bogdanm 92:4fc01daae5a5 6563 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
bogdanm 92:4fc01daae5a5 6564 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
bogdanm 92:4fc01daae5a5 6565 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
bogdanm 92:4fc01daae5a5 6566 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
bogdanm 92:4fc01daae5a5 6567 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
bogdanm 92:4fc01daae5a5 6568 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
bogdanm 92:4fc01daae5a5 6569 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
bogdanm 92:4fc01daae5a5 6570
bogdanm 92:4fc01daae5a5 6571 /******************** Bit definition forUSB_OTG_DAINT register ********************/
bogdanm 92:4fc01daae5a5 6572 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
bogdanm 92:4fc01daae5a5 6573 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
bogdanm 92:4fc01daae5a5 6574
bogdanm 92:4fc01daae5a5 6575 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
bogdanm 92:4fc01daae5a5 6576 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
bogdanm 92:4fc01daae5a5 6577
bogdanm 92:4fc01daae5a5 6578 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
bogdanm 92:4fc01daae5a5 6579 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
bogdanm 92:4fc01daae5a5 6580 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
bogdanm 92:4fc01daae5a5 6581 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
bogdanm 92:4fc01daae5a5 6582 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
bogdanm 92:4fc01daae5a5 6583
bogdanm 92:4fc01daae5a5 6584 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
bogdanm 92:4fc01daae5a5 6585 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
bogdanm 92:4fc01daae5a5 6586 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
bogdanm 92:4fc01daae5a5 6587
bogdanm 92:4fc01daae5a5 6588 /******************** Bit definition for OTG register ********************/
bogdanm 92:4fc01daae5a5 6589
bogdanm 92:4fc01daae5a5 6590 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
bogdanm 92:4fc01daae5a5 6591 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6592 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6593 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6594 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6595 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
bogdanm 92:4fc01daae5a5 6596
bogdanm 92:4fc01daae5a5 6597 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
bogdanm 92:4fc01daae5a5 6598 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6599 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6600
bogdanm 92:4fc01daae5a5 6601 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
bogdanm 92:4fc01daae5a5 6602 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6603 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6604 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6605 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6606
bogdanm 92:4fc01daae5a5 6607 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
bogdanm 92:4fc01daae5a5 6608 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6609 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6610 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6611 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6612
bogdanm 92:4fc01daae5a5 6613 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
bogdanm 92:4fc01daae5a5 6614 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6615 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6616 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6617 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6618
bogdanm 92:4fc01daae5a5 6619 /******************** Bit definition for OTG register ********************/
bogdanm 92:4fc01daae5a5 6620
bogdanm 92:4fc01daae5a5 6621 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
bogdanm 92:4fc01daae5a5 6622 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6623 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6624 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6625 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6626 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
bogdanm 92:4fc01daae5a5 6627
bogdanm 92:4fc01daae5a5 6628 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
bogdanm 92:4fc01daae5a5 6629 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6630 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6631
bogdanm 92:4fc01daae5a5 6632 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
bogdanm 92:4fc01daae5a5 6633 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6634 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6635 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6636 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6637
bogdanm 92:4fc01daae5a5 6638 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
bogdanm 92:4fc01daae5a5 6639 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6640 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6641 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6642 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6643
bogdanm 92:4fc01daae5a5 6644 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
bogdanm 92:4fc01daae5a5 6645 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6646 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6647 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6648 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6649
bogdanm 92:4fc01daae5a5 6650 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
bogdanm 92:4fc01daae5a5 6651 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
bogdanm 92:4fc01daae5a5 6652
bogdanm 92:4fc01daae5a5 6653 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
bogdanm 92:4fc01daae5a5 6654 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
bogdanm 92:4fc01daae5a5 6655
bogdanm 92:4fc01daae5a5 6656 /******************** Bit definition for OTG register ********************/
bogdanm 92:4fc01daae5a5 6657 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
bogdanm 92:4fc01daae5a5 6658 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
bogdanm 92:4fc01daae5a5 6659 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
bogdanm 92:4fc01daae5a5 6660 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
bogdanm 92:4fc01daae5a5 6661
bogdanm 92:4fc01daae5a5 6662 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
bogdanm 92:4fc01daae5a5 6663 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
bogdanm 92:4fc01daae5a5 6664
bogdanm 92:4fc01daae5a5 6665 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
bogdanm 92:4fc01daae5a5 6666 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
bogdanm 92:4fc01daae5a5 6667
bogdanm 92:4fc01daae5a5 6668 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
bogdanm 92:4fc01daae5a5 6669 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6670 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6671 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6672 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6673 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6674 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6675 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6676 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 6677
bogdanm 92:4fc01daae5a5 6678 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
bogdanm 92:4fc01daae5a5 6679 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6680 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6681 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6682 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6683 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6684 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6685 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6686
bogdanm 92:4fc01daae5a5 6687 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
bogdanm 92:4fc01daae5a5 6688 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
bogdanm 92:4fc01daae5a5 6689 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
bogdanm 92:4fc01daae5a5 6690
bogdanm 92:4fc01daae5a5 6691 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
bogdanm 92:4fc01daae5a5 6692 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6693 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6694 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6695 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6696 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6697 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6698 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6699 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 6700 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
bogdanm 92:4fc01daae5a5 6701 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
bogdanm 92:4fc01daae5a5 6702
bogdanm 92:4fc01daae5a5 6703 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
bogdanm 92:4fc01daae5a5 6704 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6705 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6706 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6707 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6708 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6709 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6710 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6711 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 6712 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
bogdanm 92:4fc01daae5a5 6713 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
bogdanm 92:4fc01daae5a5 6714
bogdanm 92:4fc01daae5a5 6715 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
bogdanm 92:4fc01daae5a5 6716 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
bogdanm 92:4fc01daae5a5 6717
bogdanm 92:4fc01daae5a5 6718 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
bogdanm 92:4fc01daae5a5 6719 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
bogdanm 92:4fc01daae5a5 6720 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
bogdanm 92:4fc01daae5a5 6721
bogdanm 92:4fc01daae5a5 6722 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
bogdanm 92:4fc01daae5a5 6723 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
bogdanm 92:4fc01daae5a5 6724 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
bogdanm 92:4fc01daae5a5 6725 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
bogdanm 92:4fc01daae5a5 6726 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
bogdanm 92:4fc01daae5a5 6727 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
bogdanm 92:4fc01daae5a5 6728 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
bogdanm 92:4fc01daae5a5 6729
bogdanm 92:4fc01daae5a5 6730 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
bogdanm 92:4fc01daae5a5 6731 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
bogdanm 92:4fc01daae5a5 6732 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
bogdanm 92:4fc01daae5a5 6733
bogdanm 92:4fc01daae5a5 6734 /******************** Bit definition forUSB_OTG_CID register ********************/
bogdanm 92:4fc01daae5a5 6735 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
bogdanm 92:4fc01daae5a5 6736
bogdanm 92:4fc01daae5a5 6737 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
bogdanm 92:4fc01daae5a5 6738 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 92:4fc01daae5a5 6739 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 92:4fc01daae5a5 6740 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
bogdanm 92:4fc01daae5a5 6741 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 92:4fc01daae5a5 6742 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 92:4fc01daae5a5 6743 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 92:4fc01daae5a5 6744 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
bogdanm 92:4fc01daae5a5 6745 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 92:4fc01daae5a5 6746 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
bogdanm 92:4fc01daae5a5 6747
bogdanm 92:4fc01daae5a5 6748 /******************** Bit definition forUSB_OTG_HPRT register ********************/
bogdanm 92:4fc01daae5a5 6749 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
bogdanm 92:4fc01daae5a5 6750 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
bogdanm 92:4fc01daae5a5 6751 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
bogdanm 92:4fc01daae5a5 6752 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
bogdanm 92:4fc01daae5a5 6753 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
bogdanm 92:4fc01daae5a5 6754 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
bogdanm 92:4fc01daae5a5 6755 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
bogdanm 92:4fc01daae5a5 6756 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
bogdanm 92:4fc01daae5a5 6757 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
bogdanm 92:4fc01daae5a5 6758
bogdanm 92:4fc01daae5a5 6759 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
bogdanm 92:4fc01daae5a5 6760 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6761 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6762 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
bogdanm 92:4fc01daae5a5 6763
bogdanm 92:4fc01daae5a5 6764 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
bogdanm 92:4fc01daae5a5 6765 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6766 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6767 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6768 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6769
bogdanm 92:4fc01daae5a5 6770 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
bogdanm 92:4fc01daae5a5 6771 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6772 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6773
bogdanm 92:4fc01daae5a5 6774 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
bogdanm 92:4fc01daae5a5 6775 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 92:4fc01daae5a5 6776 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 92:4fc01daae5a5 6777 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
bogdanm 92:4fc01daae5a5 6778 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 92:4fc01daae5a5 6779 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 92:4fc01daae5a5 6780 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 92:4fc01daae5a5 6781 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
bogdanm 92:4fc01daae5a5 6782 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 92:4fc01daae5a5 6783 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
bogdanm 92:4fc01daae5a5 6784 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
bogdanm 92:4fc01daae5a5 6785 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
bogdanm 92:4fc01daae5a5 6786
bogdanm 92:4fc01daae5a5 6787 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
bogdanm 92:4fc01daae5a5 6788 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
bogdanm 92:4fc01daae5a5 6789 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
bogdanm 92:4fc01daae5a5 6790
bogdanm 92:4fc01daae5a5 6791 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
bogdanm 92:4fc01daae5a5 6792 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
bogdanm 92:4fc01daae5a5 6793 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
bogdanm 92:4fc01daae5a5 6794 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
bogdanm 92:4fc01daae5a5 6795 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
bogdanm 92:4fc01daae5a5 6796
bogdanm 92:4fc01daae5a5 6797 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 92:4fc01daae5a5 6798 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6799 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6800 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
bogdanm 92:4fc01daae5a5 6801
bogdanm 92:4fc01daae5a5 6802 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
bogdanm 92:4fc01daae5a5 6803 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6804 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6805 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6806 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6807 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
bogdanm 92:4fc01daae5a5 6808 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
bogdanm 92:4fc01daae5a5 6809 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
bogdanm 92:4fc01daae5a5 6810 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
bogdanm 92:4fc01daae5a5 6811 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
bogdanm 92:4fc01daae5a5 6812 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
bogdanm 92:4fc01daae5a5 6813
bogdanm 92:4fc01daae5a5 6814 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
bogdanm 92:4fc01daae5a5 6815 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
bogdanm 92:4fc01daae5a5 6816
bogdanm 92:4fc01daae5a5 6817 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
bogdanm 92:4fc01daae5a5 6818 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6819 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6820 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6821 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6822 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
bogdanm 92:4fc01daae5a5 6823 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
bogdanm 92:4fc01daae5a5 6824
bogdanm 92:4fc01daae5a5 6825 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 92:4fc01daae5a5 6826 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6827 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6828
bogdanm 92:4fc01daae5a5 6829 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
bogdanm 92:4fc01daae5a5 6830 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6831 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6832
bogdanm 92:4fc01daae5a5 6833 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
bogdanm 92:4fc01daae5a5 6834 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6835 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6836 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6837 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6838 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6839 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6840 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6841 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
bogdanm 92:4fc01daae5a5 6842 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
bogdanm 92:4fc01daae5a5 6843 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
bogdanm 92:4fc01daae5a5 6844
bogdanm 92:4fc01daae5a5 6845 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
bogdanm 92:4fc01daae5a5 6846
bogdanm 92:4fc01daae5a5 6847 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
bogdanm 92:4fc01daae5a5 6848 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6849 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6850 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6851 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6852 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6853 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6854 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6855
bogdanm 92:4fc01daae5a5 6856 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
bogdanm 92:4fc01daae5a5 6857 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6858 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6859 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 6860 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6861 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6862 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
bogdanm 92:4fc01daae5a5 6863 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6864
bogdanm 92:4fc01daae5a5 6865 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
bogdanm 92:4fc01daae5a5 6866 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6867 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6868 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
bogdanm 92:4fc01daae5a5 6869 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
bogdanm 92:4fc01daae5a5 6870
bogdanm 92:4fc01daae5a5 6871 /******************** Bit definition forUSB_OTG_HCINT register ********************/
bogdanm 92:4fc01daae5a5 6872 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
bogdanm 92:4fc01daae5a5 6873 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
bogdanm 92:4fc01daae5a5 6874 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
bogdanm 92:4fc01daae5a5 6875 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
bogdanm 92:4fc01daae5a5 6876 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
bogdanm 92:4fc01daae5a5 6877 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
bogdanm 92:4fc01daae5a5 6878 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
bogdanm 92:4fc01daae5a5 6879 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
bogdanm 92:4fc01daae5a5 6880 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
bogdanm 92:4fc01daae5a5 6881 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
bogdanm 92:4fc01daae5a5 6882 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
bogdanm 92:4fc01daae5a5 6883
bogdanm 92:4fc01daae5a5 6884 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
bogdanm 92:4fc01daae5a5 6885 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
bogdanm 92:4fc01daae5a5 6886 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
bogdanm 92:4fc01daae5a5 6887 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
bogdanm 92:4fc01daae5a5 6888 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
bogdanm 92:4fc01daae5a5 6889 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
bogdanm 92:4fc01daae5a5 6890 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
bogdanm 92:4fc01daae5a5 6891 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
bogdanm 92:4fc01daae5a5 6892 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
bogdanm 92:4fc01daae5a5 6893 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
bogdanm 92:4fc01daae5a5 6894 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
bogdanm 92:4fc01daae5a5 6895 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
bogdanm 92:4fc01daae5a5 6896
bogdanm 92:4fc01daae5a5 6897 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
bogdanm 92:4fc01daae5a5 6898 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
bogdanm 92:4fc01daae5a5 6899 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
bogdanm 92:4fc01daae5a5 6900 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
bogdanm 92:4fc01daae5a5 6901 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
bogdanm 92:4fc01daae5a5 6902 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
bogdanm 92:4fc01daae5a5 6903 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
bogdanm 92:4fc01daae5a5 6904 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
bogdanm 92:4fc01daae5a5 6905 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
bogdanm 92:4fc01daae5a5 6906 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
bogdanm 92:4fc01daae5a5 6907 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
bogdanm 92:4fc01daae5a5 6908 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
bogdanm 92:4fc01daae5a5 6909
bogdanm 92:4fc01daae5a5 6910 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
bogdanm 92:4fc01daae5a5 6911
bogdanm 92:4fc01daae5a5 6912 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 92:4fc01daae5a5 6913 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 92:4fc01daae5a5 6914 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
bogdanm 92:4fc01daae5a5 6915 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
bogdanm 92:4fc01daae5a5 6916 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 92:4fc01daae5a5 6917 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 92:4fc01daae5a5 6918 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
bogdanm 92:4fc01daae5a5 6919 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
bogdanm 92:4fc01daae5a5 6920 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6921 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6922
bogdanm 92:4fc01daae5a5 6923 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
bogdanm 92:4fc01daae5a5 6924 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
bogdanm 92:4fc01daae5a5 6925
bogdanm 92:4fc01daae5a5 6926 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
bogdanm 92:4fc01daae5a5 6927 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
bogdanm 92:4fc01daae5a5 6928
bogdanm 92:4fc01daae5a5 6929 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
bogdanm 92:4fc01daae5a5 6930 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
bogdanm 92:4fc01daae5a5 6931
bogdanm 92:4fc01daae5a5 6932 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
bogdanm 92:4fc01daae5a5 6933 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
bogdanm 92:4fc01daae5a5 6934 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
bogdanm 92:4fc01daae5a5 6935
bogdanm 92:4fc01daae5a5 6936 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
bogdanm 92:4fc01daae5a5 6937
bogdanm 92:4fc01daae5a5 6938 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6939 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
bogdanm 92:4fc01daae5a5 6940 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
bogdanm 92:4fc01daae5a5 6941 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
bogdanm 92:4fc01daae5a5 6942 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
bogdanm 92:4fc01daae5a5 6943 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 92:4fc01daae5a5 6944 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6945 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6946 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
bogdanm 92:4fc01daae5a5 6947 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
bogdanm 92:4fc01daae5a5 6948 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
bogdanm 92:4fc01daae5a5 6949 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
bogdanm 92:4fc01daae5a5 6950 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
bogdanm 92:4fc01daae5a5 6951 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
bogdanm 92:4fc01daae5a5 6952
bogdanm 92:4fc01daae5a5 6953 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
bogdanm 92:4fc01daae5a5 6954 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
bogdanm 92:4fc01daae5a5 6955 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
bogdanm 92:4fc01daae5a5 6956 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
bogdanm 92:4fc01daae5a5 6957 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
bogdanm 92:4fc01daae5a5 6958 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
bogdanm 92:4fc01daae5a5 6959 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
bogdanm 92:4fc01daae5a5 6960
bogdanm 92:4fc01daae5a5 6961 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
bogdanm 92:4fc01daae5a5 6962
bogdanm 92:4fc01daae5a5 6963 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 92:4fc01daae5a5 6964 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 92:4fc01daae5a5 6965
bogdanm 92:4fc01daae5a5 6966 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
bogdanm 92:4fc01daae5a5 6967 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6968 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6969
bogdanm 92:4fc01daae5a5 6970 /******************** Bit definition for PCGCCTL register ********************/
bogdanm 92:4fc01daae5a5 6971 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
bogdanm 92:4fc01daae5a5 6972 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 6973 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6974
bogdanm 92:4fc01daae5a5 6975 /**
bogdanm 92:4fc01daae5a5 6976 * @}
bogdanm 92:4fc01daae5a5 6977 */
bogdanm 92:4fc01daae5a5 6978
bogdanm 92:4fc01daae5a5 6979 /**
bogdanm 92:4fc01daae5a5 6980 * @}
bogdanm 92:4fc01daae5a5 6981 */
bogdanm 92:4fc01daae5a5 6982
bogdanm 92:4fc01daae5a5 6983 /** @addtogroup Exported_macros
bogdanm 92:4fc01daae5a5 6984 * @{
bogdanm 92:4fc01daae5a5 6985 */
bogdanm 92:4fc01daae5a5 6986
bogdanm 92:4fc01daae5a5 6987 /******************************* ADC Instances ********************************/
bogdanm 92:4fc01daae5a5 6988 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
bogdanm 92:4fc01daae5a5 6989 ((INSTANCE) == ADC2) || \
bogdanm 92:4fc01daae5a5 6990 ((INSTANCE) == ADC3))
bogdanm 92:4fc01daae5a5 6991
bogdanm 92:4fc01daae5a5 6992 /******************************* CAN Instances ********************************/
bogdanm 92:4fc01daae5a5 6993 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
bogdanm 92:4fc01daae5a5 6994 ((INSTANCE) == CAN2))
bogdanm 92:4fc01daae5a5 6995
bogdanm 92:4fc01daae5a5 6996 /******************************* CRC Instances ********************************/
bogdanm 92:4fc01daae5a5 6997 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 92:4fc01daae5a5 6998
bogdanm 92:4fc01daae5a5 6999 /******************************* DAC Instances ********************************/
bogdanm 92:4fc01daae5a5 7000 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
bogdanm 92:4fc01daae5a5 7001
bogdanm 92:4fc01daae5a5 7002 /******************************** DMA Instances *******************************/
bogdanm 92:4fc01daae5a5 7003 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
bogdanm 92:4fc01daae5a5 7004 ((INSTANCE) == DMA1_Stream1) || \
bogdanm 92:4fc01daae5a5 7005 ((INSTANCE) == DMA1_Stream2) || \
bogdanm 92:4fc01daae5a5 7006 ((INSTANCE) == DMA1_Stream3) || \
bogdanm 92:4fc01daae5a5 7007 ((INSTANCE) == DMA1_Stream4) || \
bogdanm 92:4fc01daae5a5 7008 ((INSTANCE) == DMA1_Stream5) || \
bogdanm 92:4fc01daae5a5 7009 ((INSTANCE) == DMA1_Stream6) || \
bogdanm 92:4fc01daae5a5 7010 ((INSTANCE) == DMA1_Stream7) || \
bogdanm 92:4fc01daae5a5 7011 ((INSTANCE) == DMA2_Stream0) || \
bogdanm 92:4fc01daae5a5 7012 ((INSTANCE) == DMA2_Stream1) || \
bogdanm 92:4fc01daae5a5 7013 ((INSTANCE) == DMA2_Stream2) || \
bogdanm 92:4fc01daae5a5 7014 ((INSTANCE) == DMA2_Stream3) || \
bogdanm 92:4fc01daae5a5 7015 ((INSTANCE) == DMA2_Stream4) || \
bogdanm 92:4fc01daae5a5 7016 ((INSTANCE) == DMA2_Stream5) || \
bogdanm 92:4fc01daae5a5 7017 ((INSTANCE) == DMA2_Stream6) || \
bogdanm 92:4fc01daae5a5 7018 ((INSTANCE) == DMA2_Stream7))
bogdanm 92:4fc01daae5a5 7019
bogdanm 92:4fc01daae5a5 7020 /******************************* GPIO Instances *******************************/
bogdanm 92:4fc01daae5a5 7021 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 92:4fc01daae5a5 7022 ((INSTANCE) == GPIOB) || \
bogdanm 92:4fc01daae5a5 7023 ((INSTANCE) == GPIOC) || \
bogdanm 92:4fc01daae5a5 7024 ((INSTANCE) == GPIOD) || \
bogdanm 92:4fc01daae5a5 7025 ((INSTANCE) == GPIOE) || \
bogdanm 92:4fc01daae5a5 7026 ((INSTANCE) == GPIOF) || \
bogdanm 92:4fc01daae5a5 7027 ((INSTANCE) == GPIOG) || \
bogdanm 92:4fc01daae5a5 7028 ((INSTANCE) == GPIOH) || \
bogdanm 92:4fc01daae5a5 7029 ((INSTANCE) == GPIOI))
bogdanm 92:4fc01daae5a5 7030
bogdanm 92:4fc01daae5a5 7031 /******************************** I2C Instances *******************************/
bogdanm 92:4fc01daae5a5 7032 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
bogdanm 92:4fc01daae5a5 7033 ((INSTANCE) == I2C2) || \
bogdanm 92:4fc01daae5a5 7034 ((INSTANCE) == I2C3))
bogdanm 92:4fc01daae5a5 7035
bogdanm 92:4fc01daae5a5 7036 /******************************** I2S Instances *******************************/
bogdanm 92:4fc01daae5a5 7037 #define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
bogdanm 92:4fc01daae5a5 7038 ((INSTANCE) == SPI3))
bogdanm 92:4fc01daae5a5 7039
bogdanm 92:4fc01daae5a5 7040 /*************************** I2S Extended Instances ***************************/
bogdanm 92:4fc01daae5a5 7041 #define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
bogdanm 92:4fc01daae5a5 7042 ((INSTANCE) == SPI3) || \
bogdanm 92:4fc01daae5a5 7043 ((INSTANCE) == I2S2ext) || \
bogdanm 92:4fc01daae5a5 7044 ((INSTANCE) == I2S3ext))
bogdanm 92:4fc01daae5a5 7045
bogdanm 92:4fc01daae5a5 7046 /******************************* RNG Instances ********************************/
bogdanm 92:4fc01daae5a5 7047 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
bogdanm 92:4fc01daae5a5 7048
bogdanm 92:4fc01daae5a5 7049 /****************************** RTC Instances *********************************/
bogdanm 92:4fc01daae5a5 7050 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 92:4fc01daae5a5 7051
bogdanm 92:4fc01daae5a5 7052 /******************************** SPI Instances *******************************/
bogdanm 92:4fc01daae5a5 7053 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 92:4fc01daae5a5 7054 ((INSTANCE) == SPI2) || \
bogdanm 92:4fc01daae5a5 7055 ((INSTANCE) == SPI3))
bogdanm 92:4fc01daae5a5 7056
bogdanm 92:4fc01daae5a5 7057 /*************************** SPI Extended Instances ***************************/
bogdanm 92:4fc01daae5a5 7058 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 92:4fc01daae5a5 7059 ((INSTANCE) == SPI2) || \
bogdanm 92:4fc01daae5a5 7060 ((INSTANCE) == SPI3) || \
bogdanm 92:4fc01daae5a5 7061 ((INSTANCE) == I2S2ext) || \
bogdanm 92:4fc01daae5a5 7062 ((INSTANCE) == I2S3ext))
bogdanm 92:4fc01daae5a5 7063
bogdanm 92:4fc01daae5a5 7064 /****************** TIM Instances : All supported instances *******************/
bogdanm 92:4fc01daae5a5 7065 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7066 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7067 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7068 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7069 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7070 ((INSTANCE) == TIM6) || \
bogdanm 92:4fc01daae5a5 7071 ((INSTANCE) == TIM7) || \
bogdanm 92:4fc01daae5a5 7072 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7073 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7074 ((INSTANCE) == TIM10) || \
bogdanm 92:4fc01daae5a5 7075 ((INSTANCE) == TIM11) || \
bogdanm 92:4fc01daae5a5 7076 ((INSTANCE) == TIM12) || \
bogdanm 92:4fc01daae5a5 7077 ((INSTANCE) == TIM13) || \
bogdanm 92:4fc01daae5a5 7078 ((INSTANCE) == TIM14))
bogdanm 92:4fc01daae5a5 7079
bogdanm 92:4fc01daae5a5 7080 /************* TIM Instances : at least 1 capture/compare channel *************/
bogdanm 92:4fc01daae5a5 7081 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7082 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7083 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7084 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7085 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7086 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7087 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7088 ((INSTANCE) == TIM10) || \
bogdanm 92:4fc01daae5a5 7089 ((INSTANCE) == TIM11) || \
bogdanm 92:4fc01daae5a5 7090 ((INSTANCE) == TIM12) || \
bogdanm 92:4fc01daae5a5 7091 ((INSTANCE) == TIM13) || \
bogdanm 92:4fc01daae5a5 7092 ((INSTANCE) == TIM14))
bogdanm 92:4fc01daae5a5 7093
bogdanm 92:4fc01daae5a5 7094 /************ TIM Instances : at least 2 capture/compare channels *************/
bogdanm 92:4fc01daae5a5 7095 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7096 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7097 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7098 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7099 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7100 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7101 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7102 ((INSTANCE) == TIM12))
bogdanm 92:4fc01daae5a5 7103
bogdanm 92:4fc01daae5a5 7104 /************ TIM Instances : at least 3 capture/compare channels *************/
bogdanm 92:4fc01daae5a5 7105 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7106 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7107 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7108 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7109 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7110 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7111
bogdanm 92:4fc01daae5a5 7112 /************ TIM Instances : at least 4 capture/compare channels *************/
bogdanm 92:4fc01daae5a5 7113 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7114 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7115 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7116 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7117 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7118 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7119
bogdanm 92:4fc01daae5a5 7120 /******************** TIM Instances : Advanced-control timers *****************/
bogdanm 92:4fc01daae5a5 7121 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7122 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7123
bogdanm 92:4fc01daae5a5 7124 /******************* TIM Instances : Timer input XOR function *****************/
bogdanm 92:4fc01daae5a5 7125 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7126 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7127 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7128 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7129 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7130 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7131
bogdanm 92:4fc01daae5a5 7132 /****************** TIM Instances : DMA requests generation (UDE) *************/
bogdanm 92:4fc01daae5a5 7133 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7134 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7135 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7136 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7137 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7138 ((INSTANCE) == TIM6) || \
bogdanm 92:4fc01daae5a5 7139 ((INSTANCE) == TIM7) || \
bogdanm 92:4fc01daae5a5 7140 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7141
bogdanm 92:4fc01daae5a5 7142 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
bogdanm 92:4fc01daae5a5 7143 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7144 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7145 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7146 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7147 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7148 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7149
bogdanm 92:4fc01daae5a5 7150 /************ TIM Instances : DMA requests generation (COMDE) *****************/
bogdanm 92:4fc01daae5a5 7151 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7152 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7153 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7154 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7155 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7156 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7157
bogdanm 92:4fc01daae5a5 7158 /******************** TIM Instances : DMA burst feature ***********************/
bogdanm 92:4fc01daae5a5 7159 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7160 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7161 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7162 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7163 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7164 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7165
bogdanm 92:4fc01daae5a5 7166 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
bogdanm 92:4fc01daae5a5 7167 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7168 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7169 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7170 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7171 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7172 ((INSTANCE) == TIM6) || \
bogdanm 92:4fc01daae5a5 7173 ((INSTANCE) == TIM7) || \
bogdanm 92:4fc01daae5a5 7174 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7175 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7176 ((INSTANCE) == TIM12))
bogdanm 92:4fc01daae5a5 7177
bogdanm 92:4fc01daae5a5 7178 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
bogdanm 92:4fc01daae5a5 7179 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7180 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7181 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7182 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7183 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7184 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7185 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7186 ((INSTANCE) == TIM12))
bogdanm 92:4fc01daae5a5 7187
bogdanm 92:4fc01daae5a5 7188 /********************** TIM Instances : 32 bit Counter ************************/
bogdanm 92:4fc01daae5a5 7189 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7190 ((INSTANCE) == TIM5))
bogdanm 92:4fc01daae5a5 7191
bogdanm 92:4fc01daae5a5 7192 /***************** TIM Instances : external trigger input availabe ************/
bogdanm 92:4fc01daae5a5 7193 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7194 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7195 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7196 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7197 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7198 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7199
bogdanm 92:4fc01daae5a5 7200 /****************** TIM Instances : remapping capability **********************/
bogdanm 92:4fc01daae5a5 7201 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7202 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7203 ((INSTANCE) == TIM11))
bogdanm 92:4fc01daae5a5 7204
bogdanm 92:4fc01daae5a5 7205 /******************* TIM Instances : output(s) available **********************/
bogdanm 92:4fc01daae5a5 7206 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 92:4fc01daae5a5 7207 ((((INSTANCE) == TIM1) && \
bogdanm 92:4fc01daae5a5 7208 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7209 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7210 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7211 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7212 || \
bogdanm 92:4fc01daae5a5 7213 (((INSTANCE) == TIM2) && \
bogdanm 92:4fc01daae5a5 7214 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7215 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7216 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7217 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7218 || \
bogdanm 92:4fc01daae5a5 7219 (((INSTANCE) == TIM3) && \
bogdanm 92:4fc01daae5a5 7220 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7221 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7222 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7223 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7224 || \
bogdanm 92:4fc01daae5a5 7225 (((INSTANCE) == TIM4) && \
bogdanm 92:4fc01daae5a5 7226 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7227 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7228 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7229 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7230 || \
bogdanm 92:4fc01daae5a5 7231 (((INSTANCE) == TIM5) && \
bogdanm 92:4fc01daae5a5 7232 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7233 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7234 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7235 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7236 || \
bogdanm 92:4fc01daae5a5 7237 (((INSTANCE) == TIM8) && \
bogdanm 92:4fc01daae5a5 7238 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7239 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7240 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7241 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7242 || \
bogdanm 92:4fc01daae5a5 7243 (((INSTANCE) == TIM9) && \
bogdanm 92:4fc01daae5a5 7244 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7245 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 92:4fc01daae5a5 7246 || \
bogdanm 92:4fc01daae5a5 7247 (((INSTANCE) == TIM10) && \
bogdanm 92:4fc01daae5a5 7248 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 92:4fc01daae5a5 7249 || \
bogdanm 92:4fc01daae5a5 7250 (((INSTANCE) == TIM11) && \
bogdanm 92:4fc01daae5a5 7251 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 92:4fc01daae5a5 7252 || \
bogdanm 92:4fc01daae5a5 7253 (((INSTANCE) == TIM12) && \
bogdanm 92:4fc01daae5a5 7254 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7255 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 92:4fc01daae5a5 7256 || \
bogdanm 92:4fc01daae5a5 7257 (((INSTANCE) == TIM13) && \
bogdanm 92:4fc01daae5a5 7258 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 92:4fc01daae5a5 7259 || \
bogdanm 92:4fc01daae5a5 7260 (((INSTANCE) == TIM14) && \
bogdanm 92:4fc01daae5a5 7261 (((CHANNEL) == TIM_CHANNEL_1))))
bogdanm 92:4fc01daae5a5 7262
bogdanm 92:4fc01daae5a5 7263 /************ TIM Instances : complementary output(s) available ***************/
bogdanm 92:4fc01daae5a5 7264 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 92:4fc01daae5a5 7265 ((((INSTANCE) == TIM1) && \
bogdanm 92:4fc01daae5a5 7266 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7267 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7268 ((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm 92:4fc01daae5a5 7269 || \
bogdanm 92:4fc01daae5a5 7270 (((INSTANCE) == TIM8) && \
bogdanm 92:4fc01daae5a5 7271 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7272 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7273 ((CHANNEL) == TIM_CHANNEL_3))))
bogdanm 92:4fc01daae5a5 7274
bogdanm 92:4fc01daae5a5 7275 /******************** USART Instances : Synchronous mode **********************/
bogdanm 92:4fc01daae5a5 7276 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7277 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7278 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7279 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7280
bogdanm 92:4fc01daae5a5 7281 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 92:4fc01daae5a5 7282 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7283 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7284 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7285 ((INSTANCE) == UART4) || \
bogdanm 92:4fc01daae5a5 7286 ((INSTANCE) == UART5) || \
bogdanm 92:4fc01daae5a5 7287 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7288
bogdanm 92:4fc01daae5a5 7289 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 92:4fc01daae5a5 7290 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7291 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7292 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7293 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7294
bogdanm 92:4fc01daae5a5 7295 /********************* UART Instances : Smard card mode ***********************/
bogdanm 92:4fc01daae5a5 7296 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7297 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7298 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7299 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7300
bogdanm 92:4fc01daae5a5 7301 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 92:4fc01daae5a5 7302 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7303 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7304 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7305 ((INSTANCE) == UART4) || \
bogdanm 92:4fc01daae5a5 7306 ((INSTANCE) == UART5) || \
bogdanm 92:4fc01daae5a5 7307 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7308
bogdanm 92:4fc01daae5a5 7309 /****************************** IWDG Instances ********************************/
bogdanm 92:4fc01daae5a5 7310 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 92:4fc01daae5a5 7311
bogdanm 92:4fc01daae5a5 7312 /****************************** WWDG Instances ********************************/
bogdanm 92:4fc01daae5a5 7313 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 92:4fc01daae5a5 7314
bogdanm 92:4fc01daae5a5 7315 /******************************************************************************/
bogdanm 92:4fc01daae5a5 7316 /* For a painless codes migration between the STM32F4xx device product */
bogdanm 92:4fc01daae5a5 7317 /* lines, the aliases defined below are put in place to overcome the */
bogdanm 92:4fc01daae5a5 7318 /* differences in the interrupt handlers and IRQn definitions. */
bogdanm 92:4fc01daae5a5 7319 /* No need to update developed interrupt code when moving across */
bogdanm 92:4fc01daae5a5 7320 /* product lines within the same STM32F4 Family */
bogdanm 92:4fc01daae5a5 7321 /******************************************************************************/
bogdanm 92:4fc01daae5a5 7322
bogdanm 92:4fc01daae5a5 7323 /* Aliases for __IRQn */
bogdanm 92:4fc01daae5a5 7324 #define FMC_IRQn FSMC_IRQn
bogdanm 92:4fc01daae5a5 7325
bogdanm 92:4fc01daae5a5 7326 /* Aliases for __IRQHandler */
bogdanm 92:4fc01daae5a5 7327 #define FMC_IRQHandler FSMC_IRQHandler
bogdanm 92:4fc01daae5a5 7328
bogdanm 92:4fc01daae5a5 7329 /**
bogdanm 92:4fc01daae5a5 7330 * @}
bogdanm 92:4fc01daae5a5 7331 */
bogdanm 92:4fc01daae5a5 7332
bogdanm 92:4fc01daae5a5 7333 /**
bogdanm 92:4fc01daae5a5 7334 * @}
bogdanm 92:4fc01daae5a5 7335 */
bogdanm 92:4fc01daae5a5 7336
bogdanm 92:4fc01daae5a5 7337 /**
bogdanm 92:4fc01daae5a5 7338 * @}
bogdanm 92:4fc01daae5a5 7339 */
bogdanm 92:4fc01daae5a5 7340
bogdanm 92:4fc01daae5a5 7341 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 7342 }
bogdanm 92:4fc01daae5a5 7343 #endif /* __cplusplus */
bogdanm 92:4fc01daae5a5 7344
bogdanm 92:4fc01daae5a5 7345 #endif /* __STM32F405xx_H */
bogdanm 92:4fc01daae5a5 7346
bogdanm 92:4fc01daae5a5 7347
bogdanm 92:4fc01daae5a5 7348
bogdanm 92:4fc01daae5a5 7349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/