frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_NUCLEO_F411RE/stm32f4xx_ll_fmc.h@86:04dd9b1680ae, 2014-07-02 (annotated)

Committer:
bogdanm
Date:
Wed Jul 02 13:22:23 2014 +0100
Revision:
86:04dd9b1680ae
Release 86 of the mbed library



Main changes:





- bug fixes in various backends

- mbed "error" replaced by assert logic (mbed_assert)

- new ST Nucleo targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f4xx_ll_fmc.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.1.0
bogdanm 86:04dd9b1680ae 6 * @date 19-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of FMC HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F4xx_LL_FMC_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F4xx_LL_FMC_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 47
bogdanm 86:04dd9b1680ae 48 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 49 #include "stm32f4xx_hal_def.h"
bogdanm 86:04dd9b1680ae 50
bogdanm 86:04dd9b1680ae 51 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 86:04dd9b1680ae 52 * @{
bogdanm 86:04dd9b1680ae 53 */
bogdanm 86:04dd9b1680ae 54
bogdanm 86:04dd9b1680ae 55 /** @addtogroup FMC
bogdanm 86:04dd9b1680ae 56 * @{
bogdanm 86:04dd9b1680ae 57 */
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59 /* Exported typedef ----------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 60 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
bogdanm 86:04dd9b1680ae 61 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
bogdanm 86:04dd9b1680ae 62 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
bogdanm 86:04dd9b1680ae 63 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
bogdanm 86:04dd9b1680ae 64 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
bogdanm 86:04dd9b1680ae 65
bogdanm 86:04dd9b1680ae 66 #define FMC_NORSRAM_DEVICE FMC_Bank1
bogdanm 86:04dd9b1680ae 67 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
bogdanm 86:04dd9b1680ae 68 #define FMC_NAND_DEVICE FMC_Bank2_3
bogdanm 86:04dd9b1680ae 69 #define FMC_PCCARD_DEVICE FMC_Bank4
bogdanm 86:04dd9b1680ae 70 #define FMC_SDRAM_DEVICE FMC_Bank5_6
bogdanm 86:04dd9b1680ae 71
bogdanm 86:04dd9b1680ae 72 /**
bogdanm 86:04dd9b1680ae 73 * @brief FMC_NORSRAM Configuration Structure definition
bogdanm 86:04dd9b1680ae 74 */
bogdanm 86:04dd9b1680ae 75 typedef struct
bogdanm 86:04dd9b1680ae 76 {
bogdanm 86:04dd9b1680ae 77 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm 86:04dd9b1680ae 78 This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm 86:04dd9b1680ae 79
bogdanm 86:04dd9b1680ae 80 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm 86:04dd9b1680ae 81 multiplexed on the data bus or not.
bogdanm 86:04dd9b1680ae 82 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm 86:04dd9b1680ae 83
bogdanm 86:04dd9b1680ae 84 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 86:04dd9b1680ae 85 the corresponding memory device.
bogdanm 86:04dd9b1680ae 86 This parameter can be a value of @ref FMC_Memory_Type */
bogdanm 86:04dd9b1680ae 87
bogdanm 86:04dd9b1680ae 88 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 86:04dd9b1680ae 89 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm 86:04dd9b1680ae 90
bogdanm 86:04dd9b1680ae 91 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 86:04dd9b1680ae 92 valid only with synchronous burst Flash memories.
bogdanm 86:04dd9b1680ae 93 This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm 86:04dd9b1680ae 94
bogdanm 86:04dd9b1680ae 95 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 86:04dd9b1680ae 96 the Flash memory in burst mode.
bogdanm 86:04dd9b1680ae 97 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm 86:04dd9b1680ae 98
bogdanm 86:04dd9b1680ae 99 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 86:04dd9b1680ae 100 memory, valid only when accessing Flash memories in burst mode.
bogdanm 86:04dd9b1680ae 101 This parameter can be a value of @ref FMC_Wrap_Mode */
bogdanm 86:04dd9b1680ae 102
bogdanm 86:04dd9b1680ae 103 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 86:04dd9b1680ae 104 clock cycle before the wait state or during the wait state,
bogdanm 86:04dd9b1680ae 105 valid only when accessing memories in burst mode.
bogdanm 86:04dd9b1680ae 106 This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm 86:04dd9b1680ae 107
bogdanm 86:04dd9b1680ae 108 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
bogdanm 86:04dd9b1680ae 109 This parameter can be a value of @ref FMC_Write_Operation */
bogdanm 86:04dd9b1680ae 110
bogdanm 86:04dd9b1680ae 111 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm 86:04dd9b1680ae 112 signal, valid for Flash memory access in burst mode.
bogdanm 86:04dd9b1680ae 113 This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm 86:04dd9b1680ae 114
bogdanm 86:04dd9b1680ae 115 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 86:04dd9b1680ae 116 This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm 86:04dd9b1680ae 117
bogdanm 86:04dd9b1680ae 118 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 86:04dd9b1680ae 119 valid only with asynchronous Flash memories.
bogdanm 86:04dd9b1680ae 120 This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm 86:04dd9b1680ae 121
bogdanm 86:04dd9b1680ae 122 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 86:04dd9b1680ae 123 This parameter can be a value of @ref FMC_Write_Burst */
bogdanm 86:04dd9b1680ae 124
bogdanm 86:04dd9b1680ae 125 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
bogdanm 86:04dd9b1680ae 126 This parameter is only enabled through the FMC_BCR1 register, and don't care
bogdanm 86:04dd9b1680ae 127 through FMC_BCR2..4 registers.
bogdanm 86:04dd9b1680ae 128 This parameter can be a value of @ref FMC_Continous_Clock */
bogdanm 86:04dd9b1680ae 129
bogdanm 86:04dd9b1680ae 130 }FMC_NORSRAM_InitTypeDef;
bogdanm 86:04dd9b1680ae 131
bogdanm 86:04dd9b1680ae 132 /**
bogdanm 86:04dd9b1680ae 133 * @brief FMC_NORSRAM Timing parameters structure definition
bogdanm 86:04dd9b1680ae 134 */
bogdanm 86:04dd9b1680ae 135 typedef struct
bogdanm 86:04dd9b1680ae 136 {
bogdanm 86:04dd9b1680ae 137 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 86:04dd9b1680ae 138 the duration of the address setup time.
bogdanm 86:04dd9b1680ae 139 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 86:04dd9b1680ae 140 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 86:04dd9b1680ae 141
bogdanm 86:04dd9b1680ae 142 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 86:04dd9b1680ae 143 the duration of the address hold time.
bogdanm 86:04dd9b1680ae 144 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm 86:04dd9b1680ae 145 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 86:04dd9b1680ae 146
bogdanm 86:04dd9b1680ae 147 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 86:04dd9b1680ae 148 the duration of the data setup time.
bogdanm 86:04dd9b1680ae 149 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm 86:04dd9b1680ae 150 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm 86:04dd9b1680ae 151 NOR Flash memories. */
bogdanm 86:04dd9b1680ae 152
bogdanm 86:04dd9b1680ae 153 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 86:04dd9b1680ae 154 the duration of the bus turnaround.
bogdanm 86:04dd9b1680ae 155 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 86:04dd9b1680ae 156 @note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm 86:04dd9b1680ae 157
bogdanm 86:04dd9b1680ae 158 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm 86:04dd9b1680ae 159 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm 86:04dd9b1680ae 160 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm 86:04dd9b1680ae 161 accesses. */
bogdanm 86:04dd9b1680ae 162
bogdanm 86:04dd9b1680ae 163 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 86:04dd9b1680ae 164 to the memory before getting the first data.
bogdanm 86:04dd9b1680ae 165 The parameter value depends on the memory type as shown below:
bogdanm 86:04dd9b1680ae 166 - It must be set to 0 in case of a CRAM
bogdanm 86:04dd9b1680ae 167 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 86:04dd9b1680ae 168 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm 86:04dd9b1680ae 169 with synchronous burst mode enable */
bogdanm 86:04dd9b1680ae 170
bogdanm 86:04dd9b1680ae 171 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 86:04dd9b1680ae 172 This parameter can be a value of @ref FMC_Access_Mode */
bogdanm 86:04dd9b1680ae 173 }FMC_NORSRAM_TimingTypeDef;
bogdanm 86:04dd9b1680ae 174
bogdanm 86:04dd9b1680ae 175 /**
bogdanm 86:04dd9b1680ae 176 * @brief FMC_NAND Configuration Structure definition
bogdanm 86:04dd9b1680ae 177 */
bogdanm 86:04dd9b1680ae 178 typedef struct
bogdanm 86:04dd9b1680ae 179 {
bogdanm 86:04dd9b1680ae 180 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm 86:04dd9b1680ae 181 This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm 86:04dd9b1680ae 182
bogdanm 86:04dd9b1680ae 183 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm 86:04dd9b1680ae 184 This parameter can be any value of @ref FMC_Wait_feature */
bogdanm 86:04dd9b1680ae 185
bogdanm 86:04dd9b1680ae 186 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 86:04dd9b1680ae 187 This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm 86:04dd9b1680ae 188
bogdanm 86:04dd9b1680ae 189 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm 86:04dd9b1680ae 190 This parameter can be any value of @ref FMC_ECC */
bogdanm 86:04dd9b1680ae 191
bogdanm 86:04dd9b1680ae 192 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm 86:04dd9b1680ae 193 This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm 86:04dd9b1680ae 194
bogdanm 86:04dd9b1680ae 195 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 86:04dd9b1680ae 196 delay between CLE low and RE low.
bogdanm 86:04dd9b1680ae 197 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 86:04dd9b1680ae 198
bogdanm 86:04dd9b1680ae 199 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 86:04dd9b1680ae 200 delay between ALE low and RE low.
bogdanm 86:04dd9b1680ae 201 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 86:04dd9b1680ae 202 }FMC_NAND_InitTypeDef;
bogdanm 86:04dd9b1680ae 203
bogdanm 86:04dd9b1680ae 204 /**
bogdanm 86:04dd9b1680ae 205 * @brief FMC_NAND_PCCARD Timing parameters structure definition
bogdanm 86:04dd9b1680ae 206 */
bogdanm 86:04dd9b1680ae 207 typedef struct
bogdanm 86:04dd9b1680ae 208 {
bogdanm 86:04dd9b1680ae 209 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm 86:04dd9b1680ae 210 the command assertion for NAND-Flash read or write access
bogdanm 86:04dd9b1680ae 211 to common/Attribute or I/O memory space (depending on
bogdanm 86:04dd9b1680ae 212 the memory space timing to be configured).
bogdanm 86:04dd9b1680ae 213 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 86:04dd9b1680ae 214
bogdanm 86:04dd9b1680ae 215 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm 86:04dd9b1680ae 216 command for NAND-Flash read or write access to
bogdanm 86:04dd9b1680ae 217 common/Attribute or I/O memory space (depending on the
bogdanm 86:04dd9b1680ae 218 memory space timing to be configured).
bogdanm 86:04dd9b1680ae 219 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 86:04dd9b1680ae 220
bogdanm 86:04dd9b1680ae 221 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm 86:04dd9b1680ae 222 (and data for write access) after the command de-assertion
bogdanm 86:04dd9b1680ae 223 for NAND-Flash read or write access to common/Attribute
bogdanm 86:04dd9b1680ae 224 or I/O memory space (depending on the memory space timing
bogdanm 86:04dd9b1680ae 225 to be configured).
bogdanm 86:04dd9b1680ae 226 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 86:04dd9b1680ae 227
bogdanm 86:04dd9b1680ae 228 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm 86:04dd9b1680ae 229 data bus is kept in HiZ after the start of a NAND-Flash
bogdanm 86:04dd9b1680ae 230 write access to common/Attribute or I/O memory space (depending
bogdanm 86:04dd9b1680ae 231 on the memory space timing to be configured).
bogdanm 86:04dd9b1680ae 232 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 86:04dd9b1680ae 233 }FMC_NAND_PCC_TimingTypeDef;
bogdanm 86:04dd9b1680ae 234
bogdanm 86:04dd9b1680ae 235 /**
bogdanm 86:04dd9b1680ae 236 * @brief FMC_NAND Configuration Structure definition
bogdanm 86:04dd9b1680ae 237 */
bogdanm 86:04dd9b1680ae 238 typedef struct
bogdanm 86:04dd9b1680ae 239 {
bogdanm 86:04dd9b1680ae 240 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm 86:04dd9b1680ae 241 This parameter can be any value of @ref FMC_Wait_feature */
bogdanm 86:04dd9b1680ae 242
bogdanm 86:04dd9b1680ae 243 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 86:04dd9b1680ae 244 delay between CLE low and RE low.
bogdanm 86:04dd9b1680ae 245 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 86:04dd9b1680ae 246
bogdanm 86:04dd9b1680ae 247 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 86:04dd9b1680ae 248 delay between ALE low and RE low.
bogdanm 86:04dd9b1680ae 249 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 86:04dd9b1680ae 250 }FMC_PCCARD_InitTypeDef;
bogdanm 86:04dd9b1680ae 251
bogdanm 86:04dd9b1680ae 252 /**
bogdanm 86:04dd9b1680ae 253 * @brief FMC_SDRAM Configuration Structure definition
bogdanm 86:04dd9b1680ae 254 */
bogdanm 86:04dd9b1680ae 255 typedef struct
bogdanm 86:04dd9b1680ae 256 {
bogdanm 86:04dd9b1680ae 257 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
bogdanm 86:04dd9b1680ae 258 This parameter can be a value of @ref FMC_SDRAM_Bank */
bogdanm 86:04dd9b1680ae 259
bogdanm 86:04dd9b1680ae 260 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
bogdanm 86:04dd9b1680ae 261 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
bogdanm 86:04dd9b1680ae 262
bogdanm 86:04dd9b1680ae 263 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
bogdanm 86:04dd9b1680ae 264 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
bogdanm 86:04dd9b1680ae 265
bogdanm 86:04dd9b1680ae 266 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
bogdanm 86:04dd9b1680ae 267 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
bogdanm 86:04dd9b1680ae 268
bogdanm 86:04dd9b1680ae 269 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
bogdanm 86:04dd9b1680ae 270 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
bogdanm 86:04dd9b1680ae 271
bogdanm 86:04dd9b1680ae 272 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
bogdanm 86:04dd9b1680ae 273 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
bogdanm 86:04dd9b1680ae 274
bogdanm 86:04dd9b1680ae 275 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
bogdanm 86:04dd9b1680ae 276 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
bogdanm 86:04dd9b1680ae 277
bogdanm 86:04dd9b1680ae 278 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
bogdanm 86:04dd9b1680ae 279 to disable the clock before changing frequency.
bogdanm 86:04dd9b1680ae 280 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
bogdanm 86:04dd9b1680ae 281
bogdanm 86:04dd9b1680ae 282 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
bogdanm 86:04dd9b1680ae 283 commands during the CAS latency and stores data in the Read FIFO.
bogdanm 86:04dd9b1680ae 284 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
bogdanm 86:04dd9b1680ae 285
bogdanm 86:04dd9b1680ae 286 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
bogdanm 86:04dd9b1680ae 287 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
bogdanm 86:04dd9b1680ae 288 }FMC_SDRAM_InitTypeDef;
bogdanm 86:04dd9b1680ae 289
bogdanm 86:04dd9b1680ae 290 /**
bogdanm 86:04dd9b1680ae 291 * @brief FMC_SDRAM Timing parameters structure definition
bogdanm 86:04dd9b1680ae 292 */
bogdanm 86:04dd9b1680ae 293 typedef struct
bogdanm 86:04dd9b1680ae 294 {
bogdanm 86:04dd9b1680ae 295 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
bogdanm 86:04dd9b1680ae 296 an active or Refresh command in number of memory clock cycles.
bogdanm 86:04dd9b1680ae 297 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm 86:04dd9b1680ae 298
bogdanm 86:04dd9b1680ae 299 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
bogdanm 86:04dd9b1680ae 300 issuing the Activate command in number of memory clock cycles.
bogdanm 86:04dd9b1680ae 301 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm 86:04dd9b1680ae 302
bogdanm 86:04dd9b1680ae 303 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
bogdanm 86:04dd9b1680ae 304 cycles.
bogdanm 86:04dd9b1680ae 305 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm 86:04dd9b1680ae 306
bogdanm 86:04dd9b1680ae 307 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
bogdanm 86:04dd9b1680ae 308 and the delay between two consecutive Refresh commands in number of
bogdanm 86:04dd9b1680ae 309 memory clock cycles.
bogdanm 86:04dd9b1680ae 310 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm 86:04dd9b1680ae 311
bogdanm 86:04dd9b1680ae 312 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
bogdanm 86:04dd9b1680ae 313 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm 86:04dd9b1680ae 314
bogdanm 86:04dd9b1680ae 315 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
bogdanm 86:04dd9b1680ae 316 in number of memory clock cycles.
bogdanm 86:04dd9b1680ae 317 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm 86:04dd9b1680ae 318
bogdanm 86:04dd9b1680ae 319 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
bogdanm 86:04dd9b1680ae 320 command in number of memory clock cycles.
bogdanm 86:04dd9b1680ae 321 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm 86:04dd9b1680ae 322 }FMC_SDRAM_TimingTypeDef;
bogdanm 86:04dd9b1680ae 323
bogdanm 86:04dd9b1680ae 324 /**
bogdanm 86:04dd9b1680ae 325 * @brief SDRAM command parameters structure definition
bogdanm 86:04dd9b1680ae 326 */
bogdanm 86:04dd9b1680ae 327 typedef struct
bogdanm 86:04dd9b1680ae 328 {
bogdanm 86:04dd9b1680ae 329 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
bogdanm 86:04dd9b1680ae 330 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
bogdanm 86:04dd9b1680ae 331
bogdanm 86:04dd9b1680ae 332 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
bogdanm 86:04dd9b1680ae 333 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
bogdanm 86:04dd9b1680ae 334
bogdanm 86:04dd9b1680ae 335 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
bogdanm 86:04dd9b1680ae 336 in auto refresh mode.
bogdanm 86:04dd9b1680ae 337 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm 86:04dd9b1680ae 338 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
bogdanm 86:04dd9b1680ae 339 }FMC_SDRAM_CommandTypeDef;
bogdanm 86:04dd9b1680ae 340
bogdanm 86:04dd9b1680ae 341 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 342
bogdanm 86:04dd9b1680ae 343 /** @defgroup FMC_NOR_SRAM_Controller
bogdanm 86:04dd9b1680ae 344 * @{
bogdanm 86:04dd9b1680ae 345 */
bogdanm 86:04dd9b1680ae 346
bogdanm 86:04dd9b1680ae 347 /** @defgroup FMC_NORSRAM_Bank
bogdanm 86:04dd9b1680ae 348 * @{
bogdanm 86:04dd9b1680ae 349 */
bogdanm 86:04dd9b1680ae 350 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 351 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 352 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 353 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm 86:04dd9b1680ae 354
bogdanm 86:04dd9b1680ae 355 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
bogdanm 86:04dd9b1680ae 356 ((BANK) == FMC_NORSRAM_BANK2) || \
bogdanm 86:04dd9b1680ae 357 ((BANK) == FMC_NORSRAM_BANK3) || \
bogdanm 86:04dd9b1680ae 358 ((BANK) == FMC_NORSRAM_BANK4))
bogdanm 86:04dd9b1680ae 359 /**
bogdanm 86:04dd9b1680ae 360 * @}
bogdanm 86:04dd9b1680ae 361 */
bogdanm 86:04dd9b1680ae 362
bogdanm 86:04dd9b1680ae 363 /** @defgroup FMC_Data_Address_Bus_Multiplexing
bogdanm 86:04dd9b1680ae 364 * @{
bogdanm 86:04dd9b1680ae 365 */
bogdanm 86:04dd9b1680ae 366 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 367 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 368
bogdanm 86:04dd9b1680ae 369 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
bogdanm 86:04dd9b1680ae 370 ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
bogdanm 86:04dd9b1680ae 371 /**
bogdanm 86:04dd9b1680ae 372 * @}
bogdanm 86:04dd9b1680ae 373 */
bogdanm 86:04dd9b1680ae 374
bogdanm 86:04dd9b1680ae 375 /** @defgroup FMC_Memory_Type
bogdanm 86:04dd9b1680ae 376 * @{
bogdanm 86:04dd9b1680ae 377 */
bogdanm 86:04dd9b1680ae 378 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 379 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 380 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 381
bogdanm 86:04dd9b1680ae 382 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
bogdanm 86:04dd9b1680ae 383 ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
bogdanm 86:04dd9b1680ae 384 ((MEMORY) == FMC_MEMORY_TYPE_NOR))
bogdanm 86:04dd9b1680ae 385 /**
bogdanm 86:04dd9b1680ae 386 * @}
bogdanm 86:04dd9b1680ae 387 */
bogdanm 86:04dd9b1680ae 388
bogdanm 86:04dd9b1680ae 389 /** @defgroup FMC_NORSRAM_Data_Width
bogdanm 86:04dd9b1680ae 390 * @{
bogdanm 86:04dd9b1680ae 391 */
bogdanm 86:04dd9b1680ae 392 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 393 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 394 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 395
bogdanm 86:04dd9b1680ae 396 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
bogdanm 86:04dd9b1680ae 397 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
bogdanm 86:04dd9b1680ae 398 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
bogdanm 86:04dd9b1680ae 399 /**
bogdanm 86:04dd9b1680ae 400 * @}
bogdanm 86:04dd9b1680ae 401 */
bogdanm 86:04dd9b1680ae 402
bogdanm 86:04dd9b1680ae 403 /** @defgroup FMC_NORSRAM_Flash_Access
bogdanm 86:04dd9b1680ae 404 * @{
bogdanm 86:04dd9b1680ae 405 */
bogdanm 86:04dd9b1680ae 406 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 407 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 408 /**
bogdanm 86:04dd9b1680ae 409 * @}
bogdanm 86:04dd9b1680ae 410 */
bogdanm 86:04dd9b1680ae 411
bogdanm 86:04dd9b1680ae 412 /** @defgroup FMC_Burst_Access_Mode
bogdanm 86:04dd9b1680ae 413 * @{
bogdanm 86:04dd9b1680ae 414 */
bogdanm 86:04dd9b1680ae 415 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 416 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 417
bogdanm 86:04dd9b1680ae 418 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
bogdanm 86:04dd9b1680ae 419 ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
bogdanm 86:04dd9b1680ae 420 /**
bogdanm 86:04dd9b1680ae 421 * @}
bogdanm 86:04dd9b1680ae 422 */
bogdanm 86:04dd9b1680ae 423
bogdanm 86:04dd9b1680ae 424
bogdanm 86:04dd9b1680ae 425 /** @defgroup FMC_Wait_Signal_Polarity
bogdanm 86:04dd9b1680ae 426 * @{
bogdanm 86:04dd9b1680ae 427 */
bogdanm 86:04dd9b1680ae 428 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 429 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 430
bogdanm 86:04dd9b1680ae 431 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
bogdanm 86:04dd9b1680ae 432 ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
bogdanm 86:04dd9b1680ae 433 /**
bogdanm 86:04dd9b1680ae 434 * @}
bogdanm 86:04dd9b1680ae 435 */
bogdanm 86:04dd9b1680ae 436
bogdanm 86:04dd9b1680ae 437 /** @defgroup FMC_Wrap_Mode
bogdanm 86:04dd9b1680ae 438 * @{
bogdanm 86:04dd9b1680ae 439 */
bogdanm 86:04dd9b1680ae 440 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 441 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 442
bogdanm 86:04dd9b1680ae 443 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
bogdanm 86:04dd9b1680ae 444 ((MODE) == FMC_WRAP_MODE_ENABLE))
bogdanm 86:04dd9b1680ae 445 /**
bogdanm 86:04dd9b1680ae 446 * @}
bogdanm 86:04dd9b1680ae 447 */
bogdanm 86:04dd9b1680ae 448
bogdanm 86:04dd9b1680ae 449 /** @defgroup FMC_Wait_Timing
bogdanm 86:04dd9b1680ae 450 * @{
bogdanm 86:04dd9b1680ae 451 */
bogdanm 86:04dd9b1680ae 452 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 453 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 454
bogdanm 86:04dd9b1680ae 455 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
bogdanm 86:04dd9b1680ae 456 ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
bogdanm 86:04dd9b1680ae 457 /**
bogdanm 86:04dd9b1680ae 458 * @}
bogdanm 86:04dd9b1680ae 459 */
bogdanm 86:04dd9b1680ae 460
bogdanm 86:04dd9b1680ae 461 /** @defgroup FMC_Write_Operation
bogdanm 86:04dd9b1680ae 462 * @{
bogdanm 86:04dd9b1680ae 463 */
bogdanm 86:04dd9b1680ae 464 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 465 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 466
bogdanm 86:04dd9b1680ae 467 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
bogdanm 86:04dd9b1680ae 468 ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
bogdanm 86:04dd9b1680ae 469 /**
bogdanm 86:04dd9b1680ae 470 * @}
bogdanm 86:04dd9b1680ae 471 */
bogdanm 86:04dd9b1680ae 472
bogdanm 86:04dd9b1680ae 473 /** @defgroup FMC_Wait_Signal
bogdanm 86:04dd9b1680ae 474 * @{
bogdanm 86:04dd9b1680ae 475 */
bogdanm 86:04dd9b1680ae 476 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 477 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 478
bogdanm 86:04dd9b1680ae 479 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
bogdanm 86:04dd9b1680ae 480 ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
bogdanm 86:04dd9b1680ae 481 /**
bogdanm 86:04dd9b1680ae 482 * @}
bogdanm 86:04dd9b1680ae 483 */
bogdanm 86:04dd9b1680ae 484
bogdanm 86:04dd9b1680ae 485 /** @defgroup FMC_Extended_Mode
bogdanm 86:04dd9b1680ae 486 * @{
bogdanm 86:04dd9b1680ae 487 */
bogdanm 86:04dd9b1680ae 488 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 489 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 490
bogdanm 86:04dd9b1680ae 491 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
bogdanm 86:04dd9b1680ae 492 ((MODE) == FMC_EXTENDED_MODE_ENABLE))
bogdanm 86:04dd9b1680ae 493 /**
bogdanm 86:04dd9b1680ae 494 * @}
bogdanm 86:04dd9b1680ae 495 */
bogdanm 86:04dd9b1680ae 496
bogdanm 86:04dd9b1680ae 497 /** @defgroup FMC_AsynchronousWait
bogdanm 86:04dd9b1680ae 498 * @{
bogdanm 86:04dd9b1680ae 499 */
bogdanm 86:04dd9b1680ae 500 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 501 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 502
bogdanm 86:04dd9b1680ae 503 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
bogdanm 86:04dd9b1680ae 504 ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
bogdanm 86:04dd9b1680ae 505 /**
bogdanm 86:04dd9b1680ae 506 * @}
bogdanm 86:04dd9b1680ae 507 */
bogdanm 86:04dd9b1680ae 508
bogdanm 86:04dd9b1680ae 509 /** @defgroup FMC_Write_Burst
bogdanm 86:04dd9b1680ae 510 * @{
bogdanm 86:04dd9b1680ae 511 */
bogdanm 86:04dd9b1680ae 512 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 513 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 514
bogdanm 86:04dd9b1680ae 515 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
bogdanm 86:04dd9b1680ae 516 ((BURST) == FMC_WRITE_BURST_ENABLE))
bogdanm 86:04dd9b1680ae 517 /**
bogdanm 86:04dd9b1680ae 518 * @}
bogdanm 86:04dd9b1680ae 519 */
bogdanm 86:04dd9b1680ae 520
bogdanm 86:04dd9b1680ae 521 /** @defgroup FMC_Continous_Clock
bogdanm 86:04dd9b1680ae 522 * @{
bogdanm 86:04dd9b1680ae 523 */
bogdanm 86:04dd9b1680ae 524 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 525 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 526
bogdanm 86:04dd9b1680ae 527 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
bogdanm 86:04dd9b1680ae 528 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
bogdanm 86:04dd9b1680ae 529 /**
bogdanm 86:04dd9b1680ae 530 * @}
bogdanm 86:04dd9b1680ae 531 */
bogdanm 86:04dd9b1680ae 532
bogdanm 86:04dd9b1680ae 533 /** @defgroup FMC_Address_Setup_Time
bogdanm 86:04dd9b1680ae 534 * @{
bogdanm 86:04dd9b1680ae 535 */
bogdanm 86:04dd9b1680ae 536 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
bogdanm 86:04dd9b1680ae 537 /**
bogdanm 86:04dd9b1680ae 538 * @}
bogdanm 86:04dd9b1680ae 539 */
bogdanm 86:04dd9b1680ae 540
bogdanm 86:04dd9b1680ae 541 /** @defgroup FMC_Address_Hold_Time
bogdanm 86:04dd9b1680ae 542 * @{
bogdanm 86:04dd9b1680ae 543 */
bogdanm 86:04dd9b1680ae 544 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
bogdanm 86:04dd9b1680ae 545 /**
bogdanm 86:04dd9b1680ae 546 * @}
bogdanm 86:04dd9b1680ae 547 */
bogdanm 86:04dd9b1680ae 548
bogdanm 86:04dd9b1680ae 549 /** @defgroup FMC_Data_Setup_Time
bogdanm 86:04dd9b1680ae 550 * @{
bogdanm 86:04dd9b1680ae 551 */
bogdanm 86:04dd9b1680ae 552 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
bogdanm 86:04dd9b1680ae 553 /**
bogdanm 86:04dd9b1680ae 554 * @}
bogdanm 86:04dd9b1680ae 555 */
bogdanm 86:04dd9b1680ae 556
bogdanm 86:04dd9b1680ae 557 /** @defgroup FMC_Bus_Turn_around_Duration
bogdanm 86:04dd9b1680ae 558 * @{
bogdanm 86:04dd9b1680ae 559 */
bogdanm 86:04dd9b1680ae 560 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
bogdanm 86:04dd9b1680ae 561 /**
bogdanm 86:04dd9b1680ae 562 * @}
bogdanm 86:04dd9b1680ae 563 */
bogdanm 86:04dd9b1680ae 564
bogdanm 86:04dd9b1680ae 565 /** @defgroup FMC_CLK_Division
bogdanm 86:04dd9b1680ae 566 * @{
bogdanm 86:04dd9b1680ae 567 */
bogdanm 86:04dd9b1680ae 568 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
bogdanm 86:04dd9b1680ae 569 /**
bogdanm 86:04dd9b1680ae 570 * @}
bogdanm 86:04dd9b1680ae 571 */
bogdanm 86:04dd9b1680ae 572
bogdanm 86:04dd9b1680ae 573 /** @defgroup FMC_Data_Latency
bogdanm 86:04dd9b1680ae 574 * @{
bogdanm 86:04dd9b1680ae 575 */
bogdanm 86:04dd9b1680ae 576 #define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
bogdanm 86:04dd9b1680ae 577 /**
bogdanm 86:04dd9b1680ae 578 * @}
bogdanm 86:04dd9b1680ae 579 */
bogdanm 86:04dd9b1680ae 580
bogdanm 86:04dd9b1680ae 581 /** @defgroup FMC_Access_Mode
bogdanm 86:04dd9b1680ae 582 * @{
bogdanm 86:04dd9b1680ae 583 */
bogdanm 86:04dd9b1680ae 584 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 585 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 586 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 587 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm 86:04dd9b1680ae 588
bogdanm 86:04dd9b1680ae 589 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
bogdanm 86:04dd9b1680ae 590 ((MODE) == FMC_ACCESS_MODE_B) || \
bogdanm 86:04dd9b1680ae 591 ((MODE) == FMC_ACCESS_MODE_C) || \
bogdanm 86:04dd9b1680ae 592 ((MODE) == FMC_ACCESS_MODE_D))
bogdanm 86:04dd9b1680ae 593 /**
bogdanm 86:04dd9b1680ae 594 * @}
bogdanm 86:04dd9b1680ae 595 */
bogdanm 86:04dd9b1680ae 596
bogdanm 86:04dd9b1680ae 597 /**
bogdanm 86:04dd9b1680ae 598 * @}
bogdanm 86:04dd9b1680ae 599 */
bogdanm 86:04dd9b1680ae 600
bogdanm 86:04dd9b1680ae 601 /** @defgroup FMC_NAND_Controller
bogdanm 86:04dd9b1680ae 602 * @{
bogdanm 86:04dd9b1680ae 603 */
bogdanm 86:04dd9b1680ae 604
bogdanm 86:04dd9b1680ae 605 /** @defgroup FMC_NAND_Bank
bogdanm 86:04dd9b1680ae 606 * @{
bogdanm 86:04dd9b1680ae 607 */
bogdanm 86:04dd9b1680ae 608 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 609 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 610
bogdanm 86:04dd9b1680ae 611 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
bogdanm 86:04dd9b1680ae 612 ((BANK) == FMC_NAND_BANK3))
bogdanm 86:04dd9b1680ae 613 /**
bogdanm 86:04dd9b1680ae 614 * @}
bogdanm 86:04dd9b1680ae 615 */
bogdanm 86:04dd9b1680ae 616
bogdanm 86:04dd9b1680ae 617 /** @defgroup FMC_Wait_feature
bogdanm 86:04dd9b1680ae 618 * @{
bogdanm 86:04dd9b1680ae 619 */
bogdanm 86:04dd9b1680ae 620 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 621 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 622
bogdanm 86:04dd9b1680ae 623 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
bogdanm 86:04dd9b1680ae 624 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
bogdanm 86:04dd9b1680ae 625 /**
bogdanm 86:04dd9b1680ae 626 * @}
bogdanm 86:04dd9b1680ae 627 */
bogdanm 86:04dd9b1680ae 628
bogdanm 86:04dd9b1680ae 629 /** @defgroup FMC_PCR_Memory_Type
bogdanm 86:04dd9b1680ae 630 * @{
bogdanm 86:04dd9b1680ae 631 */
bogdanm 86:04dd9b1680ae 632 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 633 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 634 /**
bogdanm 86:04dd9b1680ae 635 * @}
bogdanm 86:04dd9b1680ae 636 */
bogdanm 86:04dd9b1680ae 637
bogdanm 86:04dd9b1680ae 638 /** @defgroup FMC_NAND_Data_Width
bogdanm 86:04dd9b1680ae 639 * @{
bogdanm 86:04dd9b1680ae 640 */
bogdanm 86:04dd9b1680ae 641 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 642 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 643
bogdanm 86:04dd9b1680ae 644 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
bogdanm 86:04dd9b1680ae 645 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
bogdanm 86:04dd9b1680ae 646 /**
bogdanm 86:04dd9b1680ae 647 * @}
bogdanm 86:04dd9b1680ae 648 */
bogdanm 86:04dd9b1680ae 649
bogdanm 86:04dd9b1680ae 650 /** @defgroup FMC_ECC
bogdanm 86:04dd9b1680ae 651 * @{
bogdanm 86:04dd9b1680ae 652 */
bogdanm 86:04dd9b1680ae 653 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 654 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 655
bogdanm 86:04dd9b1680ae 656 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
bogdanm 86:04dd9b1680ae 657 ((STATE) == FMC_NAND_ECC_ENABLE))
bogdanm 86:04dd9b1680ae 658 /**
bogdanm 86:04dd9b1680ae 659 * @}
bogdanm 86:04dd9b1680ae 660 */
bogdanm 86:04dd9b1680ae 661
bogdanm 86:04dd9b1680ae 662 /** @defgroup FMC_ECC_Page_Size
bogdanm 86:04dd9b1680ae 663 * @{
bogdanm 86:04dd9b1680ae 664 */
bogdanm 86:04dd9b1680ae 665 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 666 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 667 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 668 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm 86:04dd9b1680ae 669 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 670 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm 86:04dd9b1680ae 671
bogdanm 86:04dd9b1680ae 672 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
bogdanm 86:04dd9b1680ae 673 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
bogdanm 86:04dd9b1680ae 674 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
bogdanm 86:04dd9b1680ae 675 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
bogdanm 86:04dd9b1680ae 676 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
bogdanm 86:04dd9b1680ae 677 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
bogdanm 86:04dd9b1680ae 678 /**
bogdanm 86:04dd9b1680ae 679 * @}
bogdanm 86:04dd9b1680ae 680 */
bogdanm 86:04dd9b1680ae 681
bogdanm 86:04dd9b1680ae 682 /** @defgroup FMC_TCLR_Setup_Time
bogdanm 86:04dd9b1680ae 683 * @{
bogdanm 86:04dd9b1680ae 684 */
bogdanm 86:04dd9b1680ae 685 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
bogdanm 86:04dd9b1680ae 686 /**
bogdanm 86:04dd9b1680ae 687 * @}
bogdanm 86:04dd9b1680ae 688 */
bogdanm 86:04dd9b1680ae 689
bogdanm 86:04dd9b1680ae 690 /** @defgroup FMC_TAR_Setup_Time
bogdanm 86:04dd9b1680ae 691 * @{
bogdanm 86:04dd9b1680ae 692 */
bogdanm 86:04dd9b1680ae 693 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
bogdanm 86:04dd9b1680ae 694 /**
bogdanm 86:04dd9b1680ae 695 * @}
bogdanm 86:04dd9b1680ae 696 */
bogdanm 86:04dd9b1680ae 697
bogdanm 86:04dd9b1680ae 698 /** @defgroup FMC_Setup_Time
bogdanm 86:04dd9b1680ae 699 * @{
bogdanm 86:04dd9b1680ae 700 */
bogdanm 86:04dd9b1680ae 701 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
bogdanm 86:04dd9b1680ae 702 /**
bogdanm 86:04dd9b1680ae 703 * @}
bogdanm 86:04dd9b1680ae 704 */
bogdanm 86:04dd9b1680ae 705
bogdanm 86:04dd9b1680ae 706 /** @defgroup FMC_Wait_Setup_Time
bogdanm 86:04dd9b1680ae 707 * @{
bogdanm 86:04dd9b1680ae 708 */
bogdanm 86:04dd9b1680ae 709 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
bogdanm 86:04dd9b1680ae 710 /**
bogdanm 86:04dd9b1680ae 711 * @}
bogdanm 86:04dd9b1680ae 712 */
bogdanm 86:04dd9b1680ae 713
bogdanm 86:04dd9b1680ae 714 /** @defgroup FMC_Hold_Setup_Time
bogdanm 86:04dd9b1680ae 715 * @{
bogdanm 86:04dd9b1680ae 716 */
bogdanm 86:04dd9b1680ae 717 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
bogdanm 86:04dd9b1680ae 718 /**
bogdanm 86:04dd9b1680ae 719 * @}
bogdanm 86:04dd9b1680ae 720 */
bogdanm 86:04dd9b1680ae 721
bogdanm 86:04dd9b1680ae 722 /** @defgroup FMC_HiZ_Setup_Time
bogdanm 86:04dd9b1680ae 723 * @{
bogdanm 86:04dd9b1680ae 724 */
bogdanm 86:04dd9b1680ae 725 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
bogdanm 86:04dd9b1680ae 726 /**
bogdanm 86:04dd9b1680ae 727 * @}
bogdanm 86:04dd9b1680ae 728 */
bogdanm 86:04dd9b1680ae 729
bogdanm 86:04dd9b1680ae 730 /**
bogdanm 86:04dd9b1680ae 731 * @}
bogdanm 86:04dd9b1680ae 732 */
bogdanm 86:04dd9b1680ae 733
bogdanm 86:04dd9b1680ae 734 /** @defgroup FMC_SDRAM_Controller
bogdanm 86:04dd9b1680ae 735 * @{
bogdanm 86:04dd9b1680ae 736 */
bogdanm 86:04dd9b1680ae 737
bogdanm 86:04dd9b1680ae 738 /** @defgroup FMC_SDRAM_Bank
bogdanm 86:04dd9b1680ae 739 * @{
bogdanm 86:04dd9b1680ae 740 */
bogdanm 86:04dd9b1680ae 741 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 742 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 743
bogdanm 86:04dd9b1680ae 744 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
bogdanm 86:04dd9b1680ae 745 ((BANK) == FMC_SDRAM_BANK2))
bogdanm 86:04dd9b1680ae 746 /**
bogdanm 86:04dd9b1680ae 747 * @}
bogdanm 86:04dd9b1680ae 748 */
bogdanm 86:04dd9b1680ae 749
bogdanm 86:04dd9b1680ae 750 /** @defgroup FMC_SDRAM_Column_Bits_number
bogdanm 86:04dd9b1680ae 751 * @{
bogdanm 86:04dd9b1680ae 752 */
bogdanm 86:04dd9b1680ae 753 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 754 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 755 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 756 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
bogdanm 86:04dd9b1680ae 757
bogdanm 86:04dd9b1680ae 758 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
bogdanm 86:04dd9b1680ae 759 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
bogdanm 86:04dd9b1680ae 760 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
bogdanm 86:04dd9b1680ae 761 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
bogdanm 86:04dd9b1680ae 762 /**
bogdanm 86:04dd9b1680ae 763 * @}
bogdanm 86:04dd9b1680ae 764 */
bogdanm 86:04dd9b1680ae 765
bogdanm 86:04dd9b1680ae 766 /** @defgroup FMC_SDRAM_Row_Bits_number
bogdanm 86:04dd9b1680ae 767 * @{
bogdanm 86:04dd9b1680ae 768 */
bogdanm 86:04dd9b1680ae 769 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 770 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 771 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 772
bogdanm 86:04dd9b1680ae 773 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
bogdanm 86:04dd9b1680ae 774 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
bogdanm 86:04dd9b1680ae 775 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
bogdanm 86:04dd9b1680ae 776 /**
bogdanm 86:04dd9b1680ae 777 * @}
bogdanm 86:04dd9b1680ae 778 */
bogdanm 86:04dd9b1680ae 779
bogdanm 86:04dd9b1680ae 780 /** @defgroup FMC_SDRAM_Memory_Bus_Width
bogdanm 86:04dd9b1680ae 781 * @{
bogdanm 86:04dd9b1680ae 782 */
bogdanm 86:04dd9b1680ae 783 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 784 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 785 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 786
bogdanm 86:04dd9b1680ae 787 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
bogdanm 86:04dd9b1680ae 788 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
bogdanm 86:04dd9b1680ae 789 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
bogdanm 86:04dd9b1680ae 790 /**
bogdanm 86:04dd9b1680ae 791 * @}
bogdanm 86:04dd9b1680ae 792 */
bogdanm 86:04dd9b1680ae 793
bogdanm 86:04dd9b1680ae 794 /** @defgroup FMC_SDRAM_Internal_Banks_Number
bogdanm 86:04dd9b1680ae 795 * @{
bogdanm 86:04dd9b1680ae 796 */
bogdanm 86:04dd9b1680ae 797 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 798 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 799
bogdanm 86:04dd9b1680ae 800 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
bogdanm 86:04dd9b1680ae 801 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
bogdanm 86:04dd9b1680ae 802 /**
bogdanm 86:04dd9b1680ae 803 * @}
bogdanm 86:04dd9b1680ae 804 */
bogdanm 86:04dd9b1680ae 805
bogdanm 86:04dd9b1680ae 806 /** @defgroup FMC_SDRAM_CAS_Latency
bogdanm 86:04dd9b1680ae 807 * @{
bogdanm 86:04dd9b1680ae 808 */
bogdanm 86:04dd9b1680ae 809 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 810 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 811 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
bogdanm 86:04dd9b1680ae 812
bogdanm 86:04dd9b1680ae 813 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
bogdanm 86:04dd9b1680ae 814 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
bogdanm 86:04dd9b1680ae 815 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
bogdanm 86:04dd9b1680ae 816 /**
bogdanm 86:04dd9b1680ae 817 * @}
bogdanm 86:04dd9b1680ae 818 */
bogdanm 86:04dd9b1680ae 819
bogdanm 86:04dd9b1680ae 820 /** @defgroup FMC_SDRAM_Write_Protection
bogdanm 86:04dd9b1680ae 821 * @{
bogdanm 86:04dd9b1680ae 822 */
bogdanm 86:04dd9b1680ae 823 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 824 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 825
bogdanm 86:04dd9b1680ae 826 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
bogdanm 86:04dd9b1680ae 827 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
bogdanm 86:04dd9b1680ae 828 /**
bogdanm 86:04dd9b1680ae 829 * @}
bogdanm 86:04dd9b1680ae 830 */
bogdanm 86:04dd9b1680ae 831
bogdanm 86:04dd9b1680ae 832 /** @defgroup FMC_SDRAM_Clock_Period
bogdanm 86:04dd9b1680ae 833 * @{
bogdanm 86:04dd9b1680ae 834 */
bogdanm 86:04dd9b1680ae 835 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 836 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 837 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
bogdanm 86:04dd9b1680ae 838
bogdanm 86:04dd9b1680ae 839 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
bogdanm 86:04dd9b1680ae 840 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
bogdanm 86:04dd9b1680ae 841 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
bogdanm 86:04dd9b1680ae 842 /**
bogdanm 86:04dd9b1680ae 843 * @}
bogdanm 86:04dd9b1680ae 844 */
bogdanm 86:04dd9b1680ae 845
bogdanm 86:04dd9b1680ae 846 /** @defgroup FMC_SDRAM_Read_Burst
bogdanm 86:04dd9b1680ae 847 * @{
bogdanm 86:04dd9b1680ae 848 */
bogdanm 86:04dd9b1680ae 849 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 850 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 851
bogdanm 86:04dd9b1680ae 852 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
bogdanm 86:04dd9b1680ae 853 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
bogdanm 86:04dd9b1680ae 854 /**
bogdanm 86:04dd9b1680ae 855 * @}
bogdanm 86:04dd9b1680ae 856 */
bogdanm 86:04dd9b1680ae 857
bogdanm 86:04dd9b1680ae 858 /** @defgroup FMC_SDRAM_Read_Pipe_Delay
bogdanm 86:04dd9b1680ae 859 * @{
bogdanm 86:04dd9b1680ae 860 */
bogdanm 86:04dd9b1680ae 861 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 862 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 863 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 864
bogdanm 86:04dd9b1680ae 865 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
bogdanm 86:04dd9b1680ae 866 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
bogdanm 86:04dd9b1680ae 867 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
bogdanm 86:04dd9b1680ae 868 /**
bogdanm 86:04dd9b1680ae 869 * @}
bogdanm 86:04dd9b1680ae 870 */
bogdanm 86:04dd9b1680ae 871
bogdanm 86:04dd9b1680ae 872 /** @defgroup FMC_SDRAM_LoadToActive_Delay
bogdanm 86:04dd9b1680ae 873 * @{
bogdanm 86:04dd9b1680ae 874 */
bogdanm 86:04dd9b1680ae 875 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm 86:04dd9b1680ae 876 /**
bogdanm 86:04dd9b1680ae 877 * @}
bogdanm 86:04dd9b1680ae 878 */
bogdanm 86:04dd9b1680ae 879
bogdanm 86:04dd9b1680ae 880 /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
bogdanm 86:04dd9b1680ae 881 * @{
bogdanm 86:04dd9b1680ae 882 */
bogdanm 86:04dd9b1680ae 883 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm 86:04dd9b1680ae 884 /**
bogdanm 86:04dd9b1680ae 885 * @}
bogdanm 86:04dd9b1680ae 886 */
bogdanm 86:04dd9b1680ae 887
bogdanm 86:04dd9b1680ae 888 /** @defgroup FMC_SDRAM_SelfRefresh_Time
bogdanm 86:04dd9b1680ae 889 * @{
bogdanm 86:04dd9b1680ae 890 */
bogdanm 86:04dd9b1680ae 891 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
bogdanm 86:04dd9b1680ae 892 /**
bogdanm 86:04dd9b1680ae 893 * @}
bogdanm 86:04dd9b1680ae 894 */
bogdanm 86:04dd9b1680ae 895
bogdanm 86:04dd9b1680ae 896 /** @defgroup FMC_SDRAM_RowCycle_Delay
bogdanm 86:04dd9b1680ae 897 * @{
bogdanm 86:04dd9b1680ae 898 */
bogdanm 86:04dd9b1680ae 899 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm 86:04dd9b1680ae 900 /**
bogdanm 86:04dd9b1680ae 901 * @}
bogdanm 86:04dd9b1680ae 902 */
bogdanm 86:04dd9b1680ae 903
bogdanm 86:04dd9b1680ae 904 /** @defgroup FMC_SDRAM_Write_Recovery_Time
bogdanm 86:04dd9b1680ae 905 * @{
bogdanm 86:04dd9b1680ae 906 */
bogdanm 86:04dd9b1680ae 907 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
bogdanm 86:04dd9b1680ae 908 /**
bogdanm 86:04dd9b1680ae 909 * @}
bogdanm 86:04dd9b1680ae 910 */
bogdanm 86:04dd9b1680ae 911
bogdanm 86:04dd9b1680ae 912 /** @defgroup FMC_SDRAM_RP_Delay
bogdanm 86:04dd9b1680ae 913 * @{
bogdanm 86:04dd9b1680ae 914 */
bogdanm 86:04dd9b1680ae 915 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm 86:04dd9b1680ae 916 /**
bogdanm 86:04dd9b1680ae 917 * @}
bogdanm 86:04dd9b1680ae 918 */
bogdanm 86:04dd9b1680ae 919
bogdanm 86:04dd9b1680ae 920 /** @defgroup FMC_SDRAM_RCD_Delay
bogdanm 86:04dd9b1680ae 921 * @{
bogdanm 86:04dd9b1680ae 922 */
bogdanm 86:04dd9b1680ae 923 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm 86:04dd9b1680ae 924
bogdanm 86:04dd9b1680ae 925 /**
bogdanm 86:04dd9b1680ae 926 * @}
bogdanm 86:04dd9b1680ae 927 */
bogdanm 86:04dd9b1680ae 928
bogdanm 86:04dd9b1680ae 929 /** @defgroup FMC_SDRAM_Command_Mode
bogdanm 86:04dd9b1680ae 930 * @{
bogdanm 86:04dd9b1680ae 931 */
bogdanm 86:04dd9b1680ae 932 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 933 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 934 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 935 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
bogdanm 86:04dd9b1680ae 936 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 937 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
bogdanm 86:04dd9b1680ae 938 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
bogdanm 86:04dd9b1680ae 939
bogdanm 86:04dd9b1680ae 940 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
bogdanm 86:04dd9b1680ae 941 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
bogdanm 86:04dd9b1680ae 942 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
bogdanm 86:04dd9b1680ae 943 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
bogdanm 86:04dd9b1680ae 944 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
bogdanm 86:04dd9b1680ae 945 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
bogdanm 86:04dd9b1680ae 946 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
bogdanm 86:04dd9b1680ae 947 /**
bogdanm 86:04dd9b1680ae 948 * @}
bogdanm 86:04dd9b1680ae 949 */
bogdanm 86:04dd9b1680ae 950
bogdanm 86:04dd9b1680ae 951 /** @defgroup FMC_SDRAM_Command_Target
bogdanm 86:04dd9b1680ae 952 * @{
bogdanm 86:04dd9b1680ae 953 */
bogdanm 86:04dd9b1680ae 954 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
bogdanm 86:04dd9b1680ae 955 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
bogdanm 86:04dd9b1680ae 956 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
bogdanm 86:04dd9b1680ae 957
bogdanm 86:04dd9b1680ae 958 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
bogdanm 86:04dd9b1680ae 959 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
bogdanm 86:04dd9b1680ae 960 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
bogdanm 86:04dd9b1680ae 961 /**
bogdanm 86:04dd9b1680ae 962 * @}
bogdanm 86:04dd9b1680ae 963 */
bogdanm 86:04dd9b1680ae 964
bogdanm 86:04dd9b1680ae 965 /** @defgroup FMC_SDRAM_AutoRefresh_Number
bogdanm 86:04dd9b1680ae 966 * @{
bogdanm 86:04dd9b1680ae 967 */
bogdanm 86:04dd9b1680ae 968 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
bogdanm 86:04dd9b1680ae 969 /**
bogdanm 86:04dd9b1680ae 970 * @}
bogdanm 86:04dd9b1680ae 971 */
bogdanm 86:04dd9b1680ae 972
bogdanm 86:04dd9b1680ae 973 /** @defgroup FMC_SDRAM_ModeRegister_Definition
bogdanm 86:04dd9b1680ae 974 * @{
bogdanm 86:04dd9b1680ae 975 */
bogdanm 86:04dd9b1680ae 976 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
bogdanm 86:04dd9b1680ae 977 /**
bogdanm 86:04dd9b1680ae 978 * @}
bogdanm 86:04dd9b1680ae 979 */
bogdanm 86:04dd9b1680ae 980
bogdanm 86:04dd9b1680ae 981 /** @defgroup FMC_SDRAM_Refresh_rate
bogdanm 86:04dd9b1680ae 982 * @{
bogdanm 86:04dd9b1680ae 983 */
bogdanm 86:04dd9b1680ae 984 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
bogdanm 86:04dd9b1680ae 985 /**
bogdanm 86:04dd9b1680ae 986 * @}
bogdanm 86:04dd9b1680ae 987 */
bogdanm 86:04dd9b1680ae 988
bogdanm 86:04dd9b1680ae 989 /** @defgroup FMC_SDRAM_Mode_Status
bogdanm 86:04dd9b1680ae 990 * @{
bogdanm 86:04dd9b1680ae 991 */
bogdanm 86:04dd9b1680ae 992 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 993 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
bogdanm 86:04dd9b1680ae 994 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
bogdanm 86:04dd9b1680ae 995 /**
bogdanm 86:04dd9b1680ae 996 * @}
bogdanm 86:04dd9b1680ae 997 */
bogdanm 86:04dd9b1680ae 998
bogdanm 86:04dd9b1680ae 999 /** @defgroup FMC_NORSRAM_Device_Instance
bogdanm 86:04dd9b1680ae 1000 * @{
bogdanm 86:04dd9b1680ae 1001 */
bogdanm 86:04dd9b1680ae 1002 #define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
bogdanm 86:04dd9b1680ae 1003 /**
bogdanm 86:04dd9b1680ae 1004 * @}
bogdanm 86:04dd9b1680ae 1005 */
bogdanm 86:04dd9b1680ae 1006
bogdanm 86:04dd9b1680ae 1007 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
bogdanm 86:04dd9b1680ae 1008 * @{
bogdanm 86:04dd9b1680ae 1009 */
bogdanm 86:04dd9b1680ae 1010 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
bogdanm 86:04dd9b1680ae 1011 /**
bogdanm 86:04dd9b1680ae 1012 * @}
bogdanm 86:04dd9b1680ae 1013 */
bogdanm 86:04dd9b1680ae 1014
bogdanm 86:04dd9b1680ae 1015 /** @defgroup FMC_NAND_Device_Instance
bogdanm 86:04dd9b1680ae 1016 * @{
bogdanm 86:04dd9b1680ae 1017 */
bogdanm 86:04dd9b1680ae 1018 #define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
bogdanm 86:04dd9b1680ae 1019 /**
bogdanm 86:04dd9b1680ae 1020 * @}
bogdanm 86:04dd9b1680ae 1021 */
bogdanm 86:04dd9b1680ae 1022
bogdanm 86:04dd9b1680ae 1023 /** @defgroup FMC_PCCARD_Device_Instance
bogdanm 86:04dd9b1680ae 1024 * @{
bogdanm 86:04dd9b1680ae 1025 */
bogdanm 86:04dd9b1680ae 1026 #define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
bogdanm 86:04dd9b1680ae 1027 /**
bogdanm 86:04dd9b1680ae 1028 * @}
bogdanm 86:04dd9b1680ae 1029 */
bogdanm 86:04dd9b1680ae 1030
bogdanm 86:04dd9b1680ae 1031 /** @defgroup FMC_SDRAM_Device_Instance
bogdanm 86:04dd9b1680ae 1032 * @{
bogdanm 86:04dd9b1680ae 1033 */
bogdanm 86:04dd9b1680ae 1034 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
bogdanm 86:04dd9b1680ae 1035 /**
bogdanm 86:04dd9b1680ae 1036 * @}
bogdanm 86:04dd9b1680ae 1037 */
bogdanm 86:04dd9b1680ae 1038
bogdanm 86:04dd9b1680ae 1039 /**
bogdanm 86:04dd9b1680ae 1040 * @}
bogdanm 86:04dd9b1680ae 1041 */
bogdanm 86:04dd9b1680ae 1042
bogdanm 86:04dd9b1680ae 1043 /** @defgroup FMC_Interrupt_definition
bogdanm 86:04dd9b1680ae 1044 * @brief FMC Interrupt definition
bogdanm 86:04dd9b1680ae 1045 * @{
bogdanm 86:04dd9b1680ae 1046 */
bogdanm 86:04dd9b1680ae 1047 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1048 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1049 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1050 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1051
bogdanm 86:04dd9b1680ae 1052 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
bogdanm 86:04dd9b1680ae 1053
bogdanm 86:04dd9b1680ae 1054 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
bogdanm 86:04dd9b1680ae 1055 ((IT) == FMC_IT_LEVEL) || \
bogdanm 86:04dd9b1680ae 1056 ((IT) == FMC_IT_FALLING_EDGE) || \
bogdanm 86:04dd9b1680ae 1057 ((IT) == FMC_IT_REFRESH_ERROR))
bogdanm 86:04dd9b1680ae 1058 /**
bogdanm 86:04dd9b1680ae 1059 * @}
bogdanm 86:04dd9b1680ae 1060 */
bogdanm 86:04dd9b1680ae 1061
bogdanm 86:04dd9b1680ae 1062 /** @defgroup FMC_Flag_definition
bogdanm 86:04dd9b1680ae 1063 * @brief FMC Flag definition
bogdanm 86:04dd9b1680ae 1064 * @{
bogdanm 86:04dd9b1680ae 1065 */
bogdanm 86:04dd9b1680ae 1066 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1067 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1068 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1069 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1070 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
bogdanm 86:04dd9b1680ae 1071 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
bogdanm 86:04dd9b1680ae 1072 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
bogdanm 86:04dd9b1680ae 1073
bogdanm 86:04dd9b1680ae 1074 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
bogdanm 86:04dd9b1680ae 1075 ((FLAG) == FMC_FLAG_LEVEL) || \
bogdanm 86:04dd9b1680ae 1076 ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
bogdanm 86:04dd9b1680ae 1077 ((FLAG) == FMC_FLAG_FEMPT) || \
bogdanm 86:04dd9b1680ae 1078 ((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) || \
bogdanm 86:04dd9b1680ae 1079 ((FLAG) == FMC_SDRAM_FLAG_BUSY))
bogdanm 86:04dd9b1680ae 1080
bogdanm 86:04dd9b1680ae 1081 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
bogdanm 86:04dd9b1680ae 1082 /**
bogdanm 86:04dd9b1680ae 1083 * @}
bogdanm 86:04dd9b1680ae 1084 */
bogdanm 86:04dd9b1680ae 1085
bogdanm 86:04dd9b1680ae 1086 /* Exported macro ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 1087
bogdanm 86:04dd9b1680ae 1088 /** @defgroup FMC_NOR_Macros
bogdanm 86:04dd9b1680ae 1089 * @brief macros to handle NOR device enable/disable and read/write operations
bogdanm 86:04dd9b1680ae 1090 * @{
bogdanm 86:04dd9b1680ae 1091 */
bogdanm 86:04dd9b1680ae 1092
bogdanm 86:04dd9b1680ae 1093 /**
bogdanm 86:04dd9b1680ae 1094 * @brief Enable the NORSRAM device access.
bogdanm 86:04dd9b1680ae 1095 * @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm 86:04dd9b1680ae 1096 * @param __BANK__: FMC_NORSRAM Bank
bogdanm 86:04dd9b1680ae 1097 * @retval None
bogdanm 86:04dd9b1680ae 1098 */
bogdanm 86:04dd9b1680ae 1099 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
bogdanm 86:04dd9b1680ae 1100
bogdanm 86:04dd9b1680ae 1101 /**
bogdanm 86:04dd9b1680ae 1102 * @brief Disable the NORSRAM device access.
bogdanm 86:04dd9b1680ae 1103 * @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm 86:04dd9b1680ae 1104 * @param __BANK__: FMC_NORSRAM Bank
bogdanm 86:04dd9b1680ae 1105 * @retval None
bogdanm 86:04dd9b1680ae 1106 */
bogdanm 86:04dd9b1680ae 1107 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
bogdanm 86:04dd9b1680ae 1108
bogdanm 86:04dd9b1680ae 1109 /**
bogdanm 86:04dd9b1680ae 1110 * @}
bogdanm 86:04dd9b1680ae 1111 */
bogdanm 86:04dd9b1680ae 1112
bogdanm 86:04dd9b1680ae 1113 /** @defgroup FMC_NAND_Macros
bogdanm 86:04dd9b1680ae 1114 * @brief macros to handle NAND device enable/disable
bogdanm 86:04dd9b1680ae 1115 * @{
bogdanm 86:04dd9b1680ae 1116 */
bogdanm 86:04dd9b1680ae 1117
bogdanm 86:04dd9b1680ae 1118 /**
bogdanm 86:04dd9b1680ae 1119 * @brief Enable the NAND device access.
bogdanm 86:04dd9b1680ae 1120 * @param __INSTANCE__: FMC_NAND Instance
bogdanm 86:04dd9b1680ae 1121 * @param __BANK__: FMC_NAND Bank
bogdanm 86:04dd9b1680ae 1122 * @retval None
bogdanm 86:04dd9b1680ae 1123 */
bogdanm 86:04dd9b1680ae 1124 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
bogdanm 86:04dd9b1680ae 1125 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
bogdanm 86:04dd9b1680ae 1126
bogdanm 86:04dd9b1680ae 1127 /**
bogdanm 86:04dd9b1680ae 1128 * @brief Disable the NAND device access.
bogdanm 86:04dd9b1680ae 1129 * @param __INSTANCE__: FMC_NAND Instance
bogdanm 86:04dd9b1680ae 1130 * @param __BANK__: FMC_NAND Bank
bogdanm 86:04dd9b1680ae 1131 * @retval None
bogdanm 86:04dd9b1680ae 1132 */
bogdanm 86:04dd9b1680ae 1133 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
bogdanm 86:04dd9b1680ae 1134 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
bogdanm 86:04dd9b1680ae 1135 /**
bogdanm 86:04dd9b1680ae 1136 * @}
bogdanm 86:04dd9b1680ae 1137 */
bogdanm 86:04dd9b1680ae 1138
bogdanm 86:04dd9b1680ae 1139 /** @defgroup FMC_PCCARD_Macros
bogdanm 86:04dd9b1680ae 1140 * @brief macros to handle SRAM read/write operations
bogdanm 86:04dd9b1680ae 1141 * @{
bogdanm 86:04dd9b1680ae 1142 */
bogdanm 86:04dd9b1680ae 1143
bogdanm 86:04dd9b1680ae 1144 /**
bogdanm 86:04dd9b1680ae 1145 * @brief Enable the PCCARD device access.
bogdanm 86:04dd9b1680ae 1146 * @param __INSTANCE__: FMC_PCCARD Instance
bogdanm 86:04dd9b1680ae 1147 * @retval None
bogdanm 86:04dd9b1680ae 1148 */
bogdanm 86:04dd9b1680ae 1149 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
bogdanm 86:04dd9b1680ae 1150
bogdanm 86:04dd9b1680ae 1151 /**
bogdanm 86:04dd9b1680ae 1152 * @brief Disable the PCCARD device access.
bogdanm 86:04dd9b1680ae 1153 * @param __INSTANCE__: FMC_PCCARD Instance
bogdanm 86:04dd9b1680ae 1154 * @retval None
bogdanm 86:04dd9b1680ae 1155 */
bogdanm 86:04dd9b1680ae 1156 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
bogdanm 86:04dd9b1680ae 1157 /**
bogdanm 86:04dd9b1680ae 1158 * @}
bogdanm 86:04dd9b1680ae 1159 */
bogdanm 86:04dd9b1680ae 1160
bogdanm 86:04dd9b1680ae 1161 /** @defgroup FMC_Interrupt
bogdanm 86:04dd9b1680ae 1162 * @brief macros to handle FMC interrupts
bogdanm 86:04dd9b1680ae 1163 * @{
bogdanm 86:04dd9b1680ae 1164 */
bogdanm 86:04dd9b1680ae 1165
bogdanm 86:04dd9b1680ae 1166 /**
bogdanm 86:04dd9b1680ae 1167 * @brief Enable the NAND device interrupt.
bogdanm 86:04dd9b1680ae 1168 * @param __INSTANCE__: FMC_NAND instance
bogdanm 86:04dd9b1680ae 1169 * @param __BANK__: FMC_NAND Bank
bogdanm 86:04dd9b1680ae 1170 * @param __INTERRUPT__: FMC_NAND interrupt
bogdanm 86:04dd9b1680ae 1171 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1172 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 86:04dd9b1680ae 1173 * @arg FMC_IT_LEVEL: Interrupt level.
bogdanm 86:04dd9b1680ae 1174 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 86:04dd9b1680ae 1175 * @retval None
bogdanm 86:04dd9b1680ae 1176 */
bogdanm 86:04dd9b1680ae 1177 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
bogdanm 86:04dd9b1680ae 1178 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
bogdanm 86:04dd9b1680ae 1179
bogdanm 86:04dd9b1680ae 1180 /**
bogdanm 86:04dd9b1680ae 1181 * @brief Disable the NAND device interrupt.
bogdanm 86:04dd9b1680ae 1182 * @param __INSTANCE__: FMC_NAND handle
bogdanm 86:04dd9b1680ae 1183 * @param __BANK__: FMC_NAND Bank
bogdanm 86:04dd9b1680ae 1184 * @param __INTERRUPT__: FMC_NAND interrupt
bogdanm 86:04dd9b1680ae 1185 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1186 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 86:04dd9b1680ae 1187 * @arg FMC_IT_LEVEL: Interrupt level.
bogdanm 86:04dd9b1680ae 1188 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 86:04dd9b1680ae 1189 * @retval None
bogdanm 86:04dd9b1680ae 1190 */
bogdanm 86:04dd9b1680ae 1191 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
bogdanm 86:04dd9b1680ae 1192 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
bogdanm 86:04dd9b1680ae 1193
bogdanm 86:04dd9b1680ae 1194 /**
bogdanm 86:04dd9b1680ae 1195 * @brief Get flag status of the NAND device.
bogdanm 86:04dd9b1680ae 1196 * @param __INSTANCE__: FMC_NAND handle
bogdanm 86:04dd9b1680ae 1197 * @param __BANK__: FMC_NAND Bank
bogdanm 86:04dd9b1680ae 1198 * @param __FLAG__: FMC_NAND flag
bogdanm 86:04dd9b1680ae 1199 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1200 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 86:04dd9b1680ae 1201 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 86:04dd9b1680ae 1202 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 86:04dd9b1680ae 1203 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 86:04dd9b1680ae 1204 * @retval The state of FLAG (SET or RESET).
bogdanm 86:04dd9b1680ae 1205 */
bogdanm 86:04dd9b1680ae 1206 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
bogdanm 86:04dd9b1680ae 1207 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
bogdanm 86:04dd9b1680ae 1208 /**
bogdanm 86:04dd9b1680ae 1209 * @brief Clear flag status of the NAND device.
bogdanm 86:04dd9b1680ae 1210 * @param __INSTANCE__: FMC_NAND handle
bogdanm 86:04dd9b1680ae 1211 * @param __BANK__: FMC_NAND Bank
bogdanm 86:04dd9b1680ae 1212 * @param __FLAG__: FMC_NAND flag
bogdanm 86:04dd9b1680ae 1213 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1214 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 86:04dd9b1680ae 1215 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 86:04dd9b1680ae 1216 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 86:04dd9b1680ae 1217 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 86:04dd9b1680ae 1218 * @retval None
bogdanm 86:04dd9b1680ae 1219 */
bogdanm 86:04dd9b1680ae 1220 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
bogdanm 86:04dd9b1680ae 1221 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
bogdanm 86:04dd9b1680ae 1222 /**
bogdanm 86:04dd9b1680ae 1223 * @brief Enable the PCCARD device interrupt.
bogdanm 86:04dd9b1680ae 1224 * @param __INSTANCE__: FMC_PCCARD instance
bogdanm 86:04dd9b1680ae 1225 * @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm 86:04dd9b1680ae 1226 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1227 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 86:04dd9b1680ae 1228 * @arg FMC_IT_LEVEL: Interrupt level.
bogdanm 86:04dd9b1680ae 1229 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 86:04dd9b1680ae 1230 * @retval None
bogdanm 86:04dd9b1680ae 1231 */
bogdanm 86:04dd9b1680ae 1232 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1233
bogdanm 86:04dd9b1680ae 1234 /**
bogdanm 86:04dd9b1680ae 1235 * @brief Disable the PCCARD device interrupt.
bogdanm 86:04dd9b1680ae 1236 * @param __INSTANCE__: FMC_PCCARD instance
bogdanm 86:04dd9b1680ae 1237 * @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm 86:04dd9b1680ae 1238 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1239 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 86:04dd9b1680ae 1240 * @arg FMC_IT_LEVEL: Interrupt level.
bogdanm 86:04dd9b1680ae 1241 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 86:04dd9b1680ae 1242 * @retval None
bogdanm 86:04dd9b1680ae 1243 */
bogdanm 86:04dd9b1680ae 1244 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1245
bogdanm 86:04dd9b1680ae 1246 /**
bogdanm 86:04dd9b1680ae 1247 * @brief Get flag status of the PCCARD device.
bogdanm 86:04dd9b1680ae 1248 * @param __INSTANCE__: FMC_PCCARD instance
bogdanm 86:04dd9b1680ae 1249 * @param __FLAG__: FMC_PCCARD flag
bogdanm 86:04dd9b1680ae 1250 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1251 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 86:04dd9b1680ae 1252 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 86:04dd9b1680ae 1253 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 86:04dd9b1680ae 1254 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 86:04dd9b1680ae 1255 * @retval The state of FLAG (SET or RESET).
bogdanm 86:04dd9b1680ae 1256 */
bogdanm 86:04dd9b1680ae 1257 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm 86:04dd9b1680ae 1258
bogdanm 86:04dd9b1680ae 1259 /**
bogdanm 86:04dd9b1680ae 1260 * @brief Clear flag status of the PCCARD device.
bogdanm 86:04dd9b1680ae 1261 * @param __INSTANCE__: FMC_PCCARD instance
bogdanm 86:04dd9b1680ae 1262 * @param __FLAG__: FMC_PCCARD flag
bogdanm 86:04dd9b1680ae 1263 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1264 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 86:04dd9b1680ae 1265 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 86:04dd9b1680ae 1266 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 86:04dd9b1680ae 1267 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 86:04dd9b1680ae 1268 * @retval None
bogdanm 86:04dd9b1680ae 1269 */
bogdanm 86:04dd9b1680ae 1270 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
bogdanm 86:04dd9b1680ae 1271
bogdanm 86:04dd9b1680ae 1272 /**
bogdanm 86:04dd9b1680ae 1273 * @brief Enable the SDRAM device interrupt.
bogdanm 86:04dd9b1680ae 1274 * @param __INSTANCE__: FMC_SDRAM instance
bogdanm 86:04dd9b1680ae 1275 * @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm 86:04dd9b1680ae 1276 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1277 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm 86:04dd9b1680ae 1278 * @retval None
bogdanm 86:04dd9b1680ae 1279 */
bogdanm 86:04dd9b1680ae 1280 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1281
bogdanm 86:04dd9b1680ae 1282 /**
bogdanm 86:04dd9b1680ae 1283 * @brief Disable the SDRAM device interrupt.
bogdanm 86:04dd9b1680ae 1284 * @param __INSTANCE__: FMC_SDRAM instance
bogdanm 86:04dd9b1680ae 1285 * @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm 86:04dd9b1680ae 1286 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1287 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm 86:04dd9b1680ae 1288 * @retval None
bogdanm 86:04dd9b1680ae 1289 */
bogdanm 86:04dd9b1680ae 1290 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1291
bogdanm 86:04dd9b1680ae 1292 /**
bogdanm 86:04dd9b1680ae 1293 * @brief Get flag status of the SDRAM device.
bogdanm 86:04dd9b1680ae 1294 * @param __INSTANCE__: FMC_SDRAM instance
bogdanm 86:04dd9b1680ae 1295 * @param __FLAG__: FMC_SDRAM flag
bogdanm 86:04dd9b1680ae 1296 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1297 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
bogdanm 86:04dd9b1680ae 1298 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
bogdanm 86:04dd9b1680ae 1299 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
bogdanm 86:04dd9b1680ae 1300 * @retval The state of FLAG (SET or RESET).
bogdanm 86:04dd9b1680ae 1301 */
bogdanm 86:04dd9b1680ae 1302 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
bogdanm 86:04dd9b1680ae 1303
bogdanm 86:04dd9b1680ae 1304 /**
bogdanm 86:04dd9b1680ae 1305 * @brief Clear flag status of the SDRAM device.
bogdanm 86:04dd9b1680ae 1306 * @param __INSTANCE__: FMC_SDRAM instance
bogdanm 86:04dd9b1680ae 1307 * @param __FLAG__: FMC_SDRAM flag
bogdanm 86:04dd9b1680ae 1308 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1309 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
bogdanm 86:04dd9b1680ae 1310 * @retval None
bogdanm 86:04dd9b1680ae 1311 */
bogdanm 86:04dd9b1680ae 1312 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
bogdanm 86:04dd9b1680ae 1313 /**
bogdanm 86:04dd9b1680ae 1314 * @}
bogdanm 86:04dd9b1680ae 1315 */
bogdanm 86:04dd9b1680ae 1316
bogdanm 86:04dd9b1680ae 1317 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 1318
bogdanm 86:04dd9b1680ae 1319 /* FMC_NORSRAM Controller functions *******************************************/
bogdanm 86:04dd9b1680ae 1320 /* Initialization/de-initialization functions */
bogdanm 86:04dd9b1680ae 1321 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
bogdanm 86:04dd9b1680ae 1322 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1323 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm 86:04dd9b1680ae 1324 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1325
bogdanm 86:04dd9b1680ae 1326 /* FMC_NORSRAM Control functions */
bogdanm 86:04dd9b1680ae 1327 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1328 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1329
bogdanm 86:04dd9b1680ae 1330 /* FMC_NAND Controller functions **********************************************/
bogdanm 86:04dd9b1680ae 1331 /* Initialization/de-initialization functions */
bogdanm 86:04dd9b1680ae 1332 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
bogdanm 86:04dd9b1680ae 1333 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1334 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1335 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1336
bogdanm 86:04dd9b1680ae 1337 /* FMC_NAND Control functions */
bogdanm 86:04dd9b1680ae 1338 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1339 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1340 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm 86:04dd9b1680ae 1341
bogdanm 86:04dd9b1680ae 1342 /* FMC_PCCARD Controller functions ********************************************/
bogdanm 86:04dd9b1680ae 1343 /* Initialization/de-initialization functions */
bogdanm 86:04dd9b1680ae 1344 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
bogdanm 86:04dd9b1680ae 1345 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 86:04dd9b1680ae 1346 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 86:04dd9b1680ae 1347 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 86:04dd9b1680ae 1348 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
bogdanm 86:04dd9b1680ae 1349
bogdanm 86:04dd9b1680ae 1350 /* FMC_SDRAM Controller functions *********************************************/
bogdanm 86:04dd9b1680ae 1351 /* Initialization/de-initialization functions */
bogdanm 86:04dd9b1680ae 1352 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
bogdanm 86:04dd9b1680ae 1353 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1354 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1355
bogdanm 86:04dd9b1680ae 1356 /* FMC_SDRAM Control functions */
bogdanm 86:04dd9b1680ae 1357 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1358 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1359 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
bogdanm 86:04dd9b1680ae 1360 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
bogdanm 86:04dd9b1680ae 1361 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
bogdanm 86:04dd9b1680ae 1362 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm 86:04dd9b1680ae 1363
bogdanm 86:04dd9b1680ae 1364 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 1365 /**
bogdanm 86:04dd9b1680ae 1366 * @}
bogdanm 86:04dd9b1680ae 1367 */
bogdanm 86:04dd9b1680ae 1368
bogdanm 86:04dd9b1680ae 1369 /**
bogdanm 86:04dd9b1680ae 1370 * @}
bogdanm 86:04dd9b1680ae 1371 */
bogdanm 86:04dd9b1680ae 1372
bogdanm 86:04dd9b1680ae 1373 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 1374 }
bogdanm 86:04dd9b1680ae 1375 #endif
bogdanm 86:04dd9b1680ae 1376
bogdanm 86:04dd9b1680ae 1377 #endif /* __STM32F4xx_LL_FMC_H */
bogdanm 86:04dd9b1680ae 1378
bogdanm 86:04dd9b1680ae 1379 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/