frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

LPC2368/PeripheralNames.h@55:d722ed6a4237, 2013-01-16 (annotated)

Committer:
emilmont
Date:
Wed Jan 16 12:56:34 2013 +0000
Revision:
55:d722ed6a4237
Parent:
54:71b101360fb9
Child:
59:0883845fe643
Include "sleep_api.h" in "mbed.h"

Add initial IAR toolchain support

LPC I2C: better handling of status

Add sleep mode support for the LPC1768

Correct GCC "__semihost" definition

Correct GCC "_isatty" retargeting

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 44:24d45a770a51 1 /* mbed Microcontroller Library
emilmont 54:71b101360fb9 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 44:24d45a770a51 3 *
emilmont 44:24d45a770a51 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
emilmont 44:24d45a770a51 5 * of this software and associated documentation files (the "Software"), to deal
emilmont 44:24d45a770a51 6 * in the Software without restriction, including without limitation the rights
emilmont 44:24d45a770a51 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
emilmont 44:24d45a770a51 8 * copies of the Software, and to permit persons to whom the Software is
emilmont 44:24d45a770a51 9 * furnished to do so, subject to the following conditions:
emilmont 44:24d45a770a51 10 *
emilmont 44:24d45a770a51 11 * The above copyright notice and this permission notice shall be included in
emilmont 44:24d45a770a51 12 * all copies or substantial portions of the Software.
emilmont 44:24d45a770a51 13 *
emilmont 44:24d45a770a51 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
emilmont 44:24d45a770a51 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
emilmont 44:24d45a770a51 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
emilmont 44:24d45a770a51 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
emilmont 44:24d45a770a51 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
emilmont 44:24d45a770a51 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
emilmont 44:24d45a770a51 20 * SOFTWARE.
emilmont 44:24d45a770a51 21 */
emilmont 44:24d45a770a51 22 #ifndef MBED_PERIPHERALNAMES_H
emilmont 44:24d45a770a51 23 #define MBED_PERIPHERALNAMES_H
emilmont 44:24d45a770a51 24
emilmont 44:24d45a770a51 25 #include "cmsis.h"
emilmont 44:24d45a770a51 26
emilmont 44:24d45a770a51 27 #ifdef __cplusplus
emilmont 44:24d45a770a51 28 extern "C" {
emilmont 55:d722ed6a4237 29 #endif
emilmont 44:24d45a770a51 30
emilmont 44:24d45a770a51 31 typedef enum {
emilmont 44:24d45a770a51 32 UART_0 = (int)LPC_UART0_BASE,
emilmont 44:24d45a770a51 33 UART_1 = (int)LPC_UART1_BASE,
emilmont 44:24d45a770a51 34 UART_2 = (int)LPC_UART2_BASE,
emilmont 44:24d45a770a51 35 UART_3 = (int)LPC_UART3_BASE
emilmont 44:24d45a770a51 36 } UARTName;
emilmont 44:24d45a770a51 37
emilmont 44:24d45a770a51 38 typedef enum {
emilmont 44:24d45a770a51 39 ADC0_0 = 0,
emilmont 44:24d45a770a51 40 ADC0_1,
emilmont 44:24d45a770a51 41 ADC0_2,
emilmont 44:24d45a770a51 42 ADC0_3,
emilmont 44:24d45a770a51 43 ADC0_4,
emilmont 44:24d45a770a51 44 ADC0_5,
emilmont 44:24d45a770a51 45 ADC0_6,
emilmont 44:24d45a770a51 46 ADC0_7
emilmont 44:24d45a770a51 47 } ADCName;
emilmont 44:24d45a770a51 48
emilmont 44:24d45a770a51 49 typedef enum {
emilmont 44:24d45a770a51 50 DAC_0 = 0
emilmont 44:24d45a770a51 51 } DACName;
emilmont 44:24d45a770a51 52
emilmont 44:24d45a770a51 53 typedef enum {
emilmont 44:24d45a770a51 54 SPI_0 = (int)LPC_SSP0_BASE,
emilmont 44:24d45a770a51 55 SPI_1 = (int)LPC_SSP1_BASE
emilmont 44:24d45a770a51 56 } SPIName;
emilmont 44:24d45a770a51 57
emilmont 44:24d45a770a51 58 typedef enum {
emilmont 44:24d45a770a51 59 I2C_0 = (int)LPC_I2C0_BASE,
emilmont 44:24d45a770a51 60 I2C_1 = (int)LPC_I2C1_BASE,
emilmont 44:24d45a770a51 61 I2C_2 = (int)LPC_I2C2_BASE
emilmont 44:24d45a770a51 62 } I2CName;
emilmont 44:24d45a770a51 63
emilmont 44:24d45a770a51 64 typedef enum {
emilmont 44:24d45a770a51 65 PWM_1 = 1,
emilmont 44:24d45a770a51 66 PWM_2,
emilmont 44:24d45a770a51 67 PWM_3,
emilmont 44:24d45a770a51 68 PWM_4,
emilmont 55:d722ed6a4237 69 PWM_5,
emilmont 55:d722ed6a4237 70 PWM_6
emilmont 44:24d45a770a51 71 } PWMName;
emilmont 44:24d45a770a51 72
emilmont 55:d722ed6a4237 73 typedef enum {
emilmont 44:24d45a770a51 74 CAN_1 = (int)LPC_CAN1_BASE,
emilmont 44:24d45a770a51 75 CAN_2 = (int)LPC_CAN2_BASE
emilmont 44:24d45a770a51 76 } CANName;
emilmont 44:24d45a770a51 77
emilmont 44:24d45a770a51 78 #define STDIO_UART_TX USBTX
emilmont 44:24d45a770a51 79 #define STDIO_UART_RX USBRX
emilmont 44:24d45a770a51 80 #define STDIO_UART UART_0
emilmont 44:24d45a770a51 81
emilmont 44:24d45a770a51 82 #ifdef __cplusplus
emilmont 44:24d45a770a51 83 }
emilmont 44:24d45a770a51 84 #endif
emilmont 44:24d45a770a51 85
emilmont 44:24d45a770a51 86 #endif