frederic blanc
/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }
Fork of
mbed
by 
mbed official
TARGET_RZ_A1H/scux_iodefine.h@93:9dd889aeda0e, 2014-12-05 (annotated)
- Committer:
- fblanc
- Date:
- Fri Dec 05 15:42:32 2014 +0000
- Revision:
- 93:9dd889aeda0e
- Parent:
- 92:4fc01daae5a5
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 92:4fc01daae5a5 | 1 | /******************************************************************************* |
| bogdanm | 92:4fc01daae5a5 | 2 | * DISCLAIMER |
| bogdanm | 92:4fc01daae5a5 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| bogdanm | 92:4fc01daae5a5 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| bogdanm | 92:4fc01daae5a5 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| bogdanm | 92:4fc01daae5a5 | 6 | * all applicable laws, including copyright laws. |
| bogdanm | 92:4fc01daae5a5 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| bogdanm | 92:4fc01daae5a5 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| bogdanm | 92:4fc01daae5a5 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| bogdanm | 92:4fc01daae5a5 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| bogdanm | 92:4fc01daae5a5 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| bogdanm | 92:4fc01daae5a5 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| bogdanm | 92:4fc01daae5a5 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| bogdanm | 92:4fc01daae5a5 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| bogdanm | 92:4fc01daae5a5 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| bogdanm | 92:4fc01daae5a5 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| bogdanm | 92:4fc01daae5a5 | 17 | * and to discontinue the availability of this software. By using this software, |
| bogdanm | 92:4fc01daae5a5 | 18 | * you agree to the additional terms and conditions found by accessing the |
| bogdanm | 92:4fc01daae5a5 | 19 | * following link: |
| bogdanm | 92:4fc01daae5a5 | 20 | * http://www.renesas.com/disclaimer* |
| bogdanm | 92:4fc01daae5a5 | 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. |
| bogdanm | 92:4fc01daae5a5 | 22 | *******************************************************************************/ |
| bogdanm | 92:4fc01daae5a5 | 23 | /******************************************************************************* |
| bogdanm | 92:4fc01daae5a5 | 24 | * File Name : scux_iodefine.h |
| bogdanm | 92:4fc01daae5a5 | 25 | * $Rev: $ |
| bogdanm | 92:4fc01daae5a5 | 26 | * $Date:: $ |
| bogdanm | 92:4fc01daae5a5 | 27 | * Description : Definition of I/O Register (V1.00a) |
| bogdanm | 92:4fc01daae5a5 | 28 | ******************************************************************************/ |
| bogdanm | 92:4fc01daae5a5 | 29 | #ifndef SCUX_IODEFINE_H |
| bogdanm | 92:4fc01daae5a5 | 30 | #define SCUX_IODEFINE_H |
| bogdanm | 92:4fc01daae5a5 | 31 | /* ->QAC 0639 : Over 127 members (C90) */ |
| bogdanm | 92:4fc01daae5a5 | 32 | /* ->SEC M1.10.1 : Not magic number */ |
| bogdanm | 92:4fc01daae5a5 | 33 | |
| bogdanm | 92:4fc01daae5a5 | 34 | struct st_scux |
| bogdanm | 92:4fc01daae5a5 | 35 | { /* SCUX */ |
| bogdanm | 92:4fc01daae5a5 | 36 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 37 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 38 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 39 | volatile uint8_t dummy259[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 40 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 41 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 42 | volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 43 | volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 44 | volatile uint8_t dummy260[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 45 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 46 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 47 | volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 48 | volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 49 | volatile uint8_t dummy261[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 50 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 51 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 52 | volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 53 | volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 54 | volatile uint8_t dummy262[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 55 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 56 | /* start of struct st_scux_from_opcir_opc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 57 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 58 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 59 | volatile uint8_t dummy263[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 60 | /* end of struct st_scux_from_opcir_opc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 61 | /* start of struct st_scux_from_opcir_opc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 62 | volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 63 | volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 64 | volatile uint8_t dummy264[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 65 | /* end of struct st_scux_from_opcir_opc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 66 | /* start of struct st_scux_from_opcir_opc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 67 | volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 68 | volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 69 | volatile uint8_t dummy265[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 70 | /* end of struct st_scux_from_opcir_opc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 71 | /* start of struct st_scux_from_opcir_opc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 72 | volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 73 | volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 74 | volatile uint8_t dummy266[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 75 | /* end of struct st_scux_from_opcir_opc0_n */ |
| bogdanm | 92:4fc01daae5a5 | 76 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
| bogdanm | 92:4fc01daae5a5 | 77 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 78 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 79 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 80 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 81 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 82 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 83 | volatile uint8_t dummy267[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 84 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 85 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
| bogdanm | 92:4fc01daae5a5 | 86 | volatile uint8_t dummy268[224]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 87 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
| bogdanm | 92:4fc01daae5a5 | 88 | volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 89 | volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 90 | volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 91 | volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 92 | volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 93 | volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 94 | volatile uint8_t dummy269[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 95 | volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 96 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
| bogdanm | 92:4fc01daae5a5 | 97 | volatile uint8_t dummy270[224]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 98 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
| bogdanm | 92:4fc01daae5a5 | 99 | volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 100 | volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 101 | volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 102 | volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 103 | volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 104 | volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 105 | volatile uint8_t dummy271[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 106 | volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 107 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
| bogdanm | 92:4fc01daae5a5 | 108 | volatile uint8_t dummy272[224]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 109 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
| bogdanm | 92:4fc01daae5a5 | 110 | volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 111 | volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 112 | volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 113 | volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 114 | volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 115 | volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 116 | volatile uint8_t dummy273[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 117 | volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 118 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
| bogdanm | 92:4fc01daae5a5 | 119 | volatile uint8_t dummy274[224]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 120 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 121 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 122 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 123 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 124 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 125 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 126 | volatile uint8_t dummy275[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 127 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 128 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 129 | volatile uint8_t dummy276[228]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 130 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 131 | volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 132 | volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 133 | volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 134 | volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 135 | volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 136 | volatile uint8_t dummy277[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 137 | volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 138 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 139 | volatile uint8_t dummy278[228]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 140 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 141 | volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 142 | volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 143 | volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 144 | volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 145 | volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 146 | volatile uint8_t dummy279[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 147 | volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 148 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 149 | volatile uint8_t dummy280[228]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 150 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 151 | volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 152 | volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 153 | volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 154 | volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 155 | volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 156 | volatile uint8_t dummy281[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 157 | volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 158 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 159 | volatile uint8_t dummy282[228]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 160 | /* start of struct st_scux_from_srcir0_2src0_n */ |
| bogdanm | 92:4fc01daae5a5 | 161 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 162 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 163 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 164 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 165 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 166 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 167 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 168 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 169 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 170 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 171 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 172 | volatile uint8_t dummy283[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 173 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 174 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 175 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 176 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 177 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 178 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 179 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 180 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 181 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 182 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 183 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 184 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 185 | volatile uint8_t dummy284[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 186 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 187 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 188 | /* end of struct st_scux_from_srcir0_2src0_n */ |
| bogdanm | 92:4fc01daae5a5 | 189 | volatile uint8_t dummy285[148]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 190 | /* start of struct st_scux_from_srcir0_2src0_n */ |
| bogdanm | 92:4fc01daae5a5 | 191 | volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 192 | volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 193 | volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 194 | volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 195 | volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 196 | volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 197 | volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 198 | volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 199 | volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 200 | volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 201 | volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 202 | volatile uint8_t dummy286[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 203 | volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 204 | volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 205 | volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 206 | volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 207 | volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 208 | volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 209 | volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 210 | volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 211 | volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 212 | volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 213 | volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 214 | volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 215 | volatile uint8_t dummy287[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 216 | volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 217 | volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 218 | /* end of struct st_scux_from_srcir0_2src0_n */ |
| bogdanm | 92:4fc01daae5a5 | 219 | volatile uint8_t dummy288[148]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 220 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 221 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 222 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 223 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 224 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 225 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 226 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 227 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 228 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 229 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 230 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 231 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 232 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 233 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 234 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 235 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 236 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 237 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 238 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 239 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 240 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 241 | volatile uint8_t dummy289[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 242 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 243 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 244 | volatile uint8_t dummy290[168]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 245 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 246 | volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 247 | volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 248 | volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 249 | volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 250 | volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 251 | volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 252 | volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 253 | volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 254 | volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 255 | volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 256 | volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 257 | volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 258 | volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 259 | volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 260 | volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 261 | volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 262 | volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 263 | volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 264 | volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 265 | volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 266 | volatile uint8_t dummy291[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 267 | volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 268 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 269 | volatile uint8_t dummy292[168]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 270 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 271 | volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 272 | volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 273 | volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 274 | volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 275 | volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 276 | volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 277 | volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 278 | volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 279 | volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 280 | volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 281 | volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 282 | volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 283 | volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 284 | volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 285 | volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 286 | volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 287 | volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 288 | volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 289 | volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 290 | volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 291 | volatile uint8_t dummy293[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 292 | volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 293 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 294 | volatile uint8_t dummy294[168]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 295 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 296 | volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 297 | volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 298 | volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 299 | volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 300 | volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 301 | volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 302 | volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 303 | volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 304 | volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 305 | volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 306 | volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 307 | volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 308 | volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 309 | volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 310 | volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 311 | volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 312 | volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 313 | volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 314 | volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 315 | volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 316 | volatile uint8_t dummy295[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 317 | volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 318 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
| bogdanm | 92:4fc01daae5a5 | 319 | volatile uint8_t dummy296[168]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 320 | volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 321 | volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 322 | volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 323 | volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 324 | volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 325 | volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 326 | volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 327 | volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 328 | volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 329 | volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 330 | volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 331 | volatile uint8_t dummy297[212]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 332 | volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 333 | volatile uint32_t DMACR_CIM; /* DMACR_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 334 | #define SCUX_DMATDn_CIM_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 335 | union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 336 | union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 337 | union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 338 | union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 339 | #define SCUX_DMATUn_CIM_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 340 | union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 341 | union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 342 | union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 343 | union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 344 | |
| bogdanm | 92:4fc01daae5a5 | 345 | volatile uint8_t dummy298[16]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 346 | volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 347 | #define SCUX_FDTSELn_CIM_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 348 | volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 349 | volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 350 | volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 351 | volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 352 | #define SCUX_FUTSELn_CIM_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 353 | volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 354 | volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 355 | volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 356 | volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 357 | volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 358 | volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 359 | #define SCUX_SRCRSELn_CIM_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 360 | volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 361 | volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 362 | volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 363 | volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 364 | volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ |
| bogdanm | 92:4fc01daae5a5 | 365 | }; |
| bogdanm | 92:4fc01daae5a5 | 366 | |
| bogdanm | 92:4fc01daae5a5 | 367 | |
| bogdanm | 92:4fc01daae5a5 | 368 | struct st_scux_from_ipcir_ipc0_n |
| bogdanm | 92:4fc01daae5a5 | 369 | { |
| bogdanm | 92:4fc01daae5a5 | 370 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 371 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 372 | volatile uint8_t dummy1[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 373 | }; |
| bogdanm | 92:4fc01daae5a5 | 374 | |
| bogdanm | 92:4fc01daae5a5 | 375 | |
| bogdanm | 92:4fc01daae5a5 | 376 | struct st_scux_from_opcir_opc0_n |
| bogdanm | 92:4fc01daae5a5 | 377 | { |
| bogdanm | 92:4fc01daae5a5 | 378 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 379 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 380 | volatile uint8_t dummy1[248]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 381 | }; |
| bogdanm | 92:4fc01daae5a5 | 382 | |
| bogdanm | 92:4fc01daae5a5 | 383 | |
| bogdanm | 92:4fc01daae5a5 | 384 | struct st_scux_from_ffdir_ffd0_n |
| bogdanm | 92:4fc01daae5a5 | 385 | { |
| bogdanm | 92:4fc01daae5a5 | 386 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 387 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 388 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 389 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 390 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 391 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 392 | volatile uint8_t dummy1[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 393 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 394 | }; |
| bogdanm | 92:4fc01daae5a5 | 395 | |
| bogdanm | 92:4fc01daae5a5 | 396 | |
| bogdanm | 92:4fc01daae5a5 | 397 | struct st_scux_from_ffuir_ffu0_n |
| bogdanm | 92:4fc01daae5a5 | 398 | { |
| bogdanm | 92:4fc01daae5a5 | 399 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 400 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 401 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 402 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 403 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 404 | volatile uint8_t dummy1[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 405 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 406 | }; |
| bogdanm | 92:4fc01daae5a5 | 407 | |
| bogdanm | 92:4fc01daae5a5 | 408 | |
| bogdanm | 92:4fc01daae5a5 | 409 | struct st_scux_from_srcir0_2src0_n |
| bogdanm | 92:4fc01daae5a5 | 410 | { |
| bogdanm | 92:4fc01daae5a5 | 411 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 412 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 413 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 414 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 415 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 416 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 417 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 418 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 419 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 420 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 421 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 422 | volatile uint8_t dummy1[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 423 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 424 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 425 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 426 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 427 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 428 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 429 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 430 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 431 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 432 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 433 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 434 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 435 | volatile uint8_t dummy2[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 436 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 437 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 438 | }; |
| bogdanm | 92:4fc01daae5a5 | 439 | |
| bogdanm | 92:4fc01daae5a5 | 440 | |
| bogdanm | 92:4fc01daae5a5 | 441 | struct st_scux_from_dvuir_dvu0_n |
| bogdanm | 92:4fc01daae5a5 | 442 | { |
| bogdanm | 92:4fc01daae5a5 | 443 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 444 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 445 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 446 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 447 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 448 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 449 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 450 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 451 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 452 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 453 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 454 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 455 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 456 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 457 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 458 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 459 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 460 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 461 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 462 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 463 | volatile uint8_t dummy1[4]; /* */ |
| bogdanm | 92:4fc01daae5a5 | 464 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 465 | }; |
| bogdanm | 92:4fc01daae5a5 | 466 | |
| bogdanm | 92:4fc01daae5a5 | 467 | |
| bogdanm | 92:4fc01daae5a5 | 468 | #define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ |
| bogdanm | 92:4fc01daae5a5 | 469 | |
| bogdanm | 92:4fc01daae5a5 | 470 | |
| bogdanm | 92:4fc01daae5a5 | 471 | /* Start of channnel array defines of SCUX */ |
| bogdanm | 92:4fc01daae5a5 | 472 | |
| bogdanm | 92:4fc01daae5a5 | 473 | /* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ |
| bogdanm | 92:4fc01daae5a5 | 474 | /*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ |
| bogdanm | 92:4fc01daae5a5 | 475 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 476 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ |
| bogdanm | 92:4fc01daae5a5 | 477 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| bogdanm | 92:4fc01daae5a5 | 478 | &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ |
| bogdanm | 92:4fc01daae5a5 | 479 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| bogdanm | 92:4fc01daae5a5 | 480 | #define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 481 | #define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 482 | #define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 483 | #define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 484 | |
| bogdanm | 92:4fc01daae5a5 | 485 | |
| bogdanm | 92:4fc01daae5a5 | 486 | /* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ |
| bogdanm | 92:4fc01daae5a5 | 487 | /*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ |
| bogdanm | 92:4fc01daae5a5 | 488 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2 |
| bogdanm | 92:4fc01daae5a5 | 489 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ |
| bogdanm | 92:4fc01daae5a5 | 490 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| bogdanm | 92:4fc01daae5a5 | 491 | &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ |
| bogdanm | 92:4fc01daae5a5 | 492 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| bogdanm | 92:4fc01daae5a5 | 493 | #define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 494 | #define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 495 | |
| bogdanm | 92:4fc01daae5a5 | 496 | |
| bogdanm | 92:4fc01daae5a5 | 497 | /* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ |
| bogdanm | 92:4fc01daae5a5 | 498 | /*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ |
| bogdanm | 92:4fc01daae5a5 | 499 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 500 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ |
| bogdanm | 92:4fc01daae5a5 | 501 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| bogdanm | 92:4fc01daae5a5 | 502 | &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ |
| bogdanm | 92:4fc01daae5a5 | 503 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| bogdanm | 92:4fc01daae5a5 | 504 | #define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 505 | #define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 506 | #define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 507 | #define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 508 | |
| bogdanm | 92:4fc01daae5a5 | 509 | |
| bogdanm | 92:4fc01daae5a5 | 510 | /* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ |
| bogdanm | 92:4fc01daae5a5 | 511 | /*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ |
| bogdanm | 92:4fc01daae5a5 | 512 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 513 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ |
| bogdanm | 92:4fc01daae5a5 | 514 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| bogdanm | 92:4fc01daae5a5 | 515 | &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ |
| bogdanm | 92:4fc01daae5a5 | 516 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| bogdanm | 92:4fc01daae5a5 | 517 | #define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 518 | #define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 519 | #define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 520 | #define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 521 | |
| bogdanm | 92:4fc01daae5a5 | 522 | |
| bogdanm | 92:4fc01daae5a5 | 523 | /* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ |
| bogdanm | 92:4fc01daae5a5 | 524 | /*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ |
| bogdanm | 92:4fc01daae5a5 | 525 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 526 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ |
| bogdanm | 92:4fc01daae5a5 | 527 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| bogdanm | 92:4fc01daae5a5 | 528 | &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ |
| bogdanm | 92:4fc01daae5a5 | 529 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| bogdanm | 92:4fc01daae5a5 | 530 | #define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 531 | #define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 532 | #define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 533 | #define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 534 | |
| bogdanm | 92:4fc01daae5a5 | 535 | |
| bogdanm | 92:4fc01daae5a5 | 536 | /* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ |
| bogdanm | 92:4fc01daae5a5 | 537 | /*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ |
| bogdanm | 92:4fc01daae5a5 | 538 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4 |
| bogdanm | 92:4fc01daae5a5 | 539 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ |
| bogdanm | 92:4fc01daae5a5 | 540 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| bogdanm | 92:4fc01daae5a5 | 541 | &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ |
| bogdanm | 92:4fc01daae5a5 | 542 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| bogdanm | 92:4fc01daae5a5 | 543 | #define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ |
| bogdanm | 92:4fc01daae5a5 | 544 | #define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ |
| bogdanm | 92:4fc01daae5a5 | 545 | #define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ |
| bogdanm | 92:4fc01daae5a5 | 546 | #define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ |
| bogdanm | 92:4fc01daae5a5 | 547 | |
| bogdanm | 92:4fc01daae5a5 | 548 | /* End of channnel array defines of SCUX */ |
| bogdanm | 92:4fc01daae5a5 | 549 | |
| bogdanm | 92:4fc01daae5a5 | 550 | |
| bogdanm | 92:4fc01daae5a5 | 551 | #define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0 |
| bogdanm | 92:4fc01daae5a5 | 552 | #define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0 |
| bogdanm | 92:4fc01daae5a5 | 553 | #define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1 |
| bogdanm | 92:4fc01daae5a5 | 554 | #define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1 |
| bogdanm | 92:4fc01daae5a5 | 555 | #define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2 |
| bogdanm | 92:4fc01daae5a5 | 556 | #define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2 |
| bogdanm | 92:4fc01daae5a5 | 557 | #define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3 |
| bogdanm | 92:4fc01daae5a5 | 558 | #define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3 |
| bogdanm | 92:4fc01daae5a5 | 559 | #define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0 |
| bogdanm | 92:4fc01daae5a5 | 560 | #define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0 |
| bogdanm | 92:4fc01daae5a5 | 561 | #define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1 |
| bogdanm | 92:4fc01daae5a5 | 562 | #define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1 |
| bogdanm | 92:4fc01daae5a5 | 563 | #define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2 |
| bogdanm | 92:4fc01daae5a5 | 564 | #define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2 |
| bogdanm | 92:4fc01daae5a5 | 565 | #define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3 |
| bogdanm | 92:4fc01daae5a5 | 566 | #define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3 |
| bogdanm | 92:4fc01daae5a5 | 567 | #define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0 |
| bogdanm | 92:4fc01daae5a5 | 568 | #define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0 |
| bogdanm | 92:4fc01daae5a5 | 569 | #define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0 |
| bogdanm | 92:4fc01daae5a5 | 570 | #define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0 |
| bogdanm | 92:4fc01daae5a5 | 571 | #define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0 |
| bogdanm | 92:4fc01daae5a5 | 572 | #define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0 |
| bogdanm | 92:4fc01daae5a5 | 573 | #define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0 |
| bogdanm | 92:4fc01daae5a5 | 574 | #define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1 |
| bogdanm | 92:4fc01daae5a5 | 575 | #define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1 |
| bogdanm | 92:4fc01daae5a5 | 576 | #define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1 |
| bogdanm | 92:4fc01daae5a5 | 577 | #define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1 |
| bogdanm | 92:4fc01daae5a5 | 578 | #define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1 |
| bogdanm | 92:4fc01daae5a5 | 579 | #define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1 |
| bogdanm | 92:4fc01daae5a5 | 580 | #define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1 |
| bogdanm | 92:4fc01daae5a5 | 581 | #define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2 |
| bogdanm | 92:4fc01daae5a5 | 582 | #define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2 |
| bogdanm | 92:4fc01daae5a5 | 583 | #define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2 |
| bogdanm | 92:4fc01daae5a5 | 584 | #define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2 |
| bogdanm | 92:4fc01daae5a5 | 585 | #define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2 |
| bogdanm | 92:4fc01daae5a5 | 586 | #define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2 |
| bogdanm | 92:4fc01daae5a5 | 587 | #define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2 |
| bogdanm | 92:4fc01daae5a5 | 588 | #define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3 |
| bogdanm | 92:4fc01daae5a5 | 589 | #define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3 |
| bogdanm | 92:4fc01daae5a5 | 590 | #define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3 |
| bogdanm | 92:4fc01daae5a5 | 591 | #define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3 |
| bogdanm | 92:4fc01daae5a5 | 592 | #define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3 |
| bogdanm | 92:4fc01daae5a5 | 593 | #define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3 |
| bogdanm | 92:4fc01daae5a5 | 594 | #define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3 |
| bogdanm | 92:4fc01daae5a5 | 595 | #define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0 |
| bogdanm | 92:4fc01daae5a5 | 596 | #define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0 |
| bogdanm | 92:4fc01daae5a5 | 597 | #define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0 |
| bogdanm | 92:4fc01daae5a5 | 598 | #define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0 |
| bogdanm | 92:4fc01daae5a5 | 599 | #define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0 |
| bogdanm | 92:4fc01daae5a5 | 600 | #define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0 |
| bogdanm | 92:4fc01daae5a5 | 601 | #define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1 |
| bogdanm | 92:4fc01daae5a5 | 602 | #define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1 |
| bogdanm | 92:4fc01daae5a5 | 603 | #define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1 |
| bogdanm | 92:4fc01daae5a5 | 604 | #define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1 |
| bogdanm | 92:4fc01daae5a5 | 605 | #define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1 |
| bogdanm | 92:4fc01daae5a5 | 606 | #define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1 |
| bogdanm | 92:4fc01daae5a5 | 607 | #define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2 |
| bogdanm | 92:4fc01daae5a5 | 608 | #define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2 |
| bogdanm | 92:4fc01daae5a5 | 609 | #define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2 |
| bogdanm | 92:4fc01daae5a5 | 610 | #define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2 |
| bogdanm | 92:4fc01daae5a5 | 611 | #define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2 |
| bogdanm | 92:4fc01daae5a5 | 612 | #define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2 |
| bogdanm | 92:4fc01daae5a5 | 613 | #define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3 |
| bogdanm | 92:4fc01daae5a5 | 614 | #define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3 |
| bogdanm | 92:4fc01daae5a5 | 615 | #define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3 |
| bogdanm | 92:4fc01daae5a5 | 616 | #define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3 |
| bogdanm | 92:4fc01daae5a5 | 617 | #define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3 |
| bogdanm | 92:4fc01daae5a5 | 618 | #define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3 |
| bogdanm | 92:4fc01daae5a5 | 619 | #define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 620 | #define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 621 | #define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 622 | #define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 623 | #define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 624 | #define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 625 | #define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 626 | #define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 627 | #define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 628 | #define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 629 | #define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 630 | #define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 631 | #define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 632 | #define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 633 | #define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 634 | #define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 635 | #define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 636 | #define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 637 | #define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 638 | #define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 639 | #define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 640 | #define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 641 | #define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 642 | #define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 643 | #define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0 |
| bogdanm | 92:4fc01daae5a5 | 644 | #define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 645 | #define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 646 | #define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 647 | #define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 648 | #define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 649 | #define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 650 | #define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 651 | #define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 652 | #define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 653 | #define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 654 | #define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 655 | #define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 656 | #define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 657 | #define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 658 | #define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 659 | #define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 660 | #define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 661 | #define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 662 | #define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 663 | #define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 664 | #define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 665 | #define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 666 | #define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 667 | #define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 668 | #define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1 |
| bogdanm | 92:4fc01daae5a5 | 669 | #define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 670 | #define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 671 | #define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 672 | #define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 673 | #define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 674 | #define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 675 | #define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 676 | #define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 677 | #define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 678 | #define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 679 | #define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 680 | #define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 681 | #define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 682 | #define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 683 | #define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 684 | #define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 685 | #define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 686 | #define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 687 | #define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 688 | #define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 689 | #define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0 |
| bogdanm | 92:4fc01daae5a5 | 690 | #define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 691 | #define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 692 | #define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 693 | #define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 694 | #define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 695 | #define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 696 | #define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 697 | #define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 698 | #define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 699 | #define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 700 | #define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 701 | #define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 702 | #define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 703 | #define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 704 | #define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 705 | #define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 706 | #define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 707 | #define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 708 | #define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 709 | #define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 710 | #define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1 |
| bogdanm | 92:4fc01daae5a5 | 711 | #define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 712 | #define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 713 | #define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 714 | #define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 715 | #define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 716 | #define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 717 | #define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 718 | #define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 719 | #define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 720 | #define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 721 | #define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 722 | #define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 723 | #define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 724 | #define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 725 | #define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 726 | #define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 727 | #define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 728 | #define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 729 | #define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 730 | #define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 731 | #define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2 |
| bogdanm | 92:4fc01daae5a5 | 732 | #define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 733 | #define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 734 | #define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 735 | #define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 736 | #define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 737 | #define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 738 | #define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 739 | #define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 740 | #define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 741 | #define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 742 | #define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 743 | #define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 744 | #define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 745 | #define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 746 | #define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 747 | #define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 748 | #define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 749 | #define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 750 | #define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 751 | #define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 752 | #define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3 |
| bogdanm | 92:4fc01daae5a5 | 753 | #define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 754 | #define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 755 | #define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 756 | #define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 757 | #define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 758 | #define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 759 | #define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 760 | #define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 761 | #define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 762 | #define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 763 | #define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0 |
| bogdanm | 92:4fc01daae5a5 | 764 | #define SCUXSWRSR_CIM SCUX.SWRSR_CIM |
| bogdanm | 92:4fc01daae5a5 | 765 | #define SCUXDMACR_CIM SCUX.DMACR_CIM |
| bogdanm | 92:4fc01daae5a5 | 766 | #define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32 |
| bogdanm | 92:4fc01daae5a5 | 767 | #define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L] |
| bogdanm | 92:4fc01daae5a5 | 768 | #define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H] |
| bogdanm | 92:4fc01daae5a5 | 769 | #define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32 |
| bogdanm | 92:4fc01daae5a5 | 770 | #define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L] |
| bogdanm | 92:4fc01daae5a5 | 771 | #define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H] |
| bogdanm | 92:4fc01daae5a5 | 772 | #define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32 |
| bogdanm | 92:4fc01daae5a5 | 773 | #define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L] |
| bogdanm | 92:4fc01daae5a5 | 774 | #define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H] |
| bogdanm | 92:4fc01daae5a5 | 775 | #define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32 |
| bogdanm | 92:4fc01daae5a5 | 776 | #define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L] |
| bogdanm | 92:4fc01daae5a5 | 777 | #define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H] |
| bogdanm | 92:4fc01daae5a5 | 778 | #define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32 |
| bogdanm | 92:4fc01daae5a5 | 779 | #define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L] |
| bogdanm | 92:4fc01daae5a5 | 780 | #define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H] |
| bogdanm | 92:4fc01daae5a5 | 781 | #define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32 |
| bogdanm | 92:4fc01daae5a5 | 782 | #define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L] |
| bogdanm | 92:4fc01daae5a5 | 783 | #define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H] |
| bogdanm | 92:4fc01daae5a5 | 784 | #define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32 |
| bogdanm | 92:4fc01daae5a5 | 785 | #define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L] |
| bogdanm | 92:4fc01daae5a5 | 786 | #define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H] |
| bogdanm | 92:4fc01daae5a5 | 787 | #define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32 |
| bogdanm | 92:4fc01daae5a5 | 788 | #define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L] |
| bogdanm | 92:4fc01daae5a5 | 789 | #define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H] |
| bogdanm | 92:4fc01daae5a5 | 790 | #define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM |
| bogdanm | 92:4fc01daae5a5 | 791 | #define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM |
| bogdanm | 92:4fc01daae5a5 | 792 | #define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM |
| bogdanm | 92:4fc01daae5a5 | 793 | #define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM |
| bogdanm | 92:4fc01daae5a5 | 794 | #define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM |
| bogdanm | 92:4fc01daae5a5 | 795 | #define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM |
| bogdanm | 92:4fc01daae5a5 | 796 | #define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM |
| bogdanm | 92:4fc01daae5a5 | 797 | #define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM |
| bogdanm | 92:4fc01daae5a5 | 798 | #define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM |
| bogdanm | 92:4fc01daae5a5 | 799 | #define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM |
| bogdanm | 92:4fc01daae5a5 | 800 | #define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM |
| bogdanm | 92:4fc01daae5a5 | 801 | #define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM |
| bogdanm | 92:4fc01daae5a5 | 802 | #define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM |
| bogdanm | 92:4fc01daae5a5 | 803 | #define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM |
| bogdanm | 92:4fc01daae5a5 | 804 | #define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM |
| bogdanm | 92:4fc01daae5a5 | 805 | #define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM |
| bogdanm | 92:4fc01daae5a5 | 806 | /* <-SEC M1.10.1 */ |
| bogdanm | 92:4fc01daae5a5 | 807 | /* <-QAC 0639 */ |
| bogdanm | 92:4fc01daae5a5 | 808 | #endif |