frederic blanc
/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }
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TARGET_NUCLEO_L152RE/stm32l1xx_hal_rcc_ex.h@93:9dd889aeda0e, 2014-12-05 (annotated)
- Committer:
- fblanc
- Date:
- Fri Dec 05 15:42:32 2014 +0000
- Revision:
- 93:9dd889aeda0e
- Parent:
- 90:cb3d968589d8
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 90:cb3d968589d8 | 1 | /** |
| Kojto | 90:cb3d968589d8 | 2 | ****************************************************************************** |
| Kojto | 90:cb3d968589d8 | 3 | * @file stm32l1xx_hal_rcc_ex.h |
| Kojto | 90:cb3d968589d8 | 4 | * @author MCD Application Team |
| Kojto | 90:cb3d968589d8 | 5 | * @version V1.0.0 |
| Kojto | 90:cb3d968589d8 | 6 | * @date 5-September-2014 |
| Kojto | 90:cb3d968589d8 | 7 | * @brief Header file of RCC HAL Extension module. |
| Kojto | 90:cb3d968589d8 | 8 | ****************************************************************************** |
| Kojto | 90:cb3d968589d8 | 9 | * @attention |
| Kojto | 90:cb3d968589d8 | 10 | * |
| Kojto | 90:cb3d968589d8 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| Kojto | 90:cb3d968589d8 | 12 | * |
| Kojto | 90:cb3d968589d8 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 90:cb3d968589d8 | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 90:cb3d968589d8 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 90:cb3d968589d8 | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 90:cb3d968589d8 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 90:cb3d968589d8 | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 90:cb3d968589d8 | 19 | * and/or other materials provided with the distribution. |
| Kojto | 90:cb3d968589d8 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 90:cb3d968589d8 | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 90:cb3d968589d8 | 22 | * without specific prior written permission. |
| Kojto | 90:cb3d968589d8 | 23 | * |
| Kojto | 90:cb3d968589d8 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 90:cb3d968589d8 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 90:cb3d968589d8 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 90:cb3d968589d8 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 90:cb3d968589d8 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 90:cb3d968589d8 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 90:cb3d968589d8 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 90:cb3d968589d8 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 90:cb3d968589d8 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 90:cb3d968589d8 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 90:cb3d968589d8 | 34 | * |
| Kojto | 90:cb3d968589d8 | 35 | ****************************************************************************** |
| Kojto | 90:cb3d968589d8 | 36 | */ |
| Kojto | 90:cb3d968589d8 | 37 | |
| Kojto | 90:cb3d968589d8 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 90:cb3d968589d8 | 39 | #ifndef __STM32L1xx_HAL_RCC_EX_H |
| Kojto | 90:cb3d968589d8 | 40 | #define __STM32L1xx_HAL_RCC_EX_H |
| Kojto | 90:cb3d968589d8 | 41 | |
| Kojto | 90:cb3d968589d8 | 42 | #ifdef __cplusplus |
| Kojto | 90:cb3d968589d8 | 43 | extern "C" { |
| Kojto | 90:cb3d968589d8 | 44 | #endif |
| Kojto | 90:cb3d968589d8 | 45 | |
| Kojto | 90:cb3d968589d8 | 46 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 90:cb3d968589d8 | 47 | #include "stm32l1xx_hal_def.h" |
| Kojto | 90:cb3d968589d8 | 48 | |
| Kojto | 90:cb3d968589d8 | 49 | /** @addtogroup STM32L1xx_HAL_Driver |
| Kojto | 90:cb3d968589d8 | 50 | * @{ |
| Kojto | 90:cb3d968589d8 | 51 | */ |
| Kojto | 90:cb3d968589d8 | 52 | |
| Kojto | 90:cb3d968589d8 | 53 | /** @addtogroup RCCEx |
| Kojto | 90:cb3d968589d8 | 54 | * @{ |
| Kojto | 90:cb3d968589d8 | 55 | */ |
| Kojto | 90:cb3d968589d8 | 56 | |
| Kojto | 90:cb3d968589d8 | 57 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 90:cb3d968589d8 | 58 | |
| Kojto | 90:cb3d968589d8 | 59 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
| Kojto | 90:cb3d968589d8 | 60 | * @{ |
| Kojto | 90:cb3d968589d8 | 61 | */ |
| Kojto | 90:cb3d968589d8 | 62 | |
| Kojto | 90:cb3d968589d8 | 63 | /** |
| Kojto | 90:cb3d968589d8 | 64 | * @brief RCC extended clocks structure definition |
| Kojto | 90:cb3d968589d8 | 65 | */ |
| Kojto | 90:cb3d968589d8 | 66 | typedef struct |
| Kojto | 90:cb3d968589d8 | 67 | { |
| Kojto | 90:cb3d968589d8 | 68 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| Kojto | 90:cb3d968589d8 | 69 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| Kojto | 90:cb3d968589d8 | 70 | |
| Kojto | 90:cb3d968589d8 | 71 | uint32_t RTCClockSelection; /*!< specifies the RTC clock source. |
| Kojto | 90:cb3d968589d8 | 72 | This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ |
| Kojto | 90:cb3d968589d8 | 73 | |
| Kojto | 90:cb3d968589d8 | 74 | #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ |
| Kojto | 90:cb3d968589d8 | 75 | defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ |
| Kojto | 90:cb3d968589d8 | 76 | defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ |
| Kojto | 90:cb3d968589d8 | 77 | defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ |
| Kojto | 90:cb3d968589d8 | 78 | defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 79 | |
| Kojto | 90:cb3d968589d8 | 80 | uint32_t LCDClockSelection; /*!< specifies the LCD clock source. |
| Kojto | 90:cb3d968589d8 | 81 | This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ |
| Kojto | 90:cb3d968589d8 | 82 | |
| Kojto | 90:cb3d968589d8 | 83 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 84 | } RCC_PeriphCLKInitTypeDef; |
| Kojto | 90:cb3d968589d8 | 85 | |
| Kojto | 90:cb3d968589d8 | 86 | /** |
| Kojto | 90:cb3d968589d8 | 87 | * @} |
| Kojto | 90:cb3d968589d8 | 88 | */ |
| Kojto | 90:cb3d968589d8 | 89 | |
| Kojto | 90:cb3d968589d8 | 90 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 90:cb3d968589d8 | 91 | |
| Kojto | 90:cb3d968589d8 | 92 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
| Kojto | 90:cb3d968589d8 | 93 | * @{ |
| Kojto | 90:cb3d968589d8 | 94 | */ |
| Kojto | 90:cb3d968589d8 | 95 | |
| Kojto | 90:cb3d968589d8 | 96 | /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection |
| Kojto | 90:cb3d968589d8 | 97 | * @{ |
| Kojto | 90:cb3d968589d8 | 98 | */ |
| Kojto | 90:cb3d968589d8 | 99 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001) |
| Kojto | 90:cb3d968589d8 | 100 | |
| Kojto | 90:cb3d968589d8 | 101 | #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ |
| Kojto | 90:cb3d968589d8 | 102 | defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ |
| Kojto | 90:cb3d968589d8 | 103 | defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ |
| Kojto | 90:cb3d968589d8 | 104 | defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ |
| Kojto | 90:cb3d968589d8 | 105 | defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 106 | |
| Kojto | 90:cb3d968589d8 | 107 | #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002) |
| Kojto | 90:cb3d968589d8 | 108 | |
| Kojto | 90:cb3d968589d8 | 109 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 110 | |
| Kojto | 90:cb3d968589d8 | 111 | #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ |
| Kojto | 90:cb3d968589d8 | 112 | defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ |
| Kojto | 90:cb3d968589d8 | 113 | defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ |
| Kojto | 90:cb3d968589d8 | 114 | defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ |
| Kojto | 90:cb3d968589d8 | 115 | defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 116 | |
| Kojto | 90:cb3d968589d8 | 117 | #define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) |
| Kojto | 90:cb3d968589d8 | 118 | |
| Kojto | 90:cb3d968589d8 | 119 | #else /* Not LCD LINE */ |
| Kojto | 90:cb3d968589d8 | 120 | |
| Kojto | 90:cb3d968589d8 | 121 | #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) |
| Kojto | 90:cb3d968589d8 | 122 | |
| Kojto | 90:cb3d968589d8 | 123 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 124 | /** |
| Kojto | 90:cb3d968589d8 | 125 | * @} |
| Kojto | 90:cb3d968589d8 | 126 | */ |
| Kojto | 90:cb3d968589d8 | 127 | |
| Kojto | 90:cb3d968589d8 | 128 | #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ |
| Kojto | 90:cb3d968589d8 | 129 | defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 130 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 131 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 132 | |
| Kojto | 90:cb3d968589d8 | 133 | /* Alias word address of LSECSSON bit */ |
| Kojto | 90:cb3d968589d8 | 134 | #define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON) |
| Kojto | 90:cb3d968589d8 | 135 | #define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4))) |
| Kojto | 90:cb3d968589d8 | 136 | |
| Kojto | 90:cb3d968589d8 | 137 | #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ |
| Kojto | 90:cb3d968589d8 | 138 | |
| Kojto | 90:cb3d968589d8 | 139 | /** |
| Kojto | 90:cb3d968589d8 | 140 | * @} |
| Kojto | 90:cb3d968589d8 | 141 | */ |
| Kojto | 90:cb3d968589d8 | 142 | |
| Kojto | 90:cb3d968589d8 | 143 | /* Exported macro ------------------------------------------------------------*/ |
| Kojto | 90:cb3d968589d8 | 144 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
| Kojto | 90:cb3d968589d8 | 145 | * @{ |
| Kojto | 90:cb3d968589d8 | 146 | */ |
| Kojto | 90:cb3d968589d8 | 147 | |
| Kojto | 90:cb3d968589d8 | 148 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
| Kojto | 90:cb3d968589d8 | 149 | * @brief Enables or disables the AHB1 peripheral clock. |
| Kojto | 90:cb3d968589d8 | 150 | * @note After reset, the peripheral clock (used for registers read/write access) |
| Kojto | 90:cb3d968589d8 | 151 | * is disabled and the application software has to enable this clock before |
| Kojto | 90:cb3d968589d8 | 152 | * using it. |
| Kojto | 90:cb3d968589d8 | 153 | * @{ |
| Kojto | 90:cb3d968589d8 | 154 | */ |
| Kojto | 90:cb3d968589d8 | 155 | #if defined (STM32L151xB) || defined (STM32L152xB) || \ |
| Kojto | 90:cb3d968589d8 | 156 | defined (STM32L151xBA) || defined (STM32L152xBA) || \ |
| Kojto | 90:cb3d968589d8 | 157 | defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 158 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 159 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 160 | |
| Kojto | 90:cb3d968589d8 | 161 | #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) |
| Kojto | 90:cb3d968589d8 | 162 | #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
| Kojto | 90:cb3d968589d8 | 163 | |
| Kojto | 90:cb3d968589d8 | 164 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 165 | |
| Kojto | 90:cb3d968589d8 | 166 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 167 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 168 | |
| Kojto | 90:cb3d968589d8 | 169 | #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) |
| Kojto | 90:cb3d968589d8 | 170 | #define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN)) |
| Kojto | 90:cb3d968589d8 | 171 | |
| Kojto | 90:cb3d968589d8 | 172 | #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
| Kojto | 90:cb3d968589d8 | 173 | #define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) |
| Kojto | 90:cb3d968589d8 | 174 | |
| Kojto | 90:cb3d968589d8 | 175 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 176 | |
| Kojto | 90:cb3d968589d8 | 177 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 178 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 179 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 180 | |
| Kojto | 90:cb3d968589d8 | 181 | #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN)) |
| Kojto | 90:cb3d968589d8 | 182 | #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
| Kojto | 90:cb3d968589d8 | 183 | |
| Kojto | 90:cb3d968589d8 | 184 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 185 | |
| Kojto | 90:cb3d968589d8 | 186 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 187 | |
| Kojto | 90:cb3d968589d8 | 188 | #define __CRYP_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_AESEN)) |
| Kojto | 90:cb3d968589d8 | 189 | #define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) |
| Kojto | 90:cb3d968589d8 | 190 | |
| Kojto | 90:cb3d968589d8 | 191 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 192 | |
| Kojto | 90:cb3d968589d8 | 193 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| Kojto | 90:cb3d968589d8 | 194 | |
| Kojto | 90:cb3d968589d8 | 195 | #define __FSMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FSMCEN)) |
| Kojto | 90:cb3d968589d8 | 196 | #define __FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) |
| Kojto | 90:cb3d968589d8 | 197 | |
| Kojto | 90:cb3d968589d8 | 198 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| Kojto | 90:cb3d968589d8 | 199 | |
| Kojto | 90:cb3d968589d8 | 200 | #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ |
| Kojto | 90:cb3d968589d8 | 201 | defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ |
| Kojto | 90:cb3d968589d8 | 202 | defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ |
| Kojto | 90:cb3d968589d8 | 203 | defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ |
| Kojto | 90:cb3d968589d8 | 204 | defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 205 | |
| Kojto | 90:cb3d968589d8 | 206 | #define __LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN)) |
| Kojto | 90:cb3d968589d8 | 207 | #define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) |
| Kojto | 90:cb3d968589d8 | 208 | |
| Kojto | 90:cb3d968589d8 | 209 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 210 | |
| Kojto | 90:cb3d968589d8 | 211 | /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. |
| Kojto | 90:cb3d968589d8 | 212 | * @note After reset, the peripheral clock (used for registers read/write access) |
| Kojto | 90:cb3d968589d8 | 213 | * is disabled and the application software has to enable this clock before |
| Kojto | 90:cb3d968589d8 | 214 | * using it. |
| Kojto | 90:cb3d968589d8 | 215 | */ |
| Kojto | 90:cb3d968589d8 | 216 | #if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 217 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 218 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 219 | |
| Kojto | 90:cb3d968589d8 | 220 | #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN)) |
| Kojto | 90:cb3d968589d8 | 221 | #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
| Kojto | 90:cb3d968589d8 | 222 | |
| Kojto | 90:cb3d968589d8 | 223 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 224 | |
| Kojto | 90:cb3d968589d8 | 225 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 226 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 227 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 228 | |
| Kojto | 90:cb3d968589d8 | 229 | #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN)) |
| Kojto | 90:cb3d968589d8 | 230 | #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
| Kojto | 90:cb3d968589d8 | 231 | |
| Kojto | 90:cb3d968589d8 | 232 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 233 | |
| Kojto | 90:cb3d968589d8 | 234 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 235 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 236 | |
| Kojto | 90:cb3d968589d8 | 237 | #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN)) |
| Kojto | 90:cb3d968589d8 | 238 | #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN)) |
| Kojto | 90:cb3d968589d8 | 239 | |
| Kojto | 90:cb3d968589d8 | 240 | #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
| Kojto | 90:cb3d968589d8 | 241 | #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
| Kojto | 90:cb3d968589d8 | 242 | |
| Kojto | 90:cb3d968589d8 | 243 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 244 | |
| Kojto | 90:cb3d968589d8 | 245 | #if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) |
| Kojto | 90:cb3d968589d8 | 246 | |
| Kojto | 90:cb3d968589d8 | 247 | #define __OPAMP_CLK_ENABLE() __COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
| Kojto | 90:cb3d968589d8 | 248 | #define __OPAMP_CLK_DISABLE() __COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
| Kojto | 90:cb3d968589d8 | 249 | |
| Kojto | 90:cb3d968589d8 | 250 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
| Kojto | 90:cb3d968589d8 | 251 | |
| Kojto | 90:cb3d968589d8 | 252 | /** @brief Enables or disables the High Speed APB (APB2) peripheral clock. |
| Kojto | 90:cb3d968589d8 | 253 | * @note After reset, the peripheral clock (used for registers read/write access) |
| Kojto | 90:cb3d968589d8 | 254 | * is disabled and the application software has to enable this clock before |
| Kojto | 90:cb3d968589d8 | 255 | * using it. |
| Kojto | 90:cb3d968589d8 | 256 | */ |
| Kojto | 90:cb3d968589d8 | 257 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| Kojto | 90:cb3d968589d8 | 258 | |
| Kojto | 90:cb3d968589d8 | 259 | #define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN)) |
| Kojto | 90:cb3d968589d8 | 260 | #define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) |
| Kojto | 90:cb3d968589d8 | 261 | |
| Kojto | 90:cb3d968589d8 | 262 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| Kojto | 90:cb3d968589d8 | 263 | |
| Kojto | 90:cb3d968589d8 | 264 | /** |
| Kojto | 90:cb3d968589d8 | 265 | * @} |
| Kojto | 90:cb3d968589d8 | 266 | */ |
| Kojto | 90:cb3d968589d8 | 267 | |
| Kojto | 90:cb3d968589d8 | 268 | |
| Kojto | 90:cb3d968589d8 | 269 | /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
| Kojto | 90:cb3d968589d8 | 270 | * @brief Forces or releases AHB peripheral reset. |
| Kojto | 90:cb3d968589d8 | 271 | * @{ |
| Kojto | 90:cb3d968589d8 | 272 | */ |
| Kojto | 90:cb3d968589d8 | 273 | #if defined (STM32L151xB) || defined (STM32L152xB) || \ |
| Kojto | 90:cb3d968589d8 | 274 | defined (STM32L151xBA) || defined (STM32L152xBA) || \ |
| Kojto | 90:cb3d968589d8 | 275 | defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 276 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 277 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 278 | |
| Kojto | 90:cb3d968589d8 | 279 | #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
| Kojto | 90:cb3d968589d8 | 280 | #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
| Kojto | 90:cb3d968589d8 | 281 | |
| Kojto | 90:cb3d968589d8 | 282 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 283 | |
| Kojto | 90:cb3d968589d8 | 284 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 285 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 286 | |
| Kojto | 90:cb3d968589d8 | 287 | #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) |
| Kojto | 90:cb3d968589d8 | 288 | #define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) |
| Kojto | 90:cb3d968589d8 | 289 | |
| Kojto | 90:cb3d968589d8 | 290 | #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) |
| Kojto | 90:cb3d968589d8 | 291 | #define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) |
| Kojto | 90:cb3d968589d8 | 292 | |
| Kojto | 90:cb3d968589d8 | 293 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 294 | |
| Kojto | 90:cb3d968589d8 | 295 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 296 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 297 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 298 | |
| Kojto | 90:cb3d968589d8 | 299 | #define __DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) |
| Kojto | 90:cb3d968589d8 | 300 | #define __DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) |
| Kojto | 90:cb3d968589d8 | 301 | |
| Kojto | 90:cb3d968589d8 | 302 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 303 | |
| Kojto | 90:cb3d968589d8 | 304 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 305 | |
| Kojto | 90:cb3d968589d8 | 306 | #define __CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) |
| Kojto | 90:cb3d968589d8 | 307 | #define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) |
| Kojto | 90:cb3d968589d8 | 308 | |
| Kojto | 90:cb3d968589d8 | 309 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 310 | |
| Kojto | 90:cb3d968589d8 | 311 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| Kojto | 90:cb3d968589d8 | 312 | |
| Kojto | 90:cb3d968589d8 | 313 | #define __FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) |
| Kojto | 90:cb3d968589d8 | 314 | #define __FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) |
| Kojto | 90:cb3d968589d8 | 315 | |
| Kojto | 90:cb3d968589d8 | 316 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| Kojto | 90:cb3d968589d8 | 317 | |
| Kojto | 90:cb3d968589d8 | 318 | #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ |
| Kojto | 90:cb3d968589d8 | 319 | defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ |
| Kojto | 90:cb3d968589d8 | 320 | defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ |
| Kojto | 90:cb3d968589d8 | 321 | defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ |
| Kojto | 90:cb3d968589d8 | 322 | defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 323 | |
| Kojto | 90:cb3d968589d8 | 324 | #define __LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) |
| Kojto | 90:cb3d968589d8 | 325 | #define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) |
| Kojto | 90:cb3d968589d8 | 326 | |
| Kojto | 90:cb3d968589d8 | 327 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 328 | |
| Kojto | 90:cb3d968589d8 | 329 | /** @brief Forces or releases APB1 peripheral reset. |
| Kojto | 90:cb3d968589d8 | 330 | */ |
| Kojto | 90:cb3d968589d8 | 331 | #if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 332 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 333 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 334 | |
| Kojto | 90:cb3d968589d8 | 335 | #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
| Kojto | 90:cb3d968589d8 | 336 | #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
| Kojto | 90:cb3d968589d8 | 337 | |
| Kojto | 90:cb3d968589d8 | 338 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 339 | |
| Kojto | 90:cb3d968589d8 | 340 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 341 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 342 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 343 | |
| Kojto | 90:cb3d968589d8 | 344 | #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
| Kojto | 90:cb3d968589d8 | 345 | #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
| Kojto | 90:cb3d968589d8 | 346 | |
| Kojto | 90:cb3d968589d8 | 347 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 348 | |
| Kojto | 90:cb3d968589d8 | 349 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 350 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 351 | |
| Kojto | 90:cb3d968589d8 | 352 | #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
| Kojto | 90:cb3d968589d8 | 353 | #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
| Kojto | 90:cb3d968589d8 | 354 | |
| Kojto | 90:cb3d968589d8 | 355 | #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
| Kojto | 90:cb3d968589d8 | 356 | #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
| Kojto | 90:cb3d968589d8 | 357 | |
| Kojto | 90:cb3d968589d8 | 358 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 359 | |
| Kojto | 90:cb3d968589d8 | 360 | #if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) |
| Kojto | 90:cb3d968589d8 | 361 | |
| Kojto | 90:cb3d968589d8 | 362 | #define __OPAMP_FORCE_RESET() __COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ |
| Kojto | 90:cb3d968589d8 | 363 | #define __OPAMP_RELEASE_RESET() __COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ |
| Kojto | 90:cb3d968589d8 | 364 | |
| Kojto | 90:cb3d968589d8 | 365 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
| Kojto | 90:cb3d968589d8 | 366 | |
| Kojto | 90:cb3d968589d8 | 367 | /** @brief Forces or releases APB2 peripheral reset. |
| Kojto | 90:cb3d968589d8 | 368 | */ |
| Kojto | 90:cb3d968589d8 | 369 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| Kojto | 90:cb3d968589d8 | 370 | |
| Kojto | 90:cb3d968589d8 | 371 | #define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) |
| Kojto | 90:cb3d968589d8 | 372 | #define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) |
| Kojto | 90:cb3d968589d8 | 373 | |
| Kojto | 90:cb3d968589d8 | 374 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| Kojto | 90:cb3d968589d8 | 375 | |
| Kojto | 90:cb3d968589d8 | 376 | /** |
| Kojto | 90:cb3d968589d8 | 377 | * @} |
| Kojto | 90:cb3d968589d8 | 378 | */ |
| Kojto | 90:cb3d968589d8 | 379 | |
| Kojto | 90:cb3d968589d8 | 380 | /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable |
| Kojto | 90:cb3d968589d8 | 381 | * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. |
| Kojto | 90:cb3d968589d8 | 382 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| Kojto | 90:cb3d968589d8 | 383 | * power consumption. |
| Kojto | 90:cb3d968589d8 | 384 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| Kojto | 90:cb3d968589d8 | 385 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| Kojto | 90:cb3d968589d8 | 386 | * @{ |
| Kojto | 90:cb3d968589d8 | 387 | */ |
| Kojto | 90:cb3d968589d8 | 388 | #if defined (STM32L151xB) || defined (STM32L152xB) || \ |
| Kojto | 90:cb3d968589d8 | 389 | defined (STM32L151xBA) || defined (STM32L152xBA) || \ |
| Kojto | 90:cb3d968589d8 | 390 | defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 391 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 392 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 393 | |
| Kojto | 90:cb3d968589d8 | 394 | #define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) |
| Kojto | 90:cb3d968589d8 | 395 | #define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) |
| Kojto | 90:cb3d968589d8 | 396 | |
| Kojto | 90:cb3d968589d8 | 397 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 398 | |
| Kojto | 90:cb3d968589d8 | 399 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 400 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 401 | |
| Kojto | 90:cb3d968589d8 | 402 | #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) |
| Kojto | 90:cb3d968589d8 | 403 | #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) |
| Kojto | 90:cb3d968589d8 | 404 | |
| Kojto | 90:cb3d968589d8 | 405 | #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) |
| Kojto | 90:cb3d968589d8 | 406 | #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) |
| Kojto | 90:cb3d968589d8 | 407 | |
| Kojto | 90:cb3d968589d8 | 408 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 409 | |
| Kojto | 90:cb3d968589d8 | 410 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 411 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 412 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 413 | |
| Kojto | 90:cb3d968589d8 | 414 | #define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) |
| Kojto | 90:cb3d968589d8 | 415 | #define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) |
| Kojto | 90:cb3d968589d8 | 416 | |
| Kojto | 90:cb3d968589d8 | 417 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 418 | |
| Kojto | 90:cb3d968589d8 | 419 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 420 | |
| Kojto | 90:cb3d968589d8 | 421 | #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) |
| Kojto | 90:cb3d968589d8 | 422 | #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) |
| Kojto | 90:cb3d968589d8 | 423 | |
| Kojto | 90:cb3d968589d8 | 424 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 425 | |
| Kojto | 90:cb3d968589d8 | 426 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| Kojto | 90:cb3d968589d8 | 427 | |
| Kojto | 90:cb3d968589d8 | 428 | #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) |
| Kojto | 90:cb3d968589d8 | 429 | #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) |
| Kojto | 90:cb3d968589d8 | 430 | |
| Kojto | 90:cb3d968589d8 | 431 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| Kojto | 90:cb3d968589d8 | 432 | |
| Kojto | 90:cb3d968589d8 | 433 | #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ |
| Kojto | 90:cb3d968589d8 | 434 | defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ |
| Kojto | 90:cb3d968589d8 | 435 | defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ |
| Kojto | 90:cb3d968589d8 | 436 | defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ |
| Kojto | 90:cb3d968589d8 | 437 | defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 438 | |
| Kojto | 90:cb3d968589d8 | 439 | #define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) |
| Kojto | 90:cb3d968589d8 | 440 | #define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) |
| Kojto | 90:cb3d968589d8 | 441 | |
| Kojto | 90:cb3d968589d8 | 442 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 443 | |
| Kojto | 90:cb3d968589d8 | 444 | /** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. |
| Kojto | 90:cb3d968589d8 | 445 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| Kojto | 90:cb3d968589d8 | 446 | * power consumption. |
| Kojto | 90:cb3d968589d8 | 447 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| Kojto | 90:cb3d968589d8 | 448 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| Kojto | 90:cb3d968589d8 | 449 | */ |
| Kojto | 90:cb3d968589d8 | 450 | #if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 451 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 452 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 453 | |
| Kojto | 90:cb3d968589d8 | 454 | #define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) |
| Kojto | 90:cb3d968589d8 | 455 | #define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) |
| Kojto | 90:cb3d968589d8 | 456 | |
| Kojto | 90:cb3d968589d8 | 457 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 458 | |
| Kojto | 90:cb3d968589d8 | 459 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 460 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 461 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 462 | |
| Kojto | 90:cb3d968589d8 | 463 | #define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) |
| Kojto | 90:cb3d968589d8 | 464 | #define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) |
| Kojto | 90:cb3d968589d8 | 465 | |
| Kojto | 90:cb3d968589d8 | 466 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 467 | |
| Kojto | 90:cb3d968589d8 | 468 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 469 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 470 | |
| Kojto | 90:cb3d968589d8 | 471 | #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
| Kojto | 90:cb3d968589d8 | 472 | #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
| Kojto | 90:cb3d968589d8 | 473 | |
| Kojto | 90:cb3d968589d8 | 474 | #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
| Kojto | 90:cb3d968589d8 | 475 | #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
| Kojto | 90:cb3d968589d8 | 476 | |
| Kojto | 90:cb3d968589d8 | 477 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 478 | |
| Kojto | 90:cb3d968589d8 | 479 | /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. |
| Kojto | 90:cb3d968589d8 | 480 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| Kojto | 90:cb3d968589d8 | 481 | * power consumption. |
| Kojto | 90:cb3d968589d8 | 482 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| Kojto | 90:cb3d968589d8 | 483 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| Kojto | 90:cb3d968589d8 | 484 | */ |
| Kojto | 90:cb3d968589d8 | 485 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| Kojto | 90:cb3d968589d8 | 486 | |
| Kojto | 90:cb3d968589d8 | 487 | #define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) |
| Kojto | 90:cb3d968589d8 | 488 | #define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) |
| Kojto | 90:cb3d968589d8 | 489 | |
| Kojto | 90:cb3d968589d8 | 490 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| Kojto | 90:cb3d968589d8 | 491 | |
| Kojto | 90:cb3d968589d8 | 492 | /** |
| Kojto | 90:cb3d968589d8 | 493 | * @} |
| Kojto | 90:cb3d968589d8 | 494 | */ |
| Kojto | 90:cb3d968589d8 | 495 | |
| Kojto | 90:cb3d968589d8 | 496 | #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ |
| Kojto | 90:cb3d968589d8 | 497 | defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ |
| Kojto | 90:cb3d968589d8 | 498 | defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ |
| Kojto | 90:cb3d968589d8 | 499 | defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ |
| Kojto | 90:cb3d968589d8 | 500 | defined(STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 501 | |
| Kojto | 90:cb3d968589d8 | 502 | |
| Kojto | 90:cb3d968589d8 | 503 | /** @brief Macro to configures LCD clock (LCDCLK). |
| Kojto | 90:cb3d968589d8 | 504 | * @note LCD and RTC use the same configuration |
| Kojto | 90:cb3d968589d8 | 505 | * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the |
| Kojto | 90:cb3d968589d8 | 506 | * LCD clock source. |
| Kojto | 90:cb3d968589d8 | 507 | * |
| Kojto | 90:cb3d968589d8 | 508 | * @param __LCD_CLKSOURCE__: specifies the LCD clock source. |
| Kojto | 90:cb3d968589d8 | 509 | * This parameter can be one of the following values: |
| Kojto | 90:cb3d968589d8 | 510 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
| Kojto | 90:cb3d968589d8 | 511 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
| Kojto | 90:cb3d968589d8 | 512 | * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock |
| Kojto | 90:cb3d968589d8 | 513 | * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock |
| Kojto | 90:cb3d968589d8 | 514 | * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock |
| Kojto | 90:cb3d968589d8 | 515 | * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock |
| Kojto | 90:cb3d968589d8 | 516 | */ |
| Kojto | 90:cb3d968589d8 | 517 | #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) |
| Kojto | 90:cb3d968589d8 | 518 | |
| Kojto | 90:cb3d968589d8 | 519 | /** @brief macros to get the LCD clock source. |
| Kojto | 90:cb3d968589d8 | 520 | */ |
| Kojto | 90:cb3d968589d8 | 521 | #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() |
| Kojto | 90:cb3d968589d8 | 522 | |
| Kojto | 90:cb3d968589d8 | 523 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ |
| Kojto | 90:cb3d968589d8 | 524 | |
| Kojto | 90:cb3d968589d8 | 525 | /** |
| Kojto | 90:cb3d968589d8 | 526 | * @} |
| Kojto | 90:cb3d968589d8 | 527 | */ |
| Kojto | 90:cb3d968589d8 | 528 | |
| Kojto | 90:cb3d968589d8 | 529 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 90:cb3d968589d8 | 530 | /** @addtogroup RCCEx_Private_Functions |
| Kojto | 90:cb3d968589d8 | 531 | * @{ |
| Kojto | 90:cb3d968589d8 | 532 | */ |
| Kojto | 90:cb3d968589d8 | 533 | |
| Kojto | 90:cb3d968589d8 | 534 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
| Kojto | 90:cb3d968589d8 | 535 | * @{ |
| Kojto | 90:cb3d968589d8 | 536 | */ |
| Kojto | 90:cb3d968589d8 | 537 | |
| Kojto | 90:cb3d968589d8 | 538 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
| Kojto | 90:cb3d968589d8 | 539 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
| Kojto | 90:cb3d968589d8 | 540 | |
| Kojto | 90:cb3d968589d8 | 541 | #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ |
| Kojto | 90:cb3d968589d8 | 542 | defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ |
| Kojto | 90:cb3d968589d8 | 543 | defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ |
| Kojto | 90:cb3d968589d8 | 544 | defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) |
| Kojto | 90:cb3d968589d8 | 545 | |
| Kojto | 90:cb3d968589d8 | 546 | void HAL_RCCEx_EnableLSECSS(void); |
| Kojto | 90:cb3d968589d8 | 547 | void HAL_RCCEx_DisableLSECSS(void); |
| Kojto | 90:cb3d968589d8 | 548 | |
| Kojto | 90:cb3d968589d8 | 549 | #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ |
| Kojto | 90:cb3d968589d8 | 550 | |
| Kojto | 90:cb3d968589d8 | 551 | /** |
| Kojto | 90:cb3d968589d8 | 552 | * @} |
| Kojto | 90:cb3d968589d8 | 553 | */ |
| Kojto | 90:cb3d968589d8 | 554 | |
| Kojto | 90:cb3d968589d8 | 555 | /** |
| Kojto | 90:cb3d968589d8 | 556 | * @} |
| Kojto | 90:cb3d968589d8 | 557 | */ |
| Kojto | 90:cb3d968589d8 | 558 | |
| Kojto | 90:cb3d968589d8 | 559 | /** |
| Kojto | 90:cb3d968589d8 | 560 | * @} |
| Kojto | 90:cb3d968589d8 | 561 | */ |
| Kojto | 90:cb3d968589d8 | 562 | |
| Kojto | 90:cb3d968589d8 | 563 | /** |
| Kojto | 90:cb3d968589d8 | 564 | * @} |
| Kojto | 90:cb3d968589d8 | 565 | */ |
| Kojto | 90:cb3d968589d8 | 566 | |
| Kojto | 90:cb3d968589d8 | 567 | #ifdef __cplusplus |
| Kojto | 90:cb3d968589d8 | 568 | } |
| Kojto | 90:cb3d968589d8 | 569 | #endif |
| Kojto | 90:cb3d968589d8 | 570 | |
| Kojto | 90:cb3d968589d8 | 571 | #endif /* __STM32L1xx_HAL_RCC_EX_H */ |
| Kojto | 90:cb3d968589d8 | 572 | |
| Kojto | 90:cb3d968589d8 | 573 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |