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TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:: fblanc
Date:: Fri Dec 05 15:42:32 2014 +0000
Revision:: 93:9dd889aeda0e
Parent:: 86:04dd9b1680ae

substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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User	Revision	Line number	New contents of line
bogdanm	86:04dd9b1680ae	1	/**
bogdanm	86:04dd9b1680ae	2	******************************************************************************
bogdanm	86:04dd9b1680ae	3	* @file stm32f4xx_hal_rcc.h
bogdanm	86:04dd9b1680ae	4	* @author MCD Application Team
bogdanm	86:04dd9b1680ae	5	* @version V1.1.0
bogdanm	86:04dd9b1680ae	6	* @date 19-June-2014
bogdanm	86:04dd9b1680ae	7	* @brief Header file of RCC HAL module.
bogdanm	86:04dd9b1680ae	8	******************************************************************************
bogdanm	86:04dd9b1680ae	9	* @attention
bogdanm	86:04dd9b1680ae	10	*
bogdanm	86:04dd9b1680ae	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	86:04dd9b1680ae	12	*
bogdanm	86:04dd9b1680ae	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	86:04dd9b1680ae	14	* are permitted provided that the following conditions are met:
bogdanm	86:04dd9b1680ae	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	86:04dd9b1680ae	16	* this list of conditions and the following disclaimer.
bogdanm	86:04dd9b1680ae	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	86:04dd9b1680ae	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	86:04dd9b1680ae	19	* and/or other materials provided with the distribution.
bogdanm	86:04dd9b1680ae	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	86:04dd9b1680ae	21	* may be used to endorse or promote products derived from this software
bogdanm	86:04dd9b1680ae	22	* without specific prior written permission.
bogdanm	86:04dd9b1680ae	23	*
bogdanm	86:04dd9b1680ae	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	86:04dd9b1680ae	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	86:04dd9b1680ae	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	86:04dd9b1680ae	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	86:04dd9b1680ae	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	86:04dd9b1680ae	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	86:04dd9b1680ae	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	86:04dd9b1680ae	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	86:04dd9b1680ae	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	86:04dd9b1680ae	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	86:04dd9b1680ae	34	*
bogdanm	86:04dd9b1680ae	35	******************************************************************************
bogdanm	86:04dd9b1680ae	36	*/
bogdanm	86:04dd9b1680ae	37
bogdanm	86:04dd9b1680ae	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	86:04dd9b1680ae	39	#ifndef __STM32F4xx_HAL_RCC_H
bogdanm	86:04dd9b1680ae	40	#define __STM32F4xx_HAL_RCC_H
bogdanm	86:04dd9b1680ae	41
bogdanm	86:04dd9b1680ae	42	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	43	extern "C" {
bogdanm	86:04dd9b1680ae	44	#endif
bogdanm	86:04dd9b1680ae	45
bogdanm	86:04dd9b1680ae	46	/* Includes ------------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	47	#include "stm32f4xx_hal_def.h"
bogdanm	86:04dd9b1680ae	48
bogdanm	86:04dd9b1680ae	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	86:04dd9b1680ae	50	* @{
bogdanm	86:04dd9b1680ae	51	*/
bogdanm	86:04dd9b1680ae	52
bogdanm	86:04dd9b1680ae	53	/** @addtogroup RCC
bogdanm	86:04dd9b1680ae	54	* @{
bogdanm	86:04dd9b1680ae	55	*/
bogdanm	86:04dd9b1680ae	56
bogdanm	86:04dd9b1680ae	57	/* Exported types ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	58
bogdanm	86:04dd9b1680ae	59	/**
bogdanm	86:04dd9b1680ae	60	* @brief RCC PLL configuration structure definition
bogdanm	86:04dd9b1680ae	61	*/
bogdanm	86:04dd9b1680ae	62	typedef struct
bogdanm	86:04dd9b1680ae	63	{
bogdanm	86:04dd9b1680ae	64	uint32_t PLLState; /*!< The new state of the PLL.
bogdanm	86:04dd9b1680ae	65	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	86:04dd9b1680ae	66
bogdanm	86:04dd9b1680ae	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm	86:04dd9b1680ae	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	86:04dd9b1680ae	69
bogdanm	86:04dd9b1680ae	70	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
bogdanm	86:04dd9b1680ae	71	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
bogdanm	86:04dd9b1680ae	72
bogdanm	86:04dd9b1680ae	73	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
bogdanm	86:04dd9b1680ae	74	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
bogdanm	86:04dd9b1680ae	75
bogdanm	86:04dd9b1680ae	76	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
bogdanm	86:04dd9b1680ae	77	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
bogdanm	86:04dd9b1680ae	78
bogdanm	86:04dd9b1680ae	79	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
bogdanm	86:04dd9b1680ae	80	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
bogdanm	86:04dd9b1680ae	81
bogdanm	86:04dd9b1680ae	82	}RCC_PLLInitTypeDef;
bogdanm	86:04dd9b1680ae	83
bogdanm	86:04dd9b1680ae	84	/**
bogdanm	86:04dd9b1680ae	85	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	86:04dd9b1680ae	86	*/
bogdanm	86:04dd9b1680ae	87	typedef struct
bogdanm	86:04dd9b1680ae	88	{
bogdanm	86:04dd9b1680ae	89	uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm	86:04dd9b1680ae	90	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	86:04dd9b1680ae	91
bogdanm	86:04dd9b1680ae	92	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	86:04dd9b1680ae	93	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	86:04dd9b1680ae	94
bogdanm	86:04dd9b1680ae	95	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	86:04dd9b1680ae	96	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	86:04dd9b1680ae	97
bogdanm	86:04dd9b1680ae	98	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	86:04dd9b1680ae	99	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	86:04dd9b1680ae	100
bogdanm	86:04dd9b1680ae	101	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm	86:04dd9b1680ae	102	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	86:04dd9b1680ae	103
bogdanm	86:04dd9b1680ae	104	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	86:04dd9b1680ae	105	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	86:04dd9b1680ae	106
bogdanm	86:04dd9b1680ae	107	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	86:04dd9b1680ae	108
bogdanm	86:04dd9b1680ae	109	}RCC_OscInitTypeDef;
bogdanm	86:04dd9b1680ae	110
bogdanm	86:04dd9b1680ae	111	/**
bogdanm	86:04dd9b1680ae	112	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	86:04dd9b1680ae	113	*/
bogdanm	86:04dd9b1680ae	114	typedef struct
bogdanm	86:04dd9b1680ae	115	{
bogdanm	86:04dd9b1680ae	116	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	86:04dd9b1680ae	117	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	86:04dd9b1680ae	118
bogdanm	86:04dd9b1680ae	119	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	86:04dd9b1680ae	120	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	86:04dd9b1680ae	121
bogdanm	86:04dd9b1680ae	122	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	86:04dd9b1680ae	123	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	86:04dd9b1680ae	124
bogdanm	86:04dd9b1680ae	125	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	86:04dd9b1680ae	126	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	86:04dd9b1680ae	127
bogdanm	86:04dd9b1680ae	128	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	86:04dd9b1680ae	129	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	86:04dd9b1680ae	130
bogdanm	86:04dd9b1680ae	131	}RCC_ClkInitTypeDef;
bogdanm	86:04dd9b1680ae	132
bogdanm	86:04dd9b1680ae	133	/* Exported constants --------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	134	/** @defgroup RCC_Exported_Constants
bogdanm	86:04dd9b1680ae	135	* @{
bogdanm	86:04dd9b1680ae	136	*/
bogdanm	86:04dd9b1680ae	137
bogdanm	86:04dd9b1680ae	138	/** @defgroup RCC_BitAddress_AliasRegion
bogdanm	86:04dd9b1680ae	139	* @brief RCC registers bit address in the alias region
bogdanm	86:04dd9b1680ae	140	* @{
bogdanm	86:04dd9b1680ae	141	*/
bogdanm	86:04dd9b1680ae	142	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	86:04dd9b1680ae	143	/* --- CR Register ---*/
bogdanm	86:04dd9b1680ae	144	/* Alias word address of HSION bit */
bogdanm	86:04dd9b1680ae	145	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm	86:04dd9b1680ae	146	#define HSION_BitNumber 0x00
bogdanm	86:04dd9b1680ae	147	#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
bogdanm	86:04dd9b1680ae	148	/* Alias word address of CSSON bit */
bogdanm	86:04dd9b1680ae	149	#define CSSON_BitNumber 0x13
bogdanm	86:04dd9b1680ae	150	#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
bogdanm	86:04dd9b1680ae	151	/* Alias word address of PLLON bit */
bogdanm	86:04dd9b1680ae	152	#define PLLON_BitNumber 0x18
bogdanm	86:04dd9b1680ae	153	#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
bogdanm	86:04dd9b1680ae	154	/* Alias word address of PLLI2SON bit */
bogdanm	86:04dd9b1680ae	155	#define PLLI2SON_BitNumber 0x1A
bogdanm	86:04dd9b1680ae	156	#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
bogdanm	86:04dd9b1680ae	157
bogdanm	86:04dd9b1680ae	158	/* --- CFGR Register ---*/
bogdanm	86:04dd9b1680ae	159	/* Alias word address of I2SSRC bit */
bogdanm	86:04dd9b1680ae	160	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
bogdanm	86:04dd9b1680ae	161	#define I2SSRC_BitNumber 0x17
bogdanm	86:04dd9b1680ae	162	#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
bogdanm	86:04dd9b1680ae	163
bogdanm	86:04dd9b1680ae	164	/* --- BDCR Register ---*/
bogdanm	86:04dd9b1680ae	165	/* Alias word address of RTCEN bit */
bogdanm	86:04dd9b1680ae	166	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
bogdanm	86:04dd9b1680ae	167	#define RTCEN_BitNumber 0x0F
bogdanm	86:04dd9b1680ae	168	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
bogdanm	86:04dd9b1680ae	169	/* Alias word address of BDRST bit */
bogdanm	86:04dd9b1680ae	170	#define BDRST_BitNumber 0x10
bogdanm	86:04dd9b1680ae	171	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
bogdanm	86:04dd9b1680ae	172
bogdanm	86:04dd9b1680ae	173	/* --- CSR Register ---*/
bogdanm	86:04dd9b1680ae	174	/* Alias word address of LSION bit */
bogdanm	86:04dd9b1680ae	175	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
bogdanm	86:04dd9b1680ae	176	#define LSION_BitNumber 0x00
bogdanm	86:04dd9b1680ae	177	#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
bogdanm	86:04dd9b1680ae	178
bogdanm	86:04dd9b1680ae	179	/* CR register byte 3 (Bits[23:16]) base address */
bogdanm	86:04dd9b1680ae	180	#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
bogdanm	86:04dd9b1680ae	181
bogdanm	86:04dd9b1680ae	182	/* CIR register byte 2 (Bits[15:8]) base address */
bogdanm	86:04dd9b1680ae	183	#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
bogdanm	86:04dd9b1680ae	184
bogdanm	86:04dd9b1680ae	185	/* CIR register byte 3 (Bits[23:16]) base address */
bogdanm	86:04dd9b1680ae	186	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
bogdanm	86:04dd9b1680ae	187
bogdanm	86:04dd9b1680ae	188	/* BDCR register base address */
bogdanm	86:04dd9b1680ae	189	#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm	86:04dd9b1680ae	190
bogdanm	86:04dd9b1680ae	191
bogdanm	86:04dd9b1680ae	192	#define DBP_TIMEOUT_VALUE ((uint32_t)100)
bogdanm	86:04dd9b1680ae	193	#define LSE_TIMEOUT_VALUE ((uint32_t)600)
bogdanm	86:04dd9b1680ae	194	/**
bogdanm	86:04dd9b1680ae	195	* @}
bogdanm	86:04dd9b1680ae	196	*/
bogdanm	86:04dd9b1680ae	197
bogdanm	86:04dd9b1680ae	198	/** @defgroup RCC_Oscillator_Type
bogdanm	86:04dd9b1680ae	199	* @{
bogdanm	86:04dd9b1680ae	200	*/
bogdanm	86:04dd9b1680ae	201	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	202	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	203	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	204	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	205	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	206
bogdanm	86:04dd9b1680ae	207	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
bogdanm	86:04dd9b1680ae	208	/**
bogdanm	86:04dd9b1680ae	209	* @}
bogdanm	86:04dd9b1680ae	210	*/
bogdanm	86:04dd9b1680ae	211
bogdanm	86:04dd9b1680ae	212	/** @defgroup RCC_HSE_Config
bogdanm	86:04dd9b1680ae	213	* @{
bogdanm	86:04dd9b1680ae	214	*/
bogdanm	86:04dd9b1680ae	215	#define RCC_HSE_OFF ((uint8_t)0x00)
bogdanm	86:04dd9b1680ae	216	#define RCC_HSE_ON ((uint8_t)0x01)
bogdanm	86:04dd9b1680ae	217	#define RCC_HSE_BYPASS ((uint8_t)0x05)
bogdanm	86:04dd9b1680ae	218
bogdanm	86:04dd9b1680ae	219	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
bogdanm	86:04dd9b1680ae	220	((HSE) == RCC_HSE_BYPASS))
bogdanm	86:04dd9b1680ae	221	/**
bogdanm	86:04dd9b1680ae	222	* @}
bogdanm	86:04dd9b1680ae	223	*/
bogdanm	86:04dd9b1680ae	224
bogdanm	86:04dd9b1680ae	225	/** @defgroup RCC_LSE_Config
bogdanm	86:04dd9b1680ae	226	* @{
bogdanm	86:04dd9b1680ae	227	*/
bogdanm	86:04dd9b1680ae	228	#define RCC_LSE_OFF ((uint8_t)0x00)
bogdanm	86:04dd9b1680ae	229	#define RCC_LSE_ON ((uint8_t)0x01)
bogdanm	86:04dd9b1680ae	230	#define RCC_LSE_BYPASS ((uint8_t)0x05)
bogdanm	86:04dd9b1680ae	231
bogdanm	86:04dd9b1680ae	232	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
bogdanm	86:04dd9b1680ae	233	((LSE) == RCC_LSE_BYPASS))
bogdanm	86:04dd9b1680ae	234	/**
bogdanm	86:04dd9b1680ae	235	* @}
bogdanm	86:04dd9b1680ae	236	*/
bogdanm	86:04dd9b1680ae	237
bogdanm	86:04dd9b1680ae	238	/** @defgroup RCC_HSI_Config
bogdanm	86:04dd9b1680ae	239	* @{
bogdanm	86:04dd9b1680ae	240	*/
bogdanm	86:04dd9b1680ae	241	#define RCC_HSI_OFF ((uint8_t)0x00)
bogdanm	86:04dd9b1680ae	242	#define RCC_HSI_ON ((uint8_t)0x01)
bogdanm	86:04dd9b1680ae	243
bogdanm	86:04dd9b1680ae	244	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
bogdanm	86:04dd9b1680ae	245	/**
bogdanm	86:04dd9b1680ae	246	* @}
bogdanm	86:04dd9b1680ae	247	*/
bogdanm	86:04dd9b1680ae	248
bogdanm	86:04dd9b1680ae	249	/** @defgroup RCC_LSI_Config
bogdanm	86:04dd9b1680ae	250	* @{
bogdanm	86:04dd9b1680ae	251	*/
bogdanm	86:04dd9b1680ae	252	#define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm	86:04dd9b1680ae	253	#define RCC_LSI_ON ((uint8_t)0x01)
bogdanm	86:04dd9b1680ae	254
bogdanm	86:04dd9b1680ae	255	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
bogdanm	86:04dd9b1680ae	256	/**
bogdanm	86:04dd9b1680ae	257	* @}
bogdanm	86:04dd9b1680ae	258	*/
bogdanm	86:04dd9b1680ae	259
bogdanm	86:04dd9b1680ae	260	/** @defgroup RCC_PLL_Config
bogdanm	86:04dd9b1680ae	261	* @{
bogdanm	86:04dd9b1680ae	262	*/
bogdanm	86:04dd9b1680ae	263	#define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm	86:04dd9b1680ae	264	#define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm	86:04dd9b1680ae	265	#define RCC_PLL_ON ((uint8_t)0x02)
bogdanm	86:04dd9b1680ae	266
bogdanm	86:04dd9b1680ae	267	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
bogdanm	86:04dd9b1680ae	268	/**
bogdanm	86:04dd9b1680ae	269	* @}
bogdanm	86:04dd9b1680ae	270	*/
bogdanm	86:04dd9b1680ae	271
bogdanm	86:04dd9b1680ae	272	/** @defgroup RCC_PLLP_Clock_Divider
bogdanm	86:04dd9b1680ae	273	* @{
bogdanm	86:04dd9b1680ae	274	*/
bogdanm	86:04dd9b1680ae	275	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	276	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	277	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
bogdanm	86:04dd9b1680ae	278	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	279	/**
bogdanm	86:04dd9b1680ae	280	* @}
bogdanm	86:04dd9b1680ae	281	*/
bogdanm	86:04dd9b1680ae	282
bogdanm	86:04dd9b1680ae	283	/** @defgroup RCC_PLL_Clock_Source
bogdanm	86:04dd9b1680ae	284	* @{
bogdanm	86:04dd9b1680ae	285	*/
bogdanm	86:04dd9b1680ae	286	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
bogdanm	86:04dd9b1680ae	287	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
bogdanm	86:04dd9b1680ae	288
bogdanm	86:04dd9b1680ae	289	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	290	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	86:04dd9b1680ae	291	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
bogdanm	86:04dd9b1680ae	292	#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm	86:04dd9b1680ae	293	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) \|\| ((VALUE) == 4) \|\| ((VALUE) == 6) \|\| ((VALUE) == 8))
bogdanm	86:04dd9b1680ae	294	#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
bogdanm	86:04dd9b1680ae	295
bogdanm	86:04dd9b1680ae	296	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm	86:04dd9b1680ae	297	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm	86:04dd9b1680ae	298
bogdanm	86:04dd9b1680ae	299	/**
bogdanm	86:04dd9b1680ae	300	* @}
bogdanm	86:04dd9b1680ae	301	*/
bogdanm	86:04dd9b1680ae	302
bogdanm	86:04dd9b1680ae	303	/** @defgroup RCC_System_Clock_Type
bogdanm	86:04dd9b1680ae	304	* @{
bogdanm	86:04dd9b1680ae	305	*/
bogdanm	86:04dd9b1680ae	306	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	307	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	308	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	309	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	310
bogdanm	86:04dd9b1680ae	311	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
bogdanm	86:04dd9b1680ae	312	/**
bogdanm	86:04dd9b1680ae	313	* @}
bogdanm	86:04dd9b1680ae	314	*/
bogdanm	86:04dd9b1680ae	315
bogdanm	86:04dd9b1680ae	316	/** @defgroup RCC_System_Clock_Source
bogdanm	86:04dd9b1680ae	317	* @{
bogdanm	86:04dd9b1680ae	318	*/
bogdanm	86:04dd9b1680ae	319	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm	86:04dd9b1680ae	320	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm	86:04dd9b1680ae	321	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm	86:04dd9b1680ae	322
bogdanm	86:04dd9b1680ae	323	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	324	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	86:04dd9b1680ae	325	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	86:04dd9b1680ae	326	/**
bogdanm	86:04dd9b1680ae	327	* @}
bogdanm	86:04dd9b1680ae	328	*/
bogdanm	86:04dd9b1680ae	329
bogdanm	86:04dd9b1680ae	330	/** @defgroup RCC_AHB_Clock_Source
bogdanm	86:04dd9b1680ae	331	* @{
bogdanm	86:04dd9b1680ae	332	*/
bogdanm	86:04dd9b1680ae	333	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm	86:04dd9b1680ae	334	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm	86:04dd9b1680ae	335	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm	86:04dd9b1680ae	336	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm	86:04dd9b1680ae	337	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm	86:04dd9b1680ae	338	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm	86:04dd9b1680ae	339	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm	86:04dd9b1680ae	340	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm	86:04dd9b1680ae	341	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm	86:04dd9b1680ae	342
bogdanm	86:04dd9b1680ae	343	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	86:04dd9b1680ae	344	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	345	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	86:04dd9b1680ae	346	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	86:04dd9b1680ae	347	((HCLK) == RCC_SYSCLK_DIV512))
bogdanm	86:04dd9b1680ae	348	/**
bogdanm	86:04dd9b1680ae	349	* @}
bogdanm	86:04dd9b1680ae	350	*/
bogdanm	86:04dd9b1680ae	351
bogdanm	86:04dd9b1680ae	352	/** @defgroup RCC_APB1_APB2_Clock_Source
bogdanm	86:04dd9b1680ae	353	* @{
bogdanm	86:04dd9b1680ae	354	*/
bogdanm	86:04dd9b1680ae	355	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm	86:04dd9b1680ae	356	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm	86:04dd9b1680ae	357	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm	86:04dd9b1680ae	358	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm	86:04dd9b1680ae	359	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm	86:04dd9b1680ae	360
bogdanm	86:04dd9b1680ae	361	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
bogdanm	86:04dd9b1680ae	362	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	363	((PCLK) == RCC_HCLK_DIV16))
bogdanm	86:04dd9b1680ae	364	/**
bogdanm	86:04dd9b1680ae	365	* @}
bogdanm	86:04dd9b1680ae	366	*/
bogdanm	86:04dd9b1680ae	367
bogdanm	86:04dd9b1680ae	368	/** @defgroup RCC_RTC_Clock_Source
bogdanm	86:04dd9b1680ae	369	* @{
bogdanm	86:04dd9b1680ae	370	*/
bogdanm	86:04dd9b1680ae	371	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
bogdanm	86:04dd9b1680ae	372	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
bogdanm	86:04dd9b1680ae	373	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
bogdanm	86:04dd9b1680ae	374	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
bogdanm	86:04dd9b1680ae	375	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
bogdanm	86:04dd9b1680ae	376	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
bogdanm	86:04dd9b1680ae	377	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
bogdanm	86:04dd9b1680ae	378	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
bogdanm	86:04dd9b1680ae	379	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
bogdanm	86:04dd9b1680ae	380	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
bogdanm	86:04dd9b1680ae	381	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
bogdanm	86:04dd9b1680ae	382	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
bogdanm	86:04dd9b1680ae	383	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
bogdanm	86:04dd9b1680ae	384	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
bogdanm	86:04dd9b1680ae	385	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
bogdanm	86:04dd9b1680ae	386	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
bogdanm	86:04dd9b1680ae	387	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
bogdanm	86:04dd9b1680ae	388	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
bogdanm	86:04dd9b1680ae	389	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
bogdanm	86:04dd9b1680ae	390	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
bogdanm	86:04dd9b1680ae	391	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
bogdanm	86:04dd9b1680ae	392	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
bogdanm	86:04dd9b1680ae	393	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
bogdanm	86:04dd9b1680ae	394	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
bogdanm	86:04dd9b1680ae	395	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
bogdanm	86:04dd9b1680ae	396	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
bogdanm	86:04dd9b1680ae	397	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
bogdanm	86:04dd9b1680ae	398	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
bogdanm	86:04dd9b1680ae	399	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
bogdanm	86:04dd9b1680ae	400	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
bogdanm	86:04dd9b1680ae	401	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
bogdanm	86:04dd9b1680ae	402	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
bogdanm	86:04dd9b1680ae	403	/**
bogdanm	86:04dd9b1680ae	404	* @}
bogdanm	86:04dd9b1680ae	405	*/
bogdanm	86:04dd9b1680ae	406
bogdanm	86:04dd9b1680ae	407	/** @defgroup RCC_I2S_Clock_Source
bogdanm	86:04dd9b1680ae	408	* @{
bogdanm	86:04dd9b1680ae	409	*/
bogdanm	86:04dd9b1680ae	410	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	411	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	412	/**
bogdanm	86:04dd9b1680ae	413	* @}
bogdanm	86:04dd9b1680ae	414	*/
bogdanm	86:04dd9b1680ae	415
bogdanm	86:04dd9b1680ae	416	/** @defgroup RCC_MCO_Index
bogdanm	86:04dd9b1680ae	417	* @{
bogdanm	86:04dd9b1680ae	418	*/
bogdanm	86:04dd9b1680ae	419	#define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	420	#define RCC_MCO2 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	421
bogdanm	86:04dd9b1680ae	422	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
bogdanm	86:04dd9b1680ae	423	/**
bogdanm	86:04dd9b1680ae	424	* @}
bogdanm	86:04dd9b1680ae	425	*/
bogdanm	86:04dd9b1680ae	426
bogdanm	86:04dd9b1680ae	427	/** @defgroup RCC_MCO1_Clock_Source
bogdanm	86:04dd9b1680ae	428	* @{
bogdanm	86:04dd9b1680ae	429	*/
bogdanm	86:04dd9b1680ae	430	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	431	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
bogdanm	86:04dd9b1680ae	432	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
bogdanm	86:04dd9b1680ae	433	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
bogdanm	86:04dd9b1680ae	434
bogdanm	86:04dd9b1680ae	435	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	436	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
bogdanm	86:04dd9b1680ae	437	/**
bogdanm	86:04dd9b1680ae	438	* @}
bogdanm	86:04dd9b1680ae	439	*/
bogdanm	86:04dd9b1680ae	440
bogdanm	86:04dd9b1680ae	441	/** @defgroup RCC_MCO2_Clock_Source
bogdanm	86:04dd9b1680ae	442	* @{
bogdanm	86:04dd9b1680ae	443	*/
bogdanm	86:04dd9b1680ae	444	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	445	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
bogdanm	86:04dd9b1680ae	446	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
bogdanm	86:04dd9b1680ae	447	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
bogdanm	86:04dd9b1680ae	448
bogdanm	86:04dd9b1680ae	449	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
bogdanm	86:04dd9b1680ae	450	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
bogdanm	86:04dd9b1680ae	451	/**
bogdanm	86:04dd9b1680ae	452	* @}
bogdanm	86:04dd9b1680ae	453	*/
bogdanm	86:04dd9b1680ae	454
bogdanm	86:04dd9b1680ae	455	/** @defgroup RCC_MCOx_Clock_Prescaler
bogdanm	86:04dd9b1680ae	456	* @{
bogdanm	86:04dd9b1680ae	457	*/
bogdanm	86:04dd9b1680ae	458	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	459	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
bogdanm	86:04dd9b1680ae	460	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
bogdanm	86:04dd9b1680ae	461	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
bogdanm	86:04dd9b1680ae	462	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
bogdanm	86:04dd9b1680ae	463
bogdanm	86:04dd9b1680ae	464	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
bogdanm	86:04dd9b1680ae	465	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
bogdanm	86:04dd9b1680ae	466	((DIV) == RCC_MCODIV_5))
bogdanm	86:04dd9b1680ae	467	/**
bogdanm	86:04dd9b1680ae	468	* @}
bogdanm	86:04dd9b1680ae	469	*/
bogdanm	86:04dd9b1680ae	470
bogdanm	86:04dd9b1680ae	471	/** @defgroup RCC_Interrupt
bogdanm	86:04dd9b1680ae	472	* @{
bogdanm	86:04dd9b1680ae	473	*/
bogdanm	86:04dd9b1680ae	474	#define RCC_IT_LSIRDY ((uint8_t)0x01)
bogdanm	86:04dd9b1680ae	475	#define RCC_IT_LSERDY ((uint8_t)0x02)
bogdanm	86:04dd9b1680ae	476	#define RCC_IT_HSIRDY ((uint8_t)0x04)
bogdanm	86:04dd9b1680ae	477	#define RCC_IT_HSERDY ((uint8_t)0x08)
bogdanm	86:04dd9b1680ae	478	#define RCC_IT_PLLRDY ((uint8_t)0x10)
bogdanm	86:04dd9b1680ae	479	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
bogdanm	86:04dd9b1680ae	480	#define RCC_IT_CSS ((uint8_t)0x80)
bogdanm	86:04dd9b1680ae	481	/**
bogdanm	86:04dd9b1680ae	482	* @}
bogdanm	86:04dd9b1680ae	483	*/
bogdanm	86:04dd9b1680ae	484
bogdanm	86:04dd9b1680ae	485	/** @defgroup RCC_Flag
bogdanm	86:04dd9b1680ae	486	* Elements values convention: 0XXYYYYYb
bogdanm	86:04dd9b1680ae	487	* - YYYYY : Flag position in the register
bogdanm	86:04dd9b1680ae	488	* - 0XX : Register index
bogdanm	86:04dd9b1680ae	489	* - 01: CR register
bogdanm	86:04dd9b1680ae	490	* - 10: BDCR register
bogdanm	86:04dd9b1680ae	491	* - 11: CSR register
bogdanm	86:04dd9b1680ae	492	* @{
bogdanm	86:04dd9b1680ae	493	*/
bogdanm	86:04dd9b1680ae	494	/* Flags in the CR register */
bogdanm	86:04dd9b1680ae	495	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
bogdanm	86:04dd9b1680ae	496	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm	86:04dd9b1680ae	497	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm	86:04dd9b1680ae	498	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
bogdanm	86:04dd9b1680ae	499
bogdanm	86:04dd9b1680ae	500	/* Flags in the BDCR register */
bogdanm	86:04dd9b1680ae	501	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
bogdanm	86:04dd9b1680ae	502
bogdanm	86:04dd9b1680ae	503	/* Flags in the CSR register */
bogdanm	86:04dd9b1680ae	504	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
bogdanm	86:04dd9b1680ae	505	#define RCC_FLAG_BORRST ((uint8_t)0x79)
bogdanm	86:04dd9b1680ae	506	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
bogdanm	86:04dd9b1680ae	507	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
bogdanm	86:04dd9b1680ae	508	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
bogdanm	86:04dd9b1680ae	509	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
bogdanm	86:04dd9b1680ae	510	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
bogdanm	86:04dd9b1680ae	511	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
bogdanm	86:04dd9b1680ae	512
bogdanm	86:04dd9b1680ae	513	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm	86:04dd9b1680ae	514	/**
bogdanm	86:04dd9b1680ae	515	* @}
bogdanm	86:04dd9b1680ae	516	*/
bogdanm	86:04dd9b1680ae	517
bogdanm	86:04dd9b1680ae	518	/**
bogdanm	86:04dd9b1680ae	519	* @}
bogdanm	86:04dd9b1680ae	520	*/
bogdanm	86:04dd9b1680ae	521	/* Exported macro ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	522
bogdanm	86:04dd9b1680ae	523	/** @brief Enable or disable the AHB1 peripheral clock.
bogdanm	86:04dd9b1680ae	524	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	525	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	526	* using it.
bogdanm	86:04dd9b1680ae	527	*/
bogdanm	86:04dd9b1680ae	528	#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOAEN))
bogdanm	86:04dd9b1680ae	529	#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOBEN))
bogdanm	86:04dd9b1680ae	530	#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOCEN))
bogdanm	86:04dd9b1680ae	531	#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIODEN))
bogdanm	86:04dd9b1680ae	532	#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOEEN))
bogdanm	86:04dd9b1680ae	533	#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOHEN))
bogdanm	86:04dd9b1680ae	534	#define __CRC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CRCEN))
bogdanm	86:04dd9b1680ae	535	#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_BKPSRAMEN))
bogdanm	86:04dd9b1680ae	536	#define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CCMDATARAMEN))
bogdanm	86:04dd9b1680ae	537	#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA1EN))
bogdanm	86:04dd9b1680ae	538	#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA2EN))
bogdanm	86:04dd9b1680ae	539
bogdanm	86:04dd9b1680ae	540	#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
bogdanm	86:04dd9b1680ae	541	#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
bogdanm	86:04dd9b1680ae	542	#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
bogdanm	86:04dd9b1680ae	543	#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
bogdanm	86:04dd9b1680ae	544	#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
bogdanm	86:04dd9b1680ae	545	#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
bogdanm	86:04dd9b1680ae	546	#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm	86:04dd9b1680ae	547	#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
bogdanm	86:04dd9b1680ae	548	#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
bogdanm	86:04dd9b1680ae	549	#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
bogdanm	86:04dd9b1680ae	550	#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
bogdanm	86:04dd9b1680ae	551
bogdanm	86:04dd9b1680ae	552	/** @brief Enable or disable the AHB2 peripheral clock.
bogdanm	86:04dd9b1680ae	553	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	554	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	555	* using it.
bogdanm	86:04dd9b1680ae	556	*/
bogdanm	86:04dd9b1680ae	557	#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
bogdanm	86:04dd9b1680ae	558	__SYSCFG_CLK_ENABLE();\
bogdanm	86:04dd9b1680ae	559	}while(0)
bogdanm	86:04dd9b1680ae	560
bogdanm	86:04dd9b1680ae	561
bogdanm	86:04dd9b1680ae	562	#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
bogdanm	86:04dd9b1680ae	563	__SYSCFG_CLK_DISABLE();\
bogdanm	86:04dd9b1680ae	564	}while(0)
bogdanm	86:04dd9b1680ae	565
bogdanm	86:04dd9b1680ae	566	#define __RNG_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_RNGEN))
bogdanm	86:04dd9b1680ae	567	#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
bogdanm	86:04dd9b1680ae	568	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	86:04dd9b1680ae	569	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	570	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	571	* using it.
bogdanm	86:04dd9b1680ae	572	*/
bogdanm	86:04dd9b1680ae	573	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	86:04dd9b1680ae	574	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
bogdanm	86:04dd9b1680ae	575	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
bogdanm	86:04dd9b1680ae	576	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
bogdanm	86:04dd9b1680ae	577	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
bogdanm	86:04dd9b1680ae	578	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	86:04dd9b1680ae	579	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
bogdanm	86:04dd9b1680ae	580	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	86:04dd9b1680ae	581	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
bogdanm	86:04dd9b1680ae	582	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	86:04dd9b1680ae	583	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
bogdanm	86:04dd9b1680ae	584	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
bogdanm	86:04dd9b1680ae	585
bogdanm	86:04dd9b1680ae	586	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	86:04dd9b1680ae	587	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	86:04dd9b1680ae	588	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm	86:04dd9b1680ae	589	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
bogdanm	86:04dd9b1680ae	590	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	86:04dd9b1680ae	591	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	86:04dd9b1680ae	592	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm	86:04dd9b1680ae	593	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	86:04dd9b1680ae	594	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm	86:04dd9b1680ae	595	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	86:04dd9b1680ae	596	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm	86:04dd9b1680ae	597	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm	86:04dd9b1680ae	598
bogdanm	86:04dd9b1680ae	599	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	86:04dd9b1680ae	600	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	601	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	602	* using it.
bogdanm	86:04dd9b1680ae	603	*/
bogdanm	86:04dd9b1680ae	604	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
bogdanm	86:04dd9b1680ae	605	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
bogdanm	86:04dd9b1680ae	606	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
bogdanm	86:04dd9b1680ae	607	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
bogdanm	86:04dd9b1680ae	608	#define __SDIO_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDIOEN))
bogdanm	86:04dd9b1680ae	609	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
bogdanm	86:04dd9b1680ae	610	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
bogdanm	86:04dd9b1680ae	611	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
bogdanm	86:04dd9b1680ae	612	#define __TIM9_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM9EN))
bogdanm	86:04dd9b1680ae	613	#define __TIM10_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM10EN))
bogdanm	86:04dd9b1680ae	614	#define __TIM11_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM11EN))
bogdanm	86:04dd9b1680ae	615
bogdanm	86:04dd9b1680ae	616	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm	86:04dd9b1680ae	617	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm	86:04dd9b1680ae	618	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
bogdanm	86:04dd9b1680ae	619	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm	86:04dd9b1680ae	620	#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
bogdanm	86:04dd9b1680ae	621	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	86:04dd9b1680ae	622	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
bogdanm	86:04dd9b1680ae	623	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm	86:04dd9b1680ae	624	#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
bogdanm	86:04dd9b1680ae	625	#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
bogdanm	86:04dd9b1680ae	626	#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
bogdanm	86:04dd9b1680ae	627
bogdanm	86:04dd9b1680ae	628	/** @brief Force or release AHB1 peripheral reset.
bogdanm	86:04dd9b1680ae	629	*/
bogdanm	86:04dd9b1680ae	630	#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
bogdanm	86:04dd9b1680ae	631	#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
bogdanm	86:04dd9b1680ae	632	#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
bogdanm	86:04dd9b1680ae	633	#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
bogdanm	86:04dd9b1680ae	634	#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
bogdanm	86:04dd9b1680ae	635	#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
bogdanm	86:04dd9b1680ae	636	#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
bogdanm	86:04dd9b1680ae	637	#define __CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
bogdanm	86:04dd9b1680ae	638	#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
bogdanm	86:04dd9b1680ae	639	#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
bogdanm	86:04dd9b1680ae	640
bogdanm	86:04dd9b1680ae	641	#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
bogdanm	86:04dd9b1680ae	642	#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
bogdanm	86:04dd9b1680ae	643	#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
bogdanm	86:04dd9b1680ae	644	#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
bogdanm	86:04dd9b1680ae	645	#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
bogdanm	86:04dd9b1680ae	646	#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
bogdanm	86:04dd9b1680ae	647	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm	86:04dd9b1680ae	648	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm	86:04dd9b1680ae	649	#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
bogdanm	86:04dd9b1680ae	650	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm	86:04dd9b1680ae	651	#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
bogdanm	86:04dd9b1680ae	652	#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
bogdanm	86:04dd9b1680ae	653	#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
bogdanm	86:04dd9b1680ae	654
bogdanm	86:04dd9b1680ae	655	/** @brief Force or release AHB2 peripheral reset.
bogdanm	86:04dd9b1680ae	656	*/
bogdanm	86:04dd9b1680ae	657	#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
bogdanm	86:04dd9b1680ae	658	#define __USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
bogdanm	86:04dd9b1680ae	659
bogdanm	86:04dd9b1680ae	660	#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
bogdanm	86:04dd9b1680ae	661	#define __USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
bogdanm	86:04dd9b1680ae	662
bogdanm	86:04dd9b1680ae	663	/* alias define maintained for legacy */
bogdanm	86:04dd9b1680ae	664	#define __OTGFS_FORCE_RESET __USB_OTG_FS_FORCE_RESET
bogdanm	86:04dd9b1680ae	665	#define __OTGFS_RELEASE_RESET __USB_OTG_FS_RELEASE_RESET
bogdanm	86:04dd9b1680ae	666
bogdanm	86:04dd9b1680ae	667	#define __RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
bogdanm	86:04dd9b1680ae	668	#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
bogdanm	86:04dd9b1680ae	669
bogdanm	86:04dd9b1680ae	670	/** @brief Force or release APB1 peripheral reset.
bogdanm	86:04dd9b1680ae	671	*/
bogdanm	86:04dd9b1680ae	672	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm	86:04dd9b1680ae	673	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	86:04dd9b1680ae	674	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	86:04dd9b1680ae	675	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
bogdanm	86:04dd9b1680ae	676	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
bogdanm	86:04dd9b1680ae	677	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
bogdanm	86:04dd9b1680ae	678	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	86:04dd9b1680ae	679	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
bogdanm	86:04dd9b1680ae	680	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	86:04dd9b1680ae	681	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	86:04dd9b1680ae	682	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	86:04dd9b1680ae	683	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
bogdanm	86:04dd9b1680ae	684	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	86:04dd9b1680ae	685
bogdanm	86:04dd9b1680ae	686	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm	86:04dd9b1680ae	687	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	86:04dd9b1680ae	688	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	86:04dd9b1680ae	689	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm	86:04dd9b1680ae	690	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
bogdanm	86:04dd9b1680ae	691	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm	86:04dd9b1680ae	692	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	86:04dd9b1680ae	693	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm	86:04dd9b1680ae	694	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	86:04dd9b1680ae	695	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm	86:04dd9b1680ae	696	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	86:04dd9b1680ae	697	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm	86:04dd9b1680ae	698	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm	86:04dd9b1680ae	699
bogdanm	86:04dd9b1680ae	700	/** @brief Force or release APB2 peripheral reset.
bogdanm	86:04dd9b1680ae	701	*/
bogdanm	86:04dd9b1680ae	702	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm	86:04dd9b1680ae	703	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
bogdanm	86:04dd9b1680ae	704	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	86:04dd9b1680ae	705	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
bogdanm	86:04dd9b1680ae	706	#define __ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
bogdanm	86:04dd9b1680ae	707	#define __SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
bogdanm	86:04dd9b1680ae	708	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	86:04dd9b1680ae	709	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
bogdanm	86:04dd9b1680ae	710	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
bogdanm	86:04dd9b1680ae	711	#define __TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
bogdanm	86:04dd9b1680ae	712	#define __TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
bogdanm	86:04dd9b1680ae	713	#define __TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
bogdanm	86:04dd9b1680ae	714
bogdanm	86:04dd9b1680ae	715	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm	86:04dd9b1680ae	716	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm	86:04dd9b1680ae	717	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	86:04dd9b1680ae	718	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
bogdanm	86:04dd9b1680ae	719	#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
bogdanm	86:04dd9b1680ae	720	#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
bogdanm	86:04dd9b1680ae	721	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	86:04dd9b1680ae	722	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
bogdanm	86:04dd9b1680ae	723	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm	86:04dd9b1680ae	724	#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
bogdanm	86:04dd9b1680ae	725	#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
bogdanm	86:04dd9b1680ae	726	#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
bogdanm	86:04dd9b1680ae	727
bogdanm	86:04dd9b1680ae	728	/** @brief Force or release AHB3 peripheral reset.
bogdanm	86:04dd9b1680ae	729	*/
bogdanm	86:04dd9b1680ae	730	#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
bogdanm	86:04dd9b1680ae	731	#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
bogdanm	86:04dd9b1680ae	732
bogdanm	86:04dd9b1680ae	733	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	86:04dd9b1680ae	734	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	86:04dd9b1680ae	735	* power consumption.
bogdanm	86:04dd9b1680ae	736	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	86:04dd9b1680ae	737	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	86:04dd9b1680ae	738	*/
bogdanm	86:04dd9b1680ae	739	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
bogdanm	86:04dd9b1680ae	740	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
bogdanm	86:04dd9b1680ae	741	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
bogdanm	86:04dd9b1680ae	742	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
bogdanm	86:04dd9b1680ae	743	#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
bogdanm	86:04dd9b1680ae	744	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
bogdanm	86:04dd9b1680ae	745	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
bogdanm	86:04dd9b1680ae	746	#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
bogdanm	86:04dd9b1680ae	747	#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
bogdanm	86:04dd9b1680ae	748	#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm	86:04dd9b1680ae	749	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
bogdanm	86:04dd9b1680ae	750	#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
bogdanm	86:04dd9b1680ae	751
bogdanm	86:04dd9b1680ae	752	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
bogdanm	86:04dd9b1680ae	753	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
bogdanm	86:04dd9b1680ae	754	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
bogdanm	86:04dd9b1680ae	755	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
bogdanm	86:04dd9b1680ae	756	#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
bogdanm	86:04dd9b1680ae	757	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
bogdanm	86:04dd9b1680ae	758	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
bogdanm	86:04dd9b1680ae	759	#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
bogdanm	86:04dd9b1680ae	760	#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
bogdanm	86:04dd9b1680ae	761	#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm	86:04dd9b1680ae	762	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
bogdanm	86:04dd9b1680ae	763	#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
bogdanm	86:04dd9b1680ae	764
bogdanm	86:04dd9b1680ae	765	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	86:04dd9b1680ae	766	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	86:04dd9b1680ae	767	* power consumption.
bogdanm	86:04dd9b1680ae	768	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	86:04dd9b1680ae	769	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	86:04dd9b1680ae	770	*/
bogdanm	86:04dd9b1680ae	771	#define __USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
bogdanm	86:04dd9b1680ae	772
bogdanm	86:04dd9b1680ae	773	#define __USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
bogdanm	86:04dd9b1680ae	774
bogdanm	86:04dd9b1680ae	775	/* alias define maintained for legacy */
bogdanm	86:04dd9b1680ae	776	#define __OTGFS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_ENABLE
bogdanm	86:04dd9b1680ae	777	#define __OTGFS_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_SLEEP_DISABLE
bogdanm	86:04dd9b1680ae	778
bogdanm	86:04dd9b1680ae	779	#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
bogdanm	86:04dd9b1680ae	780	#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
bogdanm	86:04dd9b1680ae	781
bogdanm	86:04dd9b1680ae	782	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	86:04dd9b1680ae	783	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	86:04dd9b1680ae	784	* power consumption.
bogdanm	86:04dd9b1680ae	785	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	86:04dd9b1680ae	786	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	86:04dd9b1680ae	787	*/
bogdanm	86:04dd9b1680ae	788	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
bogdanm	86:04dd9b1680ae	789	#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
bogdanm	86:04dd9b1680ae	790	#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
bogdanm	86:04dd9b1680ae	791	#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
bogdanm	86:04dd9b1680ae	792	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
bogdanm	86:04dd9b1680ae	793	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
bogdanm	86:04dd9b1680ae	794	#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
bogdanm	86:04dd9b1680ae	795	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
bogdanm	86:04dd9b1680ae	796	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
bogdanm	86:04dd9b1680ae	797	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
bogdanm	86:04dd9b1680ae	798	#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
bogdanm	86:04dd9b1680ae	799	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
bogdanm	86:04dd9b1680ae	800
bogdanm	86:04dd9b1680ae	801	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
bogdanm	86:04dd9b1680ae	802	#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
bogdanm	86:04dd9b1680ae	803	#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
bogdanm	86:04dd9b1680ae	804	#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
bogdanm	86:04dd9b1680ae	805	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
bogdanm	86:04dd9b1680ae	806	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
bogdanm	86:04dd9b1680ae	807	#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
bogdanm	86:04dd9b1680ae	808	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
bogdanm	86:04dd9b1680ae	809	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
bogdanm	86:04dd9b1680ae	810	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
bogdanm	86:04dd9b1680ae	811	#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
bogdanm	86:04dd9b1680ae	812	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
bogdanm	86:04dd9b1680ae	813
bogdanm	86:04dd9b1680ae	814	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	86:04dd9b1680ae	815	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	86:04dd9b1680ae	816	* power consumption.
bogdanm	86:04dd9b1680ae	817	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	86:04dd9b1680ae	818	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	86:04dd9b1680ae	819	*/
bogdanm	86:04dd9b1680ae	820	#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
bogdanm	86:04dd9b1680ae	821	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
bogdanm	86:04dd9b1680ae	822	#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
bogdanm	86:04dd9b1680ae	823	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
bogdanm	86:04dd9b1680ae	824	#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
bogdanm	86:04dd9b1680ae	825	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
bogdanm	86:04dd9b1680ae	826	#define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
bogdanm	86:04dd9b1680ae	827	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
bogdanm	86:04dd9b1680ae	828	#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
bogdanm	86:04dd9b1680ae	829	#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
bogdanm	86:04dd9b1680ae	830	#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
bogdanm	86:04dd9b1680ae	831
bogdanm	86:04dd9b1680ae	832	#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
bogdanm	86:04dd9b1680ae	833	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
bogdanm	86:04dd9b1680ae	834	#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
bogdanm	86:04dd9b1680ae	835	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
bogdanm	86:04dd9b1680ae	836	#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
bogdanm	86:04dd9b1680ae	837	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
bogdanm	86:04dd9b1680ae	838	#define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
bogdanm	86:04dd9b1680ae	839	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
bogdanm	86:04dd9b1680ae	840	#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
bogdanm	86:04dd9b1680ae	841	#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
bogdanm	86:04dd9b1680ae	842	#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
bogdanm	86:04dd9b1680ae	843
bogdanm	86:04dd9b1680ae	844	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	86:04dd9b1680ae	845	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	846	* It is used (enabled by hardware) as system clock source after startup
bogdanm	86:04dd9b1680ae	847	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm	86:04dd9b1680ae	848	* of the HSE used directly or indirectly as system clock (if the Clock
bogdanm	86:04dd9b1680ae	849	* Security System CSS is enabled).
bogdanm	86:04dd9b1680ae	850	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	86:04dd9b1680ae	851	* you have to select another source of the system clock then stop the HSI.
bogdanm	86:04dd9b1680ae	852	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	86:04dd9b1680ae	853	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	86:04dd9b1680ae	854	* system clock source.
bogdanm	86:04dd9b1680ae	855	* This parameter can be: ENABLE or DISABLE.
bogdanm	86:04dd9b1680ae	856	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	86:04dd9b1680ae	857	* clock cycles.
bogdanm	86:04dd9b1680ae	858	*/
bogdanm	86:04dd9b1680ae	859	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) CR_HSION_BB = ENABLE)
bogdanm	86:04dd9b1680ae	860	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) CR_HSION_BB = DISABLE)
bogdanm	86:04dd9b1680ae	861
bogdanm	86:04dd9b1680ae	862	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	86:04dd9b1680ae	863	* @note The calibration is used to compensate for the variations in voltage
bogdanm	86:04dd9b1680ae	864	* and temperature that influence the frequency of the internal HSI RC.
bogdanm	86:04dd9b1680ae	865	* @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm	86:04dd9b1680ae	866	* This parameter must be a number between 0 and 0x1F.
bogdanm	86:04dd9b1680ae	867	*/
bogdanm	86:04dd9b1680ae	868	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
bogdanm	86:04dd9b1680ae	869	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
bogdanm	86:04dd9b1680ae	870
bogdanm	86:04dd9b1680ae	871	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	86:04dd9b1680ae	872	* @note After enabling the LSI, the application software should wait on
bogdanm	86:04dd9b1680ae	873	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	86:04dd9b1680ae	874	* be used to clock the IWDG and/or the RTC.
bogdanm	86:04dd9b1680ae	875	* @note LSI can not be disabled if the IWDG is running.
bogdanm	86:04dd9b1680ae	876	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	86:04dd9b1680ae	877	* clock cycles.
bogdanm	86:04dd9b1680ae	878	*/
bogdanm	86:04dd9b1680ae	879	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) CSR_LSION_BB = ENABLE)
bogdanm	86:04dd9b1680ae	880	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) CSR_LSION_BB = DISABLE)
bogdanm	86:04dd9b1680ae	881
bogdanm	86:04dd9b1680ae	882	/**
bogdanm	86:04dd9b1680ae	883	* @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm	86:04dd9b1680ae	884	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	86:04dd9b1680ae	885	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	86:04dd9b1680ae	886	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	86:04dd9b1680ae	887	* @note HSE state can not be changed if it is used directly or through the
bogdanm	86:04dd9b1680ae	888	* PLL as system clock. In this case, you have to select another source
bogdanm	86:04dd9b1680ae	889	* of the system clock then change the HSE state (ex. disable it).
bogdanm	86:04dd9b1680ae	890	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	891	* @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm	86:04dd9b1680ae	892	* was previously enabled you have to enable it again after calling this
bogdanm	86:04dd9b1680ae	893	* function.
bogdanm	86:04dd9b1680ae	894	* @param __STATE__: specifies the new state of the HSE.
bogdanm	86:04dd9b1680ae	895	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	896	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	86:04dd9b1680ae	897	* 6 HSE oscillator clock cycles.
bogdanm	86:04dd9b1680ae	898	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm	86:04dd9b1680ae	899	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm	86:04dd9b1680ae	900	*/
bogdanm	86:04dd9b1680ae	901	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) CR_BYTE2_ADDRESS = (__STATE__))
bogdanm	86:04dd9b1680ae	902
bogdanm	86:04dd9b1680ae	903	/**
bogdanm	86:04dd9b1680ae	904	* @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm	86:04dd9b1680ae	905	* @note As the LSE is in the Backup domain and write access is denied to
bogdanm	86:04dd9b1680ae	906	* this domain after reset, you have to enable write access using
bogdanm	86:04dd9b1680ae	907	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm	86:04dd9b1680ae	908	* (to be done once after reset).
bogdanm	86:04dd9b1680ae	909	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	86:04dd9b1680ae	910	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	86:04dd9b1680ae	911	* is stable and can be used to clock the RTC.
bogdanm	86:04dd9b1680ae	912	* @param __STATE__: specifies the new state of the LSE.
bogdanm	86:04dd9b1680ae	913	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	914	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	86:04dd9b1680ae	915	* 6 LSE oscillator clock cycles.
bogdanm	86:04dd9b1680ae	916	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm	86:04dd9b1680ae	917	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm	86:04dd9b1680ae	918	*/
bogdanm	86:04dd9b1680ae	919	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) BDCR_BYTE0_ADDRESS = (__STATE__))
bogdanm	86:04dd9b1680ae	920
bogdanm	86:04dd9b1680ae	921	/** @brief Macros to enable or disable the the RTC clock.
bogdanm	86:04dd9b1680ae	922	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	86:04dd9b1680ae	923	*/
bogdanm	86:04dd9b1680ae	924	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = ENABLE)
bogdanm	86:04dd9b1680ae	925	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = DISABLE)
bogdanm	86:04dd9b1680ae	926
bogdanm	86:04dd9b1680ae	927	/** @brief Macros to configure the RTC clock (RTCCLK).
bogdanm	86:04dd9b1680ae	928	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	86:04dd9b1680ae	929	* access is denied to this domain after reset, you have to enable write
bogdanm	86:04dd9b1680ae	930	* access using the Power Backup Access macro before to configure
bogdanm	86:04dd9b1680ae	931	* the RTC clock source (to be done once after reset).
bogdanm	86:04dd9b1680ae	932	* @note Once the RTC clock is configured it can't be changed unless the
bogdanm	86:04dd9b1680ae	933	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm	86:04dd9b1680ae	934	* a Power On Reset (POR).
bogdanm	86:04dd9b1680ae	935	* @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm	86:04dd9b1680ae	936	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	937	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm	86:04dd9b1680ae	938	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm	86:04dd9b1680ae	939	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
bogdanm	86:04dd9b1680ae	940	* as RTC clock, where x:[2,31]
bogdanm	86:04dd9b1680ae	941	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	86:04dd9b1680ae	942	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	86:04dd9b1680ae	943	* However, when the HSE clock is used as RTC clock source, the RTC
bogdanm	86:04dd9b1680ae	944	* cannot be used in STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	945	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm	86:04dd9b1680ae	946	* RTC clock source).
bogdanm	86:04dd9b1680ae	947	*/
bogdanm	86:04dd9b1680ae	948	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
bogdanm	86:04dd9b1680ae	949	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm	86:04dd9b1680ae	950
bogdanm	86:04dd9b1680ae	951	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
bogdanm	86:04dd9b1680ae	952	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
bogdanm	86:04dd9b1680ae	953	} while (0)
bogdanm	86:04dd9b1680ae	954
bogdanm	86:04dd9b1680ae	955	/** @brief Macros to force or release the Backup domain reset.
bogdanm	86:04dd9b1680ae	956	* @note This function resets the RTC peripheral (including the backup registers)
bogdanm	86:04dd9b1680ae	957	* and the RTC clock source selection in RCC_CSR register.
bogdanm	86:04dd9b1680ae	958	* @note The BKPSRAM is not affected by this reset.
bogdanm	86:04dd9b1680ae	959	*/
bogdanm	86:04dd9b1680ae	960	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) BDCR_BDRST_BB = ENABLE)
bogdanm	86:04dd9b1680ae	961	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) BDCR_BDRST_BB = DISABLE)
bogdanm	86:04dd9b1680ae	962
bogdanm	86:04dd9b1680ae	963	/** @brief Macros to enable or disable the main PLL.
bogdanm	86:04dd9b1680ae	964	* @note After enabling the main PLL, the application software should wait on
bogdanm	86:04dd9b1680ae	965	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	86:04dd9b1680ae	966	* be used as system clock source.
bogdanm	86:04dd9b1680ae	967	* @note The main PLL can not be disabled if it is used as system clock source
bogdanm	86:04dd9b1680ae	968	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	969	*/
bogdanm	86:04dd9b1680ae	970	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) CR_PLLON_BB = ENABLE)
bogdanm	86:04dd9b1680ae	971	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) CR_PLLON_BB = DISABLE)
bogdanm	86:04dd9b1680ae	972
bogdanm	86:04dd9b1680ae	973	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm	86:04dd9b1680ae	974	* @note This function must be used only when the main PLL is disabled.
bogdanm	86:04dd9b1680ae	975	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm	86:04dd9b1680ae	976	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	977	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	86:04dd9b1680ae	978	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	86:04dd9b1680ae	979	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
bogdanm	86:04dd9b1680ae	980	* @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm	86:04dd9b1680ae	981	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm	86:04dd9b1680ae	982	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm	86:04dd9b1680ae	983	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm	86:04dd9b1680ae	984	* of 2 MHz to limit PLL jitter.
bogdanm	86:04dd9b1680ae	985	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
bogdanm	86:04dd9b1680ae	986	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	86:04dd9b1680ae	987	* @note You have to set the PLLN parameter correctly to ensure that the VCO
bogdanm	86:04dd9b1680ae	988	* output frequency is between 192 and 432 MHz.
bogdanm	86:04dd9b1680ae	989	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
bogdanm	86:04dd9b1680ae	990	* This parameter must be a number in the range {2, 4, 6, or 8}.
bogdanm	86:04dd9b1680ae	991	* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
bogdanm	86:04dd9b1680ae	992	* the System clock frequency.
bogdanm	86:04dd9b1680ae	993	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
bogdanm	86:04dd9b1680ae	994	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	86:04dd9b1680ae	995	* @note If the USB OTG FS is used in your application, you have to set the
bogdanm	86:04dd9b1680ae	996	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
bogdanm	86:04dd9b1680ae	997	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
bogdanm	86:04dd9b1680ae	998	* correctly.
bogdanm	86:04dd9b1680ae	999	*/
bogdanm	86:04dd9b1680ae	1000	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
bogdanm	86:04dd9b1680ae	1001	(RCC->PLLCFGR = (0x20000000 \| (__PLLM__) \| ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
bogdanm	86:04dd9b1680ae	1002	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| (__RCC_PLLSource__) \| \
bogdanm	86:04dd9b1680ae	1003	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
bogdanm	86:04dd9b1680ae	1004
bogdanm	86:04dd9b1680ae	1005	/** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm	86:04dd9b1680ae	1006	* @note This function must be called before enabling the I2S APB clock.
bogdanm	86:04dd9b1680ae	1007	* @param __SOURCE__: specifies the I2S clock source.
bogdanm	86:04dd9b1680ae	1008	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	1009	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
bogdanm	86:04dd9b1680ae	1010	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm	86:04dd9b1680ae	1011	* used as I2S clock source.
bogdanm	86:04dd9b1680ae	1012	*/
bogdanm	86:04dd9b1680ae	1013	#define __HAL_RCC_I2SCLK(__SOURCE__) ((__IO uint32_t ) CFGR_I2SSRC_BB = (__SOURCE__))
bogdanm	86:04dd9b1680ae	1014
bogdanm	86:04dd9b1680ae	1015	/** @brief Macros to enable or disable the PLLI2S.
bogdanm	86:04dd9b1680ae	1016	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	1017	*/
bogdanm	86:04dd9b1680ae	1018	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = ENABLE)
bogdanm	86:04dd9b1680ae	1019	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = DISABLE)
bogdanm	86:04dd9b1680ae	1020
bogdanm	86:04dd9b1680ae	1021	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
bogdanm	86:04dd9b1680ae	1022	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	86:04dd9b1680ae	1023	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	86:04dd9b1680ae	1024	* HAL_RCC_ClockConfig() API).
bogdanm	86:04dd9b1680ae	1025	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
bogdanm	86:04dd9b1680ae	1026	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	86:04dd9b1680ae	1027	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm	86:04dd9b1680ae	1028	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	86:04dd9b1680ae	1029	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	86:04dd9b1680ae	1030	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	86:04dd9b1680ae	1031	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm	86:04dd9b1680ae	1032	* on the I2S clock frequency.
bogdanm	86:04dd9b1680ae	1033	*/
bogdanm	86:04dd9b1680ae	1034	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
bogdanm	86:04dd9b1680ae	1035
bogdanm	86:04dd9b1680ae	1036	/** @brief Macro to get the clock source used as system clock.
bogdanm	86:04dd9b1680ae	1037	* @retval The clock source used as system clock. The returned value can be one
bogdanm	86:04dd9b1680ae	1038	* of the following:
bogdanm	86:04dd9b1680ae	1039	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
bogdanm	86:04dd9b1680ae	1040	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
bogdanm	86:04dd9b1680ae	1041	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
bogdanm	86:04dd9b1680ae	1042	*/
bogdanm	86:04dd9b1680ae	1043	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm	86:04dd9b1680ae	1044
bogdanm	86:04dd9b1680ae	1045	/** @brief Macro to get the oscillator used as PLL clock source.
bogdanm	86:04dd9b1680ae	1046	* @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm	86:04dd9b1680ae	1047	* of the following:
bogdanm	86:04dd9b1680ae	1048	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm	86:04dd9b1680ae	1049	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm	86:04dd9b1680ae	1050	*/
bogdanm	86:04dd9b1680ae	1051	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
bogdanm	86:04dd9b1680ae	1052
bogdanm	86:04dd9b1680ae	1053	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm	86:04dd9b1680ae	1054	* the selected interrupts).
bogdanm	86:04dd9b1680ae	1055	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	86:04dd9b1680ae	1056	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	1057	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	86:04dd9b1680ae	1058	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	86:04dd9b1680ae	1059	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	86:04dd9b1680ae	1060	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	86:04dd9b1680ae	1061	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	86:04dd9b1680ae	1062	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm	86:04dd9b1680ae	1063	*/
bogdanm	86:04dd9b1680ae	1064	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	86:04dd9b1680ae	1065
bogdanm	86:04dd9b1680ae	1066	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm	86:04dd9b1680ae	1067	* the selected interrupts).
bogdanm	86:04dd9b1680ae	1068	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	86:04dd9b1680ae	1069	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	1070	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	86:04dd9b1680ae	1071	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	86:04dd9b1680ae	1072	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	86:04dd9b1680ae	1073	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	86:04dd9b1680ae	1074	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	86:04dd9b1680ae	1075	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm	86:04dd9b1680ae	1076	*/
bogdanm	86:04dd9b1680ae	1077	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm	86:04dd9b1680ae	1078
bogdanm	86:04dd9b1680ae	1079	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm	86:04dd9b1680ae	1080	* bits to clear the selected interrupt pending bits.
bogdanm	86:04dd9b1680ae	1081	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	86:04dd9b1680ae	1082	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	1083	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	86:04dd9b1680ae	1084	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	86:04dd9b1680ae	1085	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	86:04dd9b1680ae	1086	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	86:04dd9b1680ae	1087	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	86:04dd9b1680ae	1088	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm	86:04dd9b1680ae	1089	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	86:04dd9b1680ae	1090	*/
bogdanm	86:04dd9b1680ae	1091	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm	86:04dd9b1680ae	1092
bogdanm	86:04dd9b1680ae	1093	/** @brief Check the RCC's interrupt has occurred or not.
bogdanm	86:04dd9b1680ae	1094	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm	86:04dd9b1680ae	1095	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	1096	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	86:04dd9b1680ae	1097	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	86:04dd9b1680ae	1098	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	86:04dd9b1680ae	1099	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	86:04dd9b1680ae	1100	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	86:04dd9b1680ae	1101	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm	86:04dd9b1680ae	1102	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	86:04dd9b1680ae	1103	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	86:04dd9b1680ae	1104	*/
bogdanm	86:04dd9b1680ae	1105	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	86:04dd9b1680ae	1106
bogdanm	86:04dd9b1680ae	1107	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm	86:04dd9b1680ae	1108	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
bogdanm	86:04dd9b1680ae	1109	*/
bogdanm	86:04dd9b1680ae	1110	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
bogdanm	86:04dd9b1680ae	1111
bogdanm	86:04dd9b1680ae	1112	/** @brief Check RCC flag is set or not.
bogdanm	86:04dd9b1680ae	1113	* @param __FLAG__: specifies the flag to check.
bogdanm	86:04dd9b1680ae	1114	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	1115	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm	86:04dd9b1680ae	1116	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm	86:04dd9b1680ae	1117	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm	86:04dd9b1680ae	1118	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
bogdanm	86:04dd9b1680ae	1119	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm	86:04dd9b1680ae	1120	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm	86:04dd9b1680ae	1121	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
bogdanm	86:04dd9b1680ae	1122	* @arg RCC_FLAG_PINRST: Pin reset.
bogdanm	86:04dd9b1680ae	1123	* @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm	86:04dd9b1680ae	1124	* @arg RCC_FLAG_SFTRST: Software reset.
bogdanm	86:04dd9b1680ae	1125	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm	86:04dd9b1680ae	1126	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm	86:04dd9b1680ae	1127	* @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm	86:04dd9b1680ae	1128	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	86:04dd9b1680ae	1129	*/
bogdanm	86:04dd9b1680ae	1130	#define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm	86:04dd9b1680ae	1131	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
bogdanm	86:04dd9b1680ae	1132
bogdanm	86:04dd9b1680ae	1133	#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
bogdanm	86:04dd9b1680ae	1134
bogdanm	86:04dd9b1680ae	1135
bogdanm	86:04dd9b1680ae	1136	/* Include RCC HAL Extension module */
bogdanm	86:04dd9b1680ae	1137	#include "stm32f4xx_hal_rcc_ex.h"
bogdanm	86:04dd9b1680ae	1138
bogdanm	86:04dd9b1680ae	1139	/* Exported functions --------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	1140
bogdanm	86:04dd9b1680ae	1141	/* Initialization and de-initialization functions ******************************/
bogdanm	86:04dd9b1680ae	1142	void HAL_RCC_DeInit(void);
bogdanm	86:04dd9b1680ae	1143	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	86:04dd9b1680ae	1144	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	86:04dd9b1680ae	1145
bogdanm	86:04dd9b1680ae	1146	/* Peripheral Control functions ************************************************/
bogdanm	86:04dd9b1680ae	1147	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	86:04dd9b1680ae	1148	void HAL_RCC_EnableCSS(void);
bogdanm	86:04dd9b1680ae	1149	void HAL_RCC_DisableCSS(void);
bogdanm	86:04dd9b1680ae	1150	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	86:04dd9b1680ae	1151	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	86:04dd9b1680ae	1152	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	86:04dd9b1680ae	1153	uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm	86:04dd9b1680ae	1154	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	86:04dd9b1680ae	1155	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	86:04dd9b1680ae	1156
bogdanm	86:04dd9b1680ae	1157	/* CSS NMI IRQ handler */
bogdanm	86:04dd9b1680ae	1158	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	86:04dd9b1680ae	1159
bogdanm	86:04dd9b1680ae	1160	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	86:04dd9b1680ae	1161	void HAL_RCC_CCSCallback(void);
bogdanm	86:04dd9b1680ae	1162
bogdanm	86:04dd9b1680ae	1163	/**
bogdanm	86:04dd9b1680ae	1164	* @}
bogdanm	86:04dd9b1680ae	1165	*/
bogdanm	86:04dd9b1680ae	1166
bogdanm	86:04dd9b1680ae	1167	/**
bogdanm	86:04dd9b1680ae	1168	* @}
bogdanm	86:04dd9b1680ae	1169	*/
bogdanm	86:04dd9b1680ae	1170
bogdanm	86:04dd9b1680ae	1171	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	1172	}
bogdanm	86:04dd9b1680ae	1173	#endif
bogdanm	86:04dd9b1680ae	1174
bogdanm	86:04dd9b1680ae	1175	#endif /* __STM32F4xx_HAL_RCC_H */
bogdanm	86:04dd9b1680ae	1176
bogdanm	86:04dd9b1680ae	1177	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
Dependents:	0
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Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc.h@93:9dd889aeda0e, 2014-12-05 (annotated)

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