frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_NUCLEO_F411RE/stm32f4xx_hal_dma.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:
fblanc
Date:
Fri Dec 05 15:42:32 2014 +0000
Revision:
93:9dd889aeda0e
Parent:
86:04dd9b1680ae 
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f4xx_hal_dma.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.1.0
bogdanm 86:04dd9b1680ae 6 * @date 19-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of DMA HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F4xx_HAL_DMA_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F4xx_HAL_DMA_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f4xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup DMA
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59 /**
bogdanm 86:04dd9b1680ae 60 * @brief DMA Configuration Structure definition
bogdanm 86:04dd9b1680ae 61 */
bogdanm 86:04dd9b1680ae 62 typedef struct
bogdanm 86:04dd9b1680ae 63 {
bogdanm 86:04dd9b1680ae 64 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
bogdanm 86:04dd9b1680ae 65 This parameter can be a value of @ref DMA_Channel_selection */
bogdanm 86:04dd9b1680ae 66
bogdanm 86:04dd9b1680ae 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 86:04dd9b1680ae 68 from memory to memory or from peripheral to memory.
bogdanm 86:04dd9b1680ae 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 86:04dd9b1680ae 70
bogdanm 86:04dd9b1680ae 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 86:04dd9b1680ae 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 86:04dd9b1680ae 73
bogdanm 86:04dd9b1680ae 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 86:04dd9b1680ae 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 86:04dd9b1680ae 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 86:04dd9b1680ae 79
bogdanm 86:04dd9b1680ae 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 86:04dd9b1680ae 81 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 86:04dd9b1680ae 82
bogdanm 86:04dd9b1680ae 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
bogdanm 86:04dd9b1680ae 84 This parameter can be a value of @ref DMA_mode
bogdanm 86:04dd9b1680ae 85 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 86:04dd9b1680ae 86 data transfer is configured on the selected Stream */
bogdanm 86:04dd9b1680ae 87
bogdanm 86:04dd9b1680ae 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
bogdanm 86:04dd9b1680ae 89 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 86:04dd9b1680ae 90
bogdanm 86:04dd9b1680ae 91 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
bogdanm 86:04dd9b1680ae 92 This parameter can be a value of @ref DMA_FIFO_direct_mode
bogdanm 86:04dd9b1680ae 93 @note The Direct mode (FIFO mode disabled) cannot be used if the
bogdanm 86:04dd9b1680ae 94 memory-to-memory data transfer is configured on the selected stream */
bogdanm 86:04dd9b1680ae 95
bogdanm 86:04dd9b1680ae 96 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
bogdanm 86:04dd9b1680ae 97 This parameter can be a value of @ref DMA_FIFO_threshold_level */
bogdanm 86:04dd9b1680ae 98
bogdanm 86:04dd9b1680ae 99 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
bogdanm 86:04dd9b1680ae 100 It specifies the amount of data to be transferred in a single non interruptable
bogdanm 86:04dd9b1680ae 101 transaction.
bogdanm 86:04dd9b1680ae 102 This parameter can be a value of @ref DMA_Memory_burst
bogdanm 86:04dd9b1680ae 103 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 86:04dd9b1680ae 104
bogdanm 86:04dd9b1680ae 105 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
bogdanm 86:04dd9b1680ae 106 It specifies the amount of data to be transferred in a single non interruptable
bogdanm 86:04dd9b1680ae 107 transaction.
bogdanm 86:04dd9b1680ae 108 This parameter can be a value of @ref DMA_Peripheral_burst
bogdanm 86:04dd9b1680ae 109 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 86:04dd9b1680ae 110 }DMA_InitTypeDef;
bogdanm 86:04dd9b1680ae 111
bogdanm 86:04dd9b1680ae 112 /**
bogdanm 86:04dd9b1680ae 113 * @brief HAL DMA State structures definition
bogdanm 86:04dd9b1680ae 114 */
bogdanm 86:04dd9b1680ae 115 typedef enum
bogdanm 86:04dd9b1680ae 116 {
bogdanm 86:04dd9b1680ae 117 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 86:04dd9b1680ae 118 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
bogdanm 86:04dd9b1680ae 119 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
bogdanm 86:04dd9b1680ae 120 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
bogdanm 86:04dd9b1680ae 121 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
bogdanm 86:04dd9b1680ae 122 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
bogdanm 86:04dd9b1680ae 123 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 86:04dd9b1680ae 124 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
bogdanm 86:04dd9b1680ae 125 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
bogdanm 86:04dd9b1680ae 126 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 86:04dd9b1680ae 127 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 86:04dd9b1680ae 128 }HAL_DMA_StateTypeDef;
bogdanm 86:04dd9b1680ae 129
bogdanm 86:04dd9b1680ae 130 /**
bogdanm 86:04dd9b1680ae 131 * @brief HAL DMA Error Code structure definition
bogdanm 86:04dd9b1680ae 132 */
bogdanm 86:04dd9b1680ae 133 typedef enum
bogdanm 86:04dd9b1680ae 134 {
bogdanm 86:04dd9b1680ae 135 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 86:04dd9b1680ae 136 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 86:04dd9b1680ae 137 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 86:04dd9b1680ae 138
bogdanm 86:04dd9b1680ae 139 /**
bogdanm 86:04dd9b1680ae 140 * @brief DMA handle Structure definition
bogdanm 86:04dd9b1680ae 141 */
bogdanm 86:04dd9b1680ae 142 typedef struct __DMA_HandleTypeDef
bogdanm 86:04dd9b1680ae 143 {
bogdanm 86:04dd9b1680ae 144 DMA_Stream_TypeDef *Instance; /*!< Register base address */
bogdanm 86:04dd9b1680ae 145
bogdanm 86:04dd9b1680ae 146 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 86:04dd9b1680ae 147
bogdanm 86:04dd9b1680ae 148 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 86:04dd9b1680ae 149
bogdanm 86:04dd9b1680ae 150 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 86:04dd9b1680ae 151
bogdanm 86:04dd9b1680ae 152 void *Parent; /*!< Parent object state */
bogdanm 86:04dd9b1680ae 153
bogdanm 86:04dd9b1680ae 154 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 86:04dd9b1680ae 155
bogdanm 86:04dd9b1680ae 156 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 86:04dd9b1680ae 157
bogdanm 86:04dd9b1680ae 158 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
bogdanm 86:04dd9b1680ae 159
bogdanm 86:04dd9b1680ae 160 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 86:04dd9b1680ae 161
bogdanm 86:04dd9b1680ae 162 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 86:04dd9b1680ae 163 }DMA_HandleTypeDef;
bogdanm 86:04dd9b1680ae 164
bogdanm 86:04dd9b1680ae 165 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 166
bogdanm 86:04dd9b1680ae 167 /** @defgroup DMA_Exported_Constants
bogdanm 86:04dd9b1680ae 168 * @{
bogdanm 86:04dd9b1680ae 169 */
bogdanm 86:04dd9b1680ae 170
bogdanm 86:04dd9b1680ae 171 /** @defgroup DMA_Error_Code
bogdanm 86:04dd9b1680ae 172 * @{
bogdanm 86:04dd9b1680ae 173 */
bogdanm 86:04dd9b1680ae 174 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 86:04dd9b1680ae 175 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 86:04dd9b1680ae 176 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
bogdanm 86:04dd9b1680ae 177 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
bogdanm 86:04dd9b1680ae 178 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 86:04dd9b1680ae 179 /**
bogdanm 86:04dd9b1680ae 180 * @}
bogdanm 86:04dd9b1680ae 181 */
bogdanm 86:04dd9b1680ae 182
bogdanm 86:04dd9b1680ae 183 /** @defgroup DMA_Channel_selection
bogdanm 86:04dd9b1680ae 184 * @{
bogdanm 86:04dd9b1680ae 185 */
bogdanm 86:04dd9b1680ae 186 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
bogdanm 86:04dd9b1680ae 187 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
bogdanm 86:04dd9b1680ae 188 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
bogdanm 86:04dd9b1680ae 189 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
bogdanm 86:04dd9b1680ae 190 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
bogdanm 86:04dd9b1680ae 191 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
bogdanm 86:04dd9b1680ae 192 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
bogdanm 86:04dd9b1680ae 193 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
bogdanm 86:04dd9b1680ae 194
bogdanm 86:04dd9b1680ae 195 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
bogdanm 86:04dd9b1680ae 196 ((CHANNEL) == DMA_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 197 ((CHANNEL) == DMA_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 198 ((CHANNEL) == DMA_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 199 ((CHANNEL) == DMA_CHANNEL_4) || \
bogdanm 86:04dd9b1680ae 200 ((CHANNEL) == DMA_CHANNEL_5) || \
bogdanm 86:04dd9b1680ae 201 ((CHANNEL) == DMA_CHANNEL_6) || \
bogdanm 86:04dd9b1680ae 202 ((CHANNEL) == DMA_CHANNEL_7))
bogdanm 86:04dd9b1680ae 203 /**
bogdanm 86:04dd9b1680ae 204 * @}
bogdanm 86:04dd9b1680ae 205 */
bogdanm 86:04dd9b1680ae 206
bogdanm 86:04dd9b1680ae 207 /** @defgroup DMA_Data_transfer_direction
bogdanm 86:04dd9b1680ae 208 * @{
bogdanm 86:04dd9b1680ae 209 */
bogdanm 86:04dd9b1680ae 210 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 86:04dd9b1680ae 211 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
bogdanm 86:04dd9b1680ae 212 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
bogdanm 86:04dd9b1680ae 213
bogdanm 86:04dd9b1680ae 214 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 86:04dd9b1680ae 215 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 86:04dd9b1680ae 216 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 86:04dd9b1680ae 217 /**
bogdanm 86:04dd9b1680ae 218 * @}
bogdanm 86:04dd9b1680ae 219 */
bogdanm 86:04dd9b1680ae 220
bogdanm 86:04dd9b1680ae 221 /** @defgroup DMA_Data_buffer_size
bogdanm 86:04dd9b1680ae 222 * @{
bogdanm 86:04dd9b1680ae 223 */
bogdanm 86:04dd9b1680ae 224 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 86:04dd9b1680ae 225 /**
bogdanm 86:04dd9b1680ae 226 * @}
bogdanm 86:04dd9b1680ae 227 */
bogdanm 86:04dd9b1680ae 228
bogdanm 86:04dd9b1680ae 229 /** @defgroup DMA_Peripheral_incremented_mode
bogdanm 86:04dd9b1680ae 230 * @{
bogdanm 86:04dd9b1680ae 231 */
bogdanm 86:04dd9b1680ae 232 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
bogdanm 86:04dd9b1680ae 233 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
bogdanm 86:04dd9b1680ae 234
bogdanm 86:04dd9b1680ae 235 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 86:04dd9b1680ae 236 ((STATE) == DMA_PINC_DISABLE))
bogdanm 86:04dd9b1680ae 237 /**
bogdanm 86:04dd9b1680ae 238 * @}
bogdanm 86:04dd9b1680ae 239 */
bogdanm 86:04dd9b1680ae 240
bogdanm 86:04dd9b1680ae 241 /** @defgroup DMA_Memory_incremented_mode
bogdanm 86:04dd9b1680ae 242 * @{
bogdanm 86:04dd9b1680ae 243 */
bogdanm 86:04dd9b1680ae 244 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
bogdanm 86:04dd9b1680ae 245 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
bogdanm 86:04dd9b1680ae 246
bogdanm 86:04dd9b1680ae 247 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 86:04dd9b1680ae 248 ((STATE) == DMA_MINC_DISABLE))
bogdanm 86:04dd9b1680ae 249 /**
bogdanm 86:04dd9b1680ae 250 * @}
bogdanm 86:04dd9b1680ae 251 */
bogdanm 86:04dd9b1680ae 252
bogdanm 86:04dd9b1680ae 253 /** @defgroup DMA_Peripheral_data_size
bogdanm 86:04dd9b1680ae 254 * @{
bogdanm 86:04dd9b1680ae 255 */
bogdanm 86:04dd9b1680ae 256 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
bogdanm 86:04dd9b1680ae 257 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
bogdanm 86:04dd9b1680ae 258 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
bogdanm 86:04dd9b1680ae 259
bogdanm 86:04dd9b1680ae 260 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 86:04dd9b1680ae 261 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 86:04dd9b1680ae 262 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 86:04dd9b1680ae 263 /**
bogdanm 86:04dd9b1680ae 264 * @}
bogdanm 86:04dd9b1680ae 265 */
bogdanm 86:04dd9b1680ae 266
bogdanm 86:04dd9b1680ae 267
bogdanm 86:04dd9b1680ae 268 /** @defgroup DMA_Memory_data_size
bogdanm 86:04dd9b1680ae 269 * @{
bogdanm 86:04dd9b1680ae 270 */
bogdanm 86:04dd9b1680ae 271 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
bogdanm 86:04dd9b1680ae 272 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
bogdanm 86:04dd9b1680ae 273 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
bogdanm 86:04dd9b1680ae 274
bogdanm 86:04dd9b1680ae 275 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 86:04dd9b1680ae 276 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 86:04dd9b1680ae 277 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 86:04dd9b1680ae 278 /**
bogdanm 86:04dd9b1680ae 279 * @}
bogdanm 86:04dd9b1680ae 280 */
bogdanm 86:04dd9b1680ae 281
bogdanm 86:04dd9b1680ae 282 /** @defgroup DMA_mode
bogdanm 86:04dd9b1680ae 283 * @{
bogdanm 86:04dd9b1680ae 284 */
bogdanm 86:04dd9b1680ae 285 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
bogdanm 86:04dd9b1680ae 286 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
bogdanm 86:04dd9b1680ae 287 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
bogdanm 86:04dd9b1680ae 288
bogdanm 86:04dd9b1680ae 289 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 86:04dd9b1680ae 290 ((MODE) == DMA_CIRCULAR) || \
bogdanm 86:04dd9b1680ae 291 ((MODE) == DMA_PFCTRL))
bogdanm 86:04dd9b1680ae 292 /**
bogdanm 86:04dd9b1680ae 293 * @}
bogdanm 86:04dd9b1680ae 294 */
bogdanm 86:04dd9b1680ae 295
bogdanm 86:04dd9b1680ae 296 /** @defgroup DMA_Priority_level
bogdanm 86:04dd9b1680ae 297 * @{
bogdanm 86:04dd9b1680ae 298 */
bogdanm 86:04dd9b1680ae 299 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
bogdanm 86:04dd9b1680ae 300 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
bogdanm 86:04dd9b1680ae 301 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
bogdanm 86:04dd9b1680ae 302 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
bogdanm 86:04dd9b1680ae 303
bogdanm 86:04dd9b1680ae 304 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 86:04dd9b1680ae 305 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 86:04dd9b1680ae 306 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 86:04dd9b1680ae 307 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 86:04dd9b1680ae 308 /**
bogdanm 86:04dd9b1680ae 309 * @}
bogdanm 86:04dd9b1680ae 310 */
bogdanm 86:04dd9b1680ae 311
bogdanm 86:04dd9b1680ae 312 /** @defgroup DMA_FIFO_direct_mode
bogdanm 86:04dd9b1680ae 313 * @{
bogdanm 86:04dd9b1680ae 314 */
bogdanm 86:04dd9b1680ae 315 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
bogdanm 86:04dd9b1680ae 316 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
bogdanm 86:04dd9b1680ae 317
bogdanm 86:04dd9b1680ae 318 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
bogdanm 86:04dd9b1680ae 319 ((STATE) == DMA_FIFOMODE_ENABLE))
bogdanm 86:04dd9b1680ae 320 /**
bogdanm 86:04dd9b1680ae 321 * @}
bogdanm 86:04dd9b1680ae 322 */
bogdanm 86:04dd9b1680ae 323
bogdanm 86:04dd9b1680ae 324 /** @defgroup DMA_FIFO_threshold_level
bogdanm 86:04dd9b1680ae 325 * @{
bogdanm 86:04dd9b1680ae 326 */
bogdanm 86:04dd9b1680ae 327 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
bogdanm 86:04dd9b1680ae 328 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
bogdanm 86:04dd9b1680ae 329 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
bogdanm 86:04dd9b1680ae 330 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
bogdanm 86:04dd9b1680ae 331
bogdanm 86:04dd9b1680ae 332 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
bogdanm 86:04dd9b1680ae 333 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
bogdanm 86:04dd9b1680ae 334 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
bogdanm 86:04dd9b1680ae 335 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
bogdanm 86:04dd9b1680ae 336 /**
bogdanm 86:04dd9b1680ae 337 * @}
bogdanm 86:04dd9b1680ae 338 */
bogdanm 86:04dd9b1680ae 339
bogdanm 86:04dd9b1680ae 340 /** @defgroup DMA_Memory_burst
bogdanm 86:04dd9b1680ae 341 * @{
bogdanm 86:04dd9b1680ae 342 */
bogdanm 86:04dd9b1680ae 343 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 344 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
bogdanm 86:04dd9b1680ae 345 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
bogdanm 86:04dd9b1680ae 346 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
bogdanm 86:04dd9b1680ae 347
bogdanm 86:04dd9b1680ae 348 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
bogdanm 86:04dd9b1680ae 349 ((BURST) == DMA_MBURST_INC4) || \
bogdanm 86:04dd9b1680ae 350 ((BURST) == DMA_MBURST_INC8) || \
bogdanm 86:04dd9b1680ae 351 ((BURST) == DMA_MBURST_INC16))
bogdanm 86:04dd9b1680ae 352 /**
bogdanm 86:04dd9b1680ae 353 * @}
bogdanm 86:04dd9b1680ae 354 */
bogdanm 86:04dd9b1680ae 355
bogdanm 86:04dd9b1680ae 356 /** @defgroup DMA_Peripheral_burst
bogdanm 86:04dd9b1680ae 357 * @{
bogdanm 86:04dd9b1680ae 358 */
bogdanm 86:04dd9b1680ae 359 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 360 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
bogdanm 86:04dd9b1680ae 361 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
bogdanm 86:04dd9b1680ae 362 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
bogdanm 86:04dd9b1680ae 363
bogdanm 86:04dd9b1680ae 364 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
bogdanm 86:04dd9b1680ae 365 ((BURST) == DMA_PBURST_INC4) || \
bogdanm 86:04dd9b1680ae 366 ((BURST) == DMA_PBURST_INC8) || \
bogdanm 86:04dd9b1680ae 367 ((BURST) == DMA_PBURST_INC16))
bogdanm 86:04dd9b1680ae 368 /**
bogdanm 86:04dd9b1680ae 369 * @}
bogdanm 86:04dd9b1680ae 370 */
bogdanm 86:04dd9b1680ae 371
bogdanm 86:04dd9b1680ae 372 /** @defgroup DMA_interrupt_enable_definitions
bogdanm 86:04dd9b1680ae 373 * @{
bogdanm 86:04dd9b1680ae 374 */
bogdanm 86:04dd9b1680ae 375 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
bogdanm 86:04dd9b1680ae 376 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
bogdanm 86:04dd9b1680ae 377 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
bogdanm 86:04dd9b1680ae 378 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
bogdanm 86:04dd9b1680ae 379 #define DMA_IT_FE ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 380 /**
bogdanm 86:04dd9b1680ae 381 * @}
bogdanm 86:04dd9b1680ae 382 */
bogdanm 86:04dd9b1680ae 383
bogdanm 86:04dd9b1680ae 384 /** @defgroup DMA_flag_definitions
bogdanm 86:04dd9b1680ae 385 * @{
bogdanm 86:04dd9b1680ae 386 */
bogdanm 86:04dd9b1680ae 387 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
bogdanm 86:04dd9b1680ae 388 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
bogdanm 86:04dd9b1680ae 389 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 390 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 391 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 392 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 393 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 394 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 395 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 396 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 397 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 398 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 399 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 400 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 401 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 402 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 403 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 404 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 405 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 406 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 407 /**
bogdanm 86:04dd9b1680ae 408 * @}
bogdanm 86:04dd9b1680ae 409 */
bogdanm 86:04dd9b1680ae 410
bogdanm 86:04dd9b1680ae 411 /**
bogdanm 86:04dd9b1680ae 412 * @}
bogdanm 86:04dd9b1680ae 413 */
bogdanm 86:04dd9b1680ae 414
bogdanm 86:04dd9b1680ae 415 /* Exported macro ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 416
bogdanm 86:04dd9b1680ae 417 /** @brief Reset DMA handle state
bogdanm 86:04dd9b1680ae 418 * @param __HANDLE__: specifies the DMA handle.
bogdanm 86:04dd9b1680ae 419 * @retval None
bogdanm 86:04dd9b1680ae 420 */
bogdanm 86:04dd9b1680ae 421 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 86:04dd9b1680ae 422
bogdanm 86:04dd9b1680ae 423 /**
bogdanm 86:04dd9b1680ae 424 * @brief Return the current DMA Stream FIFO filled level.
bogdanm 86:04dd9b1680ae 425 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 426 * @retval The FIFO filling state.
bogdanm 86:04dd9b1680ae 427 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
bogdanm 86:04dd9b1680ae 428 * and not empty.
bogdanm 86:04dd9b1680ae 429 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
bogdanm 86:04dd9b1680ae 430 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
bogdanm 86:04dd9b1680ae 431 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
bogdanm 86:04dd9b1680ae 432 * - DMA_FIFOStatus_Empty: when FIFO is empty
bogdanm 86:04dd9b1680ae 433 * - DMA_FIFOStatus_Full: when FIFO is full
bogdanm 86:04dd9b1680ae 434 */
bogdanm 86:04dd9b1680ae 435 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
bogdanm 86:04dd9b1680ae 436
bogdanm 86:04dd9b1680ae 437 /**
bogdanm 86:04dd9b1680ae 438 * @brief Enable the specified DMA Stream.
bogdanm 86:04dd9b1680ae 439 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 440 * @retval None
bogdanm 86:04dd9b1680ae 441 */
bogdanm 86:04dd9b1680ae 442 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
bogdanm 86:04dd9b1680ae 443
bogdanm 86:04dd9b1680ae 444 /**
bogdanm 86:04dd9b1680ae 445 * @brief Disable the specified DMA Stream.
bogdanm 86:04dd9b1680ae 446 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 447 * @retval None
bogdanm 86:04dd9b1680ae 448 */
bogdanm 86:04dd9b1680ae 449 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
bogdanm 86:04dd9b1680ae 450
bogdanm 86:04dd9b1680ae 451 /* Interrupt & Flag management */
bogdanm 86:04dd9b1680ae 452
bogdanm 86:04dd9b1680ae 453 /**
bogdanm 86:04dd9b1680ae 454 * @brief Return the current DMA Stream transfer complete flag.
bogdanm 86:04dd9b1680ae 455 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 456 * @retval The specified transfer complete flag index.
bogdanm 86:04dd9b1680ae 457 */
bogdanm 86:04dd9b1680ae 458 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 86:04dd9b1680ae 459 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 86:04dd9b1680ae 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 86:04dd9b1680ae 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 86:04dd9b1680ae 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 86:04dd9b1680ae 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 86:04dd9b1680ae 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 86:04dd9b1680ae 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 86:04dd9b1680ae 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 86:04dd9b1680ae 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 86:04dd9b1680ae 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 86:04dd9b1680ae 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 86:04dd9b1680ae 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 86:04dd9b1680ae 471 DMA_FLAG_TCIF3_7)
bogdanm 86:04dd9b1680ae 472
bogdanm 86:04dd9b1680ae 473 /**
bogdanm 86:04dd9b1680ae 474 * @brief Return the current DMA Stream half transfer complete flag.
bogdanm 86:04dd9b1680ae 475 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 476 * @retval The specified half transfer complete flag index.
bogdanm 86:04dd9b1680ae 477 */
bogdanm 86:04dd9b1680ae 478 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 86:04dd9b1680ae 479 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 86:04dd9b1680ae 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 86:04dd9b1680ae 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 86:04dd9b1680ae 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 86:04dd9b1680ae 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 86:04dd9b1680ae 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 86:04dd9b1680ae 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 86:04dd9b1680ae 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 86:04dd9b1680ae 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 86:04dd9b1680ae 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 86:04dd9b1680ae 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 86:04dd9b1680ae 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 86:04dd9b1680ae 491 DMA_FLAG_HTIF3_7)
bogdanm 86:04dd9b1680ae 492
bogdanm 86:04dd9b1680ae 493 /**
bogdanm 86:04dd9b1680ae 494 * @brief Return the current DMA Stream transfer error flag.
bogdanm 86:04dd9b1680ae 495 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 496 * @retval The specified transfer error flag index.
bogdanm 86:04dd9b1680ae 497 */
bogdanm 86:04dd9b1680ae 498 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 86:04dd9b1680ae 499 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 86:04dd9b1680ae 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 86:04dd9b1680ae 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 86:04dd9b1680ae 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 86:04dd9b1680ae 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 86:04dd9b1680ae 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 86:04dd9b1680ae 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 86:04dd9b1680ae 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 86:04dd9b1680ae 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 86:04dd9b1680ae 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 86:04dd9b1680ae 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 86:04dd9b1680ae 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 86:04dd9b1680ae 511 DMA_FLAG_TEIF3_7)
bogdanm 86:04dd9b1680ae 512
bogdanm 86:04dd9b1680ae 513 /**
bogdanm 86:04dd9b1680ae 514 * @brief Return the current DMA Stream FIFO error flag.
bogdanm 86:04dd9b1680ae 515 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 516 * @retval The specified FIFO error flag index.
bogdanm 86:04dd9b1680ae 517 */
bogdanm 86:04dd9b1680ae 518 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
bogdanm 86:04dd9b1680ae 519 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 86:04dd9b1680ae 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 86:04dd9b1680ae 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 86:04dd9b1680ae 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 86:04dd9b1680ae 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 86:04dd9b1680ae 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 86:04dd9b1680ae 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 86:04dd9b1680ae 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 86:04dd9b1680ae 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 86:04dd9b1680ae 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 86:04dd9b1680ae 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 86:04dd9b1680ae 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 86:04dd9b1680ae 531 DMA_FLAG_FEIF3_7)
bogdanm 86:04dd9b1680ae 532
bogdanm 86:04dd9b1680ae 533 /**
bogdanm 86:04dd9b1680ae 534 * @brief Return the current DMA Stream direct mode error flag.
bogdanm 86:04dd9b1680ae 535 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 536 * @retval The specified direct mode error flag index.
bogdanm 86:04dd9b1680ae 537 */
bogdanm 86:04dd9b1680ae 538 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
bogdanm 86:04dd9b1680ae 539 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 86:04dd9b1680ae 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 86:04dd9b1680ae 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 86:04dd9b1680ae 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 86:04dd9b1680ae 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 86:04dd9b1680ae 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 86:04dd9b1680ae 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 86:04dd9b1680ae 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 86:04dd9b1680ae 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 86:04dd9b1680ae 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 86:04dd9b1680ae 549 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 86:04dd9b1680ae 550 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 86:04dd9b1680ae 551 DMA_FLAG_DMEIF3_7)
bogdanm 86:04dd9b1680ae 552
bogdanm 86:04dd9b1680ae 553 /**
bogdanm 86:04dd9b1680ae 554 * @brief Get the DMA Stream pending flags.
bogdanm 86:04dd9b1680ae 555 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 556 * @param __FLAG__: Get the specified flag.
bogdanm 86:04dd9b1680ae 557 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 558 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 86:04dd9b1680ae 559 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 86:04dd9b1680ae 560 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 86:04dd9b1680ae 561 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 86:04dd9b1680ae 562 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 86:04dd9b1680ae 563 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 86:04dd9b1680ae 564 * @retval The state of FLAG (SET or RESET).
bogdanm 86:04dd9b1680ae 565 */
bogdanm 86:04dd9b1680ae 566 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
bogdanm 86:04dd9b1680ae 567 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
bogdanm 86:04dd9b1680ae 568 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
bogdanm 86:04dd9b1680ae 569 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
bogdanm 86:04dd9b1680ae 570
bogdanm 86:04dd9b1680ae 571 /**
bogdanm 86:04dd9b1680ae 572 * @brief Clear the DMA Stream pending flags.
bogdanm 86:04dd9b1680ae 573 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 574 * @param __FLAG__: specifies the flag to clear.
bogdanm 86:04dd9b1680ae 575 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 576 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 86:04dd9b1680ae 577 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 86:04dd9b1680ae 578 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 86:04dd9b1680ae 579 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 86:04dd9b1680ae 580 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 86:04dd9b1680ae 581 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 86:04dd9b1680ae 582 * @retval None
bogdanm 86:04dd9b1680ae 583 */
bogdanm 86:04dd9b1680ae 584 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
bogdanm 86:04dd9b1680ae 585 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
bogdanm 86:04dd9b1680ae 586 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
bogdanm 86:04dd9b1680ae 587 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
bogdanm 86:04dd9b1680ae 588
bogdanm 86:04dd9b1680ae 589 /**
bogdanm 86:04dd9b1680ae 590 * @brief Enable the specified DMA Stream interrupts.
bogdanm 86:04dd9b1680ae 591 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 592 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 86:04dd9b1680ae 593 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 594 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 86:04dd9b1680ae 595 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 86:04dd9b1680ae 596 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 86:04dd9b1680ae 597 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 86:04dd9b1680ae 598 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 86:04dd9b1680ae 599 * @retval None
bogdanm 86:04dd9b1680ae 600 */
bogdanm 86:04dd9b1680ae 601 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 86:04dd9b1680ae 602 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
bogdanm 86:04dd9b1680ae 603
bogdanm 86:04dd9b1680ae 604 /**
bogdanm 86:04dd9b1680ae 605 * @brief Disable the specified DMA Stream interrupts.
bogdanm 86:04dd9b1680ae 606 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 607 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 86:04dd9b1680ae 608 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 609 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 86:04dd9b1680ae 610 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 86:04dd9b1680ae 611 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 86:04dd9b1680ae 612 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 86:04dd9b1680ae 613 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 86:04dd9b1680ae 614 * @retval None
bogdanm 86:04dd9b1680ae 615 */
bogdanm 86:04dd9b1680ae 616 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 86:04dd9b1680ae 617 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
bogdanm 86:04dd9b1680ae 618
bogdanm 86:04dd9b1680ae 619 /**
bogdanm 86:04dd9b1680ae 620 * @brief Check whether the specified DMA Stream interrupt has occurred or not.
bogdanm 86:04dd9b1680ae 621 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 622 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 86:04dd9b1680ae 623 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 624 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 86:04dd9b1680ae 625 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 86:04dd9b1680ae 626 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 86:04dd9b1680ae 627 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 86:04dd9b1680ae 628 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 86:04dd9b1680ae 629 * @retval The state of DMA_IT.
bogdanm 86:04dd9b1680ae 630 */
bogdanm 86:04dd9b1680ae 631 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 86:04dd9b1680ae 632 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
bogdanm 86:04dd9b1680ae 633 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
bogdanm 86:04dd9b1680ae 634
bogdanm 86:04dd9b1680ae 635 /**
bogdanm 86:04dd9b1680ae 636 * @brief Writes the number of data units to be transferred on the DMA Stream.
bogdanm 86:04dd9b1680ae 637 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 638 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
bogdanm 86:04dd9b1680ae 639 * Number of data items depends only on the Peripheral data format.
bogdanm 86:04dd9b1680ae 640 *
bogdanm 86:04dd9b1680ae 641 * @note If Peripheral data format is Bytes: number of data units is equal
bogdanm 86:04dd9b1680ae 642 * to total number of bytes to be transferred.
bogdanm 86:04dd9b1680ae 643 *
bogdanm 86:04dd9b1680ae 644 * @note If Peripheral data format is Half-Word: number of data units is
bogdanm 86:04dd9b1680ae 645 * equal to total number of bytes to be transferred / 2.
bogdanm 86:04dd9b1680ae 646 *
bogdanm 86:04dd9b1680ae 647 * @note If Peripheral data format is Word: number of data units is equal
bogdanm 86:04dd9b1680ae 648 * to total number of bytes to be transferred / 4.
bogdanm 86:04dd9b1680ae 649 *
bogdanm 86:04dd9b1680ae 650 * @retval The number of remaining data units in the current DMAy Streamx transfer.
bogdanm 86:04dd9b1680ae 651 */
bogdanm 86:04dd9b1680ae 652 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
bogdanm 86:04dd9b1680ae 653
bogdanm 86:04dd9b1680ae 654 /**
bogdanm 86:04dd9b1680ae 655 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
bogdanm 86:04dd9b1680ae 656 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 657 *
bogdanm 86:04dd9b1680ae 658 * @retval The number of remaining data units in the current DMA Stream transfer.
bogdanm 86:04dd9b1680ae 659 */
bogdanm 86:04dd9b1680ae 660 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
bogdanm 86:04dd9b1680ae 661
bogdanm 86:04dd9b1680ae 662
bogdanm 86:04dd9b1680ae 663 /* Include DMA HAL Extension module */
bogdanm 86:04dd9b1680ae 664 #include "stm32f4xx_hal_dma_ex.h"
bogdanm 86:04dd9b1680ae 665
bogdanm 86:04dd9b1680ae 666 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 667
bogdanm 86:04dd9b1680ae 668 /* Initialization and de-initialization functions *****************************/
bogdanm 86:04dd9b1680ae 669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 671
bogdanm 86:04dd9b1680ae 672 /* IO operation functions *****************************************************/
bogdanm 86:04dd9b1680ae 673 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 86:04dd9b1680ae 674 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 86:04dd9b1680ae 675 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 676 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 86:04dd9b1680ae 677 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 678
bogdanm 86:04dd9b1680ae 679 /* Peripheral State and Error functions ***************************************/
bogdanm 86:04dd9b1680ae 680 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 681 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 682
bogdanm 86:04dd9b1680ae 683 /**
bogdanm 86:04dd9b1680ae 684 * @}
bogdanm 86:04dd9b1680ae 685 */
bogdanm 86:04dd9b1680ae 686
bogdanm 86:04dd9b1680ae 687 /**
bogdanm 86:04dd9b1680ae 688 * @}
bogdanm 86:04dd9b1680ae 689 */
bogdanm 86:04dd9b1680ae 690
bogdanm 86:04dd9b1680ae 691 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 692 }
bogdanm 86:04dd9b1680ae 693 #endif
bogdanm 86:04dd9b1680ae 694
bogdanm 86:04dd9b1680ae 695 #endif /* __STM32F4xx_HAL_DMA_H */
bogdanm 86:04dd9b1680ae 696
bogdanm 86:04dd9b1680ae 697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/