frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

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TARGET_NUCLEO_F334R8/stm32f3xx_hal_sram.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:
fblanc
Date:
Fri Dec 05 15:42:32 2014 +0000
Revision:
93:9dd889aeda0e
Parent:
92:4fc01daae5a5 
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f3xx_hal_sram.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 12-Sept-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of SRAM HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F3xx_HAL_SRAM_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F3xx_HAL_SRAM_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 48 #include "stm32f3xx_ll_fmc.h"
bogdanm 92:4fc01daae5a5 49 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51
bogdanm 92:4fc01daae5a5 52 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 92:4fc01daae5a5 53 * @{
bogdanm 92:4fc01daae5a5 54 */
bogdanm 92:4fc01daae5a5 55
bogdanm 92:4fc01daae5a5 56 /** @addtogroup SRAM
bogdanm 92:4fc01daae5a5 57 * @{
bogdanm 92:4fc01daae5a5 58 */
bogdanm 92:4fc01daae5a5 59
bogdanm 92:4fc01daae5a5 60 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 61
bogdanm 92:4fc01daae5a5 62 /* Exported typedef ----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 63
bogdanm 92:4fc01daae5a5 64 /** @defgroup SRAM_Exported_Types SRAM Exported Types
bogdanm 92:4fc01daae5a5 65 * @{
bogdanm 92:4fc01daae5a5 66 */
bogdanm 92:4fc01daae5a5 67 /**
bogdanm 92:4fc01daae5a5 68 * @brief HAL SRAM State structures definition
bogdanm 92:4fc01daae5a5 69 */
bogdanm 92:4fc01daae5a5 70 typedef enum
bogdanm 92:4fc01daae5a5 71 {
bogdanm 92:4fc01daae5a5 72 HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 73 HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
bogdanm 92:4fc01daae5a5 74 HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
bogdanm 92:4fc01daae5a5 75 HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
bogdanm 92:4fc01daae5a5 76 HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 }HAL_SRAM_StateTypeDef;
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 /**
bogdanm 92:4fc01daae5a5 81 * @brief SRAM handle Structure definition
bogdanm 92:4fc01daae5a5 82 */
bogdanm 92:4fc01daae5a5 83 typedef struct
bogdanm 92:4fc01daae5a5 84 {
bogdanm 92:4fc01daae5a5 85 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 86
bogdanm 92:4fc01daae5a5 87 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
bogdanm 92:4fc01daae5a5 88
bogdanm 92:4fc01daae5a5 89 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
bogdanm 92:4fc01daae5a5 90
bogdanm 92:4fc01daae5a5 91 HAL_LockTypeDef Lock; /*!< SRAM locking object */
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
bogdanm 92:4fc01daae5a5 96
bogdanm 92:4fc01daae5a5 97 }SRAM_HandleTypeDef;
bogdanm 92:4fc01daae5a5 98
bogdanm 92:4fc01daae5a5 99 /**
bogdanm 92:4fc01daae5a5 100 * @}
bogdanm 92:4fc01daae5a5 101 */
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 104 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 105
bogdanm 92:4fc01daae5a5 106 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
bogdanm 92:4fc01daae5a5 107 * @{
bogdanm 92:4fc01daae5a5 108 */
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110 /** @brief Reset SRAM handle state
bogdanm 92:4fc01daae5a5 111 * @param __HANDLE__: SRAM handle
bogdanm 92:4fc01daae5a5 112 * @retval None
bogdanm 92:4fc01daae5a5 113 */
bogdanm 92:4fc01daae5a5 114 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
bogdanm 92:4fc01daae5a5 115
bogdanm 92:4fc01daae5a5 116 /**
bogdanm 92:4fc01daae5a5 117 * @}
bogdanm 92:4fc01daae5a5 118 */
bogdanm 92:4fc01daae5a5 119
bogdanm 92:4fc01daae5a5 120 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 121 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
bogdanm 92:4fc01daae5a5 122 * @{
bogdanm 92:4fc01daae5a5 123 */
bogdanm 92:4fc01daae5a5 124
bogdanm 92:4fc01daae5a5 125 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 92:4fc01daae5a5 126 * @{
bogdanm 92:4fc01daae5a5 127 */
bogdanm 92:4fc01daae5a5 128
bogdanm 92:4fc01daae5a5 129 /* Initialization/de-initialization functions ********************************/
bogdanm 92:4fc01daae5a5 130 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
bogdanm 92:4fc01daae5a5 131 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
bogdanm 92:4fc01daae5a5 132 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
bogdanm 92:4fc01daae5a5 133 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
bogdanm 92:4fc01daae5a5 134
bogdanm 92:4fc01daae5a5 135 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 136 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 137
bogdanm 92:4fc01daae5a5 138 /**
bogdanm 92:4fc01daae5a5 139 * @}
bogdanm 92:4fc01daae5a5 140 */
bogdanm 92:4fc01daae5a5 141
bogdanm 92:4fc01daae5a5 142 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
bogdanm 92:4fc01daae5a5 143 * @{
bogdanm 92:4fc01daae5a5 144 */
bogdanm 92:4fc01daae5a5 145
bogdanm 92:4fc01daae5a5 146 /* I/O operation functions ***************************************************/
bogdanm 92:4fc01daae5a5 147 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 148 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 149 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 150 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 151 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 152 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 153 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 154 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 155
bogdanm 92:4fc01daae5a5 156 /**
bogdanm 92:4fc01daae5a5 157 * @}
bogdanm 92:4fc01daae5a5 158 */
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
bogdanm 92:4fc01daae5a5 161 * @{
bogdanm 92:4fc01daae5a5 162 */
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 /* SRAM Control functions ****************************************************/
bogdanm 92:4fc01daae5a5 165 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
bogdanm 92:4fc01daae5a5 166 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
bogdanm 92:4fc01daae5a5 167
bogdanm 92:4fc01daae5a5 168 /**
bogdanm 92:4fc01daae5a5 169 * @}
bogdanm 92:4fc01daae5a5 170 */
bogdanm 92:4fc01daae5a5 171
bogdanm 92:4fc01daae5a5 172 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
bogdanm 92:4fc01daae5a5 173 * @{
bogdanm 92:4fc01daae5a5 174 */
bogdanm 92:4fc01daae5a5 175
bogdanm 92:4fc01daae5a5 176 /* SRAM Peripheral State functions ********************************************/
bogdanm 92:4fc01daae5a5 177 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179 /**
bogdanm 92:4fc01daae5a5 180 * @}
bogdanm 92:4fc01daae5a5 181 */
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183 /**
bogdanm 92:4fc01daae5a5 184 * @}
bogdanm 92:4fc01daae5a5 185 */
bogdanm 92:4fc01daae5a5 186
bogdanm 92:4fc01daae5a5 187 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 188 /**
bogdanm 92:4fc01daae5a5 189 * @}
bogdanm 92:4fc01daae5a5 190 */
bogdanm 92:4fc01daae5a5 191
bogdanm 92:4fc01daae5a5 192 /**
bogdanm 92:4fc01daae5a5 193 * @}
bogdanm 92:4fc01daae5a5 194 */
bogdanm 92:4fc01daae5a5 195
bogdanm 92:4fc01daae5a5 196 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 197 }
bogdanm 92:4fc01daae5a5 198 #endif
bogdanm 92:4fc01daae5a5 199
bogdanm 92:4fc01daae5a5 200 #endif /* __STM32F3xx_HAL_SRAM_H */
bogdanm 92:4fc01daae5a5 201
bogdanm 92:4fc01daae5a5 202 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/