frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_NUCLEO_F103RB/stm32f10x.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:
fblanc
Date:
Fri Dec 05 15:42:32 2014 +0000
Revision:
93:9dd889aeda0e
Parent:
84:0b3ab51c8877 
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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bogdanm 73:1efda918f0ba 1 /**
bogdanm 73:1efda918f0ba 2 ******************************************************************************
bogdanm 73:1efda918f0ba 3 * @file stm32f10x.h
bogdanm 73:1efda918f0ba 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V3.6.2
emilmont 77:869cf507173a 6 * @date 28-February-2013
bogdanm 73:1efda918f0ba 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
bogdanm 73:1efda918f0ba 8 * This file contains all the peripheral register's definitions, bits
bogdanm 73:1efda918f0ba 9 * definitions and memory mapping for STM32F10x Connectivity line,
bogdanm 73:1efda918f0ba 10 * High density, High density value line, Medium density,
bogdanm 73:1efda918f0ba 11 * Medium density Value line, Low density, Low density Value line
bogdanm 73:1efda918f0ba 12 * and XL-density devices.
bogdanm 73:1efda918f0ba 13 *
bogdanm 73:1efda918f0ba 14 * The file is the unique include file that the application programmer
bogdanm 73:1efda918f0ba 15 * is using in the C source code, usually in main.c. This file contains:
bogdanm 73:1efda918f0ba 16 * - Configuration section that allows to select:
bogdanm 73:1efda918f0ba 17 * - The device used in the target application
bogdanm 73:1efda918f0ba 18 * - To use or not the peripheral’s drivers in application code(i.e.
bogdanm 73:1efda918f0ba 19 * code will be based on direct access to peripheral’s registers
bogdanm 73:1efda918f0ba 20 * rather than drivers API), this option is controlled by
bogdanm 73:1efda918f0ba 21 * "#define USE_STDPERIPH_DRIVER"
bogdanm 73:1efda918f0ba 22 * - To change few application-specific parameters such as the HSE
bogdanm 73:1efda918f0ba 23 * crystal frequency
bogdanm 73:1efda918f0ba 24 * - Data structures and the address mapping for all peripherals
bogdanm 73:1efda918f0ba 25 * - Peripheral's registers declarations and bits definition
bogdanm 73:1efda918f0ba 26 * - Macros to access peripheral’s registers hardware
bogdanm 73:1efda918f0ba 27 *
bogdanm 76:824293ae5e43 28 *******************************************************************************
bogdanm 76:824293ae5e43 29 * Copyright (c) 2014, STMicroelectronics
bogdanm 76:824293ae5e43 30 * All rights reserved.
bogdanm 76:824293ae5e43 31 *
bogdanm 76:824293ae5e43 32 * Redistribution and use in source and binary forms, with or without
bogdanm 76:824293ae5e43 33 * modification, are permitted provided that the following conditions are met:
bogdanm 76:824293ae5e43 34 *
bogdanm 76:824293ae5e43 35 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 76:824293ae5e43 36 * this list of conditions and the following disclaimer.
bogdanm 76:824293ae5e43 37 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 76:824293ae5e43 38 * this list of conditions and the following disclaimer in the documentation
bogdanm 76:824293ae5e43 39 * and/or other materials provided with the distribution.
bogdanm 76:824293ae5e43 40 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 76:824293ae5e43 41 * may be used to endorse or promote products derived from this software
bogdanm 76:824293ae5e43 42 * without specific prior written permission.
bogdanm 76:824293ae5e43 43 *
bogdanm 76:824293ae5e43 44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 76:824293ae5e43 45 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 76:824293ae5e43 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 76:824293ae5e43 47 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 76:824293ae5e43 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 76:824293ae5e43 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 76:824293ae5e43 50 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 76:824293ae5e43 51 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 76:824293ae5e43 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 76:824293ae5e43 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 76:824293ae5e43 54 *******************************************************************************
bogdanm 76:824293ae5e43 55 */
bogdanm 73:1efda918f0ba 56
bogdanm 73:1efda918f0ba 57 /** @addtogroup CMSIS
bogdanm 73:1efda918f0ba 58 * @{
bogdanm 73:1efda918f0ba 59 */
bogdanm 73:1efda918f0ba 60
bogdanm 73:1efda918f0ba 61 /** @addtogroup stm32f10x
bogdanm 73:1efda918f0ba 62 * @{
bogdanm 73:1efda918f0ba 63 */
bogdanm 73:1efda918f0ba 64
bogdanm 73:1efda918f0ba 65 #ifndef __STM32F10x_H
bogdanm 73:1efda918f0ba 66 #define __STM32F10x_H
bogdanm 73:1efda918f0ba 67
bogdanm 73:1efda918f0ba 68 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 69 extern "C" {
emilmont 77:869cf507173a 70 #endif /* __cplusplus */
bogdanm 73:1efda918f0ba 71
bogdanm 73:1efda918f0ba 72 /** @addtogroup Library_configuration_section
bogdanm 73:1efda918f0ba 73 * @{
bogdanm 73:1efda918f0ba 74 */
bogdanm 73:1efda918f0ba 75
bogdanm 73:1efda918f0ba 76 /* Uncomment the line below according to the target STM32 device used in your
bogdanm 73:1efda918f0ba 77 application
bogdanm 73:1efda918f0ba 78 */
bogdanm 73:1efda918f0ba 79
bogdanm 73:1efda918f0ba 80 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
bogdanm 73:1efda918f0ba 81 /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
emilmont 77:869cf507173a 82 /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
emilmont 77:869cf507173a 83 #define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */
emilmont 77:869cf507173a 84 /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
bogdanm 73:1efda918f0ba 85 /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
emilmont 77:869cf507173a 86 /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
bogdanm 73:1efda918f0ba 87 /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */
bogdanm 73:1efda918f0ba 88 /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
bogdanm 73:1efda918f0ba 89 #endif
bogdanm 73:1efda918f0ba 90 /* Tip: To avoid modifying this file each time you need to switch between these
bogdanm 73:1efda918f0ba 91 devices, you can define the device in your toolchain compiler preprocessor.
bogdanm 73:1efda918f0ba 92
bogdanm 73:1efda918f0ba 93 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
bogdanm 73:1efda918f0ba 94 where the Flash memory density ranges between 16 and 32 Kbytes.
bogdanm 73:1efda918f0ba 95 - Low-density value line devices are STM32F100xx microcontrollers where the Flash
bogdanm 73:1efda918f0ba 96 memory density ranges between 16 and 32 Kbytes.
bogdanm 73:1efda918f0ba 97 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
bogdanm 73:1efda918f0ba 98 where the Flash memory density ranges between 64 and 128 Kbytes.
bogdanm 73:1efda918f0ba 99 - Medium-density value line devices are STM32F100xx microcontrollers where the
bogdanm 73:1efda918f0ba 100 Flash memory density ranges between 64 and 128 Kbytes.
bogdanm 73:1efda918f0ba 101 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
bogdanm 73:1efda918f0ba 102 the Flash memory density ranges between 256 and 512 Kbytes.
bogdanm 73:1efda918f0ba 103 - High-density value line devices are STM32F100xx microcontrollers where the
bogdanm 73:1efda918f0ba 104 Flash memory density ranges between 256 and 512 Kbytes.
bogdanm 73:1efda918f0ba 105 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
bogdanm 73:1efda918f0ba 106 the Flash memory density ranges between 512 and 1024 Kbytes.
bogdanm 73:1efda918f0ba 107 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
bogdanm 73:1efda918f0ba 108 */
bogdanm 73:1efda918f0ba 109
bogdanm 73:1efda918f0ba 110 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
bogdanm 73:1efda918f0ba 111 #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
bogdanm 73:1efda918f0ba 112 #endif
bogdanm 73:1efda918f0ba 113
emilmont 77:869cf507173a 114 #if !defined (USE_STDPERIPH_DRIVER)
bogdanm 73:1efda918f0ba 115 /**
bogdanm 73:1efda918f0ba 116 * @brief Comment the line below if you will not use the peripherals drivers.
bogdanm 73:1efda918f0ba 117 In this case, these drivers will not be included and the application code will
bogdanm 73:1efda918f0ba 118 be based on direct access to peripherals registers
bogdanm 73:1efda918f0ba 119 */
bogdanm 73:1efda918f0ba 120 #define USE_STDPERIPH_DRIVER
emilmont 77:869cf507173a 121 #endif /* USE_STDPERIPH_DRIVER */
bogdanm 73:1efda918f0ba 122
bogdanm 73:1efda918f0ba 123 /**
bogdanm 73:1efda918f0ba 124 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
bogdanm 73:1efda918f0ba 125 used in your application
bogdanm 73:1efda918f0ba 126
bogdanm 73:1efda918f0ba 127 Tip: To avoid modifying this file each time you need to use different HSE, you
bogdanm 73:1efda918f0ba 128 can define the HSE value in your toolchain compiler preprocessor.
bogdanm 73:1efda918f0ba 129 */
bogdanm 73:1efda918f0ba 130 #if !defined HSE_VALUE
bogdanm 73:1efda918f0ba 131 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 132 #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
bogdanm 73:1efda918f0ba 133 #else
bogdanm 73:1efda918f0ba 134 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
bogdanm 73:1efda918f0ba 135 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 136 #endif /* HSE_VALUE */
bogdanm 73:1efda918f0ba 137
bogdanm 73:1efda918f0ba 138 /**
bogdanm 73:1efda918f0ba 139 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
bogdanm 73:1efda918f0ba 140 Timeout value
bogdanm 73:1efda918f0ba 141 */
emilmont 77:869cf507173a 142 #if !defined (HSE_STARTUP_TIMEOUT)
emilmont 77:869cf507173a 143 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
emilmont 77:869cf507173a 144 #endif /* HSE_STARTUP_TIMEOUT */
emilmont 77:869cf507173a 145
emilmont 77:869cf507173a 146 #if !defined (HSI_VALUE)
emilmont 77:869cf507173a 147 #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
emilmont 77:869cf507173a 148 #endif /* HSI_VALUE */
bogdanm 73:1efda918f0ba 149
bogdanm 84:0b3ab51c8877 150 #if !defined (LSE_VALUE)
bogdanm 84:0b3ab51c8877 151 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
bogdanm 84:0b3ab51c8877 152 #endif
bogdanm 84:0b3ab51c8877 153
bogdanm 73:1efda918f0ba 154 /**
bogdanm 73:1efda918f0ba 155 * @brief STM32F10x Standard Peripheral Library version number
bogdanm 73:1efda918f0ba 156 */
emilmont 77:869cf507173a 157 #define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
emilmont 77:869cf507173a 158 #define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
emilmont 77:869cf507173a 159 #define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
emilmont 77:869cf507173a 160 #define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
emilmont 77:869cf507173a 161 #define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
bogdanm 73:1efda918f0ba 162 |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
bogdanm 73:1efda918f0ba 163 |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
bogdanm 73:1efda918f0ba 164 |(__STM32F10X_STDPERIPH_VERSION_RC))
bogdanm 73:1efda918f0ba 165
bogdanm 73:1efda918f0ba 166 /**
bogdanm 73:1efda918f0ba 167 * @}
bogdanm 73:1efda918f0ba 168 */
bogdanm 73:1efda918f0ba 169
bogdanm 73:1efda918f0ba 170 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 73:1efda918f0ba 171 * @{
bogdanm 73:1efda918f0ba 172 */
bogdanm 73:1efda918f0ba 173
bogdanm 73:1efda918f0ba 174 /**
bogdanm 73:1efda918f0ba 175 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
bogdanm 73:1efda918f0ba 176 */
bogdanm 73:1efda918f0ba 177 #ifdef STM32F10X_XL
emilmont 77:869cf507173a 178 #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
bogdanm 73:1efda918f0ba 179 #else
emilmont 77:869cf507173a 180 #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
bogdanm 73:1efda918f0ba 181 #endif /* STM32F10X_XL */
emilmont 77:869cf507173a 182 #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
emilmont 77:869cf507173a 183 #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
emilmont 77:869cf507173a 184 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 73:1efda918f0ba 185
bogdanm 73:1efda918f0ba 186 /**
bogdanm 73:1efda918f0ba 187 * @brief STM32F10x Interrupt Number Definition, according to the selected device
bogdanm 73:1efda918f0ba 188 * in @ref Library_configuration_section
bogdanm 73:1efda918f0ba 189 */
bogdanm 73:1efda918f0ba 190 typedef enum IRQn
bogdanm 73:1efda918f0ba 191 {
bogdanm 73:1efda918f0ba 192 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
bogdanm 73:1efda918f0ba 193 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 73:1efda918f0ba 194 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
bogdanm 73:1efda918f0ba 195 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
bogdanm 73:1efda918f0ba 196 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
bogdanm 73:1efda918f0ba 197 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
bogdanm 73:1efda918f0ba 198 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
bogdanm 73:1efda918f0ba 199 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
bogdanm 73:1efda918f0ba 200 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
bogdanm 73:1efda918f0ba 201
bogdanm 73:1efda918f0ba 202 /****** STM32 specific Interrupt Numbers *********************************************************/
bogdanm 73:1efda918f0ba 203 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 73:1efda918f0ba 204 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 73:1efda918f0ba 205 TAMPER_IRQn = 2, /*!< Tamper Interrupt */
bogdanm 73:1efda918f0ba 206 RTC_IRQn = 3, /*!< RTC global Interrupt */
bogdanm 73:1efda918f0ba 207 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 73:1efda918f0ba 208 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 73:1efda918f0ba 209 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 73:1efda918f0ba 210 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 73:1efda918f0ba 211 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
bogdanm 73:1efda918f0ba 212 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 73:1efda918f0ba 213 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 73:1efda918f0ba 214 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
bogdanm 73:1efda918f0ba 215 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
bogdanm 73:1efda918f0ba 216 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
bogdanm 73:1efda918f0ba 217 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
bogdanm 73:1efda918f0ba 218 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
bogdanm 73:1efda918f0ba 219 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
bogdanm 73:1efda918f0ba 220 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
bogdanm 73:1efda918f0ba 221
bogdanm 73:1efda918f0ba 222 #ifdef STM32F10X_LD
bogdanm 73:1efda918f0ba 223 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
bogdanm 73:1efda918f0ba 224 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
bogdanm 73:1efda918f0ba 225 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
bogdanm 73:1efda918f0ba 226 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 73:1efda918f0ba 227 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 73:1efda918f0ba 228 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 73:1efda918f0ba 229 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
bogdanm 73:1efda918f0ba 230 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
bogdanm 73:1efda918f0ba 231 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
bogdanm 73:1efda918f0ba 232 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 233 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 73:1efda918f0ba 234 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 73:1efda918f0ba 235 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 73:1efda918f0ba 236 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 73:1efda918f0ba 237 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 73:1efda918f0ba 238 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 73:1efda918f0ba 239 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 73:1efda918f0ba 240 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 73:1efda918f0ba 241 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
emilmont 77:869cf507173a 242 USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 243 #endif /* STM32F10X_LD */
bogdanm 73:1efda918f0ba 244
bogdanm 73:1efda918f0ba 245 #ifdef STM32F10X_LD_VL
bogdanm 73:1efda918f0ba 246 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
bogdanm 73:1efda918f0ba 247 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 73:1efda918f0ba 248 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
bogdanm 73:1efda918f0ba 249 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
bogdanm 73:1efda918f0ba 250 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
bogdanm 73:1efda918f0ba 251 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 252 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 73:1efda918f0ba 253 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 73:1efda918f0ba 254 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 73:1efda918f0ba 255 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 73:1efda918f0ba 256 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 73:1efda918f0ba 257 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 73:1efda918f0ba 258 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 73:1efda918f0ba 259 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 73:1efda918f0ba 260 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 261 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
bogdanm 73:1efda918f0ba 262 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
emilmont 77:869cf507173a 263 TIM7_IRQn = 55 /*!< TIM7 Interrupt */
bogdanm 73:1efda918f0ba 264 #endif /* STM32F10X_LD_VL */
bogdanm 73:1efda918f0ba 265
bogdanm 73:1efda918f0ba 266 #ifdef STM32F10X_MD
bogdanm 73:1efda918f0ba 267 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
bogdanm 73:1efda918f0ba 268 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
bogdanm 73:1efda918f0ba 269 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
bogdanm 73:1efda918f0ba 270 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 73:1efda918f0ba 271 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 73:1efda918f0ba 272 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 73:1efda918f0ba 273 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
bogdanm 73:1efda918f0ba 274 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
bogdanm 73:1efda918f0ba 275 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
bogdanm 73:1efda918f0ba 276 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 277 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 73:1efda918f0ba 278 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 73:1efda918f0ba 279 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 73:1efda918f0ba 280 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 73:1efda918f0ba 281 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 73:1efda918f0ba 282 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 73:1efda918f0ba 283 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 73:1efda918f0ba 284 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 73:1efda918f0ba 285 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 73:1efda918f0ba 286 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 73:1efda918f0ba 287 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 73:1efda918f0ba 288 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 73:1efda918f0ba 289 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 73:1efda918f0ba 290 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
emilmont 77:869cf507173a 291 USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 292 #endif /* STM32F10X_MD */
bogdanm 73:1efda918f0ba 293
bogdanm 73:1efda918f0ba 294 #ifdef STM32F10X_MD_VL
bogdanm 73:1efda918f0ba 295 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
bogdanm 73:1efda918f0ba 296 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 73:1efda918f0ba 297 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
bogdanm 73:1efda918f0ba 298 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
bogdanm 73:1efda918f0ba 299 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
bogdanm 73:1efda918f0ba 300 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 301 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 73:1efda918f0ba 302 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 73:1efda918f0ba 303 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 73:1efda918f0ba 304 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 73:1efda918f0ba 305 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 73:1efda918f0ba 306 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 73:1efda918f0ba 307 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 73:1efda918f0ba 308 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 73:1efda918f0ba 309 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 73:1efda918f0ba 310 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 73:1efda918f0ba 311 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 73:1efda918f0ba 312 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 73:1efda918f0ba 313 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 73:1efda918f0ba 314 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 315 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
bogdanm 73:1efda918f0ba 316 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
emilmont 77:869cf507173a 317 TIM7_IRQn = 55 /*!< TIM7 Interrupt */
bogdanm 73:1efda918f0ba 318 #endif /* STM32F10X_MD_VL */
bogdanm 73:1efda918f0ba 319
bogdanm 73:1efda918f0ba 320 #ifdef STM32F10X_HD
bogdanm 73:1efda918f0ba 321 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
bogdanm 73:1efda918f0ba 322 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
bogdanm 73:1efda918f0ba 323 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
bogdanm 73:1efda918f0ba 324 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 73:1efda918f0ba 325 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 73:1efda918f0ba 326 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 73:1efda918f0ba 327 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
bogdanm 73:1efda918f0ba 328 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
bogdanm 73:1efda918f0ba 329 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
bogdanm 73:1efda918f0ba 330 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 331 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 73:1efda918f0ba 332 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 73:1efda918f0ba 333 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 73:1efda918f0ba 334 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 73:1efda918f0ba 335 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 73:1efda918f0ba 336 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 73:1efda918f0ba 337 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 73:1efda918f0ba 338 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 73:1efda918f0ba 339 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 73:1efda918f0ba 340 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 73:1efda918f0ba 341 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 73:1efda918f0ba 342 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 73:1efda918f0ba 343 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 73:1efda918f0ba 344 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 345 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 346 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
bogdanm 73:1efda918f0ba 347 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
bogdanm 73:1efda918f0ba 348 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
bogdanm 73:1efda918f0ba 349 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 350 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
bogdanm 73:1efda918f0ba 351 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
bogdanm 73:1efda918f0ba 352 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
bogdanm 73:1efda918f0ba 353 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 73:1efda918f0ba 354 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 73:1efda918f0ba 355 UART4_IRQn = 52, /*!< UART4 global Interrupt */
bogdanm 73:1efda918f0ba 356 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 73:1efda918f0ba 357 TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
bogdanm 73:1efda918f0ba 358 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
bogdanm 73:1efda918f0ba 359 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
bogdanm 73:1efda918f0ba 360 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
bogdanm 73:1efda918f0ba 361 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
bogdanm 73:1efda918f0ba 362 DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
bogdanm 73:1efda918f0ba 363 #endif /* STM32F10X_HD */
bogdanm 73:1efda918f0ba 364
bogdanm 73:1efda918f0ba 365 #ifdef STM32F10X_HD_VL
bogdanm 73:1efda918f0ba 366 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
bogdanm 73:1efda918f0ba 367 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 73:1efda918f0ba 368 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
bogdanm 73:1efda918f0ba 369 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
bogdanm 73:1efda918f0ba 370 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
bogdanm 73:1efda918f0ba 371 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 372 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 73:1efda918f0ba 373 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 73:1efda918f0ba 374 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 73:1efda918f0ba 375 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 73:1efda918f0ba 376 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 73:1efda918f0ba 377 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 73:1efda918f0ba 378 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 73:1efda918f0ba 379 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 73:1efda918f0ba 380 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 73:1efda918f0ba 381 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 73:1efda918f0ba 382 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 73:1efda918f0ba 383 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 73:1efda918f0ba 384 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 73:1efda918f0ba 385 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 386 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
bogdanm 73:1efda918f0ba 387 TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
bogdanm 73:1efda918f0ba 388 TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
bogdanm 73:1efda918f0ba 389 TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
bogdanm 73:1efda918f0ba 390 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 73:1efda918f0ba 391 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 73:1efda918f0ba 392 UART4_IRQn = 52, /*!< UART4 global Interrupt */
emilmont 77:869cf507173a 393 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 73:1efda918f0ba 394 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
emilmont 77:869cf507173a 395 TIM7_IRQn = 55, /*!< TIM7 Interrupt */
bogdanm 73:1efda918f0ba 396 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
bogdanm 73:1efda918f0ba 397 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
bogdanm 73:1efda918f0ba 398 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
bogdanm 73:1efda918f0ba 399 DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
bogdanm 73:1efda918f0ba 400 DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
bogdanm 73:1efda918f0ba 401 mapped at position 60 only if the MISC_REMAP bit in
emilmont 77:869cf507173a 402 the AFIO_MAPR2 register is set) */
bogdanm 73:1efda918f0ba 403 #endif /* STM32F10X_HD_VL */
bogdanm 73:1efda918f0ba 404
bogdanm 73:1efda918f0ba 405 #ifdef STM32F10X_XL
bogdanm 73:1efda918f0ba 406 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
bogdanm 73:1efda918f0ba 407 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
bogdanm 73:1efda918f0ba 408 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
bogdanm 73:1efda918f0ba 409 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 73:1efda918f0ba 410 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 73:1efda918f0ba 411 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 73:1efda918f0ba 412 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */
bogdanm 73:1efda918f0ba 413 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */
bogdanm 73:1efda918f0ba 414 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
bogdanm 73:1efda918f0ba 415 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 416 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 73:1efda918f0ba 417 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 73:1efda918f0ba 418 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 73:1efda918f0ba 419 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 73:1efda918f0ba 420 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 73:1efda918f0ba 421 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 73:1efda918f0ba 422 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 73:1efda918f0ba 423 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 73:1efda918f0ba 424 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 73:1efda918f0ba 425 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 73:1efda918f0ba 426 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 73:1efda918f0ba 427 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 73:1efda918f0ba 428 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 73:1efda918f0ba 429 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 430 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 431 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */
bogdanm 73:1efda918f0ba 432 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */
bogdanm 73:1efda918f0ba 433 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
bogdanm 73:1efda918f0ba 434 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 435 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
bogdanm 73:1efda918f0ba 436 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
bogdanm 73:1efda918f0ba 437 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
bogdanm 73:1efda918f0ba 438 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 73:1efda918f0ba 439 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 73:1efda918f0ba 440 UART4_IRQn = 52, /*!< UART4 global Interrupt */
bogdanm 73:1efda918f0ba 441 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 73:1efda918f0ba 442 TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
bogdanm 73:1efda918f0ba 443 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
bogdanm 73:1efda918f0ba 444 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
bogdanm 73:1efda918f0ba 445 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
bogdanm 73:1efda918f0ba 446 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
bogdanm 73:1efda918f0ba 447 DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
bogdanm 73:1efda918f0ba 448 #endif /* STM32F10X_XL */
bogdanm 73:1efda918f0ba 449
bogdanm 73:1efda918f0ba 450 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 451 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
bogdanm 73:1efda918f0ba 452 CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
bogdanm 73:1efda918f0ba 453 CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
bogdanm 73:1efda918f0ba 454 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 73:1efda918f0ba 455 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 73:1efda918f0ba 456 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 73:1efda918f0ba 457 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
bogdanm 73:1efda918f0ba 458 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
bogdanm 73:1efda918f0ba 459 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
bogdanm 73:1efda918f0ba 460 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 73:1efda918f0ba 461 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 73:1efda918f0ba 462 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 73:1efda918f0ba 463 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 73:1efda918f0ba 464 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 73:1efda918f0ba 465 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 73:1efda918f0ba 466 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 73:1efda918f0ba 467 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 73:1efda918f0ba 468 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 73:1efda918f0ba 469 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 73:1efda918f0ba 470 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 73:1efda918f0ba 471 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 73:1efda918f0ba 472 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 73:1efda918f0ba 473 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 73:1efda918f0ba 474 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 475 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
bogdanm 73:1efda918f0ba 476 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 73:1efda918f0ba 477 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 73:1efda918f0ba 478 UART4_IRQn = 52, /*!< UART4 global Interrupt */
bogdanm 73:1efda918f0ba 479 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 73:1efda918f0ba 480 TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
bogdanm 73:1efda918f0ba 481 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
bogdanm 73:1efda918f0ba 482 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
bogdanm 73:1efda918f0ba 483 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
bogdanm 73:1efda918f0ba 484 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
bogdanm 73:1efda918f0ba 485 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
bogdanm 73:1efda918f0ba 486 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
bogdanm 73:1efda918f0ba 487 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
bogdanm 73:1efda918f0ba 488 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
bogdanm 73:1efda918f0ba 489 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
bogdanm 73:1efda918f0ba 490 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
bogdanm 73:1efda918f0ba 491 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
bogdanm 73:1efda918f0ba 492 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
bogdanm 73:1efda918f0ba 493 OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
emilmont 77:869cf507173a 494 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 495 } IRQn_Type;
bogdanm 73:1efda918f0ba 496
bogdanm 73:1efda918f0ba 497 /**
bogdanm 73:1efda918f0ba 498 * @}
bogdanm 73:1efda918f0ba 499 */
bogdanm 73:1efda918f0ba 500
bogdanm 73:1efda918f0ba 501 #include "core_cm3.h"
bogdanm 73:1efda918f0ba 502 #include "system_stm32f10x.h"
bogdanm 73:1efda918f0ba 503 #include <stdint.h>
bogdanm 73:1efda918f0ba 504
bogdanm 73:1efda918f0ba 505 /** @addtogroup Exported_types
bogdanm 73:1efda918f0ba 506 * @{
bogdanm 73:1efda918f0ba 507 */
bogdanm 73:1efda918f0ba 508
bogdanm 73:1efda918f0ba 509 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
bogdanm 73:1efda918f0ba 510 typedef int32_t s32;
bogdanm 73:1efda918f0ba 511 typedef int16_t s16;
bogdanm 73:1efda918f0ba 512 typedef int8_t s8;
bogdanm 73:1efda918f0ba 513
bogdanm 73:1efda918f0ba 514 typedef const int32_t sc32; /*!< Read Only */
bogdanm 73:1efda918f0ba 515 typedef const int16_t sc16; /*!< Read Only */
bogdanm 73:1efda918f0ba 516 typedef const int8_t sc8; /*!< Read Only */
bogdanm 73:1efda918f0ba 517
bogdanm 73:1efda918f0ba 518 typedef __IO int32_t vs32;
bogdanm 73:1efda918f0ba 519 typedef __IO int16_t vs16;
bogdanm 73:1efda918f0ba 520 typedef __IO int8_t vs8;
bogdanm 73:1efda918f0ba 521
bogdanm 73:1efda918f0ba 522 typedef __I int32_t vsc32; /*!< Read Only */
bogdanm 73:1efda918f0ba 523 typedef __I int16_t vsc16; /*!< Read Only */
bogdanm 73:1efda918f0ba 524 typedef __I int8_t vsc8; /*!< Read Only */
bogdanm 73:1efda918f0ba 525
bogdanm 73:1efda918f0ba 526 typedef uint32_t u32;
bogdanm 73:1efda918f0ba 527 typedef uint16_t u16;
bogdanm 73:1efda918f0ba 528 typedef uint8_t u8;
bogdanm 73:1efda918f0ba 529
bogdanm 73:1efda918f0ba 530 typedef const uint32_t uc32; /*!< Read Only */
bogdanm 73:1efda918f0ba 531 typedef const uint16_t uc16; /*!< Read Only */
bogdanm 73:1efda918f0ba 532 typedef const uint8_t uc8; /*!< Read Only */
bogdanm 73:1efda918f0ba 533
bogdanm 73:1efda918f0ba 534 typedef __IO uint32_t vu32;
bogdanm 73:1efda918f0ba 535 typedef __IO uint16_t vu16;
bogdanm 73:1efda918f0ba 536 typedef __IO uint8_t vu8;
bogdanm 73:1efda918f0ba 537
bogdanm 73:1efda918f0ba 538 typedef __I uint32_t vuc32; /*!< Read Only */
bogdanm 73:1efda918f0ba 539 typedef __I uint16_t vuc16; /*!< Read Only */
bogdanm 73:1efda918f0ba 540 typedef __I uint8_t vuc8; /*!< Read Only */
bogdanm 73:1efda918f0ba 541
bogdanm 73:1efda918f0ba 542 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
bogdanm 73:1efda918f0ba 543
bogdanm 73:1efda918f0ba 544 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
bogdanm 73:1efda918f0ba 545 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
bogdanm 73:1efda918f0ba 546
bogdanm 73:1efda918f0ba 547 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
bogdanm 73:1efda918f0ba 548
bogdanm 73:1efda918f0ba 549 /*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
bogdanm 73:1efda918f0ba 550 #define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
bogdanm 73:1efda918f0ba 551 #define HSE_Value HSE_VALUE
bogdanm 73:1efda918f0ba 552 #define HSI_Value HSI_VALUE
bogdanm 73:1efda918f0ba 553 /**
bogdanm 73:1efda918f0ba 554 * @}
bogdanm 73:1efda918f0ba 555 */
bogdanm 73:1efda918f0ba 556
bogdanm 73:1efda918f0ba 557 /** @addtogroup Peripheral_registers_structures
bogdanm 73:1efda918f0ba 558 * @{
bogdanm 73:1efda918f0ba 559 */
bogdanm 73:1efda918f0ba 560
bogdanm 73:1efda918f0ba 561 /**
bogdanm 73:1efda918f0ba 562 * @brief Analog to Digital Converter
bogdanm 73:1efda918f0ba 563 */
bogdanm 73:1efda918f0ba 564
bogdanm 73:1efda918f0ba 565 typedef struct
bogdanm 73:1efda918f0ba 566 {
bogdanm 73:1efda918f0ba 567 __IO uint32_t SR;
bogdanm 73:1efda918f0ba 568 __IO uint32_t CR1;
bogdanm 73:1efda918f0ba 569 __IO uint32_t CR2;
bogdanm 73:1efda918f0ba 570 __IO uint32_t SMPR1;
bogdanm 73:1efda918f0ba 571 __IO uint32_t SMPR2;
bogdanm 73:1efda918f0ba 572 __IO uint32_t JOFR1;
bogdanm 73:1efda918f0ba 573 __IO uint32_t JOFR2;
bogdanm 73:1efda918f0ba 574 __IO uint32_t JOFR3;
bogdanm 73:1efda918f0ba 575 __IO uint32_t JOFR4;
bogdanm 73:1efda918f0ba 576 __IO uint32_t HTR;
bogdanm 73:1efda918f0ba 577 __IO uint32_t LTR;
bogdanm 73:1efda918f0ba 578 __IO uint32_t SQR1;
bogdanm 73:1efda918f0ba 579 __IO uint32_t SQR2;
bogdanm 73:1efda918f0ba 580 __IO uint32_t SQR3;
bogdanm 73:1efda918f0ba 581 __IO uint32_t JSQR;
bogdanm 73:1efda918f0ba 582 __IO uint32_t JDR1;
bogdanm 73:1efda918f0ba 583 __IO uint32_t JDR2;
bogdanm 73:1efda918f0ba 584 __IO uint32_t JDR3;
bogdanm 73:1efda918f0ba 585 __IO uint32_t JDR4;
bogdanm 73:1efda918f0ba 586 __IO uint32_t DR;
bogdanm 73:1efda918f0ba 587 } ADC_TypeDef;
bogdanm 73:1efda918f0ba 588
bogdanm 73:1efda918f0ba 589 /**
bogdanm 73:1efda918f0ba 590 * @brief Backup Registers
bogdanm 73:1efda918f0ba 591 */
bogdanm 73:1efda918f0ba 592
bogdanm 73:1efda918f0ba 593 typedef struct
bogdanm 73:1efda918f0ba 594 {
bogdanm 73:1efda918f0ba 595 uint32_t RESERVED0;
bogdanm 73:1efda918f0ba 596 __IO uint16_t DR1;
bogdanm 73:1efda918f0ba 597 uint16_t RESERVED1;
bogdanm 73:1efda918f0ba 598 __IO uint16_t DR2;
bogdanm 73:1efda918f0ba 599 uint16_t RESERVED2;
bogdanm 73:1efda918f0ba 600 __IO uint16_t DR3;
bogdanm 73:1efda918f0ba 601 uint16_t RESERVED3;
bogdanm 73:1efda918f0ba 602 __IO uint16_t DR4;
bogdanm 73:1efda918f0ba 603 uint16_t RESERVED4;
bogdanm 73:1efda918f0ba 604 __IO uint16_t DR5;
bogdanm 73:1efda918f0ba 605 uint16_t RESERVED5;
bogdanm 73:1efda918f0ba 606 __IO uint16_t DR6;
bogdanm 73:1efda918f0ba 607 uint16_t RESERVED6;
bogdanm 73:1efda918f0ba 608 __IO uint16_t DR7;
bogdanm 73:1efda918f0ba 609 uint16_t RESERVED7;
bogdanm 73:1efda918f0ba 610 __IO uint16_t DR8;
bogdanm 73:1efda918f0ba 611 uint16_t RESERVED8;
bogdanm 73:1efda918f0ba 612 __IO uint16_t DR9;
bogdanm 73:1efda918f0ba 613 uint16_t RESERVED9;
bogdanm 73:1efda918f0ba 614 __IO uint16_t DR10;
bogdanm 73:1efda918f0ba 615 uint16_t RESERVED10;
bogdanm 73:1efda918f0ba 616 __IO uint16_t RTCCR;
bogdanm 73:1efda918f0ba 617 uint16_t RESERVED11;
bogdanm 73:1efda918f0ba 618 __IO uint16_t CR;
bogdanm 73:1efda918f0ba 619 uint16_t RESERVED12;
bogdanm 73:1efda918f0ba 620 __IO uint16_t CSR;
bogdanm 73:1efda918f0ba 621 uint16_t RESERVED13[5];
bogdanm 73:1efda918f0ba 622 __IO uint16_t DR11;
bogdanm 73:1efda918f0ba 623 uint16_t RESERVED14;
bogdanm 73:1efda918f0ba 624 __IO uint16_t DR12;
bogdanm 73:1efda918f0ba 625 uint16_t RESERVED15;
bogdanm 73:1efda918f0ba 626 __IO uint16_t DR13;
bogdanm 73:1efda918f0ba 627 uint16_t RESERVED16;
bogdanm 73:1efda918f0ba 628 __IO uint16_t DR14;
bogdanm 73:1efda918f0ba 629 uint16_t RESERVED17;
bogdanm 73:1efda918f0ba 630 __IO uint16_t DR15;
bogdanm 73:1efda918f0ba 631 uint16_t RESERVED18;
bogdanm 73:1efda918f0ba 632 __IO uint16_t DR16;
bogdanm 73:1efda918f0ba 633 uint16_t RESERVED19;
bogdanm 73:1efda918f0ba 634 __IO uint16_t DR17;
bogdanm 73:1efda918f0ba 635 uint16_t RESERVED20;
bogdanm 73:1efda918f0ba 636 __IO uint16_t DR18;
bogdanm 73:1efda918f0ba 637 uint16_t RESERVED21;
bogdanm 73:1efda918f0ba 638 __IO uint16_t DR19;
bogdanm 73:1efda918f0ba 639 uint16_t RESERVED22;
bogdanm 73:1efda918f0ba 640 __IO uint16_t DR20;
bogdanm 73:1efda918f0ba 641 uint16_t RESERVED23;
bogdanm 73:1efda918f0ba 642 __IO uint16_t DR21;
bogdanm 73:1efda918f0ba 643 uint16_t RESERVED24;
bogdanm 73:1efda918f0ba 644 __IO uint16_t DR22;
bogdanm 73:1efda918f0ba 645 uint16_t RESERVED25;
bogdanm 73:1efda918f0ba 646 __IO uint16_t DR23;
bogdanm 73:1efda918f0ba 647 uint16_t RESERVED26;
bogdanm 73:1efda918f0ba 648 __IO uint16_t DR24;
bogdanm 73:1efda918f0ba 649 uint16_t RESERVED27;
bogdanm 73:1efda918f0ba 650 __IO uint16_t DR25;
bogdanm 73:1efda918f0ba 651 uint16_t RESERVED28;
bogdanm 73:1efda918f0ba 652 __IO uint16_t DR26;
bogdanm 73:1efda918f0ba 653 uint16_t RESERVED29;
bogdanm 73:1efda918f0ba 654 __IO uint16_t DR27;
bogdanm 73:1efda918f0ba 655 uint16_t RESERVED30;
bogdanm 73:1efda918f0ba 656 __IO uint16_t DR28;
bogdanm 73:1efda918f0ba 657 uint16_t RESERVED31;
bogdanm 73:1efda918f0ba 658 __IO uint16_t DR29;
bogdanm 73:1efda918f0ba 659 uint16_t RESERVED32;
bogdanm 73:1efda918f0ba 660 __IO uint16_t DR30;
bogdanm 73:1efda918f0ba 661 uint16_t RESERVED33;
bogdanm 73:1efda918f0ba 662 __IO uint16_t DR31;
bogdanm 73:1efda918f0ba 663 uint16_t RESERVED34;
bogdanm 73:1efda918f0ba 664 __IO uint16_t DR32;
bogdanm 73:1efda918f0ba 665 uint16_t RESERVED35;
bogdanm 73:1efda918f0ba 666 __IO uint16_t DR33;
bogdanm 73:1efda918f0ba 667 uint16_t RESERVED36;
bogdanm 73:1efda918f0ba 668 __IO uint16_t DR34;
bogdanm 73:1efda918f0ba 669 uint16_t RESERVED37;
bogdanm 73:1efda918f0ba 670 __IO uint16_t DR35;
bogdanm 73:1efda918f0ba 671 uint16_t RESERVED38;
bogdanm 73:1efda918f0ba 672 __IO uint16_t DR36;
bogdanm 73:1efda918f0ba 673 uint16_t RESERVED39;
bogdanm 73:1efda918f0ba 674 __IO uint16_t DR37;
bogdanm 73:1efda918f0ba 675 uint16_t RESERVED40;
bogdanm 73:1efda918f0ba 676 __IO uint16_t DR38;
bogdanm 73:1efda918f0ba 677 uint16_t RESERVED41;
bogdanm 73:1efda918f0ba 678 __IO uint16_t DR39;
bogdanm 73:1efda918f0ba 679 uint16_t RESERVED42;
bogdanm 73:1efda918f0ba 680 __IO uint16_t DR40;
bogdanm 73:1efda918f0ba 681 uint16_t RESERVED43;
bogdanm 73:1efda918f0ba 682 __IO uint16_t DR41;
bogdanm 73:1efda918f0ba 683 uint16_t RESERVED44;
bogdanm 73:1efda918f0ba 684 __IO uint16_t DR42;
bogdanm 73:1efda918f0ba 685 uint16_t RESERVED45;
bogdanm 73:1efda918f0ba 686 } BKP_TypeDef;
bogdanm 73:1efda918f0ba 687
bogdanm 73:1efda918f0ba 688 /**
bogdanm 73:1efda918f0ba 689 * @brief Controller Area Network TxMailBox
bogdanm 73:1efda918f0ba 690 */
bogdanm 73:1efda918f0ba 691
bogdanm 73:1efda918f0ba 692 typedef struct
bogdanm 73:1efda918f0ba 693 {
bogdanm 73:1efda918f0ba 694 __IO uint32_t TIR;
bogdanm 73:1efda918f0ba 695 __IO uint32_t TDTR;
bogdanm 73:1efda918f0ba 696 __IO uint32_t TDLR;
bogdanm 73:1efda918f0ba 697 __IO uint32_t TDHR;
bogdanm 73:1efda918f0ba 698 } CAN_TxMailBox_TypeDef;
bogdanm 73:1efda918f0ba 699
bogdanm 73:1efda918f0ba 700 /**
bogdanm 73:1efda918f0ba 701 * @brief Controller Area Network FIFOMailBox
bogdanm 73:1efda918f0ba 702 */
bogdanm 73:1efda918f0ba 703
bogdanm 73:1efda918f0ba 704 typedef struct
bogdanm 73:1efda918f0ba 705 {
bogdanm 73:1efda918f0ba 706 __IO uint32_t RIR;
bogdanm 73:1efda918f0ba 707 __IO uint32_t RDTR;
bogdanm 73:1efda918f0ba 708 __IO uint32_t RDLR;
bogdanm 73:1efda918f0ba 709 __IO uint32_t RDHR;
bogdanm 73:1efda918f0ba 710 } CAN_FIFOMailBox_TypeDef;
bogdanm 73:1efda918f0ba 711
bogdanm 73:1efda918f0ba 712 /**
bogdanm 73:1efda918f0ba 713 * @brief Controller Area Network FilterRegister
bogdanm 73:1efda918f0ba 714 */
bogdanm 73:1efda918f0ba 715
bogdanm 73:1efda918f0ba 716 typedef struct
bogdanm 73:1efda918f0ba 717 {
bogdanm 73:1efda918f0ba 718 __IO uint32_t FR1;
bogdanm 73:1efda918f0ba 719 __IO uint32_t FR2;
bogdanm 73:1efda918f0ba 720 } CAN_FilterRegister_TypeDef;
bogdanm 73:1efda918f0ba 721
bogdanm 73:1efda918f0ba 722 /**
bogdanm 73:1efda918f0ba 723 * @brief Controller Area Network
bogdanm 73:1efda918f0ba 724 */
bogdanm 73:1efda918f0ba 725
bogdanm 73:1efda918f0ba 726 typedef struct
bogdanm 73:1efda918f0ba 727 {
bogdanm 73:1efda918f0ba 728 __IO uint32_t MCR;
bogdanm 73:1efda918f0ba 729 __IO uint32_t MSR;
bogdanm 73:1efda918f0ba 730 __IO uint32_t TSR;
bogdanm 73:1efda918f0ba 731 __IO uint32_t RF0R;
bogdanm 73:1efda918f0ba 732 __IO uint32_t RF1R;
bogdanm 73:1efda918f0ba 733 __IO uint32_t IER;
bogdanm 73:1efda918f0ba 734 __IO uint32_t ESR;
bogdanm 73:1efda918f0ba 735 __IO uint32_t BTR;
bogdanm 73:1efda918f0ba 736 uint32_t RESERVED0[88];
bogdanm 73:1efda918f0ba 737 CAN_TxMailBox_TypeDef sTxMailBox[3];
bogdanm 73:1efda918f0ba 738 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
bogdanm 73:1efda918f0ba 739 uint32_t RESERVED1[12];
bogdanm 73:1efda918f0ba 740 __IO uint32_t FMR;
bogdanm 73:1efda918f0ba 741 __IO uint32_t FM1R;
bogdanm 73:1efda918f0ba 742 uint32_t RESERVED2;
bogdanm 73:1efda918f0ba 743 __IO uint32_t FS1R;
bogdanm 73:1efda918f0ba 744 uint32_t RESERVED3;
bogdanm 73:1efda918f0ba 745 __IO uint32_t FFA1R;
bogdanm 73:1efda918f0ba 746 uint32_t RESERVED4;
bogdanm 73:1efda918f0ba 747 __IO uint32_t FA1R;
bogdanm 73:1efda918f0ba 748 uint32_t RESERVED5[8];
bogdanm 73:1efda918f0ba 749 #ifndef STM32F10X_CL
bogdanm 73:1efda918f0ba 750 CAN_FilterRegister_TypeDef sFilterRegister[14];
bogdanm 73:1efda918f0ba 751 #else
bogdanm 73:1efda918f0ba 752 CAN_FilterRegister_TypeDef sFilterRegister[28];
bogdanm 73:1efda918f0ba 753 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 754 } CAN_TypeDef;
bogdanm 73:1efda918f0ba 755
bogdanm 73:1efda918f0ba 756 /**
bogdanm 73:1efda918f0ba 757 * @brief Consumer Electronics Control (CEC)
bogdanm 73:1efda918f0ba 758 */
bogdanm 73:1efda918f0ba 759 typedef struct
bogdanm 73:1efda918f0ba 760 {
bogdanm 73:1efda918f0ba 761 __IO uint32_t CFGR;
bogdanm 73:1efda918f0ba 762 __IO uint32_t OAR;
bogdanm 73:1efda918f0ba 763 __IO uint32_t PRES;
bogdanm 73:1efda918f0ba 764 __IO uint32_t ESR;
bogdanm 73:1efda918f0ba 765 __IO uint32_t CSR;
bogdanm 73:1efda918f0ba 766 __IO uint32_t TXD;
bogdanm 73:1efda918f0ba 767 __IO uint32_t RXD;
bogdanm 73:1efda918f0ba 768 } CEC_TypeDef;
bogdanm 73:1efda918f0ba 769
bogdanm 73:1efda918f0ba 770 /**
bogdanm 73:1efda918f0ba 771 * @brief CRC calculation unit
bogdanm 73:1efda918f0ba 772 */
bogdanm 73:1efda918f0ba 773
bogdanm 73:1efda918f0ba 774 typedef struct
bogdanm 73:1efda918f0ba 775 {
bogdanm 73:1efda918f0ba 776 __IO uint32_t DR;
bogdanm 73:1efda918f0ba 777 __IO uint8_t IDR;
bogdanm 73:1efda918f0ba 778 uint8_t RESERVED0;
bogdanm 73:1efda918f0ba 779 uint16_t RESERVED1;
bogdanm 73:1efda918f0ba 780 __IO uint32_t CR;
bogdanm 73:1efda918f0ba 781 } CRC_TypeDef;
bogdanm 73:1efda918f0ba 782
bogdanm 73:1efda918f0ba 783 /**
bogdanm 73:1efda918f0ba 784 * @brief Digital to Analog Converter
bogdanm 73:1efda918f0ba 785 */
bogdanm 73:1efda918f0ba 786
bogdanm 73:1efda918f0ba 787 typedef struct
bogdanm 73:1efda918f0ba 788 {
bogdanm 73:1efda918f0ba 789 __IO uint32_t CR;
bogdanm 73:1efda918f0ba 790 __IO uint32_t SWTRIGR;
bogdanm 73:1efda918f0ba 791 __IO uint32_t DHR12R1;
bogdanm 73:1efda918f0ba 792 __IO uint32_t DHR12L1;
bogdanm 73:1efda918f0ba 793 __IO uint32_t DHR8R1;
bogdanm 73:1efda918f0ba 794 __IO uint32_t DHR12R2;
bogdanm 73:1efda918f0ba 795 __IO uint32_t DHR12L2;
bogdanm 73:1efda918f0ba 796 __IO uint32_t DHR8R2;
bogdanm 73:1efda918f0ba 797 __IO uint32_t DHR12RD;
bogdanm 73:1efda918f0ba 798 __IO uint32_t DHR12LD;
bogdanm 73:1efda918f0ba 799 __IO uint32_t DHR8RD;
bogdanm 73:1efda918f0ba 800 __IO uint32_t DOR1;
bogdanm 73:1efda918f0ba 801 __IO uint32_t DOR2;
bogdanm 73:1efda918f0ba 802 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 803 __IO uint32_t SR;
bogdanm 73:1efda918f0ba 804 #endif
bogdanm 73:1efda918f0ba 805 } DAC_TypeDef;
bogdanm 73:1efda918f0ba 806
bogdanm 73:1efda918f0ba 807 /**
bogdanm 73:1efda918f0ba 808 * @brief Debug MCU
bogdanm 73:1efda918f0ba 809 */
bogdanm 73:1efda918f0ba 810
bogdanm 73:1efda918f0ba 811 typedef struct
bogdanm 73:1efda918f0ba 812 {
bogdanm 73:1efda918f0ba 813 __IO uint32_t IDCODE;
bogdanm 73:1efda918f0ba 814 __IO uint32_t CR;
bogdanm 73:1efda918f0ba 815 }DBGMCU_TypeDef;
bogdanm 73:1efda918f0ba 816
bogdanm 73:1efda918f0ba 817 /**
bogdanm 73:1efda918f0ba 818 * @brief DMA Controller
bogdanm 73:1efda918f0ba 819 */
bogdanm 73:1efda918f0ba 820
bogdanm 73:1efda918f0ba 821 typedef struct
bogdanm 73:1efda918f0ba 822 {
bogdanm 73:1efda918f0ba 823 __IO uint32_t CCR;
bogdanm 73:1efda918f0ba 824 __IO uint32_t CNDTR;
bogdanm 73:1efda918f0ba 825 __IO uint32_t CPAR;
bogdanm 73:1efda918f0ba 826 __IO uint32_t CMAR;
bogdanm 73:1efda918f0ba 827 } DMA_Channel_TypeDef;
bogdanm 73:1efda918f0ba 828
bogdanm 73:1efda918f0ba 829 typedef struct
bogdanm 73:1efda918f0ba 830 {
bogdanm 73:1efda918f0ba 831 __IO uint32_t ISR;
bogdanm 73:1efda918f0ba 832 __IO uint32_t IFCR;
bogdanm 73:1efda918f0ba 833 } DMA_TypeDef;
bogdanm 73:1efda918f0ba 834
bogdanm 73:1efda918f0ba 835 /**
bogdanm 73:1efda918f0ba 836 * @brief Ethernet MAC
bogdanm 73:1efda918f0ba 837 */
bogdanm 73:1efda918f0ba 838
bogdanm 73:1efda918f0ba 839 typedef struct
bogdanm 73:1efda918f0ba 840 {
bogdanm 73:1efda918f0ba 841 __IO uint32_t MACCR;
bogdanm 73:1efda918f0ba 842 __IO uint32_t MACFFR;
bogdanm 73:1efda918f0ba 843 __IO uint32_t MACHTHR;
bogdanm 73:1efda918f0ba 844 __IO uint32_t MACHTLR;
bogdanm 73:1efda918f0ba 845 __IO uint32_t MACMIIAR;
bogdanm 73:1efda918f0ba 846 __IO uint32_t MACMIIDR;
bogdanm 73:1efda918f0ba 847 __IO uint32_t MACFCR;
bogdanm 73:1efda918f0ba 848 __IO uint32_t MACVLANTR; /* 8 */
bogdanm 73:1efda918f0ba 849 uint32_t RESERVED0[2];
bogdanm 73:1efda918f0ba 850 __IO uint32_t MACRWUFFR; /* 11 */
bogdanm 73:1efda918f0ba 851 __IO uint32_t MACPMTCSR;
bogdanm 73:1efda918f0ba 852 uint32_t RESERVED1[2];
bogdanm 73:1efda918f0ba 853 __IO uint32_t MACSR; /* 15 */
bogdanm 73:1efda918f0ba 854 __IO uint32_t MACIMR;
bogdanm 73:1efda918f0ba 855 __IO uint32_t MACA0HR;
bogdanm 73:1efda918f0ba 856 __IO uint32_t MACA0LR;
bogdanm 73:1efda918f0ba 857 __IO uint32_t MACA1HR;
bogdanm 73:1efda918f0ba 858 __IO uint32_t MACA1LR;
bogdanm 73:1efda918f0ba 859 __IO uint32_t MACA2HR;
bogdanm 73:1efda918f0ba 860 __IO uint32_t MACA2LR;
bogdanm 73:1efda918f0ba 861 __IO uint32_t MACA3HR;
bogdanm 73:1efda918f0ba 862 __IO uint32_t MACA3LR; /* 24 */
bogdanm 73:1efda918f0ba 863 uint32_t RESERVED2[40];
bogdanm 73:1efda918f0ba 864 __IO uint32_t MMCCR; /* 65 */
bogdanm 73:1efda918f0ba 865 __IO uint32_t MMCRIR;
bogdanm 73:1efda918f0ba 866 __IO uint32_t MMCTIR;
bogdanm 73:1efda918f0ba 867 __IO uint32_t MMCRIMR;
bogdanm 73:1efda918f0ba 868 __IO uint32_t MMCTIMR; /* 69 */
bogdanm 73:1efda918f0ba 869 uint32_t RESERVED3[14];
bogdanm 73:1efda918f0ba 870 __IO uint32_t MMCTGFSCCR; /* 84 */
bogdanm 73:1efda918f0ba 871 __IO uint32_t MMCTGFMSCCR;
bogdanm 73:1efda918f0ba 872 uint32_t RESERVED4[5];
bogdanm 73:1efda918f0ba 873 __IO uint32_t MMCTGFCR;
bogdanm 73:1efda918f0ba 874 uint32_t RESERVED5[10];
bogdanm 73:1efda918f0ba 875 __IO uint32_t MMCRFCECR;
bogdanm 73:1efda918f0ba 876 __IO uint32_t MMCRFAECR;
bogdanm 73:1efda918f0ba 877 uint32_t RESERVED6[10];
bogdanm 73:1efda918f0ba 878 __IO uint32_t MMCRGUFCR;
bogdanm 73:1efda918f0ba 879 uint32_t RESERVED7[334];
bogdanm 73:1efda918f0ba 880 __IO uint32_t PTPTSCR;
bogdanm 73:1efda918f0ba 881 __IO uint32_t PTPSSIR;
bogdanm 73:1efda918f0ba 882 __IO uint32_t PTPTSHR;
bogdanm 73:1efda918f0ba 883 __IO uint32_t PTPTSLR;
bogdanm 73:1efda918f0ba 884 __IO uint32_t PTPTSHUR;
bogdanm 73:1efda918f0ba 885 __IO uint32_t PTPTSLUR;
bogdanm 73:1efda918f0ba 886 __IO uint32_t PTPTSAR;
bogdanm 73:1efda918f0ba 887 __IO uint32_t PTPTTHR;
bogdanm 73:1efda918f0ba 888 __IO uint32_t PTPTTLR;
bogdanm 73:1efda918f0ba 889 uint32_t RESERVED8[567];
bogdanm 73:1efda918f0ba 890 __IO uint32_t DMABMR;
bogdanm 73:1efda918f0ba 891 __IO uint32_t DMATPDR;
bogdanm 73:1efda918f0ba 892 __IO uint32_t DMARPDR;
bogdanm 73:1efda918f0ba 893 __IO uint32_t DMARDLAR;
bogdanm 73:1efda918f0ba 894 __IO uint32_t DMATDLAR;
bogdanm 73:1efda918f0ba 895 __IO uint32_t DMASR;
bogdanm 73:1efda918f0ba 896 __IO uint32_t DMAOMR;
bogdanm 73:1efda918f0ba 897 __IO uint32_t DMAIER;
bogdanm 73:1efda918f0ba 898 __IO uint32_t DMAMFBOCR;
bogdanm 73:1efda918f0ba 899 uint32_t RESERVED9[9];
bogdanm 73:1efda918f0ba 900 __IO uint32_t DMACHTDR;
bogdanm 73:1efda918f0ba 901 __IO uint32_t DMACHRDR;
bogdanm 73:1efda918f0ba 902 __IO uint32_t DMACHTBAR;
bogdanm 73:1efda918f0ba 903 __IO uint32_t DMACHRBAR;
bogdanm 73:1efda918f0ba 904 } ETH_TypeDef;
bogdanm 73:1efda918f0ba 905
bogdanm 73:1efda918f0ba 906 /**
bogdanm 73:1efda918f0ba 907 * @brief External Interrupt/Event Controller
bogdanm 73:1efda918f0ba 908 */
bogdanm 73:1efda918f0ba 909
bogdanm 73:1efda918f0ba 910 typedef struct
bogdanm 73:1efda918f0ba 911 {
bogdanm 73:1efda918f0ba 912 __IO uint32_t IMR;
bogdanm 73:1efda918f0ba 913 __IO uint32_t EMR;
bogdanm 73:1efda918f0ba 914 __IO uint32_t RTSR;
bogdanm 73:1efda918f0ba 915 __IO uint32_t FTSR;
bogdanm 73:1efda918f0ba 916 __IO uint32_t SWIER;
bogdanm 73:1efda918f0ba 917 __IO uint32_t PR;
bogdanm 73:1efda918f0ba 918 } EXTI_TypeDef;
bogdanm 73:1efda918f0ba 919
bogdanm 73:1efda918f0ba 920 /**
bogdanm 73:1efda918f0ba 921 * @brief FLASH Registers
bogdanm 73:1efda918f0ba 922 */
bogdanm 73:1efda918f0ba 923
bogdanm 73:1efda918f0ba 924 typedef struct
bogdanm 73:1efda918f0ba 925 {
bogdanm 73:1efda918f0ba 926 __IO uint32_t ACR;
bogdanm 73:1efda918f0ba 927 __IO uint32_t KEYR;
bogdanm 73:1efda918f0ba 928 __IO uint32_t OPTKEYR;
bogdanm 73:1efda918f0ba 929 __IO uint32_t SR;
bogdanm 73:1efda918f0ba 930 __IO uint32_t CR;
bogdanm 73:1efda918f0ba 931 __IO uint32_t AR;
bogdanm 73:1efda918f0ba 932 __IO uint32_t RESERVED;
bogdanm 73:1efda918f0ba 933 __IO uint32_t OBR;
bogdanm 73:1efda918f0ba 934 __IO uint32_t WRPR;
bogdanm 73:1efda918f0ba 935 #ifdef STM32F10X_XL
bogdanm 73:1efda918f0ba 936 uint32_t RESERVED1[8];
bogdanm 73:1efda918f0ba 937 __IO uint32_t KEYR2;
bogdanm 73:1efda918f0ba 938 uint32_t RESERVED2;
bogdanm 73:1efda918f0ba 939 __IO uint32_t SR2;
bogdanm 73:1efda918f0ba 940 __IO uint32_t CR2;
bogdanm 73:1efda918f0ba 941 __IO uint32_t AR2;
bogdanm 73:1efda918f0ba 942 #endif /* STM32F10X_XL */
bogdanm 73:1efda918f0ba 943 } FLASH_TypeDef;
bogdanm 73:1efda918f0ba 944
bogdanm 73:1efda918f0ba 945 /**
bogdanm 73:1efda918f0ba 946 * @brief Option Bytes Registers
bogdanm 73:1efda918f0ba 947 */
bogdanm 73:1efda918f0ba 948
bogdanm 73:1efda918f0ba 949 typedef struct
bogdanm 73:1efda918f0ba 950 {
bogdanm 73:1efda918f0ba 951 __IO uint16_t RDP;
bogdanm 73:1efda918f0ba 952 __IO uint16_t USER;
bogdanm 73:1efda918f0ba 953 __IO uint16_t Data0;
bogdanm 73:1efda918f0ba 954 __IO uint16_t Data1;
bogdanm 73:1efda918f0ba 955 __IO uint16_t WRP0;
bogdanm 73:1efda918f0ba 956 __IO uint16_t WRP1;
bogdanm 73:1efda918f0ba 957 __IO uint16_t WRP2;
bogdanm 73:1efda918f0ba 958 __IO uint16_t WRP3;
bogdanm 73:1efda918f0ba 959 } OB_TypeDef;
bogdanm 73:1efda918f0ba 960
bogdanm 73:1efda918f0ba 961 /**
bogdanm 73:1efda918f0ba 962 * @brief Flexible Static Memory Controller
bogdanm 73:1efda918f0ba 963 */
bogdanm 73:1efda918f0ba 964
bogdanm 73:1efda918f0ba 965 typedef struct
bogdanm 73:1efda918f0ba 966 {
bogdanm 73:1efda918f0ba 967 __IO uint32_t BTCR[8];
bogdanm 73:1efda918f0ba 968 } FSMC_Bank1_TypeDef;
bogdanm 73:1efda918f0ba 969
bogdanm 73:1efda918f0ba 970 /**
bogdanm 73:1efda918f0ba 971 * @brief Flexible Static Memory Controller Bank1E
bogdanm 73:1efda918f0ba 972 */
bogdanm 73:1efda918f0ba 973
bogdanm 73:1efda918f0ba 974 typedef struct
bogdanm 73:1efda918f0ba 975 {
bogdanm 73:1efda918f0ba 976 __IO uint32_t BWTR[7];
bogdanm 73:1efda918f0ba 977 } FSMC_Bank1E_TypeDef;
bogdanm 73:1efda918f0ba 978
bogdanm 73:1efda918f0ba 979 /**
bogdanm 73:1efda918f0ba 980 * @brief Flexible Static Memory Controller Bank2
bogdanm 73:1efda918f0ba 981 */
bogdanm 73:1efda918f0ba 982
bogdanm 73:1efda918f0ba 983 typedef struct
bogdanm 73:1efda918f0ba 984 {
bogdanm 73:1efda918f0ba 985 __IO uint32_t PCR2;
bogdanm 73:1efda918f0ba 986 __IO uint32_t SR2;
bogdanm 73:1efda918f0ba 987 __IO uint32_t PMEM2;
bogdanm 73:1efda918f0ba 988 __IO uint32_t PATT2;
bogdanm 73:1efda918f0ba 989 uint32_t RESERVED0;
bogdanm 73:1efda918f0ba 990 __IO uint32_t ECCR2;
bogdanm 73:1efda918f0ba 991 } FSMC_Bank2_TypeDef;
bogdanm 73:1efda918f0ba 992
bogdanm 73:1efda918f0ba 993 /**
bogdanm 73:1efda918f0ba 994 * @brief Flexible Static Memory Controller Bank3
bogdanm 73:1efda918f0ba 995 */
bogdanm 73:1efda918f0ba 996
bogdanm 73:1efda918f0ba 997 typedef struct
bogdanm 73:1efda918f0ba 998 {
bogdanm 73:1efda918f0ba 999 __IO uint32_t PCR3;
bogdanm 73:1efda918f0ba 1000 __IO uint32_t SR3;
bogdanm 73:1efda918f0ba 1001 __IO uint32_t PMEM3;
bogdanm 73:1efda918f0ba 1002 __IO uint32_t PATT3;
bogdanm 73:1efda918f0ba 1003 uint32_t RESERVED0;
bogdanm 73:1efda918f0ba 1004 __IO uint32_t ECCR3;
bogdanm 73:1efda918f0ba 1005 } FSMC_Bank3_TypeDef;
bogdanm 73:1efda918f0ba 1006
bogdanm 73:1efda918f0ba 1007 /**
bogdanm 73:1efda918f0ba 1008 * @brief Flexible Static Memory Controller Bank4
bogdanm 73:1efda918f0ba 1009 */
bogdanm 73:1efda918f0ba 1010
bogdanm 73:1efda918f0ba 1011 typedef struct
bogdanm 73:1efda918f0ba 1012 {
bogdanm 73:1efda918f0ba 1013 __IO uint32_t PCR4;
bogdanm 73:1efda918f0ba 1014 __IO uint32_t SR4;
bogdanm 73:1efda918f0ba 1015 __IO uint32_t PMEM4;
bogdanm 73:1efda918f0ba 1016 __IO uint32_t PATT4;
bogdanm 73:1efda918f0ba 1017 __IO uint32_t PIO4;
bogdanm 73:1efda918f0ba 1018 } FSMC_Bank4_TypeDef;
bogdanm 73:1efda918f0ba 1019
bogdanm 73:1efda918f0ba 1020 /**
bogdanm 73:1efda918f0ba 1021 * @brief General Purpose I/O
bogdanm 73:1efda918f0ba 1022 */
bogdanm 73:1efda918f0ba 1023
bogdanm 73:1efda918f0ba 1024 typedef struct
bogdanm 73:1efda918f0ba 1025 {
bogdanm 73:1efda918f0ba 1026 __IO uint32_t CRL;
bogdanm 73:1efda918f0ba 1027 __IO uint32_t CRH;
bogdanm 73:1efda918f0ba 1028 __IO uint32_t IDR;
bogdanm 73:1efda918f0ba 1029 __IO uint32_t ODR;
bogdanm 73:1efda918f0ba 1030 __IO uint32_t BSRR;
bogdanm 73:1efda918f0ba 1031 __IO uint32_t BRR;
bogdanm 73:1efda918f0ba 1032 __IO uint32_t LCKR;
bogdanm 73:1efda918f0ba 1033 } GPIO_TypeDef;
bogdanm 73:1efda918f0ba 1034
bogdanm 73:1efda918f0ba 1035 /**
bogdanm 73:1efda918f0ba 1036 * @brief Alternate Function I/O
bogdanm 73:1efda918f0ba 1037 */
bogdanm 73:1efda918f0ba 1038
bogdanm 73:1efda918f0ba 1039 typedef struct
bogdanm 73:1efda918f0ba 1040 {
bogdanm 73:1efda918f0ba 1041 __IO uint32_t EVCR;
bogdanm 73:1efda918f0ba 1042 __IO uint32_t MAPR;
bogdanm 73:1efda918f0ba 1043 __IO uint32_t EXTICR[4];
bogdanm 73:1efda918f0ba 1044 uint32_t RESERVED0;
bogdanm 73:1efda918f0ba 1045 __IO uint32_t MAPR2;
bogdanm 73:1efda918f0ba 1046 } AFIO_TypeDef;
bogdanm 73:1efda918f0ba 1047 /**
bogdanm 73:1efda918f0ba 1048 * @brief Inter Integrated Circuit Interface
bogdanm 73:1efda918f0ba 1049 */
bogdanm 73:1efda918f0ba 1050
bogdanm 73:1efda918f0ba 1051 typedef struct
bogdanm 73:1efda918f0ba 1052 {
bogdanm 73:1efda918f0ba 1053 __IO uint16_t CR1;
bogdanm 73:1efda918f0ba 1054 uint16_t RESERVED0;
bogdanm 73:1efda918f0ba 1055 __IO uint16_t CR2;
bogdanm 73:1efda918f0ba 1056 uint16_t RESERVED1;
bogdanm 73:1efda918f0ba 1057 __IO uint16_t OAR1;
bogdanm 73:1efda918f0ba 1058 uint16_t RESERVED2;
bogdanm 73:1efda918f0ba 1059 __IO uint16_t OAR2;
bogdanm 73:1efda918f0ba 1060 uint16_t RESERVED3;
bogdanm 73:1efda918f0ba 1061 __IO uint16_t DR;
bogdanm 73:1efda918f0ba 1062 uint16_t RESERVED4;
bogdanm 73:1efda918f0ba 1063 __IO uint16_t SR1;
bogdanm 73:1efda918f0ba 1064 uint16_t RESERVED5;
bogdanm 73:1efda918f0ba 1065 __IO uint16_t SR2;
bogdanm 73:1efda918f0ba 1066 uint16_t RESERVED6;
bogdanm 73:1efda918f0ba 1067 __IO uint16_t CCR;
bogdanm 73:1efda918f0ba 1068 uint16_t RESERVED7;
bogdanm 73:1efda918f0ba 1069 __IO uint16_t TRISE;
bogdanm 73:1efda918f0ba 1070 uint16_t RESERVED8;
bogdanm 73:1efda918f0ba 1071 } I2C_TypeDef;
bogdanm 73:1efda918f0ba 1072
bogdanm 73:1efda918f0ba 1073 /**
bogdanm 73:1efda918f0ba 1074 * @brief Independent WATCHDOG
bogdanm 73:1efda918f0ba 1075 */
bogdanm 73:1efda918f0ba 1076
bogdanm 73:1efda918f0ba 1077 typedef struct
bogdanm 73:1efda918f0ba 1078 {
bogdanm 73:1efda918f0ba 1079 __IO uint32_t KR;
bogdanm 73:1efda918f0ba 1080 __IO uint32_t PR;
bogdanm 73:1efda918f0ba 1081 __IO uint32_t RLR;
bogdanm 73:1efda918f0ba 1082 __IO uint32_t SR;
bogdanm 73:1efda918f0ba 1083 } IWDG_TypeDef;
bogdanm 73:1efda918f0ba 1084
bogdanm 73:1efda918f0ba 1085 /**
bogdanm 73:1efda918f0ba 1086 * @brief Power Control
bogdanm 73:1efda918f0ba 1087 */
bogdanm 73:1efda918f0ba 1088
bogdanm 73:1efda918f0ba 1089 typedef struct
bogdanm 73:1efda918f0ba 1090 {
bogdanm 73:1efda918f0ba 1091 __IO uint32_t CR;
bogdanm 73:1efda918f0ba 1092 __IO uint32_t CSR;
bogdanm 73:1efda918f0ba 1093 } PWR_TypeDef;
bogdanm 73:1efda918f0ba 1094
bogdanm 73:1efda918f0ba 1095 /**
bogdanm 73:1efda918f0ba 1096 * @brief Reset and Clock Control
bogdanm 73:1efda918f0ba 1097 */
bogdanm 73:1efda918f0ba 1098
bogdanm 73:1efda918f0ba 1099 typedef struct
bogdanm 73:1efda918f0ba 1100 {
bogdanm 73:1efda918f0ba 1101 __IO uint32_t CR;
bogdanm 73:1efda918f0ba 1102 __IO uint32_t CFGR;
bogdanm 73:1efda918f0ba 1103 __IO uint32_t CIR;
bogdanm 73:1efda918f0ba 1104 __IO uint32_t APB2RSTR;
bogdanm 73:1efda918f0ba 1105 __IO uint32_t APB1RSTR;
bogdanm 73:1efda918f0ba 1106 __IO uint32_t AHBENR;
bogdanm 73:1efda918f0ba 1107 __IO uint32_t APB2ENR;
bogdanm 73:1efda918f0ba 1108 __IO uint32_t APB1ENR;
bogdanm 73:1efda918f0ba 1109 __IO uint32_t BDCR;
bogdanm 73:1efda918f0ba 1110 __IO uint32_t CSR;
bogdanm 73:1efda918f0ba 1111
bogdanm 73:1efda918f0ba 1112 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 1113 __IO uint32_t AHBRSTR;
bogdanm 73:1efda918f0ba 1114 __IO uint32_t CFGR2;
bogdanm 73:1efda918f0ba 1115 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 1116
bogdanm 73:1efda918f0ba 1117 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 1118 uint32_t RESERVED0;
bogdanm 73:1efda918f0ba 1119 __IO uint32_t CFGR2;
bogdanm 73:1efda918f0ba 1120 #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
bogdanm 73:1efda918f0ba 1121 } RCC_TypeDef;
bogdanm 73:1efda918f0ba 1122
bogdanm 73:1efda918f0ba 1123 /**
bogdanm 73:1efda918f0ba 1124 * @brief Real-Time Clock
bogdanm 73:1efda918f0ba 1125 */
bogdanm 73:1efda918f0ba 1126
bogdanm 73:1efda918f0ba 1127 typedef struct
bogdanm 73:1efda918f0ba 1128 {
bogdanm 73:1efda918f0ba 1129 __IO uint16_t CRH;
bogdanm 73:1efda918f0ba 1130 uint16_t RESERVED0;
bogdanm 73:1efda918f0ba 1131 __IO uint16_t CRL;
bogdanm 73:1efda918f0ba 1132 uint16_t RESERVED1;
bogdanm 73:1efda918f0ba 1133 __IO uint16_t PRLH;
bogdanm 73:1efda918f0ba 1134 uint16_t RESERVED2;
bogdanm 73:1efda918f0ba 1135 __IO uint16_t PRLL;
bogdanm 73:1efda918f0ba 1136 uint16_t RESERVED3;
bogdanm 73:1efda918f0ba 1137 __IO uint16_t DIVH;
bogdanm 73:1efda918f0ba 1138 uint16_t RESERVED4;
bogdanm 73:1efda918f0ba 1139 __IO uint16_t DIVL;
bogdanm 73:1efda918f0ba 1140 uint16_t RESERVED5;
bogdanm 73:1efda918f0ba 1141 __IO uint16_t CNTH;
bogdanm 73:1efda918f0ba 1142 uint16_t RESERVED6;
bogdanm 73:1efda918f0ba 1143 __IO uint16_t CNTL;
bogdanm 73:1efda918f0ba 1144 uint16_t RESERVED7;
bogdanm 73:1efda918f0ba 1145 __IO uint16_t ALRH;
bogdanm 73:1efda918f0ba 1146 uint16_t RESERVED8;
bogdanm 73:1efda918f0ba 1147 __IO uint16_t ALRL;
bogdanm 73:1efda918f0ba 1148 uint16_t RESERVED9;
bogdanm 73:1efda918f0ba 1149 } RTC_TypeDef;
bogdanm 73:1efda918f0ba 1150
bogdanm 73:1efda918f0ba 1151 /**
bogdanm 73:1efda918f0ba 1152 * @brief SD host Interface
bogdanm 73:1efda918f0ba 1153 */
bogdanm 73:1efda918f0ba 1154
bogdanm 73:1efda918f0ba 1155 typedef struct
bogdanm 73:1efda918f0ba 1156 {
bogdanm 73:1efda918f0ba 1157 __IO uint32_t POWER;
bogdanm 73:1efda918f0ba 1158 __IO uint32_t CLKCR;
bogdanm 73:1efda918f0ba 1159 __IO uint32_t ARG;
bogdanm 73:1efda918f0ba 1160 __IO uint32_t CMD;
bogdanm 73:1efda918f0ba 1161 __I uint32_t RESPCMD;
bogdanm 73:1efda918f0ba 1162 __I uint32_t RESP1;
bogdanm 73:1efda918f0ba 1163 __I uint32_t RESP2;
bogdanm 73:1efda918f0ba 1164 __I uint32_t RESP3;
bogdanm 73:1efda918f0ba 1165 __I uint32_t RESP4;
bogdanm 73:1efda918f0ba 1166 __IO uint32_t DTIMER;
bogdanm 73:1efda918f0ba 1167 __IO uint32_t DLEN;
bogdanm 73:1efda918f0ba 1168 __IO uint32_t DCTRL;
bogdanm 73:1efda918f0ba 1169 __I uint32_t DCOUNT;
bogdanm 73:1efda918f0ba 1170 __I uint32_t STA;
bogdanm 73:1efda918f0ba 1171 __IO uint32_t ICR;
bogdanm 73:1efda918f0ba 1172 __IO uint32_t MASK;
bogdanm 73:1efda918f0ba 1173 uint32_t RESERVED0[2];
bogdanm 73:1efda918f0ba 1174 __I uint32_t FIFOCNT;
bogdanm 73:1efda918f0ba 1175 uint32_t RESERVED1[13];
bogdanm 73:1efda918f0ba 1176 __IO uint32_t FIFO;
bogdanm 73:1efda918f0ba 1177 } SDIO_TypeDef;
bogdanm 73:1efda918f0ba 1178
bogdanm 73:1efda918f0ba 1179 /**
bogdanm 73:1efda918f0ba 1180 * @brief Serial Peripheral Interface
bogdanm 73:1efda918f0ba 1181 */
bogdanm 73:1efda918f0ba 1182
bogdanm 73:1efda918f0ba 1183 typedef struct
bogdanm 73:1efda918f0ba 1184 {
bogdanm 73:1efda918f0ba 1185 __IO uint16_t CR1;
bogdanm 73:1efda918f0ba 1186 uint16_t RESERVED0;
bogdanm 73:1efda918f0ba 1187 __IO uint16_t CR2;
bogdanm 73:1efda918f0ba 1188 uint16_t RESERVED1;
bogdanm 73:1efda918f0ba 1189 __IO uint16_t SR;
bogdanm 73:1efda918f0ba 1190 uint16_t RESERVED2;
bogdanm 73:1efda918f0ba 1191 __IO uint16_t DR;
bogdanm 73:1efda918f0ba 1192 uint16_t RESERVED3;
bogdanm 73:1efda918f0ba 1193 __IO uint16_t CRCPR;
bogdanm 73:1efda918f0ba 1194 uint16_t RESERVED4;
bogdanm 73:1efda918f0ba 1195 __IO uint16_t RXCRCR;
bogdanm 73:1efda918f0ba 1196 uint16_t RESERVED5;
bogdanm 73:1efda918f0ba 1197 __IO uint16_t TXCRCR;
bogdanm 73:1efda918f0ba 1198 uint16_t RESERVED6;
bogdanm 73:1efda918f0ba 1199 __IO uint16_t I2SCFGR;
bogdanm 73:1efda918f0ba 1200 uint16_t RESERVED7;
bogdanm 73:1efda918f0ba 1201 __IO uint16_t I2SPR;
bogdanm 73:1efda918f0ba 1202 uint16_t RESERVED8;
bogdanm 73:1efda918f0ba 1203 } SPI_TypeDef;
bogdanm 73:1efda918f0ba 1204
bogdanm 73:1efda918f0ba 1205 /**
bogdanm 73:1efda918f0ba 1206 * @brief TIM
bogdanm 73:1efda918f0ba 1207 */
bogdanm 73:1efda918f0ba 1208
bogdanm 73:1efda918f0ba 1209 typedef struct
bogdanm 73:1efda918f0ba 1210 {
bogdanm 73:1efda918f0ba 1211 __IO uint16_t CR1;
bogdanm 73:1efda918f0ba 1212 uint16_t RESERVED0;
bogdanm 73:1efda918f0ba 1213 __IO uint16_t CR2;
bogdanm 73:1efda918f0ba 1214 uint16_t RESERVED1;
bogdanm 73:1efda918f0ba 1215 __IO uint16_t SMCR;
bogdanm 73:1efda918f0ba 1216 uint16_t RESERVED2;
bogdanm 73:1efda918f0ba 1217 __IO uint16_t DIER;
bogdanm 73:1efda918f0ba 1218 uint16_t RESERVED3;
bogdanm 73:1efda918f0ba 1219 __IO uint16_t SR;
bogdanm 73:1efda918f0ba 1220 uint16_t RESERVED4;
bogdanm 73:1efda918f0ba 1221 __IO uint16_t EGR;
bogdanm 73:1efda918f0ba 1222 uint16_t RESERVED5;
bogdanm 73:1efda918f0ba 1223 __IO uint16_t CCMR1;
bogdanm 73:1efda918f0ba 1224 uint16_t RESERVED6;
bogdanm 73:1efda918f0ba 1225 __IO uint16_t CCMR2;
bogdanm 73:1efda918f0ba 1226 uint16_t RESERVED7;
bogdanm 73:1efda918f0ba 1227 __IO uint16_t CCER;
bogdanm 73:1efda918f0ba 1228 uint16_t RESERVED8;
bogdanm 73:1efda918f0ba 1229 __IO uint16_t CNT;
bogdanm 73:1efda918f0ba 1230 uint16_t RESERVED9;
bogdanm 73:1efda918f0ba 1231 __IO uint16_t PSC;
bogdanm 73:1efda918f0ba 1232 uint16_t RESERVED10;
bogdanm 73:1efda918f0ba 1233 __IO uint16_t ARR;
bogdanm 73:1efda918f0ba 1234 uint16_t RESERVED11;
bogdanm 73:1efda918f0ba 1235 __IO uint16_t RCR;
bogdanm 73:1efda918f0ba 1236 uint16_t RESERVED12;
bogdanm 73:1efda918f0ba 1237 __IO uint16_t CCR1;
bogdanm 73:1efda918f0ba 1238 uint16_t RESERVED13;
bogdanm 73:1efda918f0ba 1239 __IO uint16_t CCR2;
bogdanm 73:1efda918f0ba 1240 uint16_t RESERVED14;
bogdanm 73:1efda918f0ba 1241 __IO uint16_t CCR3;
bogdanm 73:1efda918f0ba 1242 uint16_t RESERVED15;
bogdanm 73:1efda918f0ba 1243 __IO uint16_t CCR4;
bogdanm 73:1efda918f0ba 1244 uint16_t RESERVED16;
bogdanm 73:1efda918f0ba 1245 __IO uint16_t BDTR;
bogdanm 73:1efda918f0ba 1246 uint16_t RESERVED17;
bogdanm 73:1efda918f0ba 1247 __IO uint16_t DCR;
bogdanm 73:1efda918f0ba 1248 uint16_t RESERVED18;
bogdanm 73:1efda918f0ba 1249 __IO uint16_t DMAR;
bogdanm 73:1efda918f0ba 1250 uint16_t RESERVED19;
bogdanm 73:1efda918f0ba 1251 } TIM_TypeDef;
bogdanm 73:1efda918f0ba 1252
bogdanm 73:1efda918f0ba 1253 /**
bogdanm 73:1efda918f0ba 1254 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 73:1efda918f0ba 1255 */
bogdanm 73:1efda918f0ba 1256
bogdanm 73:1efda918f0ba 1257 typedef struct
bogdanm 73:1efda918f0ba 1258 {
bogdanm 73:1efda918f0ba 1259 __IO uint16_t SR;
bogdanm 73:1efda918f0ba 1260 uint16_t RESERVED0;
bogdanm 73:1efda918f0ba 1261 __IO uint16_t DR;
bogdanm 73:1efda918f0ba 1262 uint16_t RESERVED1;
bogdanm 73:1efda918f0ba 1263 __IO uint16_t BRR;
bogdanm 73:1efda918f0ba 1264 uint16_t RESERVED2;
bogdanm 73:1efda918f0ba 1265 __IO uint16_t CR1;
bogdanm 73:1efda918f0ba 1266 uint16_t RESERVED3;
bogdanm 73:1efda918f0ba 1267 __IO uint16_t CR2;
bogdanm 73:1efda918f0ba 1268 uint16_t RESERVED4;
bogdanm 73:1efda918f0ba 1269 __IO uint16_t CR3;
bogdanm 73:1efda918f0ba 1270 uint16_t RESERVED5;
bogdanm 73:1efda918f0ba 1271 __IO uint16_t GTPR;
bogdanm 73:1efda918f0ba 1272 uint16_t RESERVED6;
bogdanm 73:1efda918f0ba 1273 } USART_TypeDef;
bogdanm 73:1efda918f0ba 1274
bogdanm 73:1efda918f0ba 1275 /**
bogdanm 73:1efda918f0ba 1276 * @brief Window WATCHDOG
bogdanm 73:1efda918f0ba 1277 */
bogdanm 73:1efda918f0ba 1278
bogdanm 73:1efda918f0ba 1279 typedef struct
bogdanm 73:1efda918f0ba 1280 {
bogdanm 73:1efda918f0ba 1281 __IO uint32_t CR;
bogdanm 73:1efda918f0ba 1282 __IO uint32_t CFR;
bogdanm 73:1efda918f0ba 1283 __IO uint32_t SR;
bogdanm 73:1efda918f0ba 1284 } WWDG_TypeDef;
bogdanm 73:1efda918f0ba 1285
bogdanm 73:1efda918f0ba 1286 /**
bogdanm 73:1efda918f0ba 1287 * @}
bogdanm 73:1efda918f0ba 1288 */
bogdanm 73:1efda918f0ba 1289
bogdanm 73:1efda918f0ba 1290 /** @addtogroup Peripheral_memory_map
bogdanm 73:1efda918f0ba 1291 * @{
bogdanm 73:1efda918f0ba 1292 */
bogdanm 73:1efda918f0ba 1293
bogdanm 73:1efda918f0ba 1294
bogdanm 73:1efda918f0ba 1295 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
bogdanm 73:1efda918f0ba 1296 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
bogdanm 73:1efda918f0ba 1297 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 73:1efda918f0ba 1298
bogdanm 73:1efda918f0ba 1299 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
bogdanm 73:1efda918f0ba 1300 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
bogdanm 73:1efda918f0ba 1301
bogdanm 73:1efda918f0ba 1302 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
bogdanm 73:1efda918f0ba 1303
bogdanm 73:1efda918f0ba 1304 /*!< Peripheral memory map */
bogdanm 73:1efda918f0ba 1305 #define APB1PERIPH_BASE PERIPH_BASE
bogdanm 73:1efda918f0ba 1306 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
bogdanm 73:1efda918f0ba 1307 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
bogdanm 73:1efda918f0ba 1308
bogdanm 73:1efda918f0ba 1309 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
bogdanm 73:1efda918f0ba 1310 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
bogdanm 73:1efda918f0ba 1311 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
bogdanm 73:1efda918f0ba 1312 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
bogdanm 73:1efda918f0ba 1313 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
bogdanm 73:1efda918f0ba 1314 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
bogdanm 73:1efda918f0ba 1315 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
bogdanm 73:1efda918f0ba 1316 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
bogdanm 73:1efda918f0ba 1317 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
bogdanm 73:1efda918f0ba 1318 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
bogdanm 73:1efda918f0ba 1319 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
bogdanm 73:1efda918f0ba 1320 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
bogdanm 73:1efda918f0ba 1321 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
bogdanm 73:1efda918f0ba 1322 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
bogdanm 73:1efda918f0ba 1323 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
bogdanm 73:1efda918f0ba 1324 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
bogdanm 73:1efda918f0ba 1325 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
bogdanm 73:1efda918f0ba 1326 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
bogdanm 73:1efda918f0ba 1327 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
bogdanm 73:1efda918f0ba 1328 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
bogdanm 73:1efda918f0ba 1329 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
bogdanm 73:1efda918f0ba 1330 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
bogdanm 73:1efda918f0ba 1331 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
bogdanm 73:1efda918f0ba 1332 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
bogdanm 73:1efda918f0ba 1333 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
bogdanm 73:1efda918f0ba 1334 #define CEC_BASE (APB1PERIPH_BASE + 0x7800)
bogdanm 73:1efda918f0ba 1335
bogdanm 73:1efda918f0ba 1336 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
bogdanm 73:1efda918f0ba 1337 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
bogdanm 73:1efda918f0ba 1338 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
bogdanm 73:1efda918f0ba 1339 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
bogdanm 73:1efda918f0ba 1340 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
bogdanm 73:1efda918f0ba 1341 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
bogdanm 73:1efda918f0ba 1342 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
bogdanm 73:1efda918f0ba 1343 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
bogdanm 73:1efda918f0ba 1344 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
bogdanm 73:1efda918f0ba 1345 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
bogdanm 73:1efda918f0ba 1346 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
bogdanm 73:1efda918f0ba 1347 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
bogdanm 73:1efda918f0ba 1348 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
bogdanm 73:1efda918f0ba 1349 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
bogdanm 73:1efda918f0ba 1350 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
bogdanm 73:1efda918f0ba 1351 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
bogdanm 73:1efda918f0ba 1352 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
bogdanm 73:1efda918f0ba 1353 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
bogdanm 73:1efda918f0ba 1354 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
bogdanm 73:1efda918f0ba 1355 #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
bogdanm 73:1efda918f0ba 1356 #define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
bogdanm 73:1efda918f0ba 1357 #define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
bogdanm 73:1efda918f0ba 1358
bogdanm 73:1efda918f0ba 1359 #define SDIO_BASE (PERIPH_BASE + 0x18000)
bogdanm 73:1efda918f0ba 1360
bogdanm 73:1efda918f0ba 1361 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
bogdanm 73:1efda918f0ba 1362 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
bogdanm 73:1efda918f0ba 1363 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
bogdanm 73:1efda918f0ba 1364 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
bogdanm 73:1efda918f0ba 1365 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
bogdanm 73:1efda918f0ba 1366 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
bogdanm 73:1efda918f0ba 1367 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
bogdanm 73:1efda918f0ba 1368 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
bogdanm 73:1efda918f0ba 1369 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
bogdanm 73:1efda918f0ba 1370 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
bogdanm 73:1efda918f0ba 1371 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
bogdanm 73:1efda918f0ba 1372 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
bogdanm 73:1efda918f0ba 1373 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
bogdanm 73:1efda918f0ba 1374 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
bogdanm 73:1efda918f0ba 1375 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
bogdanm 73:1efda918f0ba 1376 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
bogdanm 73:1efda918f0ba 1377
bogdanm 73:1efda918f0ba 1378 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
bogdanm 73:1efda918f0ba 1379 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
bogdanm 73:1efda918f0ba 1380
bogdanm 73:1efda918f0ba 1381 #define ETH_BASE (AHBPERIPH_BASE + 0x8000)
bogdanm 73:1efda918f0ba 1382 #define ETH_MAC_BASE (ETH_BASE)
bogdanm 73:1efda918f0ba 1383 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
bogdanm 73:1efda918f0ba 1384 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
bogdanm 73:1efda918f0ba 1385 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
bogdanm 73:1efda918f0ba 1386
bogdanm 73:1efda918f0ba 1387 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
bogdanm 73:1efda918f0ba 1388 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
bogdanm 73:1efda918f0ba 1389 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
bogdanm 73:1efda918f0ba 1390 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
bogdanm 73:1efda918f0ba 1391 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
bogdanm 73:1efda918f0ba 1392
bogdanm 73:1efda918f0ba 1393 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
bogdanm 73:1efda918f0ba 1394
bogdanm 73:1efda918f0ba 1395 /**
bogdanm 73:1efda918f0ba 1396 * @}
bogdanm 73:1efda918f0ba 1397 */
bogdanm 73:1efda918f0ba 1398
bogdanm 73:1efda918f0ba 1399 /** @addtogroup Peripheral_declaration
bogdanm 73:1efda918f0ba 1400 * @{
bogdanm 73:1efda918f0ba 1401 */
bogdanm 73:1efda918f0ba 1402
bogdanm 73:1efda918f0ba 1403 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 73:1efda918f0ba 1404 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 73:1efda918f0ba 1405 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm 73:1efda918f0ba 1406 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
bogdanm 73:1efda918f0ba 1407 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 73:1efda918f0ba 1408 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 73:1efda918f0ba 1409 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
bogdanm 73:1efda918f0ba 1410 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
bogdanm 73:1efda918f0ba 1411 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm 73:1efda918f0ba 1412 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 73:1efda918f0ba 1413 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 73:1efda918f0ba 1414 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 73:1efda918f0ba 1415 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 73:1efda918f0ba 1416 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm 73:1efda918f0ba 1417 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 73:1efda918f0ba 1418 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 73:1efda918f0ba 1419 #define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm 73:1efda918f0ba 1420 #define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm 73:1efda918f0ba 1421 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 73:1efda918f0ba 1422 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 73:1efda918f0ba 1423 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm 73:1efda918f0ba 1424 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
bogdanm 73:1efda918f0ba 1425 #define BKP ((BKP_TypeDef *) BKP_BASE)
bogdanm 73:1efda918f0ba 1426 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 73:1efda918f0ba 1427 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 73:1efda918f0ba 1428 #define CEC ((CEC_TypeDef *) CEC_BASE)
bogdanm 73:1efda918f0ba 1429 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
bogdanm 73:1efda918f0ba 1430 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 73:1efda918f0ba 1431 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 73:1efda918f0ba 1432 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 73:1efda918f0ba 1433 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 73:1efda918f0ba 1434 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 73:1efda918f0ba 1435 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 73:1efda918f0ba 1436 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 73:1efda918f0ba 1437 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
bogdanm 73:1efda918f0ba 1438 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 73:1efda918f0ba 1439 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm 73:1efda918f0ba 1440 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 73:1efda918f0ba 1441 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 73:1efda918f0ba 1442 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm 73:1efda918f0ba 1443 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 73:1efda918f0ba 1444 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm 73:1efda918f0ba 1445 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm 73:1efda918f0ba 1446 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm 73:1efda918f0ba 1447 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm 73:1efda918f0ba 1448 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
bogdanm 73:1efda918f0ba 1449 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
bogdanm 73:1efda918f0ba 1450 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
bogdanm 73:1efda918f0ba 1451 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
bogdanm 73:1efda918f0ba 1452 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 73:1efda918f0ba 1453 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm 73:1efda918f0ba 1454 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm 73:1efda918f0ba 1455 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm 73:1efda918f0ba 1456 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm 73:1efda918f0ba 1457 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm 73:1efda918f0ba 1458 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm 73:1efda918f0ba 1459 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm 73:1efda918f0ba 1460 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm 73:1efda918f0ba 1461 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
bogdanm 73:1efda918f0ba 1462 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
bogdanm 73:1efda918f0ba 1463 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
bogdanm 73:1efda918f0ba 1464 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
bogdanm 73:1efda918f0ba 1465 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
bogdanm 73:1efda918f0ba 1466 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 73:1efda918f0ba 1467 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 73:1efda918f0ba 1468 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 73:1efda918f0ba 1469 #define OB ((OB_TypeDef *) OB_BASE)
bogdanm 73:1efda918f0ba 1470 #define ETH ((ETH_TypeDef *) ETH_BASE)
bogdanm 73:1efda918f0ba 1471 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
bogdanm 73:1efda918f0ba 1472 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
bogdanm 73:1efda918f0ba 1473 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
bogdanm 73:1efda918f0ba 1474 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
bogdanm 73:1efda918f0ba 1475 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
bogdanm 73:1efda918f0ba 1476 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 73:1efda918f0ba 1477
bogdanm 73:1efda918f0ba 1478 /**
bogdanm 73:1efda918f0ba 1479 * @}
bogdanm 73:1efda918f0ba 1480 */
bogdanm 73:1efda918f0ba 1481
bogdanm 73:1efda918f0ba 1482 /** @addtogroup Exported_constants
bogdanm 73:1efda918f0ba 1483 * @{
bogdanm 73:1efda918f0ba 1484 */
bogdanm 73:1efda918f0ba 1485
bogdanm 73:1efda918f0ba 1486 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 73:1efda918f0ba 1487 * @{
bogdanm 73:1efda918f0ba 1488 */
bogdanm 73:1efda918f0ba 1489
bogdanm 73:1efda918f0ba 1490 /******************************************************************************/
bogdanm 73:1efda918f0ba 1491 /* Peripheral Registers_Bits_Definition */
bogdanm 73:1efda918f0ba 1492 /******************************************************************************/
bogdanm 73:1efda918f0ba 1493
bogdanm 73:1efda918f0ba 1494 /******************************************************************************/
bogdanm 73:1efda918f0ba 1495 /* */
bogdanm 73:1efda918f0ba 1496 /* CRC calculation unit */
bogdanm 73:1efda918f0ba 1497 /* */
bogdanm 73:1efda918f0ba 1498 /******************************************************************************/
bogdanm 73:1efda918f0ba 1499
bogdanm 73:1efda918f0ba 1500 /******************* Bit definition for CRC_DR register *********************/
bogdanm 73:1efda918f0ba 1501 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 73:1efda918f0ba 1502
bogdanm 73:1efda918f0ba 1503
bogdanm 73:1efda918f0ba 1504 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 73:1efda918f0ba 1505 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
bogdanm 73:1efda918f0ba 1506
bogdanm 73:1efda918f0ba 1507
bogdanm 73:1efda918f0ba 1508 /******************** Bit definition for CRC_CR register ********************/
bogdanm 73:1efda918f0ba 1509 #define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
bogdanm 73:1efda918f0ba 1510
bogdanm 73:1efda918f0ba 1511 /******************************************************************************/
bogdanm 73:1efda918f0ba 1512 /* */
bogdanm 73:1efda918f0ba 1513 /* Power Control */
bogdanm 73:1efda918f0ba 1514 /* */
bogdanm 73:1efda918f0ba 1515 /******************************************************************************/
bogdanm 73:1efda918f0ba 1516
bogdanm 73:1efda918f0ba 1517 /******************** Bit definition for PWR_CR register ********************/
bogdanm 73:1efda918f0ba 1518 #define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
bogdanm 73:1efda918f0ba 1519 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
bogdanm 73:1efda918f0ba 1520 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
bogdanm 73:1efda918f0ba 1521 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
bogdanm 73:1efda918f0ba 1522 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
bogdanm 73:1efda918f0ba 1523
bogdanm 73:1efda918f0ba 1524 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 73:1efda918f0ba 1525 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1526 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1527 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 1528
bogdanm 73:1efda918f0ba 1529 /*!< PVD level configuration */
bogdanm 73:1efda918f0ba 1530 #define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
bogdanm 73:1efda918f0ba 1531 #define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
bogdanm 73:1efda918f0ba 1532 #define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
bogdanm 73:1efda918f0ba 1533 #define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
bogdanm 73:1efda918f0ba 1534 #define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
bogdanm 73:1efda918f0ba 1535 #define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
bogdanm 73:1efda918f0ba 1536 #define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
bogdanm 73:1efda918f0ba 1537 #define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
bogdanm 73:1efda918f0ba 1538
bogdanm 73:1efda918f0ba 1539 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
bogdanm 73:1efda918f0ba 1540
bogdanm 73:1efda918f0ba 1541
bogdanm 73:1efda918f0ba 1542 /******************* Bit definition for PWR_CSR register ********************/
bogdanm 73:1efda918f0ba 1543 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
bogdanm 73:1efda918f0ba 1544 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
bogdanm 73:1efda918f0ba 1545 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
bogdanm 73:1efda918f0ba 1546 #define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
bogdanm 73:1efda918f0ba 1547
bogdanm 73:1efda918f0ba 1548 /******************************************************************************/
bogdanm 73:1efda918f0ba 1549 /* */
bogdanm 73:1efda918f0ba 1550 /* Backup registers */
bogdanm 73:1efda918f0ba 1551 /* */
bogdanm 73:1efda918f0ba 1552 /******************************************************************************/
bogdanm 73:1efda918f0ba 1553
bogdanm 73:1efda918f0ba 1554 /******************* Bit definition for BKP_DR1 register ********************/
bogdanm 73:1efda918f0ba 1555 #define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1556
bogdanm 73:1efda918f0ba 1557 /******************* Bit definition for BKP_DR2 register ********************/
bogdanm 73:1efda918f0ba 1558 #define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1559
bogdanm 73:1efda918f0ba 1560 /******************* Bit definition for BKP_DR3 register ********************/
bogdanm 73:1efda918f0ba 1561 #define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1562
bogdanm 73:1efda918f0ba 1563 /******************* Bit definition for BKP_DR4 register ********************/
bogdanm 73:1efda918f0ba 1564 #define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1565
bogdanm 73:1efda918f0ba 1566 /******************* Bit definition for BKP_DR5 register ********************/
bogdanm 73:1efda918f0ba 1567 #define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1568
bogdanm 73:1efda918f0ba 1569 /******************* Bit definition for BKP_DR6 register ********************/
bogdanm 73:1efda918f0ba 1570 #define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1571
bogdanm 73:1efda918f0ba 1572 /******************* Bit definition for BKP_DR7 register ********************/
bogdanm 73:1efda918f0ba 1573 #define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1574
bogdanm 73:1efda918f0ba 1575 /******************* Bit definition for BKP_DR8 register ********************/
bogdanm 73:1efda918f0ba 1576 #define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1577
bogdanm 73:1efda918f0ba 1578 /******************* Bit definition for BKP_DR9 register ********************/
bogdanm 73:1efda918f0ba 1579 #define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1580
bogdanm 73:1efda918f0ba 1581 /******************* Bit definition for BKP_DR10 register *******************/
bogdanm 73:1efda918f0ba 1582 #define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1583
bogdanm 73:1efda918f0ba 1584 /******************* Bit definition for BKP_DR11 register *******************/
bogdanm 73:1efda918f0ba 1585 #define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1586
bogdanm 73:1efda918f0ba 1587 /******************* Bit definition for BKP_DR12 register *******************/
bogdanm 73:1efda918f0ba 1588 #define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1589
bogdanm 73:1efda918f0ba 1590 /******************* Bit definition for BKP_DR13 register *******************/
bogdanm 73:1efda918f0ba 1591 #define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1592
bogdanm 73:1efda918f0ba 1593 /******************* Bit definition for BKP_DR14 register *******************/
bogdanm 73:1efda918f0ba 1594 #define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1595
bogdanm 73:1efda918f0ba 1596 /******************* Bit definition for BKP_DR15 register *******************/
bogdanm 73:1efda918f0ba 1597 #define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1598
bogdanm 73:1efda918f0ba 1599 /******************* Bit definition for BKP_DR16 register *******************/
bogdanm 73:1efda918f0ba 1600 #define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1601
bogdanm 73:1efda918f0ba 1602 /******************* Bit definition for BKP_DR17 register *******************/
bogdanm 73:1efda918f0ba 1603 #define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1604
bogdanm 73:1efda918f0ba 1605 /****************** Bit definition for BKP_DR18 register ********************/
bogdanm 73:1efda918f0ba 1606 #define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1607
bogdanm 73:1efda918f0ba 1608 /******************* Bit definition for BKP_DR19 register *******************/
bogdanm 73:1efda918f0ba 1609 #define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1610
bogdanm 73:1efda918f0ba 1611 /******************* Bit definition for BKP_DR20 register *******************/
bogdanm 73:1efda918f0ba 1612 #define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1613
bogdanm 73:1efda918f0ba 1614 /******************* Bit definition for BKP_DR21 register *******************/
bogdanm 73:1efda918f0ba 1615 #define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1616
bogdanm 73:1efda918f0ba 1617 /******************* Bit definition for BKP_DR22 register *******************/
bogdanm 73:1efda918f0ba 1618 #define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1619
bogdanm 73:1efda918f0ba 1620 /******************* Bit definition for BKP_DR23 register *******************/
bogdanm 73:1efda918f0ba 1621 #define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1622
bogdanm 73:1efda918f0ba 1623 /******************* Bit definition for BKP_DR24 register *******************/
bogdanm 73:1efda918f0ba 1624 #define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1625
bogdanm 73:1efda918f0ba 1626 /******************* Bit definition for BKP_DR25 register *******************/
bogdanm 73:1efda918f0ba 1627 #define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1628
bogdanm 73:1efda918f0ba 1629 /******************* Bit definition for BKP_DR26 register *******************/
bogdanm 73:1efda918f0ba 1630 #define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1631
bogdanm 73:1efda918f0ba 1632 /******************* Bit definition for BKP_DR27 register *******************/
bogdanm 73:1efda918f0ba 1633 #define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1634
bogdanm 73:1efda918f0ba 1635 /******************* Bit definition for BKP_DR28 register *******************/
bogdanm 73:1efda918f0ba 1636 #define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1637
bogdanm 73:1efda918f0ba 1638 /******************* Bit definition for BKP_DR29 register *******************/
bogdanm 73:1efda918f0ba 1639 #define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1640
bogdanm 73:1efda918f0ba 1641 /******************* Bit definition for BKP_DR30 register *******************/
bogdanm 73:1efda918f0ba 1642 #define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1643
bogdanm 73:1efda918f0ba 1644 /******************* Bit definition for BKP_DR31 register *******************/
bogdanm 73:1efda918f0ba 1645 #define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1646
bogdanm 73:1efda918f0ba 1647 /******************* Bit definition for BKP_DR32 register *******************/
bogdanm 73:1efda918f0ba 1648 #define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1649
bogdanm 73:1efda918f0ba 1650 /******************* Bit definition for BKP_DR33 register *******************/
bogdanm 73:1efda918f0ba 1651 #define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1652
bogdanm 73:1efda918f0ba 1653 /******************* Bit definition for BKP_DR34 register *******************/
bogdanm 73:1efda918f0ba 1654 #define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1655
bogdanm 73:1efda918f0ba 1656 /******************* Bit definition for BKP_DR35 register *******************/
bogdanm 73:1efda918f0ba 1657 #define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1658
bogdanm 73:1efda918f0ba 1659 /******************* Bit definition for BKP_DR36 register *******************/
bogdanm 73:1efda918f0ba 1660 #define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1661
bogdanm 73:1efda918f0ba 1662 /******************* Bit definition for BKP_DR37 register *******************/
bogdanm 73:1efda918f0ba 1663 #define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1664
bogdanm 73:1efda918f0ba 1665 /******************* Bit definition for BKP_DR38 register *******************/
bogdanm 73:1efda918f0ba 1666 #define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1667
bogdanm 73:1efda918f0ba 1668 /******************* Bit definition for BKP_DR39 register *******************/
bogdanm 73:1efda918f0ba 1669 #define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1670
bogdanm 73:1efda918f0ba 1671 /******************* Bit definition for BKP_DR40 register *******************/
bogdanm 73:1efda918f0ba 1672 #define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1673
bogdanm 73:1efda918f0ba 1674 /******************* Bit definition for BKP_DR41 register *******************/
bogdanm 73:1efda918f0ba 1675 #define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1676
bogdanm 73:1efda918f0ba 1677 /******************* Bit definition for BKP_DR42 register *******************/
bogdanm 73:1efda918f0ba 1678 #define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
bogdanm 73:1efda918f0ba 1679
bogdanm 73:1efda918f0ba 1680 /****************** Bit definition for BKP_RTCCR register *******************/
bogdanm 73:1efda918f0ba 1681 #define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
bogdanm 73:1efda918f0ba 1682 #define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
bogdanm 73:1efda918f0ba 1683 #define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
bogdanm 73:1efda918f0ba 1684 #define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
bogdanm 73:1efda918f0ba 1685
bogdanm 73:1efda918f0ba 1686 /******************** Bit definition for BKP_CR register ********************/
bogdanm 73:1efda918f0ba 1687 #define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
bogdanm 73:1efda918f0ba 1688 #define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
bogdanm 73:1efda918f0ba 1689
bogdanm 73:1efda918f0ba 1690 /******************* Bit definition for BKP_CSR register ********************/
bogdanm 73:1efda918f0ba 1691 #define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
bogdanm 73:1efda918f0ba 1692 #define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
bogdanm 73:1efda918f0ba 1693 #define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
bogdanm 73:1efda918f0ba 1694 #define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
bogdanm 73:1efda918f0ba 1695 #define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
bogdanm 73:1efda918f0ba 1696
bogdanm 73:1efda918f0ba 1697 /******************************************************************************/
bogdanm 73:1efda918f0ba 1698 /* */
bogdanm 73:1efda918f0ba 1699 /* Reset and Clock Control */
bogdanm 73:1efda918f0ba 1700 /* */
bogdanm 73:1efda918f0ba 1701 /******************************************************************************/
bogdanm 73:1efda918f0ba 1702
bogdanm 73:1efda918f0ba 1703 /******************** Bit definition for RCC_CR register ********************/
bogdanm 73:1efda918f0ba 1704 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
bogdanm 73:1efda918f0ba 1705 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
bogdanm 73:1efda918f0ba 1706 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
bogdanm 73:1efda918f0ba 1707 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
bogdanm 73:1efda918f0ba 1708 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
bogdanm 73:1efda918f0ba 1709 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
bogdanm 73:1efda918f0ba 1710 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
bogdanm 73:1efda918f0ba 1711 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
bogdanm 73:1efda918f0ba 1712 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
bogdanm 73:1efda918f0ba 1713 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
bogdanm 73:1efda918f0ba 1714
bogdanm 73:1efda918f0ba 1715 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 1716 #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
bogdanm 73:1efda918f0ba 1717 #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
bogdanm 73:1efda918f0ba 1718 #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
bogdanm 73:1efda918f0ba 1719 #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
bogdanm 73:1efda918f0ba 1720 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 1721
bogdanm 73:1efda918f0ba 1722 /******************* Bit definition for RCC_CFGR register *******************/
bogdanm 73:1efda918f0ba 1723 /*!< SW configuration */
bogdanm 73:1efda918f0ba 1724 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 73:1efda918f0ba 1725 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1726 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1727
bogdanm 73:1efda918f0ba 1728 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
bogdanm 73:1efda918f0ba 1729 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
bogdanm 73:1efda918f0ba 1730 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
bogdanm 73:1efda918f0ba 1731
bogdanm 73:1efda918f0ba 1732 /*!< SWS configuration */
bogdanm 73:1efda918f0ba 1733 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 73:1efda918f0ba 1734 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1735 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1736
bogdanm 73:1efda918f0ba 1737 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
bogdanm 73:1efda918f0ba 1738 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
bogdanm 73:1efda918f0ba 1739 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
bogdanm 73:1efda918f0ba 1740
bogdanm 73:1efda918f0ba 1741 /*!< HPRE configuration */
bogdanm 73:1efda918f0ba 1742 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 73:1efda918f0ba 1743 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1744 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1745 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 1746 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 1747
bogdanm 73:1efda918f0ba 1748 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 73:1efda918f0ba 1749 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 73:1efda918f0ba 1750 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 73:1efda918f0ba 1751 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 73:1efda918f0ba 1752 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 73:1efda918f0ba 1753 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 73:1efda918f0ba 1754 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 73:1efda918f0ba 1755 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 73:1efda918f0ba 1756 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 73:1efda918f0ba 1757
bogdanm 73:1efda918f0ba 1758 /*!< PPRE1 configuration */
bogdanm 73:1efda918f0ba 1759 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
bogdanm 73:1efda918f0ba 1760 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1761 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1762 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 1763
bogdanm 73:1efda918f0ba 1764 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 73:1efda918f0ba 1765 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
bogdanm 73:1efda918f0ba 1766 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
bogdanm 73:1efda918f0ba 1767 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
bogdanm 73:1efda918f0ba 1768 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
bogdanm 73:1efda918f0ba 1769
bogdanm 73:1efda918f0ba 1770 /*!< PPRE2 configuration */
bogdanm 73:1efda918f0ba 1771 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
bogdanm 73:1efda918f0ba 1772 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1773 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1774 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 1775
bogdanm 73:1efda918f0ba 1776 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 73:1efda918f0ba 1777 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
bogdanm 73:1efda918f0ba 1778 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
bogdanm 73:1efda918f0ba 1779 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
bogdanm 73:1efda918f0ba 1780 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
bogdanm 73:1efda918f0ba 1781
bogdanm 73:1efda918f0ba 1782 /*!< ADCPPRE configuration */
bogdanm 73:1efda918f0ba 1783 #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
bogdanm 73:1efda918f0ba 1784 #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1785 #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1786
bogdanm 73:1efda918f0ba 1787 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
bogdanm 73:1efda918f0ba 1788 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
bogdanm 73:1efda918f0ba 1789 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
bogdanm 73:1efda918f0ba 1790 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
bogdanm 73:1efda918f0ba 1791
bogdanm 73:1efda918f0ba 1792 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
bogdanm 73:1efda918f0ba 1793
bogdanm 73:1efda918f0ba 1794 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
bogdanm 73:1efda918f0ba 1795
bogdanm 73:1efda918f0ba 1796 /*!< PLLMUL configuration */
bogdanm 73:1efda918f0ba 1797 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
bogdanm 73:1efda918f0ba 1798 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1799 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1800 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 1801 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 1802
bogdanm 73:1efda918f0ba 1803 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 1804 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
bogdanm 73:1efda918f0ba 1805 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
bogdanm 73:1efda918f0ba 1806
bogdanm 73:1efda918f0ba 1807 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
bogdanm 73:1efda918f0ba 1808 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
bogdanm 73:1efda918f0ba 1809
bogdanm 73:1efda918f0ba 1810 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
bogdanm 73:1efda918f0ba 1811 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
bogdanm 73:1efda918f0ba 1812 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
bogdanm 73:1efda918f0ba 1813 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
bogdanm 73:1efda918f0ba 1814 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
bogdanm 73:1efda918f0ba 1815 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
bogdanm 73:1efda918f0ba 1816 #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
bogdanm 73:1efda918f0ba 1817
bogdanm 73:1efda918f0ba 1818 #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */
bogdanm 73:1efda918f0ba 1819
bogdanm 73:1efda918f0ba 1820 /*!< MCO configuration */
bogdanm 73:1efda918f0ba 1821 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
bogdanm 73:1efda918f0ba 1822 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1823 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1824 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 1825 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 1826
bogdanm 73:1efda918f0ba 1827 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 73:1efda918f0ba 1828 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
bogdanm 73:1efda918f0ba 1829 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
bogdanm 73:1efda918f0ba 1830 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
bogdanm 73:1efda918f0ba 1831 #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
bogdanm 73:1efda918f0ba 1832 #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
bogdanm 73:1efda918f0ba 1833 #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
bogdanm 73:1efda918f0ba 1834 #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
bogdanm 73:1efda918f0ba 1835 #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
bogdanm 73:1efda918f0ba 1836 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 1837 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
bogdanm 73:1efda918f0ba 1838 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
bogdanm 73:1efda918f0ba 1839
bogdanm 73:1efda918f0ba 1840 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
bogdanm 73:1efda918f0ba 1841 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
bogdanm 73:1efda918f0ba 1842
bogdanm 73:1efda918f0ba 1843 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
bogdanm 73:1efda918f0ba 1844 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
bogdanm 73:1efda918f0ba 1845 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
bogdanm 73:1efda918f0ba 1846 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
bogdanm 73:1efda918f0ba 1847 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
bogdanm 73:1efda918f0ba 1848 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
bogdanm 73:1efda918f0ba 1849 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
bogdanm 73:1efda918f0ba 1850 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
bogdanm 73:1efda918f0ba 1851 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
bogdanm 73:1efda918f0ba 1852 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
bogdanm 73:1efda918f0ba 1853 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
bogdanm 73:1efda918f0ba 1854 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
bogdanm 73:1efda918f0ba 1855 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
bogdanm 73:1efda918f0ba 1856 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
bogdanm 73:1efda918f0ba 1857 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
bogdanm 73:1efda918f0ba 1858
bogdanm 73:1efda918f0ba 1859 /*!< MCO configuration */
bogdanm 73:1efda918f0ba 1860 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
bogdanm 73:1efda918f0ba 1861 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1862 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1863 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 1864
bogdanm 73:1efda918f0ba 1865 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 73:1efda918f0ba 1866 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
bogdanm 73:1efda918f0ba 1867 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
bogdanm 73:1efda918f0ba 1868 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
bogdanm 73:1efda918f0ba 1869 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
bogdanm 73:1efda918f0ba 1870 #else
bogdanm 73:1efda918f0ba 1871 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
bogdanm 73:1efda918f0ba 1872 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
bogdanm 73:1efda918f0ba 1873
bogdanm 73:1efda918f0ba 1874 #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
bogdanm 73:1efda918f0ba 1875 #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
bogdanm 73:1efda918f0ba 1876
bogdanm 73:1efda918f0ba 1877 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
bogdanm 73:1efda918f0ba 1878 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
bogdanm 73:1efda918f0ba 1879 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
bogdanm 73:1efda918f0ba 1880 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
bogdanm 73:1efda918f0ba 1881 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
bogdanm 73:1efda918f0ba 1882 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
bogdanm 73:1efda918f0ba 1883 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
bogdanm 73:1efda918f0ba 1884 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
bogdanm 73:1efda918f0ba 1885 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
bogdanm 73:1efda918f0ba 1886 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
bogdanm 73:1efda918f0ba 1887 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
bogdanm 73:1efda918f0ba 1888 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
bogdanm 73:1efda918f0ba 1889 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
bogdanm 73:1efda918f0ba 1890 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
bogdanm 73:1efda918f0ba 1891 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
bogdanm 73:1efda918f0ba 1892 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
bogdanm 73:1efda918f0ba 1893
bogdanm 73:1efda918f0ba 1894 /*!< MCO configuration */
bogdanm 73:1efda918f0ba 1895 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
bogdanm 73:1efda918f0ba 1896 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 1897 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 1898 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 1899
bogdanm 73:1efda918f0ba 1900 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 73:1efda918f0ba 1901 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
bogdanm 73:1efda918f0ba 1902 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
bogdanm 73:1efda918f0ba 1903 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
bogdanm 73:1efda918f0ba 1904 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
bogdanm 73:1efda918f0ba 1905 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 1906
bogdanm 73:1efda918f0ba 1907 /*!<****************** Bit definition for RCC_CIR register ********************/
bogdanm 73:1efda918f0ba 1908 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
bogdanm 73:1efda918f0ba 1909 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
bogdanm 73:1efda918f0ba 1910 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
bogdanm 73:1efda918f0ba 1911 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
bogdanm 73:1efda918f0ba 1912 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
bogdanm 73:1efda918f0ba 1913 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
bogdanm 73:1efda918f0ba 1914 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
bogdanm 73:1efda918f0ba 1915 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
bogdanm 73:1efda918f0ba 1916 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
bogdanm 73:1efda918f0ba 1917 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
bogdanm 73:1efda918f0ba 1918 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
bogdanm 73:1efda918f0ba 1919 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
bogdanm 73:1efda918f0ba 1920 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
bogdanm 73:1efda918f0ba 1921 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
bogdanm 73:1efda918f0ba 1922 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
bogdanm 73:1efda918f0ba 1923 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
bogdanm 73:1efda918f0ba 1924 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
bogdanm 73:1efda918f0ba 1925
bogdanm 73:1efda918f0ba 1926 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 1927 #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
bogdanm 73:1efda918f0ba 1928 #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
bogdanm 73:1efda918f0ba 1929 #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
bogdanm 73:1efda918f0ba 1930 #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
bogdanm 73:1efda918f0ba 1931 #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
bogdanm 73:1efda918f0ba 1932 #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
bogdanm 73:1efda918f0ba 1933 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 1934
bogdanm 73:1efda918f0ba 1935 /***************** Bit definition for RCC_APB2RSTR register *****************/
bogdanm 73:1efda918f0ba 1936 #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
bogdanm 73:1efda918f0ba 1937 #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
bogdanm 73:1efda918f0ba 1938 #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
bogdanm 73:1efda918f0ba 1939 #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
bogdanm 73:1efda918f0ba 1940 #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
bogdanm 73:1efda918f0ba 1941 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
bogdanm 73:1efda918f0ba 1942
bogdanm 73:1efda918f0ba 1943 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 1944 #define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
bogdanm 73:1efda918f0ba 1945 #endif
bogdanm 73:1efda918f0ba 1946
bogdanm 73:1efda918f0ba 1947 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
bogdanm 73:1efda918f0ba 1948 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
bogdanm 73:1efda918f0ba 1949 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
bogdanm 73:1efda918f0ba 1950
bogdanm 73:1efda918f0ba 1951 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 1952 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
bogdanm 73:1efda918f0ba 1953 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
bogdanm 73:1efda918f0ba 1954 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
bogdanm 73:1efda918f0ba 1955 #endif
bogdanm 73:1efda918f0ba 1956
bogdanm 73:1efda918f0ba 1957 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
bogdanm 73:1efda918f0ba 1958 #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
bogdanm 73:1efda918f0ba 1959 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
bogdanm 73:1efda918f0ba 1960
bogdanm 73:1efda918f0ba 1961 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
bogdanm 73:1efda918f0ba 1962 #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
bogdanm 73:1efda918f0ba 1963 #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
bogdanm 73:1efda918f0ba 1964 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
bogdanm 73:1efda918f0ba 1965 #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */
bogdanm 73:1efda918f0ba 1966 #endif
bogdanm 73:1efda918f0ba 1967
bogdanm 73:1efda918f0ba 1968 #if defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 1969 #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
bogdanm 73:1efda918f0ba 1970 #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
bogdanm 73:1efda918f0ba 1971 #endif
bogdanm 73:1efda918f0ba 1972
bogdanm 73:1efda918f0ba 1973 #ifdef STM32F10X_XL
bogdanm 73:1efda918f0ba 1974 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */
bogdanm 73:1efda918f0ba 1975 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */
bogdanm 73:1efda918f0ba 1976 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */
bogdanm 73:1efda918f0ba 1977 #endif /* STM32F10X_XL */
bogdanm 73:1efda918f0ba 1978
bogdanm 73:1efda918f0ba 1979 /***************** Bit definition for RCC_APB1RSTR register *****************/
bogdanm 73:1efda918f0ba 1980 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
bogdanm 73:1efda918f0ba 1981 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
bogdanm 73:1efda918f0ba 1982 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
bogdanm 73:1efda918f0ba 1983 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
bogdanm 73:1efda918f0ba 1984 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
bogdanm 73:1efda918f0ba 1985
bogdanm 73:1efda918f0ba 1986 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 1987 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
bogdanm 73:1efda918f0ba 1988 #endif
bogdanm 73:1efda918f0ba 1989
bogdanm 73:1efda918f0ba 1990 #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
bogdanm 73:1efda918f0ba 1991 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
bogdanm 73:1efda918f0ba 1992
bogdanm 73:1efda918f0ba 1993 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
bogdanm 73:1efda918f0ba 1994 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
bogdanm 73:1efda918f0ba 1995 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
bogdanm 73:1efda918f0ba 1996 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
bogdanm 73:1efda918f0ba 1997 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
bogdanm 73:1efda918f0ba 1998 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
bogdanm 73:1efda918f0ba 1999
bogdanm 73:1efda918f0ba 2000 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
bogdanm 73:1efda918f0ba 2001 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
bogdanm 73:1efda918f0ba 2002 #endif
bogdanm 73:1efda918f0ba 2003
bogdanm 73:1efda918f0ba 2004 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
bogdanm 73:1efda918f0ba 2005 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
bogdanm 73:1efda918f0ba 2006 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
bogdanm 73:1efda918f0ba 2007 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
bogdanm 73:1efda918f0ba 2008 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
bogdanm 73:1efda918f0ba 2009 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
bogdanm 73:1efda918f0ba 2010 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
bogdanm 73:1efda918f0ba 2011 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
bogdanm 73:1efda918f0ba 2012 #endif
bogdanm 73:1efda918f0ba 2013
bogdanm 73:1efda918f0ba 2014 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2015 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
bogdanm 73:1efda918f0ba 2016 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
bogdanm 73:1efda918f0ba 2017 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
bogdanm 73:1efda918f0ba 2018 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
bogdanm 73:1efda918f0ba 2019 #endif
bogdanm 73:1efda918f0ba 2020
bogdanm 73:1efda918f0ba 2021 #if defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2022 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
bogdanm 73:1efda918f0ba 2023 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
bogdanm 73:1efda918f0ba 2024 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
bogdanm 73:1efda918f0ba 2025 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
bogdanm 73:1efda918f0ba 2026 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
bogdanm 73:1efda918f0ba 2027 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
bogdanm 73:1efda918f0ba 2028 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
bogdanm 73:1efda918f0ba 2029 #endif
bogdanm 73:1efda918f0ba 2030
bogdanm 73:1efda918f0ba 2031 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 2032 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */
bogdanm 73:1efda918f0ba 2033 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 2034
bogdanm 73:1efda918f0ba 2035 #ifdef STM32F10X_XL
bogdanm 73:1efda918f0ba 2036 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
bogdanm 73:1efda918f0ba 2037 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
bogdanm 73:1efda918f0ba 2038 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
bogdanm 73:1efda918f0ba 2039 #endif /* STM32F10X_XL */
bogdanm 73:1efda918f0ba 2040
bogdanm 73:1efda918f0ba 2041 /****************** Bit definition for RCC_AHBENR register ******************/
bogdanm 73:1efda918f0ba 2042 #define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
bogdanm 73:1efda918f0ba 2043 #define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
bogdanm 73:1efda918f0ba 2044 #define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
bogdanm 73:1efda918f0ba 2045 #define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
bogdanm 73:1efda918f0ba 2046
emilmont 77:869cf507173a 2047 #if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2048 #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
bogdanm 73:1efda918f0ba 2049 #endif
bogdanm 73:1efda918f0ba 2050
bogdanm 73:1efda918f0ba 2051 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
bogdanm 73:1efda918f0ba 2052 #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
bogdanm 73:1efda918f0ba 2053 #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
bogdanm 73:1efda918f0ba 2054 #endif
bogdanm 73:1efda918f0ba 2055
bogdanm 73:1efda918f0ba 2056 #if defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2057 #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
bogdanm 73:1efda918f0ba 2058 #endif
bogdanm 73:1efda918f0ba 2059
bogdanm 73:1efda918f0ba 2060 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 2061 #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
bogdanm 73:1efda918f0ba 2062 #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
bogdanm 73:1efda918f0ba 2063 #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
bogdanm 73:1efda918f0ba 2064 #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
bogdanm 73:1efda918f0ba 2065 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 2066
bogdanm 73:1efda918f0ba 2067 /****************** Bit definition for RCC_APB2ENR register *****************/
bogdanm 73:1efda918f0ba 2068 #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
bogdanm 73:1efda918f0ba 2069 #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
bogdanm 73:1efda918f0ba 2070 #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
bogdanm 73:1efda918f0ba 2071 #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
bogdanm 73:1efda918f0ba 2072 #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
bogdanm 73:1efda918f0ba 2073 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
bogdanm 73:1efda918f0ba 2074
bogdanm 73:1efda918f0ba 2075 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2076 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
bogdanm 73:1efda918f0ba 2077 #endif
bogdanm 73:1efda918f0ba 2078
bogdanm 73:1efda918f0ba 2079 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
bogdanm 73:1efda918f0ba 2080 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
bogdanm 73:1efda918f0ba 2081 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
bogdanm 73:1efda918f0ba 2082
bogdanm 73:1efda918f0ba 2083 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2084 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
bogdanm 73:1efda918f0ba 2085 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
bogdanm 73:1efda918f0ba 2086 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
bogdanm 73:1efda918f0ba 2087 #endif
bogdanm 73:1efda918f0ba 2088
bogdanm 73:1efda918f0ba 2089 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
bogdanm 73:1efda918f0ba 2090 #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
bogdanm 73:1efda918f0ba 2091 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
bogdanm 73:1efda918f0ba 2092
bogdanm 73:1efda918f0ba 2093 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
bogdanm 73:1efda918f0ba 2094 #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
bogdanm 73:1efda918f0ba 2095 #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
bogdanm 73:1efda918f0ba 2096 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
bogdanm 73:1efda918f0ba 2097 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */
bogdanm 73:1efda918f0ba 2098 #endif
bogdanm 73:1efda918f0ba 2099
bogdanm 73:1efda918f0ba 2100 #if defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2101 #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
bogdanm 73:1efda918f0ba 2102 #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
bogdanm 73:1efda918f0ba 2103 #endif
bogdanm 73:1efda918f0ba 2104
bogdanm 73:1efda918f0ba 2105 #ifdef STM32F10X_XL
bogdanm 73:1efda918f0ba 2106 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */
bogdanm 73:1efda918f0ba 2107 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */
bogdanm 73:1efda918f0ba 2108 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */
bogdanm 73:1efda918f0ba 2109 #endif
bogdanm 73:1efda918f0ba 2110
bogdanm 73:1efda918f0ba 2111 /***************** Bit definition for RCC_APB1ENR register ******************/
bogdanm 73:1efda918f0ba 2112 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
bogdanm 73:1efda918f0ba 2113 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
bogdanm 73:1efda918f0ba 2114 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
bogdanm 73:1efda918f0ba 2115 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
bogdanm 73:1efda918f0ba 2116 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
bogdanm 73:1efda918f0ba 2117
bogdanm 73:1efda918f0ba 2118 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2119 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
bogdanm 73:1efda918f0ba 2120 #endif
bogdanm 73:1efda918f0ba 2121
bogdanm 73:1efda918f0ba 2122 #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
bogdanm 73:1efda918f0ba 2123 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
bogdanm 73:1efda918f0ba 2124
bogdanm 73:1efda918f0ba 2125 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
bogdanm 73:1efda918f0ba 2126 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
bogdanm 73:1efda918f0ba 2127 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
bogdanm 73:1efda918f0ba 2128 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
bogdanm 73:1efda918f0ba 2129 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
bogdanm 73:1efda918f0ba 2130 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
bogdanm 73:1efda918f0ba 2131
bogdanm 73:1efda918f0ba 2132 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
bogdanm 73:1efda918f0ba 2133 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
bogdanm 73:1efda918f0ba 2134 #endif
bogdanm 73:1efda918f0ba 2135
bogdanm 73:1efda918f0ba 2136 #if defined (STM32F10X_HD) || defined (STM32F10X_CL)
bogdanm 73:1efda918f0ba 2137 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
bogdanm 73:1efda918f0ba 2138 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
bogdanm 73:1efda918f0ba 2139 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
bogdanm 73:1efda918f0ba 2140 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
bogdanm 73:1efda918f0ba 2141 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
bogdanm 73:1efda918f0ba 2142 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
bogdanm 73:1efda918f0ba 2143 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
bogdanm 73:1efda918f0ba 2144 #endif
bogdanm 73:1efda918f0ba 2145
bogdanm 73:1efda918f0ba 2146 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2147 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
bogdanm 73:1efda918f0ba 2148 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
bogdanm 73:1efda918f0ba 2149 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
bogdanm 73:1efda918f0ba 2150 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
bogdanm 73:1efda918f0ba 2151 #endif
bogdanm 73:1efda918f0ba 2152
bogdanm 73:1efda918f0ba 2153 #ifdef STM32F10X_HD_VL
bogdanm 73:1efda918f0ba 2154 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
bogdanm 73:1efda918f0ba 2155 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
bogdanm 73:1efda918f0ba 2156 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
bogdanm 73:1efda918f0ba 2157 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
bogdanm 73:1efda918f0ba 2158 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
bogdanm 73:1efda918f0ba 2159 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
bogdanm 73:1efda918f0ba 2160 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
bogdanm 73:1efda918f0ba 2161 #endif /* STM32F10X_HD_VL */
bogdanm 73:1efda918f0ba 2162
bogdanm 73:1efda918f0ba 2163 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 2164 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */
bogdanm 73:1efda918f0ba 2165 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 2166
bogdanm 73:1efda918f0ba 2167 #ifdef STM32F10X_XL
bogdanm 73:1efda918f0ba 2168 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
bogdanm 73:1efda918f0ba 2169 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
bogdanm 73:1efda918f0ba 2170 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
bogdanm 73:1efda918f0ba 2171 #endif /* STM32F10X_XL */
bogdanm 73:1efda918f0ba 2172
bogdanm 73:1efda918f0ba 2173 /******************* Bit definition for RCC_BDCR register *******************/
bogdanm 73:1efda918f0ba 2174 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
bogdanm 73:1efda918f0ba 2175 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
bogdanm 73:1efda918f0ba 2176 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
bogdanm 73:1efda918f0ba 2177
bogdanm 73:1efda918f0ba 2178 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
bogdanm 73:1efda918f0ba 2179 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2180 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2181
bogdanm 73:1efda918f0ba 2182 /*!< RTC congiguration */
bogdanm 73:1efda918f0ba 2183 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 73:1efda918f0ba 2184 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
bogdanm 73:1efda918f0ba 2185 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
bogdanm 73:1efda918f0ba 2186 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
bogdanm 73:1efda918f0ba 2187
bogdanm 73:1efda918f0ba 2188 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
bogdanm 73:1efda918f0ba 2189 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
bogdanm 73:1efda918f0ba 2190
bogdanm 73:1efda918f0ba 2191 /******************* Bit definition for RCC_CSR register ********************/
bogdanm 73:1efda918f0ba 2192 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
bogdanm 73:1efda918f0ba 2193 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
bogdanm 73:1efda918f0ba 2194 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
bogdanm 73:1efda918f0ba 2195 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
bogdanm 73:1efda918f0ba 2196 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
bogdanm 73:1efda918f0ba 2197 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
bogdanm 73:1efda918f0ba 2198 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
bogdanm 73:1efda918f0ba 2199 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
bogdanm 73:1efda918f0ba 2200 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
bogdanm 73:1efda918f0ba 2201
bogdanm 73:1efda918f0ba 2202 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 2203 /******************* Bit definition for RCC_AHBRSTR register ****************/
bogdanm 73:1efda918f0ba 2204 #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
bogdanm 73:1efda918f0ba 2205 #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
bogdanm 73:1efda918f0ba 2206
bogdanm 73:1efda918f0ba 2207 /******************* Bit definition for RCC_CFGR2 register ******************/
bogdanm 73:1efda918f0ba 2208 /*!< PREDIV1 configuration */
bogdanm 73:1efda918f0ba 2209 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
bogdanm 73:1efda918f0ba 2210 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2211 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2212 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 2213 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 2214
bogdanm 73:1efda918f0ba 2215 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
bogdanm 73:1efda918f0ba 2216 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
bogdanm 73:1efda918f0ba 2217 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
bogdanm 73:1efda918f0ba 2218 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
bogdanm 73:1efda918f0ba 2219 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
bogdanm 73:1efda918f0ba 2220 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
bogdanm 73:1efda918f0ba 2221 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
bogdanm 73:1efda918f0ba 2222 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
bogdanm 73:1efda918f0ba 2223 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
bogdanm 73:1efda918f0ba 2224 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
bogdanm 73:1efda918f0ba 2225 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
bogdanm 73:1efda918f0ba 2226 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
bogdanm 73:1efda918f0ba 2227 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
bogdanm 73:1efda918f0ba 2228 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
bogdanm 73:1efda918f0ba 2229 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
bogdanm 73:1efda918f0ba 2230 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
bogdanm 73:1efda918f0ba 2231
bogdanm 73:1efda918f0ba 2232 /*!< PREDIV2 configuration */
bogdanm 73:1efda918f0ba 2233 #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
bogdanm 73:1efda918f0ba 2234 #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2235 #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2236 #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 2237 #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 2238
bogdanm 73:1efda918f0ba 2239 #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
bogdanm 73:1efda918f0ba 2240 #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
bogdanm 73:1efda918f0ba 2241 #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
bogdanm 73:1efda918f0ba 2242 #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
bogdanm 73:1efda918f0ba 2243 #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
bogdanm 73:1efda918f0ba 2244 #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
bogdanm 73:1efda918f0ba 2245 #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
bogdanm 73:1efda918f0ba 2246 #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
bogdanm 73:1efda918f0ba 2247 #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
bogdanm 73:1efda918f0ba 2248 #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
bogdanm 73:1efda918f0ba 2249 #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
bogdanm 73:1efda918f0ba 2250 #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
bogdanm 73:1efda918f0ba 2251 #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
bogdanm 73:1efda918f0ba 2252 #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
bogdanm 73:1efda918f0ba 2253 #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
bogdanm 73:1efda918f0ba 2254 #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
bogdanm 73:1efda918f0ba 2255
bogdanm 73:1efda918f0ba 2256 /*!< PLL2MUL configuration */
bogdanm 73:1efda918f0ba 2257 #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
bogdanm 73:1efda918f0ba 2258 #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2259 #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2260 #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 2261 #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 2262
bogdanm 73:1efda918f0ba 2263 #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
bogdanm 73:1efda918f0ba 2264 #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
bogdanm 73:1efda918f0ba 2265 #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
bogdanm 73:1efda918f0ba 2266 #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
bogdanm 73:1efda918f0ba 2267 #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
bogdanm 73:1efda918f0ba 2268 #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
bogdanm 73:1efda918f0ba 2269 #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
bogdanm 73:1efda918f0ba 2270 #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
bogdanm 73:1efda918f0ba 2271 #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
bogdanm 73:1efda918f0ba 2272
bogdanm 73:1efda918f0ba 2273 /*!< PLL3MUL configuration */
bogdanm 73:1efda918f0ba 2274 #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
bogdanm 73:1efda918f0ba 2275 #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2276 #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2277 #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 2278 #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 2279
bogdanm 73:1efda918f0ba 2280 #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
bogdanm 73:1efda918f0ba 2281 #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
bogdanm 73:1efda918f0ba 2282 #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
bogdanm 73:1efda918f0ba 2283 #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
bogdanm 73:1efda918f0ba 2284 #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
bogdanm 73:1efda918f0ba 2285 #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
bogdanm 73:1efda918f0ba 2286 #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
bogdanm 73:1efda918f0ba 2287 #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
bogdanm 73:1efda918f0ba 2288 #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
bogdanm 73:1efda918f0ba 2289
bogdanm 73:1efda918f0ba 2290 #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
bogdanm 73:1efda918f0ba 2291 #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
bogdanm 73:1efda918f0ba 2292 #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
bogdanm 73:1efda918f0ba 2293 #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
bogdanm 73:1efda918f0ba 2294 #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
bogdanm 73:1efda918f0ba 2295 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 2296
bogdanm 73:1efda918f0ba 2297 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2298 /******************* Bit definition for RCC_CFGR2 register ******************/
bogdanm 73:1efda918f0ba 2299 /*!< PREDIV1 configuration */
bogdanm 73:1efda918f0ba 2300 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
bogdanm 73:1efda918f0ba 2301 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2302 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2303 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 2304 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 2305
bogdanm 73:1efda918f0ba 2306 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
bogdanm 73:1efda918f0ba 2307 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
bogdanm 73:1efda918f0ba 2308 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
bogdanm 73:1efda918f0ba 2309 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
bogdanm 73:1efda918f0ba 2310 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
bogdanm 73:1efda918f0ba 2311 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
bogdanm 73:1efda918f0ba 2312 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
bogdanm 73:1efda918f0ba 2313 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
bogdanm 73:1efda918f0ba 2314 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
bogdanm 73:1efda918f0ba 2315 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
bogdanm 73:1efda918f0ba 2316 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
bogdanm 73:1efda918f0ba 2317 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
bogdanm 73:1efda918f0ba 2318 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
bogdanm 73:1efda918f0ba 2319 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
bogdanm 73:1efda918f0ba 2320 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
bogdanm 73:1efda918f0ba 2321 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
bogdanm 73:1efda918f0ba 2322 #endif
bogdanm 73:1efda918f0ba 2323
bogdanm 73:1efda918f0ba 2324 /******************************************************************************/
bogdanm 73:1efda918f0ba 2325 /* */
bogdanm 73:1efda918f0ba 2326 /* General Purpose and Alternate Function I/O */
bogdanm 73:1efda918f0ba 2327 /* */
bogdanm 73:1efda918f0ba 2328 /******************************************************************************/
bogdanm 73:1efda918f0ba 2329
bogdanm 73:1efda918f0ba 2330 /******************* Bit definition for GPIO_CRL register *******************/
bogdanm 73:1efda918f0ba 2331 #define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
bogdanm 73:1efda918f0ba 2332
bogdanm 73:1efda918f0ba 2333 #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
bogdanm 73:1efda918f0ba 2334 #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2335 #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2336
bogdanm 73:1efda918f0ba 2337 #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
bogdanm 73:1efda918f0ba 2338 #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2339 #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2340
bogdanm 73:1efda918f0ba 2341 #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
bogdanm 73:1efda918f0ba 2342 #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2343 #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2344
bogdanm 73:1efda918f0ba 2345 #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
bogdanm 73:1efda918f0ba 2346 #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2347 #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2348
bogdanm 73:1efda918f0ba 2349 #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
bogdanm 73:1efda918f0ba 2350 #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2351 #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2352
bogdanm 73:1efda918f0ba 2353 #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
bogdanm 73:1efda918f0ba 2354 #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2355 #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2356
bogdanm 73:1efda918f0ba 2357 #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
bogdanm 73:1efda918f0ba 2358 #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2359 #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2360
bogdanm 73:1efda918f0ba 2361 #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
bogdanm 73:1efda918f0ba 2362 #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2363 #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2364
bogdanm 73:1efda918f0ba 2365 #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
bogdanm 73:1efda918f0ba 2366
bogdanm 73:1efda918f0ba 2367 #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
bogdanm 73:1efda918f0ba 2368 #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2369 #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2370
bogdanm 73:1efda918f0ba 2371 #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
bogdanm 73:1efda918f0ba 2372 #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2373 #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2374
bogdanm 73:1efda918f0ba 2375 #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
bogdanm 73:1efda918f0ba 2376 #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2377 #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2378
bogdanm 73:1efda918f0ba 2379 #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
bogdanm 73:1efda918f0ba 2380 #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2381 #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2382
bogdanm 73:1efda918f0ba 2383 #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
bogdanm 73:1efda918f0ba 2384 #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2385 #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2386
bogdanm 73:1efda918f0ba 2387 #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
bogdanm 73:1efda918f0ba 2388 #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2389 #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2390
bogdanm 73:1efda918f0ba 2391 #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
bogdanm 73:1efda918f0ba 2392 #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2393 #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2394
bogdanm 73:1efda918f0ba 2395 #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
bogdanm 73:1efda918f0ba 2396 #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2397 #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2398
bogdanm 73:1efda918f0ba 2399 /******************* Bit definition for GPIO_CRH register *******************/
bogdanm 73:1efda918f0ba 2400 #define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
bogdanm 73:1efda918f0ba 2401
bogdanm 73:1efda918f0ba 2402 #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
bogdanm 73:1efda918f0ba 2403 #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2404 #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2405
bogdanm 73:1efda918f0ba 2406 #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
bogdanm 73:1efda918f0ba 2407 #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2408 #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2409
bogdanm 73:1efda918f0ba 2410 #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
bogdanm 73:1efda918f0ba 2411 #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2412 #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2413
bogdanm 73:1efda918f0ba 2414 #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
bogdanm 73:1efda918f0ba 2415 #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2416 #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2417
bogdanm 73:1efda918f0ba 2418 #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
bogdanm 73:1efda918f0ba 2419 #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2420 #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2421
bogdanm 73:1efda918f0ba 2422 #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
bogdanm 73:1efda918f0ba 2423 #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2424 #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2425
bogdanm 73:1efda918f0ba 2426 #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
bogdanm 73:1efda918f0ba 2427 #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2428 #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2429
bogdanm 73:1efda918f0ba 2430 #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
bogdanm 73:1efda918f0ba 2431 #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2432 #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2433
bogdanm 73:1efda918f0ba 2434 #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
bogdanm 73:1efda918f0ba 2435
bogdanm 73:1efda918f0ba 2436 #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
bogdanm 73:1efda918f0ba 2437 #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2438 #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2439
bogdanm 73:1efda918f0ba 2440 #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
bogdanm 73:1efda918f0ba 2441 #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2442 #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2443
bogdanm 73:1efda918f0ba 2444 #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
bogdanm 73:1efda918f0ba 2445 #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2446 #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2447
bogdanm 73:1efda918f0ba 2448 #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
bogdanm 73:1efda918f0ba 2449 #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2450 #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2451
bogdanm 73:1efda918f0ba 2452 #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
bogdanm 73:1efda918f0ba 2453 #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2454 #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2455
bogdanm 73:1efda918f0ba 2456 #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
bogdanm 73:1efda918f0ba 2457 #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2458 #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2459
bogdanm 73:1efda918f0ba 2460 #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
bogdanm 73:1efda918f0ba 2461 #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2462 #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2463
bogdanm 73:1efda918f0ba 2464 #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
bogdanm 73:1efda918f0ba 2465 #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2466 #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2467
bogdanm 73:1efda918f0ba 2468 /*!<****************** Bit definition for GPIO_IDR register *******************/
bogdanm 73:1efda918f0ba 2469 #define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
bogdanm 73:1efda918f0ba 2470 #define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
bogdanm 73:1efda918f0ba 2471 #define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
bogdanm 73:1efda918f0ba 2472 #define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
bogdanm 73:1efda918f0ba 2473 #define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
bogdanm 73:1efda918f0ba 2474 #define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
bogdanm 73:1efda918f0ba 2475 #define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
bogdanm 73:1efda918f0ba 2476 #define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
bogdanm 73:1efda918f0ba 2477 #define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
bogdanm 73:1efda918f0ba 2478 #define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
bogdanm 73:1efda918f0ba 2479 #define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
bogdanm 73:1efda918f0ba 2480 #define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
bogdanm 73:1efda918f0ba 2481 #define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
bogdanm 73:1efda918f0ba 2482 #define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
bogdanm 73:1efda918f0ba 2483 #define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
bogdanm 73:1efda918f0ba 2484 #define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
bogdanm 73:1efda918f0ba 2485
bogdanm 73:1efda918f0ba 2486 /******************* Bit definition for GPIO_ODR register *******************/
bogdanm 73:1efda918f0ba 2487 #define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
bogdanm 73:1efda918f0ba 2488 #define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
bogdanm 73:1efda918f0ba 2489 #define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
bogdanm 73:1efda918f0ba 2490 #define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
bogdanm 73:1efda918f0ba 2491 #define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
bogdanm 73:1efda918f0ba 2492 #define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
bogdanm 73:1efda918f0ba 2493 #define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
bogdanm 73:1efda918f0ba 2494 #define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
bogdanm 73:1efda918f0ba 2495 #define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
bogdanm 73:1efda918f0ba 2496 #define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
bogdanm 73:1efda918f0ba 2497 #define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
bogdanm 73:1efda918f0ba 2498 #define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
bogdanm 73:1efda918f0ba 2499 #define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
bogdanm 73:1efda918f0ba 2500 #define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
bogdanm 73:1efda918f0ba 2501 #define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
bogdanm 73:1efda918f0ba 2502 #define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
bogdanm 73:1efda918f0ba 2503
bogdanm 73:1efda918f0ba 2504 /****************** Bit definition for GPIO_BSRR register *******************/
bogdanm 73:1efda918f0ba 2505 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
bogdanm 73:1efda918f0ba 2506 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
bogdanm 73:1efda918f0ba 2507 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
bogdanm 73:1efda918f0ba 2508 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
bogdanm 73:1efda918f0ba 2509 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
bogdanm 73:1efda918f0ba 2510 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
bogdanm 73:1efda918f0ba 2511 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
bogdanm 73:1efda918f0ba 2512 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
bogdanm 73:1efda918f0ba 2513 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
bogdanm 73:1efda918f0ba 2514 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
bogdanm 73:1efda918f0ba 2515 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
bogdanm 73:1efda918f0ba 2516 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
bogdanm 73:1efda918f0ba 2517 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
bogdanm 73:1efda918f0ba 2518 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
bogdanm 73:1efda918f0ba 2519 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
bogdanm 73:1efda918f0ba 2520 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
bogdanm 73:1efda918f0ba 2521
bogdanm 73:1efda918f0ba 2522 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
bogdanm 73:1efda918f0ba 2523 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
bogdanm 73:1efda918f0ba 2524 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
bogdanm 73:1efda918f0ba 2525 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
bogdanm 73:1efda918f0ba 2526 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
bogdanm 73:1efda918f0ba 2527 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
bogdanm 73:1efda918f0ba 2528 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
bogdanm 73:1efda918f0ba 2529 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
bogdanm 73:1efda918f0ba 2530 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
bogdanm 73:1efda918f0ba 2531 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
bogdanm 73:1efda918f0ba 2532 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
bogdanm 73:1efda918f0ba 2533 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
bogdanm 73:1efda918f0ba 2534 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
bogdanm 73:1efda918f0ba 2535 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
bogdanm 73:1efda918f0ba 2536 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
bogdanm 73:1efda918f0ba 2537 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
bogdanm 73:1efda918f0ba 2538
bogdanm 73:1efda918f0ba 2539 /******************* Bit definition for GPIO_BRR register *******************/
bogdanm 73:1efda918f0ba 2540 #define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
bogdanm 73:1efda918f0ba 2541 #define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
bogdanm 73:1efda918f0ba 2542 #define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
bogdanm 73:1efda918f0ba 2543 #define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
bogdanm 73:1efda918f0ba 2544 #define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
bogdanm 73:1efda918f0ba 2545 #define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
bogdanm 73:1efda918f0ba 2546 #define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
bogdanm 73:1efda918f0ba 2547 #define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
bogdanm 73:1efda918f0ba 2548 #define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
bogdanm 73:1efda918f0ba 2549 #define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
bogdanm 73:1efda918f0ba 2550 #define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
bogdanm 73:1efda918f0ba 2551 #define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
bogdanm 73:1efda918f0ba 2552 #define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
bogdanm 73:1efda918f0ba 2553 #define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
bogdanm 73:1efda918f0ba 2554 #define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
bogdanm 73:1efda918f0ba 2555 #define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
bogdanm 73:1efda918f0ba 2556
bogdanm 73:1efda918f0ba 2557 /****************** Bit definition for GPIO_LCKR register *******************/
bogdanm 73:1efda918f0ba 2558 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
bogdanm 73:1efda918f0ba 2559 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
bogdanm 73:1efda918f0ba 2560 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
bogdanm 73:1efda918f0ba 2561 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
bogdanm 73:1efda918f0ba 2562 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
bogdanm 73:1efda918f0ba 2563 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
bogdanm 73:1efda918f0ba 2564 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
bogdanm 73:1efda918f0ba 2565 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
bogdanm 73:1efda918f0ba 2566 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
bogdanm 73:1efda918f0ba 2567 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
bogdanm 73:1efda918f0ba 2568 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
bogdanm 73:1efda918f0ba 2569 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
bogdanm 73:1efda918f0ba 2570 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
bogdanm 73:1efda918f0ba 2571 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
bogdanm 73:1efda918f0ba 2572 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
bogdanm 73:1efda918f0ba 2573 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
bogdanm 73:1efda918f0ba 2574 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
bogdanm 73:1efda918f0ba 2575
bogdanm 73:1efda918f0ba 2576 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 2577
bogdanm 73:1efda918f0ba 2578 /****************** Bit definition for AFIO_EVCR register *******************/
bogdanm 73:1efda918f0ba 2579 #define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
bogdanm 73:1efda918f0ba 2580 #define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2581 #define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2582 #define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 2583 #define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 2584
bogdanm 73:1efda918f0ba 2585 /*!< PIN configuration */
bogdanm 73:1efda918f0ba 2586 #define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
bogdanm 73:1efda918f0ba 2587 #define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
bogdanm 73:1efda918f0ba 2588 #define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
bogdanm 73:1efda918f0ba 2589 #define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
bogdanm 73:1efda918f0ba 2590 #define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
bogdanm 73:1efda918f0ba 2591 #define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
bogdanm 73:1efda918f0ba 2592 #define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
bogdanm 73:1efda918f0ba 2593 #define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
bogdanm 73:1efda918f0ba 2594 #define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
bogdanm 73:1efda918f0ba 2595 #define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
bogdanm 73:1efda918f0ba 2596 #define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
bogdanm 73:1efda918f0ba 2597 #define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
bogdanm 73:1efda918f0ba 2598 #define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
bogdanm 73:1efda918f0ba 2599 #define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
bogdanm 73:1efda918f0ba 2600 #define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
bogdanm 73:1efda918f0ba 2601 #define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
bogdanm 73:1efda918f0ba 2602
bogdanm 73:1efda918f0ba 2603 #define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
bogdanm 73:1efda918f0ba 2604 #define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2605 #define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2606 #define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 2607
bogdanm 73:1efda918f0ba 2608 /*!< PORT configuration */
bogdanm 73:1efda918f0ba 2609 #define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
bogdanm 73:1efda918f0ba 2610 #define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
bogdanm 73:1efda918f0ba 2611 #define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
bogdanm 73:1efda918f0ba 2612 #define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
bogdanm 73:1efda918f0ba 2613 #define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
bogdanm 73:1efda918f0ba 2614
bogdanm 73:1efda918f0ba 2615 #define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
bogdanm 73:1efda918f0ba 2616
bogdanm 73:1efda918f0ba 2617 /****************** Bit definition for AFIO_MAPR register *******************/
bogdanm 73:1efda918f0ba 2618 #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
bogdanm 73:1efda918f0ba 2619 #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
bogdanm 73:1efda918f0ba 2620 #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
bogdanm 73:1efda918f0ba 2621 #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
bogdanm 73:1efda918f0ba 2622
bogdanm 73:1efda918f0ba 2623 #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
bogdanm 73:1efda918f0ba 2624 #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2625 #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2626
bogdanm 73:1efda918f0ba 2627 /* USART3_REMAP configuration */
bogdanm 73:1efda918f0ba 2628 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
bogdanm 73:1efda918f0ba 2629 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
bogdanm 73:1efda918f0ba 2630 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
bogdanm 73:1efda918f0ba 2631
bogdanm 73:1efda918f0ba 2632 #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
bogdanm 73:1efda918f0ba 2633 #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2634 #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2635
bogdanm 73:1efda918f0ba 2636 /*!< TIM1_REMAP configuration */
bogdanm 73:1efda918f0ba 2637 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
bogdanm 73:1efda918f0ba 2638 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
bogdanm 73:1efda918f0ba 2639 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
bogdanm 73:1efda918f0ba 2640
bogdanm 73:1efda918f0ba 2641 #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
bogdanm 73:1efda918f0ba 2642 #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2643 #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2644
bogdanm 73:1efda918f0ba 2645 /*!< TIM2_REMAP configuration */
bogdanm 73:1efda918f0ba 2646 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
bogdanm 73:1efda918f0ba 2647 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
bogdanm 73:1efda918f0ba 2648 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
bogdanm 73:1efda918f0ba 2649 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
bogdanm 73:1efda918f0ba 2650
bogdanm 73:1efda918f0ba 2651 #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
bogdanm 73:1efda918f0ba 2652 #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2653 #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2654
bogdanm 73:1efda918f0ba 2655 /*!< TIM3_REMAP configuration */
bogdanm 73:1efda918f0ba 2656 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
bogdanm 73:1efda918f0ba 2657 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
bogdanm 73:1efda918f0ba 2658 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
bogdanm 73:1efda918f0ba 2659
bogdanm 73:1efda918f0ba 2660 #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
bogdanm 73:1efda918f0ba 2661
bogdanm 73:1efda918f0ba 2662 #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
bogdanm 73:1efda918f0ba 2663 #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2664 #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2665
bogdanm 73:1efda918f0ba 2666 /*!< CAN_REMAP configuration */
bogdanm 73:1efda918f0ba 2667 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
bogdanm 73:1efda918f0ba 2668 #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
bogdanm 73:1efda918f0ba 2669 #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
bogdanm 73:1efda918f0ba 2670
bogdanm 73:1efda918f0ba 2671 #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
bogdanm 73:1efda918f0ba 2672 #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
bogdanm 73:1efda918f0ba 2673 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
bogdanm 73:1efda918f0ba 2674 #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
bogdanm 73:1efda918f0ba 2675 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
bogdanm 73:1efda918f0ba 2676 #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
bogdanm 73:1efda918f0ba 2677
bogdanm 73:1efda918f0ba 2678 /*!< SWJ_CFG configuration */
bogdanm 73:1efda918f0ba 2679 #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
bogdanm 73:1efda918f0ba 2680 #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 2681 #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 2682 #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 2683
bogdanm 73:1efda918f0ba 2684 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
bogdanm 73:1efda918f0ba 2685 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
bogdanm 73:1efda918f0ba 2686 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
bogdanm 73:1efda918f0ba 2687 #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
bogdanm 73:1efda918f0ba 2688
bogdanm 73:1efda918f0ba 2689 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 2690 /*!< ETH_REMAP configuration */
bogdanm 73:1efda918f0ba 2691 #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
bogdanm 73:1efda918f0ba 2692
bogdanm 73:1efda918f0ba 2693 /*!< CAN2_REMAP configuration */
bogdanm 73:1efda918f0ba 2694 #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
bogdanm 73:1efda918f0ba 2695
bogdanm 73:1efda918f0ba 2696 /*!< MII_RMII_SEL configuration */
bogdanm 73:1efda918f0ba 2697 #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
bogdanm 73:1efda918f0ba 2698
bogdanm 73:1efda918f0ba 2699 /*!< SPI3_REMAP configuration */
bogdanm 73:1efda918f0ba 2700 #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */
bogdanm 73:1efda918f0ba 2701
bogdanm 73:1efda918f0ba 2702 /*!< TIM2ITR1_IREMAP configuration */
bogdanm 73:1efda918f0ba 2703 #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
bogdanm 73:1efda918f0ba 2704
bogdanm 73:1efda918f0ba 2705 /*!< PTP_PPS_REMAP configuration */
bogdanm 73:1efda918f0ba 2706 #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
bogdanm 73:1efda918f0ba 2707 #endif
bogdanm 73:1efda918f0ba 2708
bogdanm 73:1efda918f0ba 2709 /***************** Bit definition for AFIO_EXTICR1 register *****************/
bogdanm 73:1efda918f0ba 2710 #define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
bogdanm 73:1efda918f0ba 2711 #define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
bogdanm 73:1efda918f0ba 2712 #define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
bogdanm 73:1efda918f0ba 2713 #define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
bogdanm 73:1efda918f0ba 2714
bogdanm 73:1efda918f0ba 2715 /*!< EXTI0 configuration */
bogdanm 73:1efda918f0ba 2716 #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
bogdanm 73:1efda918f0ba 2717 #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
bogdanm 73:1efda918f0ba 2718 #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
bogdanm 73:1efda918f0ba 2719 #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
bogdanm 73:1efda918f0ba 2720 #define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
bogdanm 73:1efda918f0ba 2721 #define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
bogdanm 73:1efda918f0ba 2722 #define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
bogdanm 73:1efda918f0ba 2723
bogdanm 73:1efda918f0ba 2724 /*!< EXTI1 configuration */
bogdanm 73:1efda918f0ba 2725 #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
bogdanm 73:1efda918f0ba 2726 #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
bogdanm 73:1efda918f0ba 2727 #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
bogdanm 73:1efda918f0ba 2728 #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
bogdanm 73:1efda918f0ba 2729 #define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
bogdanm 73:1efda918f0ba 2730 #define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
bogdanm 73:1efda918f0ba 2731 #define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
bogdanm 73:1efda918f0ba 2732
bogdanm 73:1efda918f0ba 2733 /*!< EXTI2 configuration */
bogdanm 73:1efda918f0ba 2734 #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
bogdanm 73:1efda918f0ba 2735 #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
bogdanm 73:1efda918f0ba 2736 #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
bogdanm 73:1efda918f0ba 2737 #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
bogdanm 73:1efda918f0ba 2738 #define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
bogdanm 73:1efda918f0ba 2739 #define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
bogdanm 73:1efda918f0ba 2740 #define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
bogdanm 73:1efda918f0ba 2741
bogdanm 73:1efda918f0ba 2742 /*!< EXTI3 configuration */
bogdanm 73:1efda918f0ba 2743 #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
bogdanm 73:1efda918f0ba 2744 #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
bogdanm 73:1efda918f0ba 2745 #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
bogdanm 73:1efda918f0ba 2746 #define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
bogdanm 73:1efda918f0ba 2747 #define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
bogdanm 73:1efda918f0ba 2748 #define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
bogdanm 73:1efda918f0ba 2749 #define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
bogdanm 73:1efda918f0ba 2750
bogdanm 73:1efda918f0ba 2751 /***************** Bit definition for AFIO_EXTICR2 register *****************/
bogdanm 73:1efda918f0ba 2752 #define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
bogdanm 73:1efda918f0ba 2753 #define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
bogdanm 73:1efda918f0ba 2754 #define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
bogdanm 73:1efda918f0ba 2755 #define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
bogdanm 73:1efda918f0ba 2756
bogdanm 73:1efda918f0ba 2757 /*!< EXTI4 configuration */
bogdanm 73:1efda918f0ba 2758 #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
bogdanm 73:1efda918f0ba 2759 #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
bogdanm 73:1efda918f0ba 2760 #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
bogdanm 73:1efda918f0ba 2761 #define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
bogdanm 73:1efda918f0ba 2762 #define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
bogdanm 73:1efda918f0ba 2763 #define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
bogdanm 73:1efda918f0ba 2764 #define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
bogdanm 73:1efda918f0ba 2765
bogdanm 73:1efda918f0ba 2766 /* EXTI5 configuration */
bogdanm 73:1efda918f0ba 2767 #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
bogdanm 73:1efda918f0ba 2768 #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
bogdanm 73:1efda918f0ba 2769 #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
bogdanm 73:1efda918f0ba 2770 #define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
bogdanm 73:1efda918f0ba 2771 #define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
bogdanm 73:1efda918f0ba 2772 #define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
bogdanm 73:1efda918f0ba 2773 #define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
bogdanm 73:1efda918f0ba 2774
bogdanm 73:1efda918f0ba 2775 /*!< EXTI6 configuration */
bogdanm 73:1efda918f0ba 2776 #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
bogdanm 73:1efda918f0ba 2777 #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
bogdanm 73:1efda918f0ba 2778 #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
bogdanm 73:1efda918f0ba 2779 #define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
bogdanm 73:1efda918f0ba 2780 #define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
bogdanm 73:1efda918f0ba 2781 #define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
bogdanm 73:1efda918f0ba 2782 #define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
bogdanm 73:1efda918f0ba 2783
bogdanm 73:1efda918f0ba 2784 /*!< EXTI7 configuration */
bogdanm 73:1efda918f0ba 2785 #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
bogdanm 73:1efda918f0ba 2786 #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
bogdanm 73:1efda918f0ba 2787 #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
bogdanm 73:1efda918f0ba 2788 #define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
bogdanm 73:1efda918f0ba 2789 #define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
bogdanm 73:1efda918f0ba 2790 #define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
bogdanm 73:1efda918f0ba 2791 #define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
bogdanm 73:1efda918f0ba 2792
bogdanm 73:1efda918f0ba 2793 /***************** Bit definition for AFIO_EXTICR3 register *****************/
bogdanm 73:1efda918f0ba 2794 #define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
bogdanm 73:1efda918f0ba 2795 #define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
bogdanm 73:1efda918f0ba 2796 #define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
bogdanm 73:1efda918f0ba 2797 #define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
bogdanm 73:1efda918f0ba 2798
bogdanm 73:1efda918f0ba 2799 /*!< EXTI8 configuration */
bogdanm 73:1efda918f0ba 2800 #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
bogdanm 73:1efda918f0ba 2801 #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
bogdanm 73:1efda918f0ba 2802 #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
bogdanm 73:1efda918f0ba 2803 #define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
bogdanm 73:1efda918f0ba 2804 #define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
bogdanm 73:1efda918f0ba 2805 #define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
bogdanm 73:1efda918f0ba 2806 #define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
bogdanm 73:1efda918f0ba 2807
bogdanm 73:1efda918f0ba 2808 /*!< EXTI9 configuration */
bogdanm 73:1efda918f0ba 2809 #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
bogdanm 73:1efda918f0ba 2810 #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
bogdanm 73:1efda918f0ba 2811 #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
bogdanm 73:1efda918f0ba 2812 #define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
bogdanm 73:1efda918f0ba 2813 #define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
bogdanm 73:1efda918f0ba 2814 #define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
bogdanm 73:1efda918f0ba 2815 #define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
bogdanm 73:1efda918f0ba 2816
bogdanm 73:1efda918f0ba 2817 /*!< EXTI10 configuration */
bogdanm 73:1efda918f0ba 2818 #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
bogdanm 73:1efda918f0ba 2819 #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
bogdanm 73:1efda918f0ba 2820 #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
bogdanm 73:1efda918f0ba 2821 #define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
bogdanm 73:1efda918f0ba 2822 #define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
bogdanm 73:1efda918f0ba 2823 #define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
bogdanm 73:1efda918f0ba 2824 #define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
bogdanm 73:1efda918f0ba 2825
bogdanm 73:1efda918f0ba 2826 /*!< EXTI11 configuration */
bogdanm 73:1efda918f0ba 2827 #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
bogdanm 73:1efda918f0ba 2828 #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
bogdanm 73:1efda918f0ba 2829 #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
bogdanm 73:1efda918f0ba 2830 #define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
bogdanm 73:1efda918f0ba 2831 #define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
bogdanm 73:1efda918f0ba 2832 #define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
bogdanm 73:1efda918f0ba 2833 #define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
bogdanm 73:1efda918f0ba 2834
bogdanm 73:1efda918f0ba 2835 /***************** Bit definition for AFIO_EXTICR4 register *****************/
bogdanm 73:1efda918f0ba 2836 #define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
bogdanm 73:1efda918f0ba 2837 #define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
bogdanm 73:1efda918f0ba 2838 #define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
bogdanm 73:1efda918f0ba 2839 #define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
bogdanm 73:1efda918f0ba 2840
bogdanm 73:1efda918f0ba 2841 /* EXTI12 configuration */
bogdanm 73:1efda918f0ba 2842 #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
bogdanm 73:1efda918f0ba 2843 #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
bogdanm 73:1efda918f0ba 2844 #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
bogdanm 73:1efda918f0ba 2845 #define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
bogdanm 73:1efda918f0ba 2846 #define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
bogdanm 73:1efda918f0ba 2847 #define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
bogdanm 73:1efda918f0ba 2848 #define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
bogdanm 73:1efda918f0ba 2849
bogdanm 73:1efda918f0ba 2850 /* EXTI13 configuration */
bogdanm 73:1efda918f0ba 2851 #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
bogdanm 73:1efda918f0ba 2852 #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
bogdanm 73:1efda918f0ba 2853 #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
bogdanm 73:1efda918f0ba 2854 #define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
bogdanm 73:1efda918f0ba 2855 #define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
bogdanm 73:1efda918f0ba 2856 #define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
bogdanm 73:1efda918f0ba 2857 #define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
bogdanm 73:1efda918f0ba 2858
bogdanm 73:1efda918f0ba 2859 /*!< EXTI14 configuration */
bogdanm 73:1efda918f0ba 2860 #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
bogdanm 73:1efda918f0ba 2861 #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
bogdanm 73:1efda918f0ba 2862 #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
bogdanm 73:1efda918f0ba 2863 #define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
bogdanm 73:1efda918f0ba 2864 #define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
bogdanm 73:1efda918f0ba 2865 #define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
bogdanm 73:1efda918f0ba 2866 #define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
bogdanm 73:1efda918f0ba 2867
bogdanm 73:1efda918f0ba 2868 /*!< EXTI15 configuration */
bogdanm 73:1efda918f0ba 2869 #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
bogdanm 73:1efda918f0ba 2870 #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
bogdanm 73:1efda918f0ba 2871 #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
bogdanm 73:1efda918f0ba 2872 #define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
bogdanm 73:1efda918f0ba 2873 #define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
bogdanm 73:1efda918f0ba 2874 #define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
bogdanm 73:1efda918f0ba 2875 #define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
bogdanm 73:1efda918f0ba 2876
bogdanm 73:1efda918f0ba 2877 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
bogdanm 73:1efda918f0ba 2878 /****************** Bit definition for AFIO_MAPR2 register ******************/
bogdanm 73:1efda918f0ba 2879 #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
bogdanm 73:1efda918f0ba 2880 #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
bogdanm 73:1efda918f0ba 2881 #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
bogdanm 73:1efda918f0ba 2882 #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
bogdanm 73:1efda918f0ba 2883 #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
bogdanm 73:1efda918f0ba 2884 #endif
bogdanm 73:1efda918f0ba 2885
bogdanm 73:1efda918f0ba 2886 #ifdef STM32F10X_HD_VL
bogdanm 73:1efda918f0ba 2887 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
bogdanm 73:1efda918f0ba 2888 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
bogdanm 73:1efda918f0ba 2889 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
bogdanm 73:1efda918f0ba 2890 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
bogdanm 73:1efda918f0ba 2891 #define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */
bogdanm 73:1efda918f0ba 2892 #define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */
bogdanm 73:1efda918f0ba 2893 #endif
bogdanm 73:1efda918f0ba 2894
bogdanm 73:1efda918f0ba 2895 #ifdef STM32F10X_XL
bogdanm 73:1efda918f0ba 2896 /****************** Bit definition for AFIO_MAPR2 register ******************/
bogdanm 73:1efda918f0ba 2897 #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */
bogdanm 73:1efda918f0ba 2898 #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */
bogdanm 73:1efda918f0ba 2899 #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */
bogdanm 73:1efda918f0ba 2900 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
bogdanm 73:1efda918f0ba 2901 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
bogdanm 73:1efda918f0ba 2902 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
bogdanm 73:1efda918f0ba 2903 #endif
bogdanm 73:1efda918f0ba 2904
bogdanm 73:1efda918f0ba 2905 /******************************************************************************/
bogdanm 73:1efda918f0ba 2906 /* */
bogdanm 73:1efda918f0ba 2907 /* SystemTick */
bogdanm 73:1efda918f0ba 2908 /* */
bogdanm 73:1efda918f0ba 2909 /******************************************************************************/
bogdanm 73:1efda918f0ba 2910
bogdanm 73:1efda918f0ba 2911 /***************** Bit definition for SysTick_CTRL register *****************/
bogdanm 73:1efda918f0ba 2912 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
bogdanm 73:1efda918f0ba 2913 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
bogdanm 73:1efda918f0ba 2914 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
bogdanm 73:1efda918f0ba 2915 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
bogdanm 73:1efda918f0ba 2916
bogdanm 73:1efda918f0ba 2917 /***************** Bit definition for SysTick_LOAD register *****************/
bogdanm 73:1efda918f0ba 2918 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
bogdanm 73:1efda918f0ba 2919
bogdanm 73:1efda918f0ba 2920 /***************** Bit definition for SysTick_VAL register ******************/
bogdanm 73:1efda918f0ba 2921 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
bogdanm 73:1efda918f0ba 2922
bogdanm 73:1efda918f0ba 2923 /***************** Bit definition for SysTick_CALIB register ****************/
bogdanm 73:1efda918f0ba 2924 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
bogdanm 73:1efda918f0ba 2925 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
bogdanm 73:1efda918f0ba 2926 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
bogdanm 73:1efda918f0ba 2927
bogdanm 73:1efda918f0ba 2928 /******************************************************************************/
bogdanm 73:1efda918f0ba 2929 /* */
bogdanm 73:1efda918f0ba 2930 /* Nested Vectored Interrupt Controller */
bogdanm 73:1efda918f0ba 2931 /* */
bogdanm 73:1efda918f0ba 2932 /******************************************************************************/
bogdanm 73:1efda918f0ba 2933
bogdanm 73:1efda918f0ba 2934 /****************** Bit definition for NVIC_ISER register *******************/
bogdanm 73:1efda918f0ba 2935 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
bogdanm 73:1efda918f0ba 2936 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
bogdanm 73:1efda918f0ba 2937 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
bogdanm 73:1efda918f0ba 2938 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
bogdanm 73:1efda918f0ba 2939 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
bogdanm 73:1efda918f0ba 2940 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
bogdanm 73:1efda918f0ba 2941 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
bogdanm 73:1efda918f0ba 2942 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
bogdanm 73:1efda918f0ba 2943 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
bogdanm 73:1efda918f0ba 2944 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
bogdanm 73:1efda918f0ba 2945 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
bogdanm 73:1efda918f0ba 2946 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
bogdanm 73:1efda918f0ba 2947 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
bogdanm 73:1efda918f0ba 2948 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
bogdanm 73:1efda918f0ba 2949 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
bogdanm 73:1efda918f0ba 2950 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
bogdanm 73:1efda918f0ba 2951 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
bogdanm 73:1efda918f0ba 2952 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
bogdanm 73:1efda918f0ba 2953 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
bogdanm 73:1efda918f0ba 2954 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
bogdanm 73:1efda918f0ba 2955 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
bogdanm 73:1efda918f0ba 2956 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
bogdanm 73:1efda918f0ba 2957 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
bogdanm 73:1efda918f0ba 2958 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
bogdanm 73:1efda918f0ba 2959 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
bogdanm 73:1efda918f0ba 2960 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
bogdanm 73:1efda918f0ba 2961 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
bogdanm 73:1efda918f0ba 2962 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
bogdanm 73:1efda918f0ba 2963 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
bogdanm 73:1efda918f0ba 2964 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
bogdanm 73:1efda918f0ba 2965 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
bogdanm 73:1efda918f0ba 2966 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
bogdanm 73:1efda918f0ba 2967 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
bogdanm 73:1efda918f0ba 2968
bogdanm 73:1efda918f0ba 2969 /****************** Bit definition for NVIC_ICER register *******************/
bogdanm 73:1efda918f0ba 2970 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
bogdanm 73:1efda918f0ba 2971 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
bogdanm 73:1efda918f0ba 2972 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
bogdanm 73:1efda918f0ba 2973 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
bogdanm 73:1efda918f0ba 2974 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
bogdanm 73:1efda918f0ba 2975 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
bogdanm 73:1efda918f0ba 2976 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
bogdanm 73:1efda918f0ba 2977 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
bogdanm 73:1efda918f0ba 2978 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
bogdanm 73:1efda918f0ba 2979 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
bogdanm 73:1efda918f0ba 2980 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
bogdanm 73:1efda918f0ba 2981 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
bogdanm 73:1efda918f0ba 2982 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
bogdanm 73:1efda918f0ba 2983 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
bogdanm 73:1efda918f0ba 2984 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
bogdanm 73:1efda918f0ba 2985 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
bogdanm 73:1efda918f0ba 2986 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
bogdanm 73:1efda918f0ba 2987 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
bogdanm 73:1efda918f0ba 2988 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
bogdanm 73:1efda918f0ba 2989 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
bogdanm 73:1efda918f0ba 2990 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
bogdanm 73:1efda918f0ba 2991 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
bogdanm 73:1efda918f0ba 2992 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
bogdanm 73:1efda918f0ba 2993 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
bogdanm 73:1efda918f0ba 2994 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
bogdanm 73:1efda918f0ba 2995 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
bogdanm 73:1efda918f0ba 2996 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
bogdanm 73:1efda918f0ba 2997 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
bogdanm 73:1efda918f0ba 2998 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
bogdanm 73:1efda918f0ba 2999 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
bogdanm 73:1efda918f0ba 3000 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
bogdanm 73:1efda918f0ba 3001 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
bogdanm 73:1efda918f0ba 3002 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
bogdanm 73:1efda918f0ba 3003
bogdanm 73:1efda918f0ba 3004 /****************** Bit definition for NVIC_ISPR register *******************/
bogdanm 73:1efda918f0ba 3005 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
bogdanm 73:1efda918f0ba 3006 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
bogdanm 73:1efda918f0ba 3007 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
bogdanm 73:1efda918f0ba 3008 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
bogdanm 73:1efda918f0ba 3009 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
bogdanm 73:1efda918f0ba 3010 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
bogdanm 73:1efda918f0ba 3011 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
bogdanm 73:1efda918f0ba 3012 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
bogdanm 73:1efda918f0ba 3013 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
bogdanm 73:1efda918f0ba 3014 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
bogdanm 73:1efda918f0ba 3015 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
bogdanm 73:1efda918f0ba 3016 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
bogdanm 73:1efda918f0ba 3017 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
bogdanm 73:1efda918f0ba 3018 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
bogdanm 73:1efda918f0ba 3019 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
bogdanm 73:1efda918f0ba 3020 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
bogdanm 73:1efda918f0ba 3021 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
bogdanm 73:1efda918f0ba 3022 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
bogdanm 73:1efda918f0ba 3023 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
bogdanm 73:1efda918f0ba 3024 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
bogdanm 73:1efda918f0ba 3025 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
bogdanm 73:1efda918f0ba 3026 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
bogdanm 73:1efda918f0ba 3027 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
bogdanm 73:1efda918f0ba 3028 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
bogdanm 73:1efda918f0ba 3029 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
bogdanm 73:1efda918f0ba 3030 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
bogdanm 73:1efda918f0ba 3031 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
bogdanm 73:1efda918f0ba 3032 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
bogdanm 73:1efda918f0ba 3033 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
bogdanm 73:1efda918f0ba 3034 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
bogdanm 73:1efda918f0ba 3035 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
bogdanm 73:1efda918f0ba 3036 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
bogdanm 73:1efda918f0ba 3037 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
bogdanm 73:1efda918f0ba 3038
bogdanm 73:1efda918f0ba 3039 /****************** Bit definition for NVIC_ICPR register *******************/
bogdanm 73:1efda918f0ba 3040 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
bogdanm 73:1efda918f0ba 3041 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
bogdanm 73:1efda918f0ba 3042 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
bogdanm 73:1efda918f0ba 3043 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
bogdanm 73:1efda918f0ba 3044 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
bogdanm 73:1efda918f0ba 3045 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
bogdanm 73:1efda918f0ba 3046 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
bogdanm 73:1efda918f0ba 3047 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
bogdanm 73:1efda918f0ba 3048 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
bogdanm 73:1efda918f0ba 3049 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
bogdanm 73:1efda918f0ba 3050 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
bogdanm 73:1efda918f0ba 3051 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
bogdanm 73:1efda918f0ba 3052 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
bogdanm 73:1efda918f0ba 3053 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
bogdanm 73:1efda918f0ba 3054 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
bogdanm 73:1efda918f0ba 3055 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
bogdanm 73:1efda918f0ba 3056 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
bogdanm 73:1efda918f0ba 3057 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
bogdanm 73:1efda918f0ba 3058 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
bogdanm 73:1efda918f0ba 3059 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
bogdanm 73:1efda918f0ba 3060 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
bogdanm 73:1efda918f0ba 3061 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
bogdanm 73:1efda918f0ba 3062 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
bogdanm 73:1efda918f0ba 3063 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
bogdanm 73:1efda918f0ba 3064 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
bogdanm 73:1efda918f0ba 3065 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
bogdanm 73:1efda918f0ba 3066 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
bogdanm 73:1efda918f0ba 3067 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
bogdanm 73:1efda918f0ba 3068 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
bogdanm 73:1efda918f0ba 3069 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
bogdanm 73:1efda918f0ba 3070 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
bogdanm 73:1efda918f0ba 3071 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
bogdanm 73:1efda918f0ba 3072 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
bogdanm 73:1efda918f0ba 3073
bogdanm 73:1efda918f0ba 3074 /****************** Bit definition for NVIC_IABR register *******************/
bogdanm 73:1efda918f0ba 3075 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
bogdanm 73:1efda918f0ba 3076 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
bogdanm 73:1efda918f0ba 3077 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
bogdanm 73:1efda918f0ba 3078 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
bogdanm 73:1efda918f0ba 3079 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
bogdanm 73:1efda918f0ba 3080 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
bogdanm 73:1efda918f0ba 3081 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
bogdanm 73:1efda918f0ba 3082 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
bogdanm 73:1efda918f0ba 3083 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
bogdanm 73:1efda918f0ba 3084 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
bogdanm 73:1efda918f0ba 3085 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
bogdanm 73:1efda918f0ba 3086 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
bogdanm 73:1efda918f0ba 3087 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
bogdanm 73:1efda918f0ba 3088 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
bogdanm 73:1efda918f0ba 3089 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
bogdanm 73:1efda918f0ba 3090 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
bogdanm 73:1efda918f0ba 3091 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
bogdanm 73:1efda918f0ba 3092 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
bogdanm 73:1efda918f0ba 3093 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
bogdanm 73:1efda918f0ba 3094 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
bogdanm 73:1efda918f0ba 3095 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
bogdanm 73:1efda918f0ba 3096 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
bogdanm 73:1efda918f0ba 3097 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
bogdanm 73:1efda918f0ba 3098 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
bogdanm 73:1efda918f0ba 3099 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
bogdanm 73:1efda918f0ba 3100 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
bogdanm 73:1efda918f0ba 3101 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
bogdanm 73:1efda918f0ba 3102 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
bogdanm 73:1efda918f0ba 3103 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
bogdanm 73:1efda918f0ba 3104 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
bogdanm 73:1efda918f0ba 3105 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
bogdanm 73:1efda918f0ba 3106 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
bogdanm 73:1efda918f0ba 3107 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
bogdanm 73:1efda918f0ba 3108
bogdanm 73:1efda918f0ba 3109 /****************** Bit definition for NVIC_PRI0 register *******************/
bogdanm 73:1efda918f0ba 3110 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
bogdanm 73:1efda918f0ba 3111 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
bogdanm 73:1efda918f0ba 3112 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
bogdanm 73:1efda918f0ba 3113 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
bogdanm 73:1efda918f0ba 3114
bogdanm 73:1efda918f0ba 3115 /****************** Bit definition for NVIC_PRI1 register *******************/
bogdanm 73:1efda918f0ba 3116 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
bogdanm 73:1efda918f0ba 3117 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
bogdanm 73:1efda918f0ba 3118 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
bogdanm 73:1efda918f0ba 3119 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
bogdanm 73:1efda918f0ba 3120
bogdanm 73:1efda918f0ba 3121 /****************** Bit definition for NVIC_PRI2 register *******************/
bogdanm 73:1efda918f0ba 3122 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
bogdanm 73:1efda918f0ba 3123 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
bogdanm 73:1efda918f0ba 3124 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
bogdanm 73:1efda918f0ba 3125 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
bogdanm 73:1efda918f0ba 3126
bogdanm 73:1efda918f0ba 3127 /****************** Bit definition for NVIC_PRI3 register *******************/
bogdanm 73:1efda918f0ba 3128 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
bogdanm 73:1efda918f0ba 3129 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
bogdanm 73:1efda918f0ba 3130 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
bogdanm 73:1efda918f0ba 3131 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
bogdanm 73:1efda918f0ba 3132
bogdanm 73:1efda918f0ba 3133 /****************** Bit definition for NVIC_PRI4 register *******************/
bogdanm 73:1efda918f0ba 3134 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
bogdanm 73:1efda918f0ba 3135 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
bogdanm 73:1efda918f0ba 3136 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
bogdanm 73:1efda918f0ba 3137 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
bogdanm 73:1efda918f0ba 3138
bogdanm 73:1efda918f0ba 3139 /****************** Bit definition for NVIC_PRI5 register *******************/
bogdanm 73:1efda918f0ba 3140 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
bogdanm 73:1efda918f0ba 3141 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
bogdanm 73:1efda918f0ba 3142 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
bogdanm 73:1efda918f0ba 3143 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
bogdanm 73:1efda918f0ba 3144
bogdanm 73:1efda918f0ba 3145 /****************** Bit definition for NVIC_PRI6 register *******************/
bogdanm 73:1efda918f0ba 3146 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
bogdanm 73:1efda918f0ba 3147 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
bogdanm 73:1efda918f0ba 3148 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
bogdanm 73:1efda918f0ba 3149 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
bogdanm 73:1efda918f0ba 3150
bogdanm 73:1efda918f0ba 3151 /****************** Bit definition for NVIC_PRI7 register *******************/
bogdanm 73:1efda918f0ba 3152 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
bogdanm 73:1efda918f0ba 3153 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
bogdanm 73:1efda918f0ba 3154 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
bogdanm 73:1efda918f0ba 3155 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
bogdanm 73:1efda918f0ba 3156
bogdanm 73:1efda918f0ba 3157 /****************** Bit definition for SCB_CPUID register *******************/
bogdanm 73:1efda918f0ba 3158 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
bogdanm 73:1efda918f0ba 3159 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
bogdanm 73:1efda918f0ba 3160 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
bogdanm 73:1efda918f0ba 3161 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
bogdanm 73:1efda918f0ba 3162 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
bogdanm 73:1efda918f0ba 3163
bogdanm 73:1efda918f0ba 3164 /******************* Bit definition for SCB_ICSR register *******************/
bogdanm 73:1efda918f0ba 3165 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
bogdanm 73:1efda918f0ba 3166 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
bogdanm 73:1efda918f0ba 3167 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
bogdanm 73:1efda918f0ba 3168 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
bogdanm 73:1efda918f0ba 3169 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
bogdanm 73:1efda918f0ba 3170 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
bogdanm 73:1efda918f0ba 3171 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
bogdanm 73:1efda918f0ba 3172 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
bogdanm 73:1efda918f0ba 3173 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
bogdanm 73:1efda918f0ba 3174 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
bogdanm 73:1efda918f0ba 3175
bogdanm 73:1efda918f0ba 3176 /******************* Bit definition for SCB_VTOR register *******************/
bogdanm 73:1efda918f0ba 3177 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
bogdanm 73:1efda918f0ba 3178 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
bogdanm 73:1efda918f0ba 3179
bogdanm 73:1efda918f0ba 3180 /*!<***************** Bit definition for SCB_AIRCR register *******************/
bogdanm 73:1efda918f0ba 3181 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
bogdanm 73:1efda918f0ba 3182 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
bogdanm 73:1efda918f0ba 3183 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
bogdanm 73:1efda918f0ba 3184
bogdanm 73:1efda918f0ba 3185 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
bogdanm 73:1efda918f0ba 3186 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3187 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3188 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3189
bogdanm 73:1efda918f0ba 3190 /* prority group configuration */
bogdanm 73:1efda918f0ba 3191 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
bogdanm 73:1efda918f0ba 3192 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
bogdanm 73:1efda918f0ba 3193 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
bogdanm 73:1efda918f0ba 3194 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
bogdanm 73:1efda918f0ba 3195 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
bogdanm 73:1efda918f0ba 3196 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
bogdanm 73:1efda918f0ba 3197 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
bogdanm 73:1efda918f0ba 3198 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
bogdanm 73:1efda918f0ba 3199
bogdanm 73:1efda918f0ba 3200 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
bogdanm 73:1efda918f0ba 3201 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
bogdanm 73:1efda918f0ba 3202
bogdanm 73:1efda918f0ba 3203 /******************* Bit definition for SCB_SCR register ********************/
bogdanm 73:1efda918f0ba 3204 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
bogdanm 73:1efda918f0ba 3205 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
bogdanm 73:1efda918f0ba 3206 #define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
bogdanm 73:1efda918f0ba 3207
bogdanm 73:1efda918f0ba 3208 /******************** Bit definition for SCB_CCR register *******************/
bogdanm 73:1efda918f0ba 3209 #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
bogdanm 73:1efda918f0ba 3210 #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
bogdanm 73:1efda918f0ba 3211 #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
bogdanm 73:1efda918f0ba 3212 #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
bogdanm 73:1efda918f0ba 3213 #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
bogdanm 73:1efda918f0ba 3214 #define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
bogdanm 73:1efda918f0ba 3215
bogdanm 73:1efda918f0ba 3216 /******************* Bit definition for SCB_SHPR register ********************/
bogdanm 73:1efda918f0ba 3217 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
bogdanm 73:1efda918f0ba 3218 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
bogdanm 73:1efda918f0ba 3219 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
bogdanm 73:1efda918f0ba 3220 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
bogdanm 73:1efda918f0ba 3221
bogdanm 73:1efda918f0ba 3222 /****************** Bit definition for SCB_SHCSR register *******************/
bogdanm 73:1efda918f0ba 3223 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
bogdanm 73:1efda918f0ba 3224 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
bogdanm 73:1efda918f0ba 3225 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
bogdanm 73:1efda918f0ba 3226 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
bogdanm 73:1efda918f0ba 3227 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
bogdanm 73:1efda918f0ba 3228 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
bogdanm 73:1efda918f0ba 3229 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
bogdanm 73:1efda918f0ba 3230 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
bogdanm 73:1efda918f0ba 3231 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
bogdanm 73:1efda918f0ba 3232 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
bogdanm 73:1efda918f0ba 3233 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
bogdanm 73:1efda918f0ba 3234 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
bogdanm 73:1efda918f0ba 3235 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
bogdanm 73:1efda918f0ba 3236 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
bogdanm 73:1efda918f0ba 3237
bogdanm 73:1efda918f0ba 3238 /******************* Bit definition for SCB_CFSR register *******************/
bogdanm 73:1efda918f0ba 3239 /*!< MFSR */
bogdanm 73:1efda918f0ba 3240 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
bogdanm 73:1efda918f0ba 3241 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
bogdanm 73:1efda918f0ba 3242 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
bogdanm 73:1efda918f0ba 3243 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
bogdanm 73:1efda918f0ba 3244 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
bogdanm 73:1efda918f0ba 3245 /*!< BFSR */
bogdanm 73:1efda918f0ba 3246 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
bogdanm 73:1efda918f0ba 3247 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
bogdanm 73:1efda918f0ba 3248 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
bogdanm 73:1efda918f0ba 3249 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
bogdanm 73:1efda918f0ba 3250 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
bogdanm 73:1efda918f0ba 3251 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
bogdanm 73:1efda918f0ba 3252 /*!< UFSR */
bogdanm 73:1efda918f0ba 3253 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
bogdanm 73:1efda918f0ba 3254 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
bogdanm 73:1efda918f0ba 3255 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
bogdanm 73:1efda918f0ba 3256 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
bogdanm 73:1efda918f0ba 3257 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
bogdanm 73:1efda918f0ba 3258 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
bogdanm 73:1efda918f0ba 3259
bogdanm 73:1efda918f0ba 3260 /******************* Bit definition for SCB_HFSR register *******************/
bogdanm 73:1efda918f0ba 3261 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
bogdanm 73:1efda918f0ba 3262 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
bogdanm 73:1efda918f0ba 3263 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
bogdanm 73:1efda918f0ba 3264
bogdanm 73:1efda918f0ba 3265 /******************* Bit definition for SCB_DFSR register *******************/
bogdanm 73:1efda918f0ba 3266 #define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
bogdanm 73:1efda918f0ba 3267 #define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
bogdanm 73:1efda918f0ba 3268 #define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
bogdanm 73:1efda918f0ba 3269 #define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
bogdanm 73:1efda918f0ba 3270 #define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
bogdanm 73:1efda918f0ba 3271
bogdanm 73:1efda918f0ba 3272 /******************* Bit definition for SCB_MMFAR register ******************/
bogdanm 73:1efda918f0ba 3273 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
bogdanm 73:1efda918f0ba 3274
bogdanm 73:1efda918f0ba 3275 /******************* Bit definition for SCB_BFAR register *******************/
bogdanm 73:1efda918f0ba 3276 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
bogdanm 73:1efda918f0ba 3277
bogdanm 73:1efda918f0ba 3278 /******************* Bit definition for SCB_afsr register *******************/
bogdanm 73:1efda918f0ba 3279 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
bogdanm 73:1efda918f0ba 3280
bogdanm 73:1efda918f0ba 3281 /******************************************************************************/
bogdanm 73:1efda918f0ba 3282 /* */
bogdanm 73:1efda918f0ba 3283 /* External Interrupt/Event Controller */
bogdanm 73:1efda918f0ba 3284 /* */
bogdanm 73:1efda918f0ba 3285 /******************************************************************************/
bogdanm 73:1efda918f0ba 3286
bogdanm 73:1efda918f0ba 3287 /******************* Bit definition for EXTI_IMR register *******************/
bogdanm 73:1efda918f0ba 3288 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 73:1efda918f0ba 3289 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 73:1efda918f0ba 3290 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 73:1efda918f0ba 3291 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 73:1efda918f0ba 3292 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 73:1efda918f0ba 3293 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 73:1efda918f0ba 3294 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 73:1efda918f0ba 3295 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 73:1efda918f0ba 3296 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 73:1efda918f0ba 3297 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 73:1efda918f0ba 3298 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 73:1efda918f0ba 3299 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 73:1efda918f0ba 3300 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 73:1efda918f0ba 3301 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 73:1efda918f0ba 3302 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 73:1efda918f0ba 3303 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 73:1efda918f0ba 3304 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 73:1efda918f0ba 3305 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 73:1efda918f0ba 3306 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 73:1efda918f0ba 3307 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 73:1efda918f0ba 3308
bogdanm 73:1efda918f0ba 3309 /******************* Bit definition for EXTI_EMR register *******************/
bogdanm 73:1efda918f0ba 3310 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 73:1efda918f0ba 3311 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 73:1efda918f0ba 3312 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 73:1efda918f0ba 3313 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 73:1efda918f0ba 3314 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 73:1efda918f0ba 3315 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 73:1efda918f0ba 3316 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 73:1efda918f0ba 3317 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 73:1efda918f0ba 3318 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 73:1efda918f0ba 3319 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 73:1efda918f0ba 3320 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 73:1efda918f0ba 3321 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 73:1efda918f0ba 3322 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 73:1efda918f0ba 3323 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 73:1efda918f0ba 3324 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 73:1efda918f0ba 3325 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 73:1efda918f0ba 3326 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 73:1efda918f0ba 3327 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 73:1efda918f0ba 3328 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 73:1efda918f0ba 3329 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 73:1efda918f0ba 3330
bogdanm 73:1efda918f0ba 3331 /****************** Bit definition for EXTI_RTSR register *******************/
bogdanm 73:1efda918f0ba 3332 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 73:1efda918f0ba 3333 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 73:1efda918f0ba 3334 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 73:1efda918f0ba 3335 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 73:1efda918f0ba 3336 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 73:1efda918f0ba 3337 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 73:1efda918f0ba 3338 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 73:1efda918f0ba 3339 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 73:1efda918f0ba 3340 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 73:1efda918f0ba 3341 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 73:1efda918f0ba 3342 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 73:1efda918f0ba 3343 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 73:1efda918f0ba 3344 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 73:1efda918f0ba 3345 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 73:1efda918f0ba 3346 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 73:1efda918f0ba 3347 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 73:1efda918f0ba 3348 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 73:1efda918f0ba 3349 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 73:1efda918f0ba 3350 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
bogdanm 73:1efda918f0ba 3351 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 73:1efda918f0ba 3352
bogdanm 73:1efda918f0ba 3353 /****************** Bit definition for EXTI_FTSR register *******************/
bogdanm 73:1efda918f0ba 3354 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 73:1efda918f0ba 3355 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 73:1efda918f0ba 3356 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 73:1efda918f0ba 3357 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 73:1efda918f0ba 3358 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 73:1efda918f0ba 3359 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 73:1efda918f0ba 3360 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 73:1efda918f0ba 3361 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 73:1efda918f0ba 3362 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 73:1efda918f0ba 3363 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 73:1efda918f0ba 3364 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 73:1efda918f0ba 3365 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 73:1efda918f0ba 3366 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 73:1efda918f0ba 3367 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 73:1efda918f0ba 3368 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 73:1efda918f0ba 3369 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 73:1efda918f0ba 3370 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 73:1efda918f0ba 3371 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 73:1efda918f0ba 3372 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
bogdanm 73:1efda918f0ba 3373 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 73:1efda918f0ba 3374
bogdanm 73:1efda918f0ba 3375 /****************** Bit definition for EXTI_SWIER register ******************/
bogdanm 73:1efda918f0ba 3376 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 73:1efda918f0ba 3377 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 73:1efda918f0ba 3378 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 73:1efda918f0ba 3379 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 73:1efda918f0ba 3380 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 73:1efda918f0ba 3381 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 73:1efda918f0ba 3382 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 73:1efda918f0ba 3383 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 73:1efda918f0ba 3384 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 73:1efda918f0ba 3385 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 73:1efda918f0ba 3386 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 73:1efda918f0ba 3387 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 73:1efda918f0ba 3388 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 73:1efda918f0ba 3389 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 73:1efda918f0ba 3390 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 73:1efda918f0ba 3391 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 73:1efda918f0ba 3392 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 73:1efda918f0ba 3393 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 73:1efda918f0ba 3394 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
bogdanm 73:1efda918f0ba 3395 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 73:1efda918f0ba 3396
bogdanm 73:1efda918f0ba 3397 /******************* Bit definition for EXTI_PR register ********************/
bogdanm 73:1efda918f0ba 3398 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
bogdanm 73:1efda918f0ba 3399 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
bogdanm 73:1efda918f0ba 3400 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
bogdanm 73:1efda918f0ba 3401 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
bogdanm 73:1efda918f0ba 3402 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
bogdanm 73:1efda918f0ba 3403 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
bogdanm 73:1efda918f0ba 3404 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
bogdanm 73:1efda918f0ba 3405 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
bogdanm 73:1efda918f0ba 3406 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
bogdanm 73:1efda918f0ba 3407 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
bogdanm 73:1efda918f0ba 3408 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
bogdanm 73:1efda918f0ba 3409 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
bogdanm 73:1efda918f0ba 3410 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
bogdanm 73:1efda918f0ba 3411 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
bogdanm 73:1efda918f0ba 3412 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
bogdanm 73:1efda918f0ba 3413 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
bogdanm 73:1efda918f0ba 3414 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
bogdanm 73:1efda918f0ba 3415 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
bogdanm 73:1efda918f0ba 3416 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
bogdanm 73:1efda918f0ba 3417 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
bogdanm 73:1efda918f0ba 3418
bogdanm 73:1efda918f0ba 3419 /******************************************************************************/
bogdanm 73:1efda918f0ba 3420 /* */
bogdanm 73:1efda918f0ba 3421 /* DMA Controller */
bogdanm 73:1efda918f0ba 3422 /* */
bogdanm 73:1efda918f0ba 3423 /******************************************************************************/
bogdanm 73:1efda918f0ba 3424
bogdanm 73:1efda918f0ba 3425 /******************* Bit definition for DMA_ISR register ********************/
bogdanm 73:1efda918f0ba 3426 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
bogdanm 73:1efda918f0ba 3427 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
bogdanm 73:1efda918f0ba 3428 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
bogdanm 73:1efda918f0ba 3429 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
bogdanm 73:1efda918f0ba 3430 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
bogdanm 73:1efda918f0ba 3431 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
bogdanm 73:1efda918f0ba 3432 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
bogdanm 73:1efda918f0ba 3433 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
bogdanm 73:1efda918f0ba 3434 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
bogdanm 73:1efda918f0ba 3435 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
bogdanm 73:1efda918f0ba 3436 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
bogdanm 73:1efda918f0ba 3437 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
bogdanm 73:1efda918f0ba 3438 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
bogdanm 73:1efda918f0ba 3439 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
bogdanm 73:1efda918f0ba 3440 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
bogdanm 73:1efda918f0ba 3441 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
bogdanm 73:1efda918f0ba 3442 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
bogdanm 73:1efda918f0ba 3443 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
bogdanm 73:1efda918f0ba 3444 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
bogdanm 73:1efda918f0ba 3445 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
bogdanm 73:1efda918f0ba 3446 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
bogdanm 73:1efda918f0ba 3447 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
bogdanm 73:1efda918f0ba 3448 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
bogdanm 73:1efda918f0ba 3449 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
bogdanm 73:1efda918f0ba 3450 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
bogdanm 73:1efda918f0ba 3451 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
bogdanm 73:1efda918f0ba 3452 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
bogdanm 73:1efda918f0ba 3453 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
bogdanm 73:1efda918f0ba 3454
bogdanm 73:1efda918f0ba 3455 /******************* Bit definition for DMA_IFCR register *******************/
bogdanm 73:1efda918f0ba 3456 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
bogdanm 73:1efda918f0ba 3457 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
bogdanm 73:1efda918f0ba 3458 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
bogdanm 73:1efda918f0ba 3459 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
bogdanm 73:1efda918f0ba 3460 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
bogdanm 73:1efda918f0ba 3461 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
bogdanm 73:1efda918f0ba 3462 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
bogdanm 73:1efda918f0ba 3463 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
bogdanm 73:1efda918f0ba 3464 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
bogdanm 73:1efda918f0ba 3465 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
bogdanm 73:1efda918f0ba 3466 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
bogdanm 73:1efda918f0ba 3467 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
bogdanm 73:1efda918f0ba 3468 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
bogdanm 73:1efda918f0ba 3469 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
bogdanm 73:1efda918f0ba 3470 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
bogdanm 73:1efda918f0ba 3471 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
bogdanm 73:1efda918f0ba 3472 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
bogdanm 73:1efda918f0ba 3473 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
bogdanm 73:1efda918f0ba 3474 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
bogdanm 73:1efda918f0ba 3475 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
bogdanm 73:1efda918f0ba 3476 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
bogdanm 73:1efda918f0ba 3477 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
bogdanm 73:1efda918f0ba 3478 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
bogdanm 73:1efda918f0ba 3479 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
bogdanm 73:1efda918f0ba 3480 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
bogdanm 73:1efda918f0ba 3481 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
bogdanm 73:1efda918f0ba 3482 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
bogdanm 73:1efda918f0ba 3483 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
bogdanm 73:1efda918f0ba 3484
bogdanm 73:1efda918f0ba 3485 /******************* Bit definition for DMA_CCR1 register *******************/
bogdanm 73:1efda918f0ba 3486 #define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
bogdanm 73:1efda918f0ba 3487 #define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
bogdanm 73:1efda918f0ba 3488 #define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
bogdanm 73:1efda918f0ba 3489 #define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
bogdanm 73:1efda918f0ba 3490 #define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
bogdanm 73:1efda918f0ba 3491 #define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
bogdanm 73:1efda918f0ba 3492 #define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
bogdanm 73:1efda918f0ba 3493 #define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
bogdanm 73:1efda918f0ba 3494
bogdanm 73:1efda918f0ba 3495 #define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 73:1efda918f0ba 3496 #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3497 #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3498
bogdanm 73:1efda918f0ba 3499 #define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 73:1efda918f0ba 3500 #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3501 #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3502
bogdanm 73:1efda918f0ba 3503 #define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
bogdanm 73:1efda918f0ba 3504 #define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3505 #define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3506
bogdanm 73:1efda918f0ba 3507 #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
bogdanm 73:1efda918f0ba 3508
bogdanm 73:1efda918f0ba 3509 /******************* Bit definition for DMA_CCR2 register *******************/
bogdanm 73:1efda918f0ba 3510 #define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
bogdanm 73:1efda918f0ba 3511 #define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
bogdanm 73:1efda918f0ba 3512 #define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
bogdanm 73:1efda918f0ba 3513 #define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
bogdanm 73:1efda918f0ba 3514 #define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
bogdanm 73:1efda918f0ba 3515 #define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
bogdanm 73:1efda918f0ba 3516 #define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
bogdanm 73:1efda918f0ba 3517 #define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
bogdanm 73:1efda918f0ba 3518
bogdanm 73:1efda918f0ba 3519 #define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 73:1efda918f0ba 3520 #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3521 #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3522
bogdanm 73:1efda918f0ba 3523 #define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 73:1efda918f0ba 3524 #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3525 #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3526
bogdanm 73:1efda918f0ba 3527 #define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
bogdanm 73:1efda918f0ba 3528 #define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3529 #define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3530
bogdanm 73:1efda918f0ba 3531 #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
bogdanm 73:1efda918f0ba 3532
bogdanm 73:1efda918f0ba 3533 /******************* Bit definition for DMA_CCR3 register *******************/
bogdanm 73:1efda918f0ba 3534 #define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
bogdanm 73:1efda918f0ba 3535 #define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
bogdanm 73:1efda918f0ba 3536 #define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
bogdanm 73:1efda918f0ba 3537 #define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
bogdanm 73:1efda918f0ba 3538 #define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
bogdanm 73:1efda918f0ba 3539 #define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
bogdanm 73:1efda918f0ba 3540 #define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
bogdanm 73:1efda918f0ba 3541 #define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
bogdanm 73:1efda918f0ba 3542
bogdanm 73:1efda918f0ba 3543 #define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 73:1efda918f0ba 3544 #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3545 #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3546
bogdanm 73:1efda918f0ba 3547 #define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 73:1efda918f0ba 3548 #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3549 #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3550
bogdanm 73:1efda918f0ba 3551 #define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
bogdanm 73:1efda918f0ba 3552 #define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3553 #define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3554
bogdanm 73:1efda918f0ba 3555 #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
bogdanm 73:1efda918f0ba 3556
bogdanm 73:1efda918f0ba 3557 /*!<****************** Bit definition for DMA_CCR4 register *******************/
bogdanm 73:1efda918f0ba 3558 #define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
bogdanm 73:1efda918f0ba 3559 #define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
bogdanm 73:1efda918f0ba 3560 #define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
bogdanm 73:1efda918f0ba 3561 #define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
bogdanm 73:1efda918f0ba 3562 #define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
bogdanm 73:1efda918f0ba 3563 #define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
bogdanm 73:1efda918f0ba 3564 #define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
bogdanm 73:1efda918f0ba 3565 #define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
bogdanm 73:1efda918f0ba 3566
bogdanm 73:1efda918f0ba 3567 #define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 73:1efda918f0ba 3568 #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3569 #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3570
bogdanm 73:1efda918f0ba 3571 #define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 73:1efda918f0ba 3572 #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3573 #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3574
bogdanm 73:1efda918f0ba 3575 #define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
bogdanm 73:1efda918f0ba 3576 #define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3577 #define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3578
bogdanm 73:1efda918f0ba 3579 #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
bogdanm 73:1efda918f0ba 3580
bogdanm 73:1efda918f0ba 3581 /****************** Bit definition for DMA_CCR5 register *******************/
bogdanm 73:1efda918f0ba 3582 #define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
bogdanm 73:1efda918f0ba 3583 #define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
bogdanm 73:1efda918f0ba 3584 #define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
bogdanm 73:1efda918f0ba 3585 #define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
bogdanm 73:1efda918f0ba 3586 #define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
bogdanm 73:1efda918f0ba 3587 #define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
bogdanm 73:1efda918f0ba 3588 #define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
bogdanm 73:1efda918f0ba 3589 #define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
bogdanm 73:1efda918f0ba 3590
bogdanm 73:1efda918f0ba 3591 #define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 73:1efda918f0ba 3592 #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3593 #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3594
bogdanm 73:1efda918f0ba 3595 #define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 73:1efda918f0ba 3596 #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3597 #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3598
bogdanm 73:1efda918f0ba 3599 #define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
bogdanm 73:1efda918f0ba 3600 #define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3601 #define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3602
bogdanm 73:1efda918f0ba 3603 #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
bogdanm 73:1efda918f0ba 3604
bogdanm 73:1efda918f0ba 3605 /******************* Bit definition for DMA_CCR6 register *******************/
bogdanm 73:1efda918f0ba 3606 #define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
bogdanm 73:1efda918f0ba 3607 #define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
bogdanm 73:1efda918f0ba 3608 #define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
bogdanm 73:1efda918f0ba 3609 #define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
bogdanm 73:1efda918f0ba 3610 #define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
bogdanm 73:1efda918f0ba 3611 #define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
bogdanm 73:1efda918f0ba 3612 #define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
bogdanm 73:1efda918f0ba 3613 #define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
bogdanm 73:1efda918f0ba 3614
bogdanm 73:1efda918f0ba 3615 #define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 73:1efda918f0ba 3616 #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3617 #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3618
bogdanm 73:1efda918f0ba 3619 #define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 73:1efda918f0ba 3620 #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3621 #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3622
bogdanm 73:1efda918f0ba 3623 #define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
bogdanm 73:1efda918f0ba 3624 #define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3625 #define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3626
bogdanm 73:1efda918f0ba 3627 #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
bogdanm 73:1efda918f0ba 3628
bogdanm 73:1efda918f0ba 3629 /******************* Bit definition for DMA_CCR7 register *******************/
bogdanm 73:1efda918f0ba 3630 #define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
bogdanm 73:1efda918f0ba 3631 #define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
bogdanm 73:1efda918f0ba 3632 #define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
bogdanm 73:1efda918f0ba 3633 #define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
bogdanm 73:1efda918f0ba 3634 #define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
bogdanm 73:1efda918f0ba 3635 #define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
bogdanm 73:1efda918f0ba 3636 #define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
bogdanm 73:1efda918f0ba 3637 #define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
bogdanm 73:1efda918f0ba 3638
emilmont 77:869cf507173a 3639 #define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 73:1efda918f0ba 3640 #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3641 #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3642
bogdanm 73:1efda918f0ba 3643 #define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 73:1efda918f0ba 3644 #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3645 #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3646
bogdanm 73:1efda918f0ba 3647 #define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
bogdanm 73:1efda918f0ba 3648 #define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3649 #define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3650
bogdanm 73:1efda918f0ba 3651 #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
bogdanm 73:1efda918f0ba 3652
bogdanm 73:1efda918f0ba 3653 /****************** Bit definition for DMA_CNDTR1 register ******************/
bogdanm 73:1efda918f0ba 3654 #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
bogdanm 73:1efda918f0ba 3655
bogdanm 73:1efda918f0ba 3656 /****************** Bit definition for DMA_CNDTR2 register ******************/
bogdanm 73:1efda918f0ba 3657 #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
bogdanm 73:1efda918f0ba 3658
bogdanm 73:1efda918f0ba 3659 /****************** Bit definition for DMA_CNDTR3 register ******************/
bogdanm 73:1efda918f0ba 3660 #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
bogdanm 73:1efda918f0ba 3661
bogdanm 73:1efda918f0ba 3662 /****************** Bit definition for DMA_CNDTR4 register ******************/
bogdanm 73:1efda918f0ba 3663 #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
bogdanm 73:1efda918f0ba 3664
bogdanm 73:1efda918f0ba 3665 /****************** Bit definition for DMA_CNDTR5 register ******************/
bogdanm 73:1efda918f0ba 3666 #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
bogdanm 73:1efda918f0ba 3667
bogdanm 73:1efda918f0ba 3668 /****************** Bit definition for DMA_CNDTR6 register ******************/
bogdanm 73:1efda918f0ba 3669 #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
bogdanm 73:1efda918f0ba 3670
bogdanm 73:1efda918f0ba 3671 /****************** Bit definition for DMA_CNDTR7 register ******************/
bogdanm 73:1efda918f0ba 3672 #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
bogdanm 73:1efda918f0ba 3673
bogdanm 73:1efda918f0ba 3674 /****************** Bit definition for DMA_CPAR1 register *******************/
bogdanm 73:1efda918f0ba 3675 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 73:1efda918f0ba 3676
bogdanm 73:1efda918f0ba 3677 /****************** Bit definition for DMA_CPAR2 register *******************/
bogdanm 73:1efda918f0ba 3678 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 73:1efda918f0ba 3679
bogdanm 73:1efda918f0ba 3680 /****************** Bit definition for DMA_CPAR3 register *******************/
bogdanm 73:1efda918f0ba 3681 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 73:1efda918f0ba 3682
bogdanm 73:1efda918f0ba 3683
bogdanm 73:1efda918f0ba 3684 /****************** Bit definition for DMA_CPAR4 register *******************/
bogdanm 73:1efda918f0ba 3685 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 73:1efda918f0ba 3686
bogdanm 73:1efda918f0ba 3687 /****************** Bit definition for DMA_CPAR5 register *******************/
bogdanm 73:1efda918f0ba 3688 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 73:1efda918f0ba 3689
bogdanm 73:1efda918f0ba 3690 /****************** Bit definition for DMA_CPAR6 register *******************/
bogdanm 73:1efda918f0ba 3691 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 73:1efda918f0ba 3692
bogdanm 73:1efda918f0ba 3693
bogdanm 73:1efda918f0ba 3694 /****************** Bit definition for DMA_CPAR7 register *******************/
bogdanm 73:1efda918f0ba 3695 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 73:1efda918f0ba 3696
bogdanm 73:1efda918f0ba 3697 /****************** Bit definition for DMA_CMAR1 register *******************/
bogdanm 73:1efda918f0ba 3698 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 73:1efda918f0ba 3699
bogdanm 73:1efda918f0ba 3700 /****************** Bit definition for DMA_CMAR2 register *******************/
bogdanm 73:1efda918f0ba 3701 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 73:1efda918f0ba 3702
bogdanm 73:1efda918f0ba 3703 /****************** Bit definition for DMA_CMAR3 register *******************/
bogdanm 73:1efda918f0ba 3704 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 73:1efda918f0ba 3705
bogdanm 73:1efda918f0ba 3706
bogdanm 73:1efda918f0ba 3707 /****************** Bit definition for DMA_CMAR4 register *******************/
bogdanm 73:1efda918f0ba 3708 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 73:1efda918f0ba 3709
bogdanm 73:1efda918f0ba 3710 /****************** Bit definition for DMA_CMAR5 register *******************/
bogdanm 73:1efda918f0ba 3711 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 73:1efda918f0ba 3712
bogdanm 73:1efda918f0ba 3713 /****************** Bit definition for DMA_CMAR6 register *******************/
bogdanm 73:1efda918f0ba 3714 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 73:1efda918f0ba 3715
bogdanm 73:1efda918f0ba 3716 /****************** Bit definition for DMA_CMAR7 register *******************/
bogdanm 73:1efda918f0ba 3717 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 73:1efda918f0ba 3718
bogdanm 73:1efda918f0ba 3719 /******************************************************************************/
bogdanm 73:1efda918f0ba 3720 /* */
bogdanm 73:1efda918f0ba 3721 /* Analog to Digital Converter */
bogdanm 73:1efda918f0ba 3722 /* */
bogdanm 73:1efda918f0ba 3723 /******************************************************************************/
bogdanm 73:1efda918f0ba 3724
bogdanm 73:1efda918f0ba 3725 /******************** Bit definition for ADC_SR register ********************/
bogdanm 73:1efda918f0ba 3726 #define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */
bogdanm 73:1efda918f0ba 3727 #define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */
bogdanm 73:1efda918f0ba 3728 #define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */
bogdanm 73:1efda918f0ba 3729 #define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */
bogdanm 73:1efda918f0ba 3730 #define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */
bogdanm 73:1efda918f0ba 3731
bogdanm 73:1efda918f0ba 3732 /******************* Bit definition for ADC_CR1 register ********************/
bogdanm 73:1efda918f0ba 3733 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
bogdanm 73:1efda918f0ba 3734 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3735 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3736 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3737 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3738 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3739
bogdanm 73:1efda918f0ba 3740 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
bogdanm 73:1efda918f0ba 3741 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
bogdanm 73:1efda918f0ba 3742 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
bogdanm 73:1efda918f0ba 3743 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
bogdanm 73:1efda918f0ba 3744 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
bogdanm 73:1efda918f0ba 3745 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
bogdanm 73:1efda918f0ba 3746 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
bogdanm 73:1efda918f0ba 3747 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
bogdanm 73:1efda918f0ba 3748
bogdanm 73:1efda918f0ba 3749 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
bogdanm 73:1efda918f0ba 3750 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3751 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3752 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3753
bogdanm 73:1efda918f0ba 3754 #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */
bogdanm 73:1efda918f0ba 3755 #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3756 #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3757 #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3758 #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3759
bogdanm 73:1efda918f0ba 3760 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
bogdanm 73:1efda918f0ba 3761 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
bogdanm 73:1efda918f0ba 3762
bogdanm 73:1efda918f0ba 3763
bogdanm 73:1efda918f0ba 3764 /******************* Bit definition for ADC_CR2 register ********************/
bogdanm 73:1efda918f0ba 3765 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
bogdanm 73:1efda918f0ba 3766 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
bogdanm 73:1efda918f0ba 3767 #define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
bogdanm 73:1efda918f0ba 3768 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
bogdanm 73:1efda918f0ba 3769 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
bogdanm 73:1efda918f0ba 3770 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
bogdanm 73:1efda918f0ba 3771
bogdanm 73:1efda918f0ba 3772 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
bogdanm 73:1efda918f0ba 3773 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3774 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3775 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3776
bogdanm 73:1efda918f0ba 3777 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
bogdanm 73:1efda918f0ba 3778
bogdanm 73:1efda918f0ba 3779 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
bogdanm 73:1efda918f0ba 3780 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3781 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3782 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3783
bogdanm 73:1efda918f0ba 3784 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
bogdanm 73:1efda918f0ba 3785 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
bogdanm 73:1efda918f0ba 3786 #define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
bogdanm 73:1efda918f0ba 3787 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
bogdanm 73:1efda918f0ba 3788
bogdanm 73:1efda918f0ba 3789 /****************** Bit definition for ADC_SMPR1 register *******************/
bogdanm 73:1efda918f0ba 3790 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
bogdanm 73:1efda918f0ba 3791 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3792 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3793 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3794
bogdanm 73:1efda918f0ba 3795 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
bogdanm 73:1efda918f0ba 3796 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3797 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3798 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3799
bogdanm 73:1efda918f0ba 3800 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
bogdanm 73:1efda918f0ba 3801 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3802 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3803 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3804
bogdanm 73:1efda918f0ba 3805 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
bogdanm 73:1efda918f0ba 3806 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3807 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3808 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3809
bogdanm 73:1efda918f0ba 3810 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
bogdanm 73:1efda918f0ba 3811 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3812 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3813 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3814
bogdanm 73:1efda918f0ba 3815 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
bogdanm 73:1efda918f0ba 3816 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3817 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3818 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3819
bogdanm 73:1efda918f0ba 3820 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
bogdanm 73:1efda918f0ba 3821 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3822 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3823 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3824
bogdanm 73:1efda918f0ba 3825 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
bogdanm 73:1efda918f0ba 3826 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3827 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3828 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3829
bogdanm 73:1efda918f0ba 3830 /****************** Bit definition for ADC_SMPR2 register *******************/
bogdanm 73:1efda918f0ba 3831 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
bogdanm 73:1efda918f0ba 3832 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3833 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3834 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3835
bogdanm 73:1efda918f0ba 3836 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
bogdanm 73:1efda918f0ba 3837 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3838 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3839 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3840
bogdanm 73:1efda918f0ba 3841 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
bogdanm 73:1efda918f0ba 3842 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3843 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3844 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3845
bogdanm 73:1efda918f0ba 3846 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
bogdanm 73:1efda918f0ba 3847 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3848 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3849 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3850
bogdanm 73:1efda918f0ba 3851 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
bogdanm 73:1efda918f0ba 3852 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3853 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3854 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3855
bogdanm 73:1efda918f0ba 3856 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
bogdanm 73:1efda918f0ba 3857 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3858 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3859 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3860
bogdanm 73:1efda918f0ba 3861 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
bogdanm 73:1efda918f0ba 3862 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3863 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3864 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3865
bogdanm 73:1efda918f0ba 3866 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
bogdanm 73:1efda918f0ba 3867 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3868 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3869 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3870
bogdanm 73:1efda918f0ba 3871 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
bogdanm 73:1efda918f0ba 3872 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3873 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3874 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3875
bogdanm 73:1efda918f0ba 3876 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
bogdanm 73:1efda918f0ba 3877 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3878 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3879 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3880
bogdanm 73:1efda918f0ba 3881 /****************** Bit definition for ADC_JOFR1 register *******************/
bogdanm 73:1efda918f0ba 3882 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
bogdanm 73:1efda918f0ba 3883
bogdanm 73:1efda918f0ba 3884 /****************** Bit definition for ADC_JOFR2 register *******************/
bogdanm 73:1efda918f0ba 3885 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
bogdanm 73:1efda918f0ba 3886
bogdanm 73:1efda918f0ba 3887 /****************** Bit definition for ADC_JOFR3 register *******************/
bogdanm 73:1efda918f0ba 3888 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
bogdanm 73:1efda918f0ba 3889
bogdanm 73:1efda918f0ba 3890 /****************** Bit definition for ADC_JOFR4 register *******************/
bogdanm 73:1efda918f0ba 3891 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
bogdanm 73:1efda918f0ba 3892
bogdanm 73:1efda918f0ba 3893 /******************* Bit definition for ADC_HTR register ********************/
bogdanm 73:1efda918f0ba 3894 #define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
bogdanm 73:1efda918f0ba 3895
bogdanm 73:1efda918f0ba 3896 /******************* Bit definition for ADC_LTR register ********************/
bogdanm 73:1efda918f0ba 3897 #define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
bogdanm 73:1efda918f0ba 3898
bogdanm 73:1efda918f0ba 3899 /******************* Bit definition for ADC_SQR1 register *******************/
bogdanm 73:1efda918f0ba 3900 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3901 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3902 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3903 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3904 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3905 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3906
bogdanm 73:1efda918f0ba 3907 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3908 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3909 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3910 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3911 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3912 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3913
bogdanm 73:1efda918f0ba 3914 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3915 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3916 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3917 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3918 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3919 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3920
bogdanm 73:1efda918f0ba 3921 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3922 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3923 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3924 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3925 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3926 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3927
bogdanm 73:1efda918f0ba 3928 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
bogdanm 73:1efda918f0ba 3929 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3930 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3931 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3932 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3933
bogdanm 73:1efda918f0ba 3934 /******************* Bit definition for ADC_SQR2 register *******************/
bogdanm 73:1efda918f0ba 3935 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3936 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3937 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3938 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3939 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3940 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3941
bogdanm 73:1efda918f0ba 3942 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3943 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3944 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3945 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3946 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3947 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3948
bogdanm 73:1efda918f0ba 3949 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3950 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3951 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3952 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3953 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3954 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3955
bogdanm 73:1efda918f0ba 3956 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3957 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3958 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3959 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3960 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3961 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3962
bogdanm 73:1efda918f0ba 3963 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3964 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3965 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3966 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3967 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3968 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3969
bogdanm 73:1efda918f0ba 3970 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3971 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3972 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3973 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3974 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3975 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3976
bogdanm 73:1efda918f0ba 3977 /******************* Bit definition for ADC_SQR3 register *******************/
bogdanm 73:1efda918f0ba 3978 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3979 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3980 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3981 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3982 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3983 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3984
bogdanm 73:1efda918f0ba 3985 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3986 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3987 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3988 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3989 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3990 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3991
bogdanm 73:1efda918f0ba 3992 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
bogdanm 73:1efda918f0ba 3993 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 3994 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 3995 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 3996 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 3997 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 3998
bogdanm 73:1efda918f0ba 3999 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 4000 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4001 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4002 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4003 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4004 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4005
bogdanm 73:1efda918f0ba 4006 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 4007 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4008 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4009 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4010 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4011 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4012
bogdanm 73:1efda918f0ba 4013 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
bogdanm 73:1efda918f0ba 4014 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4015 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4016 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4017 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4018 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4019
bogdanm 73:1efda918f0ba 4020 /******************* Bit definition for ADC_JSQR register *******************/
bogdanm 73:1efda918f0ba 4021 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
bogdanm 73:1efda918f0ba 4022 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4023 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4024 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4025 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4026 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4027
bogdanm 73:1efda918f0ba 4028 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
bogdanm 73:1efda918f0ba 4029 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4030 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4031 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4032 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4033 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4034
bogdanm 73:1efda918f0ba 4035 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
bogdanm 73:1efda918f0ba 4036 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4037 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4038 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4039 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4040 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4041
bogdanm 73:1efda918f0ba 4042 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
bogdanm 73:1efda918f0ba 4043 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4044 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4045 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4046 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4047 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4048
bogdanm 73:1efda918f0ba 4049 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
bogdanm 73:1efda918f0ba 4050 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4051 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4052
bogdanm 73:1efda918f0ba 4053 /******************* Bit definition for ADC_JDR1 register *******************/
bogdanm 73:1efda918f0ba 4054 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
bogdanm 73:1efda918f0ba 4055
bogdanm 73:1efda918f0ba 4056 /******************* Bit definition for ADC_JDR2 register *******************/
bogdanm 73:1efda918f0ba 4057 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
bogdanm 73:1efda918f0ba 4058
bogdanm 73:1efda918f0ba 4059 /******************* Bit definition for ADC_JDR3 register *******************/
bogdanm 73:1efda918f0ba 4060 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
bogdanm 73:1efda918f0ba 4061
bogdanm 73:1efda918f0ba 4062 /******************* Bit definition for ADC_JDR4 register *******************/
bogdanm 73:1efda918f0ba 4063 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
bogdanm 73:1efda918f0ba 4064
bogdanm 73:1efda918f0ba 4065 /******************** Bit definition for ADC_DR register ********************/
bogdanm 73:1efda918f0ba 4066 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
bogdanm 73:1efda918f0ba 4067 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */
bogdanm 73:1efda918f0ba 4068
bogdanm 73:1efda918f0ba 4069 /******************************************************************************/
bogdanm 73:1efda918f0ba 4070 /* */
bogdanm 73:1efda918f0ba 4071 /* Digital to Analog Converter */
bogdanm 73:1efda918f0ba 4072 /* */
bogdanm 73:1efda918f0ba 4073 /******************************************************************************/
bogdanm 73:1efda918f0ba 4074
bogdanm 73:1efda918f0ba 4075 /******************** Bit definition for DAC_CR register ********************/
bogdanm 73:1efda918f0ba 4076 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
bogdanm 73:1efda918f0ba 4077 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
bogdanm 73:1efda918f0ba 4078 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
bogdanm 73:1efda918f0ba 4079
bogdanm 73:1efda918f0ba 4080 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
bogdanm 73:1efda918f0ba 4081 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4082 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4083 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4084
bogdanm 73:1efda918f0ba 4085 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
bogdanm 73:1efda918f0ba 4086 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4087 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4088
bogdanm 73:1efda918f0ba 4089 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
bogdanm 73:1efda918f0ba 4090 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4091 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4092 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4093 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4094
bogdanm 73:1efda918f0ba 4095 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
bogdanm 73:1efda918f0ba 4096 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
bogdanm 73:1efda918f0ba 4097 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
bogdanm 73:1efda918f0ba 4098 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
bogdanm 73:1efda918f0ba 4099
bogdanm 73:1efda918f0ba 4100 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
bogdanm 73:1efda918f0ba 4101 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4102 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4103 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4104
bogdanm 73:1efda918f0ba 4105 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
bogdanm 73:1efda918f0ba 4106 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4107 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4108
bogdanm 73:1efda918f0ba 4109 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
bogdanm 73:1efda918f0ba 4110 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4111 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4112 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4113 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4114
bogdanm 73:1efda918f0ba 4115 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
bogdanm 73:1efda918f0ba 4116
emilmont 77:869cf507173a 4117 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
emilmont 77:869cf507173a 4118 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */
emilmont 77:869cf507173a 4119 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */
emilmont 77:869cf507173a 4120 #endif
emilmont 77:869cf507173a 4121
bogdanm 73:1efda918f0ba 4122 /***************** Bit definition for DAC_SWTRIGR register ******************/
bogdanm 73:1efda918f0ba 4123 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
bogdanm 73:1efda918f0ba 4124 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
bogdanm 73:1efda918f0ba 4125
bogdanm 73:1efda918f0ba 4126 /***************** Bit definition for DAC_DHR12R1 register ******************/
bogdanm 73:1efda918f0ba 4127 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 73:1efda918f0ba 4128
bogdanm 73:1efda918f0ba 4129 /***************** Bit definition for DAC_DHR12L1 register ******************/
bogdanm 73:1efda918f0ba 4130 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 73:1efda918f0ba 4131
bogdanm 73:1efda918f0ba 4132 /****************** Bit definition for DAC_DHR8R1 register ******************/
bogdanm 73:1efda918f0ba 4133 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 73:1efda918f0ba 4134
bogdanm 73:1efda918f0ba 4135 /***************** Bit definition for DAC_DHR12R2 register ******************/
bogdanm 73:1efda918f0ba 4136 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 73:1efda918f0ba 4137
bogdanm 73:1efda918f0ba 4138 /***************** Bit definition for DAC_DHR12L2 register ******************/
bogdanm 73:1efda918f0ba 4139 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 73:1efda918f0ba 4140
bogdanm 73:1efda918f0ba 4141 /****************** Bit definition for DAC_DHR8R2 register ******************/
bogdanm 73:1efda918f0ba 4142 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 73:1efda918f0ba 4143
bogdanm 73:1efda918f0ba 4144 /***************** Bit definition for DAC_DHR12RD register ******************/
bogdanm 73:1efda918f0ba 4145 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 73:1efda918f0ba 4146 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 73:1efda918f0ba 4147
bogdanm 73:1efda918f0ba 4148 /***************** Bit definition for DAC_DHR12LD register ******************/
bogdanm 73:1efda918f0ba 4149 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 73:1efda918f0ba 4150 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 73:1efda918f0ba 4151
bogdanm 73:1efda918f0ba 4152 /****************** Bit definition for DAC_DHR8RD register ******************/
bogdanm 73:1efda918f0ba 4153 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 73:1efda918f0ba 4154 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 73:1efda918f0ba 4155
bogdanm 73:1efda918f0ba 4156 /******************* Bit definition for DAC_DOR1 register *******************/
bogdanm 73:1efda918f0ba 4157 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
bogdanm 73:1efda918f0ba 4158
bogdanm 73:1efda918f0ba 4159 /******************* Bit definition for DAC_DOR2 register *******************/
bogdanm 73:1efda918f0ba 4160 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
bogdanm 73:1efda918f0ba 4161
bogdanm 73:1efda918f0ba 4162 /******************** Bit definition for DAC_SR register ********************/
bogdanm 73:1efda918f0ba 4163 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
bogdanm 73:1efda918f0ba 4164 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
bogdanm 73:1efda918f0ba 4165
bogdanm 73:1efda918f0ba 4166 /******************************************************************************/
bogdanm 73:1efda918f0ba 4167 /* */
bogdanm 73:1efda918f0ba 4168 /* CEC */
bogdanm 73:1efda918f0ba 4169 /* */
bogdanm 73:1efda918f0ba 4170 /******************************************************************************/
bogdanm 73:1efda918f0ba 4171 /******************** Bit definition for CEC_CFGR register ******************/
bogdanm 73:1efda918f0ba 4172 #define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
bogdanm 73:1efda918f0ba 4173 #define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
bogdanm 73:1efda918f0ba 4174 #define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
bogdanm 73:1efda918f0ba 4175 #define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
bogdanm 73:1efda918f0ba 4176
bogdanm 73:1efda918f0ba 4177 /******************** Bit definition for CEC_OAR register ******************/
bogdanm 73:1efda918f0ba 4178 #define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
bogdanm 73:1efda918f0ba 4179 #define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4180 #define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4181 #define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4182 #define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4183
bogdanm 73:1efda918f0ba 4184 /******************** Bit definition for CEC_PRES register ******************/
bogdanm 73:1efda918f0ba 4185 #define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
bogdanm 73:1efda918f0ba 4186
bogdanm 73:1efda918f0ba 4187 /******************** Bit definition for CEC_ESR register ******************/
bogdanm 73:1efda918f0ba 4188 #define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
bogdanm 73:1efda918f0ba 4189 #define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
bogdanm 73:1efda918f0ba 4190 #define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
bogdanm 73:1efda918f0ba 4191 #define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
bogdanm 73:1efda918f0ba 4192 #define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
bogdanm 73:1efda918f0ba 4193 #define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
bogdanm 73:1efda918f0ba 4194 #define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */
bogdanm 73:1efda918f0ba 4195
bogdanm 73:1efda918f0ba 4196 /******************** Bit definition for CEC_CSR register ******************/
bogdanm 73:1efda918f0ba 4197 #define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
bogdanm 73:1efda918f0ba 4198 #define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
bogdanm 73:1efda918f0ba 4199 #define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
bogdanm 73:1efda918f0ba 4200 #define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
bogdanm 73:1efda918f0ba 4201 #define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
bogdanm 73:1efda918f0ba 4202 #define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
bogdanm 73:1efda918f0ba 4203 #define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
bogdanm 73:1efda918f0ba 4204 #define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
bogdanm 73:1efda918f0ba 4205
bogdanm 73:1efda918f0ba 4206 /******************** Bit definition for CEC_TXD register ******************/
bogdanm 73:1efda918f0ba 4207 #define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
bogdanm 73:1efda918f0ba 4208
bogdanm 73:1efda918f0ba 4209 /******************** Bit definition for CEC_RXD register ******************/
bogdanm 73:1efda918f0ba 4210 #define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
bogdanm 73:1efda918f0ba 4211
bogdanm 73:1efda918f0ba 4212 /******************************************************************************/
bogdanm 73:1efda918f0ba 4213 /* */
bogdanm 73:1efda918f0ba 4214 /* TIM */
bogdanm 73:1efda918f0ba 4215 /* */
bogdanm 73:1efda918f0ba 4216 /******************************************************************************/
bogdanm 73:1efda918f0ba 4217
bogdanm 73:1efda918f0ba 4218 /******************* Bit definition for TIM_CR1 register ********************/
bogdanm 73:1efda918f0ba 4219 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */
bogdanm 73:1efda918f0ba 4220 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */
bogdanm 73:1efda918f0ba 4221 #define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */
bogdanm 73:1efda918f0ba 4222 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */
bogdanm 73:1efda918f0ba 4223 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */
bogdanm 73:1efda918f0ba 4224
bogdanm 73:1efda918f0ba 4225 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 73:1efda918f0ba 4226 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4227 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4228
bogdanm 73:1efda918f0ba 4229 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */
bogdanm 73:1efda918f0ba 4230
bogdanm 73:1efda918f0ba 4231 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */
bogdanm 73:1efda918f0ba 4232 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4233 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4234
bogdanm 73:1efda918f0ba 4235 /******************* Bit definition for TIM_CR2 register ********************/
bogdanm 73:1efda918f0ba 4236 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */
bogdanm 73:1efda918f0ba 4237 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */
bogdanm 73:1efda918f0ba 4238 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */
bogdanm 73:1efda918f0ba 4239
bogdanm 73:1efda918f0ba 4240 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */
bogdanm 73:1efda918f0ba 4241 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4242 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4243 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4244
bogdanm 73:1efda918f0ba 4245 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */
bogdanm 73:1efda918f0ba 4246 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */
bogdanm 73:1efda918f0ba 4247 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */
bogdanm 73:1efda918f0ba 4248 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */
bogdanm 73:1efda918f0ba 4249 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */
bogdanm 73:1efda918f0ba 4250 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */
bogdanm 73:1efda918f0ba 4251 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */
bogdanm 73:1efda918f0ba 4252 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */
bogdanm 73:1efda918f0ba 4253
bogdanm 73:1efda918f0ba 4254 /******************* Bit definition for TIM_SMCR register *******************/
bogdanm 73:1efda918f0ba 4255 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
bogdanm 73:1efda918f0ba 4256 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4257 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4258 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4259
bogdanm 73:1efda918f0ba 4260 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
bogdanm 73:1efda918f0ba 4261 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4262 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4263 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4264
bogdanm 73:1efda918f0ba 4265 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */
bogdanm 73:1efda918f0ba 4266
bogdanm 73:1efda918f0ba 4267 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
bogdanm 73:1efda918f0ba 4268 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4269 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4270 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4271 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4272
bogdanm 73:1efda918f0ba 4273 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
bogdanm 73:1efda918f0ba 4274 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4275 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4276
bogdanm 73:1efda918f0ba 4277 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */
bogdanm 73:1efda918f0ba 4278 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */
bogdanm 73:1efda918f0ba 4279
bogdanm 73:1efda918f0ba 4280 /******************* Bit definition for TIM_DIER register *******************/
bogdanm 73:1efda918f0ba 4281 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */
bogdanm 73:1efda918f0ba 4282 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
bogdanm 73:1efda918f0ba 4283 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
bogdanm 73:1efda918f0ba 4284 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
bogdanm 73:1efda918f0ba 4285 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
bogdanm 73:1efda918f0ba 4286 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */
bogdanm 73:1efda918f0ba 4287 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */
bogdanm 73:1efda918f0ba 4288 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */
bogdanm 73:1efda918f0ba 4289 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */
bogdanm 73:1efda918f0ba 4290 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
bogdanm 73:1efda918f0ba 4291 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
bogdanm 73:1efda918f0ba 4292 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
bogdanm 73:1efda918f0ba 4293 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
bogdanm 73:1efda918f0ba 4294 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */
bogdanm 73:1efda918f0ba 4295 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */
bogdanm 73:1efda918f0ba 4296
bogdanm 73:1efda918f0ba 4297 /******************** Bit definition for TIM_SR register ********************/
bogdanm 73:1efda918f0ba 4298 #define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */
bogdanm 73:1efda918f0ba 4299 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */
bogdanm 73:1efda918f0ba 4300 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */
bogdanm 73:1efda918f0ba 4301 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */
bogdanm 73:1efda918f0ba 4302 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */
bogdanm 73:1efda918f0ba 4303 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */
bogdanm 73:1efda918f0ba 4304 #define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */
bogdanm 73:1efda918f0ba 4305 #define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */
bogdanm 73:1efda918f0ba 4306 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */
bogdanm 73:1efda918f0ba 4307 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */
bogdanm 73:1efda918f0ba 4308 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */
bogdanm 73:1efda918f0ba 4309 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */
bogdanm 73:1efda918f0ba 4310
bogdanm 73:1efda918f0ba 4311 /******************* Bit definition for TIM_EGR register ********************/
bogdanm 73:1efda918f0ba 4312 #define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */
bogdanm 73:1efda918f0ba 4313 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
bogdanm 73:1efda918f0ba 4314 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
bogdanm 73:1efda918f0ba 4315 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
bogdanm 73:1efda918f0ba 4316 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
bogdanm 73:1efda918f0ba 4317 #define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
bogdanm 73:1efda918f0ba 4318 #define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */
bogdanm 73:1efda918f0ba 4319 #define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */
bogdanm 73:1efda918f0ba 4320
bogdanm 73:1efda918f0ba 4321 /****************** Bit definition for TIM_CCMR1 register *******************/
bogdanm 73:1efda918f0ba 4322 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 73:1efda918f0ba 4323 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4324 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4325
bogdanm 73:1efda918f0ba 4326 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
bogdanm 73:1efda918f0ba 4327 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
bogdanm 73:1efda918f0ba 4328
bogdanm 73:1efda918f0ba 4329 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 73:1efda918f0ba 4330 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4331 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4332 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4333
bogdanm 73:1efda918f0ba 4334 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
bogdanm 73:1efda918f0ba 4335
bogdanm 73:1efda918f0ba 4336 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 73:1efda918f0ba 4337 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4338 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4339
bogdanm 73:1efda918f0ba 4340 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
bogdanm 73:1efda918f0ba 4341 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
bogdanm 73:1efda918f0ba 4342
bogdanm 73:1efda918f0ba 4343 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 73:1efda918f0ba 4344 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4345 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4346 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4347
bogdanm 73:1efda918f0ba 4348 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
bogdanm 73:1efda918f0ba 4349
bogdanm 73:1efda918f0ba 4350 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 4351
bogdanm 73:1efda918f0ba 4352 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 73:1efda918f0ba 4353 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4354 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4355
bogdanm 73:1efda918f0ba 4356 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 73:1efda918f0ba 4357 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4358 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4359 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4360 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4361
bogdanm 73:1efda918f0ba 4362 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 73:1efda918f0ba 4363 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4364 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4365
bogdanm 73:1efda918f0ba 4366 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 73:1efda918f0ba 4367 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4368 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4369 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4370 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4371
bogdanm 73:1efda918f0ba 4372 /****************** Bit definition for TIM_CCMR2 register *******************/
bogdanm 73:1efda918f0ba 4373 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 73:1efda918f0ba 4374 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4375 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4376
bogdanm 73:1efda918f0ba 4377 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
bogdanm 73:1efda918f0ba 4378 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
bogdanm 73:1efda918f0ba 4379
bogdanm 73:1efda918f0ba 4380 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 73:1efda918f0ba 4381 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4382 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4383 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4384
bogdanm 73:1efda918f0ba 4385 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
bogdanm 73:1efda918f0ba 4386
bogdanm 73:1efda918f0ba 4387 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 73:1efda918f0ba 4388 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4389 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4390
bogdanm 73:1efda918f0ba 4391 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
bogdanm 73:1efda918f0ba 4392 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
bogdanm 73:1efda918f0ba 4393
bogdanm 73:1efda918f0ba 4394 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 73:1efda918f0ba 4395 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4396 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4397 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4398
bogdanm 73:1efda918f0ba 4399 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
bogdanm 73:1efda918f0ba 4400
bogdanm 73:1efda918f0ba 4401 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 4402
bogdanm 73:1efda918f0ba 4403 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 73:1efda918f0ba 4404 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4405 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4406
bogdanm 73:1efda918f0ba 4407 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 73:1efda918f0ba 4408 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4409 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4410 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4411 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4412
bogdanm 73:1efda918f0ba 4413 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 73:1efda918f0ba 4414 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4415 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4416
bogdanm 73:1efda918f0ba 4417 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 73:1efda918f0ba 4418 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4419 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4420 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4421 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4422
bogdanm 73:1efda918f0ba 4423 /******************* Bit definition for TIM_CCER register *******************/
bogdanm 73:1efda918f0ba 4424 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */
bogdanm 73:1efda918f0ba 4425 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */
bogdanm 73:1efda918f0ba 4426 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */
bogdanm 73:1efda918f0ba 4427 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */
bogdanm 73:1efda918f0ba 4428 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */
bogdanm 73:1efda918f0ba 4429 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */
bogdanm 73:1efda918f0ba 4430 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */
bogdanm 73:1efda918f0ba 4431 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */
bogdanm 73:1efda918f0ba 4432 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */
bogdanm 73:1efda918f0ba 4433 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */
bogdanm 73:1efda918f0ba 4434 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */
bogdanm 73:1efda918f0ba 4435 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */
bogdanm 73:1efda918f0ba 4436 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */
bogdanm 73:1efda918f0ba 4437 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */
bogdanm 73:1efda918f0ba 4438 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */
bogdanm 73:1efda918f0ba 4439
bogdanm 73:1efda918f0ba 4440 /******************* Bit definition for TIM_CNT register ********************/
bogdanm 73:1efda918f0ba 4441 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
bogdanm 73:1efda918f0ba 4442
bogdanm 73:1efda918f0ba 4443 /******************* Bit definition for TIM_PSC register ********************/
bogdanm 73:1efda918f0ba 4444 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
bogdanm 73:1efda918f0ba 4445
bogdanm 73:1efda918f0ba 4446 /******************* Bit definition for TIM_ARR register ********************/
bogdanm 73:1efda918f0ba 4447 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
bogdanm 73:1efda918f0ba 4448
bogdanm 73:1efda918f0ba 4449 /******************* Bit definition for TIM_RCR register ********************/
bogdanm 73:1efda918f0ba 4450 #define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */
bogdanm 73:1efda918f0ba 4451
bogdanm 73:1efda918f0ba 4452 /******************* Bit definition for TIM_CCR1 register *******************/
bogdanm 73:1efda918f0ba 4453 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
bogdanm 73:1efda918f0ba 4454
bogdanm 73:1efda918f0ba 4455 /******************* Bit definition for TIM_CCR2 register *******************/
bogdanm 73:1efda918f0ba 4456 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
bogdanm 73:1efda918f0ba 4457
bogdanm 73:1efda918f0ba 4458 /******************* Bit definition for TIM_CCR3 register *******************/
bogdanm 73:1efda918f0ba 4459 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
bogdanm 73:1efda918f0ba 4460
bogdanm 73:1efda918f0ba 4461 /******************* Bit definition for TIM_CCR4 register *******************/
bogdanm 73:1efda918f0ba 4462 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
bogdanm 73:1efda918f0ba 4463
bogdanm 73:1efda918f0ba 4464 /******************* Bit definition for TIM_BDTR register *******************/
bogdanm 73:1efda918f0ba 4465 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 73:1efda918f0ba 4466 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4467 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4468 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4469 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4470 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4471 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 4472 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 4473 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 4474
bogdanm 73:1efda918f0ba 4475 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
bogdanm 73:1efda918f0ba 4476 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4477 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4478
bogdanm 73:1efda918f0ba 4479 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
bogdanm 73:1efda918f0ba 4480 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
bogdanm 73:1efda918f0ba 4481 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */
bogdanm 73:1efda918f0ba 4482 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */
bogdanm 73:1efda918f0ba 4483 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */
bogdanm 73:1efda918f0ba 4484 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */
bogdanm 73:1efda918f0ba 4485
bogdanm 73:1efda918f0ba 4486 /******************* Bit definition for TIM_DCR register ********************/
bogdanm 73:1efda918f0ba 4487 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
bogdanm 73:1efda918f0ba 4488 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4489 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4490 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4491 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4492 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4493
bogdanm 73:1efda918f0ba 4494 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
bogdanm 73:1efda918f0ba 4495 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4496 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4497 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4498 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4499 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4500
bogdanm 73:1efda918f0ba 4501 /******************* Bit definition for TIM_DMAR register *******************/
bogdanm 73:1efda918f0ba 4502 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
bogdanm 73:1efda918f0ba 4503
bogdanm 73:1efda918f0ba 4504 /******************************************************************************/
bogdanm 73:1efda918f0ba 4505 /* */
bogdanm 73:1efda918f0ba 4506 /* Real-Time Clock */
bogdanm 73:1efda918f0ba 4507 /* */
bogdanm 73:1efda918f0ba 4508 /******************************************************************************/
bogdanm 73:1efda918f0ba 4509
bogdanm 73:1efda918f0ba 4510 /******************* Bit definition for RTC_CRH register ********************/
bogdanm 73:1efda918f0ba 4511 #define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */
bogdanm 73:1efda918f0ba 4512 #define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */
bogdanm 73:1efda918f0ba 4513 #define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */
bogdanm 73:1efda918f0ba 4514
bogdanm 73:1efda918f0ba 4515 /******************* Bit definition for RTC_CRL register ********************/
bogdanm 73:1efda918f0ba 4516 #define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */
bogdanm 73:1efda918f0ba 4517 #define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */
bogdanm 73:1efda918f0ba 4518 #define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */
bogdanm 73:1efda918f0ba 4519 #define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */
bogdanm 73:1efda918f0ba 4520 #define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */
bogdanm 73:1efda918f0ba 4521 #define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */
bogdanm 73:1efda918f0ba 4522
bogdanm 73:1efda918f0ba 4523 /******************* Bit definition for RTC_PRLH register *******************/
bogdanm 73:1efda918f0ba 4524 #define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */
bogdanm 73:1efda918f0ba 4525
bogdanm 73:1efda918f0ba 4526 /******************* Bit definition for RTC_PRLL register *******************/
bogdanm 73:1efda918f0ba 4527 #define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */
bogdanm 73:1efda918f0ba 4528
bogdanm 73:1efda918f0ba 4529 /******************* Bit definition for RTC_DIVH register *******************/
bogdanm 73:1efda918f0ba 4530 #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */
bogdanm 73:1efda918f0ba 4531
bogdanm 73:1efda918f0ba 4532 /******************* Bit definition for RTC_DIVL register *******************/
bogdanm 73:1efda918f0ba 4533 #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */
bogdanm 73:1efda918f0ba 4534
bogdanm 73:1efda918f0ba 4535 /******************* Bit definition for RTC_CNTH register *******************/
bogdanm 73:1efda918f0ba 4536 #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */
bogdanm 73:1efda918f0ba 4537
bogdanm 73:1efda918f0ba 4538 /******************* Bit definition for RTC_CNTL register *******************/
bogdanm 73:1efda918f0ba 4539 #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */
bogdanm 73:1efda918f0ba 4540
bogdanm 73:1efda918f0ba 4541 /******************* Bit definition for RTC_ALRH register *******************/
bogdanm 73:1efda918f0ba 4542 #define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */
bogdanm 73:1efda918f0ba 4543
bogdanm 73:1efda918f0ba 4544 /******************* Bit definition for RTC_ALRL register *******************/
bogdanm 73:1efda918f0ba 4545 #define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */
bogdanm 73:1efda918f0ba 4546
bogdanm 73:1efda918f0ba 4547 /******************************************************************************/
bogdanm 73:1efda918f0ba 4548 /* */
bogdanm 73:1efda918f0ba 4549 /* Independent WATCHDOG */
bogdanm 73:1efda918f0ba 4550 /* */
bogdanm 73:1efda918f0ba 4551 /******************************************************************************/
bogdanm 73:1efda918f0ba 4552
bogdanm 73:1efda918f0ba 4553 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 73:1efda918f0ba 4554 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
bogdanm 73:1efda918f0ba 4555
bogdanm 73:1efda918f0ba 4556 /******************* Bit definition for IWDG_PR register ********************/
bogdanm 73:1efda918f0ba 4557 #define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
bogdanm 73:1efda918f0ba 4558 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4559 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4560 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4561
bogdanm 73:1efda918f0ba 4562 /******************* Bit definition for IWDG_RLR register *******************/
bogdanm 73:1efda918f0ba 4563 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
bogdanm 73:1efda918f0ba 4564
bogdanm 73:1efda918f0ba 4565 /******************* Bit definition for IWDG_SR register ********************/
bogdanm 73:1efda918f0ba 4566 #define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
bogdanm 73:1efda918f0ba 4567 #define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
bogdanm 73:1efda918f0ba 4568
bogdanm 73:1efda918f0ba 4569 /******************************************************************************/
bogdanm 73:1efda918f0ba 4570 /* */
bogdanm 73:1efda918f0ba 4571 /* Window WATCHDOG */
bogdanm 73:1efda918f0ba 4572 /* */
bogdanm 73:1efda918f0ba 4573 /******************************************************************************/
bogdanm 73:1efda918f0ba 4574
bogdanm 73:1efda918f0ba 4575 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 73:1efda918f0ba 4576 #define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 73:1efda918f0ba 4577 #define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4578 #define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4579 #define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4580 #define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4581 #define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4582 #define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 4583 #define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 4584
bogdanm 73:1efda918f0ba 4585 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
bogdanm 73:1efda918f0ba 4586
bogdanm 73:1efda918f0ba 4587 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 73:1efda918f0ba 4588 #define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
bogdanm 73:1efda918f0ba 4589 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4590 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4591 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4592 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4593 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 4594 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 4595 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 4596
bogdanm 73:1efda918f0ba 4597 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
bogdanm 73:1efda918f0ba 4598 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4599 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4600
bogdanm 73:1efda918f0ba 4601 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
bogdanm 73:1efda918f0ba 4602
bogdanm 73:1efda918f0ba 4603 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 73:1efda918f0ba 4604 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
bogdanm 73:1efda918f0ba 4605
bogdanm 73:1efda918f0ba 4606 /******************************************************************************/
bogdanm 73:1efda918f0ba 4607 /* */
bogdanm 73:1efda918f0ba 4608 /* Flexible Static Memory Controller */
bogdanm 73:1efda918f0ba 4609 /* */
bogdanm 73:1efda918f0ba 4610 /******************************************************************************/
bogdanm 73:1efda918f0ba 4611
bogdanm 73:1efda918f0ba 4612 /****************** Bit definition for FSMC_BCR1 register *******************/
bogdanm 73:1efda918f0ba 4613 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
bogdanm 73:1efda918f0ba 4614 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
bogdanm 73:1efda918f0ba 4615
bogdanm 73:1efda918f0ba 4616 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
bogdanm 73:1efda918f0ba 4617 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4618 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4619
bogdanm 73:1efda918f0ba 4620 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
bogdanm 73:1efda918f0ba 4621 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4622 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4623
bogdanm 73:1efda918f0ba 4624 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
bogdanm 73:1efda918f0ba 4625 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
bogdanm 73:1efda918f0ba 4626 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
bogdanm 73:1efda918f0ba 4627 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
bogdanm 73:1efda918f0ba 4628 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
bogdanm 73:1efda918f0ba 4629 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
bogdanm 73:1efda918f0ba 4630 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
bogdanm 73:1efda918f0ba 4631 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
bogdanm 73:1efda918f0ba 4632 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
bogdanm 73:1efda918f0ba 4633 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
bogdanm 73:1efda918f0ba 4634
bogdanm 73:1efda918f0ba 4635 /****************** Bit definition for FSMC_BCR2 register *******************/
bogdanm 73:1efda918f0ba 4636 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
bogdanm 73:1efda918f0ba 4637 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
bogdanm 73:1efda918f0ba 4638
bogdanm 73:1efda918f0ba 4639 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
bogdanm 73:1efda918f0ba 4640 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4641 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4642
bogdanm 73:1efda918f0ba 4643 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
bogdanm 73:1efda918f0ba 4644 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4645 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4646
bogdanm 73:1efda918f0ba 4647 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
bogdanm 73:1efda918f0ba 4648 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
bogdanm 73:1efda918f0ba 4649 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
bogdanm 73:1efda918f0ba 4650 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
bogdanm 73:1efda918f0ba 4651 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
bogdanm 73:1efda918f0ba 4652 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
bogdanm 73:1efda918f0ba 4653 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
bogdanm 73:1efda918f0ba 4654 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
bogdanm 73:1efda918f0ba 4655 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
bogdanm 73:1efda918f0ba 4656 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
bogdanm 73:1efda918f0ba 4657
bogdanm 73:1efda918f0ba 4658 /****************** Bit definition for FSMC_BCR3 register *******************/
bogdanm 73:1efda918f0ba 4659 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
bogdanm 73:1efda918f0ba 4660 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
bogdanm 73:1efda918f0ba 4661
bogdanm 73:1efda918f0ba 4662 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
bogdanm 73:1efda918f0ba 4663 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4664 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4665
bogdanm 73:1efda918f0ba 4666 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
bogdanm 73:1efda918f0ba 4667 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4668 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4669
bogdanm 73:1efda918f0ba 4670 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
bogdanm 73:1efda918f0ba 4671 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
bogdanm 73:1efda918f0ba 4672 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
bogdanm 73:1efda918f0ba 4673 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
bogdanm 73:1efda918f0ba 4674 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
bogdanm 73:1efda918f0ba 4675 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
bogdanm 73:1efda918f0ba 4676 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
bogdanm 73:1efda918f0ba 4677 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
bogdanm 73:1efda918f0ba 4678 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
bogdanm 73:1efda918f0ba 4679 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
bogdanm 73:1efda918f0ba 4680
bogdanm 73:1efda918f0ba 4681 /****************** Bit definition for FSMC_BCR4 register *******************/
bogdanm 73:1efda918f0ba 4682 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
bogdanm 73:1efda918f0ba 4683 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
bogdanm 73:1efda918f0ba 4684
bogdanm 73:1efda918f0ba 4685 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
bogdanm 73:1efda918f0ba 4686 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4687 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4688
bogdanm 73:1efda918f0ba 4689 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
bogdanm 73:1efda918f0ba 4690 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4691 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4692
bogdanm 73:1efda918f0ba 4693 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
bogdanm 73:1efda918f0ba 4694 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
bogdanm 73:1efda918f0ba 4695 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
bogdanm 73:1efda918f0ba 4696 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
bogdanm 73:1efda918f0ba 4697 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
bogdanm 73:1efda918f0ba 4698 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
bogdanm 73:1efda918f0ba 4699 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
bogdanm 73:1efda918f0ba 4700 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
bogdanm 73:1efda918f0ba 4701 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
bogdanm 73:1efda918f0ba 4702 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
bogdanm 73:1efda918f0ba 4703
bogdanm 73:1efda918f0ba 4704 /****************** Bit definition for FSMC_BTR1 register ******************/
bogdanm 73:1efda918f0ba 4705 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 73:1efda918f0ba 4706 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4707 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4708 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4709 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4710
bogdanm 73:1efda918f0ba 4711 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 73:1efda918f0ba 4712 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4713 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4714 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4715 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4716
bogdanm 73:1efda918f0ba 4717 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
bogdanm 73:1efda918f0ba 4718 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4719 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4720 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4721 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 4722 #define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
emilmont 77:869cf507173a 4723 #define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
emilmont 77:869cf507173a 4724 #define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
emilmont 77:869cf507173a 4725 #define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 4726
bogdanm 73:1efda918f0ba 4727 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 73:1efda918f0ba 4728 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4729 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4730 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4731 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4732
bogdanm 73:1efda918f0ba 4733 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 73:1efda918f0ba 4734 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4735 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4736 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4737 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4738
bogdanm 73:1efda918f0ba 4739 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
bogdanm 73:1efda918f0ba 4740 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4741 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4742 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4743 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4744
bogdanm 73:1efda918f0ba 4745 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
bogdanm 73:1efda918f0ba 4746 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4747 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4748
bogdanm 73:1efda918f0ba 4749 /****************** Bit definition for FSMC_BTR2 register *******************/
bogdanm 73:1efda918f0ba 4750 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 73:1efda918f0ba 4751 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4752 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4753 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4754 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4755
bogdanm 73:1efda918f0ba 4756 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 73:1efda918f0ba 4757 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4758 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4759 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4760 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4761
bogdanm 73:1efda918f0ba 4762 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
bogdanm 73:1efda918f0ba 4763 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4764 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4765 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4766 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 4767 #define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
emilmont 77:869cf507173a 4768 #define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
emilmont 77:869cf507173a 4769 #define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
emilmont 77:869cf507173a 4770 #define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 4771
bogdanm 73:1efda918f0ba 4772 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 73:1efda918f0ba 4773 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4774 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4775 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4776 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4777
bogdanm 73:1efda918f0ba 4778 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 73:1efda918f0ba 4779 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4780 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4781 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4782 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4783
bogdanm 73:1efda918f0ba 4784 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
bogdanm 73:1efda918f0ba 4785 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4786 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4787 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4788 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4789
bogdanm 73:1efda918f0ba 4790 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
bogdanm 73:1efda918f0ba 4791 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4792 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4793
bogdanm 73:1efda918f0ba 4794 /******************* Bit definition for FSMC_BTR3 register *******************/
bogdanm 73:1efda918f0ba 4795 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 73:1efda918f0ba 4796 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4797 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4798 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4799 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4800
bogdanm 73:1efda918f0ba 4801 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 73:1efda918f0ba 4802 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4803 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4804 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4805 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4806
bogdanm 73:1efda918f0ba 4807 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
bogdanm 73:1efda918f0ba 4808 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4809 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4810 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4811 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 4812 #define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
emilmont 77:869cf507173a 4813 #define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
emilmont 77:869cf507173a 4814 #define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
emilmont 77:869cf507173a 4815 #define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 4816
bogdanm 73:1efda918f0ba 4817 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 73:1efda918f0ba 4818 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4819 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4820 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4821 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4822
bogdanm 73:1efda918f0ba 4823 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 73:1efda918f0ba 4824 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4825 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4826 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4827 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4828
bogdanm 73:1efda918f0ba 4829 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
bogdanm 73:1efda918f0ba 4830 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4831 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4832 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4833 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4834
bogdanm 73:1efda918f0ba 4835 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
bogdanm 73:1efda918f0ba 4836 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4837 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4838
bogdanm 73:1efda918f0ba 4839 /****************** Bit definition for FSMC_BTR4 register *******************/
bogdanm 73:1efda918f0ba 4840 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 73:1efda918f0ba 4841 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4842 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4843 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4844 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4845
bogdanm 73:1efda918f0ba 4846 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 73:1efda918f0ba 4847 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4848 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4849 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4850 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4851
bogdanm 73:1efda918f0ba 4852 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
bogdanm 73:1efda918f0ba 4853 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4854 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4855 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4856 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 4857 #define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
emilmont 77:869cf507173a 4858 #define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
emilmont 77:869cf507173a 4859 #define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
emilmont 77:869cf507173a 4860 #define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 4861
bogdanm 73:1efda918f0ba 4862 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 73:1efda918f0ba 4863 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4864 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4865 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4866 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4867
bogdanm 73:1efda918f0ba 4868 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 73:1efda918f0ba 4869 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4870 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4871 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4872 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4873
bogdanm 73:1efda918f0ba 4874 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
bogdanm 73:1efda918f0ba 4875 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4876 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4877 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4878 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4879
bogdanm 73:1efda918f0ba 4880 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
bogdanm 73:1efda918f0ba 4881 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4882 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4883
bogdanm 73:1efda918f0ba 4884 /****************** Bit definition for FSMC_BWTR1 register ******************/
bogdanm 73:1efda918f0ba 4885 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 73:1efda918f0ba 4886 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4887 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4888 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4889 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4890
bogdanm 73:1efda918f0ba 4891 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 73:1efda918f0ba 4892 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4893 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4894 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4895 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4896
bogdanm 73:1efda918f0ba 4897 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
bogdanm 73:1efda918f0ba 4898 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4899 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4900 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4901 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 4902 #define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
emilmont 77:869cf507173a 4903 #define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
emilmont 77:869cf507173a 4904 #define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
emilmont 77:869cf507173a 4905 #define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 4906
bogdanm 73:1efda918f0ba 4907 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 73:1efda918f0ba 4908 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4909 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4910 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4911 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4912
bogdanm 73:1efda918f0ba 4913 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
bogdanm 73:1efda918f0ba 4914 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4915 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4916 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4917 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4918
bogdanm 73:1efda918f0ba 4919 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
bogdanm 73:1efda918f0ba 4920 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4921 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4922
bogdanm 73:1efda918f0ba 4923 /****************** Bit definition for FSMC_BWTR2 register ******************/
bogdanm 73:1efda918f0ba 4924 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 73:1efda918f0ba 4925 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4926 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4927 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4928 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4929
bogdanm 73:1efda918f0ba 4930 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 73:1efda918f0ba 4931 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4932 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4933 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4934 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4935
bogdanm 73:1efda918f0ba 4936 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
bogdanm 73:1efda918f0ba 4937 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4938 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4939 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4940 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 4941 #define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
emilmont 77:869cf507173a 4942 #define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
emilmont 77:869cf507173a 4943 #define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
emilmont 77:869cf507173a 4944 #define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 4945
bogdanm 73:1efda918f0ba 4946 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 73:1efda918f0ba 4947 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4948 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
bogdanm 73:1efda918f0ba 4949 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4950 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4951
bogdanm 73:1efda918f0ba 4952 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
bogdanm 73:1efda918f0ba 4953 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4954 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4955 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4956 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4957
bogdanm 73:1efda918f0ba 4958 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
bogdanm 73:1efda918f0ba 4959 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4960 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4961
bogdanm 73:1efda918f0ba 4962 /****************** Bit definition for FSMC_BWTR3 register ******************/
bogdanm 73:1efda918f0ba 4963 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 73:1efda918f0ba 4964 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4965 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4966 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4967 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4968
bogdanm 73:1efda918f0ba 4969 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 73:1efda918f0ba 4970 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4971 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4972 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4973 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4974
bogdanm 73:1efda918f0ba 4975 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
bogdanm 73:1efda918f0ba 4976 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4977 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4978 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4979 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 4980 #define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
emilmont 77:869cf507173a 4981 #define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
emilmont 77:869cf507173a 4982 #define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
emilmont 77:869cf507173a 4983 #define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 4984
bogdanm 73:1efda918f0ba 4985 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 73:1efda918f0ba 4986 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4987 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4988 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4989 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4990
bogdanm 73:1efda918f0ba 4991 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
bogdanm 73:1efda918f0ba 4992 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4993 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 4994 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 4995 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 4996
bogdanm 73:1efda918f0ba 4997 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
bogdanm 73:1efda918f0ba 4998 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 4999 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5000
bogdanm 73:1efda918f0ba 5001 /****************** Bit definition for FSMC_BWTR4 register ******************/
bogdanm 73:1efda918f0ba 5002 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 73:1efda918f0ba 5003 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5004 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5005 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5006 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5007
bogdanm 73:1efda918f0ba 5008 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 73:1efda918f0ba 5009 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5010 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5011 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5012 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5013
bogdanm 73:1efda918f0ba 5014 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
bogdanm 73:1efda918f0ba 5015 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5016 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5017 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5018 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 5019 #define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
emilmont 77:869cf507173a 5020 #define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
emilmont 77:869cf507173a 5021 #define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
emilmont 77:869cf507173a 5022 #define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5023
bogdanm 73:1efda918f0ba 5024 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 73:1efda918f0ba 5025 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5026 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5027 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5028 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5029
bogdanm 73:1efda918f0ba 5030 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
bogdanm 73:1efda918f0ba 5031 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5032 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5033 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5034 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5035
bogdanm 73:1efda918f0ba 5036 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
bogdanm 73:1efda918f0ba 5037 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5038 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5039
bogdanm 73:1efda918f0ba 5040 /****************** Bit definition for FSMC_PCR2 register *******************/
bogdanm 73:1efda918f0ba 5041 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
bogdanm 73:1efda918f0ba 5042 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
bogdanm 73:1efda918f0ba 5043 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */
bogdanm 73:1efda918f0ba 5044
bogdanm 73:1efda918f0ba 5045 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
bogdanm 73:1efda918f0ba 5046 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5047 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5048
bogdanm 73:1efda918f0ba 5049 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
bogdanm 73:1efda918f0ba 5050
bogdanm 73:1efda918f0ba 5051 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
bogdanm 73:1efda918f0ba 5052 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5053 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5054 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5055 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5056
bogdanm 73:1efda918f0ba 5057 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
bogdanm 73:1efda918f0ba 5058 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5059 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5060 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5061 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5062
bogdanm 73:1efda918f0ba 5063 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
bogdanm 73:1efda918f0ba 5064 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5065 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5066 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5067
bogdanm 73:1efda918f0ba 5068 /****************** Bit definition for FSMC_PCR3 register *******************/
bogdanm 73:1efda918f0ba 5069 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
bogdanm 73:1efda918f0ba 5070 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
bogdanm 73:1efda918f0ba 5071 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */
bogdanm 73:1efda918f0ba 5072
bogdanm 73:1efda918f0ba 5073 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
bogdanm 73:1efda918f0ba 5074 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5075 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5076
bogdanm 73:1efda918f0ba 5077 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
bogdanm 73:1efda918f0ba 5078
bogdanm 73:1efda918f0ba 5079 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
bogdanm 73:1efda918f0ba 5080 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5081 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5082 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5083 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5084
bogdanm 73:1efda918f0ba 5085 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
bogdanm 73:1efda918f0ba 5086 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5087 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5088 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5089 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5090
bogdanm 73:1efda918f0ba 5091 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
bogdanm 73:1efda918f0ba 5092 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5093 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5094 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5095
bogdanm 73:1efda918f0ba 5096 /****************** Bit definition for FSMC_PCR4 register *******************/
bogdanm 73:1efda918f0ba 5097 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
bogdanm 73:1efda918f0ba 5098 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
bogdanm 73:1efda918f0ba 5099 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */
bogdanm 73:1efda918f0ba 5100
bogdanm 73:1efda918f0ba 5101 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
bogdanm 73:1efda918f0ba 5102 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5103 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5104
bogdanm 73:1efda918f0ba 5105 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
bogdanm 73:1efda918f0ba 5106
bogdanm 73:1efda918f0ba 5107 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
bogdanm 73:1efda918f0ba 5108 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5109 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5110 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5111 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5112
bogdanm 73:1efda918f0ba 5113 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
bogdanm 73:1efda918f0ba 5114 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5115 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5116 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5117 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5118
bogdanm 73:1efda918f0ba 5119 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
bogdanm 73:1efda918f0ba 5120 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5121 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5122 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5123
bogdanm 73:1efda918f0ba 5124 /******************* Bit definition for FSMC_SR2 register *******************/
bogdanm 73:1efda918f0ba 5125 #define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
bogdanm 73:1efda918f0ba 5126 #define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
bogdanm 73:1efda918f0ba 5127 #define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
bogdanm 73:1efda918f0ba 5128 #define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
bogdanm 73:1efda918f0ba 5129 #define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
bogdanm 73:1efda918f0ba 5130 #define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
bogdanm 73:1efda918f0ba 5131 #define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
bogdanm 73:1efda918f0ba 5132
bogdanm 73:1efda918f0ba 5133 /******************* Bit definition for FSMC_SR3 register *******************/
bogdanm 73:1efda918f0ba 5134 #define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
bogdanm 73:1efda918f0ba 5135 #define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
bogdanm 73:1efda918f0ba 5136 #define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
bogdanm 73:1efda918f0ba 5137 #define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
bogdanm 73:1efda918f0ba 5138 #define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
bogdanm 73:1efda918f0ba 5139 #define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
bogdanm 73:1efda918f0ba 5140 #define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
bogdanm 73:1efda918f0ba 5141
bogdanm 73:1efda918f0ba 5142 /******************* Bit definition for FSMC_SR4 register *******************/
bogdanm 73:1efda918f0ba 5143 #define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
bogdanm 73:1efda918f0ba 5144 #define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
bogdanm 73:1efda918f0ba 5145 #define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
bogdanm 73:1efda918f0ba 5146 #define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
bogdanm 73:1efda918f0ba 5147 #define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
bogdanm 73:1efda918f0ba 5148 #define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
bogdanm 73:1efda918f0ba 5149 #define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
bogdanm 73:1efda918f0ba 5150
bogdanm 73:1efda918f0ba 5151 /****************** Bit definition for FSMC_PMEM2 register ******************/
bogdanm 73:1efda918f0ba 5152 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
bogdanm 73:1efda918f0ba 5153 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5154 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5155 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5156 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5157 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5158 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5159 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5160 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5161
bogdanm 73:1efda918f0ba 5162 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
bogdanm 73:1efda918f0ba 5163 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5164 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5165 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5166 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5167 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5168 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5169 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5170 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5171
bogdanm 73:1efda918f0ba 5172 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
bogdanm 73:1efda918f0ba 5173 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5174 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5175 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5176 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5177 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5178 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5179 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5180 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5181
bogdanm 73:1efda918f0ba 5182 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
bogdanm 73:1efda918f0ba 5183 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5184 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5185 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5186 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5187 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5188 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5189 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5190 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5191
bogdanm 73:1efda918f0ba 5192 /****************** Bit definition for FSMC_PMEM3 register ******************/
bogdanm 73:1efda918f0ba 5193 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
bogdanm 73:1efda918f0ba 5194 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5195 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5196 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5197 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5198 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5199 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5200 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5201 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5202
bogdanm 73:1efda918f0ba 5203 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
bogdanm 73:1efda918f0ba 5204 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5205 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5206 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5207 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5208 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5209 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5210 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5211 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5212
bogdanm 73:1efda918f0ba 5213 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
bogdanm 73:1efda918f0ba 5214 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5215 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5216 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5217 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5218 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5219 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5220 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5221 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5222
bogdanm 73:1efda918f0ba 5223 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
bogdanm 73:1efda918f0ba 5224 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5225 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5226 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5227 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5228 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5229 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5230 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5231 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5232
bogdanm 73:1efda918f0ba 5233 /****************** Bit definition for FSMC_PMEM4 register ******************/
bogdanm 73:1efda918f0ba 5234 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
bogdanm 73:1efda918f0ba 5235 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5236 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5237 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5238 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5239 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5240 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5241 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5242 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5243
bogdanm 73:1efda918f0ba 5244 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
bogdanm 73:1efda918f0ba 5245 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5246 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5247 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5248 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5249 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5250 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5251 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5252 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5253
bogdanm 73:1efda918f0ba 5254 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
bogdanm 73:1efda918f0ba 5255 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5256 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5257 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5258 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5259 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5260 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5261 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5262 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5263
bogdanm 73:1efda918f0ba 5264 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
bogdanm 73:1efda918f0ba 5265 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5266 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5267 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5268 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5269 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5270 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5271 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5272 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5273
bogdanm 73:1efda918f0ba 5274 /****************** Bit definition for FSMC_PATT2 register ******************/
bogdanm 73:1efda918f0ba 5275 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
bogdanm 73:1efda918f0ba 5276 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5277 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5278 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5279 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5280 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5281 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5282 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5283 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5284
bogdanm 73:1efda918f0ba 5285 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
bogdanm 73:1efda918f0ba 5286 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5287 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5288 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5289 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5290 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5291 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5292 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5293 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5294
bogdanm 73:1efda918f0ba 5295 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
bogdanm 73:1efda918f0ba 5296 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5297 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5298 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5299 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5300 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5301 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5302 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5303 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5304
bogdanm 73:1efda918f0ba 5305 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
bogdanm 73:1efda918f0ba 5306 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5307 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5308 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5309 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5310 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5311 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5312 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5313 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5314
bogdanm 73:1efda918f0ba 5315 /****************** Bit definition for FSMC_PATT3 register ******************/
bogdanm 73:1efda918f0ba 5316 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
bogdanm 73:1efda918f0ba 5317 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5318 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5319 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5320 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5321 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5322 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5323 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5324 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5325
bogdanm 73:1efda918f0ba 5326 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
bogdanm 73:1efda918f0ba 5327 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5328 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5329 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5330 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5331 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5332 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5333 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5334 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5335
bogdanm 73:1efda918f0ba 5336 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
bogdanm 73:1efda918f0ba 5337 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5338 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5339 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5340 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5341 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5342 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5343 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5344 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5345
bogdanm 73:1efda918f0ba 5346 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
bogdanm 73:1efda918f0ba 5347 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5348 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5349 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5350 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5351 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5352 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5353 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5354 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5355
bogdanm 73:1efda918f0ba 5356 /****************** Bit definition for FSMC_PATT4 register ******************/
bogdanm 73:1efda918f0ba 5357 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
bogdanm 73:1efda918f0ba 5358 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5359 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5360 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5361 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5362 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5363 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5364 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5365 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5366
bogdanm 73:1efda918f0ba 5367 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
bogdanm 73:1efda918f0ba 5368 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5369 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5370 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5371 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5372 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5373 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5374 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5375 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5376
bogdanm 73:1efda918f0ba 5377 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
bogdanm 73:1efda918f0ba 5378 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5379 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5380 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5381 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5382 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5383 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5384 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5385 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5386
bogdanm 73:1efda918f0ba 5387 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
bogdanm 73:1efda918f0ba 5388 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5389 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5390 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5391 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5392 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5393 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5394 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5395 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5396
bogdanm 73:1efda918f0ba 5397 /****************** Bit definition for FSMC_PIO4 register *******************/
bogdanm 73:1efda918f0ba 5398 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */
bogdanm 73:1efda918f0ba 5399 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5400 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5401 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5402 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5403 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5404 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5405 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5406 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5407
bogdanm 73:1efda918f0ba 5408 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
bogdanm 73:1efda918f0ba 5409 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5410 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5411 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5412 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5413 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5414 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5415 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5416 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5417
bogdanm 73:1efda918f0ba 5418 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
bogdanm 73:1efda918f0ba 5419 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5420 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5421 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5422 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5423 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5424 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5425 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5426 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5427
bogdanm 73:1efda918f0ba 5428 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
bogdanm 73:1efda918f0ba 5429 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5430 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5431 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5432 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5433 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5434 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5435 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5436 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 5437
bogdanm 73:1efda918f0ba 5438 /****************** Bit definition for FSMC_ECCR2 register ******************/
bogdanm 73:1efda918f0ba 5439 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
bogdanm 73:1efda918f0ba 5440
bogdanm 73:1efda918f0ba 5441 /****************** Bit definition for FSMC_ECCR3 register ******************/
bogdanm 73:1efda918f0ba 5442 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
bogdanm 73:1efda918f0ba 5443
bogdanm 73:1efda918f0ba 5444 /******************************************************************************/
bogdanm 73:1efda918f0ba 5445 /* */
bogdanm 73:1efda918f0ba 5446 /* SD host Interface */
bogdanm 73:1efda918f0ba 5447 /* */
bogdanm 73:1efda918f0ba 5448 /******************************************************************************/
bogdanm 73:1efda918f0ba 5449
bogdanm 73:1efda918f0ba 5450 /****************** Bit definition for SDIO_POWER register ******************/
bogdanm 73:1efda918f0ba 5451 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
bogdanm 73:1efda918f0ba 5452 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5453 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5454
bogdanm 73:1efda918f0ba 5455 /****************** Bit definition for SDIO_CLKCR register ******************/
bogdanm 73:1efda918f0ba 5456 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */
bogdanm 73:1efda918f0ba 5457 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */
bogdanm 73:1efda918f0ba 5458 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */
bogdanm 73:1efda918f0ba 5459 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */
bogdanm 73:1efda918f0ba 5460
bogdanm 73:1efda918f0ba 5461 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
bogdanm 73:1efda918f0ba 5462 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5463 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5464
bogdanm 73:1efda918f0ba 5465 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */
bogdanm 73:1efda918f0ba 5466 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */
bogdanm 73:1efda918f0ba 5467
bogdanm 73:1efda918f0ba 5468 /******************* Bit definition for SDIO_ARG register *******************/
bogdanm 73:1efda918f0ba 5469 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
bogdanm 73:1efda918f0ba 5470
bogdanm 73:1efda918f0ba 5471 /******************* Bit definition for SDIO_CMD register *******************/
bogdanm 73:1efda918f0ba 5472 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */
bogdanm 73:1efda918f0ba 5473
bogdanm 73:1efda918f0ba 5474 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
bogdanm 73:1efda918f0ba 5475 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5476 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5477
bogdanm 73:1efda918f0ba 5478 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */
bogdanm 73:1efda918f0ba 5479 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
bogdanm 73:1efda918f0ba 5480 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
bogdanm 73:1efda918f0ba 5481 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */
bogdanm 73:1efda918f0ba 5482 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */
bogdanm 73:1efda918f0ba 5483 #define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */
bogdanm 73:1efda918f0ba 5484 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */
bogdanm 73:1efda918f0ba 5485
bogdanm 73:1efda918f0ba 5486 /***************** Bit definition for SDIO_RESPCMD register *****************/
bogdanm 73:1efda918f0ba 5487 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */
bogdanm 73:1efda918f0ba 5488
bogdanm 73:1efda918f0ba 5489 /****************** Bit definition for SDIO_RESP0 register ******************/
bogdanm 73:1efda918f0ba 5490 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
bogdanm 73:1efda918f0ba 5491
bogdanm 73:1efda918f0ba 5492 /****************** Bit definition for SDIO_RESP1 register ******************/
bogdanm 73:1efda918f0ba 5493 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
bogdanm 73:1efda918f0ba 5494
bogdanm 73:1efda918f0ba 5495 /****************** Bit definition for SDIO_RESP2 register ******************/
bogdanm 73:1efda918f0ba 5496 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
bogdanm 73:1efda918f0ba 5497
bogdanm 73:1efda918f0ba 5498 /****************** Bit definition for SDIO_RESP3 register ******************/
bogdanm 73:1efda918f0ba 5499 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
bogdanm 73:1efda918f0ba 5500
bogdanm 73:1efda918f0ba 5501 /****************** Bit definition for SDIO_RESP4 register ******************/
bogdanm 73:1efda918f0ba 5502 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
bogdanm 73:1efda918f0ba 5503
bogdanm 73:1efda918f0ba 5504 /****************** Bit definition for SDIO_DTIMER register *****************/
bogdanm 73:1efda918f0ba 5505 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
bogdanm 73:1efda918f0ba 5506
bogdanm 73:1efda918f0ba 5507 /****************** Bit definition for SDIO_DLEN register *******************/
bogdanm 73:1efda918f0ba 5508 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
bogdanm 73:1efda918f0ba 5509
bogdanm 73:1efda918f0ba 5510 /****************** Bit definition for SDIO_DCTRL register ******************/
bogdanm 73:1efda918f0ba 5511 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */
bogdanm 73:1efda918f0ba 5512 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */
bogdanm 73:1efda918f0ba 5513 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */
bogdanm 73:1efda918f0ba 5514 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */
bogdanm 73:1efda918f0ba 5515
bogdanm 73:1efda918f0ba 5516 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
bogdanm 73:1efda918f0ba 5517 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5518 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5519 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5520 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5521
bogdanm 73:1efda918f0ba 5522 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */
bogdanm 73:1efda918f0ba 5523 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */
bogdanm 73:1efda918f0ba 5524 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */
bogdanm 73:1efda918f0ba 5525 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */
bogdanm 73:1efda918f0ba 5526
bogdanm 73:1efda918f0ba 5527 /****************** Bit definition for SDIO_DCOUNT register *****************/
bogdanm 73:1efda918f0ba 5528 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
bogdanm 73:1efda918f0ba 5529
bogdanm 73:1efda918f0ba 5530 /****************** Bit definition for SDIO_STA register ********************/
bogdanm 73:1efda918f0ba 5531 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
bogdanm 73:1efda918f0ba 5532 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
bogdanm 73:1efda918f0ba 5533 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
bogdanm 73:1efda918f0ba 5534 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
bogdanm 73:1efda918f0ba 5535 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
bogdanm 73:1efda918f0ba 5536 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
bogdanm 73:1efda918f0ba 5537 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
bogdanm 73:1efda918f0ba 5538 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
bogdanm 73:1efda918f0ba 5539 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
bogdanm 73:1efda918f0ba 5540 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
bogdanm 73:1efda918f0ba 5541 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
bogdanm 73:1efda918f0ba 5542 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
bogdanm 73:1efda918f0ba 5543 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
bogdanm 73:1efda918f0ba 5544 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
bogdanm 73:1efda918f0ba 5545 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
bogdanm 73:1efda918f0ba 5546 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
bogdanm 73:1efda918f0ba 5547 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
bogdanm 73:1efda918f0ba 5548 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
bogdanm 73:1efda918f0ba 5549 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
bogdanm 73:1efda918f0ba 5550 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
bogdanm 73:1efda918f0ba 5551 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
bogdanm 73:1efda918f0ba 5552 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
bogdanm 73:1efda918f0ba 5553 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
bogdanm 73:1efda918f0ba 5554 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
bogdanm 73:1efda918f0ba 5555
bogdanm 73:1efda918f0ba 5556 /******************* Bit definition for SDIO_ICR register *******************/
bogdanm 73:1efda918f0ba 5557 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
bogdanm 73:1efda918f0ba 5558 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
bogdanm 73:1efda918f0ba 5559 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
bogdanm 73:1efda918f0ba 5560 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
bogdanm 73:1efda918f0ba 5561 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
bogdanm 73:1efda918f0ba 5562 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
bogdanm 73:1efda918f0ba 5563 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
bogdanm 73:1efda918f0ba 5564 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
bogdanm 73:1efda918f0ba 5565 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
bogdanm 73:1efda918f0ba 5566 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
bogdanm 73:1efda918f0ba 5567 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
bogdanm 73:1efda918f0ba 5568 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
bogdanm 73:1efda918f0ba 5569 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
bogdanm 73:1efda918f0ba 5570
bogdanm 73:1efda918f0ba 5571 /****************** Bit definition for SDIO_MASK register *******************/
bogdanm 73:1efda918f0ba 5572 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
bogdanm 73:1efda918f0ba 5573 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
bogdanm 73:1efda918f0ba 5574 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
bogdanm 73:1efda918f0ba 5575 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
bogdanm 73:1efda918f0ba 5576 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
bogdanm 73:1efda918f0ba 5577 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
bogdanm 73:1efda918f0ba 5578 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
bogdanm 73:1efda918f0ba 5579 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
bogdanm 73:1efda918f0ba 5580 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
bogdanm 73:1efda918f0ba 5581 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
bogdanm 73:1efda918f0ba 5582 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
bogdanm 73:1efda918f0ba 5583 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
bogdanm 73:1efda918f0ba 5584 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
bogdanm 73:1efda918f0ba 5585 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
bogdanm 73:1efda918f0ba 5586 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
bogdanm 73:1efda918f0ba 5587 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
bogdanm 73:1efda918f0ba 5588 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
bogdanm 73:1efda918f0ba 5589 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
bogdanm 73:1efda918f0ba 5590 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
bogdanm 73:1efda918f0ba 5591 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
bogdanm 73:1efda918f0ba 5592 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
bogdanm 73:1efda918f0ba 5593 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
bogdanm 73:1efda918f0ba 5594 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
bogdanm 73:1efda918f0ba 5595 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
bogdanm 73:1efda918f0ba 5596
bogdanm 73:1efda918f0ba 5597 /***************** Bit definition for SDIO_FIFOCNT register *****************/
bogdanm 73:1efda918f0ba 5598 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
bogdanm 73:1efda918f0ba 5599
bogdanm 73:1efda918f0ba 5600 /****************** Bit definition for SDIO_FIFO register *******************/
bogdanm 73:1efda918f0ba 5601 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
bogdanm 73:1efda918f0ba 5602
bogdanm 73:1efda918f0ba 5603 /******************************************************************************/
bogdanm 73:1efda918f0ba 5604 /* */
bogdanm 73:1efda918f0ba 5605 /* USB Device FS */
bogdanm 73:1efda918f0ba 5606 /* */
bogdanm 73:1efda918f0ba 5607 /******************************************************************************/
bogdanm 73:1efda918f0ba 5608
bogdanm 73:1efda918f0ba 5609 /*!< Endpoint-specific registers */
bogdanm 73:1efda918f0ba 5610 /******************* Bit definition for USB_EP0R register *******************/
bogdanm 73:1efda918f0ba 5611 #define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
bogdanm 73:1efda918f0ba 5612
bogdanm 73:1efda918f0ba 5613 #define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
bogdanm 73:1efda918f0ba 5614 #define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5615 #define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5616
bogdanm 73:1efda918f0ba 5617 #define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
bogdanm 73:1efda918f0ba 5618 #define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
bogdanm 73:1efda918f0ba 5619 #define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
bogdanm 73:1efda918f0ba 5620
bogdanm 73:1efda918f0ba 5621 #define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
bogdanm 73:1efda918f0ba 5622 #define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5623 #define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5624
bogdanm 73:1efda918f0ba 5625 #define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
bogdanm 73:1efda918f0ba 5626
bogdanm 73:1efda918f0ba 5627 #define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
bogdanm 73:1efda918f0ba 5628 #define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5629 #define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5630
bogdanm 73:1efda918f0ba 5631 #define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
bogdanm 73:1efda918f0ba 5632 #define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
bogdanm 73:1efda918f0ba 5633
bogdanm 73:1efda918f0ba 5634 /******************* Bit definition for USB_EP1R register *******************/
bogdanm 73:1efda918f0ba 5635 #define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
bogdanm 73:1efda918f0ba 5636
bogdanm 73:1efda918f0ba 5637 #define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
bogdanm 73:1efda918f0ba 5638 #define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5639 #define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5640
bogdanm 73:1efda918f0ba 5641 #define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
bogdanm 73:1efda918f0ba 5642 #define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
bogdanm 73:1efda918f0ba 5643 #define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
bogdanm 73:1efda918f0ba 5644
bogdanm 73:1efda918f0ba 5645 #define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
bogdanm 73:1efda918f0ba 5646 #define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5647 #define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5648
bogdanm 73:1efda918f0ba 5649 #define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
bogdanm 73:1efda918f0ba 5650
bogdanm 73:1efda918f0ba 5651 #define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
bogdanm 73:1efda918f0ba 5652 #define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5653 #define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5654
bogdanm 73:1efda918f0ba 5655 #define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
bogdanm 73:1efda918f0ba 5656 #define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
bogdanm 73:1efda918f0ba 5657
bogdanm 73:1efda918f0ba 5658 /******************* Bit definition for USB_EP2R register *******************/
bogdanm 73:1efda918f0ba 5659 #define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
bogdanm 73:1efda918f0ba 5660
bogdanm 73:1efda918f0ba 5661 #define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
bogdanm 73:1efda918f0ba 5662 #define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5663 #define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5664
bogdanm 73:1efda918f0ba 5665 #define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
bogdanm 73:1efda918f0ba 5666 #define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
bogdanm 73:1efda918f0ba 5667 #define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
bogdanm 73:1efda918f0ba 5668
bogdanm 73:1efda918f0ba 5669 #define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
bogdanm 73:1efda918f0ba 5670 #define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5671 #define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5672
bogdanm 73:1efda918f0ba 5673 #define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
bogdanm 73:1efda918f0ba 5674
bogdanm 73:1efda918f0ba 5675 #define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
bogdanm 73:1efda918f0ba 5676 #define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5677 #define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5678
bogdanm 73:1efda918f0ba 5679 #define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
bogdanm 73:1efda918f0ba 5680 #define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
bogdanm 73:1efda918f0ba 5681
bogdanm 73:1efda918f0ba 5682 /******************* Bit definition for USB_EP3R register *******************/
bogdanm 73:1efda918f0ba 5683 #define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
bogdanm 73:1efda918f0ba 5684
bogdanm 73:1efda918f0ba 5685 #define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
bogdanm 73:1efda918f0ba 5686 #define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5687 #define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5688
bogdanm 73:1efda918f0ba 5689 #define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
bogdanm 73:1efda918f0ba 5690 #define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
bogdanm 73:1efda918f0ba 5691 #define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
bogdanm 73:1efda918f0ba 5692
bogdanm 73:1efda918f0ba 5693 #define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
bogdanm 73:1efda918f0ba 5694 #define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5695 #define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5696
bogdanm 73:1efda918f0ba 5697 #define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
bogdanm 73:1efda918f0ba 5698
bogdanm 73:1efda918f0ba 5699 #define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
bogdanm 73:1efda918f0ba 5700 #define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5701 #define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5702
bogdanm 73:1efda918f0ba 5703 #define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
bogdanm 73:1efda918f0ba 5704 #define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
bogdanm 73:1efda918f0ba 5705
bogdanm 73:1efda918f0ba 5706 /******************* Bit definition for USB_EP4R register *******************/
bogdanm 73:1efda918f0ba 5707 #define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
bogdanm 73:1efda918f0ba 5708
bogdanm 73:1efda918f0ba 5709 #define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
bogdanm 73:1efda918f0ba 5710 #define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5711 #define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5712
bogdanm 73:1efda918f0ba 5713 #define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
bogdanm 73:1efda918f0ba 5714 #define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
bogdanm 73:1efda918f0ba 5715 #define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
bogdanm 73:1efda918f0ba 5716
bogdanm 73:1efda918f0ba 5717 #define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
bogdanm 73:1efda918f0ba 5718 #define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5719 #define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5720
bogdanm 73:1efda918f0ba 5721 #define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
bogdanm 73:1efda918f0ba 5722
bogdanm 73:1efda918f0ba 5723 #define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
bogdanm 73:1efda918f0ba 5724 #define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5725 #define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5726
bogdanm 73:1efda918f0ba 5727 #define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
bogdanm 73:1efda918f0ba 5728 #define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
bogdanm 73:1efda918f0ba 5729
bogdanm 73:1efda918f0ba 5730 /******************* Bit definition for USB_EP5R register *******************/
bogdanm 73:1efda918f0ba 5731 #define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
bogdanm 73:1efda918f0ba 5732
bogdanm 73:1efda918f0ba 5733 #define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
bogdanm 73:1efda918f0ba 5734 #define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5735 #define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5736
bogdanm 73:1efda918f0ba 5737 #define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
bogdanm 73:1efda918f0ba 5738 #define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
bogdanm 73:1efda918f0ba 5739 #define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
bogdanm 73:1efda918f0ba 5740
bogdanm 73:1efda918f0ba 5741 #define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
bogdanm 73:1efda918f0ba 5742 #define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5743 #define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5744
bogdanm 73:1efda918f0ba 5745 #define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
bogdanm 73:1efda918f0ba 5746
bogdanm 73:1efda918f0ba 5747 #define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
bogdanm 73:1efda918f0ba 5748 #define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5749 #define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5750
bogdanm 73:1efda918f0ba 5751 #define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
bogdanm 73:1efda918f0ba 5752 #define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
bogdanm 73:1efda918f0ba 5753
bogdanm 73:1efda918f0ba 5754 /******************* Bit definition for USB_EP6R register *******************/
bogdanm 73:1efda918f0ba 5755 #define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
bogdanm 73:1efda918f0ba 5756
bogdanm 73:1efda918f0ba 5757 #define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
bogdanm 73:1efda918f0ba 5758 #define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5759 #define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5760
bogdanm 73:1efda918f0ba 5761 #define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
bogdanm 73:1efda918f0ba 5762 #define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
bogdanm 73:1efda918f0ba 5763 #define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
bogdanm 73:1efda918f0ba 5764
bogdanm 73:1efda918f0ba 5765 #define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
bogdanm 73:1efda918f0ba 5766 #define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5767 #define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5768
bogdanm 73:1efda918f0ba 5769 #define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
bogdanm 73:1efda918f0ba 5770
bogdanm 73:1efda918f0ba 5771 #define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
bogdanm 73:1efda918f0ba 5772 #define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5773 #define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5774
bogdanm 73:1efda918f0ba 5775 #define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
bogdanm 73:1efda918f0ba 5776 #define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
bogdanm 73:1efda918f0ba 5777
bogdanm 73:1efda918f0ba 5778 /******************* Bit definition for USB_EP7R register *******************/
bogdanm 73:1efda918f0ba 5779 #define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
bogdanm 73:1efda918f0ba 5780
bogdanm 73:1efda918f0ba 5781 #define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
bogdanm 73:1efda918f0ba 5782 #define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5783 #define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5784
bogdanm 73:1efda918f0ba 5785 #define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
bogdanm 73:1efda918f0ba 5786 #define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
bogdanm 73:1efda918f0ba 5787 #define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
bogdanm 73:1efda918f0ba 5788
bogdanm 73:1efda918f0ba 5789 #define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
bogdanm 73:1efda918f0ba 5790 #define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5791 #define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5792
bogdanm 73:1efda918f0ba 5793 #define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
bogdanm 73:1efda918f0ba 5794
bogdanm 73:1efda918f0ba 5795 #define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
bogdanm 73:1efda918f0ba 5796 #define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5797 #define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5798
bogdanm 73:1efda918f0ba 5799 #define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
bogdanm 73:1efda918f0ba 5800 #define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
bogdanm 73:1efda918f0ba 5801
bogdanm 73:1efda918f0ba 5802 /*!< Common registers */
bogdanm 73:1efda918f0ba 5803 /******************* Bit definition for USB_CNTR register *******************/
bogdanm 73:1efda918f0ba 5804 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */
bogdanm 73:1efda918f0ba 5805 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */
bogdanm 73:1efda918f0ba 5806 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
bogdanm 73:1efda918f0ba 5807 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */
bogdanm 73:1efda918f0ba 5808 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */
bogdanm 73:1efda918f0ba 5809 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
bogdanm 73:1efda918f0ba 5810 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
bogdanm 73:1efda918f0ba 5811 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
bogdanm 73:1efda918f0ba 5812 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
bogdanm 73:1efda918f0ba 5813 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
bogdanm 73:1efda918f0ba 5814 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */
bogdanm 73:1efda918f0ba 5815 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
bogdanm 73:1efda918f0ba 5816 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
bogdanm 73:1efda918f0ba 5817
bogdanm 73:1efda918f0ba 5818 /******************* Bit definition for USB_ISTR register *******************/
bogdanm 73:1efda918f0ba 5819 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
bogdanm 73:1efda918f0ba 5820 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */
bogdanm 73:1efda918f0ba 5821 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */
bogdanm 73:1efda918f0ba 5822 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */
bogdanm 73:1efda918f0ba 5823 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */
bogdanm 73:1efda918f0ba 5824 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */
bogdanm 73:1efda918f0ba 5825 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */
bogdanm 73:1efda918f0ba 5826 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */
bogdanm 73:1efda918f0ba 5827 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
bogdanm 73:1efda918f0ba 5828 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */
bogdanm 73:1efda918f0ba 5829
bogdanm 73:1efda918f0ba 5830 /******************* Bit definition for USB_FNR register ********************/
bogdanm 73:1efda918f0ba 5831 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
bogdanm 73:1efda918f0ba 5832 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
bogdanm 73:1efda918f0ba 5833 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */
bogdanm 73:1efda918f0ba 5834 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */
bogdanm 73:1efda918f0ba 5835 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */
bogdanm 73:1efda918f0ba 5836
bogdanm 73:1efda918f0ba 5837 /****************** Bit definition for USB_DADDR register *******************/
bogdanm 73:1efda918f0ba 5838 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
bogdanm 73:1efda918f0ba 5839 #define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5840 #define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5841 #define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5842 #define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5843 #define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5844 #define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 5845 #define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 5846
bogdanm 73:1efda918f0ba 5847 #define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */
bogdanm 73:1efda918f0ba 5848
bogdanm 73:1efda918f0ba 5849 /****************** Bit definition for USB_BTABLE register ******************/
bogdanm 73:1efda918f0ba 5850 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */
bogdanm 73:1efda918f0ba 5851
bogdanm 73:1efda918f0ba 5852 /*!< Buffer descriptor table */
bogdanm 73:1efda918f0ba 5853 /***************** Bit definition for USB_ADDR0_TX register *****************/
bogdanm 73:1efda918f0ba 5854 #define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
bogdanm 73:1efda918f0ba 5855
bogdanm 73:1efda918f0ba 5856 /***************** Bit definition for USB_ADDR1_TX register *****************/
bogdanm 73:1efda918f0ba 5857 #define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
bogdanm 73:1efda918f0ba 5858
bogdanm 73:1efda918f0ba 5859 /***************** Bit definition for USB_ADDR2_TX register *****************/
bogdanm 73:1efda918f0ba 5860 #define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
bogdanm 73:1efda918f0ba 5861
bogdanm 73:1efda918f0ba 5862 /***************** Bit definition for USB_ADDR3_TX register *****************/
bogdanm 73:1efda918f0ba 5863 #define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
bogdanm 73:1efda918f0ba 5864
bogdanm 73:1efda918f0ba 5865 /***************** Bit definition for USB_ADDR4_TX register *****************/
bogdanm 73:1efda918f0ba 5866 #define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
bogdanm 73:1efda918f0ba 5867
bogdanm 73:1efda918f0ba 5868 /***************** Bit definition for USB_ADDR5_TX register *****************/
bogdanm 73:1efda918f0ba 5869 #define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
bogdanm 73:1efda918f0ba 5870
bogdanm 73:1efda918f0ba 5871 /***************** Bit definition for USB_ADDR6_TX register *****************/
bogdanm 73:1efda918f0ba 5872 #define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
bogdanm 73:1efda918f0ba 5873
bogdanm 73:1efda918f0ba 5874 /***************** Bit definition for USB_ADDR7_TX register *****************/
bogdanm 73:1efda918f0ba 5875 #define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
bogdanm 73:1efda918f0ba 5876
bogdanm 73:1efda918f0ba 5877 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 5878
bogdanm 73:1efda918f0ba 5879 /***************** Bit definition for USB_COUNT0_TX register ****************/
bogdanm 73:1efda918f0ba 5880 #define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
bogdanm 73:1efda918f0ba 5881
bogdanm 73:1efda918f0ba 5882 /***************** Bit definition for USB_COUNT1_TX register ****************/
bogdanm 73:1efda918f0ba 5883 #define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
bogdanm 73:1efda918f0ba 5884
bogdanm 73:1efda918f0ba 5885 /***************** Bit definition for USB_COUNT2_TX register ****************/
bogdanm 73:1efda918f0ba 5886 #define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
bogdanm 73:1efda918f0ba 5887
bogdanm 73:1efda918f0ba 5888 /***************** Bit definition for USB_COUNT3_TX register ****************/
bogdanm 73:1efda918f0ba 5889 #define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
bogdanm 73:1efda918f0ba 5890
bogdanm 73:1efda918f0ba 5891 /***************** Bit definition for USB_COUNT4_TX register ****************/
bogdanm 73:1efda918f0ba 5892 #define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
bogdanm 73:1efda918f0ba 5893
bogdanm 73:1efda918f0ba 5894 /***************** Bit definition for USB_COUNT5_TX register ****************/
bogdanm 73:1efda918f0ba 5895 #define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
bogdanm 73:1efda918f0ba 5896
bogdanm 73:1efda918f0ba 5897 /***************** Bit definition for USB_COUNT6_TX register ****************/
bogdanm 73:1efda918f0ba 5898 #define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
bogdanm 73:1efda918f0ba 5899
bogdanm 73:1efda918f0ba 5900 /***************** Bit definition for USB_COUNT7_TX register ****************/
bogdanm 73:1efda918f0ba 5901 #define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
bogdanm 73:1efda918f0ba 5902
bogdanm 73:1efda918f0ba 5903 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 5904
bogdanm 73:1efda918f0ba 5905 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
bogdanm 73:1efda918f0ba 5906 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
bogdanm 73:1efda918f0ba 5907
bogdanm 73:1efda918f0ba 5908 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
bogdanm 73:1efda918f0ba 5909 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
bogdanm 73:1efda918f0ba 5910
bogdanm 73:1efda918f0ba 5911 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
bogdanm 73:1efda918f0ba 5912 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
bogdanm 73:1efda918f0ba 5913
bogdanm 73:1efda918f0ba 5914 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
bogdanm 73:1efda918f0ba 5915 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
bogdanm 73:1efda918f0ba 5916
bogdanm 73:1efda918f0ba 5917 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
bogdanm 73:1efda918f0ba 5918 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
bogdanm 73:1efda918f0ba 5919
bogdanm 73:1efda918f0ba 5920 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
bogdanm 73:1efda918f0ba 5921 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
bogdanm 73:1efda918f0ba 5922
bogdanm 73:1efda918f0ba 5923 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
bogdanm 73:1efda918f0ba 5924 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
bogdanm 73:1efda918f0ba 5925
bogdanm 73:1efda918f0ba 5926 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
bogdanm 73:1efda918f0ba 5927 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
bogdanm 73:1efda918f0ba 5928
bogdanm 73:1efda918f0ba 5929 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
bogdanm 73:1efda918f0ba 5930 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
bogdanm 73:1efda918f0ba 5931
bogdanm 73:1efda918f0ba 5932 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
bogdanm 73:1efda918f0ba 5933 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
bogdanm 73:1efda918f0ba 5934
bogdanm 73:1efda918f0ba 5935 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
bogdanm 73:1efda918f0ba 5936 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
bogdanm 73:1efda918f0ba 5937
bogdanm 73:1efda918f0ba 5938 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
bogdanm 73:1efda918f0ba 5939 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
bogdanm 73:1efda918f0ba 5940
bogdanm 73:1efda918f0ba 5941 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
bogdanm 73:1efda918f0ba 5942 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
bogdanm 73:1efda918f0ba 5943
bogdanm 73:1efda918f0ba 5944 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
bogdanm 73:1efda918f0ba 5945 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
bogdanm 73:1efda918f0ba 5946
bogdanm 73:1efda918f0ba 5947 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
bogdanm 73:1efda918f0ba 5948 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
bogdanm 73:1efda918f0ba 5949
bogdanm 73:1efda918f0ba 5950 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
bogdanm 73:1efda918f0ba 5951 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
bogdanm 73:1efda918f0ba 5952
bogdanm 73:1efda918f0ba 5953 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 5954
bogdanm 73:1efda918f0ba 5955 /***************** Bit definition for USB_ADDR0_RX register *****************/
bogdanm 73:1efda918f0ba 5956 #define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
bogdanm 73:1efda918f0ba 5957
bogdanm 73:1efda918f0ba 5958 /***************** Bit definition for USB_ADDR1_RX register *****************/
bogdanm 73:1efda918f0ba 5959 #define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
bogdanm 73:1efda918f0ba 5960
bogdanm 73:1efda918f0ba 5961 /***************** Bit definition for USB_ADDR2_RX register *****************/
bogdanm 73:1efda918f0ba 5962 #define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
bogdanm 73:1efda918f0ba 5963
bogdanm 73:1efda918f0ba 5964 /***************** Bit definition for USB_ADDR3_RX register *****************/
bogdanm 73:1efda918f0ba 5965 #define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
bogdanm 73:1efda918f0ba 5966
bogdanm 73:1efda918f0ba 5967 /***************** Bit definition for USB_ADDR4_RX register *****************/
bogdanm 73:1efda918f0ba 5968 #define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
bogdanm 73:1efda918f0ba 5969
bogdanm 73:1efda918f0ba 5970 /***************** Bit definition for USB_ADDR5_RX register *****************/
bogdanm 73:1efda918f0ba 5971 #define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
bogdanm 73:1efda918f0ba 5972
bogdanm 73:1efda918f0ba 5973 /***************** Bit definition for USB_ADDR6_RX register *****************/
bogdanm 73:1efda918f0ba 5974 #define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
bogdanm 73:1efda918f0ba 5975
bogdanm 73:1efda918f0ba 5976 /***************** Bit definition for USB_ADDR7_RX register *****************/
bogdanm 73:1efda918f0ba 5977 #define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
bogdanm 73:1efda918f0ba 5978
bogdanm 73:1efda918f0ba 5979 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 5980
bogdanm 73:1efda918f0ba 5981 /***************** Bit definition for USB_COUNT0_RX register ****************/
bogdanm 73:1efda918f0ba 5982 #define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
bogdanm 73:1efda918f0ba 5983
bogdanm 73:1efda918f0ba 5984 #define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
bogdanm 73:1efda918f0ba 5985 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5986 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5987 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 5988 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 5989 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 5990
bogdanm 73:1efda918f0ba 5991 #define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
bogdanm 73:1efda918f0ba 5992
bogdanm 73:1efda918f0ba 5993 /***************** Bit definition for USB_COUNT1_RX register ****************/
bogdanm 73:1efda918f0ba 5994 #define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
bogdanm 73:1efda918f0ba 5995
bogdanm 73:1efda918f0ba 5996 #define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
bogdanm 73:1efda918f0ba 5997 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 5998 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 5999 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6000 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6001 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6002
bogdanm 73:1efda918f0ba 6003 #define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
bogdanm 73:1efda918f0ba 6004
bogdanm 73:1efda918f0ba 6005 /***************** Bit definition for USB_COUNT2_RX register ****************/
bogdanm 73:1efda918f0ba 6006 #define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
bogdanm 73:1efda918f0ba 6007
bogdanm 73:1efda918f0ba 6008 #define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
bogdanm 73:1efda918f0ba 6009 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6010 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6011 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6012 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6013 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6014
bogdanm 73:1efda918f0ba 6015 #define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
bogdanm 73:1efda918f0ba 6016
bogdanm 73:1efda918f0ba 6017 /***************** Bit definition for USB_COUNT3_RX register ****************/
bogdanm 73:1efda918f0ba 6018 #define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
bogdanm 73:1efda918f0ba 6019
bogdanm 73:1efda918f0ba 6020 #define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
bogdanm 73:1efda918f0ba 6021 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6022 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6023 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6024 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6025 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6026
bogdanm 73:1efda918f0ba 6027 #define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
bogdanm 73:1efda918f0ba 6028
bogdanm 73:1efda918f0ba 6029 /***************** Bit definition for USB_COUNT4_RX register ****************/
bogdanm 73:1efda918f0ba 6030 #define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
bogdanm 73:1efda918f0ba 6031
bogdanm 73:1efda918f0ba 6032 #define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
bogdanm 73:1efda918f0ba 6033 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6034 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6035 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6036 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6037 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6038
bogdanm 73:1efda918f0ba 6039 #define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
bogdanm 73:1efda918f0ba 6040
bogdanm 73:1efda918f0ba 6041 /***************** Bit definition for USB_COUNT5_RX register ****************/
bogdanm 73:1efda918f0ba 6042 #define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
bogdanm 73:1efda918f0ba 6043
bogdanm 73:1efda918f0ba 6044 #define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
bogdanm 73:1efda918f0ba 6045 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6046 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6047 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6048 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6049 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6050
bogdanm 73:1efda918f0ba 6051 #define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
bogdanm 73:1efda918f0ba 6052
bogdanm 73:1efda918f0ba 6053 /***************** Bit definition for USB_COUNT6_RX register ****************/
bogdanm 73:1efda918f0ba 6054 #define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
bogdanm 73:1efda918f0ba 6055
bogdanm 73:1efda918f0ba 6056 #define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
bogdanm 73:1efda918f0ba 6057 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6058 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6059 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6060 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6061 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6062
bogdanm 73:1efda918f0ba 6063 #define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
bogdanm 73:1efda918f0ba 6064
bogdanm 73:1efda918f0ba 6065 /***************** Bit definition for USB_COUNT7_RX register ****************/
bogdanm 73:1efda918f0ba 6066 #define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
bogdanm 73:1efda918f0ba 6067
bogdanm 73:1efda918f0ba 6068 #define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
bogdanm 73:1efda918f0ba 6069 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6070 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6071 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6072 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6073 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6074
bogdanm 73:1efda918f0ba 6075 #define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
bogdanm 73:1efda918f0ba 6076
bogdanm 73:1efda918f0ba 6077 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 6078
bogdanm 73:1efda918f0ba 6079 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
bogdanm 73:1efda918f0ba 6080 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
bogdanm 73:1efda918f0ba 6081
bogdanm 73:1efda918f0ba 6082 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
bogdanm 73:1efda918f0ba 6083 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6084 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6085 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6086 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6087 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6088
bogdanm 73:1efda918f0ba 6089 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
bogdanm 73:1efda918f0ba 6090
bogdanm 73:1efda918f0ba 6091 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
bogdanm 73:1efda918f0ba 6092 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
bogdanm 73:1efda918f0ba 6093
bogdanm 73:1efda918f0ba 6094 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
bogdanm 73:1efda918f0ba 6095 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6096 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6097 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6098 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6099 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6100
bogdanm 73:1efda918f0ba 6101 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
bogdanm 73:1efda918f0ba 6102
bogdanm 73:1efda918f0ba 6103 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
bogdanm 73:1efda918f0ba 6104 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
bogdanm 73:1efda918f0ba 6105
bogdanm 73:1efda918f0ba 6106 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
bogdanm 73:1efda918f0ba 6107 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6108 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6109 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6110 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6111 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6112
bogdanm 73:1efda918f0ba 6113 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
bogdanm 73:1efda918f0ba 6114
bogdanm 73:1efda918f0ba 6115 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
bogdanm 73:1efda918f0ba 6116 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
bogdanm 73:1efda918f0ba 6117
bogdanm 73:1efda918f0ba 6118 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
bogdanm 73:1efda918f0ba 6119 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6120 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6121 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6122 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6123 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6124
bogdanm 73:1efda918f0ba 6125 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
bogdanm 73:1efda918f0ba 6126
bogdanm 73:1efda918f0ba 6127 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
bogdanm 73:1efda918f0ba 6128 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
bogdanm 73:1efda918f0ba 6129
bogdanm 73:1efda918f0ba 6130 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
bogdanm 73:1efda918f0ba 6131 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6132 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6133 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6134 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6135 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6136
bogdanm 73:1efda918f0ba 6137 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
bogdanm 73:1efda918f0ba 6138
bogdanm 73:1efda918f0ba 6139 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
bogdanm 73:1efda918f0ba 6140 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
bogdanm 73:1efda918f0ba 6141
bogdanm 73:1efda918f0ba 6142 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
bogdanm 73:1efda918f0ba 6143 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6144 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6145 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6146 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6147 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6148
bogdanm 73:1efda918f0ba 6149 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
bogdanm 73:1efda918f0ba 6150
bogdanm 73:1efda918f0ba 6151 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
bogdanm 73:1efda918f0ba 6152 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
bogdanm 73:1efda918f0ba 6153
bogdanm 73:1efda918f0ba 6154 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
bogdanm 73:1efda918f0ba 6155 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6156 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6157 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6158 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6159 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6160
bogdanm 73:1efda918f0ba 6161 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
bogdanm 73:1efda918f0ba 6162
bogdanm 73:1efda918f0ba 6163 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
bogdanm 73:1efda918f0ba 6164 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
bogdanm 73:1efda918f0ba 6165
bogdanm 73:1efda918f0ba 6166 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
bogdanm 73:1efda918f0ba 6167 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6168 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6169 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6170 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6171 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6172
bogdanm 73:1efda918f0ba 6173 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
bogdanm 73:1efda918f0ba 6174
bogdanm 73:1efda918f0ba 6175 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
bogdanm 73:1efda918f0ba 6176 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
bogdanm 73:1efda918f0ba 6177
bogdanm 73:1efda918f0ba 6178 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
bogdanm 73:1efda918f0ba 6179 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6180 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6181 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6182 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6183 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6184
bogdanm 73:1efda918f0ba 6185 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
bogdanm 73:1efda918f0ba 6186
bogdanm 73:1efda918f0ba 6187 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
bogdanm 73:1efda918f0ba 6188 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
bogdanm 73:1efda918f0ba 6189
bogdanm 73:1efda918f0ba 6190 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
bogdanm 73:1efda918f0ba 6191 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6192 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6193 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6194 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6195 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6196
bogdanm 73:1efda918f0ba 6197 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
bogdanm 73:1efda918f0ba 6198
bogdanm 73:1efda918f0ba 6199 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
bogdanm 73:1efda918f0ba 6200 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
bogdanm 73:1efda918f0ba 6201
bogdanm 73:1efda918f0ba 6202 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
bogdanm 73:1efda918f0ba 6203 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6204 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6205 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6206 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6207 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6208
bogdanm 73:1efda918f0ba 6209 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
bogdanm 73:1efda918f0ba 6210
bogdanm 73:1efda918f0ba 6211 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
bogdanm 73:1efda918f0ba 6212 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
bogdanm 73:1efda918f0ba 6213
bogdanm 73:1efda918f0ba 6214 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
bogdanm 73:1efda918f0ba 6215 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6216 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6217 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6218 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6219 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6220
bogdanm 73:1efda918f0ba 6221 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
bogdanm 73:1efda918f0ba 6222
bogdanm 73:1efda918f0ba 6223 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
bogdanm 73:1efda918f0ba 6224 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
bogdanm 73:1efda918f0ba 6225
bogdanm 73:1efda918f0ba 6226 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
bogdanm 73:1efda918f0ba 6227 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6228 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6229 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6230 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6231 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6232
bogdanm 73:1efda918f0ba 6233 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
bogdanm 73:1efda918f0ba 6234
bogdanm 73:1efda918f0ba 6235 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
bogdanm 73:1efda918f0ba 6236 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
bogdanm 73:1efda918f0ba 6237
bogdanm 73:1efda918f0ba 6238 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
bogdanm 73:1efda918f0ba 6239 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6240 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6241 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6242 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6243 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6244
bogdanm 73:1efda918f0ba 6245 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
bogdanm 73:1efda918f0ba 6246
bogdanm 73:1efda918f0ba 6247 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
bogdanm 73:1efda918f0ba 6248 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
bogdanm 73:1efda918f0ba 6249
bogdanm 73:1efda918f0ba 6250 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
bogdanm 73:1efda918f0ba 6251 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6252 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6253 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6254 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6255 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6256
bogdanm 73:1efda918f0ba 6257 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
bogdanm 73:1efda918f0ba 6258
bogdanm 73:1efda918f0ba 6259 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
bogdanm 73:1efda918f0ba 6260 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
bogdanm 73:1efda918f0ba 6261
bogdanm 73:1efda918f0ba 6262 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
bogdanm 73:1efda918f0ba 6263 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6264 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6265 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6266 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 6267 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 6268
bogdanm 73:1efda918f0ba 6269 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
bogdanm 73:1efda918f0ba 6270
bogdanm 73:1efda918f0ba 6271 /******************************************************************************/
bogdanm 73:1efda918f0ba 6272 /* */
bogdanm 73:1efda918f0ba 6273 /* Controller Area Network */
bogdanm 73:1efda918f0ba 6274 /* */
bogdanm 73:1efda918f0ba 6275 /******************************************************************************/
bogdanm 73:1efda918f0ba 6276
bogdanm 73:1efda918f0ba 6277 /*!< CAN control and status registers */
bogdanm 73:1efda918f0ba 6278 /******************* Bit definition for CAN_MCR register ********************/
bogdanm 73:1efda918f0ba 6279 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */
bogdanm 73:1efda918f0ba 6280 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */
bogdanm 73:1efda918f0ba 6281 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */
bogdanm 73:1efda918f0ba 6282 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */
bogdanm 73:1efda918f0ba 6283 #define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */
bogdanm 73:1efda918f0ba 6284 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
bogdanm 73:1efda918f0ba 6285 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
bogdanm 73:1efda918f0ba 6286 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
bogdanm 73:1efda918f0ba 6287 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */
bogdanm 73:1efda918f0ba 6288
bogdanm 73:1efda918f0ba 6289 /******************* Bit definition for CAN_MSR register ********************/
bogdanm 73:1efda918f0ba 6290 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
bogdanm 73:1efda918f0ba 6291 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */
bogdanm 73:1efda918f0ba 6292 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */
bogdanm 73:1efda918f0ba 6293 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */
bogdanm 73:1efda918f0ba 6294 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
bogdanm 73:1efda918f0ba 6295 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */
bogdanm 73:1efda918f0ba 6296 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */
bogdanm 73:1efda918f0ba 6297 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */
bogdanm 73:1efda918f0ba 6298 #define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */
bogdanm 73:1efda918f0ba 6299
bogdanm 73:1efda918f0ba 6300 /******************* Bit definition for CAN_TSR register ********************/
bogdanm 73:1efda918f0ba 6301 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
bogdanm 73:1efda918f0ba 6302 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
bogdanm 73:1efda918f0ba 6303 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
bogdanm 73:1efda918f0ba 6304 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
bogdanm 73:1efda918f0ba 6305 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
bogdanm 73:1efda918f0ba 6306 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
bogdanm 73:1efda918f0ba 6307 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
bogdanm 73:1efda918f0ba 6308 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
bogdanm 73:1efda918f0ba 6309 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
bogdanm 73:1efda918f0ba 6310 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
bogdanm 73:1efda918f0ba 6311 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
bogdanm 73:1efda918f0ba 6312 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
bogdanm 73:1efda918f0ba 6313 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
bogdanm 73:1efda918f0ba 6314 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
bogdanm 73:1efda918f0ba 6315 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
bogdanm 73:1efda918f0ba 6316 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
bogdanm 73:1efda918f0ba 6317
bogdanm 73:1efda918f0ba 6318 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
bogdanm 73:1efda918f0ba 6319 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
bogdanm 73:1efda918f0ba 6320 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
bogdanm 73:1efda918f0ba 6321 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
bogdanm 73:1efda918f0ba 6322
bogdanm 73:1efda918f0ba 6323 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
bogdanm 73:1efda918f0ba 6324 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
bogdanm 73:1efda918f0ba 6325 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
bogdanm 73:1efda918f0ba 6326 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
bogdanm 73:1efda918f0ba 6327
bogdanm 73:1efda918f0ba 6328 /******************* Bit definition for CAN_RF0R register *******************/
bogdanm 73:1efda918f0ba 6329 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */
bogdanm 73:1efda918f0ba 6330 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */
bogdanm 73:1efda918f0ba 6331 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */
bogdanm 73:1efda918f0ba 6332 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */
bogdanm 73:1efda918f0ba 6333
bogdanm 73:1efda918f0ba 6334 /******************* Bit definition for CAN_RF1R register *******************/
bogdanm 73:1efda918f0ba 6335 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */
bogdanm 73:1efda918f0ba 6336 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */
bogdanm 73:1efda918f0ba 6337 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */
bogdanm 73:1efda918f0ba 6338 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */
bogdanm 73:1efda918f0ba 6339
bogdanm 73:1efda918f0ba 6340 /******************** Bit definition for CAN_IER register *******************/
bogdanm 73:1efda918f0ba 6341 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
bogdanm 73:1efda918f0ba 6342 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */
bogdanm 73:1efda918f0ba 6343 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */
bogdanm 73:1efda918f0ba 6344 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */
bogdanm 73:1efda918f0ba 6345 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */
bogdanm 73:1efda918f0ba 6346 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */
bogdanm 73:1efda918f0ba 6347 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */
bogdanm 73:1efda918f0ba 6348 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
bogdanm 73:1efda918f0ba 6349 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
bogdanm 73:1efda918f0ba 6350 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
bogdanm 73:1efda918f0ba 6351 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
bogdanm 73:1efda918f0ba 6352 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
bogdanm 73:1efda918f0ba 6353 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
bogdanm 73:1efda918f0ba 6354 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
bogdanm 73:1efda918f0ba 6355
bogdanm 73:1efda918f0ba 6356 /******************** Bit definition for CAN_ESR register *******************/
bogdanm 73:1efda918f0ba 6357 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */
bogdanm 73:1efda918f0ba 6358 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */
bogdanm 73:1efda918f0ba 6359 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
bogdanm 73:1efda918f0ba 6360
bogdanm 73:1efda918f0ba 6361 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
bogdanm 73:1efda918f0ba 6362 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 6363 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 6364 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 6365
bogdanm 73:1efda918f0ba 6366 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
bogdanm 73:1efda918f0ba 6367 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
bogdanm 73:1efda918f0ba 6368
bogdanm 73:1efda918f0ba 6369 /******************* Bit definition for CAN_BTR register ********************/
bogdanm 73:1efda918f0ba 6370 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
bogdanm 73:1efda918f0ba 6371 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
bogdanm 73:1efda918f0ba 6372 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
bogdanm 73:1efda918f0ba 6373 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
bogdanm 73:1efda918f0ba 6374 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
bogdanm 73:1efda918f0ba 6375 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */
bogdanm 73:1efda918f0ba 6376
bogdanm 73:1efda918f0ba 6377 /*!< Mailbox registers */
bogdanm 73:1efda918f0ba 6378 /****************** Bit definition for CAN_TI0R register ********************/
bogdanm 73:1efda918f0ba 6379 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
bogdanm 73:1efda918f0ba 6380 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
bogdanm 73:1efda918f0ba 6381 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
bogdanm 73:1efda918f0ba 6382 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
bogdanm 73:1efda918f0ba 6383 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
bogdanm 73:1efda918f0ba 6384
bogdanm 73:1efda918f0ba 6385 /****************** Bit definition for CAN_TDT0R register *******************/
bogdanm 73:1efda918f0ba 6386 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
bogdanm 73:1efda918f0ba 6387 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
bogdanm 73:1efda918f0ba 6388 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
bogdanm 73:1efda918f0ba 6389
bogdanm 73:1efda918f0ba 6390 /****************** Bit definition for CAN_TDL0R register *******************/
bogdanm 73:1efda918f0ba 6391 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
bogdanm 73:1efda918f0ba 6392 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
bogdanm 73:1efda918f0ba 6393 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
bogdanm 73:1efda918f0ba 6394 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
bogdanm 73:1efda918f0ba 6395
bogdanm 73:1efda918f0ba 6396 /****************** Bit definition for CAN_TDH0R register *******************/
bogdanm 73:1efda918f0ba 6397 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
bogdanm 73:1efda918f0ba 6398 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
bogdanm 73:1efda918f0ba 6399 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
bogdanm 73:1efda918f0ba 6400 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
bogdanm 73:1efda918f0ba 6401
bogdanm 73:1efda918f0ba 6402 /******************* Bit definition for CAN_TI1R register *******************/
bogdanm 73:1efda918f0ba 6403 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
bogdanm 73:1efda918f0ba 6404 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
bogdanm 73:1efda918f0ba 6405 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
bogdanm 73:1efda918f0ba 6406 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
bogdanm 73:1efda918f0ba 6407 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
bogdanm 73:1efda918f0ba 6408
bogdanm 73:1efda918f0ba 6409 /******************* Bit definition for CAN_TDT1R register ******************/
bogdanm 73:1efda918f0ba 6410 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
bogdanm 73:1efda918f0ba 6411 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
bogdanm 73:1efda918f0ba 6412 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
bogdanm 73:1efda918f0ba 6413
bogdanm 73:1efda918f0ba 6414 /******************* Bit definition for CAN_TDL1R register ******************/
bogdanm 73:1efda918f0ba 6415 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
bogdanm 73:1efda918f0ba 6416 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
bogdanm 73:1efda918f0ba 6417 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
bogdanm 73:1efda918f0ba 6418 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
bogdanm 73:1efda918f0ba 6419
bogdanm 73:1efda918f0ba 6420 /******************* Bit definition for CAN_TDH1R register ******************/
bogdanm 73:1efda918f0ba 6421 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
bogdanm 73:1efda918f0ba 6422 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
bogdanm 73:1efda918f0ba 6423 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
bogdanm 73:1efda918f0ba 6424 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
bogdanm 73:1efda918f0ba 6425
bogdanm 73:1efda918f0ba 6426 /******************* Bit definition for CAN_TI2R register *******************/
bogdanm 73:1efda918f0ba 6427 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
bogdanm 73:1efda918f0ba 6428 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
bogdanm 73:1efda918f0ba 6429 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
bogdanm 73:1efda918f0ba 6430 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
bogdanm 73:1efda918f0ba 6431 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
bogdanm 73:1efda918f0ba 6432
bogdanm 73:1efda918f0ba 6433 /******************* Bit definition for CAN_TDT2R register ******************/
bogdanm 73:1efda918f0ba 6434 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
bogdanm 73:1efda918f0ba 6435 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
bogdanm 73:1efda918f0ba 6436 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
bogdanm 73:1efda918f0ba 6437
bogdanm 73:1efda918f0ba 6438 /******************* Bit definition for CAN_TDL2R register ******************/
bogdanm 73:1efda918f0ba 6439 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
bogdanm 73:1efda918f0ba 6440 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
bogdanm 73:1efda918f0ba 6441 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
bogdanm 73:1efda918f0ba 6442 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
bogdanm 73:1efda918f0ba 6443
bogdanm 73:1efda918f0ba 6444 /******************* Bit definition for CAN_TDH2R register ******************/
bogdanm 73:1efda918f0ba 6445 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
bogdanm 73:1efda918f0ba 6446 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
bogdanm 73:1efda918f0ba 6447 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
bogdanm 73:1efda918f0ba 6448 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
bogdanm 73:1efda918f0ba 6449
bogdanm 73:1efda918f0ba 6450 /******************* Bit definition for CAN_RI0R register *******************/
bogdanm 73:1efda918f0ba 6451 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
bogdanm 73:1efda918f0ba 6452 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
bogdanm 73:1efda918f0ba 6453 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
bogdanm 73:1efda918f0ba 6454 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
bogdanm 73:1efda918f0ba 6455
bogdanm 73:1efda918f0ba 6456 /******************* Bit definition for CAN_RDT0R register ******************/
bogdanm 73:1efda918f0ba 6457 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
bogdanm 73:1efda918f0ba 6458 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
bogdanm 73:1efda918f0ba 6459 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
bogdanm 73:1efda918f0ba 6460
bogdanm 73:1efda918f0ba 6461 /******************* Bit definition for CAN_RDL0R register ******************/
bogdanm 73:1efda918f0ba 6462 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
bogdanm 73:1efda918f0ba 6463 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
bogdanm 73:1efda918f0ba 6464 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
bogdanm 73:1efda918f0ba 6465 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
bogdanm 73:1efda918f0ba 6466
bogdanm 73:1efda918f0ba 6467 /******************* Bit definition for CAN_RDH0R register ******************/
bogdanm 73:1efda918f0ba 6468 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
bogdanm 73:1efda918f0ba 6469 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
bogdanm 73:1efda918f0ba 6470 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
bogdanm 73:1efda918f0ba 6471 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
bogdanm 73:1efda918f0ba 6472
bogdanm 73:1efda918f0ba 6473 /******************* Bit definition for CAN_RI1R register *******************/
bogdanm 73:1efda918f0ba 6474 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
bogdanm 73:1efda918f0ba 6475 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
bogdanm 73:1efda918f0ba 6476 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
bogdanm 73:1efda918f0ba 6477 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
bogdanm 73:1efda918f0ba 6478
bogdanm 73:1efda918f0ba 6479 /******************* Bit definition for CAN_RDT1R register ******************/
bogdanm 73:1efda918f0ba 6480 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
bogdanm 73:1efda918f0ba 6481 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
bogdanm 73:1efda918f0ba 6482 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
bogdanm 73:1efda918f0ba 6483
bogdanm 73:1efda918f0ba 6484 /******************* Bit definition for CAN_RDL1R register ******************/
bogdanm 73:1efda918f0ba 6485 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
bogdanm 73:1efda918f0ba 6486 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
bogdanm 73:1efda918f0ba 6487 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
bogdanm 73:1efda918f0ba 6488 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
bogdanm 73:1efda918f0ba 6489
bogdanm 73:1efda918f0ba 6490 /******************* Bit definition for CAN_RDH1R register ******************/
bogdanm 73:1efda918f0ba 6491 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
bogdanm 73:1efda918f0ba 6492 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
bogdanm 73:1efda918f0ba 6493 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
bogdanm 73:1efda918f0ba 6494 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
bogdanm 73:1efda918f0ba 6495
bogdanm 73:1efda918f0ba 6496 /*!< CAN filter registers */
bogdanm 73:1efda918f0ba 6497 /******************* Bit definition for CAN_FMR register ********************/
bogdanm 73:1efda918f0ba 6498 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */
bogdanm 73:1efda918f0ba 6499
bogdanm 73:1efda918f0ba 6500 /******************* Bit definition for CAN_FM1R register *******************/
bogdanm 73:1efda918f0ba 6501 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */
bogdanm 73:1efda918f0ba 6502 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
bogdanm 73:1efda918f0ba 6503 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
bogdanm 73:1efda918f0ba 6504 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
bogdanm 73:1efda918f0ba 6505 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
bogdanm 73:1efda918f0ba 6506 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
bogdanm 73:1efda918f0ba 6507 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
bogdanm 73:1efda918f0ba 6508 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
bogdanm 73:1efda918f0ba 6509 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
bogdanm 73:1efda918f0ba 6510 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
bogdanm 73:1efda918f0ba 6511 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
bogdanm 73:1efda918f0ba 6512 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
bogdanm 73:1efda918f0ba 6513 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
bogdanm 73:1efda918f0ba 6514 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
bogdanm 73:1efda918f0ba 6515 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
bogdanm 73:1efda918f0ba 6516
bogdanm 73:1efda918f0ba 6517 /******************* Bit definition for CAN_FS1R register *******************/
bogdanm 73:1efda918f0ba 6518 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
bogdanm 73:1efda918f0ba 6519 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
bogdanm 73:1efda918f0ba 6520 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
bogdanm 73:1efda918f0ba 6521 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
bogdanm 73:1efda918f0ba 6522 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
bogdanm 73:1efda918f0ba 6523 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
bogdanm 73:1efda918f0ba 6524 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
bogdanm 73:1efda918f0ba 6525 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
bogdanm 73:1efda918f0ba 6526 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
bogdanm 73:1efda918f0ba 6527 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
bogdanm 73:1efda918f0ba 6528 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
bogdanm 73:1efda918f0ba 6529 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
bogdanm 73:1efda918f0ba 6530 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
bogdanm 73:1efda918f0ba 6531 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
bogdanm 73:1efda918f0ba 6532 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
bogdanm 73:1efda918f0ba 6533
bogdanm 73:1efda918f0ba 6534 /****************** Bit definition for CAN_FFA1R register *******************/
bogdanm 73:1efda918f0ba 6535 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */
bogdanm 73:1efda918f0ba 6536 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */
bogdanm 73:1efda918f0ba 6537 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */
bogdanm 73:1efda918f0ba 6538 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */
bogdanm 73:1efda918f0ba 6539 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */
bogdanm 73:1efda918f0ba 6540 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */
bogdanm 73:1efda918f0ba 6541 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */
bogdanm 73:1efda918f0ba 6542 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */
bogdanm 73:1efda918f0ba 6543 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */
bogdanm 73:1efda918f0ba 6544 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */
bogdanm 73:1efda918f0ba 6545 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */
bogdanm 73:1efda918f0ba 6546 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */
bogdanm 73:1efda918f0ba 6547 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */
bogdanm 73:1efda918f0ba 6548 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */
bogdanm 73:1efda918f0ba 6549 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */
bogdanm 73:1efda918f0ba 6550
bogdanm 73:1efda918f0ba 6551 /******************* Bit definition for CAN_FA1R register *******************/
bogdanm 73:1efda918f0ba 6552 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */
bogdanm 73:1efda918f0ba 6553 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */
bogdanm 73:1efda918f0ba 6554 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */
bogdanm 73:1efda918f0ba 6555 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */
bogdanm 73:1efda918f0ba 6556 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */
bogdanm 73:1efda918f0ba 6557 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */
bogdanm 73:1efda918f0ba 6558 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */
bogdanm 73:1efda918f0ba 6559 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */
bogdanm 73:1efda918f0ba 6560 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */
bogdanm 73:1efda918f0ba 6561 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */
bogdanm 73:1efda918f0ba 6562 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */
bogdanm 73:1efda918f0ba 6563 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */
bogdanm 73:1efda918f0ba 6564 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */
bogdanm 73:1efda918f0ba 6565 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */
bogdanm 73:1efda918f0ba 6566 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */
bogdanm 73:1efda918f0ba 6567
bogdanm 73:1efda918f0ba 6568 /******************* Bit definition for CAN_F0R1 register *******************/
bogdanm 73:1efda918f0ba 6569 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6570 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6571 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6572 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6573 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6574 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6575 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6576 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6577 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6578 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6579 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6580 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6581 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6582 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6583 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6584 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6585 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6586 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6587 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6588 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6589 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6590 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6591 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6592 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6593 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6594 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6595 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6596 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6597 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6598 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6599 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6600 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6601
bogdanm 73:1efda918f0ba 6602 /******************* Bit definition for CAN_F1R1 register *******************/
bogdanm 73:1efda918f0ba 6603 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6604 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6605 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6606 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6607 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6608 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6609 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6610 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6611 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6612 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6613 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6614 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6615 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6616 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6617 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6618 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6619 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6620 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6621 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6622 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6623 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6624 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6625 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6626 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6627 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6628 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6629 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6630 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6631 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6632 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6633 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6634 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6635
bogdanm 73:1efda918f0ba 6636 /******************* Bit definition for CAN_F2R1 register *******************/
bogdanm 73:1efda918f0ba 6637 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6638 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6639 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6640 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6641 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6642 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6643 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6644 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6645 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6646 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6647 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6648 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6649 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6650 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6651 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6652 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6653 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6654 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6655 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6656 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6657 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6658 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6659 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6660 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6661 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6662 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6663 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6664 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6665 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6666 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6667 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6668 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6669
bogdanm 73:1efda918f0ba 6670 /******************* Bit definition for CAN_F3R1 register *******************/
bogdanm 73:1efda918f0ba 6671 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6672 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6673 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6674 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6675 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6676 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6677 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6678 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6679 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6680 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6681 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6682 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6683 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6684 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6685 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6686 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6687 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6688 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6689 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6690 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6691 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6692 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6693 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6694 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6695 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6696 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6697 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6698 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6699 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6700 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6701 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6702 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6703
bogdanm 73:1efda918f0ba 6704 /******************* Bit definition for CAN_F4R1 register *******************/
bogdanm 73:1efda918f0ba 6705 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6706 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6707 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6708 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6709 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6710 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6711 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6712 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6713 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6714 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6715 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6716 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6717 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6718 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6719 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6720 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6721 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6722 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6723 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6724 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6725 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6726 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6727 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6728 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6729 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6730 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6731 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6732 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6733 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6734 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6735 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6736 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6737
bogdanm 73:1efda918f0ba 6738 /******************* Bit definition for CAN_F5R1 register *******************/
bogdanm 73:1efda918f0ba 6739 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6740 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6741 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6742 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6743 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6744 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6745 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6746 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6747 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6748 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6749 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6750 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6751 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6752 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6753 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6754 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6755 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6756 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6757 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6758 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6759 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6760 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6761 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6762 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6763 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6764 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6765 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6766 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6767 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6768 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6769 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6770 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6771
bogdanm 73:1efda918f0ba 6772 /******************* Bit definition for CAN_F6R1 register *******************/
bogdanm 73:1efda918f0ba 6773 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6774 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6775 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6776 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6777 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6778 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6779 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6780 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6781 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6782 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6783 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6784 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6785 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6786 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6787 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6788 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6789 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6790 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6791 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6792 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6793 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6794 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6795 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6796 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6797 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6798 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6799 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6800 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6801 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6802 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6803 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6804 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6805
bogdanm 73:1efda918f0ba 6806 /******************* Bit definition for CAN_F7R1 register *******************/
bogdanm 73:1efda918f0ba 6807 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6808 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6809 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6810 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6811 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6812 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6813 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6814 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6815 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6816 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6817 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6818 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6819 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6820 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6821 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6822 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6823 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6824 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6825 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6826 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6827 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6828 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6829 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6830 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6831 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6832 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6833 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6834 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6835 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6836 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6837 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6838 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6839
bogdanm 73:1efda918f0ba 6840 /******************* Bit definition for CAN_F8R1 register *******************/
bogdanm 73:1efda918f0ba 6841 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6842 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6843 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6844 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6845 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6846 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6847 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6848 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6849 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6850 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6851 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6852 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6853 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6854 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6855 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6856 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6857 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6858 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6859 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6860 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6861 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6862 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6863 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6864 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6865 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6866 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6867 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6868 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6869 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6870 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6871 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6872 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6873
bogdanm 73:1efda918f0ba 6874 /******************* Bit definition for CAN_F9R1 register *******************/
bogdanm 73:1efda918f0ba 6875 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6876 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6877 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6878 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6879 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6880 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6881 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6882 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6883 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6884 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6885 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6886 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6887 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6888 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6889 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6890 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6891 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6892 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6893 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6894 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6895 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6896 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6897 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6898 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6899 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6900 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6901 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6902 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6903 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6904 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6905 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6906 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6907
bogdanm 73:1efda918f0ba 6908 /******************* Bit definition for CAN_F10R1 register ******************/
bogdanm 73:1efda918f0ba 6909 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6910 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6911 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6912 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6913 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6914 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6915 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6916 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6917 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6918 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6919 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6920 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6921 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6922 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6923 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6924 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6925 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6926 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6927 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6928 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6929 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6930 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6931 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6932 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6933 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6934 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6935 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6936 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6937 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6938 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6939 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6940 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6941
bogdanm 73:1efda918f0ba 6942 /******************* Bit definition for CAN_F11R1 register ******************/
bogdanm 73:1efda918f0ba 6943 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6944 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6945 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6946 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6947 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6948 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6949 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6950 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6951 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6952 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6953 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6954 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6955 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6956 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6957 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6958 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6959 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6960 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6961 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6962 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6963 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6964 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6965 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 6966 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 6967 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 6968 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 6969 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 6970 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 6971 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 6972 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 6973 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 6974 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 6975
bogdanm 73:1efda918f0ba 6976 /******************* Bit definition for CAN_F12R1 register ******************/
bogdanm 73:1efda918f0ba 6977 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 6978 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 6979 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 6980 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 6981 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 6982 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 6983 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 6984 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 6985 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 6986 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 6987 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 6988 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 6989 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 6990 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 6991 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 6992 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 6993 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 6994 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 6995 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 6996 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 6997 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 6998 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 6999 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7000 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7001 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7002 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7003 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7004 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7005 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7006 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7007 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7008 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7009
bogdanm 73:1efda918f0ba 7010 /******************* Bit definition for CAN_F13R1 register ******************/
bogdanm 73:1efda918f0ba 7011 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7012 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7013 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7014 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7015 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7016 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7017 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7018 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7019 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7020 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7021 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7022 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7023 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7024 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7025 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7026 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7027 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7028 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7029 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7030 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7031 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7032 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7033 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7034 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7035 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7036 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7037 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7038 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7039 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7040 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7041 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7042 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7043
bogdanm 73:1efda918f0ba 7044 /******************* Bit definition for CAN_F0R2 register *******************/
bogdanm 73:1efda918f0ba 7045 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7046 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7047 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7048 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7049 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7050 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7051 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7052 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7053 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7054 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7055 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7056 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7057 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7058 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7059 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7060 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7061 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7062 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7063 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7064 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7065 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7066 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7067 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7068 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7069 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7070 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7071 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7072 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7073 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7074 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7075 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7076 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7077
bogdanm 73:1efda918f0ba 7078 /******************* Bit definition for CAN_F1R2 register *******************/
bogdanm 73:1efda918f0ba 7079 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7080 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7081 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7082 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7083 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7084 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7085 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7086 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7087 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7088 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7089 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7090 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7091 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7092 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7093 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7094 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7095 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7096 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7097 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7098 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7099 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7100 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7101 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7102 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7103 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7104 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7105 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7106 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7107 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7108 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7109 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7110 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7111
bogdanm 73:1efda918f0ba 7112 /******************* Bit definition for CAN_F2R2 register *******************/
bogdanm 73:1efda918f0ba 7113 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7114 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7115 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7116 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7117 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7118 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7119 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7120 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7121 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7122 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7123 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7124 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7125 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7126 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7127 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7128 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7129 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7130 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7131 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7132 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7133 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7134 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7135 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7136 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7137 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7138 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7139 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7140 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7141 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7142 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7143 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7144 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7145
bogdanm 73:1efda918f0ba 7146 /******************* Bit definition for CAN_F3R2 register *******************/
bogdanm 73:1efda918f0ba 7147 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7148 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7149 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7150 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7151 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7152 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7153 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7154 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7155 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7156 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7157 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7158 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7159 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7160 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7161 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7162 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7163 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7164 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7165 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7166 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7167 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7168 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7169 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7170 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7171 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7172 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7173 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7174 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7175 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7176 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7177 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7178 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7179
bogdanm 73:1efda918f0ba 7180 /******************* Bit definition for CAN_F4R2 register *******************/
bogdanm 73:1efda918f0ba 7181 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7182 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7183 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7184 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7185 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7186 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7187 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7188 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7189 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7190 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7191 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7192 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7193 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7194 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7195 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7196 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7197 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7198 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7199 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7200 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7201 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7202 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7203 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7204 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7205 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7206 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7207 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7208 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7209 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7210 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7211 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7212 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7213
bogdanm 73:1efda918f0ba 7214 /******************* Bit definition for CAN_F5R2 register *******************/
bogdanm 73:1efda918f0ba 7215 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7216 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7217 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7218 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7219 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7220 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7221 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7222 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7223 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7224 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7225 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7226 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7227 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7228 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7229 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7230 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7231 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7232 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7233 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7234 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7235 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7236 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7237 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7238 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7239 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7240 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7241 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7242 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7243 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7244 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7245 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7246 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7247
bogdanm 73:1efda918f0ba 7248 /******************* Bit definition for CAN_F6R2 register *******************/
bogdanm 73:1efda918f0ba 7249 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7250 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7251 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7252 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7253 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7254 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7255 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7256 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7257 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7258 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7259 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7260 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7261 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7262 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7263 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7264 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7265 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7266 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7267 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7268 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7269 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7270 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7271 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7272 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7273 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7274 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7275 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7276 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7277 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7278 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7279 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7280 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7281
bogdanm 73:1efda918f0ba 7282 /******************* Bit definition for CAN_F7R2 register *******************/
bogdanm 73:1efda918f0ba 7283 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7284 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7285 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7286 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7287 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7288 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7289 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7290 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7291 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7292 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7293 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7294 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7295 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7296 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7297 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7298 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7299 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7300 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7301 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7302 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7303 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7304 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7305 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7306 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7307 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7308 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7309 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7310 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7311 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7312 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7313 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7314 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7315
bogdanm 73:1efda918f0ba 7316 /******************* Bit definition for CAN_F8R2 register *******************/
bogdanm 73:1efda918f0ba 7317 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7318 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7319 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7320 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7321 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7322 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7323 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7324 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7325 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7326 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7327 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7328 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7329 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7330 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7331 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7332 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7333 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7334 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7335 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7336 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7337 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7338 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7339 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7340 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7341 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7342 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7343 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7344 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7345 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7346 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7347 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7348 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7349
bogdanm 73:1efda918f0ba 7350 /******************* Bit definition for CAN_F9R2 register *******************/
bogdanm 73:1efda918f0ba 7351 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7352 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7353 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7354 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7355 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7356 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7357 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7358 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7359 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7360 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7361 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7362 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7363 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7364 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7365 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7366 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7367 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7368 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7369 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7370 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7371 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7372 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7373 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7374 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7375 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7376 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7377 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7378 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7379 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7380 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7381 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7382 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7383
bogdanm 73:1efda918f0ba 7384 /******************* Bit definition for CAN_F10R2 register ******************/
bogdanm 73:1efda918f0ba 7385 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7386 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7387 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7388 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7389 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7390 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7391 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7392 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7393 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7394 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7395 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7396 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7397 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7398 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7399 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7400 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7401 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7402 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7403 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7404 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7405 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7406 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7407 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7408 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7409 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7410 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7411 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7412 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7413 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7414 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7415 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7416 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7417
bogdanm 73:1efda918f0ba 7418 /******************* Bit definition for CAN_F11R2 register ******************/
bogdanm 73:1efda918f0ba 7419 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7420 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7421 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7422 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7423 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7424 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7425 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7426 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7427 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7428 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7429 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7430 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7431 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7432 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7433 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7434 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7435 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7436 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7437 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7438 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7439 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7440 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7441 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7442 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7443 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7444 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7445 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7446 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7447 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7448 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7449 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7450 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7451
bogdanm 73:1efda918f0ba 7452 /******************* Bit definition for CAN_F12R2 register ******************/
bogdanm 73:1efda918f0ba 7453 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7454 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7455 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7456 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7457 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7458 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7459 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7460 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7461 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7462 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7463 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7464 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7465 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7466 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7467 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7468 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7469 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7470 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7471 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7472 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7473 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7474 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7475 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7476 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7477 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7478 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7479 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7480 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7481 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7482 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7483 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7484 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7485
bogdanm 73:1efda918f0ba 7486 /******************* Bit definition for CAN_F13R2 register ******************/
bogdanm 73:1efda918f0ba 7487 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
bogdanm 73:1efda918f0ba 7488 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
bogdanm 73:1efda918f0ba 7489 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
bogdanm 73:1efda918f0ba 7490 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
bogdanm 73:1efda918f0ba 7491 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
bogdanm 73:1efda918f0ba 7492 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
bogdanm 73:1efda918f0ba 7493 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
bogdanm 73:1efda918f0ba 7494 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
bogdanm 73:1efda918f0ba 7495 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
bogdanm 73:1efda918f0ba 7496 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
bogdanm 73:1efda918f0ba 7497 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
bogdanm 73:1efda918f0ba 7498 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
bogdanm 73:1efda918f0ba 7499 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
bogdanm 73:1efda918f0ba 7500 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
bogdanm 73:1efda918f0ba 7501 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
bogdanm 73:1efda918f0ba 7502 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
bogdanm 73:1efda918f0ba 7503 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
bogdanm 73:1efda918f0ba 7504 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
bogdanm 73:1efda918f0ba 7505 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
bogdanm 73:1efda918f0ba 7506 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
bogdanm 73:1efda918f0ba 7507 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
bogdanm 73:1efda918f0ba 7508 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
bogdanm 73:1efda918f0ba 7509 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
bogdanm 73:1efda918f0ba 7510 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
bogdanm 73:1efda918f0ba 7511 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
bogdanm 73:1efda918f0ba 7512 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
bogdanm 73:1efda918f0ba 7513 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
bogdanm 73:1efda918f0ba 7514 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
bogdanm 73:1efda918f0ba 7515 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
bogdanm 73:1efda918f0ba 7516 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
bogdanm 73:1efda918f0ba 7517 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
bogdanm 73:1efda918f0ba 7518 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
bogdanm 73:1efda918f0ba 7519
bogdanm 73:1efda918f0ba 7520 /******************************************************************************/
bogdanm 73:1efda918f0ba 7521 /* */
bogdanm 73:1efda918f0ba 7522 /* Serial Peripheral Interface */
bogdanm 73:1efda918f0ba 7523 /* */
bogdanm 73:1efda918f0ba 7524 /******************************************************************************/
bogdanm 73:1efda918f0ba 7525
bogdanm 73:1efda918f0ba 7526 /******************* Bit definition for SPI_CR1 register ********************/
bogdanm 73:1efda918f0ba 7527 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
bogdanm 73:1efda918f0ba 7528 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
bogdanm 73:1efda918f0ba 7529 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
bogdanm 73:1efda918f0ba 7530
bogdanm 73:1efda918f0ba 7531 #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
bogdanm 73:1efda918f0ba 7532 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7533 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7534 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 7535
bogdanm 73:1efda918f0ba 7536 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
bogdanm 73:1efda918f0ba 7537 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
bogdanm 73:1efda918f0ba 7538 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
bogdanm 73:1efda918f0ba 7539 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
bogdanm 73:1efda918f0ba 7540 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
bogdanm 73:1efda918f0ba 7541 #define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
bogdanm 73:1efda918f0ba 7542 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
bogdanm 73:1efda918f0ba 7543 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
bogdanm 73:1efda918f0ba 7544 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
bogdanm 73:1efda918f0ba 7545 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
bogdanm 73:1efda918f0ba 7546
bogdanm 73:1efda918f0ba 7547 /******************* Bit definition for SPI_CR2 register ********************/
bogdanm 73:1efda918f0ba 7548 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
bogdanm 73:1efda918f0ba 7549 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
bogdanm 73:1efda918f0ba 7550 #define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
bogdanm 73:1efda918f0ba 7551 #define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
bogdanm 73:1efda918f0ba 7552 #define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
bogdanm 73:1efda918f0ba 7553 #define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
bogdanm 73:1efda918f0ba 7554
bogdanm 73:1efda918f0ba 7555 /******************** Bit definition for SPI_SR register ********************/
bogdanm 73:1efda918f0ba 7556 #define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
bogdanm 73:1efda918f0ba 7557 #define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
bogdanm 73:1efda918f0ba 7558 #define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */
bogdanm 73:1efda918f0ba 7559 #define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */
bogdanm 73:1efda918f0ba 7560 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
bogdanm 73:1efda918f0ba 7561 #define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
bogdanm 73:1efda918f0ba 7562 #define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
bogdanm 73:1efda918f0ba 7563 #define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
bogdanm 73:1efda918f0ba 7564
bogdanm 73:1efda918f0ba 7565 /******************** Bit definition for SPI_DR register ********************/
bogdanm 73:1efda918f0ba 7566 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
bogdanm 73:1efda918f0ba 7567
bogdanm 73:1efda918f0ba 7568 /******************* Bit definition for SPI_CRCPR register ******************/
bogdanm 73:1efda918f0ba 7569 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
bogdanm 73:1efda918f0ba 7570
bogdanm 73:1efda918f0ba 7571 /****************** Bit definition for SPI_RXCRCR register ******************/
bogdanm 73:1efda918f0ba 7572 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
bogdanm 73:1efda918f0ba 7573
bogdanm 73:1efda918f0ba 7574 /****************** Bit definition for SPI_TXCRCR register ******************/
bogdanm 73:1efda918f0ba 7575 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
bogdanm 73:1efda918f0ba 7576
bogdanm 73:1efda918f0ba 7577 /****************** Bit definition for SPI_I2SCFGR register *****************/
bogdanm 73:1efda918f0ba 7578 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
bogdanm 73:1efda918f0ba 7579
bogdanm 73:1efda918f0ba 7580 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */
bogdanm 73:1efda918f0ba 7581 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7582 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7583
bogdanm 73:1efda918f0ba 7584 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
bogdanm 73:1efda918f0ba 7585
bogdanm 73:1efda918f0ba 7586 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */
bogdanm 73:1efda918f0ba 7587 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7588 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7589
bogdanm 73:1efda918f0ba 7590 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
bogdanm 73:1efda918f0ba 7591
bogdanm 73:1efda918f0ba 7592 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */
bogdanm 73:1efda918f0ba 7593 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7594 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7595
bogdanm 73:1efda918f0ba 7596 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */
bogdanm 73:1efda918f0ba 7597 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */
bogdanm 73:1efda918f0ba 7598
bogdanm 73:1efda918f0ba 7599 /****************** Bit definition for SPI_I2SPR register *******************/
bogdanm 73:1efda918f0ba 7600 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
bogdanm 73:1efda918f0ba 7601 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
bogdanm 73:1efda918f0ba 7602 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */
bogdanm 73:1efda918f0ba 7603
bogdanm 73:1efda918f0ba 7604 /******************************************************************************/
bogdanm 73:1efda918f0ba 7605 /* */
bogdanm 73:1efda918f0ba 7606 /* Inter-integrated Circuit Interface */
bogdanm 73:1efda918f0ba 7607 /* */
bogdanm 73:1efda918f0ba 7608 /******************************************************************************/
bogdanm 73:1efda918f0ba 7609
bogdanm 73:1efda918f0ba 7610 /******************* Bit definition for I2C_CR1 register ********************/
bogdanm 73:1efda918f0ba 7611 #define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
bogdanm 73:1efda918f0ba 7612 #define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
bogdanm 73:1efda918f0ba 7613 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
bogdanm 73:1efda918f0ba 7614 #define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
bogdanm 73:1efda918f0ba 7615 #define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
bogdanm 73:1efda918f0ba 7616 #define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
bogdanm 73:1efda918f0ba 7617 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
bogdanm 73:1efda918f0ba 7618 #define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
bogdanm 73:1efda918f0ba 7619 #define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
bogdanm 73:1efda918f0ba 7620 #define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
bogdanm 73:1efda918f0ba 7621 #define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
bogdanm 73:1efda918f0ba 7622 #define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
bogdanm 73:1efda918f0ba 7623 #define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
bogdanm 73:1efda918f0ba 7624 #define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
bogdanm 73:1efda918f0ba 7625
bogdanm 73:1efda918f0ba 7626 /******************* Bit definition for I2C_CR2 register ********************/
bogdanm 73:1efda918f0ba 7627 #define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
bogdanm 73:1efda918f0ba 7628 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7629 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7630 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 7631 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 7632 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 7633 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 7634
bogdanm 73:1efda918f0ba 7635 #define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
bogdanm 73:1efda918f0ba 7636 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
bogdanm 73:1efda918f0ba 7637 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
bogdanm 73:1efda918f0ba 7638 #define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
bogdanm 73:1efda918f0ba 7639 #define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
bogdanm 73:1efda918f0ba 7640
bogdanm 73:1efda918f0ba 7641 /******************* Bit definition for I2C_OAR1 register *******************/
bogdanm 73:1efda918f0ba 7642 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
bogdanm 73:1efda918f0ba 7643 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
bogdanm 73:1efda918f0ba 7644
bogdanm 73:1efda918f0ba 7645 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7646 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7647 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 7648 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 7649 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 7650 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 7651 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 7652 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 7653 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
bogdanm 73:1efda918f0ba 7654 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
bogdanm 73:1efda918f0ba 7655
bogdanm 73:1efda918f0ba 7656 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
bogdanm 73:1efda918f0ba 7657
bogdanm 73:1efda918f0ba 7658 /******************* Bit definition for I2C_OAR2 register *******************/
bogdanm 73:1efda918f0ba 7659 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
bogdanm 73:1efda918f0ba 7660 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
bogdanm 73:1efda918f0ba 7661
bogdanm 73:1efda918f0ba 7662 /******************** Bit definition for I2C_DR register ********************/
bogdanm 73:1efda918f0ba 7663 #define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
bogdanm 73:1efda918f0ba 7664
bogdanm 73:1efda918f0ba 7665 /******************* Bit definition for I2C_SR1 register ********************/
bogdanm 73:1efda918f0ba 7666 #define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
bogdanm 73:1efda918f0ba 7667 #define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
bogdanm 73:1efda918f0ba 7668 #define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
bogdanm 73:1efda918f0ba 7669 #define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
bogdanm 73:1efda918f0ba 7670 #define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
bogdanm 73:1efda918f0ba 7671 #define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
bogdanm 73:1efda918f0ba 7672 #define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
bogdanm 73:1efda918f0ba 7673 #define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
bogdanm 73:1efda918f0ba 7674 #define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
bogdanm 73:1efda918f0ba 7675 #define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
bogdanm 73:1efda918f0ba 7676 #define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
bogdanm 73:1efda918f0ba 7677 #define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
bogdanm 73:1efda918f0ba 7678 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
bogdanm 73:1efda918f0ba 7679 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
bogdanm 73:1efda918f0ba 7680
bogdanm 73:1efda918f0ba 7681 /******************* Bit definition for I2C_SR2 register ********************/
bogdanm 73:1efda918f0ba 7682 #define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
bogdanm 73:1efda918f0ba 7683 #define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
bogdanm 73:1efda918f0ba 7684 #define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
bogdanm 73:1efda918f0ba 7685 #define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
bogdanm 73:1efda918f0ba 7686 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
bogdanm 73:1efda918f0ba 7687 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
bogdanm 73:1efda918f0ba 7688 #define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
bogdanm 73:1efda918f0ba 7689 #define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
bogdanm 73:1efda918f0ba 7690
bogdanm 73:1efda918f0ba 7691 /******************* Bit definition for I2C_CCR register ********************/
bogdanm 73:1efda918f0ba 7692 #define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
bogdanm 73:1efda918f0ba 7693 #define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
bogdanm 73:1efda918f0ba 7694 #define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
bogdanm 73:1efda918f0ba 7695
bogdanm 73:1efda918f0ba 7696 /****************** Bit definition for I2C_TRISE register *******************/
bogdanm 73:1efda918f0ba 7697 #define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
bogdanm 73:1efda918f0ba 7698
bogdanm 73:1efda918f0ba 7699 /******************************************************************************/
bogdanm 73:1efda918f0ba 7700 /* */
bogdanm 73:1efda918f0ba 7701 /* Universal Synchronous Asynchronous Receiver Transmitter */
bogdanm 73:1efda918f0ba 7702 /* */
bogdanm 73:1efda918f0ba 7703 /******************************************************************************/
bogdanm 73:1efda918f0ba 7704
bogdanm 73:1efda918f0ba 7705 /******************* Bit definition for USART_SR register *******************/
bogdanm 73:1efda918f0ba 7706 #define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
bogdanm 73:1efda918f0ba 7707 #define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
bogdanm 73:1efda918f0ba 7708 #define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
bogdanm 73:1efda918f0ba 7709 #define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
bogdanm 73:1efda918f0ba 7710 #define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
bogdanm 73:1efda918f0ba 7711 #define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
bogdanm 73:1efda918f0ba 7712 #define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
bogdanm 73:1efda918f0ba 7713 #define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
bogdanm 73:1efda918f0ba 7714 #define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
bogdanm 73:1efda918f0ba 7715 #define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
bogdanm 73:1efda918f0ba 7716
bogdanm 73:1efda918f0ba 7717 /******************* Bit definition for USART_DR register *******************/
bogdanm 73:1efda918f0ba 7718 #define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
bogdanm 73:1efda918f0ba 7719
bogdanm 73:1efda918f0ba 7720 /****************** Bit definition for USART_BRR register *******************/
bogdanm 73:1efda918f0ba 7721 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
bogdanm 73:1efda918f0ba 7722 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
bogdanm 73:1efda918f0ba 7723
bogdanm 73:1efda918f0ba 7724 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 73:1efda918f0ba 7725 #define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
bogdanm 73:1efda918f0ba 7726 #define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
bogdanm 73:1efda918f0ba 7727 #define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
bogdanm 73:1efda918f0ba 7728 #define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
bogdanm 73:1efda918f0ba 7729 #define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
bogdanm 73:1efda918f0ba 7730 #define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
bogdanm 73:1efda918f0ba 7731 #define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
bogdanm 73:1efda918f0ba 7732 #define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
bogdanm 73:1efda918f0ba 7733 #define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
bogdanm 73:1efda918f0ba 7734 #define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
bogdanm 73:1efda918f0ba 7735 #define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
bogdanm 73:1efda918f0ba 7736 #define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
bogdanm 73:1efda918f0ba 7737 #define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
bogdanm 73:1efda918f0ba 7738 #define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
bogdanm 73:1efda918f0ba 7739 #define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */
bogdanm 73:1efda918f0ba 7740
bogdanm 73:1efda918f0ba 7741 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 73:1efda918f0ba 7742 #define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
bogdanm 73:1efda918f0ba 7743 #define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
bogdanm 73:1efda918f0ba 7744 #define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
bogdanm 73:1efda918f0ba 7745 #define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
bogdanm 73:1efda918f0ba 7746 #define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
bogdanm 73:1efda918f0ba 7747 #define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
bogdanm 73:1efda918f0ba 7748 #define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
bogdanm 73:1efda918f0ba 7749
bogdanm 73:1efda918f0ba 7750 #define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
bogdanm 73:1efda918f0ba 7751 #define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7752 #define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7753
bogdanm 73:1efda918f0ba 7754 #define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
bogdanm 73:1efda918f0ba 7755
bogdanm 73:1efda918f0ba 7756 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 73:1efda918f0ba 7757 #define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
bogdanm 73:1efda918f0ba 7758 #define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
bogdanm 73:1efda918f0ba 7759 #define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
bogdanm 73:1efda918f0ba 7760 #define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
bogdanm 73:1efda918f0ba 7761 #define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
bogdanm 73:1efda918f0ba 7762 #define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
bogdanm 73:1efda918f0ba 7763 #define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
bogdanm 73:1efda918f0ba 7764 #define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
bogdanm 73:1efda918f0ba 7765 #define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
bogdanm 73:1efda918f0ba 7766 #define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
bogdanm 73:1efda918f0ba 7767 #define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
bogdanm 73:1efda918f0ba 7768 #define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */
bogdanm 73:1efda918f0ba 7769
bogdanm 73:1efda918f0ba 7770 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 73:1efda918f0ba 7771 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
bogdanm 73:1efda918f0ba 7772 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7773 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7774 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 7775 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 7776 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 7777 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 7778 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 7779 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 7780
bogdanm 73:1efda918f0ba 7781 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
bogdanm 73:1efda918f0ba 7782
bogdanm 73:1efda918f0ba 7783 /******************************************************************************/
bogdanm 73:1efda918f0ba 7784 /* */
bogdanm 73:1efda918f0ba 7785 /* Debug MCU */
bogdanm 73:1efda918f0ba 7786 /* */
bogdanm 73:1efda918f0ba 7787 /******************************************************************************/
bogdanm 73:1efda918f0ba 7788
bogdanm 73:1efda918f0ba 7789 /**************** Bit definition for DBGMCU_IDCODE register *****************/
bogdanm 73:1efda918f0ba 7790 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
bogdanm 73:1efda918f0ba 7791
bogdanm 73:1efda918f0ba 7792 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
bogdanm 73:1efda918f0ba 7793 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7794 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7795 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 73:1efda918f0ba 7796 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 73:1efda918f0ba 7797 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 73:1efda918f0ba 7798 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 73:1efda918f0ba 7799 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 73:1efda918f0ba 7800 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 73:1efda918f0ba 7801 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
bogdanm 73:1efda918f0ba 7802 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
bogdanm 73:1efda918f0ba 7803 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
bogdanm 73:1efda918f0ba 7804 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
bogdanm 73:1efda918f0ba 7805 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
bogdanm 73:1efda918f0ba 7806 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
bogdanm 73:1efda918f0ba 7807 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
bogdanm 73:1efda918f0ba 7808 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
bogdanm 73:1efda918f0ba 7809
bogdanm 73:1efda918f0ba 7810 /****************** Bit definition for DBGMCU_CR register *******************/
bogdanm 73:1efda918f0ba 7811 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
bogdanm 73:1efda918f0ba 7812 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
bogdanm 73:1efda918f0ba 7813 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
bogdanm 73:1efda918f0ba 7814 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
bogdanm 73:1efda918f0ba 7815
bogdanm 73:1efda918f0ba 7816 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
bogdanm 73:1efda918f0ba 7817 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7818 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7819
bogdanm 73:1efda918f0ba 7820 #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
bogdanm 73:1efda918f0ba 7821 #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
bogdanm 73:1efda918f0ba 7822 #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
bogdanm 73:1efda918f0ba 7823 #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
bogdanm 73:1efda918f0ba 7824 #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
bogdanm 73:1efda918f0ba 7825 #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
bogdanm 73:1efda918f0ba 7826 #define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7827 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
bogdanm 73:1efda918f0ba 7828 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
bogdanm 73:1efda918f0ba 7829 #define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
bogdanm 73:1efda918f0ba 7830 #define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
bogdanm 73:1efda918f0ba 7831 #define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
bogdanm 73:1efda918f0ba 7832 #define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
bogdanm 73:1efda918f0ba 7833 #define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7834 #define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7835 #define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7836 #define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7837 #define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7838 #define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7839 #define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7840 #define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7841 #define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7842 #define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */
bogdanm 73:1efda918f0ba 7843
bogdanm 73:1efda918f0ba 7844 /******************************************************************************/
bogdanm 73:1efda918f0ba 7845 /* */
bogdanm 73:1efda918f0ba 7846 /* FLASH and Option Bytes Registers */
bogdanm 73:1efda918f0ba 7847 /* */
bogdanm 73:1efda918f0ba 7848 /******************************************************************************/
bogdanm 73:1efda918f0ba 7849
bogdanm 73:1efda918f0ba 7850 /******************* Bit definition for FLASH_ACR register ******************/
emilmont 77:869cf507173a 7851 #define FLASH_ACR_LATENCY ((uint8_t)0x07) /*!< LATENCY[2:0] bits (Latency) */
bogdanm 73:1efda918f0ba 7852 #define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7853 #define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */
bogdanm 73:1efda918f0ba 7854 #define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */
bogdanm 73:1efda918f0ba 7855
bogdanm 73:1efda918f0ba 7856 #define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */
bogdanm 73:1efda918f0ba 7857 #define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */
bogdanm 73:1efda918f0ba 7858 #define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */
bogdanm 73:1efda918f0ba 7859
bogdanm 73:1efda918f0ba 7860 /****************** Bit definition for FLASH_KEYR register ******************/
bogdanm 73:1efda918f0ba 7861 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
bogdanm 73:1efda918f0ba 7862
emilmont 77:869cf507173a 7863 /****************** FLASH Keys **********************************************/
emilmont 77:869cf507173a 7864 #define RDP_Key ((uint16_t)0x00A5)
emilmont 77:869cf507173a 7865 #define FLASH_KEY1 ((uint32_t)0x45670123)
emilmont 77:869cf507173a 7866 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
emilmont 77:869cf507173a 7867
bogdanm 73:1efda918f0ba 7868 /***************** Bit definition for FLASH_OPTKEYR register ****************/
bogdanm 73:1efda918f0ba 7869 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
bogdanm 73:1efda918f0ba 7870
bogdanm 73:1efda918f0ba 7871 /****************** Bit definition for FLASH_SR register *******************/
bogdanm 73:1efda918f0ba 7872 #define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */
bogdanm 73:1efda918f0ba 7873 #define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */
bogdanm 73:1efda918f0ba 7874 #define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */
bogdanm 73:1efda918f0ba 7875 #define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */
bogdanm 73:1efda918f0ba 7876
bogdanm 73:1efda918f0ba 7877 /******************* Bit definition for FLASH_CR register *******************/
bogdanm 73:1efda918f0ba 7878 #define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */
bogdanm 73:1efda918f0ba 7879 #define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */
bogdanm 73:1efda918f0ba 7880 #define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */
bogdanm 73:1efda918f0ba 7881 #define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */
bogdanm 73:1efda918f0ba 7882 #define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */
bogdanm 73:1efda918f0ba 7883 #define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */
bogdanm 73:1efda918f0ba 7884 #define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */
bogdanm 73:1efda918f0ba 7885 #define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
bogdanm 73:1efda918f0ba 7886 #define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */
bogdanm 73:1efda918f0ba 7887 #define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */
bogdanm 73:1efda918f0ba 7888
bogdanm 73:1efda918f0ba 7889 /******************* Bit definition for FLASH_AR register *******************/
bogdanm 73:1efda918f0ba 7890 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
bogdanm 73:1efda918f0ba 7891
bogdanm 73:1efda918f0ba 7892 /****************** Bit definition for FLASH_OBR register *******************/
bogdanm 73:1efda918f0ba 7893 #define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */
bogdanm 73:1efda918f0ba 7894 #define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */
bogdanm 73:1efda918f0ba 7895
bogdanm 73:1efda918f0ba 7896 #define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */
bogdanm 73:1efda918f0ba 7897 #define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */
bogdanm 73:1efda918f0ba 7898 #define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */
bogdanm 73:1efda918f0ba 7899 #define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
bogdanm 73:1efda918f0ba 7900 #define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */
bogdanm 73:1efda918f0ba 7901
bogdanm 73:1efda918f0ba 7902 /****************** Bit definition for FLASH_WRPR register ******************/
bogdanm 73:1efda918f0ba 7903 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
bogdanm 73:1efda918f0ba 7904
bogdanm 73:1efda918f0ba 7905 /*----------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 7906
bogdanm 73:1efda918f0ba 7907 /****************** Bit definition for FLASH_RDP register *******************/
bogdanm 73:1efda918f0ba 7908 #define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
bogdanm 73:1efda918f0ba 7909 #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
bogdanm 73:1efda918f0ba 7910
bogdanm 73:1efda918f0ba 7911 /****************** Bit definition for FLASH_USER register ******************/
bogdanm 73:1efda918f0ba 7912 #define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
bogdanm 73:1efda918f0ba 7913 #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
bogdanm 73:1efda918f0ba 7914
bogdanm 73:1efda918f0ba 7915 /****************** Bit definition for FLASH_Data0 register *****************/
bogdanm 73:1efda918f0ba 7916 #define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
bogdanm 73:1efda918f0ba 7917 #define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
bogdanm 73:1efda918f0ba 7918
bogdanm 73:1efda918f0ba 7919 /****************** Bit definition for FLASH_Data1 register *****************/
bogdanm 73:1efda918f0ba 7920 #define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
bogdanm 73:1efda918f0ba 7921 #define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
bogdanm 73:1efda918f0ba 7922
bogdanm 73:1efda918f0ba 7923 /****************** Bit definition for FLASH_WRP0 register ******************/
bogdanm 73:1efda918f0ba 7924 #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
bogdanm 73:1efda918f0ba 7925 #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
bogdanm 73:1efda918f0ba 7926
bogdanm 73:1efda918f0ba 7927 /****************** Bit definition for FLASH_WRP1 register ******************/
bogdanm 73:1efda918f0ba 7928 #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
bogdanm 73:1efda918f0ba 7929 #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
bogdanm 73:1efda918f0ba 7930
bogdanm 73:1efda918f0ba 7931 /****************** Bit definition for FLASH_WRP2 register ******************/
bogdanm 73:1efda918f0ba 7932 #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
bogdanm 73:1efda918f0ba 7933 #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
bogdanm 73:1efda918f0ba 7934
bogdanm 73:1efda918f0ba 7935 /****************** Bit definition for FLASH_WRP3 register ******************/
bogdanm 73:1efda918f0ba 7936 #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
bogdanm 73:1efda918f0ba 7937 #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
bogdanm 73:1efda918f0ba 7938
bogdanm 73:1efda918f0ba 7939 #ifdef STM32F10X_CL
bogdanm 73:1efda918f0ba 7940 /******************************************************************************/
bogdanm 73:1efda918f0ba 7941 /* Ethernet MAC Registers bits definitions */
bogdanm 73:1efda918f0ba 7942 /******************************************************************************/
bogdanm 73:1efda918f0ba 7943 /* Bit definition for Ethernet MAC Control Register register */
bogdanm 73:1efda918f0ba 7944 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
bogdanm 73:1efda918f0ba 7945 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
bogdanm 73:1efda918f0ba 7946 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
bogdanm 73:1efda918f0ba 7947 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
bogdanm 73:1efda918f0ba 7948 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
bogdanm 73:1efda918f0ba 7949 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
bogdanm 73:1efda918f0ba 7950 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
bogdanm 73:1efda918f0ba 7951 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
bogdanm 73:1efda918f0ba 7952 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
bogdanm 73:1efda918f0ba 7953 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
bogdanm 73:1efda918f0ba 7954 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
bogdanm 73:1efda918f0ba 7955 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
bogdanm 73:1efda918f0ba 7956 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
bogdanm 73:1efda918f0ba 7957 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
bogdanm 73:1efda918f0ba 7958 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
bogdanm 73:1efda918f0ba 7959 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
bogdanm 73:1efda918f0ba 7960 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
bogdanm 73:1efda918f0ba 7961 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
bogdanm 73:1efda918f0ba 7962 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
bogdanm 73:1efda918f0ba 7963 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
bogdanm 73:1efda918f0ba 7964 a transmission attempt during retries after a collision: 0 =< r <2^k */
bogdanm 73:1efda918f0ba 7965 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
bogdanm 73:1efda918f0ba 7966 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
bogdanm 73:1efda918f0ba 7967 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
bogdanm 73:1efda918f0ba 7968 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
bogdanm 73:1efda918f0ba 7969 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
bogdanm 73:1efda918f0ba 7970 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
bogdanm 73:1efda918f0ba 7971 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
bogdanm 73:1efda918f0ba 7972
bogdanm 73:1efda918f0ba 7973 /* Bit definition for Ethernet MAC Frame Filter Register */
bogdanm 73:1efda918f0ba 7974 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
bogdanm 73:1efda918f0ba 7975 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
bogdanm 73:1efda918f0ba 7976 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
bogdanm 73:1efda918f0ba 7977 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
bogdanm 73:1efda918f0ba 7978 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
bogdanm 73:1efda918f0ba 7979 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
bogdanm 73:1efda918f0ba 7980 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
bogdanm 73:1efda918f0ba 7981 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
bogdanm 73:1efda918f0ba 7982 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
bogdanm 73:1efda918f0ba 7983 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
bogdanm 73:1efda918f0ba 7984 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
bogdanm 73:1efda918f0ba 7985 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
bogdanm 73:1efda918f0ba 7986 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
bogdanm 73:1efda918f0ba 7987 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
bogdanm 73:1efda918f0ba 7988
bogdanm 73:1efda918f0ba 7989 /* Bit definition for Ethernet MAC Hash Table High Register */
bogdanm 73:1efda918f0ba 7990 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
bogdanm 73:1efda918f0ba 7991
bogdanm 73:1efda918f0ba 7992 /* Bit definition for Ethernet MAC Hash Table Low Register */
bogdanm 73:1efda918f0ba 7993 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
bogdanm 73:1efda918f0ba 7994
bogdanm 73:1efda918f0ba 7995 /* Bit definition for Ethernet MAC MII Address Register */
bogdanm 73:1efda918f0ba 7996 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
bogdanm 73:1efda918f0ba 7997 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
bogdanm 73:1efda918f0ba 7998 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
bogdanm 73:1efda918f0ba 7999 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
bogdanm 73:1efda918f0ba 8000 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
bogdanm 73:1efda918f0ba 8001 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
bogdanm 73:1efda918f0ba 8002 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
bogdanm 73:1efda918f0ba 8003 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
bogdanm 73:1efda918f0ba 8004
bogdanm 73:1efda918f0ba 8005 /* Bit definition for Ethernet MAC MII Data Register */
bogdanm 73:1efda918f0ba 8006 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
bogdanm 73:1efda918f0ba 8007
bogdanm 73:1efda918f0ba 8008 /* Bit definition for Ethernet MAC Flow Control Register */
bogdanm 73:1efda918f0ba 8009 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
bogdanm 73:1efda918f0ba 8010 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
bogdanm 73:1efda918f0ba 8011 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
bogdanm 73:1efda918f0ba 8012 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
bogdanm 73:1efda918f0ba 8013 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
bogdanm 73:1efda918f0ba 8014 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
bogdanm 73:1efda918f0ba 8015 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
bogdanm 73:1efda918f0ba 8016 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
bogdanm 73:1efda918f0ba 8017 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
bogdanm 73:1efda918f0ba 8018 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
bogdanm 73:1efda918f0ba 8019 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
bogdanm 73:1efda918f0ba 8020
bogdanm 73:1efda918f0ba 8021 /* Bit definition for Ethernet MAC VLAN Tag Register */
bogdanm 73:1efda918f0ba 8022 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
bogdanm 73:1efda918f0ba 8023 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
bogdanm 73:1efda918f0ba 8024
bogdanm 73:1efda918f0ba 8025 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
bogdanm 73:1efda918f0ba 8026 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
bogdanm 73:1efda918f0ba 8027 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
bogdanm 73:1efda918f0ba 8028 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
bogdanm 73:1efda918f0ba 8029 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
bogdanm 73:1efda918f0ba 8030 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
bogdanm 73:1efda918f0ba 8031 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
bogdanm 73:1efda918f0ba 8032 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
bogdanm 73:1efda918f0ba 8033 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
bogdanm 73:1efda918f0ba 8034 RSVD - Filter1 Command - RSVD - Filter0 Command
bogdanm 73:1efda918f0ba 8035 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
bogdanm 73:1efda918f0ba 8036 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
bogdanm 73:1efda918f0ba 8037 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
bogdanm 73:1efda918f0ba 8038
bogdanm 73:1efda918f0ba 8039 /* Bit definition for Ethernet MAC PMT Control and Status Register */
bogdanm 73:1efda918f0ba 8040 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
bogdanm 73:1efda918f0ba 8041 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
bogdanm 73:1efda918f0ba 8042 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
bogdanm 73:1efda918f0ba 8043 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
bogdanm 73:1efda918f0ba 8044 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
bogdanm 73:1efda918f0ba 8045 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
bogdanm 73:1efda918f0ba 8046 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
bogdanm 73:1efda918f0ba 8047
bogdanm 73:1efda918f0ba 8048 /* Bit definition for Ethernet MAC Status Register */
bogdanm 73:1efda918f0ba 8049 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
bogdanm 73:1efda918f0ba 8050 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
bogdanm 73:1efda918f0ba 8051 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
bogdanm 73:1efda918f0ba 8052 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
bogdanm 73:1efda918f0ba 8053 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
bogdanm 73:1efda918f0ba 8054
bogdanm 73:1efda918f0ba 8055 /* Bit definition for Ethernet MAC Interrupt Mask Register */
bogdanm 73:1efda918f0ba 8056 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
bogdanm 73:1efda918f0ba 8057 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
bogdanm 73:1efda918f0ba 8058
bogdanm 73:1efda918f0ba 8059 /* Bit definition for Ethernet MAC Address0 High Register */
bogdanm 73:1efda918f0ba 8060 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
bogdanm 73:1efda918f0ba 8061
bogdanm 73:1efda918f0ba 8062 /* Bit definition for Ethernet MAC Address0 Low Register */
bogdanm 73:1efda918f0ba 8063 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
bogdanm 73:1efda918f0ba 8064
bogdanm 73:1efda918f0ba 8065 /* Bit definition for Ethernet MAC Address1 High Register */
bogdanm 73:1efda918f0ba 8066 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 73:1efda918f0ba 8067 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 73:1efda918f0ba 8068 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
bogdanm 73:1efda918f0ba 8069 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 73:1efda918f0ba 8070 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 73:1efda918f0ba 8071 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 73:1efda918f0ba 8072 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 73:1efda918f0ba 8073 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 73:1efda918f0ba 8074 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
bogdanm 73:1efda918f0ba 8075 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
bogdanm 73:1efda918f0ba 8076
bogdanm 73:1efda918f0ba 8077 /* Bit definition for Ethernet MAC Address1 Low Register */
bogdanm 73:1efda918f0ba 8078 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
bogdanm 73:1efda918f0ba 8079
bogdanm 73:1efda918f0ba 8080 /* Bit definition for Ethernet MAC Address2 High Register */
bogdanm 73:1efda918f0ba 8081 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 73:1efda918f0ba 8082 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 73:1efda918f0ba 8083 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
bogdanm 73:1efda918f0ba 8084 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 73:1efda918f0ba 8085 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 73:1efda918f0ba 8086 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 73:1efda918f0ba 8087 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 73:1efda918f0ba 8088 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 73:1efda918f0ba 8089 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
bogdanm 73:1efda918f0ba 8090 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
bogdanm 73:1efda918f0ba 8091
bogdanm 73:1efda918f0ba 8092 /* Bit definition for Ethernet MAC Address2 Low Register */
bogdanm 73:1efda918f0ba 8093 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
bogdanm 73:1efda918f0ba 8094
bogdanm 73:1efda918f0ba 8095 /* Bit definition for Ethernet MAC Address3 High Register */
bogdanm 73:1efda918f0ba 8096 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 73:1efda918f0ba 8097 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 73:1efda918f0ba 8098 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
bogdanm 73:1efda918f0ba 8099 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 73:1efda918f0ba 8100 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 73:1efda918f0ba 8101 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 73:1efda918f0ba 8102 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 73:1efda918f0ba 8103 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 73:1efda918f0ba 8104 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
bogdanm 73:1efda918f0ba 8105 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
bogdanm 73:1efda918f0ba 8106
bogdanm 73:1efda918f0ba 8107 /* Bit definition for Ethernet MAC Address3 Low Register */
bogdanm 73:1efda918f0ba 8108 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
bogdanm 73:1efda918f0ba 8109
bogdanm 73:1efda918f0ba 8110 /******************************************************************************/
bogdanm 73:1efda918f0ba 8111 /* Ethernet MMC Registers bits definition */
bogdanm 73:1efda918f0ba 8112 /******************************************************************************/
bogdanm 73:1efda918f0ba 8113
bogdanm 73:1efda918f0ba 8114 /* Bit definition for Ethernet MMC Contol Register */
bogdanm 73:1efda918f0ba 8115 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
bogdanm 73:1efda918f0ba 8116 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
bogdanm 73:1efda918f0ba 8117 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
bogdanm 73:1efda918f0ba 8118 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
bogdanm 73:1efda918f0ba 8119
bogdanm 73:1efda918f0ba 8120 /* Bit definition for Ethernet MMC Receive Interrupt Register */
bogdanm 73:1efda918f0ba 8121 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8122 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8123 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8124
bogdanm 73:1efda918f0ba 8125 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
bogdanm 73:1efda918f0ba 8126 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8127 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8128 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8129
bogdanm 73:1efda918f0ba 8130 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
bogdanm 73:1efda918f0ba 8131 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8132 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8133 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8134
bogdanm 73:1efda918f0ba 8135 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
bogdanm 73:1efda918f0ba 8136 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8137 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8138 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
bogdanm 73:1efda918f0ba 8139
bogdanm 73:1efda918f0ba 8140 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
bogdanm 73:1efda918f0ba 8141 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
bogdanm 73:1efda918f0ba 8142
bogdanm 73:1efda918f0ba 8143 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
bogdanm 73:1efda918f0ba 8144 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
bogdanm 73:1efda918f0ba 8145
bogdanm 73:1efda918f0ba 8146 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
bogdanm 73:1efda918f0ba 8147 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
bogdanm 73:1efda918f0ba 8148
bogdanm 73:1efda918f0ba 8149 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
bogdanm 73:1efda918f0ba 8150 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
bogdanm 73:1efda918f0ba 8151
bogdanm 73:1efda918f0ba 8152 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
bogdanm 73:1efda918f0ba 8153 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
bogdanm 73:1efda918f0ba 8154
bogdanm 73:1efda918f0ba 8155 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
bogdanm 73:1efda918f0ba 8156 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
bogdanm 73:1efda918f0ba 8157
bogdanm 73:1efda918f0ba 8158 /******************************************************************************/
bogdanm 73:1efda918f0ba 8159 /* Ethernet PTP Registers bits definition */
bogdanm 73:1efda918f0ba 8160 /******************************************************************************/
bogdanm 73:1efda918f0ba 8161
bogdanm 73:1efda918f0ba 8162 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
bogdanm 73:1efda918f0ba 8163 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
bogdanm 73:1efda918f0ba 8164 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
bogdanm 73:1efda918f0ba 8165 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
bogdanm 73:1efda918f0ba 8166 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
bogdanm 73:1efda918f0ba 8167 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
bogdanm 73:1efda918f0ba 8168 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
bogdanm 73:1efda918f0ba 8169
bogdanm 73:1efda918f0ba 8170 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
bogdanm 73:1efda918f0ba 8171 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
bogdanm 73:1efda918f0ba 8172
bogdanm 73:1efda918f0ba 8173 /* Bit definition for Ethernet PTP Time Stamp High Register */
bogdanm 73:1efda918f0ba 8174 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
bogdanm 73:1efda918f0ba 8175
bogdanm 73:1efda918f0ba 8176 /* Bit definition for Ethernet PTP Time Stamp Low Register */
bogdanm 73:1efda918f0ba 8177 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
bogdanm 73:1efda918f0ba 8178 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
bogdanm 73:1efda918f0ba 8179
bogdanm 73:1efda918f0ba 8180 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
bogdanm 73:1efda918f0ba 8181 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
bogdanm 73:1efda918f0ba 8182
bogdanm 73:1efda918f0ba 8183 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
bogdanm 73:1efda918f0ba 8184 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
bogdanm 73:1efda918f0ba 8185 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
bogdanm 73:1efda918f0ba 8186
bogdanm 73:1efda918f0ba 8187 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
bogdanm 73:1efda918f0ba 8188 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
bogdanm 73:1efda918f0ba 8189
bogdanm 73:1efda918f0ba 8190 /* Bit definition for Ethernet PTP Target Time High Register */
bogdanm 73:1efda918f0ba 8191 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
bogdanm 73:1efda918f0ba 8192
bogdanm 73:1efda918f0ba 8193 /* Bit definition for Ethernet PTP Target Time Low Register */
bogdanm 73:1efda918f0ba 8194 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
bogdanm 73:1efda918f0ba 8195
bogdanm 73:1efda918f0ba 8196 /******************************************************************************/
bogdanm 73:1efda918f0ba 8197 /* Ethernet DMA Registers bits definition */
bogdanm 73:1efda918f0ba 8198 /******************************************************************************/
bogdanm 73:1efda918f0ba 8199
bogdanm 73:1efda918f0ba 8200 /* Bit definition for Ethernet DMA Bus Mode Register */
bogdanm 73:1efda918f0ba 8201 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
bogdanm 73:1efda918f0ba 8202 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
bogdanm 73:1efda918f0ba 8203 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
bogdanm 73:1efda918f0ba 8204 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
bogdanm 73:1efda918f0ba 8205 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
bogdanm 73:1efda918f0ba 8206 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
bogdanm 73:1efda918f0ba 8207 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm 73:1efda918f0ba 8208 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm 73:1efda918f0ba 8209 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm 73:1efda918f0ba 8210 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm 73:1efda918f0ba 8211 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm 73:1efda918f0ba 8212 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm 73:1efda918f0ba 8213 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm 73:1efda918f0ba 8214 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm 73:1efda918f0ba 8215 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
bogdanm 73:1efda918f0ba 8216 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
bogdanm 73:1efda918f0ba 8217 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
bogdanm 73:1efda918f0ba 8218 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
bogdanm 73:1efda918f0ba 8219 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
bogdanm 73:1efda918f0ba 8220 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
bogdanm 73:1efda918f0ba 8221 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
bogdanm 73:1efda918f0ba 8222 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
bogdanm 73:1efda918f0ba 8223 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
bogdanm 73:1efda918f0ba 8224 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
bogdanm 73:1efda918f0ba 8225 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
bogdanm 73:1efda918f0ba 8226 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm 73:1efda918f0ba 8227 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm 73:1efda918f0ba 8228 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm 73:1efda918f0ba 8229 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm 73:1efda918f0ba 8230 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm 73:1efda918f0ba 8231 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm 73:1efda918f0ba 8232 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm 73:1efda918f0ba 8233 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm 73:1efda918f0ba 8234 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
bogdanm 73:1efda918f0ba 8235 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
bogdanm 73:1efda918f0ba 8236 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
bogdanm 73:1efda918f0ba 8237 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
bogdanm 73:1efda918f0ba 8238 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
bogdanm 73:1efda918f0ba 8239
bogdanm 73:1efda918f0ba 8240 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
bogdanm 73:1efda918f0ba 8241 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
bogdanm 73:1efda918f0ba 8242
bogdanm 73:1efda918f0ba 8243 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
bogdanm 73:1efda918f0ba 8244 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
bogdanm 73:1efda918f0ba 8245
bogdanm 73:1efda918f0ba 8246 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
bogdanm 73:1efda918f0ba 8247 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
bogdanm 73:1efda918f0ba 8248
bogdanm 73:1efda918f0ba 8249 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
bogdanm 73:1efda918f0ba 8250 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
bogdanm 73:1efda918f0ba 8251
bogdanm 73:1efda918f0ba 8252 /* Bit definition for Ethernet DMA Status Register */
bogdanm 73:1efda918f0ba 8253 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
bogdanm 73:1efda918f0ba 8254 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
bogdanm 73:1efda918f0ba 8255 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
bogdanm 73:1efda918f0ba 8256 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
bogdanm 73:1efda918f0ba 8257 /* combination with EBS[2:0] for GetFlagStatus function */
bogdanm 73:1efda918f0ba 8258 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
bogdanm 73:1efda918f0ba 8259 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
bogdanm 73:1efda918f0ba 8260 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
bogdanm 73:1efda918f0ba 8261 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
bogdanm 73:1efda918f0ba 8262 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
bogdanm 73:1efda918f0ba 8263 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
bogdanm 73:1efda918f0ba 8264 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
bogdanm 73:1efda918f0ba 8265 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
bogdanm 73:1efda918f0ba 8266 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
bogdanm 73:1efda918f0ba 8267 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
bogdanm 73:1efda918f0ba 8268 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
bogdanm 73:1efda918f0ba 8269 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
bogdanm 73:1efda918f0ba 8270 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
bogdanm 73:1efda918f0ba 8271 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
bogdanm 73:1efda918f0ba 8272 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
bogdanm 73:1efda918f0ba 8273 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
bogdanm 73:1efda918f0ba 8274 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
bogdanm 73:1efda918f0ba 8275 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
bogdanm 73:1efda918f0ba 8276 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
bogdanm 73:1efda918f0ba 8277 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
bogdanm 73:1efda918f0ba 8278 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
bogdanm 73:1efda918f0ba 8279 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
bogdanm 73:1efda918f0ba 8280 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
bogdanm 73:1efda918f0ba 8281 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
bogdanm 73:1efda918f0ba 8282 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
bogdanm 73:1efda918f0ba 8283 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
bogdanm 73:1efda918f0ba 8284 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
bogdanm 73:1efda918f0ba 8285 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
bogdanm 73:1efda918f0ba 8286 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
bogdanm 73:1efda918f0ba 8287 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
bogdanm 73:1efda918f0ba 8288 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
bogdanm 73:1efda918f0ba 8289 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
bogdanm 73:1efda918f0ba 8290
bogdanm 73:1efda918f0ba 8291 /* Bit definition for Ethernet DMA Operation Mode Register */
bogdanm 73:1efda918f0ba 8292 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
bogdanm 73:1efda918f0ba 8293 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
bogdanm 73:1efda918f0ba 8294 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
bogdanm 73:1efda918f0ba 8295 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
bogdanm 73:1efda918f0ba 8296 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
bogdanm 73:1efda918f0ba 8297 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
bogdanm 73:1efda918f0ba 8298 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
bogdanm 73:1efda918f0ba 8299 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
bogdanm 73:1efda918f0ba 8300 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
bogdanm 73:1efda918f0ba 8301 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
bogdanm 73:1efda918f0ba 8302 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
bogdanm 73:1efda918f0ba 8303 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
bogdanm 73:1efda918f0ba 8304 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
bogdanm 73:1efda918f0ba 8305 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
bogdanm 73:1efda918f0ba 8306 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
bogdanm 73:1efda918f0ba 8307 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
bogdanm 73:1efda918f0ba 8308 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
bogdanm 73:1efda918f0ba 8309 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
bogdanm 73:1efda918f0ba 8310 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
bogdanm 73:1efda918f0ba 8311 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
bogdanm 73:1efda918f0ba 8312 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
bogdanm 73:1efda918f0ba 8313 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
bogdanm 73:1efda918f0ba 8314 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
bogdanm 73:1efda918f0ba 8315 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
bogdanm 73:1efda918f0ba 8316
bogdanm 73:1efda918f0ba 8317 /* Bit definition for Ethernet DMA Interrupt Enable Register */
bogdanm 73:1efda918f0ba 8318 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
bogdanm 73:1efda918f0ba 8319 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
bogdanm 73:1efda918f0ba 8320 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
bogdanm 73:1efda918f0ba 8321 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
bogdanm 73:1efda918f0ba 8322 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
bogdanm 73:1efda918f0ba 8323 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
bogdanm 73:1efda918f0ba 8324 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
bogdanm 73:1efda918f0ba 8325 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
bogdanm 73:1efda918f0ba 8326 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
bogdanm 73:1efda918f0ba 8327 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
bogdanm 73:1efda918f0ba 8328 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
bogdanm 73:1efda918f0ba 8329 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
bogdanm 73:1efda918f0ba 8330 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
bogdanm 73:1efda918f0ba 8331 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
bogdanm 73:1efda918f0ba 8332 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
bogdanm 73:1efda918f0ba 8333
bogdanm 73:1efda918f0ba 8334 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
bogdanm 73:1efda918f0ba 8335 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
bogdanm 73:1efda918f0ba 8336 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
bogdanm 73:1efda918f0ba 8337 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
bogdanm 73:1efda918f0ba 8338 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
bogdanm 73:1efda918f0ba 8339
bogdanm 73:1efda918f0ba 8340 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
bogdanm 73:1efda918f0ba 8341 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
bogdanm 73:1efda918f0ba 8342
bogdanm 73:1efda918f0ba 8343 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
bogdanm 73:1efda918f0ba 8344 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
bogdanm 73:1efda918f0ba 8345
bogdanm 73:1efda918f0ba 8346 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
bogdanm 73:1efda918f0ba 8347 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
bogdanm 73:1efda918f0ba 8348
bogdanm 73:1efda918f0ba 8349 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
bogdanm 73:1efda918f0ba 8350 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
bogdanm 73:1efda918f0ba 8351 #endif /* STM32F10X_CL */
bogdanm 73:1efda918f0ba 8352
bogdanm 73:1efda918f0ba 8353 /**
bogdanm 73:1efda918f0ba 8354 * @}
bogdanm 73:1efda918f0ba 8355 */
bogdanm 73:1efda918f0ba 8356
bogdanm 73:1efda918f0ba 8357 /**
bogdanm 73:1efda918f0ba 8358 * @}
bogdanm 73:1efda918f0ba 8359 */
bogdanm 73:1efda918f0ba 8360
bogdanm 73:1efda918f0ba 8361 #ifdef USE_STDPERIPH_DRIVER
bogdanm 73:1efda918f0ba 8362 #include "stm32f10x_conf.h"
bogdanm 73:1efda918f0ba 8363 #endif
bogdanm 73:1efda918f0ba 8364
bogdanm 73:1efda918f0ba 8365 /** @addtogroup Exported_macro
bogdanm 73:1efda918f0ba 8366 * @{
bogdanm 73:1efda918f0ba 8367 */
bogdanm 73:1efda918f0ba 8368
bogdanm 73:1efda918f0ba 8369 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
bogdanm 73:1efda918f0ba 8370
bogdanm 73:1efda918f0ba 8371 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
bogdanm 73:1efda918f0ba 8372
bogdanm 73:1efda918f0ba 8373 #define READ_BIT(REG, BIT) ((REG) & (BIT))
bogdanm 73:1efda918f0ba 8374
bogdanm 73:1efda918f0ba 8375 #define CLEAR_REG(REG) ((REG) = (0x0))
bogdanm 73:1efda918f0ba 8376
bogdanm 73:1efda918f0ba 8377 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
bogdanm 73:1efda918f0ba 8378
bogdanm 73:1efda918f0ba 8379 #define READ_REG(REG) ((REG))
bogdanm 73:1efda918f0ba 8380
bogdanm 73:1efda918f0ba 8381 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
bogdanm 73:1efda918f0ba 8382
bogdanm 73:1efda918f0ba 8383 /**
bogdanm 73:1efda918f0ba 8384 * @}
bogdanm 73:1efda918f0ba 8385 */
bogdanm 73:1efda918f0ba 8386
bogdanm 73:1efda918f0ba 8387 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 8388 }
emilmont 77:869cf507173a 8389 #endif /* __cplusplus */
bogdanm 73:1efda918f0ba 8390
bogdanm 73:1efda918f0ba 8391 #endif /* __STM32F10x_H */
bogdanm 73:1efda918f0ba 8392
bogdanm 73:1efda918f0ba 8393 /**
bogdanm 73:1efda918f0ba 8394 * @}
bogdanm 73:1efda918f0ba 8395 */
bogdanm 73:1efda918f0ba 8396
bogdanm 73:1efda918f0ba 8397 /**
bogdanm 73:1efda918f0ba 8398 * @}
bogdanm 73:1efda918f0ba 8399 */
bogdanm 73:1efda918f0ba 8400
emilmont 77:869cf507173a 8401 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/