frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_NRF51822/core_cmInstr.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:
fblanc
Date:
Fri Dec 05 15:42:32 2014 +0000
Revision:
93:9dd889aeda0e
Parent:
80:8e73be2a2ac1 
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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emilmont 80:8e73be2a2ac1 1 /**************************************************************************//**
emilmont 80:8e73be2a2ac1 2 * @file core_cmInstr.h
emilmont 80:8e73be2a2ac1 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 80:8e73be2a2ac1 4 * @version V3.20
emilmont 80:8e73be2a2ac1 5 * @date 05. March 2013
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * @note
emilmont 80:8e73be2a2ac1 8 *
emilmont 80:8e73be2a2ac1 9 ******************************************************************************/
emilmont 80:8e73be2a2ac1 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 80:8e73be2a2ac1 11
emilmont 80:8e73be2a2ac1 12 All rights reserved.
emilmont 80:8e73be2a2ac1 13 Redistribution and use in source and binary forms, with or without
emilmont 80:8e73be2a2ac1 14 modification, are permitted provided that the following conditions are met:
emilmont 80:8e73be2a2ac1 15 - Redistributions of source code must retain the above copyright
emilmont 80:8e73be2a2ac1 16 notice, this list of conditions and the following disclaimer.
emilmont 80:8e73be2a2ac1 17 - Redistributions in binary form must reproduce the above copyright
emilmont 80:8e73be2a2ac1 18 notice, this list of conditions and the following disclaimer in the
emilmont 80:8e73be2a2ac1 19 documentation and/or other materials provided with the distribution.
emilmont 80:8e73be2a2ac1 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 80:8e73be2a2ac1 21 to endorse or promote products derived from this software without
emilmont 80:8e73be2a2ac1 22 specific prior written permission.
emilmont 80:8e73be2a2ac1 23 *
emilmont 80:8e73be2a2ac1 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 80:8e73be2a2ac1 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 80:8e73be2a2ac1 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 80:8e73be2a2ac1 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 80:8e73be2a2ac1 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 80:8e73be2a2ac1 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 80:8e73be2a2ac1 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 80:8e73be2a2ac1 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 80:8e73be2a2ac1 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 80:8e73be2a2ac1 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 80:8e73be2a2ac1 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 80:8e73be2a2ac1 35 ---------------------------------------------------------------------------*/
emilmont 80:8e73be2a2ac1 36
emilmont 80:8e73be2a2ac1 37
emilmont 80:8e73be2a2ac1 38 #ifndef __CORE_CMINSTR_H
emilmont 80:8e73be2a2ac1 39 #define __CORE_CMINSTR_H
emilmont 80:8e73be2a2ac1 40
emilmont 80:8e73be2a2ac1 41
emilmont 80:8e73be2a2ac1 42 /* ########################## Core Instruction Access ######################### */
emilmont 80:8e73be2a2ac1 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 80:8e73be2a2ac1 44 Access to dedicated instructions
emilmont 80:8e73be2a2ac1 45 @{
emilmont 80:8e73be2a2ac1 46 */
emilmont 80:8e73be2a2ac1 47
emilmont 80:8e73be2a2ac1 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 80:8e73be2a2ac1 49 /* ARM armcc specific functions */
emilmont 80:8e73be2a2ac1 50
emilmont 80:8e73be2a2ac1 51 #if (__ARMCC_VERSION < 400677)
emilmont 80:8e73be2a2ac1 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 80:8e73be2a2ac1 53 #endif
emilmont 80:8e73be2a2ac1 54
emilmont 80:8e73be2a2ac1 55
emilmont 80:8e73be2a2ac1 56 /** \brief No Operation
emilmont 80:8e73be2a2ac1 57
emilmont 80:8e73be2a2ac1 58 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 80:8e73be2a2ac1 59 */
emilmont 80:8e73be2a2ac1 60 #define __NOP __nop
emilmont 80:8e73be2a2ac1 61
emilmont 80:8e73be2a2ac1 62
emilmont 80:8e73be2a2ac1 63 /** \brief Wait For Interrupt
emilmont 80:8e73be2a2ac1 64
emilmont 80:8e73be2a2ac1 65 Wait For Interrupt is a hint instruction that suspends execution
emilmont 80:8e73be2a2ac1 66 until one of a number of events occurs.
emilmont 80:8e73be2a2ac1 67 */
emilmont 80:8e73be2a2ac1 68 #define __WFI __wfi
emilmont 80:8e73be2a2ac1 69
emilmont 80:8e73be2a2ac1 70
emilmont 80:8e73be2a2ac1 71 /** \brief Wait For Event
emilmont 80:8e73be2a2ac1 72
emilmont 80:8e73be2a2ac1 73 Wait For Event is a hint instruction that permits the processor to enter
emilmont 80:8e73be2a2ac1 74 a low-power state until one of a number of events occurs.
emilmont 80:8e73be2a2ac1 75 */
emilmont 80:8e73be2a2ac1 76 #define __WFE __wfe
emilmont 80:8e73be2a2ac1 77
emilmont 80:8e73be2a2ac1 78
emilmont 80:8e73be2a2ac1 79 /** \brief Send Event
emilmont 80:8e73be2a2ac1 80
emilmont 80:8e73be2a2ac1 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 80:8e73be2a2ac1 82 */
emilmont 80:8e73be2a2ac1 83 #define __SEV __sev
emilmont 80:8e73be2a2ac1 84
emilmont 80:8e73be2a2ac1 85
emilmont 80:8e73be2a2ac1 86 /** \brief Instruction Synchronization Barrier
emilmont 80:8e73be2a2ac1 87
emilmont 80:8e73be2a2ac1 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 80:8e73be2a2ac1 89 so that all instructions following the ISB are fetched from cache or
emilmont 80:8e73be2a2ac1 90 memory, after the instruction has been completed.
emilmont 80:8e73be2a2ac1 91 */
emilmont 80:8e73be2a2ac1 92 #define __ISB() __isb(0xF)
emilmont 80:8e73be2a2ac1 93
emilmont 80:8e73be2a2ac1 94
emilmont 80:8e73be2a2ac1 95 /** \brief Data Synchronization Barrier
emilmont 80:8e73be2a2ac1 96
emilmont 80:8e73be2a2ac1 97 This function acts as a special kind of Data Memory Barrier.
emilmont 80:8e73be2a2ac1 98 It completes when all explicit memory accesses before this instruction complete.
emilmont 80:8e73be2a2ac1 99 */
emilmont 80:8e73be2a2ac1 100 #define __DSB() __dsb(0xF)
emilmont 80:8e73be2a2ac1 101
emilmont 80:8e73be2a2ac1 102
emilmont 80:8e73be2a2ac1 103 /** \brief Data Memory Barrier
emilmont 80:8e73be2a2ac1 104
emilmont 80:8e73be2a2ac1 105 This function ensures the apparent order of the explicit memory operations before
emilmont 80:8e73be2a2ac1 106 and after the instruction, without ensuring their completion.
emilmont 80:8e73be2a2ac1 107 */
emilmont 80:8e73be2a2ac1 108 #define __DMB() __dmb(0xF)
emilmont 80:8e73be2a2ac1 109
emilmont 80:8e73be2a2ac1 110
emilmont 80:8e73be2a2ac1 111 /** \brief Reverse byte order (32 bit)
emilmont 80:8e73be2a2ac1 112
emilmont 80:8e73be2a2ac1 113 This function reverses the byte order in integer value.
emilmont 80:8e73be2a2ac1 114
emilmont 80:8e73be2a2ac1 115 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 116 \return Reversed value
emilmont 80:8e73be2a2ac1 117 */
emilmont 80:8e73be2a2ac1 118 #define __REV __rev
emilmont 80:8e73be2a2ac1 119
emilmont 80:8e73be2a2ac1 120
emilmont 80:8e73be2a2ac1 121 /** \brief Reverse byte order (16 bit)
emilmont 80:8e73be2a2ac1 122
emilmont 80:8e73be2a2ac1 123 This function reverses the byte order in two unsigned short values.
emilmont 80:8e73be2a2ac1 124
emilmont 80:8e73be2a2ac1 125 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 126 \return Reversed value
emilmont 80:8e73be2a2ac1 127 */
emilmont 80:8e73be2a2ac1 128 #ifndef __NO_EMBEDDED_ASM
emilmont 80:8e73be2a2ac1 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 80:8e73be2a2ac1 130 {
emilmont 80:8e73be2a2ac1 131 rev16 r0, r0
emilmont 80:8e73be2a2ac1 132 bx lr
emilmont 80:8e73be2a2ac1 133 }
emilmont 80:8e73be2a2ac1 134 #endif
emilmont 80:8e73be2a2ac1 135
emilmont 80:8e73be2a2ac1 136 /** \brief Reverse byte order in signed short value
emilmont 80:8e73be2a2ac1 137
emilmont 80:8e73be2a2ac1 138 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 80:8e73be2a2ac1 139
emilmont 80:8e73be2a2ac1 140 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 141 \return Reversed value
emilmont 80:8e73be2a2ac1 142 */
emilmont 80:8e73be2a2ac1 143 #ifndef __NO_EMBEDDED_ASM
emilmont 80:8e73be2a2ac1 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 80:8e73be2a2ac1 145 {
emilmont 80:8e73be2a2ac1 146 revsh r0, r0
emilmont 80:8e73be2a2ac1 147 bx lr
emilmont 80:8e73be2a2ac1 148 }
emilmont 80:8e73be2a2ac1 149 #endif
emilmont 80:8e73be2a2ac1 150
emilmont 80:8e73be2a2ac1 151
emilmont 80:8e73be2a2ac1 152 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 80:8e73be2a2ac1 153
emilmont 80:8e73be2a2ac1 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 80:8e73be2a2ac1 155
emilmont 80:8e73be2a2ac1 156 \param [in] value Value to rotate
emilmont 80:8e73be2a2ac1 157 \param [in] value Number of Bits to rotate
emilmont 80:8e73be2a2ac1 158 \return Rotated value
emilmont 80:8e73be2a2ac1 159 */
emilmont 80:8e73be2a2ac1 160 #define __ROR __ror
emilmont 80:8e73be2a2ac1 161
emilmont 80:8e73be2a2ac1 162
emilmont 80:8e73be2a2ac1 163 /** \brief Breakpoint
emilmont 80:8e73be2a2ac1 164
emilmont 80:8e73be2a2ac1 165 This function causes the processor to enter Debug state.
emilmont 80:8e73be2a2ac1 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 80:8e73be2a2ac1 167
emilmont 80:8e73be2a2ac1 168 \param [in] value is ignored by the processor.
emilmont 80:8e73be2a2ac1 169 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 80:8e73be2a2ac1 170 */
emilmont 80:8e73be2a2ac1 171 #define __BKPT(value) __breakpoint(value)
emilmont 80:8e73be2a2ac1 172
emilmont 80:8e73be2a2ac1 173
emilmont 80:8e73be2a2ac1 174 #if (__CORTEX_M >= 0x03)
emilmont 80:8e73be2a2ac1 175
emilmont 80:8e73be2a2ac1 176 /** \brief Reverse bit order of value
emilmont 80:8e73be2a2ac1 177
emilmont 80:8e73be2a2ac1 178 This function reverses the bit order of the given value.
emilmont 80:8e73be2a2ac1 179
emilmont 80:8e73be2a2ac1 180 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 181 \return Reversed value
emilmont 80:8e73be2a2ac1 182 */
emilmont 80:8e73be2a2ac1 183 #define __RBIT __rbit
emilmont 80:8e73be2a2ac1 184
emilmont 80:8e73be2a2ac1 185
emilmont 80:8e73be2a2ac1 186 /** \brief LDR Exclusive (8 bit)
emilmont 80:8e73be2a2ac1 187
emilmont 80:8e73be2a2ac1 188 This function performs a exclusive LDR command for 8 bit value.
emilmont 80:8e73be2a2ac1 189
emilmont 80:8e73be2a2ac1 190 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 191 \return value of type uint8_t at (*ptr)
emilmont 80:8e73be2a2ac1 192 */
emilmont 80:8e73be2a2ac1 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 80:8e73be2a2ac1 194
emilmont 80:8e73be2a2ac1 195
emilmont 80:8e73be2a2ac1 196 /** \brief LDR Exclusive (16 bit)
emilmont 80:8e73be2a2ac1 197
emilmont 80:8e73be2a2ac1 198 This function performs a exclusive LDR command for 16 bit values.
emilmont 80:8e73be2a2ac1 199
emilmont 80:8e73be2a2ac1 200 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 201 \return value of type uint16_t at (*ptr)
emilmont 80:8e73be2a2ac1 202 */
emilmont 80:8e73be2a2ac1 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 80:8e73be2a2ac1 204
emilmont 80:8e73be2a2ac1 205
emilmont 80:8e73be2a2ac1 206 /** \brief LDR Exclusive (32 bit)
emilmont 80:8e73be2a2ac1 207
emilmont 80:8e73be2a2ac1 208 This function performs a exclusive LDR command for 32 bit values.
emilmont 80:8e73be2a2ac1 209
emilmont 80:8e73be2a2ac1 210 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 211 \return value of type uint32_t at (*ptr)
emilmont 80:8e73be2a2ac1 212 */
emilmont 80:8e73be2a2ac1 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 80:8e73be2a2ac1 214
emilmont 80:8e73be2a2ac1 215
emilmont 80:8e73be2a2ac1 216 /** \brief STR Exclusive (8 bit)
emilmont 80:8e73be2a2ac1 217
emilmont 80:8e73be2a2ac1 218 This function performs a exclusive STR command for 8 bit values.
emilmont 80:8e73be2a2ac1 219
emilmont 80:8e73be2a2ac1 220 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 221 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 222 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 223 \return 1 Function failed
emilmont 80:8e73be2a2ac1 224 */
emilmont 80:8e73be2a2ac1 225 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 80:8e73be2a2ac1 226
emilmont 80:8e73be2a2ac1 227
emilmont 80:8e73be2a2ac1 228 /** \brief STR Exclusive (16 bit)
emilmont 80:8e73be2a2ac1 229
emilmont 80:8e73be2a2ac1 230 This function performs a exclusive STR command for 16 bit values.
emilmont 80:8e73be2a2ac1 231
emilmont 80:8e73be2a2ac1 232 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 233 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 234 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 235 \return 1 Function failed
emilmont 80:8e73be2a2ac1 236 */
emilmont 80:8e73be2a2ac1 237 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 80:8e73be2a2ac1 238
emilmont 80:8e73be2a2ac1 239
emilmont 80:8e73be2a2ac1 240 /** \brief STR Exclusive (32 bit)
emilmont 80:8e73be2a2ac1 241
emilmont 80:8e73be2a2ac1 242 This function performs a exclusive STR command for 32 bit values.
emilmont 80:8e73be2a2ac1 243
emilmont 80:8e73be2a2ac1 244 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 245 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 246 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 247 \return 1 Function failed
emilmont 80:8e73be2a2ac1 248 */
emilmont 80:8e73be2a2ac1 249 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 80:8e73be2a2ac1 250
emilmont 80:8e73be2a2ac1 251
emilmont 80:8e73be2a2ac1 252 /** \brief Remove the exclusive lock
emilmont 80:8e73be2a2ac1 253
emilmont 80:8e73be2a2ac1 254 This function removes the exclusive lock which is created by LDREX.
emilmont 80:8e73be2a2ac1 255
emilmont 80:8e73be2a2ac1 256 */
emilmont 80:8e73be2a2ac1 257 #define __CLREX __clrex
emilmont 80:8e73be2a2ac1 258
emilmont 80:8e73be2a2ac1 259
emilmont 80:8e73be2a2ac1 260 /** \brief Signed Saturate
emilmont 80:8e73be2a2ac1 261
emilmont 80:8e73be2a2ac1 262 This function saturates a signed value.
emilmont 80:8e73be2a2ac1 263
emilmont 80:8e73be2a2ac1 264 \param [in] value Value to be saturated
emilmont 80:8e73be2a2ac1 265 \param [in] sat Bit position to saturate to (1..32)
emilmont 80:8e73be2a2ac1 266 \return Saturated value
emilmont 80:8e73be2a2ac1 267 */
emilmont 80:8e73be2a2ac1 268 #define __SSAT __ssat
emilmont 80:8e73be2a2ac1 269
emilmont 80:8e73be2a2ac1 270
emilmont 80:8e73be2a2ac1 271 /** \brief Unsigned Saturate
emilmont 80:8e73be2a2ac1 272
emilmont 80:8e73be2a2ac1 273 This function saturates an unsigned value.
emilmont 80:8e73be2a2ac1 274
emilmont 80:8e73be2a2ac1 275 \param [in] value Value to be saturated
emilmont 80:8e73be2a2ac1 276 \param [in] sat Bit position to saturate to (0..31)
emilmont 80:8e73be2a2ac1 277 \return Saturated value
emilmont 80:8e73be2a2ac1 278 */
emilmont 80:8e73be2a2ac1 279 #define __USAT __usat
emilmont 80:8e73be2a2ac1 280
emilmont 80:8e73be2a2ac1 281
emilmont 80:8e73be2a2ac1 282 /** \brief Count leading zeros
emilmont 80:8e73be2a2ac1 283
emilmont 80:8e73be2a2ac1 284 This function counts the number of leading zeros of a data value.
emilmont 80:8e73be2a2ac1 285
emilmont 80:8e73be2a2ac1 286 \param [in] value Value to count the leading zeros
emilmont 80:8e73be2a2ac1 287 \return number of leading zeros in value
emilmont 80:8e73be2a2ac1 288 */
emilmont 80:8e73be2a2ac1 289 #define __CLZ __clz
emilmont 80:8e73be2a2ac1 290
emilmont 80:8e73be2a2ac1 291 #endif /* (__CORTEX_M >= 0x03) */
emilmont 80:8e73be2a2ac1 292
emilmont 80:8e73be2a2ac1 293
emilmont 80:8e73be2a2ac1 294
emilmont 80:8e73be2a2ac1 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 80:8e73be2a2ac1 296 /* IAR iccarm specific functions */
emilmont 80:8e73be2a2ac1 297
emilmont 80:8e73be2a2ac1 298 #include <cmsis_iar.h>
emilmont 80:8e73be2a2ac1 299
emilmont 80:8e73be2a2ac1 300
emilmont 80:8e73be2a2ac1 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 80:8e73be2a2ac1 302 /* TI CCS specific functions */
emilmont 80:8e73be2a2ac1 303
emilmont 80:8e73be2a2ac1 304 #include <cmsis_ccs.h>
emilmont 80:8e73be2a2ac1 305
emilmont 80:8e73be2a2ac1 306
emilmont 80:8e73be2a2ac1 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 80:8e73be2a2ac1 308 /* GNU gcc specific functions */
emilmont 80:8e73be2a2ac1 309
emilmont 80:8e73be2a2ac1 310 /* Define macros for porting to both thumb1 and thumb2.
emilmont 80:8e73be2a2ac1 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
emilmont 80:8e73be2a2ac1 312 * Otherwise, use general registers, specified by constrant "r" */
emilmont 80:8e73be2a2ac1 313 #if defined (__thumb__) && !defined (__thumb2__)
emilmont 80:8e73be2a2ac1 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
emilmont 80:8e73be2a2ac1 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
emilmont 80:8e73be2a2ac1 316 #else
emilmont 80:8e73be2a2ac1 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
emilmont 80:8e73be2a2ac1 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
emilmont 80:8e73be2a2ac1 319 #endif
emilmont 80:8e73be2a2ac1 320
emilmont 80:8e73be2a2ac1 321 /** \brief No Operation
emilmont 80:8e73be2a2ac1 322
emilmont 80:8e73be2a2ac1 323 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 80:8e73be2a2ac1 324 */
emilmont 80:8e73be2a2ac1 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
emilmont 80:8e73be2a2ac1 326 {
emilmont 80:8e73be2a2ac1 327 __ASM volatile ("nop");
emilmont 80:8e73be2a2ac1 328 }
emilmont 80:8e73be2a2ac1 329
emilmont 80:8e73be2a2ac1 330
emilmont 80:8e73be2a2ac1 331 /** \brief Wait For Interrupt
emilmont 80:8e73be2a2ac1 332
emilmont 80:8e73be2a2ac1 333 Wait For Interrupt is a hint instruction that suspends execution
emilmont 80:8e73be2a2ac1 334 until one of a number of events occurs.
emilmont 80:8e73be2a2ac1 335 */
emilmont 80:8e73be2a2ac1 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
emilmont 80:8e73be2a2ac1 337 {
emilmont 80:8e73be2a2ac1 338 __ASM volatile ("wfi");
emilmont 80:8e73be2a2ac1 339 }
emilmont 80:8e73be2a2ac1 340
emilmont 80:8e73be2a2ac1 341
emilmont 80:8e73be2a2ac1 342 /** \brief Wait For Event
emilmont 80:8e73be2a2ac1 343
emilmont 80:8e73be2a2ac1 344 Wait For Event is a hint instruction that permits the processor to enter
emilmont 80:8e73be2a2ac1 345 a low-power state until one of a number of events occurs.
emilmont 80:8e73be2a2ac1 346 */
emilmont 80:8e73be2a2ac1 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
emilmont 80:8e73be2a2ac1 348 {
emilmont 80:8e73be2a2ac1 349 __ASM volatile ("wfe");
emilmont 80:8e73be2a2ac1 350 }
emilmont 80:8e73be2a2ac1 351
emilmont 80:8e73be2a2ac1 352
emilmont 80:8e73be2a2ac1 353 /** \brief Send Event
emilmont 80:8e73be2a2ac1 354
emilmont 80:8e73be2a2ac1 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 80:8e73be2a2ac1 356 */
emilmont 80:8e73be2a2ac1 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
emilmont 80:8e73be2a2ac1 358 {
emilmont 80:8e73be2a2ac1 359 __ASM volatile ("sev");
emilmont 80:8e73be2a2ac1 360 }
emilmont 80:8e73be2a2ac1 361
emilmont 80:8e73be2a2ac1 362
emilmont 80:8e73be2a2ac1 363 /** \brief Instruction Synchronization Barrier
emilmont 80:8e73be2a2ac1 364
emilmont 80:8e73be2a2ac1 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 80:8e73be2a2ac1 366 so that all instructions following the ISB are fetched from cache or
emilmont 80:8e73be2a2ac1 367 memory, after the instruction has been completed.
emilmont 80:8e73be2a2ac1 368 */
emilmont 80:8e73be2a2ac1 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
emilmont 80:8e73be2a2ac1 370 {
emilmont 80:8e73be2a2ac1 371 __ASM volatile ("isb");
emilmont 80:8e73be2a2ac1 372 }
emilmont 80:8e73be2a2ac1 373
emilmont 80:8e73be2a2ac1 374
emilmont 80:8e73be2a2ac1 375 /** \brief Data Synchronization Barrier
emilmont 80:8e73be2a2ac1 376
emilmont 80:8e73be2a2ac1 377 This function acts as a special kind of Data Memory Barrier.
emilmont 80:8e73be2a2ac1 378 It completes when all explicit memory accesses before this instruction complete.
emilmont 80:8e73be2a2ac1 379 */
emilmont 80:8e73be2a2ac1 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
emilmont 80:8e73be2a2ac1 381 {
emilmont 80:8e73be2a2ac1 382 __ASM volatile ("dsb");
emilmont 80:8e73be2a2ac1 383 }
emilmont 80:8e73be2a2ac1 384
emilmont 80:8e73be2a2ac1 385
emilmont 80:8e73be2a2ac1 386 /** \brief Data Memory Barrier
emilmont 80:8e73be2a2ac1 387
emilmont 80:8e73be2a2ac1 388 This function ensures the apparent order of the explicit memory operations before
emilmont 80:8e73be2a2ac1 389 and after the instruction, without ensuring their completion.
emilmont 80:8e73be2a2ac1 390 */
emilmont 80:8e73be2a2ac1 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
emilmont 80:8e73be2a2ac1 392 {
emilmont 80:8e73be2a2ac1 393 __ASM volatile ("dmb");
emilmont 80:8e73be2a2ac1 394 }
emilmont 80:8e73be2a2ac1 395
emilmont 80:8e73be2a2ac1 396
emilmont 80:8e73be2a2ac1 397 /** \brief Reverse byte order (32 bit)
emilmont 80:8e73be2a2ac1 398
emilmont 80:8e73be2a2ac1 399 This function reverses the byte order in integer value.
emilmont 80:8e73be2a2ac1 400
emilmont 80:8e73be2a2ac1 401 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 402 \return Reversed value
emilmont 80:8e73be2a2ac1 403 */
emilmont 80:8e73be2a2ac1 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
emilmont 80:8e73be2a2ac1 405 {
emilmont 80:8e73be2a2ac1 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
emilmont 80:8e73be2a2ac1 407 return __builtin_bswap32(value);
emilmont 80:8e73be2a2ac1 408 #else
emilmont 80:8e73be2a2ac1 409 uint32_t result;
emilmont 80:8e73be2a2ac1 410
emilmont 80:8e73be2a2ac1 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 80:8e73be2a2ac1 412 return(result);
emilmont 80:8e73be2a2ac1 413 #endif
emilmont 80:8e73be2a2ac1 414 }
emilmont 80:8e73be2a2ac1 415
emilmont 80:8e73be2a2ac1 416
emilmont 80:8e73be2a2ac1 417 /** \brief Reverse byte order (16 bit)
emilmont 80:8e73be2a2ac1 418
emilmont 80:8e73be2a2ac1 419 This function reverses the byte order in two unsigned short values.
emilmont 80:8e73be2a2ac1 420
emilmont 80:8e73be2a2ac1 421 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 422 \return Reversed value
emilmont 80:8e73be2a2ac1 423 */
emilmont 80:8e73be2a2ac1 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
emilmont 80:8e73be2a2ac1 425 {
emilmont 80:8e73be2a2ac1 426 uint32_t result;
emilmont 80:8e73be2a2ac1 427
emilmont 80:8e73be2a2ac1 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 80:8e73be2a2ac1 429 return(result);
emilmont 80:8e73be2a2ac1 430 }
emilmont 80:8e73be2a2ac1 431
emilmont 80:8e73be2a2ac1 432
emilmont 80:8e73be2a2ac1 433 /** \brief Reverse byte order in signed short value
emilmont 80:8e73be2a2ac1 434
emilmont 80:8e73be2a2ac1 435 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 80:8e73be2a2ac1 436
emilmont 80:8e73be2a2ac1 437 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 438 \return Reversed value
emilmont 80:8e73be2a2ac1 439 */
emilmont 80:8e73be2a2ac1 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
emilmont 80:8e73be2a2ac1 441 {
emilmont 80:8e73be2a2ac1 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 80:8e73be2a2ac1 443 return (short)__builtin_bswap16(value);
emilmont 80:8e73be2a2ac1 444 #else
emilmont 80:8e73be2a2ac1 445 uint32_t result;
emilmont 80:8e73be2a2ac1 446
emilmont 80:8e73be2a2ac1 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 80:8e73be2a2ac1 448 return(result);
emilmont 80:8e73be2a2ac1 449 #endif
emilmont 80:8e73be2a2ac1 450 }
emilmont 80:8e73be2a2ac1 451
emilmont 80:8e73be2a2ac1 452
emilmont 80:8e73be2a2ac1 453 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 80:8e73be2a2ac1 454
emilmont 80:8e73be2a2ac1 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 80:8e73be2a2ac1 456
emilmont 80:8e73be2a2ac1 457 \param [in] value Value to rotate
emilmont 80:8e73be2a2ac1 458 \param [in] value Number of Bits to rotate
emilmont 80:8e73be2a2ac1 459 \return Rotated value
emilmont 80:8e73be2a2ac1 460 */
emilmont 80:8e73be2a2ac1 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
emilmont 80:8e73be2a2ac1 462 {
emilmont 80:8e73be2a2ac1 463 return (op1 >> op2) | (op1 << (32 - op2));
emilmont 80:8e73be2a2ac1 464 }
emilmont 80:8e73be2a2ac1 465
emilmont 80:8e73be2a2ac1 466
emilmont 80:8e73be2a2ac1 467 /** \brief Breakpoint
emilmont 80:8e73be2a2ac1 468
emilmont 80:8e73be2a2ac1 469 This function causes the processor to enter Debug state.
emilmont 80:8e73be2a2ac1 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 80:8e73be2a2ac1 471
emilmont 80:8e73be2a2ac1 472 \param [in] value is ignored by the processor.
emilmont 80:8e73be2a2ac1 473 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 80:8e73be2a2ac1 474 */
emilmont 80:8e73be2a2ac1 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
emilmont 80:8e73be2a2ac1 476
emilmont 80:8e73be2a2ac1 477
emilmont 80:8e73be2a2ac1 478 #if (__CORTEX_M >= 0x03)
emilmont 80:8e73be2a2ac1 479
emilmont 80:8e73be2a2ac1 480 /** \brief Reverse bit order of value
emilmont 80:8e73be2a2ac1 481
emilmont 80:8e73be2a2ac1 482 This function reverses the bit order of the given value.
emilmont 80:8e73be2a2ac1 483
emilmont 80:8e73be2a2ac1 484 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 485 \return Reversed value
emilmont 80:8e73be2a2ac1 486 */
emilmont 80:8e73be2a2ac1 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
emilmont 80:8e73be2a2ac1 488 {
emilmont 80:8e73be2a2ac1 489 uint32_t result;
emilmont 80:8e73be2a2ac1 490
emilmont 80:8e73be2a2ac1 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 80:8e73be2a2ac1 492 return(result);
emilmont 80:8e73be2a2ac1 493 }
emilmont 80:8e73be2a2ac1 494
emilmont 80:8e73be2a2ac1 495
emilmont 80:8e73be2a2ac1 496 /** \brief LDR Exclusive (8 bit)
emilmont 80:8e73be2a2ac1 497
emilmont 80:8e73be2a2ac1 498 This function performs a exclusive LDR command for 8 bit value.
emilmont 80:8e73be2a2ac1 499
emilmont 80:8e73be2a2ac1 500 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 501 \return value of type uint8_t at (*ptr)
emilmont 80:8e73be2a2ac1 502 */
emilmont 80:8e73be2a2ac1 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 80:8e73be2a2ac1 504 {
emilmont 80:8e73be2a2ac1 505 uint32_t result;
emilmont 80:8e73be2a2ac1 506
emilmont 80:8e73be2a2ac1 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 80:8e73be2a2ac1 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 80:8e73be2a2ac1 509 #else
emilmont 80:8e73be2a2ac1 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
emilmont 80:8e73be2a2ac1 511 accepted by assembler. So has to use following less efficient pattern.
emilmont 80:8e73be2a2ac1 512 */
emilmont 80:8e73be2a2ac1 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
emilmont 80:8e73be2a2ac1 514 #endif
emilmont 80:8e73be2a2ac1 515 return(result);
emilmont 80:8e73be2a2ac1 516 }
emilmont 80:8e73be2a2ac1 517
emilmont 80:8e73be2a2ac1 518
emilmont 80:8e73be2a2ac1 519 /** \brief LDR Exclusive (16 bit)
emilmont 80:8e73be2a2ac1 520
emilmont 80:8e73be2a2ac1 521 This function performs a exclusive LDR command for 16 bit values.
emilmont 80:8e73be2a2ac1 522
emilmont 80:8e73be2a2ac1 523 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 524 \return value of type uint16_t at (*ptr)
emilmont 80:8e73be2a2ac1 525 */
emilmont 80:8e73be2a2ac1 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 80:8e73be2a2ac1 527 {
emilmont 80:8e73be2a2ac1 528 uint32_t result;
emilmont 80:8e73be2a2ac1 529
emilmont 80:8e73be2a2ac1 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 80:8e73be2a2ac1 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 80:8e73be2a2ac1 532 #else
emilmont 80:8e73be2a2ac1 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
emilmont 80:8e73be2a2ac1 534 accepted by assembler. So has to use following less efficient pattern.
emilmont 80:8e73be2a2ac1 535 */
emilmont 80:8e73be2a2ac1 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
emilmont 80:8e73be2a2ac1 537 #endif
emilmont 80:8e73be2a2ac1 538 return(result);
emilmont 80:8e73be2a2ac1 539 }
emilmont 80:8e73be2a2ac1 540
emilmont 80:8e73be2a2ac1 541
emilmont 80:8e73be2a2ac1 542 /** \brief LDR Exclusive (32 bit)
emilmont 80:8e73be2a2ac1 543
emilmont 80:8e73be2a2ac1 544 This function performs a exclusive LDR command for 32 bit values.
emilmont 80:8e73be2a2ac1 545
emilmont 80:8e73be2a2ac1 546 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 547 \return value of type uint32_t at (*ptr)
emilmont 80:8e73be2a2ac1 548 */
emilmont 80:8e73be2a2ac1 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 80:8e73be2a2ac1 550 {
emilmont 80:8e73be2a2ac1 551 uint32_t result;
emilmont 80:8e73be2a2ac1 552
emilmont 80:8e73be2a2ac1 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 80:8e73be2a2ac1 554 return(result);
emilmont 80:8e73be2a2ac1 555 }
emilmont 80:8e73be2a2ac1 556
emilmont 80:8e73be2a2ac1 557
emilmont 80:8e73be2a2ac1 558 /** \brief STR Exclusive (8 bit)
emilmont 80:8e73be2a2ac1 559
emilmont 80:8e73be2a2ac1 560 This function performs a exclusive STR command for 8 bit values.
emilmont 80:8e73be2a2ac1 561
emilmont 80:8e73be2a2ac1 562 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 563 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 564 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 565 \return 1 Function failed
emilmont 80:8e73be2a2ac1 566 */
emilmont 80:8e73be2a2ac1 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 80:8e73be2a2ac1 568 {
emilmont 80:8e73be2a2ac1 569 uint32_t result;
emilmont 80:8e73be2a2ac1 570
emilmont 80:8e73be2a2ac1 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 80:8e73be2a2ac1 572 return(result);
emilmont 80:8e73be2a2ac1 573 }
emilmont 80:8e73be2a2ac1 574
emilmont 80:8e73be2a2ac1 575
emilmont 80:8e73be2a2ac1 576 /** \brief STR Exclusive (16 bit)
emilmont 80:8e73be2a2ac1 577
emilmont 80:8e73be2a2ac1 578 This function performs a exclusive STR command for 16 bit values.
emilmont 80:8e73be2a2ac1 579
emilmont 80:8e73be2a2ac1 580 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 581 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 582 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 583 \return 1 Function failed
emilmont 80:8e73be2a2ac1 584 */
emilmont 80:8e73be2a2ac1 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 80:8e73be2a2ac1 586 {
emilmont 80:8e73be2a2ac1 587 uint32_t result;
emilmont 80:8e73be2a2ac1 588
emilmont 80:8e73be2a2ac1 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 80:8e73be2a2ac1 590 return(result);
emilmont 80:8e73be2a2ac1 591 }
emilmont 80:8e73be2a2ac1 592
emilmont 80:8e73be2a2ac1 593
emilmont 80:8e73be2a2ac1 594 /** \brief STR Exclusive (32 bit)
emilmont 80:8e73be2a2ac1 595
emilmont 80:8e73be2a2ac1 596 This function performs a exclusive STR command for 32 bit values.
emilmont 80:8e73be2a2ac1 597
emilmont 80:8e73be2a2ac1 598 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 599 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 600 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 601 \return 1 Function failed
emilmont 80:8e73be2a2ac1 602 */
emilmont 80:8e73be2a2ac1 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 80:8e73be2a2ac1 604 {
emilmont 80:8e73be2a2ac1 605 uint32_t result;
emilmont 80:8e73be2a2ac1 606
emilmont 80:8e73be2a2ac1 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 80:8e73be2a2ac1 608 return(result);
emilmont 80:8e73be2a2ac1 609 }
emilmont 80:8e73be2a2ac1 610
emilmont 80:8e73be2a2ac1 611
emilmont 80:8e73be2a2ac1 612 /** \brief Remove the exclusive lock
emilmont 80:8e73be2a2ac1 613
emilmont 80:8e73be2a2ac1 614 This function removes the exclusive lock which is created by LDREX.
emilmont 80:8e73be2a2ac1 615
emilmont 80:8e73be2a2ac1 616 */
emilmont 80:8e73be2a2ac1 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
emilmont 80:8e73be2a2ac1 618 {
emilmont 80:8e73be2a2ac1 619 __ASM volatile ("clrex" ::: "memory");
emilmont 80:8e73be2a2ac1 620 }
emilmont 80:8e73be2a2ac1 621
emilmont 80:8e73be2a2ac1 622
emilmont 80:8e73be2a2ac1 623 /** \brief Signed Saturate
emilmont 80:8e73be2a2ac1 624
emilmont 80:8e73be2a2ac1 625 This function saturates a signed value.
emilmont 80:8e73be2a2ac1 626
emilmont 80:8e73be2a2ac1 627 \param [in] value Value to be saturated
emilmont 80:8e73be2a2ac1 628 \param [in] sat Bit position to saturate to (1..32)
emilmont 80:8e73be2a2ac1 629 \return Saturated value
emilmont 80:8e73be2a2ac1 630 */
emilmont 80:8e73be2a2ac1 631 #define __SSAT(ARG1,ARG2) \
emilmont 80:8e73be2a2ac1 632 ({ \
emilmont 80:8e73be2a2ac1 633 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 80:8e73be2a2ac1 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 80:8e73be2a2ac1 635 __RES; \
emilmont 80:8e73be2a2ac1 636 })
emilmont 80:8e73be2a2ac1 637
emilmont 80:8e73be2a2ac1 638
emilmont 80:8e73be2a2ac1 639 /** \brief Unsigned Saturate
emilmont 80:8e73be2a2ac1 640
emilmont 80:8e73be2a2ac1 641 This function saturates an unsigned value.
emilmont 80:8e73be2a2ac1 642
emilmont 80:8e73be2a2ac1 643 \param [in] value Value to be saturated
emilmont 80:8e73be2a2ac1 644 \param [in] sat Bit position to saturate to (0..31)
emilmont 80:8e73be2a2ac1 645 \return Saturated value
emilmont 80:8e73be2a2ac1 646 */
emilmont 80:8e73be2a2ac1 647 #define __USAT(ARG1,ARG2) \
emilmont 80:8e73be2a2ac1 648 ({ \
emilmont 80:8e73be2a2ac1 649 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 80:8e73be2a2ac1 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 80:8e73be2a2ac1 651 __RES; \
emilmont 80:8e73be2a2ac1 652 })
emilmont 80:8e73be2a2ac1 653
emilmont 80:8e73be2a2ac1 654
emilmont 80:8e73be2a2ac1 655 /** \brief Count leading zeros
emilmont 80:8e73be2a2ac1 656
emilmont 80:8e73be2a2ac1 657 This function counts the number of leading zeros of a data value.
emilmont 80:8e73be2a2ac1 658
emilmont 80:8e73be2a2ac1 659 \param [in] value Value to count the leading zeros
emilmont 80:8e73be2a2ac1 660 \return number of leading zeros in value
emilmont 80:8e73be2a2ac1 661 */
emilmont 80:8e73be2a2ac1 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
emilmont 80:8e73be2a2ac1 663 {
emilmont 80:8e73be2a2ac1 664 uint32_t result;
emilmont 80:8e73be2a2ac1 665
emilmont 80:8e73be2a2ac1 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 80:8e73be2a2ac1 667 return(result);
emilmont 80:8e73be2a2ac1 668 }
emilmont 80:8e73be2a2ac1 669
emilmont 80:8e73be2a2ac1 670 #endif /* (__CORTEX_M >= 0x03) */
emilmont 80:8e73be2a2ac1 671
emilmont 80:8e73be2a2ac1 672
emilmont 80:8e73be2a2ac1 673
emilmont 80:8e73be2a2ac1 674
emilmont 80:8e73be2a2ac1 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 80:8e73be2a2ac1 676 /* TASKING carm specific functions */
emilmont 80:8e73be2a2ac1 677
emilmont 80:8e73be2a2ac1 678 /*
emilmont 80:8e73be2a2ac1 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 80:8e73be2a2ac1 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 80:8e73be2a2ac1 681 * Including the CMSIS ones.
emilmont 80:8e73be2a2ac1 682 */
emilmont 80:8e73be2a2ac1 683
emilmont 80:8e73be2a2ac1 684 #endif
emilmont 80:8e73be2a2ac1 685
emilmont 80:8e73be2a2ac1 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 80:8e73be2a2ac1 687
emilmont 80:8e73be2a2ac1 688 #endif /* __CORE_CMINSTR_H */