frederic blanc
/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }
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TARGET_MTS_MDOT_F405RG/stm32f4xx_ll_sdmmc.h@93:9dd889aeda0e, 2014-12-05 (annotated)
- Committer:
- fblanc
- Date:
- Fri Dec 05 15:42:32 2014 +0000
- Revision:
- 93:9dd889aeda0e
- Parent:
- 92:4fc01daae5a5
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 92:4fc01daae5a5 | 1 | /** |
| bogdanm | 92:4fc01daae5a5 | 2 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 3 | * @file stm32f4xx_ll_sdmmc.h |
| bogdanm | 92:4fc01daae5a5 | 4 | * @author MCD Application Team |
| bogdanm | 92:4fc01daae5a5 | 5 | * @version V1.1.0 |
| bogdanm | 92:4fc01daae5a5 | 6 | * @date 19-June-2014 |
| bogdanm | 92:4fc01daae5a5 | 7 | * @brief Header file of SDMMC HAL module. |
| bogdanm | 92:4fc01daae5a5 | 8 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 9 | * @attention |
| bogdanm | 92:4fc01daae5a5 | 10 | * |
| bogdanm | 92:4fc01daae5a5 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 92:4fc01daae5a5 | 12 | * |
| bogdanm | 92:4fc01daae5a5 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 92:4fc01daae5a5 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 92:4fc01daae5a5 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 92:4fc01daae5a5 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 92:4fc01daae5a5 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 92:4fc01daae5a5 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 92:4fc01daae5a5 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 92:4fc01daae5a5 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 92:4fc01daae5a5 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 92:4fc01daae5a5 | 22 | * without specific prior written permission. |
| bogdanm | 92:4fc01daae5a5 | 23 | * |
| bogdanm | 92:4fc01daae5a5 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 92:4fc01daae5a5 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 92:4fc01daae5a5 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 92:4fc01daae5a5 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 92:4fc01daae5a5 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 92:4fc01daae5a5 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 92:4fc01daae5a5 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 92:4fc01daae5a5 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 92:4fc01daae5a5 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 92:4fc01daae5a5 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 92:4fc01daae5a5 | 34 | * |
| bogdanm | 92:4fc01daae5a5 | 35 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 36 | */ |
| bogdanm | 92:4fc01daae5a5 | 37 | |
| bogdanm | 92:4fc01daae5a5 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 39 | #ifndef __STM32F4xx_LL_SDMMC_H |
| bogdanm | 92:4fc01daae5a5 | 40 | #define __STM32F4xx_LL_SDMMC_H |
| bogdanm | 92:4fc01daae5a5 | 41 | |
| bogdanm | 92:4fc01daae5a5 | 42 | #ifdef __cplusplus |
| bogdanm | 92:4fc01daae5a5 | 43 | extern "C" { |
| bogdanm | 92:4fc01daae5a5 | 44 | #endif |
| bogdanm | 92:4fc01daae5a5 | 45 | |
| bogdanm | 92:4fc01daae5a5 | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 47 | #include "stm32f4xx_hal_def.h" |
| bogdanm | 92:4fc01daae5a5 | 48 | |
| bogdanm | 92:4fc01daae5a5 | 49 | /** @addtogroup STM32F4xx_Driver |
| bogdanm | 92:4fc01daae5a5 | 50 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 51 | */ |
| bogdanm | 92:4fc01daae5a5 | 52 | |
| bogdanm | 92:4fc01daae5a5 | 53 | /** @addtogroup SDMMC |
| bogdanm | 92:4fc01daae5a5 | 54 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 55 | */ |
| bogdanm | 92:4fc01daae5a5 | 56 | |
| bogdanm | 92:4fc01daae5a5 | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 58 | |
| bogdanm | 92:4fc01daae5a5 | 59 | /** @defgroup SDIO_Exported_Types SDIO Exported Types |
| bogdanm | 92:4fc01daae5a5 | 60 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 61 | */ |
| bogdanm | 92:4fc01daae5a5 | 62 | |
| bogdanm | 92:4fc01daae5a5 | 63 | /** |
| bogdanm | 92:4fc01daae5a5 | 64 | * @brief SDMMC Configuration Structure definition |
| bogdanm | 92:4fc01daae5a5 | 65 | */ |
| bogdanm | 92:4fc01daae5a5 | 66 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 67 | { |
| bogdanm | 92:4fc01daae5a5 | 68 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
| bogdanm | 92:4fc01daae5a5 | 69 | This parameter can be a value of @ref SDIO_Clock_Edge */ |
| bogdanm | 92:4fc01daae5a5 | 70 | |
| bogdanm | 92:4fc01daae5a5 | 71 | uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is |
| bogdanm | 92:4fc01daae5a5 | 72 | enabled or disabled. |
| bogdanm | 92:4fc01daae5a5 | 73 | This parameter can be a value of @ref SDIO_Clock_Bypass */ |
| bogdanm | 92:4fc01daae5a5 | 74 | |
| bogdanm | 92:4fc01daae5a5 | 75 | uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or |
| bogdanm | 92:4fc01daae5a5 | 76 | disabled when the bus is idle. |
| bogdanm | 92:4fc01daae5a5 | 77 | This parameter can be a value of @ref SDIO_Clock_Power_Save */ |
| bogdanm | 92:4fc01daae5a5 | 78 | |
| bogdanm | 92:4fc01daae5a5 | 79 | uint32_t BusWide; /*!< Specifies the SDIO bus width. |
| bogdanm | 92:4fc01daae5a5 | 80 | This parameter can be a value of @ref SDIO_Bus_Wide */ |
| bogdanm | 92:4fc01daae5a5 | 81 | |
| bogdanm | 92:4fc01daae5a5 | 82 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. |
| bogdanm | 92:4fc01daae5a5 | 83 | This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ |
| bogdanm | 92:4fc01daae5a5 | 84 | |
| bogdanm | 92:4fc01daae5a5 | 85 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. |
| bogdanm | 92:4fc01daae5a5 | 86 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 87 | |
| bogdanm | 92:4fc01daae5a5 | 88 | }SDIO_InitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 89 | |
| bogdanm | 92:4fc01daae5a5 | 90 | |
| bogdanm | 92:4fc01daae5a5 | 91 | /** |
| bogdanm | 92:4fc01daae5a5 | 92 | * @brief SDIO Command Control structure |
| bogdanm | 92:4fc01daae5a5 | 93 | */ |
| bogdanm | 92:4fc01daae5a5 | 94 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 95 | { |
| bogdanm | 92:4fc01daae5a5 | 96 | uint32_t Argument; /*!< Specifies the SDIO command argument which is sent |
| bogdanm | 92:4fc01daae5a5 | 97 | to a card as part of a command message. If a command |
| bogdanm | 92:4fc01daae5a5 | 98 | contains an argument, it must be loaded into this register |
| bogdanm | 92:4fc01daae5a5 | 99 | before writing the command to the command register. */ |
| bogdanm | 92:4fc01daae5a5 | 100 | |
| bogdanm | 92:4fc01daae5a5 | 101 | uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and |
| bogdanm | 92:4fc01daae5a5 | 102 | Max_Data = 64 */ |
| bogdanm | 92:4fc01daae5a5 | 103 | |
| bogdanm | 92:4fc01daae5a5 | 104 | uint32_t Response; /*!< Specifies the SDIO response type. |
| bogdanm | 92:4fc01daae5a5 | 105 | This parameter can be a value of @ref SDIO_Response_Type */ |
| bogdanm | 92:4fc01daae5a5 | 106 | |
| bogdanm | 92:4fc01daae5a5 | 107 | uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is |
| bogdanm | 92:4fc01daae5a5 | 108 | enabled or disabled. |
| bogdanm | 92:4fc01daae5a5 | 109 | This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ |
| bogdanm | 92:4fc01daae5a5 | 110 | |
| bogdanm | 92:4fc01daae5a5 | 111 | uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) |
| bogdanm | 92:4fc01daae5a5 | 112 | is enabled or disabled. |
| bogdanm | 92:4fc01daae5a5 | 113 | This parameter can be a value of @ref SDIO_CPSM_State */ |
| bogdanm | 92:4fc01daae5a5 | 114 | }SDIO_CmdInitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 115 | |
| bogdanm | 92:4fc01daae5a5 | 116 | |
| bogdanm | 92:4fc01daae5a5 | 117 | /** |
| bogdanm | 92:4fc01daae5a5 | 118 | * @brief SDIO Data Control structure |
| bogdanm | 92:4fc01daae5a5 | 119 | */ |
| bogdanm | 92:4fc01daae5a5 | 120 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 121 | { |
| bogdanm | 92:4fc01daae5a5 | 122 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
| bogdanm | 92:4fc01daae5a5 | 123 | |
| bogdanm | 92:4fc01daae5a5 | 124 | uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ |
| bogdanm | 92:4fc01daae5a5 | 125 | |
| bogdanm | 92:4fc01daae5a5 | 126 | uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. |
| bogdanm | 92:4fc01daae5a5 | 127 | This parameter can be a value of @ref SDIO_Data_Block_Size */ |
| bogdanm | 92:4fc01daae5a5 | 128 | |
| bogdanm | 92:4fc01daae5a5 | 129 | uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer |
| bogdanm | 92:4fc01daae5a5 | 130 | is a read or write. |
| bogdanm | 92:4fc01daae5a5 | 131 | This parameter can be a value of @ref SDIO_Transfer_Direction */ |
| bogdanm | 92:4fc01daae5a5 | 132 | |
| bogdanm | 92:4fc01daae5a5 | 133 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
| bogdanm | 92:4fc01daae5a5 | 134 | This parameter can be a value of @ref SDIO_Transfer_Type */ |
| bogdanm | 92:4fc01daae5a5 | 135 | |
| bogdanm | 92:4fc01daae5a5 | 136 | uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) |
| bogdanm | 92:4fc01daae5a5 | 137 | is enabled or disabled. |
| bogdanm | 92:4fc01daae5a5 | 138 | This parameter can be a value of @ref SDIO_DPSM_State */ |
| bogdanm | 92:4fc01daae5a5 | 139 | }SDIO_DataInitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 140 | |
| bogdanm | 92:4fc01daae5a5 | 141 | /** |
| bogdanm | 92:4fc01daae5a5 | 142 | * @} |
| bogdanm | 92:4fc01daae5a5 | 143 | */ |
| bogdanm | 92:4fc01daae5a5 | 144 | |
| bogdanm | 92:4fc01daae5a5 | 145 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 146 | |
| bogdanm | 92:4fc01daae5a5 | 147 | /** @defgroup SDIO_Exported_Constants |
| bogdanm | 92:4fc01daae5a5 | 148 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 149 | */ |
| bogdanm | 92:4fc01daae5a5 | 150 | |
| bogdanm | 92:4fc01daae5a5 | 151 | /** @defgroup SDIO_Clock_Edge |
| bogdanm | 92:4fc01daae5a5 | 152 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 153 | */ |
| bogdanm | 92:4fc01daae5a5 | 154 | #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 155 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
| bogdanm | 92:4fc01daae5a5 | 156 | |
| bogdanm | 92:4fc01daae5a5 | 157 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
| bogdanm | 92:4fc01daae5a5 | 158 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
| bogdanm | 92:4fc01daae5a5 | 159 | /** |
| bogdanm | 92:4fc01daae5a5 | 160 | * @} |
| bogdanm | 92:4fc01daae5a5 | 161 | */ |
| bogdanm | 92:4fc01daae5a5 | 162 | |
| bogdanm | 92:4fc01daae5a5 | 163 | /** @defgroup SDIO_Clock_Bypass |
| bogdanm | 92:4fc01daae5a5 | 164 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 165 | */ |
| bogdanm | 92:4fc01daae5a5 | 166 | #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 167 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
| bogdanm | 92:4fc01daae5a5 | 168 | |
| bogdanm | 92:4fc01daae5a5 | 169 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 170 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 171 | /** |
| bogdanm | 92:4fc01daae5a5 | 172 | * @} |
| bogdanm | 92:4fc01daae5a5 | 173 | */ |
| bogdanm | 92:4fc01daae5a5 | 174 | |
| bogdanm | 92:4fc01daae5a5 | 175 | /** @defgroup SDIO_Clock_Power_Save |
| bogdanm | 92:4fc01daae5a5 | 176 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 177 | */ |
| bogdanm | 92:4fc01daae5a5 | 178 | #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 179 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
| bogdanm | 92:4fc01daae5a5 | 180 | |
| bogdanm | 92:4fc01daae5a5 | 181 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 182 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 183 | /** |
| bogdanm | 92:4fc01daae5a5 | 184 | * @} |
| bogdanm | 92:4fc01daae5a5 | 185 | */ |
| bogdanm | 92:4fc01daae5a5 | 186 | |
| bogdanm | 92:4fc01daae5a5 | 187 | /** @defgroup SDIO_Bus_Wide |
| bogdanm | 92:4fc01daae5a5 | 188 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 189 | */ |
| bogdanm | 92:4fc01daae5a5 | 190 | #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 191 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
| bogdanm | 92:4fc01daae5a5 | 192 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
| bogdanm | 92:4fc01daae5a5 | 193 | |
| bogdanm | 92:4fc01daae5a5 | 194 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
| bogdanm | 92:4fc01daae5a5 | 195 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
| bogdanm | 92:4fc01daae5a5 | 196 | ((WIDE) == SDIO_BUS_WIDE_8B)) |
| bogdanm | 92:4fc01daae5a5 | 197 | /** |
| bogdanm | 92:4fc01daae5a5 | 198 | * @} |
| bogdanm | 92:4fc01daae5a5 | 199 | */ |
| bogdanm | 92:4fc01daae5a5 | 200 | |
| bogdanm | 92:4fc01daae5a5 | 201 | /** @defgroup SDIO_Hardware_Flow_Control |
| bogdanm | 92:4fc01daae5a5 | 202 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 203 | */ |
| bogdanm | 92:4fc01daae5a5 | 204 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 205 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
| bogdanm | 92:4fc01daae5a5 | 206 | |
| bogdanm | 92:4fc01daae5a5 | 207 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 208 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 209 | /** |
| bogdanm | 92:4fc01daae5a5 | 210 | * @} |
| bogdanm | 92:4fc01daae5a5 | 211 | */ |
| bogdanm | 92:4fc01daae5a5 | 212 | |
| bogdanm | 92:4fc01daae5a5 | 213 | /** @defgroup SDIO_Clock_Division |
| bogdanm | 92:4fc01daae5a5 | 214 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 215 | */ |
| bogdanm | 92:4fc01daae5a5 | 216 | #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) |
| bogdanm | 92:4fc01daae5a5 | 217 | /** |
| bogdanm | 92:4fc01daae5a5 | 218 | * @} |
| bogdanm | 92:4fc01daae5a5 | 219 | */ |
| bogdanm | 92:4fc01daae5a5 | 220 | |
| bogdanm | 92:4fc01daae5a5 | 221 | /** @defgroup SDIO_Command_Index |
| bogdanm | 92:4fc01daae5a5 | 222 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 223 | */ |
| bogdanm | 92:4fc01daae5a5 | 224 | #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) |
| bogdanm | 92:4fc01daae5a5 | 225 | /** |
| bogdanm | 92:4fc01daae5a5 | 226 | * @} |
| bogdanm | 92:4fc01daae5a5 | 227 | */ |
| bogdanm | 92:4fc01daae5a5 | 228 | |
| bogdanm | 92:4fc01daae5a5 | 229 | /** @defgroup SDIO_Response_Type |
| bogdanm | 92:4fc01daae5a5 | 230 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 231 | */ |
| bogdanm | 92:4fc01daae5a5 | 232 | #define SDIO_RESPONSE_NO ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 233 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
| bogdanm | 92:4fc01daae5a5 | 234 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
| bogdanm | 92:4fc01daae5a5 | 235 | |
| bogdanm | 92:4fc01daae5a5 | 236 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
| bogdanm | 92:4fc01daae5a5 | 237 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
| bogdanm | 92:4fc01daae5a5 | 238 | ((RESPONSE) == SDIO_RESPONSE_LONG)) |
| bogdanm | 92:4fc01daae5a5 | 239 | /** |
| bogdanm | 92:4fc01daae5a5 | 240 | * @} |
| bogdanm | 92:4fc01daae5a5 | 241 | */ |
| bogdanm | 92:4fc01daae5a5 | 242 | |
| bogdanm | 92:4fc01daae5a5 | 243 | /** @defgroup SDIO_Wait_Interrupt_State |
| bogdanm | 92:4fc01daae5a5 | 244 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 245 | */ |
| bogdanm | 92:4fc01daae5a5 | 246 | #define SDIO_WAIT_NO ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 247 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
| bogdanm | 92:4fc01daae5a5 | 248 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
| bogdanm | 92:4fc01daae5a5 | 249 | |
| bogdanm | 92:4fc01daae5a5 | 250 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
| bogdanm | 92:4fc01daae5a5 | 251 | ((WAIT) == SDIO_WAIT_IT) || \ |
| bogdanm | 92:4fc01daae5a5 | 252 | ((WAIT) == SDIO_WAIT_PEND)) |
| bogdanm | 92:4fc01daae5a5 | 253 | /** |
| bogdanm | 92:4fc01daae5a5 | 254 | * @} |
| bogdanm | 92:4fc01daae5a5 | 255 | */ |
| bogdanm | 92:4fc01daae5a5 | 256 | |
| bogdanm | 92:4fc01daae5a5 | 257 | /** @defgroup SDIO_CPSM_State |
| bogdanm | 92:4fc01daae5a5 | 258 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 259 | */ |
| bogdanm | 92:4fc01daae5a5 | 260 | #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 261 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
| bogdanm | 92:4fc01daae5a5 | 262 | |
| bogdanm | 92:4fc01daae5a5 | 263 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 264 | ((CPSM) == SDIO_CPSM_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 265 | /** |
| bogdanm | 92:4fc01daae5a5 | 266 | * @} |
| bogdanm | 92:4fc01daae5a5 | 267 | */ |
| bogdanm | 92:4fc01daae5a5 | 268 | |
| bogdanm | 92:4fc01daae5a5 | 269 | /** @defgroup SDIO_Response_Registers |
| bogdanm | 92:4fc01daae5a5 | 270 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 271 | */ |
| bogdanm | 92:4fc01daae5a5 | 272 | #define SDIO_RESP1 ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 273 | #define SDIO_RESP2 ((uint32_t)0x00000004) |
| bogdanm | 92:4fc01daae5a5 | 274 | #define SDIO_RESP3 ((uint32_t)0x00000008) |
| bogdanm | 92:4fc01daae5a5 | 275 | #define SDIO_RESP4 ((uint32_t)0x0000000C) |
| bogdanm | 92:4fc01daae5a5 | 276 | |
| bogdanm | 92:4fc01daae5a5 | 277 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
| bogdanm | 92:4fc01daae5a5 | 278 | ((RESP) == SDIO_RESP2) || \ |
| bogdanm | 92:4fc01daae5a5 | 279 | ((RESP) == SDIO_RESP3) || \ |
| bogdanm | 92:4fc01daae5a5 | 280 | ((RESP) == SDIO_RESP4)) |
| bogdanm | 92:4fc01daae5a5 | 281 | /** |
| bogdanm | 92:4fc01daae5a5 | 282 | * @} |
| bogdanm | 92:4fc01daae5a5 | 283 | */ |
| bogdanm | 92:4fc01daae5a5 | 284 | |
| bogdanm | 92:4fc01daae5a5 | 285 | /** @defgroup SDIO_Data_Length |
| bogdanm | 92:4fc01daae5a5 | 286 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 287 | */ |
| bogdanm | 92:4fc01daae5a5 | 288 | #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) |
| bogdanm | 92:4fc01daae5a5 | 289 | /** |
| bogdanm | 92:4fc01daae5a5 | 290 | * @} |
| bogdanm | 92:4fc01daae5a5 | 291 | */ |
| bogdanm | 92:4fc01daae5a5 | 292 | |
| bogdanm | 92:4fc01daae5a5 | 293 | /** @defgroup SDIO_Data_Block_Size |
| bogdanm | 92:4fc01daae5a5 | 294 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 295 | */ |
| bogdanm | 92:4fc01daae5a5 | 296 | #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 297 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
| bogdanm | 92:4fc01daae5a5 | 298 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
| bogdanm | 92:4fc01daae5a5 | 299 | #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030) |
| bogdanm | 92:4fc01daae5a5 | 300 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
| bogdanm | 92:4fc01daae5a5 | 301 | #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050) |
| bogdanm | 92:4fc01daae5a5 | 302 | #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060) |
| bogdanm | 92:4fc01daae5a5 | 303 | #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070) |
| bogdanm | 92:4fc01daae5a5 | 304 | #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 |
| bogdanm | 92:4fc01daae5a5 | 305 | #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090) |
| bogdanm | 92:4fc01daae5a5 | 306 | #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0) |
| bogdanm | 92:4fc01daae5a5 | 307 | #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0) |
| bogdanm | 92:4fc01daae5a5 | 308 | #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0) |
| bogdanm | 92:4fc01daae5a5 | 309 | #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0) |
| bogdanm | 92:4fc01daae5a5 | 310 | #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0) |
| bogdanm | 92:4fc01daae5a5 | 311 | |
| bogdanm | 92:4fc01daae5a5 | 312 | #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ |
| bogdanm | 92:4fc01daae5a5 | 313 | ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ |
| bogdanm | 92:4fc01daae5a5 | 314 | ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ |
| bogdanm | 92:4fc01daae5a5 | 315 | ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ |
| bogdanm | 92:4fc01daae5a5 | 316 | ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ |
| bogdanm | 92:4fc01daae5a5 | 317 | ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ |
| bogdanm | 92:4fc01daae5a5 | 318 | ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ |
| bogdanm | 92:4fc01daae5a5 | 319 | ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ |
| bogdanm | 92:4fc01daae5a5 | 320 | ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ |
| bogdanm | 92:4fc01daae5a5 | 321 | ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ |
| bogdanm | 92:4fc01daae5a5 | 322 | ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ |
| bogdanm | 92:4fc01daae5a5 | 323 | ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ |
| bogdanm | 92:4fc01daae5a5 | 324 | ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ |
| bogdanm | 92:4fc01daae5a5 | 325 | ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ |
| bogdanm | 92:4fc01daae5a5 | 326 | ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) |
| bogdanm | 92:4fc01daae5a5 | 327 | /** |
| bogdanm | 92:4fc01daae5a5 | 328 | * @} |
| bogdanm | 92:4fc01daae5a5 | 329 | */ |
| bogdanm | 92:4fc01daae5a5 | 330 | |
| bogdanm | 92:4fc01daae5a5 | 331 | /** @defgroup SDIO_Transfer_Direction |
| bogdanm | 92:4fc01daae5a5 | 332 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 333 | */ |
| bogdanm | 92:4fc01daae5a5 | 334 | #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 335 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
| bogdanm | 92:4fc01daae5a5 | 336 | |
| bogdanm | 92:4fc01daae5a5 | 337 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
| bogdanm | 92:4fc01daae5a5 | 338 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
| bogdanm | 92:4fc01daae5a5 | 339 | /** |
| bogdanm | 92:4fc01daae5a5 | 340 | * @} |
| bogdanm | 92:4fc01daae5a5 | 341 | */ |
| bogdanm | 92:4fc01daae5a5 | 342 | |
| bogdanm | 92:4fc01daae5a5 | 343 | /** @defgroup SDIO_Transfer_Type |
| bogdanm | 92:4fc01daae5a5 | 344 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 345 | */ |
| bogdanm | 92:4fc01daae5a5 | 346 | #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 347 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
| bogdanm | 92:4fc01daae5a5 | 348 | |
| bogdanm | 92:4fc01daae5a5 | 349 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
| bogdanm | 92:4fc01daae5a5 | 350 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
| bogdanm | 92:4fc01daae5a5 | 351 | /** |
| bogdanm | 92:4fc01daae5a5 | 352 | * @} |
| bogdanm | 92:4fc01daae5a5 | 353 | */ |
| bogdanm | 92:4fc01daae5a5 | 354 | |
| bogdanm | 92:4fc01daae5a5 | 355 | /** @defgroup SDIO_DPSM_State |
| bogdanm | 92:4fc01daae5a5 | 356 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 357 | */ |
| bogdanm | 92:4fc01daae5a5 | 358 | #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 359 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
| bogdanm | 92:4fc01daae5a5 | 360 | |
| bogdanm | 92:4fc01daae5a5 | 361 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
| bogdanm | 92:4fc01daae5a5 | 362 | ((DPSM) == SDIO_DPSM_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 363 | /** |
| bogdanm | 92:4fc01daae5a5 | 364 | * @} |
| bogdanm | 92:4fc01daae5a5 | 365 | */ |
| bogdanm | 92:4fc01daae5a5 | 366 | |
| bogdanm | 92:4fc01daae5a5 | 367 | /** @defgroup SDIO_Read_Wait_Mode |
| bogdanm | 92:4fc01daae5a5 | 368 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 369 | */ |
| bogdanm | 92:4fc01daae5a5 | 370 | #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 371 | #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001) |
| bogdanm | 92:4fc01daae5a5 | 372 | |
| bogdanm | 92:4fc01daae5a5 | 373 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
| bogdanm | 92:4fc01daae5a5 | 374 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
| bogdanm | 92:4fc01daae5a5 | 375 | /** |
| bogdanm | 92:4fc01daae5a5 | 376 | * @} |
| bogdanm | 92:4fc01daae5a5 | 377 | */ |
| bogdanm | 92:4fc01daae5a5 | 378 | |
| bogdanm | 92:4fc01daae5a5 | 379 | /** @defgroup SDIO_Interrupt_sources |
| bogdanm | 92:4fc01daae5a5 | 380 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 381 | */ |
| bogdanm | 92:4fc01daae5a5 | 382 | #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL |
| bogdanm | 92:4fc01daae5a5 | 383 | #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL |
| bogdanm | 92:4fc01daae5a5 | 384 | #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT |
| bogdanm | 92:4fc01daae5a5 | 385 | #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT |
| bogdanm | 92:4fc01daae5a5 | 386 | #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR |
| bogdanm | 92:4fc01daae5a5 | 387 | #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR |
| bogdanm | 92:4fc01daae5a5 | 388 | #define SDIO_IT_CMDREND SDIO_STA_CMDREND |
| bogdanm | 92:4fc01daae5a5 | 389 | #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT |
| bogdanm | 92:4fc01daae5a5 | 390 | #define SDIO_IT_DATAEND SDIO_STA_DATAEND |
| bogdanm | 92:4fc01daae5a5 | 391 | #define SDIO_IT_STBITERR SDIO_STA_STBITERR |
| bogdanm | 92:4fc01daae5a5 | 392 | #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND |
| bogdanm | 92:4fc01daae5a5 | 393 | #define SDIO_IT_CMDACT SDIO_STA_CMDACT |
| bogdanm | 92:4fc01daae5a5 | 394 | #define SDIO_IT_TXACT SDIO_STA_TXACT |
| bogdanm | 92:4fc01daae5a5 | 395 | #define SDIO_IT_RXACT SDIO_STA_RXACT |
| bogdanm | 92:4fc01daae5a5 | 396 | #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE |
| bogdanm | 92:4fc01daae5a5 | 397 | #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF |
| bogdanm | 92:4fc01daae5a5 | 398 | #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF |
| bogdanm | 92:4fc01daae5a5 | 399 | #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF |
| bogdanm | 92:4fc01daae5a5 | 400 | #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE |
| bogdanm | 92:4fc01daae5a5 | 401 | #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE |
| bogdanm | 92:4fc01daae5a5 | 402 | #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL |
| bogdanm | 92:4fc01daae5a5 | 403 | #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL |
| bogdanm | 92:4fc01daae5a5 | 404 | #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT |
| bogdanm | 92:4fc01daae5a5 | 405 | #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND |
| bogdanm | 92:4fc01daae5a5 | 406 | |
| bogdanm | 92:4fc01daae5a5 | 407 | #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) |
| bogdanm | 92:4fc01daae5a5 | 408 | /** |
| bogdanm | 92:4fc01daae5a5 | 409 | * @} |
| bogdanm | 92:4fc01daae5a5 | 410 | */ |
| bogdanm | 92:4fc01daae5a5 | 411 | |
| bogdanm | 92:4fc01daae5a5 | 412 | /** @defgroup SDIO_Flags |
| bogdanm | 92:4fc01daae5a5 | 413 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 414 | */ |
| bogdanm | 92:4fc01daae5a5 | 415 | #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL |
| bogdanm | 92:4fc01daae5a5 | 416 | #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL |
| bogdanm | 92:4fc01daae5a5 | 417 | #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT |
| bogdanm | 92:4fc01daae5a5 | 418 | #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT |
| bogdanm | 92:4fc01daae5a5 | 419 | #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR |
| bogdanm | 92:4fc01daae5a5 | 420 | #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR |
| bogdanm | 92:4fc01daae5a5 | 421 | #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND |
| bogdanm | 92:4fc01daae5a5 | 422 | #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT |
| bogdanm | 92:4fc01daae5a5 | 423 | #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND |
| bogdanm | 92:4fc01daae5a5 | 424 | #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR |
| bogdanm | 92:4fc01daae5a5 | 425 | #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND |
| bogdanm | 92:4fc01daae5a5 | 426 | #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT |
| bogdanm | 92:4fc01daae5a5 | 427 | #define SDIO_FLAG_TXACT SDIO_STA_TXACT |
| bogdanm | 92:4fc01daae5a5 | 428 | #define SDIO_FLAG_RXACT SDIO_STA_RXACT |
| bogdanm | 92:4fc01daae5a5 | 429 | #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE |
| bogdanm | 92:4fc01daae5a5 | 430 | #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF |
| bogdanm | 92:4fc01daae5a5 | 431 | #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF |
| bogdanm | 92:4fc01daae5a5 | 432 | #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF |
| bogdanm | 92:4fc01daae5a5 | 433 | #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE |
| bogdanm | 92:4fc01daae5a5 | 434 | #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE |
| bogdanm | 92:4fc01daae5a5 | 435 | #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL |
| bogdanm | 92:4fc01daae5a5 | 436 | #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL |
| bogdanm | 92:4fc01daae5a5 | 437 | #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT |
| bogdanm | 92:4fc01daae5a5 | 438 | #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND |
| bogdanm | 92:4fc01daae5a5 | 439 | |
| bogdanm | 92:4fc01daae5a5 | 440 | #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ |
| bogdanm | 92:4fc01daae5a5 | 441 | ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ |
| bogdanm | 92:4fc01daae5a5 | 442 | ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ |
| bogdanm | 92:4fc01daae5a5 | 443 | ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ |
| bogdanm | 92:4fc01daae5a5 | 444 | ((FLAG) == SDIO_FLAG_TXUNDERR) || \ |
| bogdanm | 92:4fc01daae5a5 | 445 | ((FLAG) == SDIO_FLAG_RXOVERR) || \ |
| bogdanm | 92:4fc01daae5a5 | 446 | ((FLAG) == SDIO_FLAG_CMDREND) || \ |
| bogdanm | 92:4fc01daae5a5 | 447 | ((FLAG) == SDIO_FLAG_CMDSENT) || \ |
| bogdanm | 92:4fc01daae5a5 | 448 | ((FLAG) == SDIO_FLAG_DATAEND) || \ |
| bogdanm | 92:4fc01daae5a5 | 449 | ((FLAG) == SDIO_FLAG_STBITERR) || \ |
| bogdanm | 92:4fc01daae5a5 | 450 | ((FLAG) == SDIO_FLAG_DBCKEND) || \ |
| bogdanm | 92:4fc01daae5a5 | 451 | ((FLAG) == SDIO_FLAG_CMDACT) || \ |
| bogdanm | 92:4fc01daae5a5 | 452 | ((FLAG) == SDIO_FLAG_TXACT) || \ |
| bogdanm | 92:4fc01daae5a5 | 453 | ((FLAG) == SDIO_FLAG_RXACT) || \ |
| bogdanm | 92:4fc01daae5a5 | 454 | ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ |
| bogdanm | 92:4fc01daae5a5 | 455 | ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ |
| bogdanm | 92:4fc01daae5a5 | 456 | ((FLAG) == SDIO_FLAG_TXFIFOF) || \ |
| bogdanm | 92:4fc01daae5a5 | 457 | ((FLAG) == SDIO_FLAG_RXFIFOF) || \ |
| bogdanm | 92:4fc01daae5a5 | 458 | ((FLAG) == SDIO_FLAG_TXFIFOE) || \ |
| bogdanm | 92:4fc01daae5a5 | 459 | ((FLAG) == SDIO_FLAG_RXFIFOE) || \ |
| bogdanm | 92:4fc01daae5a5 | 460 | ((FLAG) == SDIO_FLAG_TXDAVL) || \ |
| bogdanm | 92:4fc01daae5a5 | 461 | ((FLAG) == SDIO_FLAG_RXDAVL) || \ |
| bogdanm | 92:4fc01daae5a5 | 462 | ((FLAG) == SDIO_FLAG_SDIOIT) || \ |
| bogdanm | 92:4fc01daae5a5 | 463 | ((FLAG) == SDIO_FLAG_CEATAEND)) |
| bogdanm | 92:4fc01daae5a5 | 464 | |
| bogdanm | 92:4fc01daae5a5 | 465 | #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) |
| bogdanm | 92:4fc01daae5a5 | 466 | |
| bogdanm | 92:4fc01daae5a5 | 467 | #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ |
| bogdanm | 92:4fc01daae5a5 | 468 | ((IT) == SDIO_IT_DCRCFAIL) || \ |
| bogdanm | 92:4fc01daae5a5 | 469 | ((IT) == SDIO_IT_CTIMEOUT) || \ |
| bogdanm | 92:4fc01daae5a5 | 470 | ((IT) == SDIO_IT_DTIMEOUT) || \ |
| bogdanm | 92:4fc01daae5a5 | 471 | ((IT) == SDIO_IT_TXUNDERR) || \ |
| bogdanm | 92:4fc01daae5a5 | 472 | ((IT) == SDIO_IT_RXOVERR) || \ |
| bogdanm | 92:4fc01daae5a5 | 473 | ((IT) == SDIO_IT_CMDREND) || \ |
| bogdanm | 92:4fc01daae5a5 | 474 | ((IT) == SDIO_IT_CMDSENT) || \ |
| bogdanm | 92:4fc01daae5a5 | 475 | ((IT) == SDIO_IT_DATAEND) || \ |
| bogdanm | 92:4fc01daae5a5 | 476 | ((IT) == SDIO_IT_STBITERR) || \ |
| bogdanm | 92:4fc01daae5a5 | 477 | ((IT) == SDIO_IT_DBCKEND) || \ |
| bogdanm | 92:4fc01daae5a5 | 478 | ((IT) == SDIO_IT_CMDACT) || \ |
| bogdanm | 92:4fc01daae5a5 | 479 | ((IT) == SDIO_IT_TXACT) || \ |
| bogdanm | 92:4fc01daae5a5 | 480 | ((IT) == SDIO_IT_RXACT) || \ |
| bogdanm | 92:4fc01daae5a5 | 481 | ((IT) == SDIO_IT_TXFIFOHE) || \ |
| bogdanm | 92:4fc01daae5a5 | 482 | ((IT) == SDIO_IT_RXFIFOHF) || \ |
| bogdanm | 92:4fc01daae5a5 | 483 | ((IT) == SDIO_IT_TXFIFOF) || \ |
| bogdanm | 92:4fc01daae5a5 | 484 | ((IT) == SDIO_IT_RXFIFOF) || \ |
| bogdanm | 92:4fc01daae5a5 | 485 | ((IT) == SDIO_IT_TXFIFOE) || \ |
| bogdanm | 92:4fc01daae5a5 | 486 | ((IT) == SDIO_IT_RXFIFOE) || \ |
| bogdanm | 92:4fc01daae5a5 | 487 | ((IT) == SDIO_IT_TXDAVL) || \ |
| bogdanm | 92:4fc01daae5a5 | 488 | ((IT) == SDIO_IT_RXDAVL) || \ |
| bogdanm | 92:4fc01daae5a5 | 489 | ((IT) == SDIO_IT_SDIOIT) || \ |
| bogdanm | 92:4fc01daae5a5 | 490 | ((IT) == SDIO_IT_CEATAEND)) |
| bogdanm | 92:4fc01daae5a5 | 491 | |
| bogdanm | 92:4fc01daae5a5 | 492 | #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) |
| bogdanm | 92:4fc01daae5a5 | 493 | |
| bogdanm | 92:4fc01daae5a5 | 494 | /** |
| bogdanm | 92:4fc01daae5a5 | 495 | * @} |
| bogdanm | 92:4fc01daae5a5 | 496 | */ |
| bogdanm | 92:4fc01daae5a5 | 497 | |
| bogdanm | 92:4fc01daae5a5 | 498 | |
| bogdanm | 92:4fc01daae5a5 | 499 | /** @defgroup SDIO_Instance_definition |
| bogdanm | 92:4fc01daae5a5 | 500 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 501 | */ |
| bogdanm | 92:4fc01daae5a5 | 502 | #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) |
| bogdanm | 92:4fc01daae5a5 | 503 | |
| bogdanm | 92:4fc01daae5a5 | 504 | /** |
| bogdanm | 92:4fc01daae5a5 | 505 | * @} |
| bogdanm | 92:4fc01daae5a5 | 506 | */ |
| bogdanm | 92:4fc01daae5a5 | 507 | |
| bogdanm | 92:4fc01daae5a5 | 508 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 509 | /* ------------ SDIO registers bit address in the alias region -------------- */ |
| bogdanm | 92:4fc01daae5a5 | 510 | #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) |
| bogdanm | 92:4fc01daae5a5 | 511 | |
| bogdanm | 92:4fc01daae5a5 | 512 | /* --- CLKCR Register ---*/ |
| bogdanm | 92:4fc01daae5a5 | 513 | /* Alias word address of CLKEN bit */ |
| bogdanm | 92:4fc01daae5a5 | 514 | #define CLKCR_OFFSET (SDIO_OFFSET + 0x04) |
| bogdanm | 92:4fc01daae5a5 | 515 | #define CLKEN_BitNumber 0x08 |
| bogdanm | 92:4fc01daae5a5 | 516 | #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 517 | |
| bogdanm | 92:4fc01daae5a5 | 518 | /* --- CMD Register ---*/ |
| bogdanm | 92:4fc01daae5a5 | 519 | /* Alias word address of SDIOSUSPEND bit */ |
| bogdanm | 92:4fc01daae5a5 | 520 | #define CMD_OFFSET (SDIO_OFFSET + 0x0C) |
| bogdanm | 92:4fc01daae5a5 | 521 | #define SDIOSUSPEND_BitNumber 0x0B |
| bogdanm | 92:4fc01daae5a5 | 522 | #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 523 | |
| bogdanm | 92:4fc01daae5a5 | 524 | /* Alias word address of ENCMDCOMPL bit */ |
| bogdanm | 92:4fc01daae5a5 | 525 | #define ENCMDCOMPL_BitNumber 0x0C |
| bogdanm | 92:4fc01daae5a5 | 526 | #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 527 | |
| bogdanm | 92:4fc01daae5a5 | 528 | /* Alias word address of NIEN bit */ |
| bogdanm | 92:4fc01daae5a5 | 529 | #define NIEN_BitNumber 0x0D |
| bogdanm | 92:4fc01daae5a5 | 530 | #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 531 | |
| bogdanm | 92:4fc01daae5a5 | 532 | /* Alias word address of ATACMD bit */ |
| bogdanm | 92:4fc01daae5a5 | 533 | #define ATACMD_BitNumber 0x0E |
| bogdanm | 92:4fc01daae5a5 | 534 | #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 535 | |
| bogdanm | 92:4fc01daae5a5 | 536 | /* --- DCTRL Register ---*/ |
| bogdanm | 92:4fc01daae5a5 | 537 | /* Alias word address of DMAEN bit */ |
| bogdanm | 92:4fc01daae5a5 | 538 | #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) |
| bogdanm | 92:4fc01daae5a5 | 539 | #define DMAEN_BitNumber 0x03 |
| bogdanm | 92:4fc01daae5a5 | 540 | #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 541 | |
| bogdanm | 92:4fc01daae5a5 | 542 | /* Alias word address of RWSTART bit */ |
| bogdanm | 92:4fc01daae5a5 | 543 | #define RWSTART_BitNumber 0x08 |
| bogdanm | 92:4fc01daae5a5 | 544 | #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 545 | |
| bogdanm | 92:4fc01daae5a5 | 546 | /* Alias word address of RWSTOP bit */ |
| bogdanm | 92:4fc01daae5a5 | 547 | #define RWSTOP_BitNumber 0x09 |
| bogdanm | 92:4fc01daae5a5 | 548 | #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 549 | |
| bogdanm | 92:4fc01daae5a5 | 550 | /* Alias word address of RWMOD bit */ |
| bogdanm | 92:4fc01daae5a5 | 551 | #define RWMOD_BitNumber 0x0A |
| bogdanm | 92:4fc01daae5a5 | 552 | #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 553 | |
| bogdanm | 92:4fc01daae5a5 | 554 | /* Alias word address of SDIOEN bit */ |
| bogdanm | 92:4fc01daae5a5 | 555 | #define SDIOEN_BitNumber 0x0B |
| bogdanm | 92:4fc01daae5a5 | 556 | #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) |
| bogdanm | 92:4fc01daae5a5 | 557 | |
| bogdanm | 92:4fc01daae5a5 | 558 | /* ---------------------- SDIO registers bit mask --------------------------- */ |
| bogdanm | 92:4fc01daae5a5 | 559 | /* --- CLKCR Register ---*/ |
| bogdanm | 92:4fc01daae5a5 | 560 | /* CLKCR register clear mask */ |
| bogdanm | 92:4fc01daae5a5 | 561 | #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ |
| bogdanm | 92:4fc01daae5a5 | 562 | SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ |
| bogdanm | 92:4fc01daae5a5 | 563 | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) |
| bogdanm | 92:4fc01daae5a5 | 564 | |
| bogdanm | 92:4fc01daae5a5 | 565 | /* --- PWRCTRL Register ---*/ |
| bogdanm | 92:4fc01daae5a5 | 566 | /* --- DCTRL Register ---*/ |
| bogdanm | 92:4fc01daae5a5 | 567 | /* SDIO DCTRL Clear Mask */ |
| bogdanm | 92:4fc01daae5a5 | 568 | #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ |
| bogdanm | 92:4fc01daae5a5 | 569 | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) |
| bogdanm | 92:4fc01daae5a5 | 570 | |
| bogdanm | 92:4fc01daae5a5 | 571 | /* --- CMD Register ---*/ |
| bogdanm | 92:4fc01daae5a5 | 572 | /* CMD Register clear mask */ |
| bogdanm | 92:4fc01daae5a5 | 573 | #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ |
| bogdanm | 92:4fc01daae5a5 | 574 | SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ |
| bogdanm | 92:4fc01daae5a5 | 575 | SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) |
| bogdanm | 92:4fc01daae5a5 | 576 | |
| bogdanm | 92:4fc01daae5a5 | 577 | /* SDIO RESP Registers Address */ |
| bogdanm | 92:4fc01daae5a5 | 578 | #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) |
| bogdanm | 92:4fc01daae5a5 | 579 | |
| bogdanm | 92:4fc01daae5a5 | 580 | /* SDIO Intialization Frequency (400KHz max) */ |
| bogdanm | 92:4fc01daae5a5 | 581 | #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) |
| bogdanm | 92:4fc01daae5a5 | 582 | |
| bogdanm | 92:4fc01daae5a5 | 583 | /* SDIO Data Transfer Frequency (25MHz max) */ |
| bogdanm | 92:4fc01daae5a5 | 584 | #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) |
| bogdanm | 92:4fc01daae5a5 | 585 | |
| bogdanm | 92:4fc01daae5a5 | 586 | /** @defgroup SDIO_Interrupt_Clock |
| bogdanm | 92:4fc01daae5a5 | 587 | * @brief macros to handle interrupts and specific clock configurations |
| bogdanm | 92:4fc01daae5a5 | 588 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 589 | */ |
| bogdanm | 92:4fc01daae5a5 | 590 | |
| bogdanm | 92:4fc01daae5a5 | 591 | /** |
| bogdanm | 92:4fc01daae5a5 | 592 | * @brief Enable the SDIO device. |
| bogdanm | 92:4fc01daae5a5 | 593 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 594 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 595 | */ |
| bogdanm | 92:4fc01daae5a5 | 596 | #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) |
| bogdanm | 92:4fc01daae5a5 | 597 | |
| bogdanm | 92:4fc01daae5a5 | 598 | /** |
| bogdanm | 92:4fc01daae5a5 | 599 | * @brief Disable the SDIO device. |
| bogdanm | 92:4fc01daae5a5 | 600 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 601 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 602 | */ |
| bogdanm | 92:4fc01daae5a5 | 603 | #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) |
| bogdanm | 92:4fc01daae5a5 | 604 | |
| bogdanm | 92:4fc01daae5a5 | 605 | /** |
| bogdanm | 92:4fc01daae5a5 | 606 | * @brief Enable the SDIO DMA transfer. |
| bogdanm | 92:4fc01daae5a5 | 607 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 608 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 609 | */ |
| bogdanm | 92:4fc01daae5a5 | 610 | #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) |
| bogdanm | 92:4fc01daae5a5 | 611 | |
| bogdanm | 92:4fc01daae5a5 | 612 | /** |
| bogdanm | 92:4fc01daae5a5 | 613 | * @brief Disable the SDIO DMA transfer. |
| bogdanm | 92:4fc01daae5a5 | 614 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 615 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 616 | */ |
| bogdanm | 92:4fc01daae5a5 | 617 | #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) |
| bogdanm | 92:4fc01daae5a5 | 618 | |
| bogdanm | 92:4fc01daae5a5 | 619 | /** |
| bogdanm | 92:4fc01daae5a5 | 620 | * @brief Enable the SDIO device interrupt. |
| bogdanm | 92:4fc01daae5a5 | 621 | * @param __INSTANCE__ : Pointer to SDIO register base |
| bogdanm | 92:4fc01daae5a5 | 622 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. |
| bogdanm | 92:4fc01daae5a5 | 623 | * This parameter can be one or a combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 624 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 625 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 626 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| bogdanm | 92:4fc01daae5a5 | 627 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| bogdanm | 92:4fc01daae5a5 | 628 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| bogdanm | 92:4fc01daae5a5 | 629 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| bogdanm | 92:4fc01daae5a5 | 630 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 631 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| bogdanm | 92:4fc01daae5a5 | 632 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| bogdanm | 92:4fc01daae5a5 | 633 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| bogdanm | 92:4fc01daae5a5 | 634 | * bus mode interrupt |
| bogdanm | 92:4fc01daae5a5 | 635 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 636 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 637 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 638 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 639 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 640 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| bogdanm | 92:4fc01daae5a5 | 641 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| bogdanm | 92:4fc01daae5a5 | 642 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| bogdanm | 92:4fc01daae5a5 | 643 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 644 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 645 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| bogdanm | 92:4fc01daae5a5 | 646 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| bogdanm | 92:4fc01daae5a5 | 647 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| bogdanm | 92:4fc01daae5a5 | 648 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| bogdanm | 92:4fc01daae5a5 | 649 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 650 | */ |
| bogdanm | 92:4fc01daae5a5 | 651 | #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
| bogdanm | 92:4fc01daae5a5 | 652 | |
| bogdanm | 92:4fc01daae5a5 | 653 | /** |
| bogdanm | 92:4fc01daae5a5 | 654 | * @brief Disable the SDIO device interrupt. |
| bogdanm | 92:4fc01daae5a5 | 655 | * @param __INSTANCE__ : Pointer to SDIO register base |
| bogdanm | 92:4fc01daae5a5 | 656 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. |
| bogdanm | 92:4fc01daae5a5 | 657 | * This parameter can be one or a combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 658 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 659 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 660 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| bogdanm | 92:4fc01daae5a5 | 661 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| bogdanm | 92:4fc01daae5a5 | 662 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| bogdanm | 92:4fc01daae5a5 | 663 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| bogdanm | 92:4fc01daae5a5 | 664 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 665 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| bogdanm | 92:4fc01daae5a5 | 666 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| bogdanm | 92:4fc01daae5a5 | 667 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| bogdanm | 92:4fc01daae5a5 | 668 | * bus mode interrupt |
| bogdanm | 92:4fc01daae5a5 | 669 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 670 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 671 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 672 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 673 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 674 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| bogdanm | 92:4fc01daae5a5 | 675 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| bogdanm | 92:4fc01daae5a5 | 676 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| bogdanm | 92:4fc01daae5a5 | 677 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 678 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 679 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| bogdanm | 92:4fc01daae5a5 | 680 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| bogdanm | 92:4fc01daae5a5 | 681 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| bogdanm | 92:4fc01daae5a5 | 682 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| bogdanm | 92:4fc01daae5a5 | 683 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 684 | */ |
| bogdanm | 92:4fc01daae5a5 | 685 | #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
| bogdanm | 92:4fc01daae5a5 | 686 | |
| bogdanm | 92:4fc01daae5a5 | 687 | /** |
| bogdanm | 92:4fc01daae5a5 | 688 | * @brief Checks whether the specified SDIO flag is set or not. |
| bogdanm | 92:4fc01daae5a5 | 689 | * @param __INSTANCE__ : Pointer to SDIO register base |
| bogdanm | 92:4fc01daae5a5 | 690 | * @param __FLAG__: specifies the flag to check. |
| bogdanm | 92:4fc01daae5a5 | 691 | * This parameter can be one of the following values: |
| bogdanm | 92:4fc01daae5a5 | 692 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
| bogdanm | 92:4fc01daae5a5 | 693 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
| bogdanm | 92:4fc01daae5a5 | 694 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
| bogdanm | 92:4fc01daae5a5 | 695 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
| bogdanm | 92:4fc01daae5a5 | 696 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
| bogdanm | 92:4fc01daae5a5 | 697 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
| bogdanm | 92:4fc01daae5a5 | 698 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
| bogdanm | 92:4fc01daae5a5 | 699 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
| bogdanm | 92:4fc01daae5a5 | 700 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| bogdanm | 92:4fc01daae5a5 | 701 | * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. |
| bogdanm | 92:4fc01daae5a5 | 702 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| bogdanm | 92:4fc01daae5a5 | 703 | * @arg SDIO_FLAG_CMDACT: Command transfer in progress |
| bogdanm | 92:4fc01daae5a5 | 704 | * @arg SDIO_FLAG_TXACT: Data transmit in progress |
| bogdanm | 92:4fc01daae5a5 | 705 | * @arg SDIO_FLAG_RXACT: Data receive in progress |
| bogdanm | 92:4fc01daae5a5 | 706 | * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
| bogdanm | 92:4fc01daae5a5 | 707 | * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
| bogdanm | 92:4fc01daae5a5 | 708 | * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
| bogdanm | 92:4fc01daae5a5 | 709 | * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
| bogdanm | 92:4fc01daae5a5 | 710 | * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
| bogdanm | 92:4fc01daae5a5 | 711 | * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
| bogdanm | 92:4fc01daae5a5 | 712 | * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
| bogdanm | 92:4fc01daae5a5 | 713 | * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
| bogdanm | 92:4fc01daae5a5 | 714 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
| bogdanm | 92:4fc01daae5a5 | 715 | * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
| bogdanm | 92:4fc01daae5a5 | 716 | * @retval The new state of SDIO_FLAG (SET or RESET). |
| bogdanm | 92:4fc01daae5a5 | 717 | */ |
| bogdanm | 92:4fc01daae5a5 | 718 | #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) |
| bogdanm | 92:4fc01daae5a5 | 719 | |
| bogdanm | 92:4fc01daae5a5 | 720 | |
| bogdanm | 92:4fc01daae5a5 | 721 | /** |
| bogdanm | 92:4fc01daae5a5 | 722 | * @brief Clears the SDIO pending flags. |
| bogdanm | 92:4fc01daae5a5 | 723 | * @param __INSTANCE__ : Pointer to SDIO register base |
| bogdanm | 92:4fc01daae5a5 | 724 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 92:4fc01daae5a5 | 725 | * This parameter can be one or a combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 726 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
| bogdanm | 92:4fc01daae5a5 | 727 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
| bogdanm | 92:4fc01daae5a5 | 728 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
| bogdanm | 92:4fc01daae5a5 | 729 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
| bogdanm | 92:4fc01daae5a5 | 730 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
| bogdanm | 92:4fc01daae5a5 | 731 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
| bogdanm | 92:4fc01daae5a5 | 732 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
| bogdanm | 92:4fc01daae5a5 | 733 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
| bogdanm | 92:4fc01daae5a5 | 734 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| bogdanm | 92:4fc01daae5a5 | 735 | * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode |
| bogdanm | 92:4fc01daae5a5 | 736 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| bogdanm | 92:4fc01daae5a5 | 737 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
| bogdanm | 92:4fc01daae5a5 | 738 | * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
| bogdanm | 92:4fc01daae5a5 | 739 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 740 | */ |
| bogdanm | 92:4fc01daae5a5 | 741 | #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
| bogdanm | 92:4fc01daae5a5 | 742 | |
| bogdanm | 92:4fc01daae5a5 | 743 | /** |
| bogdanm | 92:4fc01daae5a5 | 744 | * @brief Checks whether the specified SDIO interrupt has occurred or not. |
| bogdanm | 92:4fc01daae5a5 | 745 | * @param __INSTANCE__ : Pointer to SDIO register base |
| bogdanm | 92:4fc01daae5a5 | 746 | * @param __INTERRUPT__: specifies the SDIO interrupt source to check. |
| bogdanm | 92:4fc01daae5a5 | 747 | * This parameter can be one of the following values: |
| bogdanm | 92:4fc01daae5a5 | 748 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 749 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 750 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| bogdanm | 92:4fc01daae5a5 | 751 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| bogdanm | 92:4fc01daae5a5 | 752 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| bogdanm | 92:4fc01daae5a5 | 753 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| bogdanm | 92:4fc01daae5a5 | 754 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 755 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| bogdanm | 92:4fc01daae5a5 | 756 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| bogdanm | 92:4fc01daae5a5 | 757 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| bogdanm | 92:4fc01daae5a5 | 758 | * bus mode interrupt |
| bogdanm | 92:4fc01daae5a5 | 759 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 760 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 761 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 762 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| bogdanm | 92:4fc01daae5a5 | 763 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 764 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| bogdanm | 92:4fc01daae5a5 | 765 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| bogdanm | 92:4fc01daae5a5 | 766 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| bogdanm | 92:4fc01daae5a5 | 767 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 768 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| bogdanm | 92:4fc01daae5a5 | 769 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| bogdanm | 92:4fc01daae5a5 | 770 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| bogdanm | 92:4fc01daae5a5 | 771 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| bogdanm | 92:4fc01daae5a5 | 772 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| bogdanm | 92:4fc01daae5a5 | 773 | * @retval The new state of SDIO_IT (SET or RESET). |
| bogdanm | 92:4fc01daae5a5 | 774 | */ |
| bogdanm | 92:4fc01daae5a5 | 775 | #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
| bogdanm | 92:4fc01daae5a5 | 776 | |
| bogdanm | 92:4fc01daae5a5 | 777 | /** |
| bogdanm | 92:4fc01daae5a5 | 778 | * @brief Clears the SDIO's interrupt pending bits. |
| bogdanm | 92:4fc01daae5a5 | 779 | * @param __INSTANCE__ : Pointer to SDIO register base |
| bogdanm | 92:4fc01daae5a5 | 780 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
| bogdanm | 92:4fc01daae5a5 | 781 | * This parameter can be one or a combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 782 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 783 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 784 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| bogdanm | 92:4fc01daae5a5 | 785 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| bogdanm | 92:4fc01daae5a5 | 786 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| bogdanm | 92:4fc01daae5a5 | 787 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| bogdanm | 92:4fc01daae5a5 | 788 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| bogdanm | 92:4fc01daae5a5 | 789 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| bogdanm | 92:4fc01daae5a5 | 790 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt |
| bogdanm | 92:4fc01daae5a5 | 791 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| bogdanm | 92:4fc01daae5a5 | 792 | * bus mode interrupt |
| bogdanm | 92:4fc01daae5a5 | 793 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| bogdanm | 92:4fc01daae5a5 | 794 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 |
| bogdanm | 92:4fc01daae5a5 | 795 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 796 | */ |
| bogdanm | 92:4fc01daae5a5 | 797 | #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
| bogdanm | 92:4fc01daae5a5 | 798 | |
| bogdanm | 92:4fc01daae5a5 | 799 | /** |
| bogdanm | 92:4fc01daae5a5 | 800 | * @brief Enable Start the SD I/O Read Wait operation. |
| bogdanm | 92:4fc01daae5a5 | 801 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 802 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 803 | */ |
| bogdanm | 92:4fc01daae5a5 | 804 | #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) |
| bogdanm | 92:4fc01daae5a5 | 805 | |
| bogdanm | 92:4fc01daae5a5 | 806 | /** |
| bogdanm | 92:4fc01daae5a5 | 807 | * @brief Disable Start the SD I/O Read Wait operations. |
| bogdanm | 92:4fc01daae5a5 | 808 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 809 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 810 | */ |
| bogdanm | 92:4fc01daae5a5 | 811 | #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) |
| bogdanm | 92:4fc01daae5a5 | 812 | |
| bogdanm | 92:4fc01daae5a5 | 813 | /** |
| bogdanm | 92:4fc01daae5a5 | 814 | * @brief Enable Start the SD I/O Read Wait operation. |
| bogdanm | 92:4fc01daae5a5 | 815 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 816 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 817 | */ |
| bogdanm | 92:4fc01daae5a5 | 818 | #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) |
| bogdanm | 92:4fc01daae5a5 | 819 | |
| bogdanm | 92:4fc01daae5a5 | 820 | /** |
| bogdanm | 92:4fc01daae5a5 | 821 | * @brief Disable Stop the SD I/O Read Wait operations. |
| bogdanm | 92:4fc01daae5a5 | 822 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 823 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 824 | */ |
| bogdanm | 92:4fc01daae5a5 | 825 | #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) |
| bogdanm | 92:4fc01daae5a5 | 826 | |
| bogdanm | 92:4fc01daae5a5 | 827 | /** |
| bogdanm | 92:4fc01daae5a5 | 828 | * @brief Enable the SD I/O Mode Operation. |
| bogdanm | 92:4fc01daae5a5 | 829 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 830 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 831 | */ |
| bogdanm | 92:4fc01daae5a5 | 832 | #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) |
| bogdanm | 92:4fc01daae5a5 | 833 | |
| bogdanm | 92:4fc01daae5a5 | 834 | /** |
| bogdanm | 92:4fc01daae5a5 | 835 | * @brief Disable the SD I/O Mode Operation. |
| bogdanm | 92:4fc01daae5a5 | 836 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 837 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 838 | */ |
| bogdanm | 92:4fc01daae5a5 | 839 | #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) |
| bogdanm | 92:4fc01daae5a5 | 840 | |
| bogdanm | 92:4fc01daae5a5 | 841 | /** |
| bogdanm | 92:4fc01daae5a5 | 842 | * @brief Enable the SD I/O Suspend command sending. |
| bogdanm | 92:4fc01daae5a5 | 843 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 844 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 845 | */ |
| bogdanm | 92:4fc01daae5a5 | 846 | #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) |
| bogdanm | 92:4fc01daae5a5 | 847 | |
| bogdanm | 92:4fc01daae5a5 | 848 | /** |
| bogdanm | 92:4fc01daae5a5 | 849 | * @brief Disable the SD I/O Suspend command sending. |
| bogdanm | 92:4fc01daae5a5 | 850 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 851 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 852 | */ |
| bogdanm | 92:4fc01daae5a5 | 853 | #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) |
| bogdanm | 92:4fc01daae5a5 | 854 | |
| bogdanm | 92:4fc01daae5a5 | 855 | /** |
| bogdanm | 92:4fc01daae5a5 | 856 | * @brief Enable the command completion signal. |
| bogdanm | 92:4fc01daae5a5 | 857 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 858 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 859 | */ |
| bogdanm | 92:4fc01daae5a5 | 860 | #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) |
| bogdanm | 92:4fc01daae5a5 | 861 | |
| bogdanm | 92:4fc01daae5a5 | 862 | /** |
| bogdanm | 92:4fc01daae5a5 | 863 | * @brief Disable the command completion signal. |
| bogdanm | 92:4fc01daae5a5 | 864 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 865 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 866 | */ |
| bogdanm | 92:4fc01daae5a5 | 867 | #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) |
| bogdanm | 92:4fc01daae5a5 | 868 | |
| bogdanm | 92:4fc01daae5a5 | 869 | /** |
| bogdanm | 92:4fc01daae5a5 | 870 | * @brief Enable the CE-ATA interrupt. |
| bogdanm | 92:4fc01daae5a5 | 871 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 872 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 873 | */ |
| bogdanm | 92:4fc01daae5a5 | 874 | #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0) |
| bogdanm | 92:4fc01daae5a5 | 875 | |
| bogdanm | 92:4fc01daae5a5 | 876 | /** |
| bogdanm | 92:4fc01daae5a5 | 877 | * @brief Disable the CE-ATA interrupt. |
| bogdanm | 92:4fc01daae5a5 | 878 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 879 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 880 | */ |
| bogdanm | 92:4fc01daae5a5 | 881 | #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1) |
| bogdanm | 92:4fc01daae5a5 | 882 | |
| bogdanm | 92:4fc01daae5a5 | 883 | /** |
| bogdanm | 92:4fc01daae5a5 | 884 | * @brief Enable send CE-ATA command (CMD61). |
| bogdanm | 92:4fc01daae5a5 | 885 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 886 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 887 | */ |
| bogdanm | 92:4fc01daae5a5 | 888 | #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) |
| bogdanm | 92:4fc01daae5a5 | 889 | |
| bogdanm | 92:4fc01daae5a5 | 890 | /** |
| bogdanm | 92:4fc01daae5a5 | 891 | * @brief Disable send CE-ATA command (CMD61). |
| bogdanm | 92:4fc01daae5a5 | 892 | * @param None |
| bogdanm | 92:4fc01daae5a5 | 893 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 894 | */ |
| bogdanm | 92:4fc01daae5a5 | 895 | #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) |
| bogdanm | 92:4fc01daae5a5 | 896 | |
| bogdanm | 92:4fc01daae5a5 | 897 | /** |
| bogdanm | 92:4fc01daae5a5 | 898 | * @} |
| bogdanm | 92:4fc01daae5a5 | 899 | */ |
| bogdanm | 92:4fc01daae5a5 | 900 | |
| bogdanm | 92:4fc01daae5a5 | 901 | /** |
| bogdanm | 92:4fc01daae5a5 | 902 | * @} |
| bogdanm | 92:4fc01daae5a5 | 903 | */ |
| bogdanm | 92:4fc01daae5a5 | 904 | |
| bogdanm | 92:4fc01daae5a5 | 905 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 906 | /** @addtogroup SDIO_Exported_Functions |
| bogdanm | 92:4fc01daae5a5 | 907 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 908 | */ |
| bogdanm | 92:4fc01daae5a5 | 909 | |
| bogdanm | 92:4fc01daae5a5 | 910 | /* Initialization/de-initialization functions **********************************/ |
| bogdanm | 92:4fc01daae5a5 | 911 | /** @addtogroup HAL_SDIO_Group1 |
| bogdanm | 92:4fc01daae5a5 | 912 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 913 | */ |
| bogdanm | 92:4fc01daae5a5 | 914 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); |
| bogdanm | 92:4fc01daae5a5 | 915 | /** |
| bogdanm | 92:4fc01daae5a5 | 916 | * @} |
| bogdanm | 92:4fc01daae5a5 | 917 | */ |
| bogdanm | 92:4fc01daae5a5 | 918 | |
| bogdanm | 92:4fc01daae5a5 | 919 | /* I/O operation functions *****************************************************/ |
| bogdanm | 92:4fc01daae5a5 | 920 | /** @addtogroup HAL_SDIO_Group2 |
| bogdanm | 92:4fc01daae5a5 | 921 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 922 | */ |
| bogdanm | 92:4fc01daae5a5 | 923 | /* Blocking mode: Polling */ |
| bogdanm | 92:4fc01daae5a5 | 924 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); |
| bogdanm | 92:4fc01daae5a5 | 925 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); |
| bogdanm | 92:4fc01daae5a5 | 926 | /** |
| bogdanm | 92:4fc01daae5a5 | 927 | * @} |
| bogdanm | 92:4fc01daae5a5 | 928 | */ |
| bogdanm | 92:4fc01daae5a5 | 929 | |
| bogdanm | 92:4fc01daae5a5 | 930 | /* Peripheral Control functions ************************************************/ |
| bogdanm | 92:4fc01daae5a5 | 931 | /** @addtogroup HAL_SDIO_Group3 |
| bogdanm | 92:4fc01daae5a5 | 932 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 933 | */ |
| bogdanm | 92:4fc01daae5a5 | 934 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); |
| bogdanm | 92:4fc01daae5a5 | 935 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); |
| bogdanm | 92:4fc01daae5a5 | 936 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); |
| bogdanm | 92:4fc01daae5a5 | 937 | |
| bogdanm | 92:4fc01daae5a5 | 938 | /* Command path state machine (CPSM) management functions */ |
| bogdanm | 92:4fc01daae5a5 | 939 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); |
| bogdanm | 92:4fc01daae5a5 | 940 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); |
| bogdanm | 92:4fc01daae5a5 | 941 | uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); |
| bogdanm | 92:4fc01daae5a5 | 942 | |
| bogdanm | 92:4fc01daae5a5 | 943 | /* Data path state machine (DPSM) management functions */ |
| bogdanm | 92:4fc01daae5a5 | 944 | HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct); |
| bogdanm | 92:4fc01daae5a5 | 945 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); |
| bogdanm | 92:4fc01daae5a5 | 946 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); |
| bogdanm | 92:4fc01daae5a5 | 947 | |
| bogdanm | 92:4fc01daae5a5 | 948 | /* SDIO IO Cards mode management functions */ |
| bogdanm | 92:4fc01daae5a5 | 949 | HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); |
| bogdanm | 92:4fc01daae5a5 | 950 | |
| bogdanm | 92:4fc01daae5a5 | 951 | /** |
| bogdanm | 92:4fc01daae5a5 | 952 | * @} |
| bogdanm | 92:4fc01daae5a5 | 953 | */ |
| bogdanm | 92:4fc01daae5a5 | 954 | |
| bogdanm | 92:4fc01daae5a5 | 955 | /** |
| bogdanm | 92:4fc01daae5a5 | 956 | * @} |
| bogdanm | 92:4fc01daae5a5 | 957 | */ |
| bogdanm | 92:4fc01daae5a5 | 958 | |
| bogdanm | 92:4fc01daae5a5 | 959 | /** |
| bogdanm | 92:4fc01daae5a5 | 960 | * @} |
| bogdanm | 92:4fc01daae5a5 | 961 | */ |
| bogdanm | 92:4fc01daae5a5 | 962 | |
| bogdanm | 92:4fc01daae5a5 | 963 | /** |
| bogdanm | 92:4fc01daae5a5 | 964 | * @} |
| bogdanm | 92:4fc01daae5a5 | 965 | */ |
| bogdanm | 92:4fc01daae5a5 | 966 | |
| bogdanm | 92:4fc01daae5a5 | 967 | #ifdef __cplusplus |
| bogdanm | 92:4fc01daae5a5 | 968 | } |
| bogdanm | 92:4fc01daae5a5 | 969 | #endif |
| bogdanm | 92:4fc01daae5a5 | 970 | |
| bogdanm | 92:4fc01daae5a5 | 971 | #endif /* __STM32F4xx_LL_SDMMC_H */ |
| bogdanm | 92:4fc01daae5a5 | 972 | |
| bogdanm | 92:4fc01daae5a5 | 973 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |