frederic blanc
/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }
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TARGET_MTS_MDOT_F405RG/stm32f4xx_ll_fsmc.h@93:9dd889aeda0e, 2014-12-05 (annotated)
- Committer:
- fblanc
- Date:
- Fri Dec 05 15:42:32 2014 +0000
- Revision:
- 93:9dd889aeda0e
- Parent:
- 92:4fc01daae5a5
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 92:4fc01daae5a5 | 1 | /** |
| bogdanm | 92:4fc01daae5a5 | 2 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 3 | * @file stm32f4xx_ll_fsmc.h |
| bogdanm | 92:4fc01daae5a5 | 4 | * @author MCD Application Team |
| bogdanm | 92:4fc01daae5a5 | 5 | * @version V1.1.0 |
| bogdanm | 92:4fc01daae5a5 | 6 | * @date 19-June-2014 |
| bogdanm | 92:4fc01daae5a5 | 7 | * @brief Header file of FSMC HAL module. |
| bogdanm | 92:4fc01daae5a5 | 8 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 9 | * @attention |
| bogdanm | 92:4fc01daae5a5 | 10 | * |
| bogdanm | 92:4fc01daae5a5 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 92:4fc01daae5a5 | 12 | * |
| bogdanm | 92:4fc01daae5a5 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 92:4fc01daae5a5 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 92:4fc01daae5a5 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 92:4fc01daae5a5 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 92:4fc01daae5a5 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 92:4fc01daae5a5 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 92:4fc01daae5a5 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 92:4fc01daae5a5 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 92:4fc01daae5a5 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 92:4fc01daae5a5 | 22 | * without specific prior written permission. |
| bogdanm | 92:4fc01daae5a5 | 23 | * |
| bogdanm | 92:4fc01daae5a5 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 92:4fc01daae5a5 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 92:4fc01daae5a5 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 92:4fc01daae5a5 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 92:4fc01daae5a5 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 92:4fc01daae5a5 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 92:4fc01daae5a5 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 92:4fc01daae5a5 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 92:4fc01daae5a5 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 92:4fc01daae5a5 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 92:4fc01daae5a5 | 34 | * |
| bogdanm | 92:4fc01daae5a5 | 35 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 36 | */ |
| bogdanm | 92:4fc01daae5a5 | 37 | |
| bogdanm | 92:4fc01daae5a5 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 39 | #ifndef __STM32F4xx_LL_FSMC_H |
| bogdanm | 92:4fc01daae5a5 | 40 | #define __STM32F4xx_LL_FSMC_H |
| bogdanm | 92:4fc01daae5a5 | 41 | |
| bogdanm | 92:4fc01daae5a5 | 42 | #ifdef __cplusplus |
| bogdanm | 92:4fc01daae5a5 | 43 | extern "C" { |
| bogdanm | 92:4fc01daae5a5 | 44 | #endif |
| bogdanm | 92:4fc01daae5a5 | 45 | |
| bogdanm | 92:4fc01daae5a5 | 46 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| bogdanm | 92:4fc01daae5a5 | 47 | |
| bogdanm | 92:4fc01daae5a5 | 48 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 49 | #include "stm32f4xx_hal_def.h" |
| bogdanm | 92:4fc01daae5a5 | 50 | |
| bogdanm | 92:4fc01daae5a5 | 51 | /** @addtogroup STM32F4xx_HAL_Driver |
| bogdanm | 92:4fc01daae5a5 | 52 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 53 | */ |
| bogdanm | 92:4fc01daae5a5 | 54 | |
| bogdanm | 92:4fc01daae5a5 | 55 | /** @addtogroup FSMC |
| bogdanm | 92:4fc01daae5a5 | 56 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 57 | */ |
| bogdanm | 92:4fc01daae5a5 | 58 | |
| bogdanm | 92:4fc01daae5a5 | 59 | /* Exported typedef ----------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 60 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 61 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 62 | #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 63 | #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 64 | |
| bogdanm | 92:4fc01daae5a5 | 65 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| bogdanm | 92:4fc01daae5a5 | 66 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| bogdanm | 92:4fc01daae5a5 | 67 | #define FSMC_NAND_DEVICE FSMC_Bank2_3 |
| bogdanm | 92:4fc01daae5a5 | 68 | #define FSMC_PCCARD_DEVICE FSMC_Bank4 |
| bogdanm | 92:4fc01daae5a5 | 69 | |
| bogdanm | 92:4fc01daae5a5 | 70 | /** |
| bogdanm | 92:4fc01daae5a5 | 71 | * @brief FSMC_NORSRAM Configuration Structure definition |
| bogdanm | 92:4fc01daae5a5 | 72 | */ |
| bogdanm | 92:4fc01daae5a5 | 73 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 74 | { |
| bogdanm | 92:4fc01daae5a5 | 75 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| bogdanm | 92:4fc01daae5a5 | 76 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| bogdanm | 92:4fc01daae5a5 | 77 | |
| bogdanm | 92:4fc01daae5a5 | 78 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| bogdanm | 92:4fc01daae5a5 | 79 | multiplexed on the data bus or not. |
| bogdanm | 92:4fc01daae5a5 | 80 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| bogdanm | 92:4fc01daae5a5 | 81 | |
| bogdanm | 92:4fc01daae5a5 | 82 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| bogdanm | 92:4fc01daae5a5 | 83 | the corresponding memory device. |
| bogdanm | 92:4fc01daae5a5 | 84 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| bogdanm | 92:4fc01daae5a5 | 85 | |
| bogdanm | 92:4fc01daae5a5 | 86 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| bogdanm | 92:4fc01daae5a5 | 87 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| bogdanm | 92:4fc01daae5a5 | 88 | |
| bogdanm | 92:4fc01daae5a5 | 89 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| bogdanm | 92:4fc01daae5a5 | 90 | valid only with synchronous burst Flash memories. |
| bogdanm | 92:4fc01daae5a5 | 91 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| bogdanm | 92:4fc01daae5a5 | 92 | |
| bogdanm | 92:4fc01daae5a5 | 93 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| bogdanm | 92:4fc01daae5a5 | 94 | the Flash memory in burst mode. |
| bogdanm | 92:4fc01daae5a5 | 95 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| bogdanm | 92:4fc01daae5a5 | 96 | |
| bogdanm | 92:4fc01daae5a5 | 97 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| bogdanm | 92:4fc01daae5a5 | 98 | memory, valid only when accessing Flash memories in burst mode. |
| bogdanm | 92:4fc01daae5a5 | 99 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| bogdanm | 92:4fc01daae5a5 | 100 | |
| bogdanm | 92:4fc01daae5a5 | 101 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| bogdanm | 92:4fc01daae5a5 | 102 | clock cycle before the wait state or during the wait state, |
| bogdanm | 92:4fc01daae5a5 | 103 | valid only when accessing memories in burst mode. |
| bogdanm | 92:4fc01daae5a5 | 104 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| bogdanm | 92:4fc01daae5a5 | 105 | |
| bogdanm | 92:4fc01daae5a5 | 106 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
| bogdanm | 92:4fc01daae5a5 | 107 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| bogdanm | 92:4fc01daae5a5 | 108 | |
| bogdanm | 92:4fc01daae5a5 | 109 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| bogdanm | 92:4fc01daae5a5 | 110 | signal, valid for Flash memory access in burst mode. |
| bogdanm | 92:4fc01daae5a5 | 111 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| bogdanm | 92:4fc01daae5a5 | 112 | |
| bogdanm | 92:4fc01daae5a5 | 113 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| bogdanm | 92:4fc01daae5a5 | 114 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| bogdanm | 92:4fc01daae5a5 | 115 | |
| bogdanm | 92:4fc01daae5a5 | 116 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| bogdanm | 92:4fc01daae5a5 | 117 | valid only with asynchronous Flash memories. |
| bogdanm | 92:4fc01daae5a5 | 118 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| bogdanm | 92:4fc01daae5a5 | 119 | |
| bogdanm | 92:4fc01daae5a5 | 120 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| bogdanm | 92:4fc01daae5a5 | 121 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| bogdanm | 92:4fc01daae5a5 | 122 | |
| bogdanm | 92:4fc01daae5a5 | 123 | }FSMC_NORSRAM_InitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 124 | |
| bogdanm | 92:4fc01daae5a5 | 125 | /** |
| bogdanm | 92:4fc01daae5a5 | 126 | * @brief FSMC_NORSRAM Timing parameters structure definition |
| bogdanm | 92:4fc01daae5a5 | 127 | */ |
| bogdanm | 92:4fc01daae5a5 | 128 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 129 | { |
| bogdanm | 92:4fc01daae5a5 | 130 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 92:4fc01daae5a5 | 131 | the duration of the address setup time. |
| bogdanm | 92:4fc01daae5a5 | 132 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| bogdanm | 92:4fc01daae5a5 | 133 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| bogdanm | 92:4fc01daae5a5 | 134 | |
| bogdanm | 92:4fc01daae5a5 | 135 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 92:4fc01daae5a5 | 136 | the duration of the address hold time. |
| bogdanm | 92:4fc01daae5a5 | 137 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| bogdanm | 92:4fc01daae5a5 | 138 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| bogdanm | 92:4fc01daae5a5 | 139 | |
| bogdanm | 92:4fc01daae5a5 | 140 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 92:4fc01daae5a5 | 141 | the duration of the data setup time. |
| bogdanm | 92:4fc01daae5a5 | 142 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| bogdanm | 92:4fc01daae5a5 | 143 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| bogdanm | 92:4fc01daae5a5 | 144 | NOR Flash memories. */ |
| bogdanm | 92:4fc01daae5a5 | 145 | |
| bogdanm | 92:4fc01daae5a5 | 146 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 92:4fc01daae5a5 | 147 | the duration of the bus turnaround. |
| bogdanm | 92:4fc01daae5a5 | 148 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| bogdanm | 92:4fc01daae5a5 | 149 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| bogdanm | 92:4fc01daae5a5 | 150 | |
| bogdanm | 92:4fc01daae5a5 | 151 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| bogdanm | 92:4fc01daae5a5 | 152 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| bogdanm | 92:4fc01daae5a5 | 153 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| bogdanm | 92:4fc01daae5a5 | 154 | accesses. */ |
| bogdanm | 92:4fc01daae5a5 | 155 | |
| bogdanm | 92:4fc01daae5a5 | 156 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| bogdanm | 92:4fc01daae5a5 | 157 | to the memory before getting the first data. |
| bogdanm | 92:4fc01daae5a5 | 158 | The parameter value depends on the memory type as shown below: |
| bogdanm | 92:4fc01daae5a5 | 159 | - It must be set to 0 in case of a CRAM |
| bogdanm | 92:4fc01daae5a5 | 160 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| bogdanm | 92:4fc01daae5a5 | 161 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| bogdanm | 92:4fc01daae5a5 | 162 | with synchronous burst mode enable */ |
| bogdanm | 92:4fc01daae5a5 | 163 | |
| bogdanm | 92:4fc01daae5a5 | 164 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| bogdanm | 92:4fc01daae5a5 | 165 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| bogdanm | 92:4fc01daae5a5 | 166 | |
| bogdanm | 92:4fc01daae5a5 | 167 | }FSMC_NORSRAM_TimingTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 168 | |
| bogdanm | 92:4fc01daae5a5 | 169 | /** |
| bogdanm | 92:4fc01daae5a5 | 170 | * @brief FSMC_NAND Configuration Structure definition |
| bogdanm | 92:4fc01daae5a5 | 171 | */ |
| bogdanm | 92:4fc01daae5a5 | 172 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 173 | { |
| bogdanm | 92:4fc01daae5a5 | 174 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| bogdanm | 92:4fc01daae5a5 | 175 | This parameter can be a value of @ref FSMC_NAND_Bank */ |
| bogdanm | 92:4fc01daae5a5 | 176 | |
| bogdanm | 92:4fc01daae5a5 | 177 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| bogdanm | 92:4fc01daae5a5 | 178 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| bogdanm | 92:4fc01daae5a5 | 179 | |
| bogdanm | 92:4fc01daae5a5 | 180 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| bogdanm | 92:4fc01daae5a5 | 181 | This parameter can be any value of @ref FSMC_NAND_Data_Width */ |
| bogdanm | 92:4fc01daae5a5 | 182 | |
| bogdanm | 92:4fc01daae5a5 | 183 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| bogdanm | 92:4fc01daae5a5 | 184 | This parameter can be any value of @ref FSMC_ECC */ |
| bogdanm | 92:4fc01daae5a5 | 185 | |
| bogdanm | 92:4fc01daae5a5 | 186 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| bogdanm | 92:4fc01daae5a5 | 187 | This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
| bogdanm | 92:4fc01daae5a5 | 188 | |
| bogdanm | 92:4fc01daae5a5 | 189 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 92:4fc01daae5a5 | 190 | delay between CLE low and RE low. |
| bogdanm | 92:4fc01daae5a5 | 191 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 192 | |
| bogdanm | 92:4fc01daae5a5 | 193 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 92:4fc01daae5a5 | 194 | delay between ALE low and RE low. |
| bogdanm | 92:4fc01daae5a5 | 195 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 196 | |
| bogdanm | 92:4fc01daae5a5 | 197 | }FSMC_NAND_InitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 198 | |
| bogdanm | 92:4fc01daae5a5 | 199 | /** |
| bogdanm | 92:4fc01daae5a5 | 200 | * @brief FSMC_NAND_PCCARD Timing parameters structure definition |
| bogdanm | 92:4fc01daae5a5 | 201 | */ |
| bogdanm | 92:4fc01daae5a5 | 202 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 203 | { |
| bogdanm | 92:4fc01daae5a5 | 204 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| bogdanm | 92:4fc01daae5a5 | 205 | the command assertion for NAND-Flash read or write access |
| bogdanm | 92:4fc01daae5a5 | 206 | to common/Attribute or I/O memory space (depending on |
| bogdanm | 92:4fc01daae5a5 | 207 | the memory space timing to be configured). |
| bogdanm | 92:4fc01daae5a5 | 208 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 209 | |
| bogdanm | 92:4fc01daae5a5 | 210 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| bogdanm | 92:4fc01daae5a5 | 211 | command for NAND-Flash read or write access to |
| bogdanm | 92:4fc01daae5a5 | 212 | common/Attribute or I/O memory space (depending on the |
| bogdanm | 92:4fc01daae5a5 | 213 | memory space timing to be configured). |
| bogdanm | 92:4fc01daae5a5 | 214 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 215 | |
| bogdanm | 92:4fc01daae5a5 | 216 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| bogdanm | 92:4fc01daae5a5 | 217 | (and data for write access) after the command de-assertion |
| bogdanm | 92:4fc01daae5a5 | 218 | for NAND-Flash read or write access to common/Attribute |
| bogdanm | 92:4fc01daae5a5 | 219 | or I/O memory space (depending on the memory space timing |
| bogdanm | 92:4fc01daae5a5 | 220 | to be configured). |
| bogdanm | 92:4fc01daae5a5 | 221 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 222 | |
| bogdanm | 92:4fc01daae5a5 | 223 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| bogdanm | 92:4fc01daae5a5 | 224 | data bus is kept in HiZ after the start of a NAND-Flash |
| bogdanm | 92:4fc01daae5a5 | 225 | write access to common/Attribute or I/O memory space (depending |
| bogdanm | 92:4fc01daae5a5 | 226 | on the memory space timing to be configured). |
| bogdanm | 92:4fc01daae5a5 | 227 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 228 | |
| bogdanm | 92:4fc01daae5a5 | 229 | }FSMC_NAND_PCC_TimingTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 230 | |
| bogdanm | 92:4fc01daae5a5 | 231 | /** |
| bogdanm | 92:4fc01daae5a5 | 232 | * @brief FSMC_NAND Configuration Structure definition |
| bogdanm | 92:4fc01daae5a5 | 233 | */ |
| bogdanm | 92:4fc01daae5a5 | 234 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 235 | { |
| bogdanm | 92:4fc01daae5a5 | 236 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
| bogdanm | 92:4fc01daae5a5 | 237 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| bogdanm | 92:4fc01daae5a5 | 238 | |
| bogdanm | 92:4fc01daae5a5 | 239 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 92:4fc01daae5a5 | 240 | delay between CLE low and RE low. |
| bogdanm | 92:4fc01daae5a5 | 241 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 242 | |
| bogdanm | 92:4fc01daae5a5 | 243 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 92:4fc01daae5a5 | 244 | delay between ALE low and RE low. |
| bogdanm | 92:4fc01daae5a5 | 245 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 92:4fc01daae5a5 | 246 | |
| bogdanm | 92:4fc01daae5a5 | 247 | }FSMC_PCCARD_InitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 248 | |
| bogdanm | 92:4fc01daae5a5 | 249 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 250 | |
| bogdanm | 92:4fc01daae5a5 | 251 | /** @defgroup FSMC_NOR_SRAM_Controller |
| bogdanm | 92:4fc01daae5a5 | 252 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 253 | */ |
| bogdanm | 92:4fc01daae5a5 | 254 | |
| bogdanm | 92:4fc01daae5a5 | 255 | /** @defgroup FSMC_NORSRAM_Bank |
| bogdanm | 92:4fc01daae5a5 | 256 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 257 | */ |
| bogdanm | 92:4fc01daae5a5 | 258 | #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 259 | #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
| bogdanm | 92:4fc01daae5a5 | 260 | #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
| bogdanm | 92:4fc01daae5a5 | 261 | #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
| bogdanm | 92:4fc01daae5a5 | 262 | |
| bogdanm | 92:4fc01daae5a5 | 263 | #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \ |
| bogdanm | 92:4fc01daae5a5 | 264 | ((BANK) == FSMC_NORSRAM_BANK2) || \ |
| bogdanm | 92:4fc01daae5a5 | 265 | ((BANK) == FSMC_NORSRAM_BANK3) || \ |
| bogdanm | 92:4fc01daae5a5 | 266 | ((BANK) == FSMC_NORSRAM_BANK4)) |
| bogdanm | 92:4fc01daae5a5 | 267 | /** |
| bogdanm | 92:4fc01daae5a5 | 268 | * @} |
| bogdanm | 92:4fc01daae5a5 | 269 | */ |
| bogdanm | 92:4fc01daae5a5 | 270 | |
| bogdanm | 92:4fc01daae5a5 | 271 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing |
| bogdanm | 92:4fc01daae5a5 | 272 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 273 | */ |
| bogdanm | 92:4fc01daae5a5 | 274 | |
| bogdanm | 92:4fc01daae5a5 | 275 | #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 276 | #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) |
| bogdanm | 92:4fc01daae5a5 | 277 | |
| bogdanm | 92:4fc01daae5a5 | 278 | #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 279 | ((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 280 | /** |
| bogdanm | 92:4fc01daae5a5 | 281 | * @} |
| bogdanm | 92:4fc01daae5a5 | 282 | */ |
| bogdanm | 92:4fc01daae5a5 | 283 | |
| bogdanm | 92:4fc01daae5a5 | 284 | /** @defgroup FSMC_Memory_Type |
| bogdanm | 92:4fc01daae5a5 | 285 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 286 | */ |
| bogdanm | 92:4fc01daae5a5 | 287 | |
| bogdanm | 92:4fc01daae5a5 | 288 | #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 289 | #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) |
| bogdanm | 92:4fc01daae5a5 | 290 | #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) |
| bogdanm | 92:4fc01daae5a5 | 291 | |
| bogdanm | 92:4fc01daae5a5 | 292 | |
| bogdanm | 92:4fc01daae5a5 | 293 | #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \ |
| bogdanm | 92:4fc01daae5a5 | 294 | ((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| bogdanm | 92:4fc01daae5a5 | 295 | ((MEMORY) == FSMC_MEMORY_TYPE_NOR)) |
| bogdanm | 92:4fc01daae5a5 | 296 | /** |
| bogdanm | 92:4fc01daae5a5 | 297 | * @} |
| bogdanm | 92:4fc01daae5a5 | 298 | */ |
| bogdanm | 92:4fc01daae5a5 | 299 | |
| bogdanm | 92:4fc01daae5a5 | 300 | /** @defgroup FSMC_NORSRAM_Data_Width |
| bogdanm | 92:4fc01daae5a5 | 301 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 302 | */ |
| bogdanm | 92:4fc01daae5a5 | 303 | |
| bogdanm | 92:4fc01daae5a5 | 304 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 305 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) |
| bogdanm | 92:4fc01daae5a5 | 306 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) |
| bogdanm | 92:4fc01daae5a5 | 307 | |
| bogdanm | 92:4fc01daae5a5 | 308 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| bogdanm | 92:4fc01daae5a5 | 309 | ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| bogdanm | 92:4fc01daae5a5 | 310 | ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| bogdanm | 92:4fc01daae5a5 | 311 | /** |
| bogdanm | 92:4fc01daae5a5 | 312 | * @} |
| bogdanm | 92:4fc01daae5a5 | 313 | */ |
| bogdanm | 92:4fc01daae5a5 | 314 | |
| bogdanm | 92:4fc01daae5a5 | 315 | /** @defgroup FSMC_NORSRAM_Flash_Access |
| bogdanm | 92:4fc01daae5a5 | 316 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 317 | */ |
| bogdanm | 92:4fc01daae5a5 | 318 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) |
| bogdanm | 92:4fc01daae5a5 | 319 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 320 | /** |
| bogdanm | 92:4fc01daae5a5 | 321 | * @} |
| bogdanm | 92:4fc01daae5a5 | 322 | */ |
| bogdanm | 92:4fc01daae5a5 | 323 | |
| bogdanm | 92:4fc01daae5a5 | 324 | /** @defgroup FSMC_Burst_Access_Mode |
| bogdanm | 92:4fc01daae5a5 | 325 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 326 | */ |
| bogdanm | 92:4fc01daae5a5 | 327 | |
| bogdanm | 92:4fc01daae5a5 | 328 | #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 329 | #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) |
| bogdanm | 92:4fc01daae5a5 | 330 | |
| bogdanm | 92:4fc01daae5a5 | 331 | #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 332 | ((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 333 | /** |
| bogdanm | 92:4fc01daae5a5 | 334 | * @} |
| bogdanm | 92:4fc01daae5a5 | 335 | */ |
| bogdanm | 92:4fc01daae5a5 | 336 | |
| bogdanm | 92:4fc01daae5a5 | 337 | |
| bogdanm | 92:4fc01daae5a5 | 338 | /** @defgroup FSMC_Wait_Signal_Polarity |
| bogdanm | 92:4fc01daae5a5 | 339 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 340 | */ |
| bogdanm | 92:4fc01daae5a5 | 341 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 342 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) |
| bogdanm | 92:4fc01daae5a5 | 343 | |
| bogdanm | 92:4fc01daae5a5 | 344 | #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| bogdanm | 92:4fc01daae5a5 | 345 | ((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| bogdanm | 92:4fc01daae5a5 | 346 | /** |
| bogdanm | 92:4fc01daae5a5 | 347 | * @} |
| bogdanm | 92:4fc01daae5a5 | 348 | */ |
| bogdanm | 92:4fc01daae5a5 | 349 | |
| bogdanm | 92:4fc01daae5a5 | 350 | /** @defgroup FSMC_Wrap_Mode |
| bogdanm | 92:4fc01daae5a5 | 351 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 352 | */ |
| bogdanm | 92:4fc01daae5a5 | 353 | #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 354 | #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400) |
| bogdanm | 92:4fc01daae5a5 | 355 | |
| bogdanm | 92:4fc01daae5a5 | 356 | #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 357 | ((MODE) == FSMC_WRAP_MODE_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 358 | /** |
| bogdanm | 92:4fc01daae5a5 | 359 | * @} |
| bogdanm | 92:4fc01daae5a5 | 360 | */ |
| bogdanm | 92:4fc01daae5a5 | 361 | |
| bogdanm | 92:4fc01daae5a5 | 362 | /** @defgroup FSMC_Wait_Timing |
| bogdanm | 92:4fc01daae5a5 | 363 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 364 | */ |
| bogdanm | 92:4fc01daae5a5 | 365 | #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 366 | #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) |
| bogdanm | 92:4fc01daae5a5 | 367 | |
| bogdanm | 92:4fc01daae5a5 | 368 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| bogdanm | 92:4fc01daae5a5 | 369 | ((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS)) |
| bogdanm | 92:4fc01daae5a5 | 370 | /** |
| bogdanm | 92:4fc01daae5a5 | 371 | * @} |
| bogdanm | 92:4fc01daae5a5 | 372 | */ |
| bogdanm | 92:4fc01daae5a5 | 373 | |
| bogdanm | 92:4fc01daae5a5 | 374 | /** @defgroup FSMC_Write_Operation |
| bogdanm | 92:4fc01daae5a5 | 375 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 376 | */ |
| bogdanm | 92:4fc01daae5a5 | 377 | #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 378 | #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) |
| bogdanm | 92:4fc01daae5a5 | 379 | |
| bogdanm | 92:4fc01daae5a5 | 380 | #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 381 | ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 382 | /** |
| bogdanm | 92:4fc01daae5a5 | 383 | * @} |
| bogdanm | 92:4fc01daae5a5 | 384 | */ |
| bogdanm | 92:4fc01daae5a5 | 385 | |
| bogdanm | 92:4fc01daae5a5 | 386 | /** @defgroup FSMC_Wait_Signal |
| bogdanm | 92:4fc01daae5a5 | 387 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 388 | */ |
| bogdanm | 92:4fc01daae5a5 | 389 | #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 390 | #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) |
| bogdanm | 92:4fc01daae5a5 | 391 | |
| bogdanm | 92:4fc01daae5a5 | 392 | #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 393 | ((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 394 | |
| bogdanm | 92:4fc01daae5a5 | 395 | /** |
| bogdanm | 92:4fc01daae5a5 | 396 | * @} |
| bogdanm | 92:4fc01daae5a5 | 397 | */ |
| bogdanm | 92:4fc01daae5a5 | 398 | |
| bogdanm | 92:4fc01daae5a5 | 399 | /** @defgroup FSMC_Extended_Mode |
| bogdanm | 92:4fc01daae5a5 | 400 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 401 | */ |
| bogdanm | 92:4fc01daae5a5 | 402 | #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 403 | #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) |
| bogdanm | 92:4fc01daae5a5 | 404 | |
| bogdanm | 92:4fc01daae5a5 | 405 | #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 406 | ((MODE) == FSMC_EXTENDED_MODE_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 407 | /** |
| bogdanm | 92:4fc01daae5a5 | 408 | * @} |
| bogdanm | 92:4fc01daae5a5 | 409 | */ |
| bogdanm | 92:4fc01daae5a5 | 410 | |
| bogdanm | 92:4fc01daae5a5 | 411 | /** @defgroup FSMC_AsynchronousWait |
| bogdanm | 92:4fc01daae5a5 | 412 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 413 | */ |
| bogdanm | 92:4fc01daae5a5 | 414 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 415 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) |
| bogdanm | 92:4fc01daae5a5 | 416 | |
| bogdanm | 92:4fc01daae5a5 | 417 | #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 418 | ((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 419 | |
| bogdanm | 92:4fc01daae5a5 | 420 | /** |
| bogdanm | 92:4fc01daae5a5 | 421 | * @} |
| bogdanm | 92:4fc01daae5a5 | 422 | */ |
| bogdanm | 92:4fc01daae5a5 | 423 | |
| bogdanm | 92:4fc01daae5a5 | 424 | /** @defgroup FSMC_Write_Burst |
| bogdanm | 92:4fc01daae5a5 | 425 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 426 | */ |
| bogdanm | 92:4fc01daae5a5 | 427 | |
| bogdanm | 92:4fc01daae5a5 | 428 | #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 429 | #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) |
| bogdanm | 92:4fc01daae5a5 | 430 | |
| bogdanm | 92:4fc01daae5a5 | 431 | #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 432 | ((BURST) == FSMC_WRITE_BURST_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 433 | |
| bogdanm | 92:4fc01daae5a5 | 434 | /** |
| bogdanm | 92:4fc01daae5a5 | 435 | * @} |
| bogdanm | 92:4fc01daae5a5 | 436 | */ |
| bogdanm | 92:4fc01daae5a5 | 437 | |
| bogdanm | 92:4fc01daae5a5 | 438 | /** @defgroup FSMC_Continous_Clock |
| bogdanm | 92:4fc01daae5a5 | 439 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 440 | */ |
| bogdanm | 92:4fc01daae5a5 | 441 | |
| bogdanm | 92:4fc01daae5a5 | 442 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 443 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) |
| bogdanm | 92:4fc01daae5a5 | 444 | |
| bogdanm | 92:4fc01daae5a5 | 445 | #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| bogdanm | 92:4fc01daae5a5 | 446 | ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| bogdanm | 92:4fc01daae5a5 | 447 | |
| bogdanm | 92:4fc01daae5a5 | 448 | /** |
| bogdanm | 92:4fc01daae5a5 | 449 | * @} |
| bogdanm | 92:4fc01daae5a5 | 450 | */ |
| bogdanm | 92:4fc01daae5a5 | 451 | |
| bogdanm | 92:4fc01daae5a5 | 452 | /** @defgroup FSMC_Address_Setup_Time |
| bogdanm | 92:4fc01daae5a5 | 453 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 454 | */ |
| bogdanm | 92:4fc01daae5a5 | 455 | #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15) |
| bogdanm | 92:4fc01daae5a5 | 456 | /** |
| bogdanm | 92:4fc01daae5a5 | 457 | * @} |
| bogdanm | 92:4fc01daae5a5 | 458 | */ |
| bogdanm | 92:4fc01daae5a5 | 459 | |
| bogdanm | 92:4fc01daae5a5 | 460 | /** @defgroup FSMC_Address_Hold_Time |
| bogdanm | 92:4fc01daae5a5 | 461 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 462 | */ |
| bogdanm | 92:4fc01daae5a5 | 463 | #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15)) |
| bogdanm | 92:4fc01daae5a5 | 464 | /** |
| bogdanm | 92:4fc01daae5a5 | 465 | * @} |
| bogdanm | 92:4fc01daae5a5 | 466 | */ |
| bogdanm | 92:4fc01daae5a5 | 467 | |
| bogdanm | 92:4fc01daae5a5 | 468 | /** @defgroup FSMC_Data_Setup_Time |
| bogdanm | 92:4fc01daae5a5 | 469 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 470 | */ |
| bogdanm | 92:4fc01daae5a5 | 471 | #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255)) |
| bogdanm | 92:4fc01daae5a5 | 472 | /** |
| bogdanm | 92:4fc01daae5a5 | 473 | * @} |
| bogdanm | 92:4fc01daae5a5 | 474 | */ |
| bogdanm | 92:4fc01daae5a5 | 475 | |
| bogdanm | 92:4fc01daae5a5 | 476 | /** @defgroup FSMC_Bus_Turn_around_Duration |
| bogdanm | 92:4fc01daae5a5 | 477 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 478 | */ |
| bogdanm | 92:4fc01daae5a5 | 479 | #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15) |
| bogdanm | 92:4fc01daae5a5 | 480 | /** |
| bogdanm | 92:4fc01daae5a5 | 481 | * @} |
| bogdanm | 92:4fc01daae5a5 | 482 | */ |
| bogdanm | 92:4fc01daae5a5 | 483 | |
| bogdanm | 92:4fc01daae5a5 | 484 | /** @defgroup FSMC_CLK_Division |
| bogdanm | 92:4fc01daae5a5 | 485 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 486 | */ |
| bogdanm | 92:4fc01daae5a5 | 487 | #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) |
| bogdanm | 92:4fc01daae5a5 | 488 | /** |
| bogdanm | 92:4fc01daae5a5 | 489 | * @} |
| bogdanm | 92:4fc01daae5a5 | 490 | */ |
| bogdanm | 92:4fc01daae5a5 | 491 | |
| bogdanm | 92:4fc01daae5a5 | 492 | /** @defgroup FSMC_Data_Latency |
| bogdanm | 92:4fc01daae5a5 | 493 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 494 | */ |
| bogdanm | 92:4fc01daae5a5 | 495 | #define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17)) |
| bogdanm | 92:4fc01daae5a5 | 496 | /** |
| bogdanm | 92:4fc01daae5a5 | 497 | * @} |
| bogdanm | 92:4fc01daae5a5 | 498 | */ |
| bogdanm | 92:4fc01daae5a5 | 499 | |
| bogdanm | 92:4fc01daae5a5 | 500 | /** @defgroup FSMC_Access_Mode |
| bogdanm | 92:4fc01daae5a5 | 501 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 502 | */ |
| bogdanm | 92:4fc01daae5a5 | 503 | #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 504 | #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000) |
| bogdanm | 92:4fc01daae5a5 | 505 | #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000) |
| bogdanm | 92:4fc01daae5a5 | 506 | #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000) |
| bogdanm | 92:4fc01daae5a5 | 507 | |
| bogdanm | 92:4fc01daae5a5 | 508 | #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \ |
| bogdanm | 92:4fc01daae5a5 | 509 | ((MODE) == FSMC_ACCESS_MODE_B) || \ |
| bogdanm | 92:4fc01daae5a5 | 510 | ((MODE) == FSMC_ACCESS_MODE_C) || \ |
| bogdanm | 92:4fc01daae5a5 | 511 | ((MODE) == FSMC_ACCESS_MODE_D)) |
| bogdanm | 92:4fc01daae5a5 | 512 | /** |
| bogdanm | 92:4fc01daae5a5 | 513 | * @} |
| bogdanm | 92:4fc01daae5a5 | 514 | */ |
| bogdanm | 92:4fc01daae5a5 | 515 | |
| bogdanm | 92:4fc01daae5a5 | 516 | /** |
| bogdanm | 92:4fc01daae5a5 | 517 | * @} |
| bogdanm | 92:4fc01daae5a5 | 518 | */ |
| bogdanm | 92:4fc01daae5a5 | 519 | |
| bogdanm | 92:4fc01daae5a5 | 520 | /** @defgroup FSMC_NAND_Controller |
| bogdanm | 92:4fc01daae5a5 | 521 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 522 | */ |
| bogdanm | 92:4fc01daae5a5 | 523 | |
| bogdanm | 92:4fc01daae5a5 | 524 | /** @defgroup FSMC_NAND_Bank |
| bogdanm | 92:4fc01daae5a5 | 525 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 526 | */ |
| bogdanm | 92:4fc01daae5a5 | 527 | #define FSMC_NAND_BANK2 ((uint32_t)0x00000010) |
| bogdanm | 92:4fc01daae5a5 | 528 | #define FSMC_NAND_BANK3 ((uint32_t)0x00000100) |
| bogdanm | 92:4fc01daae5a5 | 529 | |
| bogdanm | 92:4fc01daae5a5 | 530 | #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ |
| bogdanm | 92:4fc01daae5a5 | 531 | ((BANK) == FSMC_NAND_BANK3)) |
| bogdanm | 92:4fc01daae5a5 | 532 | |
| bogdanm | 92:4fc01daae5a5 | 533 | /** |
| bogdanm | 92:4fc01daae5a5 | 534 | * @} |
| bogdanm | 92:4fc01daae5a5 | 535 | */ |
| bogdanm | 92:4fc01daae5a5 | 536 | |
| bogdanm | 92:4fc01daae5a5 | 537 | /** @defgroup FSMC_Wait_feature |
| bogdanm | 92:4fc01daae5a5 | 538 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 539 | */ |
| bogdanm | 92:4fc01daae5a5 | 540 | #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 541 | #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) |
| bogdanm | 92:4fc01daae5a5 | 542 | |
| bogdanm | 92:4fc01daae5a5 | 543 | #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 544 | ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 545 | /** |
| bogdanm | 92:4fc01daae5a5 | 546 | * @} |
| bogdanm | 92:4fc01daae5a5 | 547 | */ |
| bogdanm | 92:4fc01daae5a5 | 548 | |
| bogdanm | 92:4fc01daae5a5 | 549 | /** @defgroup FSMC_PCR_Memory_Type |
| bogdanm | 92:4fc01daae5a5 | 550 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 551 | */ |
| bogdanm | 92:4fc01daae5a5 | 552 | #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 553 | #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) |
| bogdanm | 92:4fc01daae5a5 | 554 | /** |
| bogdanm | 92:4fc01daae5a5 | 555 | * @} |
| bogdanm | 92:4fc01daae5a5 | 556 | */ |
| bogdanm | 92:4fc01daae5a5 | 557 | |
| bogdanm | 92:4fc01daae5a5 | 558 | /** @defgroup FSMC_NAND_Data_Width |
| bogdanm | 92:4fc01daae5a5 | 559 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 560 | */ |
| bogdanm | 92:4fc01daae5a5 | 561 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 562 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) |
| bogdanm | 92:4fc01daae5a5 | 563 | |
| bogdanm | 92:4fc01daae5a5 | 564 | #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
| bogdanm | 92:4fc01daae5a5 | 565 | ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
| bogdanm | 92:4fc01daae5a5 | 566 | /** |
| bogdanm | 92:4fc01daae5a5 | 567 | * @} |
| bogdanm | 92:4fc01daae5a5 | 568 | */ |
| bogdanm | 92:4fc01daae5a5 | 569 | |
| bogdanm | 92:4fc01daae5a5 | 570 | /** @defgroup FSMC_ECC |
| bogdanm | 92:4fc01daae5a5 | 571 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 572 | */ |
| bogdanm | 92:4fc01daae5a5 | 573 | #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 574 | #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) |
| bogdanm | 92:4fc01daae5a5 | 575 | |
| bogdanm | 92:4fc01daae5a5 | 576 | #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 577 | ((STATE) == FSMC_NAND_ECC_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 578 | /** |
| bogdanm | 92:4fc01daae5a5 | 579 | * @} |
| bogdanm | 92:4fc01daae5a5 | 580 | */ |
| bogdanm | 92:4fc01daae5a5 | 581 | |
| bogdanm | 92:4fc01daae5a5 | 582 | /** @defgroup FSMC_ECC_Page_Size |
| bogdanm | 92:4fc01daae5a5 | 583 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 584 | */ |
| bogdanm | 92:4fc01daae5a5 | 585 | #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
| bogdanm | 92:4fc01daae5a5 | 586 | #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) |
| bogdanm | 92:4fc01daae5a5 | 587 | #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) |
| bogdanm | 92:4fc01daae5a5 | 588 | #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) |
| bogdanm | 92:4fc01daae5a5 | 589 | #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) |
| bogdanm | 92:4fc01daae5a5 | 590 | #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) |
| bogdanm | 92:4fc01daae5a5 | 591 | |
| bogdanm | 92:4fc01daae5a5 | 592 | #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| bogdanm | 92:4fc01daae5a5 | 593 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| bogdanm | 92:4fc01daae5a5 | 594 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| bogdanm | 92:4fc01daae5a5 | 595 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| bogdanm | 92:4fc01daae5a5 | 596 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| bogdanm | 92:4fc01daae5a5 | 597 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| bogdanm | 92:4fc01daae5a5 | 598 | /** |
| bogdanm | 92:4fc01daae5a5 | 599 | * @} |
| bogdanm | 92:4fc01daae5a5 | 600 | */ |
| bogdanm | 92:4fc01daae5a5 | 601 | |
| bogdanm | 92:4fc01daae5a5 | 602 | /** @defgroup FSMC_TCLR_Setup_Time |
| bogdanm | 92:4fc01daae5a5 | 603 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 604 | */ |
| bogdanm | 92:4fc01daae5a5 | 605 | #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 92:4fc01daae5a5 | 606 | /** |
| bogdanm | 92:4fc01daae5a5 | 607 | * @} |
| bogdanm | 92:4fc01daae5a5 | 608 | */ |
| bogdanm | 92:4fc01daae5a5 | 609 | |
| bogdanm | 92:4fc01daae5a5 | 610 | /** @defgroup FSMC_TAR_Setup_Time |
| bogdanm | 92:4fc01daae5a5 | 611 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 612 | */ |
| bogdanm | 92:4fc01daae5a5 | 613 | #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 92:4fc01daae5a5 | 614 | /** |
| bogdanm | 92:4fc01daae5a5 | 615 | * @} |
| bogdanm | 92:4fc01daae5a5 | 616 | */ |
| bogdanm | 92:4fc01daae5a5 | 617 | |
| bogdanm | 92:4fc01daae5a5 | 618 | /** @defgroup FSMC_Setup_Time |
| bogdanm | 92:4fc01daae5a5 | 619 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 620 | */ |
| bogdanm | 92:4fc01daae5a5 | 621 | #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 92:4fc01daae5a5 | 622 | /** |
| bogdanm | 92:4fc01daae5a5 | 623 | * @} |
| bogdanm | 92:4fc01daae5a5 | 624 | */ |
| bogdanm | 92:4fc01daae5a5 | 625 | |
| bogdanm | 92:4fc01daae5a5 | 626 | /** @defgroup FSMC_Wait_Setup_Time |
| bogdanm | 92:4fc01daae5a5 | 627 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 628 | */ |
| bogdanm | 92:4fc01daae5a5 | 629 | #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 92:4fc01daae5a5 | 630 | /** |
| bogdanm | 92:4fc01daae5a5 | 631 | * @} |
| bogdanm | 92:4fc01daae5a5 | 632 | */ |
| bogdanm | 92:4fc01daae5a5 | 633 | |
| bogdanm | 92:4fc01daae5a5 | 634 | /** @defgroup FSMC_Hold_Setup_Time |
| bogdanm | 92:4fc01daae5a5 | 635 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 636 | */ |
| bogdanm | 92:4fc01daae5a5 | 637 | #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 92:4fc01daae5a5 | 638 | /** |
| bogdanm | 92:4fc01daae5a5 | 639 | * @} |
| bogdanm | 92:4fc01daae5a5 | 640 | */ |
| bogdanm | 92:4fc01daae5a5 | 641 | |
| bogdanm | 92:4fc01daae5a5 | 642 | /** @defgroup FSMC_HiZ_Setup_Time |
| bogdanm | 92:4fc01daae5a5 | 643 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 644 | */ |
| bogdanm | 92:4fc01daae5a5 | 645 | #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 92:4fc01daae5a5 | 646 | /** |
| bogdanm | 92:4fc01daae5a5 | 647 | * @} |
| bogdanm | 92:4fc01daae5a5 | 648 | */ |
| bogdanm | 92:4fc01daae5a5 | 649 | |
| bogdanm | 92:4fc01daae5a5 | 650 | /** |
| bogdanm | 92:4fc01daae5a5 | 651 | * @} |
| bogdanm | 92:4fc01daae5a5 | 652 | */ |
| bogdanm | 92:4fc01daae5a5 | 653 | |
| bogdanm | 92:4fc01daae5a5 | 654 | |
| bogdanm | 92:4fc01daae5a5 | 655 | /** @defgroup FSMC_NORSRAM_Device_Instance |
| bogdanm | 92:4fc01daae5a5 | 656 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 657 | */ |
| bogdanm | 92:4fc01daae5a5 | 658 | #define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE) |
| bogdanm | 92:4fc01daae5a5 | 659 | |
| bogdanm | 92:4fc01daae5a5 | 660 | /** |
| bogdanm | 92:4fc01daae5a5 | 661 | * @} |
| bogdanm | 92:4fc01daae5a5 | 662 | */ |
| bogdanm | 92:4fc01daae5a5 | 663 | |
| bogdanm | 92:4fc01daae5a5 | 664 | /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance |
| bogdanm | 92:4fc01daae5a5 | 665 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 666 | */ |
| bogdanm | 92:4fc01daae5a5 | 667 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| bogdanm | 92:4fc01daae5a5 | 668 | |
| bogdanm | 92:4fc01daae5a5 | 669 | /** |
| bogdanm | 92:4fc01daae5a5 | 670 | * @} |
| bogdanm | 92:4fc01daae5a5 | 671 | */ |
| bogdanm | 92:4fc01daae5a5 | 672 | |
| bogdanm | 92:4fc01daae5a5 | 673 | /** @defgroup FSMC_NAND_Device_Instance |
| bogdanm | 92:4fc01daae5a5 | 674 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 675 | */ |
| bogdanm | 92:4fc01daae5a5 | 676 | #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) |
| bogdanm | 92:4fc01daae5a5 | 677 | |
| bogdanm | 92:4fc01daae5a5 | 678 | /** |
| bogdanm | 92:4fc01daae5a5 | 679 | * @} |
| bogdanm | 92:4fc01daae5a5 | 680 | */ |
| bogdanm | 92:4fc01daae5a5 | 681 | |
| bogdanm | 92:4fc01daae5a5 | 682 | /** @defgroup FSMC_PCCARD_Device_Instance |
| bogdanm | 92:4fc01daae5a5 | 683 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 684 | */ |
| bogdanm | 92:4fc01daae5a5 | 685 | #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) |
| bogdanm | 92:4fc01daae5a5 | 686 | |
| bogdanm | 92:4fc01daae5a5 | 687 | /** |
| bogdanm | 92:4fc01daae5a5 | 688 | * @} |
| bogdanm | 92:4fc01daae5a5 | 689 | */ |
| bogdanm | 92:4fc01daae5a5 | 690 | |
| bogdanm | 92:4fc01daae5a5 | 691 | /** @defgroup FSMC_Interrupt_definition |
| bogdanm | 92:4fc01daae5a5 | 692 | * @brief FSMC Interrupt definition |
| bogdanm | 92:4fc01daae5a5 | 693 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 694 | */ |
| bogdanm | 92:4fc01daae5a5 | 695 | #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008) |
| bogdanm | 92:4fc01daae5a5 | 696 | #define FSMC_IT_LEVEL ((uint32_t)0x00000010) |
| bogdanm | 92:4fc01daae5a5 | 697 | #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020) |
| bogdanm | 92:4fc01daae5a5 | 698 | #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) |
| bogdanm | 92:4fc01daae5a5 | 699 | |
| bogdanm | 92:4fc01daae5a5 | 700 | #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 701 | #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) || \ |
| bogdanm | 92:4fc01daae5a5 | 702 | ((IT) == FSMC_IT_LEVEL) || \ |
| bogdanm | 92:4fc01daae5a5 | 703 | ((IT) == FSMC_IT_FALLING_EDGE) || \ |
| bogdanm | 92:4fc01daae5a5 | 704 | ((IT) == FSMC_IT_REFRESH_ERROR)) |
| bogdanm | 92:4fc01daae5a5 | 705 | /** |
| bogdanm | 92:4fc01daae5a5 | 706 | * @} |
| bogdanm | 92:4fc01daae5a5 | 707 | */ |
| bogdanm | 92:4fc01daae5a5 | 708 | |
| bogdanm | 92:4fc01daae5a5 | 709 | /** @defgroup FSMC_Flag_definition |
| bogdanm | 92:4fc01daae5a5 | 710 | * @brief FSMC Flag definition |
| bogdanm | 92:4fc01daae5a5 | 711 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 712 | */ |
| bogdanm | 92:4fc01daae5a5 | 713 | #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) |
| bogdanm | 92:4fc01daae5a5 | 714 | #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002) |
| bogdanm | 92:4fc01daae5a5 | 715 | #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) |
| bogdanm | 92:4fc01daae5a5 | 716 | #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) |
| bogdanm | 92:4fc01daae5a5 | 717 | |
| bogdanm | 92:4fc01daae5a5 | 718 | #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) || \ |
| bogdanm | 92:4fc01daae5a5 | 719 | ((FLAG) == FSMC_FLAG_LEVEL) || \ |
| bogdanm | 92:4fc01daae5a5 | 720 | ((FLAG) == FSMC_FLAG_FALLING_EDGE) || \ |
| bogdanm | 92:4fc01daae5a5 | 721 | ((FLAG) == FSMC_FLAG_FEMPT)) |
| bogdanm | 92:4fc01daae5a5 | 722 | |
| bogdanm | 92:4fc01daae5a5 | 723 | #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 724 | |
| bogdanm | 92:4fc01daae5a5 | 725 | |
| bogdanm | 92:4fc01daae5a5 | 726 | /** |
| bogdanm | 92:4fc01daae5a5 | 727 | * @} |
| bogdanm | 92:4fc01daae5a5 | 728 | */ |
| bogdanm | 92:4fc01daae5a5 | 729 | |
| bogdanm | 92:4fc01daae5a5 | 730 | |
| bogdanm | 92:4fc01daae5a5 | 731 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 732 | |
| bogdanm | 92:4fc01daae5a5 | 733 | |
| bogdanm | 92:4fc01daae5a5 | 734 | /** @defgroup FSMC_NOR_Macros |
| bogdanm | 92:4fc01daae5a5 | 735 | * @brief macros to handle NOR device enable/disable and read/write operations |
| bogdanm | 92:4fc01daae5a5 | 736 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 737 | */ |
| bogdanm | 92:4fc01daae5a5 | 738 | |
| bogdanm | 92:4fc01daae5a5 | 739 | /** |
| bogdanm | 92:4fc01daae5a5 | 740 | * @brief Enable the NORSRAM device access. |
| bogdanm | 92:4fc01daae5a5 | 741 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| bogdanm | 92:4fc01daae5a5 | 742 | * @param __BANK__: FSMC_NORSRAM Bank |
| bogdanm | 92:4fc01daae5a5 | 743 | * @retval none |
| bogdanm | 92:4fc01daae5a5 | 744 | */ |
| bogdanm | 92:4fc01daae5a5 | 745 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) |
| bogdanm | 92:4fc01daae5a5 | 746 | |
| bogdanm | 92:4fc01daae5a5 | 747 | /** |
| bogdanm | 92:4fc01daae5a5 | 748 | * @brief Disable the NORSRAM device access. |
| bogdanm | 92:4fc01daae5a5 | 749 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| bogdanm | 92:4fc01daae5a5 | 750 | * @param __BANK__: FSMC_NORSRAM Bank |
| bogdanm | 92:4fc01daae5a5 | 751 | * @retval none |
| bogdanm | 92:4fc01daae5a5 | 752 | */ |
| bogdanm | 92:4fc01daae5a5 | 753 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) |
| bogdanm | 92:4fc01daae5a5 | 754 | |
| bogdanm | 92:4fc01daae5a5 | 755 | /** |
| bogdanm | 92:4fc01daae5a5 | 756 | * @} |
| bogdanm | 92:4fc01daae5a5 | 757 | */ |
| bogdanm | 92:4fc01daae5a5 | 758 | |
| bogdanm | 92:4fc01daae5a5 | 759 | |
| bogdanm | 92:4fc01daae5a5 | 760 | /** @defgroup FSMC_NAND_Macros |
| bogdanm | 92:4fc01daae5a5 | 761 | * @brief macros to handle NAND device enable/disable |
| bogdanm | 92:4fc01daae5a5 | 762 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 763 | */ |
| bogdanm | 92:4fc01daae5a5 | 764 | |
| bogdanm | 92:4fc01daae5a5 | 765 | /** |
| bogdanm | 92:4fc01daae5a5 | 766 | * @brief Enable the NAND device access. |
| bogdanm | 92:4fc01daae5a5 | 767 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 92:4fc01daae5a5 | 768 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 92:4fc01daae5a5 | 769 | * @retval none |
| bogdanm | 92:4fc01daae5a5 | 770 | */ |
| bogdanm | 92:4fc01daae5a5 | 771 | #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ |
| bogdanm | 92:4fc01daae5a5 | 772 | ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) |
| bogdanm | 92:4fc01daae5a5 | 773 | |
| bogdanm | 92:4fc01daae5a5 | 774 | |
| bogdanm | 92:4fc01daae5a5 | 775 | /** |
| bogdanm | 92:4fc01daae5a5 | 776 | * @brief Disable the NAND device access. |
| bogdanm | 92:4fc01daae5a5 | 777 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 92:4fc01daae5a5 | 778 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 92:4fc01daae5a5 | 779 | * @retval none |
| bogdanm | 92:4fc01daae5a5 | 780 | */ |
| bogdanm | 92:4fc01daae5a5 | 781 | #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ |
| bogdanm | 92:4fc01daae5a5 | 782 | ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN)) |
| bogdanm | 92:4fc01daae5a5 | 783 | |
| bogdanm | 92:4fc01daae5a5 | 784 | |
| bogdanm | 92:4fc01daae5a5 | 785 | /** |
| bogdanm | 92:4fc01daae5a5 | 786 | * @} |
| bogdanm | 92:4fc01daae5a5 | 787 | */ |
| bogdanm | 92:4fc01daae5a5 | 788 | |
| bogdanm | 92:4fc01daae5a5 | 789 | /** @defgroup FSMC_PCCARD_Macros |
| bogdanm | 92:4fc01daae5a5 | 790 | * @brief macros to handle SRAM read/write operations |
| bogdanm | 92:4fc01daae5a5 | 791 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 792 | */ |
| bogdanm | 92:4fc01daae5a5 | 793 | |
| bogdanm | 92:4fc01daae5a5 | 794 | /** |
| bogdanm | 92:4fc01daae5a5 | 795 | * @brief Enable the PCCARD device access. |
| bogdanm | 92:4fc01daae5a5 | 796 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 92:4fc01daae5a5 | 797 | * @retval none |
| bogdanm | 92:4fc01daae5a5 | 798 | */ |
| bogdanm | 92:4fc01daae5a5 | 799 | #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) |
| bogdanm | 92:4fc01daae5a5 | 800 | |
| bogdanm | 92:4fc01daae5a5 | 801 | /** |
| bogdanm | 92:4fc01daae5a5 | 802 | * @brief Disable the PCCARD device access. |
| bogdanm | 92:4fc01daae5a5 | 803 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 92:4fc01daae5a5 | 804 | * @retval none |
| bogdanm | 92:4fc01daae5a5 | 805 | */ |
| bogdanm | 92:4fc01daae5a5 | 806 | #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) |
| bogdanm | 92:4fc01daae5a5 | 807 | |
| bogdanm | 92:4fc01daae5a5 | 808 | /** |
| bogdanm | 92:4fc01daae5a5 | 809 | * @} |
| bogdanm | 92:4fc01daae5a5 | 810 | */ |
| bogdanm | 92:4fc01daae5a5 | 811 | |
| bogdanm | 92:4fc01daae5a5 | 812 | /** @defgroup FSMC_Interrupt |
| bogdanm | 92:4fc01daae5a5 | 813 | * @brief macros to handle FSMC interrupts |
| bogdanm | 92:4fc01daae5a5 | 814 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 815 | */ |
| bogdanm | 92:4fc01daae5a5 | 816 | |
| bogdanm | 92:4fc01daae5a5 | 817 | /** |
| bogdanm | 92:4fc01daae5a5 | 818 | * @brief Enable the NAND device interrupt. |
| bogdanm | 92:4fc01daae5a5 | 819 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 92:4fc01daae5a5 | 820 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 92:4fc01daae5a5 | 821 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| bogdanm | 92:4fc01daae5a5 | 822 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 823 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 92:4fc01daae5a5 | 824 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| bogdanm | 92:4fc01daae5a5 | 825 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 92:4fc01daae5a5 | 826 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 827 | */ |
| bogdanm | 92:4fc01daae5a5 | 828 | #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ |
| bogdanm | 92:4fc01daae5a5 | 829 | ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) |
| bogdanm | 92:4fc01daae5a5 | 830 | |
| bogdanm | 92:4fc01daae5a5 | 831 | /** |
| bogdanm | 92:4fc01daae5a5 | 832 | * @brief Disable the NAND device interrupt. |
| bogdanm | 92:4fc01daae5a5 | 833 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 92:4fc01daae5a5 | 834 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 92:4fc01daae5a5 | 835 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| bogdanm | 92:4fc01daae5a5 | 836 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 837 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 92:4fc01daae5a5 | 838 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| bogdanm | 92:4fc01daae5a5 | 839 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 92:4fc01daae5a5 | 840 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 841 | */ |
| bogdanm | 92:4fc01daae5a5 | 842 | #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ |
| bogdanm | 92:4fc01daae5a5 | 843 | ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) |
| bogdanm | 92:4fc01daae5a5 | 844 | |
| bogdanm | 92:4fc01daae5a5 | 845 | /** |
| bogdanm | 92:4fc01daae5a5 | 846 | * @brief Get flag status of the NAND device. |
| bogdanm | 92:4fc01daae5a5 | 847 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 92:4fc01daae5a5 | 848 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 92:4fc01daae5a5 | 849 | * @param __FLAG__: FSMC_NAND flag |
| bogdanm | 92:4fc01daae5a5 | 850 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 851 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 92:4fc01daae5a5 | 852 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 92:4fc01daae5a5 | 853 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 92:4fc01daae5a5 | 854 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 92:4fc01daae5a5 | 855 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 92:4fc01daae5a5 | 856 | */ |
| bogdanm | 92:4fc01daae5a5 | 857 | #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
| bogdanm | 92:4fc01daae5a5 | 858 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
| bogdanm | 92:4fc01daae5a5 | 859 | /** |
| bogdanm | 92:4fc01daae5a5 | 860 | * @brief Clear flag status of the NAND device. |
| bogdanm | 92:4fc01daae5a5 | 861 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 92:4fc01daae5a5 | 862 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 92:4fc01daae5a5 | 863 | * @param __FLAG__: FSMC_NAND flag |
| bogdanm | 92:4fc01daae5a5 | 864 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 865 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 92:4fc01daae5a5 | 866 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 92:4fc01daae5a5 | 867 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 92:4fc01daae5a5 | 868 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 92:4fc01daae5a5 | 869 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 870 | */ |
| bogdanm | 92:4fc01daae5a5 | 871 | #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ |
| bogdanm | 92:4fc01daae5a5 | 872 | ((__INSTANCE__)->SR3 &= ~(__FLAG__))) |
| bogdanm | 92:4fc01daae5a5 | 873 | /** |
| bogdanm | 92:4fc01daae5a5 | 874 | * @brief Enable the PCCARD device interrupt. |
| bogdanm | 92:4fc01daae5a5 | 875 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 92:4fc01daae5a5 | 876 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| bogdanm | 92:4fc01daae5a5 | 877 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 878 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 92:4fc01daae5a5 | 879 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| bogdanm | 92:4fc01daae5a5 | 880 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 92:4fc01daae5a5 | 881 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 882 | */ |
| bogdanm | 92:4fc01daae5a5 | 883 | #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) |
| bogdanm | 92:4fc01daae5a5 | 884 | |
| bogdanm | 92:4fc01daae5a5 | 885 | /** |
| bogdanm | 92:4fc01daae5a5 | 886 | * @brief Disable the PCCARD device interrupt. |
| bogdanm | 92:4fc01daae5a5 | 887 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 92:4fc01daae5a5 | 888 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| bogdanm | 92:4fc01daae5a5 | 889 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 890 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 92:4fc01daae5a5 | 891 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| bogdanm | 92:4fc01daae5a5 | 892 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 92:4fc01daae5a5 | 893 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 894 | */ |
| bogdanm | 92:4fc01daae5a5 | 895 | #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) |
| bogdanm | 92:4fc01daae5a5 | 896 | |
| bogdanm | 92:4fc01daae5a5 | 897 | /** |
| bogdanm | 92:4fc01daae5a5 | 898 | * @brief Get flag status of the PCCARD device. |
| bogdanm | 92:4fc01daae5a5 | 899 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 92:4fc01daae5a5 | 900 | * @param __FLAG__: FSMC_PCCARD flag |
| bogdanm | 92:4fc01daae5a5 | 901 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 902 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 92:4fc01daae5a5 | 903 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 92:4fc01daae5a5 | 904 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 92:4fc01daae5a5 | 905 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 92:4fc01daae5a5 | 906 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 92:4fc01daae5a5 | 907 | */ |
| bogdanm | 92:4fc01daae5a5 | 908 | #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
| bogdanm | 92:4fc01daae5a5 | 909 | |
| bogdanm | 92:4fc01daae5a5 | 910 | /** |
| bogdanm | 92:4fc01daae5a5 | 911 | * @brief Clear flag status of the PCCARD device. |
| bogdanm | 92:4fc01daae5a5 | 912 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 92:4fc01daae5a5 | 913 | * @param __FLAG__: FSMC_PCCARD flag |
| bogdanm | 92:4fc01daae5a5 | 914 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 915 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 92:4fc01daae5a5 | 916 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 92:4fc01daae5a5 | 917 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 92:4fc01daae5a5 | 918 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 92:4fc01daae5a5 | 919 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 920 | */ |
| bogdanm | 92:4fc01daae5a5 | 921 | #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) |
| bogdanm | 92:4fc01daae5a5 | 922 | |
| bogdanm | 92:4fc01daae5a5 | 923 | /** |
| bogdanm | 92:4fc01daae5a5 | 924 | * @} |
| bogdanm | 92:4fc01daae5a5 | 925 | */ |
| bogdanm | 92:4fc01daae5a5 | 926 | |
| bogdanm | 92:4fc01daae5a5 | 927 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 928 | |
| bogdanm | 92:4fc01daae5a5 | 929 | /* FSMC_NORSRAM Controller functions ******************************************/ |
| bogdanm | 92:4fc01daae5a5 | 930 | /* Initialization/de-initialization functions */ |
| bogdanm | 92:4fc01daae5a5 | 931 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); |
| bogdanm | 92:4fc01daae5a5 | 932 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 933 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| bogdanm | 92:4fc01daae5a5 | 934 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 935 | |
| bogdanm | 92:4fc01daae5a5 | 936 | /* FSMC_NORSRAM Control functions */ |
| bogdanm | 92:4fc01daae5a5 | 937 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 938 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 939 | |
| bogdanm | 92:4fc01daae5a5 | 940 | /* FSMC_NAND Controller functions *********************************************/ |
| bogdanm | 92:4fc01daae5a5 | 941 | /* Initialization/de-initialization functions */ |
| bogdanm | 92:4fc01daae5a5 | 942 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); |
| bogdanm | 92:4fc01daae5a5 | 943 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 944 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 945 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 946 | |
| bogdanm | 92:4fc01daae5a5 | 947 | /* FSMC_NAND Control functions */ |
| bogdanm | 92:4fc01daae5a5 | 948 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 949 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 92:4fc01daae5a5 | 950 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| bogdanm | 92:4fc01daae5a5 | 951 | |
| bogdanm | 92:4fc01daae5a5 | 952 | /* FSMC_PCCARD Controller functions *******************************************/ |
| bogdanm | 92:4fc01daae5a5 | 953 | /* Initialization/de-initialization functions */ |
| bogdanm | 92:4fc01daae5a5 | 954 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); |
| bogdanm | 92:4fc01daae5a5 | 955 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| bogdanm | 92:4fc01daae5a5 | 956 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| bogdanm | 92:4fc01daae5a5 | 957 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| bogdanm | 92:4fc01daae5a5 | 958 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); |
| bogdanm | 92:4fc01daae5a5 | 959 | |
| bogdanm | 92:4fc01daae5a5 | 960 | /* FSMC APIs, macros and typedefs redefinition */ |
| bogdanm | 92:4fc01daae5a5 | 961 | #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 962 | #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 963 | #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef |
| bogdanm | 92:4fc01daae5a5 | 964 | #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef |
| bogdanm | 92:4fc01daae5a5 | 965 | |
| bogdanm | 92:4fc01daae5a5 | 966 | #define FMC_NORSRAM_Init FSMC_NORSRAM_Init |
| bogdanm | 92:4fc01daae5a5 | 967 | #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init |
| bogdanm | 92:4fc01daae5a5 | 968 | #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init |
| bogdanm | 92:4fc01daae5a5 | 969 | #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit |
| bogdanm | 92:4fc01daae5a5 | 970 | #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable |
| bogdanm | 92:4fc01daae5a5 | 971 | #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable |
| bogdanm | 92:4fc01daae5a5 | 972 | |
| bogdanm | 92:4fc01daae5a5 | 973 | #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE |
| bogdanm | 92:4fc01daae5a5 | 974 | #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE |
| bogdanm | 92:4fc01daae5a5 | 975 | |
| bogdanm | 92:4fc01daae5a5 | 976 | #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef |
| bogdanm | 92:4fc01daae5a5 | 977 | #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef |
| bogdanm | 92:4fc01daae5a5 | 978 | #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef |
| bogdanm | 92:4fc01daae5a5 | 979 | |
| bogdanm | 92:4fc01daae5a5 | 980 | #define FMC_NAND_Init FSMC_NAND_Init |
| bogdanm | 92:4fc01daae5a5 | 981 | #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init |
| bogdanm | 92:4fc01daae5a5 | 982 | #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init |
| bogdanm | 92:4fc01daae5a5 | 983 | #define FMC_NAND_DeInit FSMC_NAND_DeInit |
| bogdanm | 92:4fc01daae5a5 | 984 | #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable |
| bogdanm | 92:4fc01daae5a5 | 985 | #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable |
| bogdanm | 92:4fc01daae5a5 | 986 | #define FMC_NAND_GetECC FSMC_NAND_GetECC |
| bogdanm | 92:4fc01daae5a5 | 987 | #define FMC_PCCARD_Init FSMC_PCCARD_Init |
| bogdanm | 92:4fc01daae5a5 | 988 | #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init |
| bogdanm | 92:4fc01daae5a5 | 989 | #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init |
| bogdanm | 92:4fc01daae5a5 | 990 | #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init |
| bogdanm | 92:4fc01daae5a5 | 991 | #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit |
| bogdanm | 92:4fc01daae5a5 | 992 | |
| bogdanm | 92:4fc01daae5a5 | 993 | #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE |
| bogdanm | 92:4fc01daae5a5 | 994 | #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE |
| bogdanm | 92:4fc01daae5a5 | 995 | #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE |
| bogdanm | 92:4fc01daae5a5 | 996 | #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE |
| bogdanm | 92:4fc01daae5a5 | 997 | #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT |
| bogdanm | 92:4fc01daae5a5 | 998 | #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT |
| bogdanm | 92:4fc01daae5a5 | 999 | #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG |
| bogdanm | 92:4fc01daae5a5 | 1000 | #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG |
| bogdanm | 92:4fc01daae5a5 | 1001 | #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT |
| bogdanm | 92:4fc01daae5a5 | 1002 | #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT |
| bogdanm | 92:4fc01daae5a5 | 1003 | #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG |
| bogdanm | 92:4fc01daae5a5 | 1004 | #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG |
| bogdanm | 92:4fc01daae5a5 | 1005 | |
| bogdanm | 92:4fc01daae5a5 | 1006 | #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 1007 | #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 1008 | #define FMC_NAND_TypeDef FSMC_NAND_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 1009 | #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef |
| bogdanm | 92:4fc01daae5a5 | 1010 | |
| bogdanm | 92:4fc01daae5a5 | 1011 | #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE |
| bogdanm | 92:4fc01daae5a5 | 1012 | #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE |
| bogdanm | 92:4fc01daae5a5 | 1013 | #define FMC_NAND_DEVICE FSMC_NAND_DEVICE |
| bogdanm | 92:4fc01daae5a5 | 1014 | #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE |
| bogdanm | 92:4fc01daae5a5 | 1015 | |
| bogdanm | 92:4fc01daae5a5 | 1016 | #define FMC_NAND_BANK2 FSMC_NAND_BANK2 |
| bogdanm | 92:4fc01daae5a5 | 1017 | |
| bogdanm | 92:4fc01daae5a5 | 1018 | #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 |
| bogdanm | 92:4fc01daae5a5 | 1019 | #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 |
| bogdanm | 92:4fc01daae5a5 | 1020 | #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 |
| bogdanm | 92:4fc01daae5a5 | 1021 | |
| bogdanm | 92:4fc01daae5a5 | 1022 | #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE |
| bogdanm | 92:4fc01daae5a5 | 1023 | #define FMC_IT_LEVEL FSMC_IT_LEVEL |
| bogdanm | 92:4fc01daae5a5 | 1024 | #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE |
| bogdanm | 92:4fc01daae5a5 | 1025 | #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR |
| bogdanm | 92:4fc01daae5a5 | 1026 | |
| bogdanm | 92:4fc01daae5a5 | 1027 | #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE |
| bogdanm | 92:4fc01daae5a5 | 1028 | #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL |
| bogdanm | 92:4fc01daae5a5 | 1029 | #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE |
| bogdanm | 92:4fc01daae5a5 | 1030 | #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT |
| bogdanm | 92:4fc01daae5a5 | 1031 | |
| bogdanm | 92:4fc01daae5a5 | 1032 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| bogdanm | 92:4fc01daae5a5 | 1033 | |
| bogdanm | 92:4fc01daae5a5 | 1034 | /** |
| bogdanm | 92:4fc01daae5a5 | 1035 | * @} |
| bogdanm | 92:4fc01daae5a5 | 1036 | */ |
| bogdanm | 92:4fc01daae5a5 | 1037 | |
| bogdanm | 92:4fc01daae5a5 | 1038 | /** |
| bogdanm | 92:4fc01daae5a5 | 1039 | * @} |
| bogdanm | 92:4fc01daae5a5 | 1040 | */ |
| bogdanm | 92:4fc01daae5a5 | 1041 | |
| bogdanm | 92:4fc01daae5a5 | 1042 | #ifdef __cplusplus |
| bogdanm | 92:4fc01daae5a5 | 1043 | } |
| bogdanm | 92:4fc01daae5a5 | 1044 | #endif |
| bogdanm | 92:4fc01daae5a5 | 1045 | |
| bogdanm | 92:4fc01daae5a5 | 1046 | #endif /* __STM32F4xx_LL_FSMC_H */ |
| bogdanm | 92:4fc01daae5a5 | 1047 | |
| bogdanm | 92:4fc01daae5a5 | 1048 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |