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TARGET_MTS_MDOT_F405RG/stm32f4xx_ll_fmc.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:: fblanc
Date:: Fri Dec 05 15:42:32 2014 +0000
Revision:: 93:9dd889aeda0e
Parent:: 92:4fc01daae5a5

substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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User	Revision	Line number	New contents of line
bogdanm	92:4fc01daae5a5	1	/**
bogdanm	92:4fc01daae5a5	2	******************************************************************************
bogdanm	92:4fc01daae5a5	3	* @file stm32f4xx_ll_fmc.h
bogdanm	92:4fc01daae5a5	4	* @author MCD Application Team
bogdanm	92:4fc01daae5a5	5	* @version V1.1.0
bogdanm	92:4fc01daae5a5	6	* @date 19-June-2014
bogdanm	92:4fc01daae5a5	7	* @brief Header file of FMC HAL module.
bogdanm	92:4fc01daae5a5	8	******************************************************************************
bogdanm	92:4fc01daae5a5	9	* @attention
bogdanm	92:4fc01daae5a5	10	*
bogdanm	92:4fc01daae5a5	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	92:4fc01daae5a5	12	*
bogdanm	92:4fc01daae5a5	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	92:4fc01daae5a5	14	* are permitted provided that the following conditions are met:
bogdanm	92:4fc01daae5a5	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	92:4fc01daae5a5	16	* this list of conditions and the following disclaimer.
bogdanm	92:4fc01daae5a5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	92:4fc01daae5a5	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	92:4fc01daae5a5	19	* and/or other materials provided with the distribution.
bogdanm	92:4fc01daae5a5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	92:4fc01daae5a5	21	* may be used to endorse or promote products derived from this software
bogdanm	92:4fc01daae5a5	22	* without specific prior written permission.
bogdanm	92:4fc01daae5a5	23	*
bogdanm	92:4fc01daae5a5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	92:4fc01daae5a5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	92:4fc01daae5a5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	92:4fc01daae5a5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	92:4fc01daae5a5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	92:4fc01daae5a5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	92:4fc01daae5a5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	92:4fc01daae5a5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	92:4fc01daae5a5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	92:4fc01daae5a5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	92:4fc01daae5a5	34	*
bogdanm	92:4fc01daae5a5	35	******************************************************************************
bogdanm	92:4fc01daae5a5	36	*/
bogdanm	92:4fc01daae5a5	37
bogdanm	92:4fc01daae5a5	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	92:4fc01daae5a5	39	#ifndef __STM32F4xx_LL_FMC_H
bogdanm	92:4fc01daae5a5	40	#define __STM32F4xx_LL_FMC_H
bogdanm	92:4fc01daae5a5	41
bogdanm	92:4fc01daae5a5	42	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	43	extern "C" {
bogdanm	92:4fc01daae5a5	44	#endif
bogdanm	92:4fc01daae5a5	45
bogdanm	92:4fc01daae5a5	46	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	47
bogdanm	92:4fc01daae5a5	48	/* Includes ------------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	49	#include "stm32f4xx_hal_def.h"
bogdanm	92:4fc01daae5a5	50
bogdanm	92:4fc01daae5a5	51	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	92:4fc01daae5a5	52	* @{
bogdanm	92:4fc01daae5a5	53	*/
bogdanm	92:4fc01daae5a5	54
bogdanm	92:4fc01daae5a5	55	/** @addtogroup FMC
bogdanm	92:4fc01daae5a5	56	* @{
bogdanm	92:4fc01daae5a5	57	*/
bogdanm	92:4fc01daae5a5	58
bogdanm	92:4fc01daae5a5	59	/* Exported typedef ----------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	60	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
bogdanm	92:4fc01daae5a5	61	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
bogdanm	92:4fc01daae5a5	62	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
bogdanm	92:4fc01daae5a5	63	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
bogdanm	92:4fc01daae5a5	64	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
bogdanm	92:4fc01daae5a5	65
bogdanm	92:4fc01daae5a5	66	#define FMC_NORSRAM_DEVICE FMC_Bank1
bogdanm	92:4fc01daae5a5	67	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
bogdanm	92:4fc01daae5a5	68	#define FMC_NAND_DEVICE FMC_Bank2_3
bogdanm	92:4fc01daae5a5	69	#define FMC_PCCARD_DEVICE FMC_Bank4
bogdanm	92:4fc01daae5a5	70	#define FMC_SDRAM_DEVICE FMC_Bank5_6
bogdanm	92:4fc01daae5a5	71
bogdanm	92:4fc01daae5a5	72	/**
bogdanm	92:4fc01daae5a5	73	* @brief FMC_NORSRAM Configuration Structure definition
bogdanm	92:4fc01daae5a5	74	*/
bogdanm	92:4fc01daae5a5	75	typedef struct
bogdanm	92:4fc01daae5a5	76	{
bogdanm	92:4fc01daae5a5	77	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	92:4fc01daae5a5	78	This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm	92:4fc01daae5a5	79
bogdanm	92:4fc01daae5a5	80	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm	92:4fc01daae5a5	81	multiplexed on the data bus or not.
bogdanm	92:4fc01daae5a5	82	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm	92:4fc01daae5a5	83
bogdanm	92:4fc01daae5a5	84	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm	92:4fc01daae5a5	85	the corresponding memory device.
bogdanm	92:4fc01daae5a5	86	This parameter can be a value of @ref FMC_Memory_Type */
bogdanm	92:4fc01daae5a5	87
bogdanm	92:4fc01daae5a5	88	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	92:4fc01daae5a5	89	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm	92:4fc01daae5a5	90
bogdanm	92:4fc01daae5a5	91	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm	92:4fc01daae5a5	92	valid only with synchronous burst Flash memories.
bogdanm	92:4fc01daae5a5	93	This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm	92:4fc01daae5a5	94
bogdanm	92:4fc01daae5a5	95	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm	92:4fc01daae5a5	96	the Flash memory in burst mode.
bogdanm	92:4fc01daae5a5	97	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm	92:4fc01daae5a5	98
bogdanm	92:4fc01daae5a5	99	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm	92:4fc01daae5a5	100	memory, valid only when accessing Flash memories in burst mode.
bogdanm	92:4fc01daae5a5	101	This parameter can be a value of @ref FMC_Wrap_Mode */
bogdanm	92:4fc01daae5a5	102
bogdanm	92:4fc01daae5a5	103	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm	92:4fc01daae5a5	104	clock cycle before the wait state or during the wait state,
bogdanm	92:4fc01daae5a5	105	valid only when accessing memories in burst mode.
bogdanm	92:4fc01daae5a5	106	This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm	92:4fc01daae5a5	107
bogdanm	92:4fc01daae5a5	108	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
bogdanm	92:4fc01daae5a5	109	This parameter can be a value of @ref FMC_Write_Operation */
bogdanm	92:4fc01daae5a5	110
bogdanm	92:4fc01daae5a5	111	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm	92:4fc01daae5a5	112	signal, valid for Flash memory access in burst mode.
bogdanm	92:4fc01daae5a5	113	This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm	92:4fc01daae5a5	114
bogdanm	92:4fc01daae5a5	115	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm	92:4fc01daae5a5	116	This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm	92:4fc01daae5a5	117
bogdanm	92:4fc01daae5a5	118	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm	92:4fc01daae5a5	119	valid only with asynchronous Flash memories.
bogdanm	92:4fc01daae5a5	120	This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm	92:4fc01daae5a5	121
bogdanm	92:4fc01daae5a5	122	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	92:4fc01daae5a5	123	This parameter can be a value of @ref FMC_Write_Burst */
bogdanm	92:4fc01daae5a5	124
bogdanm	92:4fc01daae5a5	125	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
bogdanm	92:4fc01daae5a5	126	This parameter is only enabled through the FMC_BCR1 register, and don't care
bogdanm	92:4fc01daae5a5	127	through FMC_BCR2..4 registers.
bogdanm	92:4fc01daae5a5	128	This parameter can be a value of @ref FMC_Continous_Clock */
bogdanm	92:4fc01daae5a5	129
bogdanm	92:4fc01daae5a5	130	}FMC_NORSRAM_InitTypeDef;
bogdanm	92:4fc01daae5a5	131
bogdanm	92:4fc01daae5a5	132	/**
bogdanm	92:4fc01daae5a5	133	* @brief FMC_NORSRAM Timing parameters structure definition
bogdanm	92:4fc01daae5a5	134	*/
bogdanm	92:4fc01daae5a5	135	typedef struct
bogdanm	92:4fc01daae5a5	136	{
bogdanm	92:4fc01daae5a5	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	92:4fc01daae5a5	138	the duration of the address setup time.
bogdanm	92:4fc01daae5a5	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	140	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	92:4fc01daae5a5	141
bogdanm	92:4fc01daae5a5	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	92:4fc01daae5a5	143	the duration of the address hold time.
bogdanm	92:4fc01daae5a5	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	145	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	92:4fc01daae5a5	146
bogdanm	92:4fc01daae5a5	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	92:4fc01daae5a5	148	the duration of the data setup time.
bogdanm	92:4fc01daae5a5	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm	92:4fc01daae5a5	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm	92:4fc01daae5a5	151	NOR Flash memories. */
bogdanm	92:4fc01daae5a5	152
bogdanm	92:4fc01daae5a5	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm	92:4fc01daae5a5	154	the duration of the bus turnaround.
bogdanm	92:4fc01daae5a5	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	156	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	92:4fc01daae5a5	157
bogdanm	92:4fc01daae5a5	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm	92:4fc01daae5a5	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm	92:4fc01daae5a5	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm	92:4fc01daae5a5	161	accesses. */
bogdanm	92:4fc01daae5a5	162
bogdanm	92:4fc01daae5a5	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm	92:4fc01daae5a5	164	to the memory before getting the first data.
bogdanm	92:4fc01daae5a5	165	The parameter value depends on the memory type as shown below:
bogdanm	92:4fc01daae5a5	166	- It must be set to 0 in case of a CRAM
bogdanm	92:4fc01daae5a5	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm	92:4fc01daae5a5	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm	92:4fc01daae5a5	169	with synchronous burst mode enable */
bogdanm	92:4fc01daae5a5	170
bogdanm	92:4fc01daae5a5	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm	92:4fc01daae5a5	172	This parameter can be a value of @ref FMC_Access_Mode */
bogdanm	92:4fc01daae5a5	173	}FMC_NORSRAM_TimingTypeDef;
bogdanm	92:4fc01daae5a5	174
bogdanm	92:4fc01daae5a5	175	/**
bogdanm	92:4fc01daae5a5	176	* @brief FMC_NAND Configuration Structure definition
bogdanm	92:4fc01daae5a5	177	*/
bogdanm	92:4fc01daae5a5	178	typedef struct
bogdanm	92:4fc01daae5a5	179	{
bogdanm	92:4fc01daae5a5	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	92:4fc01daae5a5	181	This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm	92:4fc01daae5a5	182
bogdanm	92:4fc01daae5a5	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm	92:4fc01daae5a5	184	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	92:4fc01daae5a5	185
bogdanm	92:4fc01daae5a5	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	92:4fc01daae5a5	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm	92:4fc01daae5a5	188
bogdanm	92:4fc01daae5a5	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm	92:4fc01daae5a5	190	This parameter can be any value of @ref FMC_ECC */
bogdanm	92:4fc01daae5a5	191
bogdanm	92:4fc01daae5a5	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm	92:4fc01daae5a5	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm	92:4fc01daae5a5	194
bogdanm	92:4fc01daae5a5	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	92:4fc01daae5a5	196	delay between CLE low and RE low.
bogdanm	92:4fc01daae5a5	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	198
bogdanm	92:4fc01daae5a5	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	92:4fc01daae5a5	200	delay between ALE low and RE low.
bogdanm	92:4fc01daae5a5	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	202	}FMC_NAND_InitTypeDef;
bogdanm	92:4fc01daae5a5	203
bogdanm	92:4fc01daae5a5	204	/**
bogdanm	92:4fc01daae5a5	205	* @brief FMC_NAND_PCCARD Timing parameters structure definition
bogdanm	92:4fc01daae5a5	206	*/
bogdanm	92:4fc01daae5a5	207	typedef struct
bogdanm	92:4fc01daae5a5	208	{
bogdanm	92:4fc01daae5a5	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm	92:4fc01daae5a5	210	the command assertion for NAND-Flash read or write access
bogdanm	92:4fc01daae5a5	211	to common/Attribute or I/O memory space (depending on
bogdanm	92:4fc01daae5a5	212	the memory space timing to be configured).
bogdanm	92:4fc01daae5a5	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	214
bogdanm	92:4fc01daae5a5	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm	92:4fc01daae5a5	216	command for NAND-Flash read or write access to
bogdanm	92:4fc01daae5a5	217	common/Attribute or I/O memory space (depending on the
bogdanm	92:4fc01daae5a5	218	memory space timing to be configured).
bogdanm	92:4fc01daae5a5	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	220
bogdanm	92:4fc01daae5a5	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm	92:4fc01daae5a5	222	(and data for write access) after the command de-assertion
bogdanm	92:4fc01daae5a5	223	for NAND-Flash read or write access to common/Attribute
bogdanm	92:4fc01daae5a5	224	or I/O memory space (depending on the memory space timing
bogdanm	92:4fc01daae5a5	225	to be configured).
bogdanm	92:4fc01daae5a5	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	227
bogdanm	92:4fc01daae5a5	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm	92:4fc01daae5a5	229	data bus is kept in HiZ after the start of a NAND-Flash
bogdanm	92:4fc01daae5a5	230	write access to common/Attribute or I/O memory space (depending
bogdanm	92:4fc01daae5a5	231	on the memory space timing to be configured).
bogdanm	92:4fc01daae5a5	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	233	}FMC_NAND_PCC_TimingTypeDef;
bogdanm	92:4fc01daae5a5	234
bogdanm	92:4fc01daae5a5	235	/**
bogdanm	92:4fc01daae5a5	236	* @brief FMC_NAND Configuration Structure definition
bogdanm	92:4fc01daae5a5	237	*/
bogdanm	92:4fc01daae5a5	238	typedef struct
bogdanm	92:4fc01daae5a5	239	{
bogdanm	92:4fc01daae5a5	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm	92:4fc01daae5a5	241	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	92:4fc01daae5a5	242
bogdanm	92:4fc01daae5a5	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	92:4fc01daae5a5	244	delay between CLE low and RE low.
bogdanm	92:4fc01daae5a5	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	246
bogdanm	92:4fc01daae5a5	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	92:4fc01daae5a5	248	delay between ALE low and RE low.
bogdanm	92:4fc01daae5a5	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	92:4fc01daae5a5	250	}FMC_PCCARD_InitTypeDef;
bogdanm	92:4fc01daae5a5	251
bogdanm	92:4fc01daae5a5	252	/**
bogdanm	92:4fc01daae5a5	253	* @brief FMC_SDRAM Configuration Structure definition
bogdanm	92:4fc01daae5a5	254	*/
bogdanm	92:4fc01daae5a5	255	typedef struct
bogdanm	92:4fc01daae5a5	256	{
bogdanm	92:4fc01daae5a5	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
bogdanm	92:4fc01daae5a5	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
bogdanm	92:4fc01daae5a5	259
bogdanm	92:4fc01daae5a5	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
bogdanm	92:4fc01daae5a5	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
bogdanm	92:4fc01daae5a5	262
bogdanm	92:4fc01daae5a5	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
bogdanm	92:4fc01daae5a5	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
bogdanm	92:4fc01daae5a5	265
bogdanm	92:4fc01daae5a5	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
bogdanm	92:4fc01daae5a5	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
bogdanm	92:4fc01daae5a5	268
bogdanm	92:4fc01daae5a5	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
bogdanm	92:4fc01daae5a5	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
bogdanm	92:4fc01daae5a5	271
bogdanm	92:4fc01daae5a5	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
bogdanm	92:4fc01daae5a5	274
bogdanm	92:4fc01daae5a5	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
bogdanm	92:4fc01daae5a5	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
bogdanm	92:4fc01daae5a5	277
bogdanm	92:4fc01daae5a5	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
bogdanm	92:4fc01daae5a5	279	to disable the clock before changing frequency.
bogdanm	92:4fc01daae5a5	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
bogdanm	92:4fc01daae5a5	281
bogdanm	92:4fc01daae5a5	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
bogdanm	92:4fc01daae5a5	283	commands during the CAS latency and stores data in the Read FIFO.
bogdanm	92:4fc01daae5a5	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
bogdanm	92:4fc01daae5a5	285
bogdanm	92:4fc01daae5a5	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
bogdanm	92:4fc01daae5a5	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
bogdanm	92:4fc01daae5a5	288	}FMC_SDRAM_InitTypeDef;
bogdanm	92:4fc01daae5a5	289
bogdanm	92:4fc01daae5a5	290	/**
bogdanm	92:4fc01daae5a5	291	* @brief FMC_SDRAM Timing parameters structure definition
bogdanm	92:4fc01daae5a5	292	*/
bogdanm	92:4fc01daae5a5	293	typedef struct
bogdanm	92:4fc01daae5a5	294	{
bogdanm	92:4fc01daae5a5	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
bogdanm	92:4fc01daae5a5	296	an active or Refresh command in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	298
bogdanm	92:4fc01daae5a5	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
bogdanm	92:4fc01daae5a5	300	issuing the Activate command in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	302
bogdanm	92:4fc01daae5a5	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
bogdanm	92:4fc01daae5a5	304	cycles.
bogdanm	92:4fc01daae5a5	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	306
bogdanm	92:4fc01daae5a5	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
bogdanm	92:4fc01daae5a5	308	and the delay between two consecutive Refresh commands in number of
bogdanm	92:4fc01daae5a5	309	memory clock cycles.
bogdanm	92:4fc01daae5a5	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	311
bogdanm	92:4fc01daae5a5	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	314
bogdanm	92:4fc01daae5a5	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
bogdanm	92:4fc01daae5a5	316	in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	318
bogdanm	92:4fc01daae5a5	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
bogdanm	92:4fc01daae5a5	320	command in number of memory clock cycles.
bogdanm	92:4fc01daae5a5	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	322	}FMC_SDRAM_TimingTypeDef;
bogdanm	92:4fc01daae5a5	323
bogdanm	92:4fc01daae5a5	324	/**
bogdanm	92:4fc01daae5a5	325	* @brief SDRAM command parameters structure definition
bogdanm	92:4fc01daae5a5	326	*/
bogdanm	92:4fc01daae5a5	327	typedef struct
bogdanm	92:4fc01daae5a5	328	{
bogdanm	92:4fc01daae5a5	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
bogdanm	92:4fc01daae5a5	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
bogdanm	92:4fc01daae5a5	331
bogdanm	92:4fc01daae5a5	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
bogdanm	92:4fc01daae5a5	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
bogdanm	92:4fc01daae5a5	334
bogdanm	92:4fc01daae5a5	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
bogdanm	92:4fc01daae5a5	336	in auto refresh mode.
bogdanm	92:4fc01daae5a5	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	92:4fc01daae5a5	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
bogdanm	92:4fc01daae5a5	339	}FMC_SDRAM_CommandTypeDef;
bogdanm	92:4fc01daae5a5	340
bogdanm	92:4fc01daae5a5	341	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	342
bogdanm	92:4fc01daae5a5	343	/** @defgroup FMC_NOR_SRAM_Controller
bogdanm	92:4fc01daae5a5	344	* @{
bogdanm	92:4fc01daae5a5	345	*/
bogdanm	92:4fc01daae5a5	346
bogdanm	92:4fc01daae5a5	347	/** @defgroup FMC_NORSRAM_Bank
bogdanm	92:4fc01daae5a5	348	* @{
bogdanm	92:4fc01daae5a5	349	*/
bogdanm	92:4fc01daae5a5	350	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	351	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	352	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	353	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm	92:4fc01daae5a5	354
bogdanm	92:4fc01daae5a5	355	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
bogdanm	92:4fc01daae5a5	356	((BANK) == FMC_NORSRAM_BANK2) \|\| \
bogdanm	92:4fc01daae5a5	357	((BANK) == FMC_NORSRAM_BANK3) \|\| \
bogdanm	92:4fc01daae5a5	358	((BANK) == FMC_NORSRAM_BANK4))
bogdanm	92:4fc01daae5a5	359	/**
bogdanm	92:4fc01daae5a5	360	* @}
bogdanm	92:4fc01daae5a5	361	*/
bogdanm	92:4fc01daae5a5	362
bogdanm	92:4fc01daae5a5	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing
bogdanm	92:4fc01daae5a5	364	* @{
bogdanm	92:4fc01daae5a5	365	*/
bogdanm	92:4fc01daae5a5	366	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	367	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	368
bogdanm	92:4fc01daae5a5	369	#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	370	((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
bogdanm	92:4fc01daae5a5	371	/**
bogdanm	92:4fc01daae5a5	372	* @}
bogdanm	92:4fc01daae5a5	373	*/
bogdanm	92:4fc01daae5a5	374
bogdanm	92:4fc01daae5a5	375	/** @defgroup FMC_Memory_Type
bogdanm	92:4fc01daae5a5	376	* @{
bogdanm	92:4fc01daae5a5	377	*/
bogdanm	92:4fc01daae5a5	378	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	379	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	380	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	381
bogdanm	92:4fc01daae5a5	382	#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) \|\| \
bogdanm	92:4fc01daae5a5	383	((MEMORY) == FMC_MEMORY_TYPE_PSRAM)\|\| \
bogdanm	92:4fc01daae5a5	384	((MEMORY) == FMC_MEMORY_TYPE_NOR))
bogdanm	92:4fc01daae5a5	385	/**
bogdanm	92:4fc01daae5a5	386	* @}
bogdanm	92:4fc01daae5a5	387	*/
bogdanm	92:4fc01daae5a5	388
bogdanm	92:4fc01daae5a5	389	/** @defgroup FMC_NORSRAM_Data_Width
bogdanm	92:4fc01daae5a5	390	* @{
bogdanm	92:4fc01daae5a5	391	*/
bogdanm	92:4fc01daae5a5	392	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	393	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	394	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	395
bogdanm	92:4fc01daae5a5	396	#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
bogdanm	92:4fc01daae5a5	397	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
bogdanm	92:4fc01daae5a5	398	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
bogdanm	92:4fc01daae5a5	399	/**
bogdanm	92:4fc01daae5a5	400	* @}
bogdanm	92:4fc01daae5a5	401	*/
bogdanm	92:4fc01daae5a5	402
bogdanm	92:4fc01daae5a5	403	/** @defgroup FMC_NORSRAM_Flash_Access
bogdanm	92:4fc01daae5a5	404	* @{
bogdanm	92:4fc01daae5a5	405	*/
bogdanm	92:4fc01daae5a5	406	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	407	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	408	/**
bogdanm	92:4fc01daae5a5	409	* @}
bogdanm	92:4fc01daae5a5	410	*/
bogdanm	92:4fc01daae5a5	411
bogdanm	92:4fc01daae5a5	412	/** @defgroup FMC_Burst_Access_Mode
bogdanm	92:4fc01daae5a5	413	* @{
bogdanm	92:4fc01daae5a5	414	*/
bogdanm	92:4fc01daae5a5	415	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	416	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	417
bogdanm	92:4fc01daae5a5	418	#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	419	((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
bogdanm	92:4fc01daae5a5	420	/**
bogdanm	92:4fc01daae5a5	421	* @}
bogdanm	92:4fc01daae5a5	422	*/
bogdanm	92:4fc01daae5a5	423
bogdanm	92:4fc01daae5a5	424
bogdanm	92:4fc01daae5a5	425	/** @defgroup FMC_Wait_Signal_Polarity
bogdanm	92:4fc01daae5a5	426	* @{
bogdanm	92:4fc01daae5a5	427	*/
bogdanm	92:4fc01daae5a5	428	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	429	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	430
bogdanm	92:4fc01daae5a5	431	#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
bogdanm	92:4fc01daae5a5	432	((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
bogdanm	92:4fc01daae5a5	433	/**
bogdanm	92:4fc01daae5a5	434	* @}
bogdanm	92:4fc01daae5a5	435	*/
bogdanm	92:4fc01daae5a5	436
bogdanm	92:4fc01daae5a5	437	/** @defgroup FMC_Wrap_Mode
bogdanm	92:4fc01daae5a5	438	* @{
bogdanm	92:4fc01daae5a5	439	*/
bogdanm	92:4fc01daae5a5	440	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	441	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
bogdanm	92:4fc01daae5a5	442
bogdanm	92:4fc01daae5a5	443	#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	444	((MODE) == FMC_WRAP_MODE_ENABLE))
bogdanm	92:4fc01daae5a5	445	/**
bogdanm	92:4fc01daae5a5	446	* @}
bogdanm	92:4fc01daae5a5	447	*/
bogdanm	92:4fc01daae5a5	448
bogdanm	92:4fc01daae5a5	449	/** @defgroup FMC_Wait_Timing
bogdanm	92:4fc01daae5a5	450	* @{
bogdanm	92:4fc01daae5a5	451	*/
bogdanm	92:4fc01daae5a5	452	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	453	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
bogdanm	92:4fc01daae5a5	454
bogdanm	92:4fc01daae5a5	455	#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
bogdanm	92:4fc01daae5a5	456	((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
bogdanm	92:4fc01daae5a5	457	/**
bogdanm	92:4fc01daae5a5	458	* @}
bogdanm	92:4fc01daae5a5	459	*/
bogdanm	92:4fc01daae5a5	460
bogdanm	92:4fc01daae5a5	461	/** @defgroup FMC_Write_Operation
bogdanm	92:4fc01daae5a5	462	* @{
bogdanm	92:4fc01daae5a5	463	*/
bogdanm	92:4fc01daae5a5	464	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	465	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm	92:4fc01daae5a5	466
bogdanm	92:4fc01daae5a5	467	#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	468	((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
bogdanm	92:4fc01daae5a5	469	/**
bogdanm	92:4fc01daae5a5	470	* @}
bogdanm	92:4fc01daae5a5	471	*/
bogdanm	92:4fc01daae5a5	472
bogdanm	92:4fc01daae5a5	473	/** @defgroup FMC_Wait_Signal
bogdanm	92:4fc01daae5a5	474	* @{
bogdanm	92:4fc01daae5a5	475	*/
bogdanm	92:4fc01daae5a5	476	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	477	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
bogdanm	92:4fc01daae5a5	478
bogdanm	92:4fc01daae5a5	479	#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	480	((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
bogdanm	92:4fc01daae5a5	481	/**
bogdanm	92:4fc01daae5a5	482	* @}
bogdanm	92:4fc01daae5a5	483	*/
bogdanm	92:4fc01daae5a5	484
bogdanm	92:4fc01daae5a5	485	/** @defgroup FMC_Extended_Mode
bogdanm	92:4fc01daae5a5	486	* @{
bogdanm	92:4fc01daae5a5	487	*/
bogdanm	92:4fc01daae5a5	488	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	489	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
bogdanm	92:4fc01daae5a5	490
bogdanm	92:4fc01daae5a5	491	#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	492	((MODE) == FMC_EXTENDED_MODE_ENABLE))
bogdanm	92:4fc01daae5a5	493	/**
bogdanm	92:4fc01daae5a5	494	* @}
bogdanm	92:4fc01daae5a5	495	*/
bogdanm	92:4fc01daae5a5	496
bogdanm	92:4fc01daae5a5	497	/** @defgroup FMC_AsynchronousWait
bogdanm	92:4fc01daae5a5	498	* @{
bogdanm	92:4fc01daae5a5	499	*/
bogdanm	92:4fc01daae5a5	500	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	501	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm	92:4fc01daae5a5	502
bogdanm	92:4fc01daae5a5	503	#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	504	((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
bogdanm	92:4fc01daae5a5	505	/**
bogdanm	92:4fc01daae5a5	506	* @}
bogdanm	92:4fc01daae5a5	507	*/
bogdanm	92:4fc01daae5a5	508
bogdanm	92:4fc01daae5a5	509	/** @defgroup FMC_Write_Burst
bogdanm	92:4fc01daae5a5	510	* @{
bogdanm	92:4fc01daae5a5	511	*/
bogdanm	92:4fc01daae5a5	512	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	513	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm	92:4fc01daae5a5	514
bogdanm	92:4fc01daae5a5	515	#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	516	((BURST) == FMC_WRITE_BURST_ENABLE))
bogdanm	92:4fc01daae5a5	517	/**
bogdanm	92:4fc01daae5a5	518	* @}
bogdanm	92:4fc01daae5a5	519	*/
bogdanm	92:4fc01daae5a5	520
bogdanm	92:4fc01daae5a5	521	/** @defgroup FMC_Continous_Clock
bogdanm	92:4fc01daae5a5	522	* @{
bogdanm	92:4fc01daae5a5	523	*/
bogdanm	92:4fc01daae5a5	524	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	525	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm	92:4fc01daae5a5	526
bogdanm	92:4fc01daae5a5	527	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
bogdanm	92:4fc01daae5a5	528	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
bogdanm	92:4fc01daae5a5	529	/**
bogdanm	92:4fc01daae5a5	530	* @}
bogdanm	92:4fc01daae5a5	531	*/
bogdanm	92:4fc01daae5a5	532
bogdanm	92:4fc01daae5a5	533	/** @defgroup FMC_Address_Setup_Time
bogdanm	92:4fc01daae5a5	534	* @{
bogdanm	92:4fc01daae5a5	535	*/
bogdanm	92:4fc01daae5a5	536	#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
bogdanm	92:4fc01daae5a5	537	/**
bogdanm	92:4fc01daae5a5	538	* @}
bogdanm	92:4fc01daae5a5	539	*/
bogdanm	92:4fc01daae5a5	540
bogdanm	92:4fc01daae5a5	541	/** @defgroup FMC_Address_Hold_Time
bogdanm	92:4fc01daae5a5	542	* @{
bogdanm	92:4fc01daae5a5	543	*/
bogdanm	92:4fc01daae5a5	544	#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
bogdanm	92:4fc01daae5a5	545	/**
bogdanm	92:4fc01daae5a5	546	* @}
bogdanm	92:4fc01daae5a5	547	*/
bogdanm	92:4fc01daae5a5	548
bogdanm	92:4fc01daae5a5	549	/** @defgroup FMC_Data_Setup_Time
bogdanm	92:4fc01daae5a5	550	* @{
bogdanm	92:4fc01daae5a5	551	*/
bogdanm	92:4fc01daae5a5	552	#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
bogdanm	92:4fc01daae5a5	553	/**
bogdanm	92:4fc01daae5a5	554	* @}
bogdanm	92:4fc01daae5a5	555	*/
bogdanm	92:4fc01daae5a5	556
bogdanm	92:4fc01daae5a5	557	/** @defgroup FMC_Bus_Turn_around_Duration
bogdanm	92:4fc01daae5a5	558	* @{
bogdanm	92:4fc01daae5a5	559	*/
bogdanm	92:4fc01daae5a5	560	#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
bogdanm	92:4fc01daae5a5	561	/**
bogdanm	92:4fc01daae5a5	562	* @}
bogdanm	92:4fc01daae5a5	563	*/
bogdanm	92:4fc01daae5a5	564
bogdanm	92:4fc01daae5a5	565	/** @defgroup FMC_CLK_Division
bogdanm	92:4fc01daae5a5	566	* @{
bogdanm	92:4fc01daae5a5	567	*/
bogdanm	92:4fc01daae5a5	568	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
bogdanm	92:4fc01daae5a5	569	/**
bogdanm	92:4fc01daae5a5	570	* @}
bogdanm	92:4fc01daae5a5	571	*/
bogdanm	92:4fc01daae5a5	572
bogdanm	92:4fc01daae5a5	573	/** @defgroup FMC_Data_Latency
bogdanm	92:4fc01daae5a5	574	* @{
bogdanm	92:4fc01daae5a5	575	*/
bogdanm	92:4fc01daae5a5	576	#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
bogdanm	92:4fc01daae5a5	577	/**
bogdanm	92:4fc01daae5a5	578	* @}
bogdanm	92:4fc01daae5a5	579	*/
bogdanm	92:4fc01daae5a5	580
bogdanm	92:4fc01daae5a5	581	/** @defgroup FMC_Access_Mode
bogdanm	92:4fc01daae5a5	582	* @{
bogdanm	92:4fc01daae5a5	583	*/
bogdanm	92:4fc01daae5a5	584	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	585	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm	92:4fc01daae5a5	586	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm	92:4fc01daae5a5	587	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm	92:4fc01daae5a5	588
bogdanm	92:4fc01daae5a5	589	#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) \|\| \
bogdanm	92:4fc01daae5a5	590	((MODE) == FMC_ACCESS_MODE_B) \|\| \
bogdanm	92:4fc01daae5a5	591	((MODE) == FMC_ACCESS_MODE_C) \|\| \
bogdanm	92:4fc01daae5a5	592	((MODE) == FMC_ACCESS_MODE_D))
bogdanm	92:4fc01daae5a5	593	/**
bogdanm	92:4fc01daae5a5	594	* @}
bogdanm	92:4fc01daae5a5	595	*/
bogdanm	92:4fc01daae5a5	596
bogdanm	92:4fc01daae5a5	597	/**
bogdanm	92:4fc01daae5a5	598	* @}
bogdanm	92:4fc01daae5a5	599	*/
bogdanm	92:4fc01daae5a5	600
bogdanm	92:4fc01daae5a5	601	/** @defgroup FMC_NAND_Controller
bogdanm	92:4fc01daae5a5	602	* @{
bogdanm	92:4fc01daae5a5	603	*/
bogdanm	92:4fc01daae5a5	604
bogdanm	92:4fc01daae5a5	605	/** @defgroup FMC_NAND_Bank
bogdanm	92:4fc01daae5a5	606	* @{
bogdanm	92:4fc01daae5a5	607	*/
bogdanm	92:4fc01daae5a5	608	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	609	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	610
bogdanm	92:4fc01daae5a5	611	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
bogdanm	92:4fc01daae5a5	612	((BANK) == FMC_NAND_BANK3))
bogdanm	92:4fc01daae5a5	613	/**
bogdanm	92:4fc01daae5a5	614	* @}
bogdanm	92:4fc01daae5a5	615	*/
bogdanm	92:4fc01daae5a5	616
bogdanm	92:4fc01daae5a5	617	/** @defgroup FMC_Wait_feature
bogdanm	92:4fc01daae5a5	618	* @{
bogdanm	92:4fc01daae5a5	619	*/
bogdanm	92:4fc01daae5a5	620	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	621	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	622
bogdanm	92:4fc01daae5a5	623	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	624	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
bogdanm	92:4fc01daae5a5	625	/**
bogdanm	92:4fc01daae5a5	626	* @}
bogdanm	92:4fc01daae5a5	627	*/
bogdanm	92:4fc01daae5a5	628
bogdanm	92:4fc01daae5a5	629	/** @defgroup FMC_PCR_Memory_Type
bogdanm	92:4fc01daae5a5	630	* @{
bogdanm	92:4fc01daae5a5	631	*/
bogdanm	92:4fc01daae5a5	632	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	633	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	634	/**
bogdanm	92:4fc01daae5a5	635	* @}
bogdanm	92:4fc01daae5a5	636	*/
bogdanm	92:4fc01daae5a5	637
bogdanm	92:4fc01daae5a5	638	/** @defgroup FMC_NAND_Data_Width
bogdanm	92:4fc01daae5a5	639	* @{
bogdanm	92:4fc01daae5a5	640	*/
bogdanm	92:4fc01daae5a5	641	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	642	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	643
bogdanm	92:4fc01daae5a5	644	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
bogdanm	92:4fc01daae5a5	645	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
bogdanm	92:4fc01daae5a5	646	/**
bogdanm	92:4fc01daae5a5	647	* @}
bogdanm	92:4fc01daae5a5	648	*/
bogdanm	92:4fc01daae5a5	649
bogdanm	92:4fc01daae5a5	650	/** @defgroup FMC_ECC
bogdanm	92:4fc01daae5a5	651	* @{
bogdanm	92:4fc01daae5a5	652	*/
bogdanm	92:4fc01daae5a5	653	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	654	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	655
bogdanm	92:4fc01daae5a5	656	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	657	((STATE) == FMC_NAND_ECC_ENABLE))
bogdanm	92:4fc01daae5a5	658	/**
bogdanm	92:4fc01daae5a5	659	* @}
bogdanm	92:4fc01daae5a5	660	*/
bogdanm	92:4fc01daae5a5	661
bogdanm	92:4fc01daae5a5	662	/** @defgroup FMC_ECC_Page_Size
bogdanm	92:4fc01daae5a5	663	* @{
bogdanm	92:4fc01daae5a5	664	*/
bogdanm	92:4fc01daae5a5	665	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	666	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm	92:4fc01daae5a5	667	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm	92:4fc01daae5a5	668	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm	92:4fc01daae5a5	669	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm	92:4fc01daae5a5	670	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm	92:4fc01daae5a5	671
bogdanm	92:4fc01daae5a5	672	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
bogdanm	92:4fc01daae5a5	673	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
bogdanm	92:4fc01daae5a5	674	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
bogdanm	92:4fc01daae5a5	675	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
bogdanm	92:4fc01daae5a5	676	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
bogdanm	92:4fc01daae5a5	677	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
bogdanm	92:4fc01daae5a5	678	/**
bogdanm	92:4fc01daae5a5	679	* @}
bogdanm	92:4fc01daae5a5	680	*/
bogdanm	92:4fc01daae5a5	681
bogdanm	92:4fc01daae5a5	682	/** @defgroup FMC_TCLR_Setup_Time
bogdanm	92:4fc01daae5a5	683	* @{
bogdanm	92:4fc01daae5a5	684	*/
bogdanm	92:4fc01daae5a5	685	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
bogdanm	92:4fc01daae5a5	686	/**
bogdanm	92:4fc01daae5a5	687	* @}
bogdanm	92:4fc01daae5a5	688	*/
bogdanm	92:4fc01daae5a5	689
bogdanm	92:4fc01daae5a5	690	/** @defgroup FMC_TAR_Setup_Time
bogdanm	92:4fc01daae5a5	691	* @{
bogdanm	92:4fc01daae5a5	692	*/
bogdanm	92:4fc01daae5a5	693	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
bogdanm	92:4fc01daae5a5	694	/**
bogdanm	92:4fc01daae5a5	695	* @}
bogdanm	92:4fc01daae5a5	696	*/
bogdanm	92:4fc01daae5a5	697
bogdanm	92:4fc01daae5a5	698	/** @defgroup FMC_Setup_Time
bogdanm	92:4fc01daae5a5	699	* @{
bogdanm	92:4fc01daae5a5	700	*/
bogdanm	92:4fc01daae5a5	701	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
bogdanm	92:4fc01daae5a5	702	/**
bogdanm	92:4fc01daae5a5	703	* @}
bogdanm	92:4fc01daae5a5	704	*/
bogdanm	92:4fc01daae5a5	705
bogdanm	92:4fc01daae5a5	706	/** @defgroup FMC_Wait_Setup_Time
bogdanm	92:4fc01daae5a5	707	* @{
bogdanm	92:4fc01daae5a5	708	*/
bogdanm	92:4fc01daae5a5	709	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
bogdanm	92:4fc01daae5a5	710	/**
bogdanm	92:4fc01daae5a5	711	* @}
bogdanm	92:4fc01daae5a5	712	*/
bogdanm	92:4fc01daae5a5	713
bogdanm	92:4fc01daae5a5	714	/** @defgroup FMC_Hold_Setup_Time
bogdanm	92:4fc01daae5a5	715	* @{
bogdanm	92:4fc01daae5a5	716	*/
bogdanm	92:4fc01daae5a5	717	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
bogdanm	92:4fc01daae5a5	718	/**
bogdanm	92:4fc01daae5a5	719	* @}
bogdanm	92:4fc01daae5a5	720	*/
bogdanm	92:4fc01daae5a5	721
bogdanm	92:4fc01daae5a5	722	/** @defgroup FMC_HiZ_Setup_Time
bogdanm	92:4fc01daae5a5	723	* @{
bogdanm	92:4fc01daae5a5	724	*/
bogdanm	92:4fc01daae5a5	725	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
bogdanm	92:4fc01daae5a5	726	/**
bogdanm	92:4fc01daae5a5	727	* @}
bogdanm	92:4fc01daae5a5	728	*/
bogdanm	92:4fc01daae5a5	729
bogdanm	92:4fc01daae5a5	730	/**
bogdanm	92:4fc01daae5a5	731	* @}
bogdanm	92:4fc01daae5a5	732	*/
bogdanm	92:4fc01daae5a5	733
bogdanm	92:4fc01daae5a5	734	/** @defgroup FMC_SDRAM_Controller
bogdanm	92:4fc01daae5a5	735	* @{
bogdanm	92:4fc01daae5a5	736	*/
bogdanm	92:4fc01daae5a5	737
bogdanm	92:4fc01daae5a5	738	/** @defgroup FMC_SDRAM_Bank
bogdanm	92:4fc01daae5a5	739	* @{
bogdanm	92:4fc01daae5a5	740	*/
bogdanm	92:4fc01daae5a5	741	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	742	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	743
bogdanm	92:4fc01daae5a5	744	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
bogdanm	92:4fc01daae5a5	745	((BANK) == FMC_SDRAM_BANK2))
bogdanm	92:4fc01daae5a5	746	/**
bogdanm	92:4fc01daae5a5	747	* @}
bogdanm	92:4fc01daae5a5	748	*/
bogdanm	92:4fc01daae5a5	749
bogdanm	92:4fc01daae5a5	750	/** @defgroup FMC_SDRAM_Column_Bits_number
bogdanm	92:4fc01daae5a5	751	* @{
bogdanm	92:4fc01daae5a5	752	*/
bogdanm	92:4fc01daae5a5	753	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	754	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	755	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	756	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
bogdanm	92:4fc01daae5a5	757
bogdanm	92:4fc01daae5a5	758	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
bogdanm	92:4fc01daae5a5	759	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
bogdanm	92:4fc01daae5a5	760	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
bogdanm	92:4fc01daae5a5	761	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
bogdanm	92:4fc01daae5a5	762	/**
bogdanm	92:4fc01daae5a5	763	* @}
bogdanm	92:4fc01daae5a5	764	*/
bogdanm	92:4fc01daae5a5	765
bogdanm	92:4fc01daae5a5	766	/** @defgroup FMC_SDRAM_Row_Bits_number
bogdanm	92:4fc01daae5a5	767	* @{
bogdanm	92:4fc01daae5a5	768	*/
bogdanm	92:4fc01daae5a5	769	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	770	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	771	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	772
bogdanm	92:4fc01daae5a5	773	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
bogdanm	92:4fc01daae5a5	774	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
bogdanm	92:4fc01daae5a5	775	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
bogdanm	92:4fc01daae5a5	776	/**
bogdanm	92:4fc01daae5a5	777	* @}
bogdanm	92:4fc01daae5a5	778	*/
bogdanm	92:4fc01daae5a5	779
bogdanm	92:4fc01daae5a5	780	/** @defgroup FMC_SDRAM_Memory_Bus_Width
bogdanm	92:4fc01daae5a5	781	* @{
bogdanm	92:4fc01daae5a5	782	*/
bogdanm	92:4fc01daae5a5	783	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	784	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	785	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	786
bogdanm	92:4fc01daae5a5	787	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
bogdanm	92:4fc01daae5a5	788	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
bogdanm	92:4fc01daae5a5	789	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
bogdanm	92:4fc01daae5a5	790	/**
bogdanm	92:4fc01daae5a5	791	* @}
bogdanm	92:4fc01daae5a5	792	*/
bogdanm	92:4fc01daae5a5	793
bogdanm	92:4fc01daae5a5	794	/** @defgroup FMC_SDRAM_Internal_Banks_Number
bogdanm	92:4fc01daae5a5	795	* @{
bogdanm	92:4fc01daae5a5	796	*/
bogdanm	92:4fc01daae5a5	797	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	798	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	799
bogdanm	92:4fc01daae5a5	800	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
bogdanm	92:4fc01daae5a5	801	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
bogdanm	92:4fc01daae5a5	802	/**
bogdanm	92:4fc01daae5a5	803	* @}
bogdanm	92:4fc01daae5a5	804	*/
bogdanm	92:4fc01daae5a5	805
bogdanm	92:4fc01daae5a5	806	/** @defgroup FMC_SDRAM_CAS_Latency
bogdanm	92:4fc01daae5a5	807	* @{
bogdanm	92:4fc01daae5a5	808	*/
bogdanm	92:4fc01daae5a5	809	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	810	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	811	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
bogdanm	92:4fc01daae5a5	812
bogdanm	92:4fc01daae5a5	813	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
bogdanm	92:4fc01daae5a5	814	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
bogdanm	92:4fc01daae5a5	815	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
bogdanm	92:4fc01daae5a5	816	/**
bogdanm	92:4fc01daae5a5	817	* @}
bogdanm	92:4fc01daae5a5	818	*/
bogdanm	92:4fc01daae5a5	819
bogdanm	92:4fc01daae5a5	820	/** @defgroup FMC_SDRAM_Write_Protection
bogdanm	92:4fc01daae5a5	821	* @{
bogdanm	92:4fc01daae5a5	822	*/
bogdanm	92:4fc01daae5a5	823	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	824	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	825
bogdanm	92:4fc01daae5a5	826	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	827	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
bogdanm	92:4fc01daae5a5	828	/**
bogdanm	92:4fc01daae5a5	829	* @}
bogdanm	92:4fc01daae5a5	830	*/
bogdanm	92:4fc01daae5a5	831
bogdanm	92:4fc01daae5a5	832	/** @defgroup FMC_SDRAM_Clock_Period
bogdanm	92:4fc01daae5a5	833	* @{
bogdanm	92:4fc01daae5a5	834	*/
bogdanm	92:4fc01daae5a5	835	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	836	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
bogdanm	92:4fc01daae5a5	837	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
bogdanm	92:4fc01daae5a5	838
bogdanm	92:4fc01daae5a5	839	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	840	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
bogdanm	92:4fc01daae5a5	841	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
bogdanm	92:4fc01daae5a5	842	/**
bogdanm	92:4fc01daae5a5	843	* @}
bogdanm	92:4fc01daae5a5	844	*/
bogdanm	92:4fc01daae5a5	845
bogdanm	92:4fc01daae5a5	846	/** @defgroup FMC_SDRAM_Read_Burst
bogdanm	92:4fc01daae5a5	847	* @{
bogdanm	92:4fc01daae5a5	848	*/
bogdanm	92:4fc01daae5a5	849	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	850	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
bogdanm	92:4fc01daae5a5	851
bogdanm	92:4fc01daae5a5	852	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	853	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
bogdanm	92:4fc01daae5a5	854	/**
bogdanm	92:4fc01daae5a5	855	* @}
bogdanm	92:4fc01daae5a5	856	*/
bogdanm	92:4fc01daae5a5	857
bogdanm	92:4fc01daae5a5	858	/** @defgroup FMC_SDRAM_Read_Pipe_Delay
bogdanm	92:4fc01daae5a5	859	* @{
bogdanm	92:4fc01daae5a5	860	*/
bogdanm	92:4fc01daae5a5	861	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	862	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
bogdanm	92:4fc01daae5a5	863	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
bogdanm	92:4fc01daae5a5	864
bogdanm	92:4fc01daae5a5	865	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
bogdanm	92:4fc01daae5a5	866	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
bogdanm	92:4fc01daae5a5	867	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
bogdanm	92:4fc01daae5a5	868	/**
bogdanm	92:4fc01daae5a5	869	* @}
bogdanm	92:4fc01daae5a5	870	*/
bogdanm	92:4fc01daae5a5	871
bogdanm	92:4fc01daae5a5	872	/** @defgroup FMC_SDRAM_LoadToActive_Delay
bogdanm	92:4fc01daae5a5	873	* @{
bogdanm	92:4fc01daae5a5	874	*/
bogdanm	92:4fc01daae5a5	875	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	92:4fc01daae5a5	876	/**
bogdanm	92:4fc01daae5a5	877	* @}
bogdanm	92:4fc01daae5a5	878	*/
bogdanm	92:4fc01daae5a5	879
bogdanm	92:4fc01daae5a5	880	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
bogdanm	92:4fc01daae5a5	881	* @{
bogdanm	92:4fc01daae5a5	882	*/
bogdanm	92:4fc01daae5a5	883	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	92:4fc01daae5a5	884	/**
bogdanm	92:4fc01daae5a5	885	* @}
bogdanm	92:4fc01daae5a5	886	*/
bogdanm	92:4fc01daae5a5	887
bogdanm	92:4fc01daae5a5	888	/** @defgroup FMC_SDRAM_SelfRefresh_Time
bogdanm	92:4fc01daae5a5	889	* @{
bogdanm	92:4fc01daae5a5	890	*/
bogdanm	92:4fc01daae5a5	891	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
bogdanm	92:4fc01daae5a5	892	/**
bogdanm	92:4fc01daae5a5	893	* @}
bogdanm	92:4fc01daae5a5	894	*/
bogdanm	92:4fc01daae5a5	895
bogdanm	92:4fc01daae5a5	896	/** @defgroup FMC_SDRAM_RowCycle_Delay
bogdanm	92:4fc01daae5a5	897	* @{
bogdanm	92:4fc01daae5a5	898	*/
bogdanm	92:4fc01daae5a5	899	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	92:4fc01daae5a5	900	/**
bogdanm	92:4fc01daae5a5	901	* @}
bogdanm	92:4fc01daae5a5	902	*/
bogdanm	92:4fc01daae5a5	903
bogdanm	92:4fc01daae5a5	904	/** @defgroup FMC_SDRAM_Write_Recovery_Time
bogdanm	92:4fc01daae5a5	905	* @{
bogdanm	92:4fc01daae5a5	906	*/
bogdanm	92:4fc01daae5a5	907	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
bogdanm	92:4fc01daae5a5	908	/**
bogdanm	92:4fc01daae5a5	909	* @}
bogdanm	92:4fc01daae5a5	910	*/
bogdanm	92:4fc01daae5a5	911
bogdanm	92:4fc01daae5a5	912	/** @defgroup FMC_SDRAM_RP_Delay
bogdanm	92:4fc01daae5a5	913	* @{
bogdanm	92:4fc01daae5a5	914	*/
bogdanm	92:4fc01daae5a5	915	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	92:4fc01daae5a5	916	/**
bogdanm	92:4fc01daae5a5	917	* @}
bogdanm	92:4fc01daae5a5	918	*/
bogdanm	92:4fc01daae5a5	919
bogdanm	92:4fc01daae5a5	920	/** @defgroup FMC_SDRAM_RCD_Delay
bogdanm	92:4fc01daae5a5	921	* @{
bogdanm	92:4fc01daae5a5	922	*/
bogdanm	92:4fc01daae5a5	923	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	92:4fc01daae5a5	924
bogdanm	92:4fc01daae5a5	925	/**
bogdanm	92:4fc01daae5a5	926	* @}
bogdanm	92:4fc01daae5a5	927	*/
bogdanm	92:4fc01daae5a5	928
bogdanm	92:4fc01daae5a5	929	/** @defgroup FMC_SDRAM_Command_Mode
bogdanm	92:4fc01daae5a5	930	* @{
bogdanm	92:4fc01daae5a5	931	*/
bogdanm	92:4fc01daae5a5	932	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	933	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	934	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	935	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
bogdanm	92:4fc01daae5a5	936	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	937	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
bogdanm	92:4fc01daae5a5	938	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
bogdanm	92:4fc01daae5a5	939
bogdanm	92:4fc01daae5a5	940	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
bogdanm	92:4fc01daae5a5	941	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	942	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
bogdanm	92:4fc01daae5a5	943	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
bogdanm	92:4fc01daae5a5	944	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
bogdanm	92:4fc01daae5a5	945	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
bogdanm	92:4fc01daae5a5	946	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
bogdanm	92:4fc01daae5a5	947	/**
bogdanm	92:4fc01daae5a5	948	* @}
bogdanm	92:4fc01daae5a5	949	*/
bogdanm	92:4fc01daae5a5	950
bogdanm	92:4fc01daae5a5	951	/** @defgroup FMC_SDRAM_Command_Target
bogdanm	92:4fc01daae5a5	952	* @{
bogdanm	92:4fc01daae5a5	953	*/
bogdanm	92:4fc01daae5a5	954	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
bogdanm	92:4fc01daae5a5	955	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
bogdanm	92:4fc01daae5a5	956	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
bogdanm	92:4fc01daae5a5	957
bogdanm	92:4fc01daae5a5	958	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
bogdanm	92:4fc01daae5a5	959	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
bogdanm	92:4fc01daae5a5	960	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
bogdanm	92:4fc01daae5a5	961	/**
bogdanm	92:4fc01daae5a5	962	* @}
bogdanm	92:4fc01daae5a5	963	*/
bogdanm	92:4fc01daae5a5	964
bogdanm	92:4fc01daae5a5	965	/** @defgroup FMC_SDRAM_AutoRefresh_Number
bogdanm	92:4fc01daae5a5	966	* @{
bogdanm	92:4fc01daae5a5	967	*/
bogdanm	92:4fc01daae5a5	968	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
bogdanm	92:4fc01daae5a5	969	/**
bogdanm	92:4fc01daae5a5	970	* @}
bogdanm	92:4fc01daae5a5	971	*/
bogdanm	92:4fc01daae5a5	972
bogdanm	92:4fc01daae5a5	973	/** @defgroup FMC_SDRAM_ModeRegister_Definition
bogdanm	92:4fc01daae5a5	974	* @{
bogdanm	92:4fc01daae5a5	975	*/
bogdanm	92:4fc01daae5a5	976	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
bogdanm	92:4fc01daae5a5	977	/**
bogdanm	92:4fc01daae5a5	978	* @}
bogdanm	92:4fc01daae5a5	979	*/
bogdanm	92:4fc01daae5a5	980
bogdanm	92:4fc01daae5a5	981	/** @defgroup FMC_SDRAM_Refresh_rate
bogdanm	92:4fc01daae5a5	982	* @{
bogdanm	92:4fc01daae5a5	983	*/
bogdanm	92:4fc01daae5a5	984	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
bogdanm	92:4fc01daae5a5	985	/**
bogdanm	92:4fc01daae5a5	986	* @}
bogdanm	92:4fc01daae5a5	987	*/
bogdanm	92:4fc01daae5a5	988
bogdanm	92:4fc01daae5a5	989	/** @defgroup FMC_SDRAM_Mode_Status
bogdanm	92:4fc01daae5a5	990	* @{
bogdanm	92:4fc01daae5a5	991	*/
bogdanm	92:4fc01daae5a5	992	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	993	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
bogdanm	92:4fc01daae5a5	994	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
bogdanm	92:4fc01daae5a5	995	/**
bogdanm	92:4fc01daae5a5	996	* @}
bogdanm	92:4fc01daae5a5	997	*/
bogdanm	92:4fc01daae5a5	998
bogdanm	92:4fc01daae5a5	999	/** @defgroup FMC_NORSRAM_Device_Instance
bogdanm	92:4fc01daae5a5	1000	* @{
bogdanm	92:4fc01daae5a5	1001	*/
bogdanm	92:4fc01daae5a5	1002	#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
bogdanm	92:4fc01daae5a5	1003	/**
bogdanm	92:4fc01daae5a5	1004	* @}
bogdanm	92:4fc01daae5a5	1005	*/
bogdanm	92:4fc01daae5a5	1006
bogdanm	92:4fc01daae5a5	1007	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
bogdanm	92:4fc01daae5a5	1008	* @{
bogdanm	92:4fc01daae5a5	1009	*/
bogdanm	92:4fc01daae5a5	1010	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
bogdanm	92:4fc01daae5a5	1011	/**
bogdanm	92:4fc01daae5a5	1012	* @}
bogdanm	92:4fc01daae5a5	1013	*/
bogdanm	92:4fc01daae5a5	1014
bogdanm	92:4fc01daae5a5	1015	/** @defgroup FMC_NAND_Device_Instance
bogdanm	92:4fc01daae5a5	1016	* @{
bogdanm	92:4fc01daae5a5	1017	*/
bogdanm	92:4fc01daae5a5	1018	#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
bogdanm	92:4fc01daae5a5	1019	/**
bogdanm	92:4fc01daae5a5	1020	* @}
bogdanm	92:4fc01daae5a5	1021	*/
bogdanm	92:4fc01daae5a5	1022
bogdanm	92:4fc01daae5a5	1023	/** @defgroup FMC_PCCARD_Device_Instance
bogdanm	92:4fc01daae5a5	1024	* @{
bogdanm	92:4fc01daae5a5	1025	*/
bogdanm	92:4fc01daae5a5	1026	#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
bogdanm	92:4fc01daae5a5	1027	/**
bogdanm	92:4fc01daae5a5	1028	* @}
bogdanm	92:4fc01daae5a5	1029	*/
bogdanm	92:4fc01daae5a5	1030
bogdanm	92:4fc01daae5a5	1031	/** @defgroup FMC_SDRAM_Device_Instance
bogdanm	92:4fc01daae5a5	1032	* @{
bogdanm	92:4fc01daae5a5	1033	*/
bogdanm	92:4fc01daae5a5	1034	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
bogdanm	92:4fc01daae5a5	1035	/**
bogdanm	92:4fc01daae5a5	1036	* @}
bogdanm	92:4fc01daae5a5	1037	*/
bogdanm	92:4fc01daae5a5	1038
bogdanm	92:4fc01daae5a5	1039	/**
bogdanm	92:4fc01daae5a5	1040	* @}
bogdanm	92:4fc01daae5a5	1041	*/
bogdanm	92:4fc01daae5a5	1042
bogdanm	92:4fc01daae5a5	1043	/** @defgroup FMC_Interrupt_definition
bogdanm	92:4fc01daae5a5	1044	* @brief FMC Interrupt definition
bogdanm	92:4fc01daae5a5	1045	* @{
bogdanm	92:4fc01daae5a5	1046	*/
bogdanm	92:4fc01daae5a5	1047	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	1048	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	1049	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	1050	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm	92:4fc01daae5a5	1051
bogdanm	92:4fc01daae5a5	1052	#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
bogdanm	92:4fc01daae5a5	1053
bogdanm	92:4fc01daae5a5	1054	#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) \|\| \
bogdanm	92:4fc01daae5a5	1055	((IT) == FMC_IT_LEVEL) \|\| \
bogdanm	92:4fc01daae5a5	1056	((IT) == FMC_IT_FALLING_EDGE) \|\| \
bogdanm	92:4fc01daae5a5	1057	((IT) == FMC_IT_REFRESH_ERROR))
bogdanm	92:4fc01daae5a5	1058	/**
bogdanm	92:4fc01daae5a5	1059	* @}
bogdanm	92:4fc01daae5a5	1060	*/
bogdanm	92:4fc01daae5a5	1061
bogdanm	92:4fc01daae5a5	1062	/** @defgroup FMC_Flag_definition
bogdanm	92:4fc01daae5a5	1063	* @brief FMC Flag definition
bogdanm	92:4fc01daae5a5	1064	* @{
bogdanm	92:4fc01daae5a5	1065	*/
bogdanm	92:4fc01daae5a5	1066	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	1067	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	1068	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	1069	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	1070	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
bogdanm	92:4fc01daae5a5	1071	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
bogdanm	92:4fc01daae5a5	1072	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
bogdanm	92:4fc01daae5a5	1073
bogdanm	92:4fc01daae5a5	1074	#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) \|\| \
bogdanm	92:4fc01daae5a5	1075	((FLAG) == FMC_FLAG_LEVEL) \|\| \
bogdanm	92:4fc01daae5a5	1076	((FLAG) == FMC_FLAG_FALLING_EDGE) \|\| \
bogdanm	92:4fc01daae5a5	1077	((FLAG) == FMC_FLAG_FEMPT) \|\| \
bogdanm	92:4fc01daae5a5	1078	((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) \|\| \
bogdanm	92:4fc01daae5a5	1079	((FLAG) == FMC_SDRAM_FLAG_BUSY))
bogdanm	92:4fc01daae5a5	1080
bogdanm	92:4fc01daae5a5	1081	#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
bogdanm	92:4fc01daae5a5	1082	/**
bogdanm	92:4fc01daae5a5	1083	* @}
bogdanm	92:4fc01daae5a5	1084	*/
bogdanm	92:4fc01daae5a5	1085
bogdanm	92:4fc01daae5a5	1086	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1087
bogdanm	92:4fc01daae5a5	1088	/** @defgroup FMC_NOR_Macros
bogdanm	92:4fc01daae5a5	1089	* @brief macros to handle NOR device enable/disable and read/write operations
bogdanm	92:4fc01daae5a5	1090	* @{
bogdanm	92:4fc01daae5a5	1091	*/
bogdanm	92:4fc01daae5a5	1092
bogdanm	92:4fc01daae5a5	1093	/**
bogdanm	92:4fc01daae5a5	1094	* @brief Enable the NORSRAM device access.
bogdanm	92:4fc01daae5a5	1095	* @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm	92:4fc01daae5a5	1096	* @param __BANK__: FMC_NORSRAM Bank
bogdanm	92:4fc01daae5a5	1097	* @retval None
bogdanm	92:4fc01daae5a5	1098	*/
bogdanm	92:4fc01daae5a5	1099	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
bogdanm	92:4fc01daae5a5	1100
bogdanm	92:4fc01daae5a5	1101	/**
bogdanm	92:4fc01daae5a5	1102	* @brief Disable the NORSRAM device access.
bogdanm	92:4fc01daae5a5	1103	* @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm	92:4fc01daae5a5	1104	* @param __BANK__: FMC_NORSRAM Bank
bogdanm	92:4fc01daae5a5	1105	* @retval None
bogdanm	92:4fc01daae5a5	1106	*/
bogdanm	92:4fc01daae5a5	1107	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
bogdanm	92:4fc01daae5a5	1108
bogdanm	92:4fc01daae5a5	1109	/**
bogdanm	92:4fc01daae5a5	1110	* @}
bogdanm	92:4fc01daae5a5	1111	*/
bogdanm	92:4fc01daae5a5	1112
bogdanm	92:4fc01daae5a5	1113	/** @defgroup FMC_NAND_Macros
bogdanm	92:4fc01daae5a5	1114	* @brief macros to handle NAND device enable/disable
bogdanm	92:4fc01daae5a5	1115	* @{
bogdanm	92:4fc01daae5a5	1116	*/
bogdanm	92:4fc01daae5a5	1117
bogdanm	92:4fc01daae5a5	1118	/**
bogdanm	92:4fc01daae5a5	1119	* @brief Enable the NAND device access.
bogdanm	92:4fc01daae5a5	1120	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	92:4fc01daae5a5	1121	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	1122	* @retval None
bogdanm	92:4fc01daae5a5	1123	*/
bogdanm	92:4fc01daae5a5	1124	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
bogdanm	92:4fc01daae5a5	1125	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
bogdanm	92:4fc01daae5a5	1126
bogdanm	92:4fc01daae5a5	1127	/**
bogdanm	92:4fc01daae5a5	1128	* @brief Disable the NAND device access.
bogdanm	92:4fc01daae5a5	1129	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	92:4fc01daae5a5	1130	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	1131	* @retval None
bogdanm	92:4fc01daae5a5	1132	*/
bogdanm	92:4fc01daae5a5	1133	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
bogdanm	92:4fc01daae5a5	1134	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
bogdanm	92:4fc01daae5a5	1135	/**
bogdanm	92:4fc01daae5a5	1136	* @}
bogdanm	92:4fc01daae5a5	1137	*/
bogdanm	92:4fc01daae5a5	1138
bogdanm	92:4fc01daae5a5	1139	/** @defgroup FMC_PCCARD_Macros
bogdanm	92:4fc01daae5a5	1140	* @brief macros to handle SRAM read/write operations
bogdanm	92:4fc01daae5a5	1141	* @{
bogdanm	92:4fc01daae5a5	1142	*/
bogdanm	92:4fc01daae5a5	1143
bogdanm	92:4fc01daae5a5	1144	/**
bogdanm	92:4fc01daae5a5	1145	* @brief Enable the PCCARD device access.
bogdanm	92:4fc01daae5a5	1146	* @param __INSTANCE__: FMC_PCCARD Instance
bogdanm	92:4fc01daae5a5	1147	* @retval None
bogdanm	92:4fc01daae5a5	1148	*/
bogdanm	92:4fc01daae5a5	1149	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
bogdanm	92:4fc01daae5a5	1150
bogdanm	92:4fc01daae5a5	1151	/**
bogdanm	92:4fc01daae5a5	1152	* @brief Disable the PCCARD device access.
bogdanm	92:4fc01daae5a5	1153	* @param __INSTANCE__: FMC_PCCARD Instance
bogdanm	92:4fc01daae5a5	1154	* @retval None
bogdanm	92:4fc01daae5a5	1155	*/
bogdanm	92:4fc01daae5a5	1156	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
bogdanm	92:4fc01daae5a5	1157	/**
bogdanm	92:4fc01daae5a5	1158	* @}
bogdanm	92:4fc01daae5a5	1159	*/
bogdanm	92:4fc01daae5a5	1160
bogdanm	92:4fc01daae5a5	1161	/** @defgroup FMC_Interrupt
bogdanm	92:4fc01daae5a5	1162	* @brief macros to handle FMC interrupts
bogdanm	92:4fc01daae5a5	1163	* @{
bogdanm	92:4fc01daae5a5	1164	*/
bogdanm	92:4fc01daae5a5	1165
bogdanm	92:4fc01daae5a5	1166	/**
bogdanm	92:4fc01daae5a5	1167	* @brief Enable the NAND device interrupt.
bogdanm	92:4fc01daae5a5	1168	* @param __INSTANCE__: FMC_NAND instance
bogdanm	92:4fc01daae5a5	1169	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	1170	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	92:4fc01daae5a5	1171	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1172	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	92:4fc01daae5a5	1173	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	92:4fc01daae5a5	1174	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	92:4fc01daae5a5	1175	* @retval None
bogdanm	92:4fc01daae5a5	1176	*/
bogdanm	92:4fc01daae5a5	1177	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
bogdanm	92:4fc01daae5a5	1178	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
bogdanm	92:4fc01daae5a5	1179
bogdanm	92:4fc01daae5a5	1180	/**
bogdanm	92:4fc01daae5a5	1181	* @brief Disable the NAND device interrupt.
bogdanm	92:4fc01daae5a5	1182	* @param __INSTANCE__: FMC_NAND handle
bogdanm	92:4fc01daae5a5	1183	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	1184	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	92:4fc01daae5a5	1185	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1186	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	92:4fc01daae5a5	1187	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	92:4fc01daae5a5	1188	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	92:4fc01daae5a5	1189	* @retval None
bogdanm	92:4fc01daae5a5	1190	*/
bogdanm	92:4fc01daae5a5	1191	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
bogdanm	92:4fc01daae5a5	1192	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
bogdanm	92:4fc01daae5a5	1193
bogdanm	92:4fc01daae5a5	1194	/**
bogdanm	92:4fc01daae5a5	1195	* @brief Get flag status of the NAND device.
bogdanm	92:4fc01daae5a5	1196	* @param __INSTANCE__: FMC_NAND handle
bogdanm	92:4fc01daae5a5	1197	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	1198	* @param __FLAG__: FMC_NAND flag
bogdanm	92:4fc01daae5a5	1199	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1200	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	92:4fc01daae5a5	1201	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	92:4fc01daae5a5	1202	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	92:4fc01daae5a5	1203	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	92:4fc01daae5a5	1204	* @retval The state of FLAG (SET or RESET).
bogdanm	92:4fc01daae5a5	1205	*/
bogdanm	92:4fc01daae5a5	1206	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
bogdanm	92:4fc01daae5a5	1207	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
bogdanm	92:4fc01daae5a5	1208	/**
bogdanm	92:4fc01daae5a5	1209	* @brief Clear flag status of the NAND device.
bogdanm	92:4fc01daae5a5	1210	* @param __INSTANCE__: FMC_NAND handle
bogdanm	92:4fc01daae5a5	1211	* @param __BANK__: FMC_NAND Bank
bogdanm	92:4fc01daae5a5	1212	* @param __FLAG__: FMC_NAND flag
bogdanm	92:4fc01daae5a5	1213	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1214	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	92:4fc01daae5a5	1215	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	92:4fc01daae5a5	1216	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	92:4fc01daae5a5	1217	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	92:4fc01daae5a5	1218	* @retval None
bogdanm	92:4fc01daae5a5	1219	*/
bogdanm	92:4fc01daae5a5	1220	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
bogdanm	92:4fc01daae5a5	1221	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
bogdanm	92:4fc01daae5a5	1222	/**
bogdanm	92:4fc01daae5a5	1223	* @brief Enable the PCCARD device interrupt.
bogdanm	92:4fc01daae5a5	1224	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	92:4fc01daae5a5	1225	* @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm	92:4fc01daae5a5	1226	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1227	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	92:4fc01daae5a5	1228	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	92:4fc01daae5a5	1229	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	92:4fc01daae5a5	1230	* @retval None
bogdanm	92:4fc01daae5a5	1231	*/
bogdanm	92:4fc01daae5a5	1232	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1233
bogdanm	92:4fc01daae5a5	1234	/**
bogdanm	92:4fc01daae5a5	1235	* @brief Disable the PCCARD device interrupt.
bogdanm	92:4fc01daae5a5	1236	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	92:4fc01daae5a5	1237	* @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm	92:4fc01daae5a5	1238	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1239	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	92:4fc01daae5a5	1240	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	92:4fc01daae5a5	1241	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	92:4fc01daae5a5	1242	* @retval None
bogdanm	92:4fc01daae5a5	1243	*/
bogdanm	92:4fc01daae5a5	1244	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1245
bogdanm	92:4fc01daae5a5	1246	/**
bogdanm	92:4fc01daae5a5	1247	* @brief Get flag status of the PCCARD device.
bogdanm	92:4fc01daae5a5	1248	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	92:4fc01daae5a5	1249	* @param __FLAG__: FMC_PCCARD flag
bogdanm	92:4fc01daae5a5	1250	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1251	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	92:4fc01daae5a5	1252	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	92:4fc01daae5a5	1253	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	92:4fc01daae5a5	1254	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	92:4fc01daae5a5	1255	* @retval The state of FLAG (SET or RESET).
bogdanm	92:4fc01daae5a5	1256	*/
bogdanm	92:4fc01daae5a5	1257	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm	92:4fc01daae5a5	1258
bogdanm	92:4fc01daae5a5	1259	/**
bogdanm	92:4fc01daae5a5	1260	* @brief Clear flag status of the PCCARD device.
bogdanm	92:4fc01daae5a5	1261	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	92:4fc01daae5a5	1262	* @param __FLAG__: FMC_PCCARD flag
bogdanm	92:4fc01daae5a5	1263	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1264	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	92:4fc01daae5a5	1265	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	92:4fc01daae5a5	1266	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	92:4fc01daae5a5	1267	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	92:4fc01daae5a5	1268	* @retval None
bogdanm	92:4fc01daae5a5	1269	*/
bogdanm	92:4fc01daae5a5	1270	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
bogdanm	92:4fc01daae5a5	1271
bogdanm	92:4fc01daae5a5	1272	/**
bogdanm	92:4fc01daae5a5	1273	* @brief Enable the SDRAM device interrupt.
bogdanm	92:4fc01daae5a5	1274	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	92:4fc01daae5a5	1275	* @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm	92:4fc01daae5a5	1276	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1277	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm	92:4fc01daae5a5	1278	* @retval None
bogdanm	92:4fc01daae5a5	1279	*/
bogdanm	92:4fc01daae5a5	1280	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1281
bogdanm	92:4fc01daae5a5	1282	/**
bogdanm	92:4fc01daae5a5	1283	* @brief Disable the SDRAM device interrupt.
bogdanm	92:4fc01daae5a5	1284	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	92:4fc01daae5a5	1285	* @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm	92:4fc01daae5a5	1286	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1287	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm	92:4fc01daae5a5	1288	* @retval None
bogdanm	92:4fc01daae5a5	1289	*/
bogdanm	92:4fc01daae5a5	1290	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1291
bogdanm	92:4fc01daae5a5	1292	/**
bogdanm	92:4fc01daae5a5	1293	* @brief Get flag status of the SDRAM device.
bogdanm	92:4fc01daae5a5	1294	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	92:4fc01daae5a5	1295	* @param __FLAG__: FMC_SDRAM flag
bogdanm	92:4fc01daae5a5	1296	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1297	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
bogdanm	92:4fc01daae5a5	1298	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
bogdanm	92:4fc01daae5a5	1299	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
bogdanm	92:4fc01daae5a5	1300	* @retval The state of FLAG (SET or RESET).
bogdanm	92:4fc01daae5a5	1301	*/
bogdanm	92:4fc01daae5a5	1302	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
bogdanm	92:4fc01daae5a5	1303
bogdanm	92:4fc01daae5a5	1304	/**
bogdanm	92:4fc01daae5a5	1305	* @brief Clear flag status of the SDRAM device.
bogdanm	92:4fc01daae5a5	1306	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	92:4fc01daae5a5	1307	* @param __FLAG__: FMC_SDRAM flag
bogdanm	92:4fc01daae5a5	1308	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1309	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
bogdanm	92:4fc01daae5a5	1310	* @retval None
bogdanm	92:4fc01daae5a5	1311	*/
bogdanm	92:4fc01daae5a5	1312	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
bogdanm	92:4fc01daae5a5	1313	/**
bogdanm	92:4fc01daae5a5	1314	* @}
bogdanm	92:4fc01daae5a5	1315	*/
bogdanm	92:4fc01daae5a5	1316
bogdanm	92:4fc01daae5a5	1317	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1318
bogdanm	92:4fc01daae5a5	1319	/* FMC_NORSRAM Controller functions *******************************************/
bogdanm	92:4fc01daae5a5	1320	/* Initialization/de-initialization functions */
bogdanm	92:4fc01daae5a5	1321	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
bogdanm	92:4fc01daae5a5	1322	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1323	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm	92:4fc01daae5a5	1324	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1325
bogdanm	92:4fc01daae5a5	1326	/* FMC_NORSRAM Control functions */
bogdanm	92:4fc01daae5a5	1327	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1328	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1329
bogdanm	92:4fc01daae5a5	1330	/* FMC_NAND Controller functions **********************************************/
bogdanm	92:4fc01daae5a5	1331	/* Initialization/de-initialization functions */
bogdanm	92:4fc01daae5a5	1332	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
bogdanm	92:4fc01daae5a5	1333	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1334	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1335	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1336
bogdanm	92:4fc01daae5a5	1337	/* FMC_NAND Control functions */
bogdanm	92:4fc01daae5a5	1338	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1339	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1340	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm	92:4fc01daae5a5	1341
bogdanm	92:4fc01daae5a5	1342	/* FMC_PCCARD Controller functions ********************************************/
bogdanm	92:4fc01daae5a5	1343	/* Initialization/de-initialization functions */
bogdanm	92:4fc01daae5a5	1344	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
bogdanm	92:4fc01daae5a5	1345	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	92:4fc01daae5a5	1346	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	92:4fc01daae5a5	1347	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	92:4fc01daae5a5	1348	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
bogdanm	92:4fc01daae5a5	1349
bogdanm	92:4fc01daae5a5	1350	/* FMC_SDRAM Controller functions *********************************************/
bogdanm	92:4fc01daae5a5	1351	/* Initialization/de-initialization functions */
bogdanm	92:4fc01daae5a5	1352	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
bogdanm	92:4fc01daae5a5	1353	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1354	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1355
bogdanm	92:4fc01daae5a5	1356	/* FMC_SDRAM Control functions */
bogdanm	92:4fc01daae5a5	1357	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1358	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1359	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
bogdanm	92:4fc01daae5a5	1360	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
bogdanm	92:4fc01daae5a5	1361	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
bogdanm	92:4fc01daae5a5	1362	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	92:4fc01daae5a5	1363
bogdanm	92:4fc01daae5a5	1364	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	1365	/**
bogdanm	92:4fc01daae5a5	1366	* @}
bogdanm	92:4fc01daae5a5	1367	*/
bogdanm	92:4fc01daae5a5	1368
bogdanm	92:4fc01daae5a5	1369	/**
bogdanm	92:4fc01daae5a5	1370	* @}
bogdanm	92:4fc01daae5a5	1371	*/
bogdanm	92:4fc01daae5a5	1372
bogdanm	92:4fc01daae5a5	1373	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	1374	}
bogdanm	92:4fc01daae5a5	1375	#endif
bogdanm	92:4fc01daae5a5	1376
bogdanm	92:4fc01daae5a5	1377	#endif /* __STM32F4xx_LL_FMC_H */
bogdanm	92:4fc01daae5a5	1378
bogdanm	92:4fc01daae5a5	1379	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
Dependents:	0
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_MTS_MDOT_F405RG/stm32f4xx_ll_fmc.h@93:9dd889aeda0e, 2014-12-05 (annotated)

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