frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_i2c.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:
fblanc
Date:
Fri Dec 05 15:42:32 2014 +0000
Revision:
93:9dd889aeda0e
Parent:
92:4fc01daae5a5 
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_i2c.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of I2C HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_I2C_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_I2C_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup I2C
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /**
bogdanm 92:4fc01daae5a5 60 * @brief I2C Configuration Structure definition
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62 typedef struct
bogdanm 92:4fc01daae5a5 63 {
bogdanm 92:4fc01daae5a5 64 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
bogdanm 92:4fc01daae5a5 65 This parameter must be set to a value lower than 400kHz */
bogdanm 92:4fc01daae5a5 66
bogdanm 92:4fc01daae5a5 67 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
bogdanm 92:4fc01daae5a5 68 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 uint32_t OwnAddress1; /*!< Specifies the first device own address.
bogdanm 92:4fc01daae5a5 71 This parameter can be a 7-bit or 10-bit address. */
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
bogdanm 92:4fc01daae5a5 74 This parameter can be a value of @ref I2C_addressing_mode */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
bogdanm 92:4fc01daae5a5 77 This parameter can be a value of @ref I2C_dual_addressing_mode */
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
bogdanm 92:4fc01daae5a5 80 This parameter can be a 7-bit address. */
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
bogdanm 92:4fc01daae5a5 83 This parameter can be a value of @ref I2C_general_call_addressing_mode */
bogdanm 92:4fc01daae5a5 84
bogdanm 92:4fc01daae5a5 85 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
bogdanm 92:4fc01daae5a5 86 This parameter can be a value of @ref I2C_nostretch_mode */
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 }I2C_InitTypeDef;
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 /**
bogdanm 92:4fc01daae5a5 91 * @brief HAL State structures definition
bogdanm 92:4fc01daae5a5 92 */
bogdanm 92:4fc01daae5a5 93 typedef enum
bogdanm 92:4fc01daae5a5 94 {
bogdanm 92:4fc01daae5a5 95 HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 96 HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
bogdanm 92:4fc01daae5a5 97 HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
bogdanm 92:4fc01daae5a5 98 HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 92:4fc01daae5a5 99 HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 92:4fc01daae5a5 100 HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */
bogdanm 92:4fc01daae5a5 101 HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */
bogdanm 92:4fc01daae5a5 102 HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */
bogdanm 92:4fc01daae5a5 103 HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 }HAL_I2C_StateTypeDef;
bogdanm 92:4fc01daae5a5 106
bogdanm 92:4fc01daae5a5 107 /**
bogdanm 92:4fc01daae5a5 108 * @brief HAL I2C Error Code structure definition
bogdanm 92:4fc01daae5a5 109 */
bogdanm 92:4fc01daae5a5 110 typedef enum
bogdanm 92:4fc01daae5a5 111 {
bogdanm 92:4fc01daae5a5 112 HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
bogdanm 92:4fc01daae5a5 113 HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
bogdanm 92:4fc01daae5a5 114 HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
bogdanm 92:4fc01daae5a5 115 HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
bogdanm 92:4fc01daae5a5 116 HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
bogdanm 92:4fc01daae5a5 117 HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
bogdanm 92:4fc01daae5a5 118 HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */
bogdanm 92:4fc01daae5a5 119
bogdanm 92:4fc01daae5a5 120 }HAL_I2C_ErrorTypeDef;
bogdanm 92:4fc01daae5a5 121
bogdanm 92:4fc01daae5a5 122 /**
bogdanm 92:4fc01daae5a5 123 * @brief I2C handle Structure definition
bogdanm 92:4fc01daae5a5 124 */
bogdanm 92:4fc01daae5a5 125 typedef struct
bogdanm 92:4fc01daae5a5 126 {
bogdanm 92:4fc01daae5a5 127 I2C_TypeDef *Instance; /*!< I2C registers base address */
bogdanm 92:4fc01daae5a5 128
bogdanm 92:4fc01daae5a5 129 I2C_InitTypeDef Init; /*!< I2C communication parameters */
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133 uint16_t XferSize; /*!< I2C transfer size */
bogdanm 92:4fc01daae5a5 134
bogdanm 92:4fc01daae5a5 135 __IO uint16_t XferCount; /*!< I2C transfer counter */
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
bogdanm 92:4fc01daae5a5 138
bogdanm 92:4fc01daae5a5 139 DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
bogdanm 92:4fc01daae5a5 140
bogdanm 92:4fc01daae5a5 141 HAL_LockTypeDef Lock; /*!< I2C locking object */
bogdanm 92:4fc01daae5a5 142
bogdanm 92:4fc01daae5a5 143 __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 }I2C_HandleTypeDef;
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 /** @defgroup I2C_Exported_Constants
bogdanm 92:4fc01daae5a5 152 * @{
bogdanm 92:4fc01daae5a5 153 */
bogdanm 92:4fc01daae5a5 154
bogdanm 92:4fc01daae5a5 155 /** @defgroup I2C_duty_cycle_in_fast_mode
bogdanm 92:4fc01daae5a5 156 * @{
bogdanm 92:4fc01daae5a5 157 */
bogdanm 92:4fc01daae5a5 158 #define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 159 #define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
bogdanm 92:4fc01daae5a5 160
bogdanm 92:4fc01daae5a5 161 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
bogdanm 92:4fc01daae5a5 162 ((CYCLE) == I2C_DUTYCYCLE_16_9))
bogdanm 92:4fc01daae5a5 163 /**
bogdanm 92:4fc01daae5a5 164 * @}
bogdanm 92:4fc01daae5a5 165 */
bogdanm 92:4fc01daae5a5 166
bogdanm 92:4fc01daae5a5 167 /** @defgroup I2C_addressing_mode
bogdanm 92:4fc01daae5a5 168 * @{
bogdanm 92:4fc01daae5a5 169 */
bogdanm 92:4fc01daae5a5 170 #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 171 #define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
bogdanm 92:4fc01daae5a5 174 ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
bogdanm 92:4fc01daae5a5 175 /**
bogdanm 92:4fc01daae5a5 176 * @}
bogdanm 92:4fc01daae5a5 177 */
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179 /** @defgroup I2C_dual_addressing_mode
bogdanm 92:4fc01daae5a5 180 * @{
bogdanm 92:4fc01daae5a5 181 */
bogdanm 92:4fc01daae5a5 182 #define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 183 #define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL
bogdanm 92:4fc01daae5a5 184
bogdanm 92:4fc01daae5a5 185 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
bogdanm 92:4fc01daae5a5 186 ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
bogdanm 92:4fc01daae5a5 187 /**
bogdanm 92:4fc01daae5a5 188 * @}
bogdanm 92:4fc01daae5a5 189 */
bogdanm 92:4fc01daae5a5 190
bogdanm 92:4fc01daae5a5 191 /** @defgroup I2C_general_call_addressing_mode
bogdanm 92:4fc01daae5a5 192 * @{
bogdanm 92:4fc01daae5a5 193 */
bogdanm 92:4fc01daae5a5 194 #define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 195 #define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC
bogdanm 92:4fc01daae5a5 196
bogdanm 92:4fc01daae5a5 197 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
bogdanm 92:4fc01daae5a5 198 ((CALL) == I2C_GENERALCALL_ENABLED))
bogdanm 92:4fc01daae5a5 199 /**
bogdanm 92:4fc01daae5a5 200 * @}
bogdanm 92:4fc01daae5a5 201 */
bogdanm 92:4fc01daae5a5 202
bogdanm 92:4fc01daae5a5 203 /** @defgroup I2C_nostretch_mode
bogdanm 92:4fc01daae5a5 204 * @{
bogdanm 92:4fc01daae5a5 205 */
bogdanm 92:4fc01daae5a5 206 #define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 207 #define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
bogdanm 92:4fc01daae5a5 210 ((STRETCH) == I2C_NOSTRETCH_ENABLED))
bogdanm 92:4fc01daae5a5 211 /**
bogdanm 92:4fc01daae5a5 212 * @}
bogdanm 92:4fc01daae5a5 213 */
bogdanm 92:4fc01daae5a5 214
bogdanm 92:4fc01daae5a5 215 /** @defgroup I2C_Memory_Address_Size
bogdanm 92:4fc01daae5a5 216 * @{
bogdanm 92:4fc01daae5a5 217 */
bogdanm 92:4fc01daae5a5 218 #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 219 #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 220
bogdanm 92:4fc01daae5a5 221 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
bogdanm 92:4fc01daae5a5 222 ((SIZE) == I2C_MEMADD_SIZE_16BIT))
bogdanm 92:4fc01daae5a5 223 /**
bogdanm 92:4fc01daae5a5 224 * @}
bogdanm 92:4fc01daae5a5 225 */
bogdanm 92:4fc01daae5a5 226
bogdanm 92:4fc01daae5a5 227 /** @defgroup I2C_Interrupt_configuration_definition
bogdanm 92:4fc01daae5a5 228 * @{
bogdanm 92:4fc01daae5a5 229 */
bogdanm 92:4fc01daae5a5 230 #define I2C_IT_BUF I2C_CR2_ITBUFEN
bogdanm 92:4fc01daae5a5 231 #define I2C_IT_EVT I2C_CR2_ITEVTEN
bogdanm 92:4fc01daae5a5 232 #define I2C_IT_ERR I2C_CR2_ITERREN
bogdanm 92:4fc01daae5a5 233 /**
bogdanm 92:4fc01daae5a5 234 * @}
bogdanm 92:4fc01daae5a5 235 */
bogdanm 92:4fc01daae5a5 236
bogdanm 92:4fc01daae5a5 237 /** @defgroup I2C_Flag_definition
bogdanm 92:4fc01daae5a5 238 * @{
bogdanm 92:4fc01daae5a5 239 */
bogdanm 92:4fc01daae5a5 240 #define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
bogdanm 92:4fc01daae5a5 241 #define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000)
bogdanm 92:4fc01daae5a5 242 #define I2C_FLAG_PECERR ((uint32_t)0x00011000)
bogdanm 92:4fc01daae5a5 243 #define I2C_FLAG_OVR ((uint32_t)0x00010800)
bogdanm 92:4fc01daae5a5 244 #define I2C_FLAG_AF ((uint32_t)0x00010400)
bogdanm 92:4fc01daae5a5 245 #define I2C_FLAG_ARLO ((uint32_t)0x00010200)
bogdanm 92:4fc01daae5a5 246 #define I2C_FLAG_BERR ((uint32_t)0x00010100)
bogdanm 92:4fc01daae5a5 247 #define I2C_FLAG_TXE ((uint32_t)0x00010080)
bogdanm 92:4fc01daae5a5 248 #define I2C_FLAG_RXNE ((uint32_t)0x00010040)
bogdanm 92:4fc01daae5a5 249 #define I2C_FLAG_STOPF ((uint32_t)0x00010010)
bogdanm 92:4fc01daae5a5 250 #define I2C_FLAG_ADD10 ((uint32_t)0x00010008)
bogdanm 92:4fc01daae5a5 251 #define I2C_FLAG_BTF ((uint32_t)0x00010004)
bogdanm 92:4fc01daae5a5 252 #define I2C_FLAG_ADDR ((uint32_t)0x00010002)
bogdanm 92:4fc01daae5a5 253 #define I2C_FLAG_SB ((uint32_t)0x00010001)
bogdanm 92:4fc01daae5a5 254 #define I2C_FLAG_DUALF ((uint32_t)0x00100080)
bogdanm 92:4fc01daae5a5 255 #define I2C_FLAG_SMBHOST ((uint32_t)0x00100040)
bogdanm 92:4fc01daae5a5 256 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020)
bogdanm 92:4fc01daae5a5 257 #define I2C_FLAG_GENCALL ((uint32_t)0x00100010)
bogdanm 92:4fc01daae5a5 258 #define I2C_FLAG_TRA ((uint32_t)0x00100004)
bogdanm 92:4fc01daae5a5 259 #define I2C_FLAG_BUSY ((uint32_t)0x00100002)
bogdanm 92:4fc01daae5a5 260 #define I2C_FLAG_MSL ((uint32_t)0x00100001)
bogdanm 92:4fc01daae5a5 261 /**
bogdanm 92:4fc01daae5a5 262 * @}
bogdanm 92:4fc01daae5a5 263 */
bogdanm 92:4fc01daae5a5 264
bogdanm 92:4fc01daae5a5 265 /**
bogdanm 92:4fc01daae5a5 266 * @}
bogdanm 92:4fc01daae5a5 267 */
bogdanm 92:4fc01daae5a5 268
bogdanm 92:4fc01daae5a5 269 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 270
bogdanm 92:4fc01daae5a5 271 /** @brief Reset I2C handle state
bogdanm 92:4fc01daae5a5 272 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 92:4fc01daae5a5 273 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 92:4fc01daae5a5 274 * @retval None
bogdanm 92:4fc01daae5a5 275 */
bogdanm 92:4fc01daae5a5 276 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
bogdanm 92:4fc01daae5a5 277
bogdanm 92:4fc01daae5a5 278 /** @brief Enable or disable the specified I2C interrupts.
bogdanm 92:4fc01daae5a5 279 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 92:4fc01daae5a5 280 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 92:4fc01daae5a5 281 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 92:4fc01daae5a5 282 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 283 * @arg I2C_IT_BUF: Buffer interrupt enable
bogdanm 92:4fc01daae5a5 284 * @arg I2C_IT_EVT: Event interrupt enable
bogdanm 92:4fc01daae5a5 285 * @arg I2C_IT_ERR: Error interrupt enable
bogdanm 92:4fc01daae5a5 286 * @retval None
bogdanm 92:4fc01daae5a5 287 */
bogdanm 92:4fc01daae5a5 288
bogdanm 92:4fc01daae5a5 289 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 290 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 291
bogdanm 92:4fc01daae5a5 292 /** @brief Checks if the specified I2C interrupt source is enabled or disabled.
bogdanm 92:4fc01daae5a5 293 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 92:4fc01daae5a5 294 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 92:4fc01daae5a5 295 * @param __INTERRUPT__: specifies the I2C interrupt source to check.
bogdanm 92:4fc01daae5a5 296 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 297 * @arg I2C_IT_BUF: Buffer interrupt enable
bogdanm 92:4fc01daae5a5 298 * @arg I2C_IT_EVT: Event interrupt enable
bogdanm 92:4fc01daae5a5 299 * @arg I2C_IT_ERR: Error interrupt enable
bogdanm 92:4fc01daae5a5 300 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 301 */
bogdanm 92:4fc01daae5a5 302 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 92:4fc01daae5a5 303
bogdanm 92:4fc01daae5a5 304 /** @brief Checks whether the specified I2C flag is set or not.
bogdanm 92:4fc01daae5a5 305 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 92:4fc01daae5a5 306 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 92:4fc01daae5a5 307 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 308 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 309 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
bogdanm 92:4fc01daae5a5 310 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
bogdanm 92:4fc01daae5a5 311 * @arg I2C_FLAG_PECERR: PEC error in reception flag
bogdanm 92:4fc01daae5a5 312 * @arg I2C_FLAG_OVR: Overrun/Underrun flag
bogdanm 92:4fc01daae5a5 313 * @arg I2C_FLAG_AF: Acknowledge failure flag
bogdanm 92:4fc01daae5a5 314 * @arg I2C_FLAG_ARLO: Arbitration lost flag
bogdanm 92:4fc01daae5a5 315 * @arg I2C_FLAG_BERR: Bus error flag
bogdanm 92:4fc01daae5a5 316 * @arg I2C_FLAG_TXE: Data register empty flag
bogdanm 92:4fc01daae5a5 317 * @arg I2C_FLAG_RXNE: Data register not empty flag
bogdanm 92:4fc01daae5a5 318 * @arg I2C_FLAG_STOPF: Stop detection flag
bogdanm 92:4fc01daae5a5 319 * @arg I2C_FLAG_ADD10: 10-bit header sent flag
bogdanm 92:4fc01daae5a5 320 * @arg I2C_FLAG_BTF: Byte transfer finished flag
bogdanm 92:4fc01daae5a5 321 * @arg I2C_FLAG_ADDR: Address sent flag
bogdanm 92:4fc01daae5a5 322 * Address matched flag
bogdanm 92:4fc01daae5a5 323 * @arg I2C_FLAG_SB: Start bit flag
bogdanm 92:4fc01daae5a5 324 * @arg I2C_FLAG_DUALF: Dual flag
bogdanm 92:4fc01daae5a5 325 * @arg I2C_FLAG_SMBHOST: SMBus host header
bogdanm 92:4fc01daae5a5 326 * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
bogdanm 92:4fc01daae5a5 327 * @arg I2C_FLAG_GENCALL: General call header flag
bogdanm 92:4fc01daae5a5 328 * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
bogdanm 92:4fc01daae5a5 329 * @arg I2C_FLAG_BUSY: Bus busy flag
bogdanm 92:4fc01daae5a5 330 * @arg I2C_FLAG_MSL: Master/Slave flag
bogdanm 92:4fc01daae5a5 331 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 332 */
bogdanm 92:4fc01daae5a5 333 #define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
bogdanm 92:4fc01daae5a5 334 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
bogdanm 92:4fc01daae5a5 335 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
bogdanm 92:4fc01daae5a5 336
bogdanm 92:4fc01daae5a5 337 /** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
bogdanm 92:4fc01daae5a5 338 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 92:4fc01daae5a5 339 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 92:4fc01daae5a5 340 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 341 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 342 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
bogdanm 92:4fc01daae5a5 343 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
bogdanm 92:4fc01daae5a5 344 * @arg I2C_FLAG_PECERR: PEC error in reception flag
bogdanm 92:4fc01daae5a5 345 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
bogdanm 92:4fc01daae5a5 346 * @arg I2C_FLAG_AF: Acknowledge failure flag
bogdanm 92:4fc01daae5a5 347 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
bogdanm 92:4fc01daae5a5 348 * @arg I2C_FLAG_BERR: Bus error flag
bogdanm 92:4fc01daae5a5 349 * @retval None
bogdanm 92:4fc01daae5a5 350 */
bogdanm 92:4fc01daae5a5 351 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
bogdanm 92:4fc01daae5a5 352
bogdanm 92:4fc01daae5a5 353 /** @brief Clears the I2C ADDR pending flag.
bogdanm 92:4fc01daae5a5 354 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 92:4fc01daae5a5 355 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 92:4fc01daae5a5 356 * @retval None
bogdanm 92:4fc01daae5a5 357 */
bogdanm 92:4fc01daae5a5 358
bogdanm 92:4fc01daae5a5 359 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
bogdanm 92:4fc01daae5a5 360 (__HANDLE__)->Instance->SR2;}while(0)
bogdanm 92:4fc01daae5a5 361
bogdanm 92:4fc01daae5a5 362 /** @brief Clears the I2C STOPF pending flag.
bogdanm 92:4fc01daae5a5 363 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 92:4fc01daae5a5 364 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 92:4fc01daae5a5 365 * @retval None
bogdanm 92:4fc01daae5a5 366 */
bogdanm 92:4fc01daae5a5 367 #define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
bogdanm 92:4fc01daae5a5 368 (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;}while(0)
bogdanm 92:4fc01daae5a5 369
bogdanm 92:4fc01daae5a5 370 #define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
bogdanm 92:4fc01daae5a5 371 #define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
bogdanm 92:4fc01daae5a5 372
bogdanm 92:4fc01daae5a5 373 #define __HAL_I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
bogdanm 92:4fc01daae5a5 374 #define __HAL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
bogdanm 92:4fc01daae5a5 375 #define __HAL_I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
bogdanm 92:4fc01daae5a5 376 #define __HAL_I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
bogdanm 92:4fc01daae5a5 377 #define __HAL_I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (__HAL_I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
bogdanm 92:4fc01daae5a5 378 ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
bogdanm 92:4fc01daae5a5 379 ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
bogdanm 92:4fc01daae5a5 380
bogdanm 92:4fc01daae5a5 381 #define __HAL_I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
bogdanm 92:4fc01daae5a5 382 #define __HAL_I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
bogdanm 92:4fc01daae5a5 383
bogdanm 92:4fc01daae5a5 384 #define __HAL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
bogdanm 92:4fc01daae5a5 385 #define __HAL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
bogdanm 92:4fc01daae5a5 386 #define __HAL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
bogdanm 92:4fc01daae5a5 387
bogdanm 92:4fc01daae5a5 388 #define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
bogdanm 92:4fc01daae5a5 389 #define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
bogdanm 92:4fc01daae5a5 390
bogdanm 92:4fc01daae5a5 391 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
bogdanm 92:4fc01daae5a5 392 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
bogdanm 92:4fc01daae5a5 393 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
bogdanm 92:4fc01daae5a5 394
bogdanm 92:4fc01daae5a5 395 /* Include I2C HAL Extension module */
bogdanm 92:4fc01daae5a5 396 #include "stm32f4xx_hal_i2c_ex.h"
bogdanm 92:4fc01daae5a5 397
bogdanm 92:4fc01daae5a5 398 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 399 /* Initialization/de-initialization functions **********************************/
bogdanm 92:4fc01daae5a5 400 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 401 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 402 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 403 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 404
bogdanm 92:4fc01daae5a5 405 /* I/O operation functions *****************************************************/
bogdanm 92:4fc01daae5a5 406 /******* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 407 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 408 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 409 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 410 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 411 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 412 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 413 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 414
bogdanm 92:4fc01daae5a5 415 /******* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 416 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 417 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 418 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 419 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 420 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 421 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 /******* Non-Blocking mode: DMA */
bogdanm 92:4fc01daae5a5 424 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 425 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 426 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 427 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 428 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 429 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 430
bogdanm 92:4fc01daae5a5 431 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
bogdanm 92:4fc01daae5a5 432 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 433 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 434 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 435 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 436 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 437 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 438 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 439 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 440 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 441
bogdanm 92:4fc01daae5a5 442 /* Peripheral Control and State functions **************************************/
bogdanm 92:4fc01daae5a5 443 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 444 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
bogdanm 92:4fc01daae5a5 445
bogdanm 92:4fc01daae5a5 446 /**
bogdanm 92:4fc01daae5a5 447 * @}
bogdanm 92:4fc01daae5a5 448 */
bogdanm 92:4fc01daae5a5 449
bogdanm 92:4fc01daae5a5 450 /**
bogdanm 92:4fc01daae5a5 451 * @}
bogdanm 92:4fc01daae5a5 452 */
bogdanm 92:4fc01daae5a5 453
bogdanm 92:4fc01daae5a5 454 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 455 }
bogdanm 92:4fc01daae5a5 456 #endif
bogdanm 92:4fc01daae5a5 457
bogdanm 92:4fc01daae5a5 458
bogdanm 92:4fc01daae5a5 459 #endif /* __STM32F4xx_HAL_I2C_H */
bogdanm 92:4fc01daae5a5 460
bogdanm 92:4fc01daae5a5 461 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/