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TARGET_NUCLEO_F103RB/stm32f10x_tim.h@76:824293ae5e43, 2014-01-13 (annotated)

Committer:: bogdanm
Date:: Mon Jan 13 15:31:11 2014 +0200
Revision:: 76:824293ae5e43
Parent:: 73:1efda918f0ba
Child:: 77:869cf507173a

Release 76 of the mbed library



Main changes:



- enabled SPI slave on LPC812

- the RTOS should now work with GCC_CR  (LPC1768 and LPC4088)

- GCC now uses 'hard' as the floating point ABI (arguments in floating point registers)

- Bug fixes on various platforms

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	73:1efda918f0ba	1	/**
bogdanm	73:1efda918f0ba	2	******************************************************************************
bogdanm	73:1efda918f0ba	3	* @file stm32f10x_tim.h
bogdanm	73:1efda918f0ba	4	* @author MCD Application Team
bogdanm	73:1efda918f0ba	5	* @version V3.5.0
bogdanm	73:1efda918f0ba	6	* @date 11-March-2011
bogdanm	73:1efda918f0ba	7	* @brief This file contains all the functions prototypes for the TIM firmware
bogdanm	73:1efda918f0ba	8	* library.
bogdanm	76:824293ae5e43	9	*******************************************************************************
bogdanm	76:824293ae5e43	10	* Copyright (c) 2014, STMicroelectronics
bogdanm	76:824293ae5e43	11	* All rights reserved.
bogdanm	76:824293ae5e43	12	*
bogdanm	76:824293ae5e43	13	* Redistribution and use in source and binary forms, with or without
bogdanm	76:824293ae5e43	14	* modification, are permitted provided that the following conditions are met:
bogdanm	76:824293ae5e43	15	*
bogdanm	76:824293ae5e43	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	76:824293ae5e43	17	* this list of conditions and the following disclaimer.
bogdanm	76:824293ae5e43	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	76:824293ae5e43	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	76:824293ae5e43	20	* and/or other materials provided with the distribution.
bogdanm	76:824293ae5e43	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	76:824293ae5e43	22	* may be used to endorse or promote products derived from this software
bogdanm	76:824293ae5e43	23	* without specific prior written permission.
bogdanm	76:824293ae5e43	24	*
bogdanm	76:824293ae5e43	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	76:824293ae5e43	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	76:824293ae5e43	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	76:824293ae5e43	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	76:824293ae5e43	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	76:824293ae5e43	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	76:824293ae5e43	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	76:824293ae5e43	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	76:824293ae5e43	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	76:824293ae5e43	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	76:824293ae5e43	35	*******************************************************************************
bogdanm	76:824293ae5e43	36	*/
bogdanm	73:1efda918f0ba	37
bogdanm	73:1efda918f0ba	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	73:1efda918f0ba	39	#ifndef __STM32F10x_TIM_H
bogdanm	73:1efda918f0ba	40	#define __STM32F10x_TIM_H
bogdanm	73:1efda918f0ba	41
bogdanm	73:1efda918f0ba	42	#ifdef __cplusplus
bogdanm	73:1efda918f0ba	43	extern "C" {
bogdanm	73:1efda918f0ba	44	#endif
bogdanm	73:1efda918f0ba	45
bogdanm	73:1efda918f0ba	46	/* Includes ------------------------------------------------------------------*/
bogdanm	73:1efda918f0ba	47	#include "stm32f10x.h"
bogdanm	73:1efda918f0ba	48
bogdanm	73:1efda918f0ba	49	/** @addtogroup STM32F10x_StdPeriph_Driver
bogdanm	73:1efda918f0ba	50	* @{
bogdanm	73:1efda918f0ba	51	*/
bogdanm	73:1efda918f0ba	52
bogdanm	73:1efda918f0ba	53	/** @addtogroup TIM
bogdanm	73:1efda918f0ba	54	* @{
bogdanm	73:1efda918f0ba	55	*/
bogdanm	73:1efda918f0ba	56
bogdanm	73:1efda918f0ba	57	/** @defgroup TIM_Exported_Types
bogdanm	73:1efda918f0ba	58	* @{
bogdanm	73:1efda918f0ba	59	*/
bogdanm	73:1efda918f0ba	60
bogdanm	73:1efda918f0ba	61	/**
bogdanm	73:1efda918f0ba	62	* @brief TIM Time Base Init structure definition
bogdanm	73:1efda918f0ba	63	* @note This structure is used with all TIMx except for TIM6 and TIM7.
bogdanm	73:1efda918f0ba	64	*/
bogdanm	73:1efda918f0ba	65
bogdanm	73:1efda918f0ba	66	typedef struct
bogdanm	73:1efda918f0ba	67	{
bogdanm	73:1efda918f0ba	68	uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	73:1efda918f0ba	69	This parameter can be a number between 0x0000 and 0xFFFF */
bogdanm	73:1efda918f0ba	70
bogdanm	73:1efda918f0ba	71	uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
bogdanm	73:1efda918f0ba	72	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	73:1efda918f0ba	73
bogdanm	73:1efda918f0ba	74	uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
bogdanm	73:1efda918f0ba	75	Auto-Reload Register at the next update event.
bogdanm	73:1efda918f0ba	76	This parameter must be a number between 0x0000 and 0xFFFF. */
bogdanm	73:1efda918f0ba	77
bogdanm	73:1efda918f0ba	78	uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
bogdanm	73:1efda918f0ba	79	This parameter can be a value of @ref TIM_Clock_Division_CKD */
bogdanm	73:1efda918f0ba	80
bogdanm	73:1efda918f0ba	81	uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	73:1efda918f0ba	82	reaches zero, an update event is generated and counting restarts
bogdanm	73:1efda918f0ba	83	from the RCR value (N).
bogdanm	73:1efda918f0ba	84	This means in PWM mode that (N+1) corresponds to:
bogdanm	73:1efda918f0ba	85	- the number of PWM periods in edge-aligned mode
bogdanm	73:1efda918f0ba	86	- the number of half PWM period in center-aligned mode
bogdanm	73:1efda918f0ba	87	This parameter must be a number between 0x00 and 0xFF.
bogdanm	73:1efda918f0ba	88	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	89	} TIM_TimeBaseInitTypeDef;
bogdanm	73:1efda918f0ba	90
bogdanm	73:1efda918f0ba	91	/**
bogdanm	73:1efda918f0ba	92	* @brief TIM Output Compare Init structure definition
bogdanm	73:1efda918f0ba	93	*/
bogdanm	73:1efda918f0ba	94
bogdanm	73:1efda918f0ba	95	typedef struct
bogdanm	73:1efda918f0ba	96	{
bogdanm	73:1efda918f0ba	97	uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
bogdanm	73:1efda918f0ba	98	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	73:1efda918f0ba	99
bogdanm	73:1efda918f0ba	100	uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
bogdanm	73:1efda918f0ba	101	This parameter can be a value of @ref TIM_Output_Compare_state */
bogdanm	73:1efda918f0ba	102
bogdanm	73:1efda918f0ba	103	uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
bogdanm	73:1efda918f0ba	104	This parameter can be a value of @ref TIM_Output_Compare_N_state
bogdanm	73:1efda918f0ba	105	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	106
bogdanm	73:1efda918f0ba	107	uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	73:1efda918f0ba	108	This parameter can be a number between 0x0000 and 0xFFFF */
bogdanm	73:1efda918f0ba	109
bogdanm	73:1efda918f0ba	110	uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
bogdanm	73:1efda918f0ba	111	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	73:1efda918f0ba	112
bogdanm	73:1efda918f0ba	113	uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	73:1efda918f0ba	114	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	73:1efda918f0ba	115	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	116
bogdanm	73:1efda918f0ba	117	uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	73:1efda918f0ba	118	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	73:1efda918f0ba	119	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	120
bogdanm	73:1efda918f0ba	121	uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	73:1efda918f0ba	122	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	73:1efda918f0ba	123	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	124	} TIM_OCInitTypeDef;
bogdanm	73:1efda918f0ba	125
bogdanm	73:1efda918f0ba	126	/**
bogdanm	73:1efda918f0ba	127	* @brief TIM Input Capture Init structure definition
bogdanm	73:1efda918f0ba	128	*/
bogdanm	73:1efda918f0ba	129
bogdanm	73:1efda918f0ba	130	typedef struct
bogdanm	73:1efda918f0ba	131	{
bogdanm	73:1efda918f0ba	132
bogdanm	73:1efda918f0ba	133	uint16_t TIM_Channel; /*!< Specifies the TIM channel.
bogdanm	73:1efda918f0ba	134	This parameter can be a value of @ref TIM_Channel */
bogdanm	73:1efda918f0ba	135
bogdanm	73:1efda918f0ba	136	uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	73:1efda918f0ba	137	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	73:1efda918f0ba	138
bogdanm	73:1efda918f0ba	139	uint16_t TIM_ICSelection; /*!< Specifies the input.
bogdanm	73:1efda918f0ba	140	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	73:1efda918f0ba	141
bogdanm	73:1efda918f0ba	142	uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	73:1efda918f0ba	143	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	73:1efda918f0ba	144
bogdanm	73:1efda918f0ba	145	uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
bogdanm	73:1efda918f0ba	146	This parameter can be a number between 0x0 and 0xF */
bogdanm	73:1efda918f0ba	147	} TIM_ICInitTypeDef;
bogdanm	73:1efda918f0ba	148
bogdanm	73:1efda918f0ba	149	/**
bogdanm	73:1efda918f0ba	150	* @brief BDTR structure definition
bogdanm	73:1efda918f0ba	151	* @note This structure is used only with TIM1 and TIM8.
bogdanm	73:1efda918f0ba	152	*/
bogdanm	73:1efda918f0ba	153
bogdanm	73:1efda918f0ba	154	typedef struct
bogdanm	73:1efda918f0ba	155	{
bogdanm	73:1efda918f0ba	156
bogdanm	73:1efda918f0ba	157	uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
bogdanm	73:1efda918f0ba	158	This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm	73:1efda918f0ba	159
bogdanm	73:1efda918f0ba	160	uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
bogdanm	73:1efda918f0ba	161	This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm	73:1efda918f0ba	162
bogdanm	73:1efda918f0ba	163	uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
bogdanm	73:1efda918f0ba	164	This parameter can be a value of @ref Lock_level */
bogdanm	73:1efda918f0ba	165
bogdanm	73:1efda918f0ba	166	uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
bogdanm	73:1efda918f0ba	167	switching-on of the outputs.
bogdanm	73:1efda918f0ba	168	This parameter can be a number between 0x00 and 0xFF */
bogdanm	73:1efda918f0ba	169
bogdanm	73:1efda918f0ba	170	uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
bogdanm	73:1efda918f0ba	171	This parameter can be a value of @ref Break_Input_enable_disable */
bogdanm	73:1efda918f0ba	172
bogdanm	73:1efda918f0ba	173	uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
bogdanm	73:1efda918f0ba	174	This parameter can be a value of @ref Break_Polarity */
bogdanm	73:1efda918f0ba	175
bogdanm	73:1efda918f0ba	176	uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
bogdanm	73:1efda918f0ba	177	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
bogdanm	73:1efda918f0ba	178	} TIM_BDTRInitTypeDef;
bogdanm	73:1efda918f0ba	179
bogdanm	73:1efda918f0ba	180	/** @defgroup TIM_Exported_constants
bogdanm	73:1efda918f0ba	181	* @{
bogdanm	73:1efda918f0ba	182	*/
bogdanm	73:1efda918f0ba	183
bogdanm	73:1efda918f0ba	184	#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	185	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	186	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	187	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	188	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	189	((PERIPH) == TIM6) \|\| \
bogdanm	73:1efda918f0ba	190	((PERIPH) == TIM7) \|\| \
bogdanm	73:1efda918f0ba	191	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	192	((PERIPH) == TIM9) \|\| \
bogdanm	73:1efda918f0ba	193	((PERIPH) == TIM10)\|\| \
bogdanm	73:1efda918f0ba	194	((PERIPH) == TIM11)\|\| \
bogdanm	73:1efda918f0ba	195	((PERIPH) == TIM12)\|\| \
bogdanm	73:1efda918f0ba	196	((PERIPH) == TIM13)\|\| \
bogdanm	73:1efda918f0ba	197	((PERIPH) == TIM14)\|\| \
bogdanm	73:1efda918f0ba	198	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	199	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	200	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	201
bogdanm	73:1efda918f0ba	202	/* LIST1: TIM 1 and 8 */
bogdanm	73:1efda918f0ba	203	#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	204	((PERIPH) == TIM8))
bogdanm	73:1efda918f0ba	205
bogdanm	73:1efda918f0ba	206	/* LIST2: TIM 1, 8, 15 16 and 17 */
bogdanm	73:1efda918f0ba	207	#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	208	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	209	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	210	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	211	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	212
bogdanm	73:1efda918f0ba	213	/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
bogdanm	73:1efda918f0ba	214	#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	215	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	216	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	217	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	218	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	219	((PERIPH) == TIM8))
bogdanm	73:1efda918f0ba	220
bogdanm	73:1efda918f0ba	221	/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
bogdanm	73:1efda918f0ba	222	#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	223	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	224	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	225	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	226	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	227	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	228	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	229	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	230	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	231
bogdanm	73:1efda918f0ba	232	/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
bogdanm	73:1efda918f0ba	233	#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	234	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	235	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	236	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	237	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	238	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	239	((PERIPH) == TIM15))
bogdanm	73:1efda918f0ba	240
bogdanm	73:1efda918f0ba	241	/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
bogdanm	73:1efda918f0ba	242	#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	243	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	244	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	245	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	246	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	247	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	248	((PERIPH) == TIM9) \|\| \
bogdanm	73:1efda918f0ba	249	((PERIPH) == TIM12)\|\| \
bogdanm	73:1efda918f0ba	250	((PERIPH) == TIM15))
bogdanm	73:1efda918f0ba	251
bogdanm	73:1efda918f0ba	252	/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
bogdanm	73:1efda918f0ba	253	#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	254	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	255	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	256	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	257	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	258	((PERIPH) == TIM6) \|\| \
bogdanm	73:1efda918f0ba	259	((PERIPH) == TIM7) \|\| \
bogdanm	73:1efda918f0ba	260	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	261	((PERIPH) == TIM9) \|\| \
bogdanm	73:1efda918f0ba	262	((PERIPH) == TIM12)\|\| \
bogdanm	73:1efda918f0ba	263	((PERIPH) == TIM15))
bogdanm	73:1efda918f0ba	264
bogdanm	73:1efda918f0ba	265	/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
bogdanm	73:1efda918f0ba	266	#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	267	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	268	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	269	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	270	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	271	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	272	((PERIPH) == TIM9) \|\| \
bogdanm	73:1efda918f0ba	273	((PERIPH) == TIM10)\|\| \
bogdanm	73:1efda918f0ba	274	((PERIPH) == TIM11)\|\| \
bogdanm	73:1efda918f0ba	275	((PERIPH) == TIM12)\|\| \
bogdanm	73:1efda918f0ba	276	((PERIPH) == TIM13)\|\| \
bogdanm	73:1efda918f0ba	277	((PERIPH) == TIM14)\|\| \
bogdanm	73:1efda918f0ba	278	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	279	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	280	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	281
bogdanm	73:1efda918f0ba	282	/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
bogdanm	73:1efda918f0ba	283	#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	284	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	285	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	286	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	287	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	288	((PERIPH) == TIM6) \|\| \
bogdanm	73:1efda918f0ba	289	((PERIPH) == TIM7) \|\| \
bogdanm	73:1efda918f0ba	290	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	291	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	292	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	293	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	294
bogdanm	73:1efda918f0ba	295	/**
bogdanm	73:1efda918f0ba	296	* @}
bogdanm	73:1efda918f0ba	297	*/
bogdanm	73:1efda918f0ba	298
bogdanm	73:1efda918f0ba	299	/** @defgroup TIM_Output_Compare_and_PWM_modes
bogdanm	73:1efda918f0ba	300	* @{
bogdanm	73:1efda918f0ba	301	*/
bogdanm	73:1efda918f0ba	302
bogdanm	73:1efda918f0ba	303	#define TIM_OCMode_Timing ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	304	#define TIM_OCMode_Active ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	305	#define TIM_OCMode_Inactive ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	306	#define TIM_OCMode_Toggle ((uint16_t)0x0030)
bogdanm	73:1efda918f0ba	307	#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	308	#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
bogdanm	73:1efda918f0ba	309	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
bogdanm	73:1efda918f0ba	310	((MODE) == TIM_OCMode_Active) \|\| \
bogdanm	73:1efda918f0ba	311	((MODE) == TIM_OCMode_Inactive) \|\| \
bogdanm	73:1efda918f0ba	312	((MODE) == TIM_OCMode_Toggle)\|\| \
bogdanm	73:1efda918f0ba	313	((MODE) == TIM_OCMode_PWM1) \|\| \
bogdanm	73:1efda918f0ba	314	((MODE) == TIM_OCMode_PWM2))
bogdanm	73:1efda918f0ba	315	#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
bogdanm	73:1efda918f0ba	316	((MODE) == TIM_OCMode_Active) \|\| \
bogdanm	73:1efda918f0ba	317	((MODE) == TIM_OCMode_Inactive) \|\| \
bogdanm	73:1efda918f0ba	318	((MODE) == TIM_OCMode_Toggle)\|\| \
bogdanm	73:1efda918f0ba	319	((MODE) == TIM_OCMode_PWM1) \|\| \
bogdanm	73:1efda918f0ba	320	((MODE) == TIM_OCMode_PWM2) \|\| \
bogdanm	73:1efda918f0ba	321	((MODE) == TIM_ForcedAction_Active) \|\| \
bogdanm	73:1efda918f0ba	322	((MODE) == TIM_ForcedAction_InActive))
bogdanm	73:1efda918f0ba	323	/**
bogdanm	73:1efda918f0ba	324	* @}
bogdanm	73:1efda918f0ba	325	*/
bogdanm	73:1efda918f0ba	326
bogdanm	73:1efda918f0ba	327	/** @defgroup TIM_One_Pulse_Mode
bogdanm	73:1efda918f0ba	328	* @{
bogdanm	73:1efda918f0ba	329	*/
bogdanm	73:1efda918f0ba	330
bogdanm	73:1efda918f0ba	331	#define TIM_OPMode_Single ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	332	#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	333	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) \|\| \
bogdanm	73:1efda918f0ba	334	((MODE) == TIM_OPMode_Repetitive))
bogdanm	73:1efda918f0ba	335	/**
bogdanm	73:1efda918f0ba	336	* @}
bogdanm	73:1efda918f0ba	337	*/
bogdanm	73:1efda918f0ba	338
bogdanm	73:1efda918f0ba	339	/** @defgroup TIM_Channel
bogdanm	73:1efda918f0ba	340	* @{
bogdanm	73:1efda918f0ba	341	*/
bogdanm	73:1efda918f0ba	342
bogdanm	73:1efda918f0ba	343	#define TIM_Channel_1 ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	344	#define TIM_Channel_2 ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	345	#define TIM_Channel_3 ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	346	#define TIM_Channel_4 ((uint16_t)0x000C)
bogdanm	73:1efda918f0ba	347	#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
bogdanm	73:1efda918f0ba	348	((CHANNEL) == TIM_Channel_2) \|\| \
bogdanm	73:1efda918f0ba	349	((CHANNEL) == TIM_Channel_3) \|\| \
bogdanm	73:1efda918f0ba	350	((CHANNEL) == TIM_Channel_4))
bogdanm	73:1efda918f0ba	351	#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
bogdanm	73:1efda918f0ba	352	((CHANNEL) == TIM_Channel_2))
bogdanm	73:1efda918f0ba	353	#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
bogdanm	73:1efda918f0ba	354	((CHANNEL) == TIM_Channel_2) \|\| \
bogdanm	73:1efda918f0ba	355	((CHANNEL) == TIM_Channel_3))
bogdanm	73:1efda918f0ba	356	/**
bogdanm	73:1efda918f0ba	357	* @}
bogdanm	73:1efda918f0ba	358	*/
bogdanm	73:1efda918f0ba	359
bogdanm	73:1efda918f0ba	360	/** @defgroup TIM_Clock_Division_CKD
bogdanm	73:1efda918f0ba	361	* @{
bogdanm	73:1efda918f0ba	362	*/
bogdanm	73:1efda918f0ba	363
bogdanm	73:1efda918f0ba	364	#define TIM_CKD_DIV1 ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	365	#define TIM_CKD_DIV2 ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	366	#define TIM_CKD_DIV4 ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	367	#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) \|\| \
bogdanm	73:1efda918f0ba	368	((DIV) == TIM_CKD_DIV2) \|\| \
bogdanm	73:1efda918f0ba	369	((DIV) == TIM_CKD_DIV4))
bogdanm	73:1efda918f0ba	370	/**
bogdanm	73:1efda918f0ba	371	* @}
bogdanm	73:1efda918f0ba	372	*/
bogdanm	73:1efda918f0ba	373
bogdanm	73:1efda918f0ba	374	/** @defgroup TIM_Counter_Mode
bogdanm	73:1efda918f0ba	375	* @{
bogdanm	73:1efda918f0ba	376	*/
bogdanm	73:1efda918f0ba	377
bogdanm	73:1efda918f0ba	378	#define TIM_CounterMode_Up ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	379	#define TIM_CounterMode_Down ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	380	#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	381	#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	382	#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	383	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) \|\| \
bogdanm	73:1efda918f0ba	384	((MODE) == TIM_CounterMode_Down) \|\| \
bogdanm	73:1efda918f0ba	385	((MODE) == TIM_CounterMode_CenterAligned1) \|\| \
bogdanm	73:1efda918f0ba	386	((MODE) == TIM_CounterMode_CenterAligned2) \|\| \
bogdanm	73:1efda918f0ba	387	((MODE) == TIM_CounterMode_CenterAligned3))
bogdanm	73:1efda918f0ba	388	/**
bogdanm	73:1efda918f0ba	389	* @}
bogdanm	73:1efda918f0ba	390	*/
bogdanm	73:1efda918f0ba	391
bogdanm	73:1efda918f0ba	392	/** @defgroup TIM_Output_Compare_Polarity
bogdanm	73:1efda918f0ba	393	* @{
bogdanm	73:1efda918f0ba	394	*/
bogdanm	73:1efda918f0ba	395
bogdanm	73:1efda918f0ba	396	#define TIM_OCPolarity_High ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	397	#define TIM_OCPolarity_Low ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	398	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) \|\| \
bogdanm	73:1efda918f0ba	399	((POLARITY) == TIM_OCPolarity_Low))
bogdanm	73:1efda918f0ba	400	/**
bogdanm	73:1efda918f0ba	401	* @}
bogdanm	73:1efda918f0ba	402	*/
bogdanm	73:1efda918f0ba	403
bogdanm	73:1efda918f0ba	404	/** @defgroup TIM_Output_Compare_N_Polarity
bogdanm	73:1efda918f0ba	405	* @{
bogdanm	73:1efda918f0ba	406	*/
bogdanm	73:1efda918f0ba	407
bogdanm	73:1efda918f0ba	408	#define TIM_OCNPolarity_High ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	409	#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	410	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) \|\| \
bogdanm	73:1efda918f0ba	411	((POLARITY) == TIM_OCNPolarity_Low))
bogdanm	73:1efda918f0ba	412	/**
bogdanm	73:1efda918f0ba	413	* @}
bogdanm	73:1efda918f0ba	414	*/
bogdanm	73:1efda918f0ba	415
bogdanm	73:1efda918f0ba	416	/** @defgroup TIM_Output_Compare_state
bogdanm	73:1efda918f0ba	417	* @{
bogdanm	73:1efda918f0ba	418	*/
bogdanm	73:1efda918f0ba	419
bogdanm	73:1efda918f0ba	420	#define TIM_OutputState_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	421	#define TIM_OutputState_Enable ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	422	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) \|\| \
bogdanm	73:1efda918f0ba	423	((STATE) == TIM_OutputState_Enable))
bogdanm	73:1efda918f0ba	424	/**
bogdanm	73:1efda918f0ba	425	* @}
bogdanm	73:1efda918f0ba	426	*/
bogdanm	73:1efda918f0ba	427
bogdanm	73:1efda918f0ba	428	/** @defgroup TIM_Output_Compare_N_state
bogdanm	73:1efda918f0ba	429	* @{
bogdanm	73:1efda918f0ba	430	*/
bogdanm	73:1efda918f0ba	431
bogdanm	73:1efda918f0ba	432	#define TIM_OutputNState_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	433	#define TIM_OutputNState_Enable ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	434	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) \|\| \
bogdanm	73:1efda918f0ba	435	((STATE) == TIM_OutputNState_Enable))
bogdanm	73:1efda918f0ba	436	/**
bogdanm	73:1efda918f0ba	437	* @}
bogdanm	73:1efda918f0ba	438	*/
bogdanm	73:1efda918f0ba	439
bogdanm	73:1efda918f0ba	440	/** @defgroup TIM_Capture_Compare_state
bogdanm	73:1efda918f0ba	441	* @{
bogdanm	73:1efda918f0ba	442	*/
bogdanm	73:1efda918f0ba	443
bogdanm	73:1efda918f0ba	444	#define TIM_CCx_Enable ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	445	#define TIM_CCx_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	446	#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) \|\| \
bogdanm	73:1efda918f0ba	447	((CCX) == TIM_CCx_Disable))
bogdanm	73:1efda918f0ba	448	/**
bogdanm	73:1efda918f0ba	449	* @}
bogdanm	73:1efda918f0ba	450	*/
bogdanm	73:1efda918f0ba	451
bogdanm	73:1efda918f0ba	452	/** @defgroup TIM_Capture_Compare_N_state
bogdanm	73:1efda918f0ba	453	* @{
bogdanm	73:1efda918f0ba	454	*/
bogdanm	73:1efda918f0ba	455
bogdanm	73:1efda918f0ba	456	#define TIM_CCxN_Enable ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	457	#define TIM_CCxN_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	458	#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) \|\| \
bogdanm	73:1efda918f0ba	459	((CCXN) == TIM_CCxN_Disable))
bogdanm	73:1efda918f0ba	460	/**
bogdanm	73:1efda918f0ba	461	* @}
bogdanm	73:1efda918f0ba	462	*/
bogdanm	73:1efda918f0ba	463
bogdanm	73:1efda918f0ba	464	/** @defgroup Break_Input_enable_disable
bogdanm	73:1efda918f0ba	465	* @{
bogdanm	73:1efda918f0ba	466	*/
bogdanm	73:1efda918f0ba	467
bogdanm	73:1efda918f0ba	468	#define TIM_Break_Enable ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	469	#define TIM_Break_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	470	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) \|\| \
bogdanm	73:1efda918f0ba	471	((STATE) == TIM_Break_Disable))
bogdanm	73:1efda918f0ba	472	/**
bogdanm	73:1efda918f0ba	473	* @}
bogdanm	73:1efda918f0ba	474	*/
bogdanm	73:1efda918f0ba	475
bogdanm	73:1efda918f0ba	476	/** @defgroup Break_Polarity
bogdanm	73:1efda918f0ba	477	* @{
bogdanm	73:1efda918f0ba	478	*/
bogdanm	73:1efda918f0ba	479
bogdanm	73:1efda918f0ba	480	#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	481	#define TIM_BreakPolarity_High ((uint16_t)0x2000)
bogdanm	73:1efda918f0ba	482	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) \|\| \
bogdanm	73:1efda918f0ba	483	((POLARITY) == TIM_BreakPolarity_High))
bogdanm	73:1efda918f0ba	484	/**
bogdanm	73:1efda918f0ba	485	* @}
bogdanm	73:1efda918f0ba	486	*/
bogdanm	73:1efda918f0ba	487
bogdanm	73:1efda918f0ba	488	/** @defgroup TIM_AOE_Bit_Set_Reset
bogdanm	73:1efda918f0ba	489	* @{
bogdanm	73:1efda918f0ba	490	*/
bogdanm	73:1efda918f0ba	491
bogdanm	73:1efda918f0ba	492	#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
bogdanm	73:1efda918f0ba	493	#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	494	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) \|\| \
bogdanm	73:1efda918f0ba	495	((STATE) == TIM_AutomaticOutput_Disable))
bogdanm	73:1efda918f0ba	496	/**
bogdanm	73:1efda918f0ba	497	* @}
bogdanm	73:1efda918f0ba	498	*/
bogdanm	73:1efda918f0ba	499
bogdanm	73:1efda918f0ba	500	/** @defgroup Lock_level
bogdanm	73:1efda918f0ba	501	* @{
bogdanm	73:1efda918f0ba	502	*/
bogdanm	73:1efda918f0ba	503
bogdanm	73:1efda918f0ba	504	#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	505	#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	506	#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	507	#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
bogdanm	73:1efda918f0ba	508	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) \|\| \
bogdanm	73:1efda918f0ba	509	((LEVEL) == TIM_LOCKLevel_1) \|\| \
bogdanm	73:1efda918f0ba	510	((LEVEL) == TIM_LOCKLevel_2) \|\| \
bogdanm	73:1efda918f0ba	511	((LEVEL) == TIM_LOCKLevel_3))
bogdanm	73:1efda918f0ba	512	/**
bogdanm	73:1efda918f0ba	513	* @}
bogdanm	73:1efda918f0ba	514	*/
bogdanm	73:1efda918f0ba	515
bogdanm	73:1efda918f0ba	516	/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm	73:1efda918f0ba	517	* @{
bogdanm	73:1efda918f0ba	518	*/
bogdanm	73:1efda918f0ba	519
bogdanm	73:1efda918f0ba	520	#define TIM_OSSIState_Enable ((uint16_t)0x0400)
bogdanm	73:1efda918f0ba	521	#define TIM_OSSIState_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	522	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) \|\| \
bogdanm	73:1efda918f0ba	523	((STATE) == TIM_OSSIState_Disable))
bogdanm	73:1efda918f0ba	524	/**
bogdanm	73:1efda918f0ba	525	* @}
bogdanm	73:1efda918f0ba	526	*/
bogdanm	73:1efda918f0ba	527
bogdanm	73:1efda918f0ba	528	/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
bogdanm	73:1efda918f0ba	529	* @{
bogdanm	73:1efda918f0ba	530	*/
bogdanm	73:1efda918f0ba	531
bogdanm	73:1efda918f0ba	532	#define TIM_OSSRState_Enable ((uint16_t)0x0800)
bogdanm	73:1efda918f0ba	533	#define TIM_OSSRState_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	534	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) \|\| \
bogdanm	73:1efda918f0ba	535	((STATE) == TIM_OSSRState_Disable))
bogdanm	73:1efda918f0ba	536	/**
bogdanm	73:1efda918f0ba	537	* @}
bogdanm	73:1efda918f0ba	538	*/
bogdanm	73:1efda918f0ba	539
bogdanm	73:1efda918f0ba	540	/** @defgroup TIM_Output_Compare_Idle_State
bogdanm	73:1efda918f0ba	541	* @{
bogdanm	73:1efda918f0ba	542	*/
bogdanm	73:1efda918f0ba	543
bogdanm	73:1efda918f0ba	544	#define TIM_OCIdleState_Set ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	545	#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	546	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) \|\| \
bogdanm	73:1efda918f0ba	547	((STATE) == TIM_OCIdleState_Reset))
bogdanm	73:1efda918f0ba	548	/**
bogdanm	73:1efda918f0ba	549	* @}
bogdanm	73:1efda918f0ba	550	*/
bogdanm	73:1efda918f0ba	551
bogdanm	73:1efda918f0ba	552	/** @defgroup TIM_Output_Compare_N_Idle_State
bogdanm	73:1efda918f0ba	553	* @{
bogdanm	73:1efda918f0ba	554	*/
bogdanm	73:1efda918f0ba	555
bogdanm	73:1efda918f0ba	556	#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	557	#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	558	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) \|\| \
bogdanm	73:1efda918f0ba	559	((STATE) == TIM_OCNIdleState_Reset))
bogdanm	73:1efda918f0ba	560	/**
bogdanm	73:1efda918f0ba	561	* @}
bogdanm	73:1efda918f0ba	562	*/
bogdanm	73:1efda918f0ba	563
bogdanm	73:1efda918f0ba	564	/** @defgroup TIM_Input_Capture_Polarity
bogdanm	73:1efda918f0ba	565	* @{
bogdanm	73:1efda918f0ba	566	*/
bogdanm	73:1efda918f0ba	567
bogdanm	73:1efda918f0ba	568	#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	569	#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	570	#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
bogdanm	73:1efda918f0ba	571	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) \|\| \
bogdanm	73:1efda918f0ba	572	((POLARITY) == TIM_ICPolarity_Falling))
bogdanm	73:1efda918f0ba	573	#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) \|\| \
bogdanm	73:1efda918f0ba	574	((POLARITY) == TIM_ICPolarity_Falling)\|\| \
bogdanm	73:1efda918f0ba	575	((POLARITY) == TIM_ICPolarity_BothEdge))
bogdanm	73:1efda918f0ba	576	/**
bogdanm	73:1efda918f0ba	577	* @}
bogdanm	73:1efda918f0ba	578	*/
bogdanm	73:1efda918f0ba	579
bogdanm	73:1efda918f0ba	580	/** @defgroup TIM_Input_Capture_Selection
bogdanm	73:1efda918f0ba	581	* @{
bogdanm	73:1efda918f0ba	582	*/
bogdanm	73:1efda918f0ba	583
bogdanm	73:1efda918f0ba	584	#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	73:1efda918f0ba	585	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	73:1efda918f0ba	586	#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	73:1efda918f0ba	587	connected to IC2, IC1, IC4 or IC3, respectively. */
bogdanm	73:1efda918f0ba	588	#define TIM_ICSelection_TRC ((uint16_t)0x0003) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. /
bogdanm	73:1efda918f0ba	589	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) \|\| \
bogdanm	73:1efda918f0ba	590	((SELECTION) == TIM_ICSelection_IndirectTI) \|\| \
bogdanm	73:1efda918f0ba	591	((SELECTION) == TIM_ICSelection_TRC))
bogdanm	73:1efda918f0ba	592	/**
bogdanm	73:1efda918f0ba	593	* @}
bogdanm	73:1efda918f0ba	594	*/
bogdanm	73:1efda918f0ba	595
bogdanm	73:1efda918f0ba	596	/** @defgroup TIM_Input_Capture_Prescaler
bogdanm	73:1efda918f0ba	597	* @{
bogdanm	73:1efda918f0ba	598	*/
bogdanm	73:1efda918f0ba	599
bogdanm	73:1efda918f0ba	600	#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /!< Capture performed each time an edge is detected on the capture input. /
bogdanm	73:1efda918f0ba	601	#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /!< Capture performed once every 2 events. /
bogdanm	73:1efda918f0ba	602	#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /!< Capture performed once every 4 events. /
bogdanm	73:1efda918f0ba	603	#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /!< Capture performed once every 8 events. /
bogdanm	73:1efda918f0ba	604	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	73:1efda918f0ba	605	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	73:1efda918f0ba	606	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	73:1efda918f0ba	607	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	73:1efda918f0ba	608	/**
bogdanm	73:1efda918f0ba	609	* @}
bogdanm	73:1efda918f0ba	610	*/
bogdanm	73:1efda918f0ba	611
bogdanm	73:1efda918f0ba	612	/** @defgroup TIM_interrupt_sources
bogdanm	73:1efda918f0ba	613	* @{
bogdanm	73:1efda918f0ba	614	*/
bogdanm	73:1efda918f0ba	615
bogdanm	73:1efda918f0ba	616	#define TIM_IT_Update ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	617	#define TIM_IT_CC1 ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	618	#define TIM_IT_CC2 ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	619	#define TIM_IT_CC3 ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	620	#define TIM_IT_CC4 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	621	#define TIM_IT_COM ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	622	#define TIM_IT_Trigger ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	623	#define TIM_IT_Break ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	624	#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
bogdanm	73:1efda918f0ba	625
bogdanm	73:1efda918f0ba	626	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) \|\| \
bogdanm	73:1efda918f0ba	627	((IT) == TIM_IT_CC1) \|\| \
bogdanm	73:1efda918f0ba	628	((IT) == TIM_IT_CC2) \|\| \
bogdanm	73:1efda918f0ba	629	((IT) == TIM_IT_CC3) \|\| \
bogdanm	73:1efda918f0ba	630	((IT) == TIM_IT_CC4) \|\| \
bogdanm	73:1efda918f0ba	631	((IT) == TIM_IT_COM) \|\| \
bogdanm	73:1efda918f0ba	632	((IT) == TIM_IT_Trigger) \|\| \
bogdanm	73:1efda918f0ba	633	((IT) == TIM_IT_Break))
bogdanm	73:1efda918f0ba	634	/**
bogdanm	73:1efda918f0ba	635	* @}
bogdanm	73:1efda918f0ba	636	*/
bogdanm	73:1efda918f0ba	637
bogdanm	73:1efda918f0ba	638	/** @defgroup TIM_DMA_Base_address
bogdanm	73:1efda918f0ba	639	* @{
bogdanm	73:1efda918f0ba	640	*/
bogdanm	73:1efda918f0ba	641
bogdanm	73:1efda918f0ba	642	#define TIM_DMABase_CR1 ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	643	#define TIM_DMABase_CR2 ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	644	#define TIM_DMABase_SMCR ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	645	#define TIM_DMABase_DIER ((uint16_t)0x0003)
bogdanm	73:1efda918f0ba	646	#define TIM_DMABase_SR ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	647	#define TIM_DMABase_EGR ((uint16_t)0x0005)
bogdanm	73:1efda918f0ba	648	#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
bogdanm	73:1efda918f0ba	649	#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
bogdanm	73:1efda918f0ba	650	#define TIM_DMABase_CCER ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	651	#define TIM_DMABase_CNT ((uint16_t)0x0009)
bogdanm	73:1efda918f0ba	652	#define TIM_DMABase_PSC ((uint16_t)0x000A)
bogdanm	73:1efda918f0ba	653	#define TIM_DMABase_ARR ((uint16_t)0x000B)
bogdanm	73:1efda918f0ba	654	#define TIM_DMABase_RCR ((uint16_t)0x000C)
bogdanm	73:1efda918f0ba	655	#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
bogdanm	73:1efda918f0ba	656	#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
bogdanm	73:1efda918f0ba	657	#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
bogdanm	73:1efda918f0ba	658	#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	659	#define TIM_DMABase_BDTR ((uint16_t)0x0011)
bogdanm	73:1efda918f0ba	660	#define TIM_DMABase_DCR ((uint16_t)0x0012)
bogdanm	73:1efda918f0ba	661	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
bogdanm	73:1efda918f0ba	662	((BASE) == TIM_DMABase_CR2) \|\| \
bogdanm	73:1efda918f0ba	663	((BASE) == TIM_DMABase_SMCR) \|\| \
bogdanm	73:1efda918f0ba	664	((BASE) == TIM_DMABase_DIER) \|\| \
bogdanm	73:1efda918f0ba	665	((BASE) == TIM_DMABase_SR) \|\| \
bogdanm	73:1efda918f0ba	666	((BASE) == TIM_DMABase_EGR) \|\| \
bogdanm	73:1efda918f0ba	667	((BASE) == TIM_DMABase_CCMR1) \|\| \
bogdanm	73:1efda918f0ba	668	((BASE) == TIM_DMABase_CCMR2) \|\| \
bogdanm	73:1efda918f0ba	669	((BASE) == TIM_DMABase_CCER) \|\| \
bogdanm	73:1efda918f0ba	670	((BASE) == TIM_DMABase_CNT) \|\| \
bogdanm	73:1efda918f0ba	671	((BASE) == TIM_DMABase_PSC) \|\| \
bogdanm	73:1efda918f0ba	672	((BASE) == TIM_DMABase_ARR) \|\| \
bogdanm	73:1efda918f0ba	673	((BASE) == TIM_DMABase_RCR) \|\| \
bogdanm	73:1efda918f0ba	674	((BASE) == TIM_DMABase_CCR1) \|\| \
bogdanm	73:1efda918f0ba	675	((BASE) == TIM_DMABase_CCR2) \|\| \
bogdanm	73:1efda918f0ba	676	((BASE) == TIM_DMABase_CCR3) \|\| \
bogdanm	73:1efda918f0ba	677	((BASE) == TIM_DMABase_CCR4) \|\| \
bogdanm	73:1efda918f0ba	678	((BASE) == TIM_DMABase_BDTR) \|\| \
bogdanm	73:1efda918f0ba	679	((BASE) == TIM_DMABase_DCR))
bogdanm	73:1efda918f0ba	680	/**
bogdanm	73:1efda918f0ba	681	* @}
bogdanm	73:1efda918f0ba	682	*/
bogdanm	73:1efda918f0ba	683
bogdanm	73:1efda918f0ba	684	/** @defgroup TIM_DMA_Burst_Length
bogdanm	73:1efda918f0ba	685	* @{
bogdanm	73:1efda918f0ba	686	*/
bogdanm	73:1efda918f0ba	687
bogdanm	73:1efda918f0ba	688	#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	689	#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	690	#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	691	#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
bogdanm	73:1efda918f0ba	692	#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
bogdanm	73:1efda918f0ba	693	#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
bogdanm	73:1efda918f0ba	694	#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
bogdanm	73:1efda918f0ba	695	#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
bogdanm	73:1efda918f0ba	696	#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
bogdanm	73:1efda918f0ba	697	#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
bogdanm	73:1efda918f0ba	698	#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
bogdanm	73:1efda918f0ba	699	#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
bogdanm	73:1efda918f0ba	700	#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
bogdanm	73:1efda918f0ba	701	#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
bogdanm	73:1efda918f0ba	702	#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
bogdanm	73:1efda918f0ba	703	#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
bogdanm	73:1efda918f0ba	704	#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	705	#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
bogdanm	73:1efda918f0ba	706	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
bogdanm	73:1efda918f0ba	707	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
bogdanm	73:1efda918f0ba	708	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
bogdanm	73:1efda918f0ba	709	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
bogdanm	73:1efda918f0ba	710	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
bogdanm	73:1efda918f0ba	711	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
bogdanm	73:1efda918f0ba	712	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
bogdanm	73:1efda918f0ba	713	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
bogdanm	73:1efda918f0ba	714	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
bogdanm	73:1efda918f0ba	715	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
bogdanm	73:1efda918f0ba	716	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
bogdanm	73:1efda918f0ba	717	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
bogdanm	73:1efda918f0ba	718	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
bogdanm	73:1efda918f0ba	719	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
bogdanm	73:1efda918f0ba	720	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
bogdanm	73:1efda918f0ba	721	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
bogdanm	73:1efda918f0ba	722	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
bogdanm	73:1efda918f0ba	723	((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm	73:1efda918f0ba	724	/**
bogdanm	73:1efda918f0ba	725	* @}
bogdanm	73:1efda918f0ba	726	*/
bogdanm	73:1efda918f0ba	727
bogdanm	73:1efda918f0ba	728	/** @defgroup TIM_DMA_sources
bogdanm	73:1efda918f0ba	729	* @{
bogdanm	73:1efda918f0ba	730	*/
bogdanm	73:1efda918f0ba	731
bogdanm	73:1efda918f0ba	732	#define TIM_DMA_Update ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	733	#define TIM_DMA_CC1 ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	734	#define TIM_DMA_CC2 ((uint16_t)0x0400)
bogdanm	73:1efda918f0ba	735	#define TIM_DMA_CC3 ((uint16_t)0x0800)
bogdanm	73:1efda918f0ba	736	#define TIM_DMA_CC4 ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	737	#define TIM_DMA_COM ((uint16_t)0x2000)
bogdanm	73:1efda918f0ba	738	#define TIM_DMA_Trigger ((uint16_t)0x4000)
bogdanm	73:1efda918f0ba	739	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
bogdanm	73:1efda918f0ba	740
bogdanm	73:1efda918f0ba	741	/**
bogdanm	73:1efda918f0ba	742	* @}
bogdanm	73:1efda918f0ba	743	*/
bogdanm	73:1efda918f0ba	744
bogdanm	73:1efda918f0ba	745	/** @defgroup TIM_External_Trigger_Prescaler
bogdanm	73:1efda918f0ba	746	* @{
bogdanm	73:1efda918f0ba	747	*/
bogdanm	73:1efda918f0ba	748
bogdanm	73:1efda918f0ba	749	#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	750	#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	751	#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
bogdanm	73:1efda918f0ba	752	#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
bogdanm	73:1efda918f0ba	753	#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) \|\| \
bogdanm	73:1efda918f0ba	754	((PRESCALER) == TIM_ExtTRGPSC_DIV2) \|\| \
bogdanm	73:1efda918f0ba	755	((PRESCALER) == TIM_ExtTRGPSC_DIV4) \|\| \
bogdanm	73:1efda918f0ba	756	((PRESCALER) == TIM_ExtTRGPSC_DIV8))
bogdanm	73:1efda918f0ba	757	/**
bogdanm	73:1efda918f0ba	758	* @}
bogdanm	73:1efda918f0ba	759	*/
bogdanm	73:1efda918f0ba	760
bogdanm	73:1efda918f0ba	761	/** @defgroup TIM_Internal_Trigger_Selection
bogdanm	73:1efda918f0ba	762	* @{
bogdanm	73:1efda918f0ba	763	*/
bogdanm	73:1efda918f0ba	764
bogdanm	73:1efda918f0ba	765	#define TIM_TS_ITR0 ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	766	#define TIM_TS_ITR1 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	767	#define TIM_TS_ITR2 ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	768	#define TIM_TS_ITR3 ((uint16_t)0x0030)
bogdanm	73:1efda918f0ba	769	#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	770	#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
bogdanm	73:1efda918f0ba	771	#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	772	#define TIM_TS_ETRF ((uint16_t)0x0070)
bogdanm	73:1efda918f0ba	773	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	73:1efda918f0ba	774	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	73:1efda918f0ba	775	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	73:1efda918f0ba	776	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	73:1efda918f0ba	777	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	73:1efda918f0ba	778	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	73:1efda918f0ba	779	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	73:1efda918f0ba	780	((SELECTION) == TIM_TS_ETRF))
bogdanm	73:1efda918f0ba	781	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	73:1efda918f0ba	782	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	73:1efda918f0ba	783	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	73:1efda918f0ba	784	((SELECTION) == TIM_TS_ITR3))
bogdanm	73:1efda918f0ba	785	/**
bogdanm	73:1efda918f0ba	786	* @}
bogdanm	73:1efda918f0ba	787	*/
bogdanm	73:1efda918f0ba	788
bogdanm	73:1efda918f0ba	789	/** @defgroup TIM_TIx_External_Clock_Source
bogdanm	73:1efda918f0ba	790	* @{
bogdanm	73:1efda918f0ba	791	*/
bogdanm	73:1efda918f0ba	792
bogdanm	73:1efda918f0ba	793	#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
bogdanm	73:1efda918f0ba	794	#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	795	#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	796	#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) \|\| \
bogdanm	73:1efda918f0ba	797	((SOURCE) == TIM_TIxExternalCLK1Source_TI2) \|\| \
bogdanm	73:1efda918f0ba	798	((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
bogdanm	73:1efda918f0ba	799	/**
bogdanm	73:1efda918f0ba	800	* @}
bogdanm	73:1efda918f0ba	801	*/
bogdanm	73:1efda918f0ba	802
bogdanm	73:1efda918f0ba	803	/** @defgroup TIM_External_Trigger_Polarity
bogdanm	73:1efda918f0ba	804	* @{
bogdanm	73:1efda918f0ba	805	*/
bogdanm	73:1efda918f0ba	806	#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
bogdanm	73:1efda918f0ba	807	#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	808	#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) \|\| \
bogdanm	73:1efda918f0ba	809	((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
bogdanm	73:1efda918f0ba	810	/**
bogdanm	73:1efda918f0ba	811	* @}
bogdanm	73:1efda918f0ba	812	*/
bogdanm	73:1efda918f0ba	813
bogdanm	73:1efda918f0ba	814	/** @defgroup TIM_Prescaler_Reload_Mode
bogdanm	73:1efda918f0ba	815	* @{
bogdanm	73:1efda918f0ba	816	*/
bogdanm	73:1efda918f0ba	817
bogdanm	73:1efda918f0ba	818	#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	819	#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	820	#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) \|\| \
bogdanm	73:1efda918f0ba	821	((RELOAD) == TIM_PSCReloadMode_Immediate))
bogdanm	73:1efda918f0ba	822	/**
bogdanm	73:1efda918f0ba	823	* @}
bogdanm	73:1efda918f0ba	824	*/
bogdanm	73:1efda918f0ba	825
bogdanm	73:1efda918f0ba	826	/** @defgroup TIM_Forced_Action
bogdanm	73:1efda918f0ba	827	* @{
bogdanm	73:1efda918f0ba	828	*/
bogdanm	73:1efda918f0ba	829
bogdanm	73:1efda918f0ba	830	#define TIM_ForcedAction_Active ((uint16_t)0x0050)
bogdanm	73:1efda918f0ba	831	#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	832	#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) \|\| \
bogdanm	73:1efda918f0ba	833	((ACTION) == TIM_ForcedAction_InActive))
bogdanm	73:1efda918f0ba	834	/**
bogdanm	73:1efda918f0ba	835	* @}
bogdanm	73:1efda918f0ba	836	*/
bogdanm	73:1efda918f0ba	837
bogdanm	73:1efda918f0ba	838	/** @defgroup TIM_Encoder_Mode
bogdanm	73:1efda918f0ba	839	* @{
bogdanm	73:1efda918f0ba	840	*/
bogdanm	73:1efda918f0ba	841
bogdanm	73:1efda918f0ba	842	#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	843	#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	844	#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
bogdanm	73:1efda918f0ba	845	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) \|\| \
bogdanm	73:1efda918f0ba	846	((MODE) == TIM_EncoderMode_TI2) \|\| \
bogdanm	73:1efda918f0ba	847	((MODE) == TIM_EncoderMode_TI12))
bogdanm	73:1efda918f0ba	848	/**
bogdanm	73:1efda918f0ba	849	* @}
bogdanm	73:1efda918f0ba	850	*/
bogdanm	73:1efda918f0ba	851
bogdanm	73:1efda918f0ba	852
bogdanm	73:1efda918f0ba	853	/** @defgroup TIM_Event_Source
bogdanm	73:1efda918f0ba	854	* @{
bogdanm	73:1efda918f0ba	855	*/
bogdanm	73:1efda918f0ba	856
bogdanm	73:1efda918f0ba	857	#define TIM_EventSource_Update ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	858	#define TIM_EventSource_CC1 ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	859	#define TIM_EventSource_CC2 ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	860	#define TIM_EventSource_CC3 ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	861	#define TIM_EventSource_CC4 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	862	#define TIM_EventSource_COM ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	863	#define TIM_EventSource_Trigger ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	864	#define TIM_EventSource_Break ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	865	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
bogdanm	73:1efda918f0ba	866
bogdanm	73:1efda918f0ba	867	/**
bogdanm	73:1efda918f0ba	868	* @}
bogdanm	73:1efda918f0ba	869	*/
bogdanm	73:1efda918f0ba	870
bogdanm	73:1efda918f0ba	871	/** @defgroup TIM_Update_Source
bogdanm	73:1efda918f0ba	872	* @{
bogdanm	73:1efda918f0ba	873	*/
bogdanm	73:1efda918f0ba	874
bogdanm	73:1efda918f0ba	875	#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
bogdanm	73:1efda918f0ba	876	or the setting of UG bit, or an update generation
bogdanm	73:1efda918f0ba	877	through the slave mode controller. */
bogdanm	73:1efda918f0ba	878	#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /!< Source of update is counter overflow/underflow. /
bogdanm	73:1efda918f0ba	879	#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) \|\| \
bogdanm	73:1efda918f0ba	880	((SOURCE) == TIM_UpdateSource_Regular))
bogdanm	73:1efda918f0ba	881	/**
bogdanm	73:1efda918f0ba	882	* @}
bogdanm	73:1efda918f0ba	883	*/
bogdanm	73:1efda918f0ba	884
bogdanm	73:1efda918f0ba	885	/** @defgroup TIM_Output_Compare_Preload_State
bogdanm	73:1efda918f0ba	886	* @{
bogdanm	73:1efda918f0ba	887	*/
bogdanm	73:1efda918f0ba	888
bogdanm	73:1efda918f0ba	889	#define TIM_OCPreload_Enable ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	890	#define TIM_OCPreload_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	891	#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) \|\| \
bogdanm	73:1efda918f0ba	892	((STATE) == TIM_OCPreload_Disable))
bogdanm	73:1efda918f0ba	893	/**
bogdanm	73:1efda918f0ba	894	* @}
bogdanm	73:1efda918f0ba	895	*/
bogdanm	73:1efda918f0ba	896
bogdanm	73:1efda918f0ba	897	/** @defgroup TIM_Output_Compare_Fast_State
bogdanm	73:1efda918f0ba	898	* @{
bogdanm	73:1efda918f0ba	899	*/
bogdanm	73:1efda918f0ba	900
bogdanm	73:1efda918f0ba	901	#define TIM_OCFast_Enable ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	902	#define TIM_OCFast_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	903	#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) \|\| \
bogdanm	73:1efda918f0ba	904	((STATE) == TIM_OCFast_Disable))
bogdanm	73:1efda918f0ba	905
bogdanm	73:1efda918f0ba	906	/**
bogdanm	73:1efda918f0ba	907	* @}
bogdanm	73:1efda918f0ba	908	*/
bogdanm	73:1efda918f0ba	909
bogdanm	73:1efda918f0ba	910	/** @defgroup TIM_Output_Compare_Clear_State
bogdanm	73:1efda918f0ba	911	* @{
bogdanm	73:1efda918f0ba	912	*/
bogdanm	73:1efda918f0ba	913
bogdanm	73:1efda918f0ba	914	#define TIM_OCClear_Enable ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	915	#define TIM_OCClear_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	916	#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) \|\| \
bogdanm	73:1efda918f0ba	917	((STATE) == TIM_OCClear_Disable))
bogdanm	73:1efda918f0ba	918	/**
bogdanm	73:1efda918f0ba	919	* @}
bogdanm	73:1efda918f0ba	920	*/
bogdanm	73:1efda918f0ba	921
bogdanm	73:1efda918f0ba	922	/** @defgroup TIM_Trigger_Output_Source
bogdanm	73:1efda918f0ba	923	* @{
bogdanm	73:1efda918f0ba	924	*/
bogdanm	73:1efda918f0ba	925
bogdanm	73:1efda918f0ba	926	#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	927	#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	928	#define TIM_TRGOSource_Update ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	929	#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
bogdanm	73:1efda918f0ba	930	#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	931	#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
bogdanm	73:1efda918f0ba	932	#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	933	#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
bogdanm	73:1efda918f0ba	934	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) \|\| \
bogdanm	73:1efda918f0ba	935	((SOURCE) == TIM_TRGOSource_Enable) \|\| \
bogdanm	73:1efda918f0ba	936	((SOURCE) == TIM_TRGOSource_Update) \|\| \
bogdanm	73:1efda918f0ba	937	((SOURCE) == TIM_TRGOSource_OC1) \|\| \
bogdanm	73:1efda918f0ba	938	((SOURCE) == TIM_TRGOSource_OC1Ref) \|\| \
bogdanm	73:1efda918f0ba	939	((SOURCE) == TIM_TRGOSource_OC2Ref) \|\| \
bogdanm	73:1efda918f0ba	940	((SOURCE) == TIM_TRGOSource_OC3Ref) \|\| \
bogdanm	73:1efda918f0ba	941	((SOURCE) == TIM_TRGOSource_OC4Ref))
bogdanm	73:1efda918f0ba	942	/**
bogdanm	73:1efda918f0ba	943	* @}
bogdanm	73:1efda918f0ba	944	*/
bogdanm	73:1efda918f0ba	945
bogdanm	73:1efda918f0ba	946	/** @defgroup TIM_Slave_Mode
bogdanm	73:1efda918f0ba	947	* @{
bogdanm	73:1efda918f0ba	948	*/
bogdanm	73:1efda918f0ba	949
bogdanm	73:1efda918f0ba	950	#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	951	#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
bogdanm	73:1efda918f0ba	952	#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
bogdanm	73:1efda918f0ba	953	#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
bogdanm	73:1efda918f0ba	954	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) \|\| \
bogdanm	73:1efda918f0ba	955	((MODE) == TIM_SlaveMode_Gated) \|\| \
bogdanm	73:1efda918f0ba	956	((MODE) == TIM_SlaveMode_Trigger) \|\| \
bogdanm	73:1efda918f0ba	957	((MODE) == TIM_SlaveMode_External1))
bogdanm	73:1efda918f0ba	958	/**
bogdanm	73:1efda918f0ba	959	* @}
bogdanm	73:1efda918f0ba	960	*/
bogdanm	73:1efda918f0ba	961
bogdanm	73:1efda918f0ba	962	/** @defgroup TIM_Master_Slave_Mode
bogdanm	73:1efda918f0ba	963	* @{
bogdanm	73:1efda918f0ba	964	*/
bogdanm	73:1efda918f0ba	965
bogdanm	73:1efda918f0ba	966	#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	967	#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	968	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) \|\| \
bogdanm	73:1efda918f0ba	969	((STATE) == TIM_MasterSlaveMode_Disable))
bogdanm	73:1efda918f0ba	970	/**
bogdanm	73:1efda918f0ba	971	* @}
bogdanm	73:1efda918f0ba	972	*/
bogdanm	73:1efda918f0ba	973
bogdanm	73:1efda918f0ba	974	/** @defgroup TIM_Flags
bogdanm	73:1efda918f0ba	975	* @{
bogdanm	73:1efda918f0ba	976	*/
bogdanm	73:1efda918f0ba	977
bogdanm	73:1efda918f0ba	978	#define TIM_FLAG_Update ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	979	#define TIM_FLAG_CC1 ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	980	#define TIM_FLAG_CC2 ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	981	#define TIM_FLAG_CC3 ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	982	#define TIM_FLAG_CC4 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	983	#define TIM_FLAG_COM ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	984	#define TIM_FLAG_Trigger ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	985	#define TIM_FLAG_Break ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	986	#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	987	#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
bogdanm	73:1efda918f0ba	988	#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
bogdanm	73:1efda918f0ba	989	#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	990	#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) \|\| \
bogdanm	73:1efda918f0ba	991	((FLAG) == TIM_FLAG_CC1) \|\| \
bogdanm	73:1efda918f0ba	992	((FLAG) == TIM_FLAG_CC2) \|\| \
bogdanm	73:1efda918f0ba	993	((FLAG) == TIM_FLAG_CC3) \|\| \
bogdanm	73:1efda918f0ba	994	((FLAG) == TIM_FLAG_CC4) \|\| \
bogdanm	73:1efda918f0ba	995	((FLAG) == TIM_FLAG_COM) \|\| \
bogdanm	73:1efda918f0ba	996	((FLAG) == TIM_FLAG_Trigger) \|\| \
bogdanm	73:1efda918f0ba	997	((FLAG) == TIM_FLAG_Break) \|\| \
bogdanm	73:1efda918f0ba	998	((FLAG) == TIM_FLAG_CC1OF) \|\| \
bogdanm	73:1efda918f0ba	999	((FLAG) == TIM_FLAG_CC2OF) \|\| \
bogdanm	73:1efda918f0ba	1000	((FLAG) == TIM_FLAG_CC3OF) \|\| \
bogdanm	73:1efda918f0ba	1001	((FLAG) == TIM_FLAG_CC4OF))
bogdanm	73:1efda918f0ba	1002
bogdanm	73:1efda918f0ba	1003
bogdanm	73:1efda918f0ba	1004	#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
bogdanm	73:1efda918f0ba	1005	/**
bogdanm	73:1efda918f0ba	1006	* @}
bogdanm	73:1efda918f0ba	1007	*/
bogdanm	73:1efda918f0ba	1008
bogdanm	73:1efda918f0ba	1009	/** @defgroup TIM_Input_Capture_Filer_Value
bogdanm	73:1efda918f0ba	1010	* @{
bogdanm	73:1efda918f0ba	1011	*/
bogdanm	73:1efda918f0ba	1012
bogdanm	73:1efda918f0ba	1013	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	73:1efda918f0ba	1014	/**
bogdanm	73:1efda918f0ba	1015	* @}
bogdanm	73:1efda918f0ba	1016	*/
bogdanm	73:1efda918f0ba	1017
bogdanm	73:1efda918f0ba	1018	/** @defgroup TIM_External_Trigger_Filter
bogdanm	73:1efda918f0ba	1019	* @{
bogdanm	73:1efda918f0ba	1020	*/
bogdanm	73:1efda918f0ba	1021
bogdanm	73:1efda918f0ba	1022	#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
bogdanm	73:1efda918f0ba	1023	/**
bogdanm	73:1efda918f0ba	1024	* @}
bogdanm	73:1efda918f0ba	1025	*/
bogdanm	73:1efda918f0ba	1026
bogdanm	73:1efda918f0ba	1027	/** @defgroup TIM_Legacy
bogdanm	73:1efda918f0ba	1028	* @{
bogdanm	73:1efda918f0ba	1029	*/
bogdanm	73:1efda918f0ba	1030
bogdanm	73:1efda918f0ba	1031	#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
bogdanm	73:1efda918f0ba	1032	#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
bogdanm	73:1efda918f0ba	1033	#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
bogdanm	73:1efda918f0ba	1034	#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
bogdanm	73:1efda918f0ba	1035	#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
bogdanm	73:1efda918f0ba	1036	#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
bogdanm	73:1efda918f0ba	1037	#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
bogdanm	73:1efda918f0ba	1038	#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
bogdanm	73:1efda918f0ba	1039	#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
bogdanm	73:1efda918f0ba	1040	#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
bogdanm	73:1efda918f0ba	1041	#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
bogdanm	73:1efda918f0ba	1042	#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
bogdanm	73:1efda918f0ba	1043	#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
bogdanm	73:1efda918f0ba	1044	#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
bogdanm	73:1efda918f0ba	1045	#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
bogdanm	73:1efda918f0ba	1046	#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
bogdanm	73:1efda918f0ba	1047	#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
bogdanm	73:1efda918f0ba	1048	#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
bogdanm	73:1efda918f0ba	1049	/**
bogdanm	73:1efda918f0ba	1050	* @}
bogdanm	73:1efda918f0ba	1051	*/
bogdanm	73:1efda918f0ba	1052
bogdanm	73:1efda918f0ba	1053	/**
bogdanm	73:1efda918f0ba	1054	* @}
bogdanm	73:1efda918f0ba	1055	*/
bogdanm	73:1efda918f0ba	1056
bogdanm	73:1efda918f0ba	1057	/** @defgroup TIM_Exported_Macros
bogdanm	73:1efda918f0ba	1058	* @{
bogdanm	73:1efda918f0ba	1059	*/
bogdanm	73:1efda918f0ba	1060
bogdanm	73:1efda918f0ba	1061	/**
bogdanm	73:1efda918f0ba	1062	* @}
bogdanm	73:1efda918f0ba	1063	*/
bogdanm	73:1efda918f0ba	1064
bogdanm	73:1efda918f0ba	1065	/** @defgroup TIM_Exported_Functions
bogdanm	73:1efda918f0ba	1066	* @{
bogdanm	73:1efda918f0ba	1067	*/
bogdanm	73:1efda918f0ba	1068
bogdanm	73:1efda918f0ba	1069	void TIM_DeInit(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1070	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
bogdanm	73:1efda918f0ba	1071	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1072	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1073	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1074	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1075	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm	73:1efda918f0ba	1076	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm	73:1efda918f0ba	1077	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
bogdanm	73:1efda918f0ba	1078	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
bogdanm	73:1efda918f0ba	1079	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1080	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm	73:1efda918f0ba	1081	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
bogdanm	73:1efda918f0ba	1082	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1083	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1084	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1085	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
bogdanm	73:1efda918f0ba	1086	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
bogdanm	73:1efda918f0ba	1087	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1088	void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1089	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
bogdanm	73:1efda918f0ba	1090	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
bogdanm	73:1efda918f0ba	1091	uint16_t TIM_ICPolarity, uint16_t ICFilter);
bogdanm	73:1efda918f0ba	1092	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
bogdanm	73:1efda918f0ba	1093	uint16_t ExtTRGFilter);
bogdanm	73:1efda918f0ba	1094	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
bogdanm	73:1efda918f0ba	1095	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
bogdanm	73:1efda918f0ba	1096	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
bogdanm	73:1efda918f0ba	1097	uint16_t ExtTRGFilter);
bogdanm	73:1efda918f0ba	1098	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
bogdanm	73:1efda918f0ba	1099	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
bogdanm	73:1efda918f0ba	1100	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
bogdanm	73:1efda918f0ba	1101	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
bogdanm	73:1efda918f0ba	1102	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
bogdanm	73:1efda918f0ba	1103	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm	73:1efda918f0ba	1104	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm	73:1efda918f0ba	1105	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm	73:1efda918f0ba	1106	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm	73:1efda918f0ba	1107	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1108	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1109	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1110	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1111	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm	73:1efda918f0ba	1112	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm	73:1efda918f0ba	1113	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm	73:1efda918f0ba	1114	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm	73:1efda918f0ba	1115	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm	73:1efda918f0ba	1116	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm	73:1efda918f0ba	1117	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm	73:1efda918f0ba	1118	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm	73:1efda918f0ba	1119	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm	73:1efda918f0ba	1120	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm	73:1efda918f0ba	1121	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm	73:1efda918f0ba	1122	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm	73:1efda918f0ba	1123	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm	73:1efda918f0ba	1124	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm	73:1efda918f0ba	1125	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm	73:1efda918f0ba	1126	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm	73:1efda918f0ba	1127	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm	73:1efda918f0ba	1128	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm	73:1efda918f0ba	1129	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm	73:1efda918f0ba	1130	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
bogdanm	73:1efda918f0ba	1131	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
bogdanm	73:1efda918f0ba	1132	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
bogdanm	73:1efda918f0ba	1133	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1134	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
bogdanm	73:1efda918f0ba	1135	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1136	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
bogdanm	73:1efda918f0ba	1137	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
bogdanm	73:1efda918f0ba	1138	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
bogdanm	73:1efda918f0ba	1139	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
bogdanm	73:1efda918f0ba	1140	void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
bogdanm	73:1efda918f0ba	1141	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
bogdanm	73:1efda918f0ba	1142	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
bogdanm	73:1efda918f0ba	1143	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
bogdanm	73:1efda918f0ba	1144	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
bogdanm	73:1efda918f0ba	1145	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
bogdanm	73:1efda918f0ba	1146	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm	73:1efda918f0ba	1147	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm	73:1efda918f0ba	1148	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm	73:1efda918f0ba	1149	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm	73:1efda918f0ba	1150	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
bogdanm	73:1efda918f0ba	1151	uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1152	uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1153	uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1154	uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1155	uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1156	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1157	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
bogdanm	73:1efda918f0ba	1158	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
bogdanm	73:1efda918f0ba	1159	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
bogdanm	73:1efda918f0ba	1160	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
bogdanm	73:1efda918f0ba	1161
bogdanm	73:1efda918f0ba	1162	#ifdef __cplusplus
bogdanm	73:1efda918f0ba	1163	}
bogdanm	73:1efda918f0ba	1164	#endif
bogdanm	73:1efda918f0ba	1165
bogdanm	73:1efda918f0ba	1166	#endif /__STM32F10x_TIM_H /
bogdanm	73:1efda918f0ba	1167	/**
bogdanm	73:1efda918f0ba	1168	* @}
bogdanm	73:1efda918f0ba	1169	*/
bogdanm	73:1efda918f0ba	1170
bogdanm	73:1efda918f0ba	1171	/**
bogdanm	73:1efda918f0ba	1172	* @}
bogdanm	73:1efda918f0ba	1173	*/
bogdanm	73:1efda918f0ba	1174
bogdanm	73:1efda918f0ba	1175	/**
bogdanm	73:1efda918f0ba	1176	* @}
bogdanm	73:1efda918f0ba	1177	*/
bogdanm	73:1efda918f0ba	1178
bogdanm	73:1efda918f0ba	1179	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
Dependents:	0
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F103RB/stm32f10x_tim.h@76:824293ae5e43, 2014-01-13 (annotated)

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