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/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }
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TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h@81:7d30d6019079, 2014-03-19 (annotated)
- Committer:
- bogdanm
- Date:
- Wed Mar 19 18:28:32 2014 +0000
- Revision:
- 81:7d30d6019079
- Parent:
- 77:869cf507173a
- Child:
- 85:024bf7f99721
Release 81 of the mbed library
Main changes:
- Updates and fixes for many targets
- LPC1768: serial interface code fixes
- nRF51822 targets now output a .hex file
- More exporters
- More flexible GPIO API
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32f4xx_hal_flash_ex.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| bogdanm | 81:7d30d6019079 | 5 | * @version V1.0.0 |
| bogdanm | 81:7d30d6019079 | 6 | * @date 18-February-2014 |
| emilmont | 77:869cf507173a | 7 | * @brief Header file of FLASH HAL Extension module. |
| emilmont | 77:869cf507173a | 8 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 9 | * @attention |
| emilmont | 77:869cf507173a | 10 | * |
| emilmont | 77:869cf507173a | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 12 | * |
| emilmont | 77:869cf507173a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| emilmont | 77:869cf507173a | 14 | * are permitted provided that the following conditions are met: |
| emilmont | 77:869cf507173a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| emilmont | 77:869cf507173a | 16 | * this list of conditions and the following disclaimer. |
| emilmont | 77:869cf507173a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| emilmont | 77:869cf507173a | 18 | * this list of conditions and the following disclaimer in the documentation |
| emilmont | 77:869cf507173a | 19 | * and/or other materials provided with the distribution. |
| emilmont | 77:869cf507173a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| emilmont | 77:869cf507173a | 21 | * may be used to endorse or promote products derived from this software |
| emilmont | 77:869cf507173a | 22 | * without specific prior written permission. |
| emilmont | 77:869cf507173a | 23 | * |
| emilmont | 77:869cf507173a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| emilmont | 77:869cf507173a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| emilmont | 77:869cf507173a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| emilmont | 77:869cf507173a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| emilmont | 77:869cf507173a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| emilmont | 77:869cf507173a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| emilmont | 77:869cf507173a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| emilmont | 77:869cf507173a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| emilmont | 77:869cf507173a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| emilmont | 77:869cf507173a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| emilmont | 77:869cf507173a | 34 | * |
| emilmont | 77:869cf507173a | 35 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 36 | */ |
| emilmont | 77:869cf507173a | 37 | |
| emilmont | 77:869cf507173a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 39 | #ifndef __STM32F4xx_HAL_FLASH_EX_H |
| emilmont | 77:869cf507173a | 40 | #define __STM32F4xx_HAL_FLASH_EX_H |
| emilmont | 77:869cf507173a | 41 | |
| emilmont | 77:869cf507173a | 42 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 43 | extern "C" { |
| emilmont | 77:869cf507173a | 44 | #endif |
| emilmont | 77:869cf507173a | 45 | |
| emilmont | 77:869cf507173a | 46 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 47 | #include "stm32f4xx_hal_def.h" |
| emilmont | 77:869cf507173a | 48 | |
| emilmont | 77:869cf507173a | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| emilmont | 77:869cf507173a | 50 | * @{ |
| emilmont | 77:869cf507173a | 51 | */ |
| emilmont | 77:869cf507173a | 52 | |
| emilmont | 77:869cf507173a | 53 | /** @addtogroup FLASHEx |
| emilmont | 77:869cf507173a | 54 | * @{ |
| emilmont | 77:869cf507173a | 55 | */ |
| emilmont | 77:869cf507173a | 56 | |
| emilmont | 77:869cf507173a | 57 | /* Exported types ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 58 | |
| emilmont | 77:869cf507173a | 59 | /** |
| emilmont | 77:869cf507173a | 60 | * @brief FLASH Erase structure definition |
| emilmont | 77:869cf507173a | 61 | */ |
| emilmont | 77:869cf507173a | 62 | typedef struct |
| emilmont | 77:869cf507173a | 63 | { |
| emilmont | 77:869cf507173a | 64 | uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase. |
| emilmont | 77:869cf507173a | 65 | This parameter can be a value of @ref FLASHEx_Type_Erase */ |
| emilmont | 77:869cf507173a | 66 | |
| emilmont | 77:869cf507173a | 67 | uint32_t Banks; /*!< Banks: Select banks to erase when Mass erase is enabled |
| emilmont | 77:869cf507173a | 68 | This parameter must be a value of @ref FLASHEx_Banks */ |
| emilmont | 77:869cf507173a | 69 | |
| emilmont | 77:869cf507173a | 70 | uint32_t Sector; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled |
| emilmont | 77:869cf507173a | 71 | This parameter must be a value of @ref FLASHEx_Sectors */ |
| emilmont | 77:869cf507173a | 72 | |
| emilmont | 77:869cf507173a | 73 | uint32_t NbSectors; /*!< NbSectors: Number of sectors to be erased. |
| emilmont | 77:869cf507173a | 74 | This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ |
| emilmont | 77:869cf507173a | 75 | |
| emilmont | 77:869cf507173a | 76 | uint32_t VoltageRange;/*!< VoltageRange: The device voltage range which defines the erase parallelism |
| emilmont | 77:869cf507173a | 77 | This parameter must be a value of @ref FLASHEx_Voltage_Range */ |
| emilmont | 77:869cf507173a | 78 | |
| emilmont | 77:869cf507173a | 79 | } FLASH_EraseInitTypeDef; |
| emilmont | 77:869cf507173a | 80 | |
| emilmont | 77:869cf507173a | 81 | /** |
| emilmont | 77:869cf507173a | 82 | * @brief FLASH Option Bytes Program structure definition |
| emilmont | 77:869cf507173a | 83 | */ |
| emilmont | 77:869cf507173a | 84 | typedef struct |
| emilmont | 77:869cf507173a | 85 | { |
| emilmont | 77:869cf507173a | 86 | uint32_t OptionType; /*!< OptionType: Option byte to be configured. |
| emilmont | 77:869cf507173a | 87 | This parameter can be a value of @ref FLASHEx_Option_Type */ |
| emilmont | 77:869cf507173a | 88 | |
| emilmont | 77:869cf507173a | 89 | uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. |
| emilmont | 77:869cf507173a | 90 | This parameter can be a value of @ref FLASHEx_WRP_State */ |
| emilmont | 77:869cf507173a | 91 | |
| emilmont | 77:869cf507173a | 92 | uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected |
| emilmont | 77:869cf507173a | 93 | The value of this parameter depend on device used within the same series */ |
| emilmont | 77:869cf507173a | 94 | |
| emilmont | 77:869cf507173a | 95 | uint32_t Banks; /*!< Banks: Select banks for WRP activation/deactivation of all sectors |
| emilmont | 77:869cf507173a | 96 | This parameter must be a value of @ref FLASHEx_Banks */ |
| emilmont | 77:869cf507173a | 97 | |
| emilmont | 77:869cf507173a | 98 | uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level.. |
| emilmont | 77:869cf507173a | 99 | This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ |
| emilmont | 77:869cf507173a | 100 | |
| emilmont | 77:869cf507173a | 101 | uint32_t BORLevel; /*!< BORLevel: Set the BOR Level. |
| emilmont | 77:869cf507173a | 102 | This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ |
| emilmont | 77:869cf507173a | 103 | |
| emilmont | 77:869cf507173a | 104 | uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. |
| emilmont | 77:869cf507173a | 105 | This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ |
| emilmont | 77:869cf507173a | 106 | |
| emilmont | 77:869cf507173a | 107 | } FLASH_OBProgramInitTypeDef; |
| emilmont | 77:869cf507173a | 108 | |
| emilmont | 77:869cf507173a | 109 | /** |
| emilmont | 77:869cf507173a | 110 | * @brief FLASH Advanced Option Bytes Program structure definition |
| emilmont | 77:869cf507173a | 111 | */ |
| emilmont | 77:869cf507173a | 112 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 113 | typedef struct |
| emilmont | 77:869cf507173a | 114 | { |
| emilmont | 77:869cf507173a | 115 | uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . |
| emilmont | 77:869cf507173a | 116 | This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */ |
| emilmont | 77:869cf507173a | 117 | |
| emilmont | 77:869cf507173a | 118 | uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. |
| emilmont | 77:869cf507173a | 119 | This parameter can be a value of @ref FLASHEx_PCROP_State */ |
| emilmont | 77:869cf507173a | 120 | |
| emilmont | 77:869cf507173a | 121 | #if defined (STM32F401xC) || defined (STM32F401xE) |
| emilmont | 77:869cf507173a | 122 | uint16_t Sectors; /*!< Sectors: specifies the sector(s) set for PCROP |
| emilmont | 77:869cf507173a | 123 | This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ |
| emilmont | 77:869cf507173a | 124 | #endif /* STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 125 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 126 | uint32_t Banks; /*!< Banks: Select banks for PCROP activation/deactivation of all sectors |
| emilmont | 77:869cf507173a | 127 | This parameter must be a value of @ref FLASHEx_Banks */ |
| emilmont | 77:869cf507173a | 128 | |
| emilmont | 77:869cf507173a | 129 | uint16_t SectorsBank1; /*!< SectorsBank1: specifies the sector(s) set for PCROP for Bank1 |
| emilmont | 77:869cf507173a | 130 | This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ |
| emilmont | 77:869cf507173a | 131 | |
| emilmont | 77:869cf507173a | 132 | uint16_t SectorsBank2; /*!< SectorsBank2: specifies the sector(s) set for PCROP for Bank2 |
| emilmont | 77:869cf507173a | 133 | This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ |
| emilmont | 77:869cf507173a | 134 | |
| emilmont | 77:869cf507173a | 135 | uint8_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config |
| emilmont | 77:869cf507173a | 136 | This parameter can be a value of @ref FLASHEx_Dual_Boot */ |
| emilmont | 77:869cf507173a | 137 | |
| emilmont | 77:869cf507173a | 138 | #endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| emilmont | 77:869cf507173a | 139 | } FLASH_AdvOBProgramInitTypeDef; |
| emilmont | 77:869cf507173a | 140 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 141 | |
| emilmont | 77:869cf507173a | 142 | /* Exported constants --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 143 | |
| emilmont | 77:869cf507173a | 144 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants |
| emilmont | 77:869cf507173a | 145 | * @{ |
| emilmont | 77:869cf507173a | 146 | */ |
| emilmont | 77:869cf507173a | 147 | |
| emilmont | 77:869cf507173a | 148 | /** @defgroup FLASHEx_Type_Erase FLASH Type Erase |
| emilmont | 77:869cf507173a | 149 | * @{ |
| emilmont | 77:869cf507173a | 150 | */ |
| emilmont | 77:869cf507173a | 151 | #define TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */ |
| emilmont | 77:869cf507173a | 152 | #define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */ |
| emilmont | 77:869cf507173a | 153 | |
| emilmont | 77:869cf507173a | 154 | #define IS_TYPEERASE(VALUE)(((VALUE) == TYPEERASE_SECTORS) || \ |
| emilmont | 77:869cf507173a | 155 | ((VALUE) == TYPEERASE_MASSERASE)) |
| emilmont | 77:869cf507173a | 156 | |
| emilmont | 77:869cf507173a | 157 | /** |
| emilmont | 77:869cf507173a | 158 | * @} |
| emilmont | 77:869cf507173a | 159 | */ |
| emilmont | 77:869cf507173a | 160 | |
| emilmont | 77:869cf507173a | 161 | /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range |
| emilmont | 77:869cf507173a | 162 | * @{ |
| emilmont | 77:869cf507173a | 163 | */ |
| emilmont | 77:869cf507173a | 164 | #define VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ |
| emilmont | 77:869cf507173a | 165 | #define VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */ |
| emilmont | 77:869cf507173a | 166 | #define VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */ |
| emilmont | 77:869cf507173a | 167 | #define VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ |
| emilmont | 77:869cf507173a | 168 | |
| emilmont | 77:869cf507173a | 169 | #define IS_VOLTAGERANGE(RANGE)(((RANGE) == VOLTAGE_RANGE_1) || \ |
| emilmont | 77:869cf507173a | 170 | ((RANGE) == VOLTAGE_RANGE_2) || \ |
| emilmont | 77:869cf507173a | 171 | ((RANGE) == VOLTAGE_RANGE_3) || \ |
| emilmont | 77:869cf507173a | 172 | ((RANGE) == VOLTAGE_RANGE_4)) |
| emilmont | 77:869cf507173a | 173 | |
| emilmont | 77:869cf507173a | 174 | /** |
| emilmont | 77:869cf507173a | 175 | * @} |
| emilmont | 77:869cf507173a | 176 | */ |
| emilmont | 77:869cf507173a | 177 | |
| emilmont | 77:869cf507173a | 178 | /** @defgroup FLASHEx_WRP_State FLASH WRP State |
| emilmont | 77:869cf507173a | 179 | * @{ |
| emilmont | 77:869cf507173a | 180 | */ |
| emilmont | 77:869cf507173a | 181 | #define WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */ |
| emilmont | 77:869cf507173a | 182 | #define WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */ |
| emilmont | 77:869cf507173a | 183 | |
| emilmont | 77:869cf507173a | 184 | #define IS_WRPSTATE(VALUE)(((VALUE) == WRPSTATE_DISABLE) || \ |
| emilmont | 77:869cf507173a | 185 | ((VALUE) == WRPSTATE_ENABLE)) |
| emilmont | 77:869cf507173a | 186 | |
| emilmont | 77:869cf507173a | 187 | /** |
| emilmont | 77:869cf507173a | 188 | * @} |
| emilmont | 77:869cf507173a | 189 | */ |
| emilmont | 77:869cf507173a | 190 | |
| emilmont | 77:869cf507173a | 191 | /** @defgroup FLASHEx_Option_Type FLASH Option Type |
| emilmont | 77:869cf507173a | 192 | * @{ |
| emilmont | 77:869cf507173a | 193 | */ |
| emilmont | 77:869cf507173a | 194 | #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ |
| emilmont | 77:869cf507173a | 195 | #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ |
| emilmont | 77:869cf507173a | 196 | #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ |
| emilmont | 77:869cf507173a | 197 | #define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */ |
| emilmont | 77:869cf507173a | 198 | |
| emilmont | 77:869cf507173a | 199 | #define IS_OPTIONBYTE(VALUE)(((VALUE) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR))) |
| emilmont | 77:869cf507173a | 200 | |
| emilmont | 77:869cf507173a | 201 | /** |
| emilmont | 77:869cf507173a | 202 | * @} |
| emilmont | 77:869cf507173a | 203 | */ |
| emilmont | 77:869cf507173a | 204 | |
| emilmont | 77:869cf507173a | 205 | /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection |
| emilmont | 77:869cf507173a | 206 | * @{ |
| emilmont | 77:869cf507173a | 207 | */ |
| emilmont | 77:869cf507173a | 208 | #define OB_RDP_LEVEL_0 ((uint8_t)0xAA) |
| emilmont | 77:869cf507173a | 209 | #define OB_RDP_LEVEL_1 ((uint8_t)0x55) |
| emilmont | 77:869cf507173a | 210 | /*#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 |
| emilmont | 77:869cf507173a | 211 | it s no more possible to go back to level 1 or 0 */ |
| emilmont | 77:869cf507173a | 212 | #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ |
| emilmont | 77:869cf507173a | 213 | ((LEVEL) == OB_RDP_LEVEL_1))/*||\ |
| emilmont | 77:869cf507173a | 214 | ((LEVEL) == OB_RDP_LEVEL_2))*/ |
| emilmont | 77:869cf507173a | 215 | /** |
| emilmont | 77:869cf507173a | 216 | * @} |
| emilmont | 77:869cf507173a | 217 | */ |
| emilmont | 77:869cf507173a | 218 | |
| emilmont | 77:869cf507173a | 219 | /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog |
| emilmont | 77:869cf507173a | 220 | * @{ |
| emilmont | 77:869cf507173a | 221 | */ |
| emilmont | 77:869cf507173a | 222 | #define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ |
| emilmont | 77:869cf507173a | 223 | #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ |
| emilmont | 77:869cf507173a | 224 | #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) |
| emilmont | 77:869cf507173a | 225 | /** |
| emilmont | 77:869cf507173a | 226 | * @} |
| emilmont | 77:869cf507173a | 227 | */ |
| emilmont | 77:869cf507173a | 228 | |
| emilmont | 77:869cf507173a | 229 | /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP |
| emilmont | 77:869cf507173a | 230 | * @{ |
| emilmont | 77:869cf507173a | 231 | */ |
| emilmont | 77:869cf507173a | 232 | #define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ |
| emilmont | 77:869cf507173a | 233 | #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ |
| emilmont | 77:869cf507173a | 234 | #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) |
| emilmont | 77:869cf507173a | 235 | /** |
| emilmont | 77:869cf507173a | 236 | * @} |
| emilmont | 77:869cf507173a | 237 | */ |
| emilmont | 77:869cf507173a | 238 | |
| emilmont | 77:869cf507173a | 239 | |
| emilmont | 77:869cf507173a | 240 | /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY |
| emilmont | 77:869cf507173a | 241 | * @{ |
| emilmont | 77:869cf507173a | 242 | */ |
| emilmont | 77:869cf507173a | 243 | #define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ |
| emilmont | 77:869cf507173a | 244 | #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ |
| emilmont | 77:869cf507173a | 245 | #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) |
| emilmont | 77:869cf507173a | 246 | /** |
| emilmont | 77:869cf507173a | 247 | * @} |
| emilmont | 77:869cf507173a | 248 | */ |
| emilmont | 77:869cf507173a | 249 | |
| emilmont | 77:869cf507173a | 250 | /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level |
| emilmont | 77:869cf507173a | 251 | * @{ |
| emilmont | 77:869cf507173a | 252 | */ |
| emilmont | 77:869cf507173a | 253 | #define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ |
| emilmont | 77:869cf507173a | 254 | #define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ |
| emilmont | 77:869cf507173a | 255 | #define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ |
| emilmont | 77:869cf507173a | 256 | #define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ |
| emilmont | 77:869cf507173a | 257 | #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ |
| emilmont | 77:869cf507173a | 258 | ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) |
| emilmont | 77:869cf507173a | 259 | /** |
| emilmont | 77:869cf507173a | 260 | * @} |
| emilmont | 77:869cf507173a | 261 | */ |
| emilmont | 77:869cf507173a | 262 | |
| emilmont | 77:869cf507173a | 263 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 264 | /** @defgroup FLASHEx_PCROP_State FLASH PCROP State |
| emilmont | 77:869cf507173a | 265 | * @{ |
| emilmont | 77:869cf507173a | 266 | */ |
| emilmont | 77:869cf507173a | 267 | #define PCROPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable PCROP */ |
| emilmont | 77:869cf507173a | 268 | #define PCROPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable PCROP */ |
| emilmont | 77:869cf507173a | 269 | |
| emilmont | 77:869cf507173a | 270 | #define IS_PCROPSTATE(VALUE)(((VALUE) == PCROPSTATE_DISABLE) || \ |
| emilmont | 77:869cf507173a | 271 | ((VALUE) == PCROPSTATE_ENABLE)) |
| emilmont | 77:869cf507173a | 272 | |
| emilmont | 77:869cf507173a | 273 | /** |
| emilmont | 77:869cf507173a | 274 | * @} |
| emilmont | 77:869cf507173a | 275 | */ |
| emilmont | 77:869cf507173a | 276 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 277 | |
| emilmont | 77:869cf507173a | 278 | /** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type |
| emilmont | 77:869cf507173a | 279 | * @{ |
| emilmont | 77:869cf507173a | 280 | */ |
| emilmont | 77:869cf507173a | 281 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 282 | #define OBEX_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */ |
| emilmont | 77:869cf507173a | 283 | #define OBEX_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */ |
| emilmont | 77:869cf507173a | 284 | |
| emilmont | 77:869cf507173a | 285 | #define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP) || \ |
| emilmont | 77:869cf507173a | 286 | ((VALUE) == OBEX_BOOTCONFIG)) |
| emilmont | 77:869cf507173a | 287 | |
| emilmont | 77:869cf507173a | 288 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| emilmont | 77:869cf507173a | 289 | |
| emilmont | 77:869cf507173a | 290 | #if defined(STM32F401xC) || defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 291 | #define OBEX_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration */ |
| emilmont | 77:869cf507173a | 292 | |
| emilmont | 77:869cf507173a | 293 | #define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP)) |
| emilmont | 77:869cf507173a | 294 | |
| emilmont | 77:869cf507173a | 295 | #endif /* STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 296 | /** |
| emilmont | 77:869cf507173a | 297 | * @} |
| emilmont | 77:869cf507173a | 298 | */ |
| emilmont | 77:869cf507173a | 299 | |
| emilmont | 77:869cf507173a | 300 | /** @defgroup FLASH_Latency FLASH Latency |
| emilmont | 77:869cf507173a | 301 | * @{ |
| emilmont | 77:869cf507173a | 302 | */ |
| emilmont | 77:869cf507173a | 303 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 304 | #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ |
| emilmont | 77:869cf507173a | 305 | #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ |
| emilmont | 77:869cf507173a | 306 | #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ |
| emilmont | 77:869cf507173a | 307 | #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ |
| emilmont | 77:869cf507173a | 308 | #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ |
| emilmont | 77:869cf507173a | 309 | #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ |
| emilmont | 77:869cf507173a | 310 | #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ |
| emilmont | 77:869cf507173a | 311 | #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ |
| emilmont | 77:869cf507173a | 312 | #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */ |
| emilmont | 77:869cf507173a | 313 | #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */ |
| emilmont | 77:869cf507173a | 314 | #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ |
| emilmont | 77:869cf507173a | 315 | #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ |
| emilmont | 77:869cf507173a | 316 | #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ |
| emilmont | 77:869cf507173a | 317 | #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ |
| emilmont | 77:869cf507173a | 318 | #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ |
| emilmont | 77:869cf507173a | 319 | #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ |
| emilmont | 77:869cf507173a | 320 | |
| emilmont | 77:869cf507173a | 321 | |
| emilmont | 77:869cf507173a | 322 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ |
| emilmont | 77:869cf507173a | 323 | ((LATENCY) == FLASH_LATENCY_1) || \ |
| emilmont | 77:869cf507173a | 324 | ((LATENCY) == FLASH_LATENCY_2) || \ |
| emilmont | 77:869cf507173a | 325 | ((LATENCY) == FLASH_LATENCY_3) || \ |
| emilmont | 77:869cf507173a | 326 | ((LATENCY) == FLASH_LATENCY_4) || \ |
| emilmont | 77:869cf507173a | 327 | ((LATENCY) == FLASH_LATENCY_5) || \ |
| emilmont | 77:869cf507173a | 328 | ((LATENCY) == FLASH_LATENCY_6) || \ |
| emilmont | 77:869cf507173a | 329 | ((LATENCY) == FLASH_LATENCY_7) || \ |
| emilmont | 77:869cf507173a | 330 | ((LATENCY) == FLASH_LATENCY_8) || \ |
| emilmont | 77:869cf507173a | 331 | ((LATENCY) == FLASH_LATENCY_9) || \ |
| emilmont | 77:869cf507173a | 332 | ((LATENCY) == FLASH_LATENCY_10) || \ |
| emilmont | 77:869cf507173a | 333 | ((LATENCY) == FLASH_LATENCY_11) || \ |
| emilmont | 77:869cf507173a | 334 | ((LATENCY) == FLASH_LATENCY_12) || \ |
| emilmont | 77:869cf507173a | 335 | ((LATENCY) == FLASH_LATENCY_13) || \ |
| emilmont | 77:869cf507173a | 336 | ((LATENCY) == FLASH_LATENCY_14) || \ |
| emilmont | 77:869cf507173a | 337 | ((LATENCY) == FLASH_LATENCY_15)) |
| emilmont | 77:869cf507173a | 338 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 339 | |
| emilmont | 77:869cf507173a | 340 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 341 | #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ |
| emilmont | 77:869cf507173a | 342 | #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ |
| emilmont | 77:869cf507173a | 343 | #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ |
| emilmont | 77:869cf507173a | 344 | #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ |
| emilmont | 77:869cf507173a | 345 | #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ |
| emilmont | 77:869cf507173a | 346 | #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ |
| emilmont | 77:869cf507173a | 347 | #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ |
| emilmont | 77:869cf507173a | 348 | #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ |
| emilmont | 77:869cf507173a | 349 | |
| emilmont | 77:869cf507173a | 350 | |
| emilmont | 77:869cf507173a | 351 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ |
| emilmont | 77:869cf507173a | 352 | ((LATENCY) == FLASH_LATENCY_1) || \ |
| emilmont | 77:869cf507173a | 353 | ((LATENCY) == FLASH_LATENCY_2) || \ |
| emilmont | 77:869cf507173a | 354 | ((LATENCY) == FLASH_LATENCY_3) || \ |
| emilmont | 77:869cf507173a | 355 | ((LATENCY) == FLASH_LATENCY_4) || \ |
| emilmont | 77:869cf507173a | 356 | ((LATENCY) == FLASH_LATENCY_5) || \ |
| emilmont | 77:869cf507173a | 357 | ((LATENCY) == FLASH_LATENCY_6) || \ |
| emilmont | 77:869cf507173a | 358 | ((LATENCY) == FLASH_LATENCY_7)) |
| emilmont | 77:869cf507173a | 359 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 360 | |
| emilmont | 77:869cf507173a | 361 | /** |
| emilmont | 77:869cf507173a | 362 | * @} |
| emilmont | 77:869cf507173a | 363 | */ |
| emilmont | 77:869cf507173a | 364 | |
| emilmont | 77:869cf507173a | 365 | |
| emilmont | 77:869cf507173a | 366 | /** @defgroup FLASHEx_Banks FLASH Banks |
| emilmont | 77:869cf507173a | 367 | * @{ |
| emilmont | 77:869cf507173a | 368 | */ |
| emilmont | 77:869cf507173a | 369 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 370 | #define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */ |
| emilmont | 77:869cf507173a | 371 | #define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */ |
| emilmont | 77:869cf507173a | 372 | #define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ |
| emilmont | 77:869cf507173a | 373 | |
| emilmont | 77:869cf507173a | 374 | #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ |
| emilmont | 77:869cf507173a | 375 | ((BANK) == FLASH_BANK_2) || \ |
| emilmont | 77:869cf507173a | 376 | ((BANK) == FLASH_BANK_BOTH)) |
| emilmont | 77:869cf507173a | 377 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 378 | |
| emilmont | 77:869cf507173a | 379 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 380 | #define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */ |
| emilmont | 77:869cf507173a | 381 | |
| emilmont | 77:869cf507173a | 382 | #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) |
| emilmont | 77:869cf507173a | 383 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 384 | /** |
| emilmont | 77:869cf507173a | 385 | * @} |
| emilmont | 77:869cf507173a | 386 | */ |
| emilmont | 77:869cf507173a | 387 | |
| emilmont | 77:869cf507173a | 388 | /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit |
| emilmont | 77:869cf507173a | 389 | * @{ |
| emilmont | 77:869cf507173a | 390 | */ |
| emilmont | 77:869cf507173a | 391 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 392 | #define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */ |
| emilmont | 77:869cf507173a | 393 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 394 | |
| emilmont | 77:869cf507173a | 395 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 396 | #define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */ |
| emilmont | 77:869cf507173a | 397 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 398 | /** |
| emilmont | 77:869cf507173a | 399 | * @} |
| emilmont | 77:869cf507173a | 400 | */ |
| emilmont | 77:869cf507173a | 401 | |
| emilmont | 77:869cf507173a | 402 | /** @defgroup FLASHEx_Sectors FLASH Sectors |
| emilmont | 77:869cf507173a | 403 | * @{ |
| emilmont | 77:869cf507173a | 404 | */ |
| emilmont | 77:869cf507173a | 405 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 406 | #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ |
| emilmont | 77:869cf507173a | 407 | #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ |
| emilmont | 77:869cf507173a | 408 | #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ |
| emilmont | 77:869cf507173a | 409 | #define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ |
| emilmont | 77:869cf507173a | 410 | #define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ |
| emilmont | 77:869cf507173a | 411 | #define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ |
| emilmont | 77:869cf507173a | 412 | #define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */ |
| emilmont | 77:869cf507173a | 413 | #define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */ |
| emilmont | 77:869cf507173a | 414 | #define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */ |
| emilmont | 77:869cf507173a | 415 | #define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */ |
| emilmont | 77:869cf507173a | 416 | #define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */ |
| emilmont | 77:869cf507173a | 417 | #define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */ |
| emilmont | 77:869cf507173a | 418 | #define FLASH_SECTOR_12 ((uint32_t)12) /*!< Sector Number 12 */ |
| emilmont | 77:869cf507173a | 419 | #define FLASH_SECTOR_13 ((uint32_t)13) /*!< Sector Number 13 */ |
| emilmont | 77:869cf507173a | 420 | #define FLASH_SECTOR_14 ((uint32_t)14) /*!< Sector Number 14 */ |
| emilmont | 77:869cf507173a | 421 | #define FLASH_SECTOR_15 ((uint32_t)15) /*!< Sector Number 15 */ |
| emilmont | 77:869cf507173a | 422 | #define FLASH_SECTOR_16 ((uint32_t)16) /*!< Sector Number 16 */ |
| emilmont | 77:869cf507173a | 423 | #define FLASH_SECTOR_17 ((uint32_t)17) /*!< Sector Number 17 */ |
| emilmont | 77:869cf507173a | 424 | #define FLASH_SECTOR_18 ((uint32_t)18) /*!< Sector Number 18 */ |
| emilmont | 77:869cf507173a | 425 | #define FLASH_SECTOR_19 ((uint32_t)19) /*!< Sector Number 19 */ |
| emilmont | 77:869cf507173a | 426 | #define FLASH_SECTOR_20 ((uint32_t)20) /*!< Sector Number 20 */ |
| emilmont | 77:869cf507173a | 427 | #define FLASH_SECTOR_21 ((uint32_t)21) /*!< Sector Number 21 */ |
| emilmont | 77:869cf507173a | 428 | #define FLASH_SECTOR_22 ((uint32_t)22) /*!< Sector Number 22 */ |
| emilmont | 77:869cf507173a | 429 | #define FLASH_SECTOR_23 ((uint32_t)23) /*!< Sector Number 23 */ |
| emilmont | 77:869cf507173a | 430 | |
| emilmont | 77:869cf507173a | 431 | #define FLASH_SECTOR_TOTAL 24 |
| emilmont | 77:869cf507173a | 432 | |
| emilmont | 77:869cf507173a | 433 | #define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| emilmont | 77:869cf507173a | 434 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| emilmont | 77:869cf507173a | 435 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| emilmont | 77:869cf507173a | 436 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ |
| emilmont | 77:869cf507173a | 437 | ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ |
| emilmont | 77:869cf507173a | 438 | ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ |
| emilmont | 77:869cf507173a | 439 | ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ |
| emilmont | 77:869cf507173a | 440 | ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ |
| emilmont | 77:869cf507173a | 441 | ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ |
| emilmont | 77:869cf507173a | 442 | ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ |
| emilmont | 77:869cf507173a | 443 | ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ |
| emilmont | 77:869cf507173a | 444 | ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) |
| emilmont | 77:869cf507173a | 445 | |
| emilmont | 77:869cf507173a | 446 | #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\ |
| emilmont | 77:869cf507173a | 447 | (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) |
| emilmont | 77:869cf507173a | 448 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 449 | |
| emilmont | 77:869cf507173a | 450 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| emilmont | 77:869cf507173a | 451 | #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ |
| emilmont | 77:869cf507173a | 452 | #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ |
| emilmont | 77:869cf507173a | 453 | #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ |
| emilmont | 77:869cf507173a | 454 | #define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ |
| emilmont | 77:869cf507173a | 455 | #define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ |
| emilmont | 77:869cf507173a | 456 | #define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ |
| emilmont | 77:869cf507173a | 457 | #define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */ |
| emilmont | 77:869cf507173a | 458 | #define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */ |
| emilmont | 77:869cf507173a | 459 | #define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */ |
| emilmont | 77:869cf507173a | 460 | #define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */ |
| emilmont | 77:869cf507173a | 461 | #define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */ |
| emilmont | 77:869cf507173a | 462 | #define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */ |
| emilmont | 77:869cf507173a | 463 | |
| emilmont | 77:869cf507173a | 464 | #define FLASH_SECTOR_TOTAL 12 |
| emilmont | 77:869cf507173a | 465 | |
| emilmont | 77:869cf507173a | 466 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| emilmont | 77:869cf507173a | 467 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| emilmont | 77:869cf507173a | 468 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| emilmont | 77:869cf507173a | 469 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ |
| emilmont | 77:869cf507173a | 470 | ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ |
| emilmont | 77:869cf507173a | 471 | ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11)) |
| emilmont | 77:869cf507173a | 472 | |
| emilmont | 77:869cf507173a | 473 | #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ |
| emilmont | 77:869cf507173a | 474 | (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) |
| emilmont | 77:869cf507173a | 475 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 476 | |
| emilmont | 77:869cf507173a | 477 | #if defined(STM32F401xC) |
| emilmont | 77:869cf507173a | 478 | #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ |
| emilmont | 77:869cf507173a | 479 | #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ |
| emilmont | 77:869cf507173a | 480 | #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ |
| emilmont | 77:869cf507173a | 481 | #define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ |
| emilmont | 77:869cf507173a | 482 | #define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ |
| emilmont | 77:869cf507173a | 483 | #define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ |
| emilmont | 77:869cf507173a | 484 | |
| emilmont | 77:869cf507173a | 485 | #define FLASH_SECTOR_TOTAL 6 |
| emilmont | 77:869cf507173a | 486 | |
| emilmont | 77:869cf507173a | 487 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| emilmont | 77:869cf507173a | 488 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| emilmont | 77:869cf507173a | 489 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5)) |
| emilmont | 77:869cf507173a | 490 | |
| emilmont | 77:869cf507173a | 491 | #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\ |
| emilmont | 77:869cf507173a | 492 | (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) |
| emilmont | 77:869cf507173a | 493 | #endif /* STM32F401xC */ |
| emilmont | 77:869cf507173a | 494 | |
| emilmont | 77:869cf507173a | 495 | #if defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 496 | #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ |
| emilmont | 77:869cf507173a | 497 | #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ |
| emilmont | 77:869cf507173a | 498 | #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ |
| emilmont | 77:869cf507173a | 499 | #define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ |
| emilmont | 77:869cf507173a | 500 | #define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ |
| emilmont | 77:869cf507173a | 501 | #define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ |
| emilmont | 77:869cf507173a | 502 | #define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */ |
| emilmont | 77:869cf507173a | 503 | #define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */ |
| emilmont | 77:869cf507173a | 504 | |
| emilmont | 77:869cf507173a | 505 | #define FLASH_SECTOR_TOTAL 8 |
| emilmont | 77:869cf507173a | 506 | |
| emilmont | 77:869cf507173a | 507 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| emilmont | 77:869cf507173a | 508 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| emilmont | 77:869cf507173a | 509 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| emilmont | 77:869cf507173a | 510 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) |
| emilmont | 77:869cf507173a | 511 | |
| emilmont | 77:869cf507173a | 512 | #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) ||\ |
| emilmont | 77:869cf507173a | 513 | (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) |
| emilmont | 77:869cf507173a | 514 | #endif /* STM32F401xE */ |
| emilmont | 77:869cf507173a | 515 | |
| emilmont | 77:869cf507173a | 516 | #define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) |
| emilmont | 77:869cf507173a | 517 | |
| emilmont | 77:869cf507173a | 518 | /** |
| emilmont | 77:869cf507173a | 519 | * @} |
| emilmont | 77:869cf507173a | 520 | */ |
| emilmont | 77:869cf507173a | 521 | |
| emilmont | 77:869cf507173a | 522 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection |
| emilmont | 77:869cf507173a | 523 | * @{ |
| emilmont | 77:869cf507173a | 524 | */ |
| emilmont | 77:869cf507173a | 525 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 526 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ |
| emilmont | 77:869cf507173a | 527 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ |
| emilmont | 77:869cf507173a | 528 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ |
| emilmont | 77:869cf507173a | 529 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ |
| emilmont | 77:869cf507173a | 530 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ |
| emilmont | 77:869cf507173a | 531 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ |
| emilmont | 77:869cf507173a | 532 | #define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ |
| emilmont | 77:869cf507173a | 533 | #define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ |
| emilmont | 77:869cf507173a | 534 | #define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ |
| emilmont | 77:869cf507173a | 535 | #define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ |
| emilmont | 77:869cf507173a | 536 | #define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ |
| emilmont | 77:869cf507173a | 537 | #define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ |
| emilmont | 77:869cf507173a | 538 | #define OB_WRP_SECTOR_12 ((uint32_t)0x00000001 << 12) /*!< Write protection of Sector12 */ |
| emilmont | 77:869cf507173a | 539 | #define OB_WRP_SECTOR_13 ((uint32_t)0x00000002 << 12) /*!< Write protection of Sector13 */ |
| emilmont | 77:869cf507173a | 540 | #define OB_WRP_SECTOR_14 ((uint32_t)0x00000004 << 12) /*!< Write protection of Sector14 */ |
| emilmont | 77:869cf507173a | 541 | #define OB_WRP_SECTOR_15 ((uint32_t)0x00000008 << 12) /*!< Write protection of Sector15 */ |
| emilmont | 77:869cf507173a | 542 | #define OB_WRP_SECTOR_16 ((uint32_t)0x00000010 << 12) /*!< Write protection of Sector16 */ |
| emilmont | 77:869cf507173a | 543 | #define OB_WRP_SECTOR_17 ((uint32_t)0x00000020 << 12) /*!< Write protection of Sector17 */ |
| emilmont | 77:869cf507173a | 544 | #define OB_WRP_SECTOR_18 ((uint32_t)0x00000040 << 12) /*!< Write protection of Sector18 */ |
| emilmont | 77:869cf507173a | 545 | #define OB_WRP_SECTOR_19 ((uint32_t)0x00000080 << 12) /*!< Write protection of Sector19 */ |
| emilmont | 77:869cf507173a | 546 | #define OB_WRP_SECTOR_20 ((uint32_t)0x00000100 << 12) /*!< Write protection of Sector20 */ |
| emilmont | 77:869cf507173a | 547 | #define OB_WRP_SECTOR_21 ((uint32_t)0x00000200 << 12) /*!< Write protection of Sector21 */ |
| emilmont | 77:869cf507173a | 548 | #define OB_WRP_SECTOR_22 ((uint32_t)0x00000400 << 12) /*!< Write protection of Sector22 */ |
| emilmont | 77:869cf507173a | 549 | #define OB_WRP_SECTOR_23 ((uint32_t)0x00000800 << 12) /*!< Write protection of Sector23 */ |
| emilmont | 77:869cf507173a | 550 | #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF << 12) /*!< Write protection of all Sectors */ |
| emilmont | 77:869cf507173a | 551 | |
| emilmont | 77:869cf507173a | 552 | #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| emilmont | 77:869cf507173a | 553 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 554 | |
| emilmont | 77:869cf507173a | 555 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| emilmont | 77:869cf507173a | 556 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ |
| emilmont | 77:869cf507173a | 557 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ |
| emilmont | 77:869cf507173a | 558 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ |
| emilmont | 77:869cf507173a | 559 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ |
| emilmont | 77:869cf507173a | 560 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ |
| emilmont | 77:869cf507173a | 561 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ |
| emilmont | 77:869cf507173a | 562 | #define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ |
| emilmont | 77:869cf507173a | 563 | #define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ |
| emilmont | 77:869cf507173a | 564 | #define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ |
| emilmont | 77:869cf507173a | 565 | #define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ |
| emilmont | 77:869cf507173a | 566 | #define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ |
| emilmont | 77:869cf507173a | 567 | #define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ |
| emilmont | 77:869cf507173a | 568 | #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ |
| emilmont | 77:869cf507173a | 569 | |
| emilmont | 77:869cf507173a | 570 | #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| emilmont | 77:869cf507173a | 571 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 572 | |
| emilmont | 77:869cf507173a | 573 | #if defined(STM32F401xC) |
| emilmont | 77:869cf507173a | 574 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ |
| emilmont | 77:869cf507173a | 575 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ |
| emilmont | 77:869cf507173a | 576 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ |
| emilmont | 77:869cf507173a | 577 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ |
| emilmont | 77:869cf507173a | 578 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ |
| emilmont | 77:869cf507173a | 579 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ |
| emilmont | 77:869cf507173a | 580 | #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ |
| emilmont | 77:869cf507173a | 581 | |
| emilmont | 77:869cf507173a | 582 | #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| emilmont | 77:869cf507173a | 583 | #endif /* STM32F401xC */ |
| emilmont | 77:869cf507173a | 584 | |
| emilmont | 77:869cf507173a | 585 | #if defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 586 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ |
| emilmont | 77:869cf507173a | 587 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ |
| emilmont | 77:869cf507173a | 588 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ |
| emilmont | 77:869cf507173a | 589 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ |
| emilmont | 77:869cf507173a | 590 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ |
| emilmont | 77:869cf507173a | 591 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ |
| emilmont | 77:869cf507173a | 592 | #define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ |
| emilmont | 77:869cf507173a | 593 | #define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ |
| emilmont | 77:869cf507173a | 594 | #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ |
| emilmont | 77:869cf507173a | 595 | |
| emilmont | 77:869cf507173a | 596 | #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| emilmont | 77:869cf507173a | 597 | #endif /* STM32F401xE */ |
| emilmont | 77:869cf507173a | 598 | /** |
| emilmont | 77:869cf507173a | 599 | * @} |
| emilmont | 77:869cf507173a | 600 | */ |
| emilmont | 77:869cf507173a | 601 | |
| emilmont | 77:869cf507173a | 602 | /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection |
| emilmont | 77:869cf507173a | 603 | * @{ |
| emilmont | 77:869cf507173a | 604 | */ |
| emilmont | 77:869cf507173a | 605 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 606 | #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ |
| emilmont | 77:869cf507173a | 607 | #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ |
| emilmont | 77:869cf507173a | 608 | #define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ |
| emilmont | 77:869cf507173a | 609 | #define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ |
| emilmont | 77:869cf507173a | 610 | #define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ |
| emilmont | 77:869cf507173a | 611 | #define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ |
| emilmont | 77:869cf507173a | 612 | #define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ |
| emilmont | 77:869cf507173a | 613 | #define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ |
| emilmont | 77:869cf507173a | 614 | #define OB_PCROP_SECTOR_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ |
| emilmont | 77:869cf507173a | 615 | #define OB_PCROP_SECTOR_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ |
| emilmont | 77:869cf507173a | 616 | #define OB_PCROP_SECTOR_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ |
| emilmont | 77:869cf507173a | 617 | #define OB_PCROP_SECTOR_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ |
| emilmont | 77:869cf507173a | 618 | #define OB_PCROP_SECTOR_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ |
| emilmont | 77:869cf507173a | 619 | #define OB_PCROP_SECTOR_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ |
| emilmont | 77:869cf507173a | 620 | #define OB_PCROP_SECTOR_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ |
| emilmont | 77:869cf507173a | 621 | #define OB_PCROP_SECTOR_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ |
| emilmont | 77:869cf507173a | 622 | #define OB_PCROP_SECTOR_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ |
| emilmont | 77:869cf507173a | 623 | #define OB_PCROP_SECTOR_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ |
| emilmont | 77:869cf507173a | 624 | #define OB_PCROP_SECTOR_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ |
| emilmont | 77:869cf507173a | 625 | #define OB_PCROP_SECTOR_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ |
| emilmont | 77:869cf507173a | 626 | #define OB_PCROP_SECTOR_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ |
| emilmont | 77:869cf507173a | 627 | #define OB_PCROP_SECTOR_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ |
| emilmont | 77:869cf507173a | 628 | #define OB_PCROP_SECTOR_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ |
| emilmont | 77:869cf507173a | 629 | #define OB_PCROP_SECTOR_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ |
| emilmont | 77:869cf507173a | 630 | #define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ |
| emilmont | 77:869cf507173a | 631 | |
| emilmont | 77:869cf507173a | 632 | #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| emilmont | 77:869cf507173a | 633 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 634 | |
| emilmont | 77:869cf507173a | 635 | #if defined(STM32F401xC) |
| emilmont | 77:869cf507173a | 636 | #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ |
| emilmont | 77:869cf507173a | 637 | #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ |
| emilmont | 77:869cf507173a | 638 | #define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ |
| emilmont | 77:869cf507173a | 639 | #define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ |
| emilmont | 77:869cf507173a | 640 | #define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ |
| emilmont | 77:869cf507173a | 641 | #define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ |
| emilmont | 77:869cf507173a | 642 | #define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ |
| emilmont | 77:869cf507173a | 643 | |
| emilmont | 77:869cf507173a | 644 | #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| emilmont | 77:869cf507173a | 645 | #endif /* STM32F401xC */ |
| emilmont | 77:869cf507173a | 646 | |
| emilmont | 77:869cf507173a | 647 | #if defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 648 | #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ |
| emilmont | 77:869cf507173a | 649 | #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ |
| emilmont | 77:869cf507173a | 650 | #define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ |
| emilmont | 77:869cf507173a | 651 | #define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ |
| emilmont | 77:869cf507173a | 652 | #define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ |
| emilmont | 77:869cf507173a | 653 | #define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ |
| emilmont | 77:869cf507173a | 654 | #define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ |
| emilmont | 77:869cf507173a | 655 | #define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ |
| emilmont | 77:869cf507173a | 656 | #define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ |
| emilmont | 77:869cf507173a | 657 | |
| emilmont | 77:869cf507173a | 658 | #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| emilmont | 77:869cf507173a | 659 | #endif /* STM32F401xE */ |
| emilmont | 77:869cf507173a | 660 | |
| emilmont | 77:869cf507173a | 661 | /** |
| emilmont | 77:869cf507173a | 662 | * @} |
| emilmont | 77:869cf507173a | 663 | */ |
| emilmont | 77:869cf507173a | 664 | |
| emilmont | 77:869cf507173a | 665 | /** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot |
| emilmont | 77:869cf507173a | 666 | * @{ |
| emilmont | 77:869cf507173a | 667 | */ |
| emilmont | 77:869cf507173a | 668 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 669 | #define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ |
| emilmont | 77:869cf507173a | 670 | #define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ |
| emilmont | 77:869cf507173a | 671 | #define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) |
| emilmont | 77:869cf507173a | 672 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 673 | /** |
| emilmont | 77:869cf507173a | 674 | * @} |
| emilmont | 77:869cf507173a | 675 | */ |
| emilmont | 77:869cf507173a | 676 | |
| emilmont | 77:869cf507173a | 677 | /** @defgroup FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode |
| emilmont | 77:869cf507173a | 678 | * @{ |
| emilmont | 77:869cf507173a | 679 | */ |
| emilmont | 77:869cf507173a | 680 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 681 | #define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ |
| emilmont | 77:869cf507173a | 682 | #define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ |
| emilmont | 77:869cf507173a | 683 | #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) |
| emilmont | 77:869cf507173a | 684 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 685 | /** |
| emilmont | 77:869cf507173a | 686 | * @} |
| emilmont | 77:869cf507173a | 687 | */ |
| emilmont | 77:869cf507173a | 688 | |
| emilmont | 77:869cf507173a | 689 | /** |
| emilmont | 77:869cf507173a | 690 | * @brief OPTCR1 register byte 2 (Bits[23:16]) base address |
| emilmont | 77:869cf507173a | 691 | */ |
| emilmont | 77:869cf507173a | 692 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 693 | #define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) |
| emilmont | 77:869cf507173a | 694 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 695 | |
| emilmont | 77:869cf507173a | 696 | /** |
| emilmont | 77:869cf507173a | 697 | * @} |
| emilmont | 77:869cf507173a | 698 | */ |
| emilmont | 77:869cf507173a | 699 | |
| emilmont | 77:869cf507173a | 700 | /* Exported macro ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 701 | |
| emilmont | 77:869cf507173a | 702 | /* Exported functions --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 703 | |
| emilmont | 77:869cf507173a | 704 | /* Extension Program operation functions *************************************/ |
| emilmont | 77:869cf507173a | 705 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); |
| emilmont | 77:869cf507173a | 706 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
| emilmont | 77:869cf507173a | 707 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
| emilmont | 77:869cf507173a | 708 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
| emilmont | 77:869cf507173a | 709 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) |
| emilmont | 77:869cf507173a | 710 | HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); |
| emilmont | 77:869cf507173a | 711 | void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); |
| emilmont | 77:869cf507173a | 712 | HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); |
| emilmont | 77:869cf507173a | 713 | HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); |
| emilmont | 77:869cf507173a | 714 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ |
| emilmont | 77:869cf507173a | 715 | |
| emilmont | 77:869cf507173a | 716 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| emilmont | 77:869cf507173a | 717 | uint16_t HAL_FLASHEx_OB_GetBank2WRP(void); |
| emilmont | 77:869cf507173a | 718 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| emilmont | 77:869cf507173a | 719 | |
| emilmont | 77:869cf507173a | 720 | void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); |
| emilmont | 77:869cf507173a | 721 | |
| emilmont | 77:869cf507173a | 722 | /** |
| emilmont | 77:869cf507173a | 723 | * @} |
| emilmont | 77:869cf507173a | 724 | */ |
| emilmont | 77:869cf507173a | 725 | |
| emilmont | 77:869cf507173a | 726 | /** |
| emilmont | 77:869cf507173a | 727 | * @} |
| emilmont | 77:869cf507173a | 728 | */ |
| emilmont | 77:869cf507173a | 729 | |
| emilmont | 77:869cf507173a | 730 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 731 | } |
| emilmont | 77:869cf507173a | 732 | #endif |
| emilmont | 77:869cf507173a | 733 | |
| emilmont | 77:869cf507173a | 734 | #endif /* __STM32F4xx_HAL_FLASH_EX_H */ |
| emilmont | 77:869cf507173a | 735 | |
| emilmont | 77:869cf507173a | 736 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |