frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_K64F/MK64F12.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Child:
90:cb3d968589d8
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 ** ###################################################################
bogdanm 82:6473597d706e 3 ** Processor: MK64FN1M0VMD12
bogdanm 82:6473597d706e 4 ** Compilers: ARM Compiler
bogdanm 82:6473597d706e 5 ** Freescale C/C++ for Embedded ARM
bogdanm 82:6473597d706e 6 ** GNU C Compiler
bogdanm 82:6473597d706e 7 ** GNU C Compiler - CodeSourcery Sourcery G++
bogdanm 82:6473597d706e 8 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 82:6473597d706e 9 **
bogdanm 82:6473597d706e 10 ** Reference manual: K64P144M120SF5RM, Rev.1, July 2013
bogdanm 82:6473597d706e 11 ** Version: rev. 2.1, 2013-10-29
bogdanm 82:6473597d706e 12 **
bogdanm 82:6473597d706e 13 ** Abstract:
bogdanm 82:6473597d706e 14 ** CMSIS Peripheral Access Layer for MK64F12
bogdanm 82:6473597d706e 15 **
bogdanm 82:6473597d706e 16 ** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
bogdanm 82:6473597d706e 17 **
bogdanm 82:6473597d706e 18 ** http: www.freescale.com
bogdanm 82:6473597d706e 19 ** mail: support@freescale.com
bogdanm 82:6473597d706e 20 **
bogdanm 82:6473597d706e 21 ** Revisions:
bogdanm 82:6473597d706e 22 ** - rev. 1.0 (2013-08-12)
bogdanm 82:6473597d706e 23 ** Initial version.
bogdanm 82:6473597d706e 24 ** - rev. 2.0 (2013-10-29)
bogdanm 82:6473597d706e 25 ** Register accessor macros added to the memory map.
bogdanm 82:6473597d706e 26 ** Symbols for Processor Expert memory map compatibility added to the memory map.
bogdanm 82:6473597d706e 27 ** Startup file for gcc has been updated according to CMSIS 3.2.
bogdanm 82:6473597d706e 28 ** System initialization updated.
bogdanm 82:6473597d706e 29 ** MCG - registers updated.
bogdanm 82:6473597d706e 30 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
bogdanm 82:6473597d706e 31 ** - rev. 2.1 (2013-10-29)
bogdanm 82:6473597d706e 32 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
bogdanm 82:6473597d706e 33 **
bogdanm 82:6473597d706e 34 ** ###################################################################
bogdanm 82:6473597d706e 35 */
bogdanm 82:6473597d706e 36
bogdanm 82:6473597d706e 37 /*!
bogdanm 82:6473597d706e 38 * @file MK64F12.h
bogdanm 82:6473597d706e 39 * @version 2.1
bogdanm 82:6473597d706e 40 * @date 2013-10-29
bogdanm 82:6473597d706e 41 * @brief CMSIS Peripheral Access Layer for MK64F12
bogdanm 82:6473597d706e 42 *
bogdanm 82:6473597d706e 43 * CMSIS Peripheral Access Layer for MK64F12
bogdanm 82:6473597d706e 44 */
bogdanm 82:6473597d706e 45
bogdanm 82:6473597d706e 46 #if !defined(MK64F12_H_)
bogdanm 82:6473597d706e 47 #define MK64F12_H_ /**< Symbol preventing repeated inclusion */
bogdanm 82:6473597d706e 48
bogdanm 82:6473597d706e 49
bogdanm 82:6473597d706e 50
bogdanm 82:6473597d706e 51 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 52 -- MCU activation
bogdanm 82:6473597d706e 53 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 54
bogdanm 82:6473597d706e 55 /* Prevention from multiple including the same memory map */
bogdanm 82:6473597d706e 56 #if !defined(MCU_MK64F12) /* Check if memory map has not been already included */
bogdanm 82:6473597d706e 57 #define MCU_MK64F12
bogdanm 82:6473597d706e 58
bogdanm 82:6473597d706e 59 /* Check if another memory map has not been also included */
bogdanm 82:6473597d706e 60 #if (defined(MCU_ACTIVE))
bogdanm 82:6473597d706e 61 #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
bogdanm 82:6473597d706e 62 #endif /* (defined(MCU_ACTIVE)) */
bogdanm 82:6473597d706e 63 #define MCU_ACTIVE
bogdanm 82:6473597d706e 64
bogdanm 82:6473597d706e 65 #include <stdint.h>
bogdanm 82:6473597d706e 66
bogdanm 82:6473597d706e 67 /** Memory map major version (memory maps with equal major version number are
bogdanm 82:6473597d706e 68 * compatible) */
bogdanm 82:6473597d706e 69 #define MCU_MEM_MAP_VERSION 0x0200u
bogdanm 82:6473597d706e 70 /** Memory map minor version */
bogdanm 82:6473597d706e 71 #define MCU_MEM_MAP_VERSION_MINOR 0x0001u
bogdanm 82:6473597d706e 72
bogdanm 82:6473597d706e 73 /**
bogdanm 82:6473597d706e 74 * @brief Macro to calculate address of an aliased word in the peripheral
bogdanm 82:6473597d706e 75 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
bogdanm 82:6473597d706e 76 * 0x400FFFFF).
bogdanm 82:6473597d706e 77 * @param Reg Register to access.
bogdanm 82:6473597d706e 78 * @param Bit Bit number to access.
bogdanm 82:6473597d706e 79 * @return Address of the aliased word in the peripheral bitband area.
bogdanm 82:6473597d706e 80 */
bogdanm 82:6473597d706e 81 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
bogdanm 82:6473597d706e 82 /**
bogdanm 82:6473597d706e 83 * @brief Macro to access a single bit of a peripheral register (bit band region
bogdanm 82:6473597d706e 84 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
bogdanm 82:6473597d706e 85 * be used for peripherals with 32bit access allowed.
bogdanm 82:6473597d706e 86 * @param Reg Register to access.
bogdanm 82:6473597d706e 87 * @param Bit Bit number to access.
bogdanm 82:6473597d706e 88 * @return Value of the targeted bit in the bit band region.
bogdanm 82:6473597d706e 89 */
bogdanm 82:6473597d706e 90 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
bogdanm 82:6473597d706e 91 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
bogdanm 82:6473597d706e 92 /**
bogdanm 82:6473597d706e 93 * @brief Macro to access a single bit of a peripheral register (bit band region
bogdanm 82:6473597d706e 94 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
bogdanm 82:6473597d706e 95 * be used for peripherals with 16bit access allowed.
bogdanm 82:6473597d706e 96 * @param Reg Register to access.
bogdanm 82:6473597d706e 97 * @param Bit Bit number to access.
bogdanm 82:6473597d706e 98 * @return Value of the targeted bit in the bit band region.
bogdanm 82:6473597d706e 99 */
bogdanm 82:6473597d706e 100 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
bogdanm 82:6473597d706e 101 /**
bogdanm 82:6473597d706e 102 * @brief Macro to access a single bit of a peripheral register (bit band region
bogdanm 82:6473597d706e 103 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
bogdanm 82:6473597d706e 104 * be used for peripherals with 8bit access allowed.
bogdanm 82:6473597d706e 105 * @param Reg Register to access.
bogdanm 82:6473597d706e 106 * @param Bit Bit number to access.
bogdanm 82:6473597d706e 107 * @return Value of the targeted bit in the bit band region.
bogdanm 82:6473597d706e 108 */
bogdanm 82:6473597d706e 109 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
bogdanm 82:6473597d706e 110
bogdanm 82:6473597d706e 111 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 112 -- Interrupt vector numbers
bogdanm 82:6473597d706e 113 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 114
bogdanm 82:6473597d706e 115 /*!
bogdanm 82:6473597d706e 116 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
bogdanm 82:6473597d706e 117 * @{
bogdanm 82:6473597d706e 118 */
bogdanm 82:6473597d706e 119
bogdanm 82:6473597d706e 120 /** Interrupt Number Definitions */
bogdanm 82:6473597d706e 121 typedef enum IRQn {
bogdanm 82:6473597d706e 122 /* Core interrupts */
bogdanm 82:6473597d706e 123 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
bogdanm 82:6473597d706e 124 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
bogdanm 82:6473597d706e 125 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
bogdanm 82:6473597d706e 126 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
bogdanm 82:6473597d706e 127 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
bogdanm 82:6473597d706e 128 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
bogdanm 82:6473597d706e 129 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
bogdanm 82:6473597d706e 130 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
bogdanm 82:6473597d706e 131 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
bogdanm 82:6473597d706e 132
bogdanm 82:6473597d706e 133 /* Device specific interrupts */
bogdanm 82:6473597d706e 134 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
bogdanm 82:6473597d706e 135 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
bogdanm 82:6473597d706e 136 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
bogdanm 82:6473597d706e 137 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
bogdanm 82:6473597d706e 138 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
bogdanm 82:6473597d706e 139 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
bogdanm 82:6473597d706e 140 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
bogdanm 82:6473597d706e 141 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
bogdanm 82:6473597d706e 142 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
bogdanm 82:6473597d706e 143 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
bogdanm 82:6473597d706e 144 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
bogdanm 82:6473597d706e 145 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
bogdanm 82:6473597d706e 146 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
bogdanm 82:6473597d706e 147 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
bogdanm 82:6473597d706e 148 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
bogdanm 82:6473597d706e 149 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
bogdanm 82:6473597d706e 150 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
bogdanm 82:6473597d706e 151 MCM_IRQn = 17, /**< Normal Interrupt */
bogdanm 82:6473597d706e 152 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
bogdanm 82:6473597d706e 153 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
bogdanm 82:6473597d706e 154 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
bogdanm 82:6473597d706e 155 LLW_IRQn = 21, /**< Low Leakage Wakeup */
bogdanm 82:6473597d706e 156 Watchdog_IRQn = 22, /**< WDOG Interrupt */
bogdanm 82:6473597d706e 157 RNG_IRQn = 23, /**< RNG Interrupt */
bogdanm 82:6473597d706e 158 I2C0_IRQn = 24, /**< I2C0 interrupt */
bogdanm 82:6473597d706e 159 I2C1_IRQn = 25, /**< I2C1 interrupt */
bogdanm 82:6473597d706e 160 SPI0_IRQn = 26, /**< SPI0 Interrupt */
bogdanm 82:6473597d706e 161 SPI1_IRQn = 27, /**< SPI1 Interrupt */
bogdanm 82:6473597d706e 162 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
bogdanm 82:6473597d706e 163 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
bogdanm 82:6473597d706e 164 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
bogdanm 82:6473597d706e 165 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
bogdanm 82:6473597d706e 166 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
bogdanm 82:6473597d706e 167 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
bogdanm 82:6473597d706e 168 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
bogdanm 82:6473597d706e 169 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
bogdanm 82:6473597d706e 170 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
bogdanm 82:6473597d706e 171 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
bogdanm 82:6473597d706e 172 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
bogdanm 82:6473597d706e 173 ADC0_IRQn = 39, /**< ADC0 interrupt */
bogdanm 82:6473597d706e 174 CMP0_IRQn = 40, /**< CMP0 interrupt */
bogdanm 82:6473597d706e 175 CMP1_IRQn = 41, /**< CMP1 interrupt */
bogdanm 82:6473597d706e 176 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
bogdanm 82:6473597d706e 177 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
bogdanm 82:6473597d706e 178 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
bogdanm 82:6473597d706e 179 CMT_IRQn = 45, /**< CMT interrupt */
bogdanm 82:6473597d706e 180 RTC_IRQn = 46, /**< RTC interrupt */
bogdanm 82:6473597d706e 181 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
bogdanm 82:6473597d706e 182 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
bogdanm 82:6473597d706e 183 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
bogdanm 82:6473597d706e 184 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
bogdanm 82:6473597d706e 185 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
bogdanm 82:6473597d706e 186 PDB0_IRQn = 52, /**< PDB0 Interrupt */
bogdanm 82:6473597d706e 187 USB0_IRQn = 53, /**< USB0 interrupt */
bogdanm 82:6473597d706e 188 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
bogdanm 82:6473597d706e 189 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
bogdanm 82:6473597d706e 190 DAC0_IRQn = 56, /**< DAC0 interrupt */
bogdanm 82:6473597d706e 191 MCG_IRQn = 57, /**< MCG Interrupt */
bogdanm 82:6473597d706e 192 LPTimer_IRQn = 58, /**< LPTimer interrupt */
bogdanm 82:6473597d706e 193 PORTA_IRQn = 59, /**< Port A interrupt */
bogdanm 82:6473597d706e 194 PORTB_IRQn = 60, /**< Port B interrupt */
bogdanm 82:6473597d706e 195 PORTC_IRQn = 61, /**< Port C interrupt */
bogdanm 82:6473597d706e 196 PORTD_IRQn = 62, /**< Port D interrupt */
bogdanm 82:6473597d706e 197 PORTE_IRQn = 63, /**< Port E interrupt */
bogdanm 82:6473597d706e 198 SWI_IRQn = 64, /**< Software interrupt */
bogdanm 82:6473597d706e 199 SPI2_IRQn = 65, /**< SPI2 Interrupt */
bogdanm 82:6473597d706e 200 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
bogdanm 82:6473597d706e 201 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
bogdanm 82:6473597d706e 202 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
bogdanm 82:6473597d706e 203 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
bogdanm 82:6473597d706e 204 CMP2_IRQn = 70, /**< CMP2 interrupt */
bogdanm 82:6473597d706e 205 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
bogdanm 82:6473597d706e 206 DAC1_IRQn = 72, /**< DAC1 interrupt */
bogdanm 82:6473597d706e 207 ADC1_IRQn = 73, /**< ADC1 interrupt */
bogdanm 82:6473597d706e 208 I2C2_IRQn = 74, /**< I2C2 interrupt */
bogdanm 82:6473597d706e 209 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
bogdanm 82:6473597d706e 210 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
bogdanm 82:6473597d706e 211 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
bogdanm 82:6473597d706e 212 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
bogdanm 82:6473597d706e 213 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
bogdanm 82:6473597d706e 214 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
bogdanm 82:6473597d706e 215 SDHC_IRQn = 81, /**< SDHC interrupt */
bogdanm 82:6473597d706e 216 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
bogdanm 82:6473597d706e 217 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
bogdanm 82:6473597d706e 218 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
bogdanm 82:6473597d706e 219 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
bogdanm 82:6473597d706e 220 } IRQn_Type;
bogdanm 82:6473597d706e 221
bogdanm 82:6473597d706e 222 /*!
bogdanm 82:6473597d706e 223 * @}
bogdanm 82:6473597d706e 224 */ /* end of group Interrupt_vector_numbers */
bogdanm 82:6473597d706e 225
bogdanm 82:6473597d706e 226
bogdanm 82:6473597d706e 227 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 228 -- Cortex M4 Core Configuration
bogdanm 82:6473597d706e 229 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 230
bogdanm 82:6473597d706e 231 /*!
bogdanm 82:6473597d706e 232 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
bogdanm 82:6473597d706e 233 * @{
bogdanm 82:6473597d706e 234 */
bogdanm 82:6473597d706e 235
bogdanm 82:6473597d706e 236 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
bogdanm 82:6473597d706e 237 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
bogdanm 82:6473597d706e 238 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
bogdanm 82:6473597d706e 239 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
bogdanm 82:6473597d706e 240
bogdanm 82:6473597d706e 241 #include "core_cm4.h" /* Core Peripheral Access Layer */
bogdanm 82:6473597d706e 242 #include "system_MK64F12.h" /* Device specific configuration file */
bogdanm 82:6473597d706e 243
bogdanm 82:6473597d706e 244 /*!
bogdanm 82:6473597d706e 245 * @}
bogdanm 82:6473597d706e 246 */ /* end of group Cortex_Core_Configuration */
bogdanm 82:6473597d706e 247
bogdanm 82:6473597d706e 248
bogdanm 82:6473597d706e 249 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 250 -- Device Peripheral Access Layer
bogdanm 82:6473597d706e 251 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 252
bogdanm 82:6473597d706e 253 /*!
bogdanm 82:6473597d706e 254 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
bogdanm 82:6473597d706e 255 * @{
bogdanm 82:6473597d706e 256 */
bogdanm 82:6473597d706e 257
bogdanm 82:6473597d706e 258
bogdanm 82:6473597d706e 259 /*
bogdanm 82:6473597d706e 260 ** Start of section using anonymous unions
bogdanm 82:6473597d706e 261 */
bogdanm 82:6473597d706e 262
bogdanm 82:6473597d706e 263 #if defined(__ARMCC_VERSION)
bogdanm 82:6473597d706e 264 #pragma push
bogdanm 82:6473597d706e 265 #pragma anon_unions
bogdanm 82:6473597d706e 266 #elif defined(__CWCC__)
bogdanm 82:6473597d706e 267 #pragma push
bogdanm 82:6473597d706e 268 #pragma cpp_extensions on
bogdanm 82:6473597d706e 269 #elif defined(__GNUC__)
bogdanm 82:6473597d706e 270 /* anonymous unions are enabled by default */
bogdanm 82:6473597d706e 271 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 82:6473597d706e 272 #pragma language=extended
bogdanm 82:6473597d706e 273 #else
bogdanm 82:6473597d706e 274 #error Not supported compiler type
bogdanm 82:6473597d706e 275 #endif
bogdanm 82:6473597d706e 276
bogdanm 82:6473597d706e 277 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 278 -- ADC Peripheral Access Layer
bogdanm 82:6473597d706e 279 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 280
bogdanm 82:6473597d706e 281 /*!
bogdanm 82:6473597d706e 282 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
bogdanm 82:6473597d706e 283 * @{
bogdanm 82:6473597d706e 284 */
bogdanm 82:6473597d706e 285
bogdanm 82:6473597d706e 286 /** ADC - Register Layout Typedef */
bogdanm 82:6473597d706e 287 typedef struct {
bogdanm 82:6473597d706e 288 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
bogdanm 82:6473597d706e 289 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
bogdanm 82:6473597d706e 290 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
bogdanm 82:6473597d706e 291 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
bogdanm 82:6473597d706e 292 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
bogdanm 82:6473597d706e 293 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
bogdanm 82:6473597d706e 294 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
bogdanm 82:6473597d706e 295 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
bogdanm 82:6473597d706e 296 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
bogdanm 82:6473597d706e 297 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
bogdanm 82:6473597d706e 298 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
bogdanm 82:6473597d706e 299 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
bogdanm 82:6473597d706e 300 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
bogdanm 82:6473597d706e 301 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
bogdanm 82:6473597d706e 302 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
bogdanm 82:6473597d706e 303 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
bogdanm 82:6473597d706e 304 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
bogdanm 82:6473597d706e 305 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
bogdanm 82:6473597d706e 306 uint8_t RESERVED_0[4];
bogdanm 82:6473597d706e 307 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
bogdanm 82:6473597d706e 308 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
bogdanm 82:6473597d706e 309 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
bogdanm 82:6473597d706e 310 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
bogdanm 82:6473597d706e 311 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
bogdanm 82:6473597d706e 312 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
bogdanm 82:6473597d706e 313 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
bogdanm 82:6473597d706e 314 } ADC_Type, *ADC_MemMapPtr;
bogdanm 82:6473597d706e 315
bogdanm 82:6473597d706e 316 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 317 -- ADC - Register accessor macros
bogdanm 82:6473597d706e 318 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 319
bogdanm 82:6473597d706e 320 /*!
bogdanm 82:6473597d706e 321 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
bogdanm 82:6473597d706e 322 * @{
bogdanm 82:6473597d706e 323 */
bogdanm 82:6473597d706e 324
bogdanm 82:6473597d706e 325
bogdanm 82:6473597d706e 326 /* ADC - Register accessors */
bogdanm 82:6473597d706e 327 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
bogdanm 82:6473597d706e 328 #define ADC_CFG1_REG(base) ((base)->CFG1)
bogdanm 82:6473597d706e 329 #define ADC_CFG2_REG(base) ((base)->CFG2)
bogdanm 82:6473597d706e 330 #define ADC_R_REG(base,index) ((base)->R[index])
bogdanm 82:6473597d706e 331 #define ADC_CV1_REG(base) ((base)->CV1)
bogdanm 82:6473597d706e 332 #define ADC_CV2_REG(base) ((base)->CV2)
bogdanm 82:6473597d706e 333 #define ADC_SC2_REG(base) ((base)->SC2)
bogdanm 82:6473597d706e 334 #define ADC_SC3_REG(base) ((base)->SC3)
bogdanm 82:6473597d706e 335 #define ADC_OFS_REG(base) ((base)->OFS)
bogdanm 82:6473597d706e 336 #define ADC_PG_REG(base) ((base)->PG)
bogdanm 82:6473597d706e 337 #define ADC_MG_REG(base) ((base)->MG)
bogdanm 82:6473597d706e 338 #define ADC_CLPD_REG(base) ((base)->CLPD)
bogdanm 82:6473597d706e 339 #define ADC_CLPS_REG(base) ((base)->CLPS)
bogdanm 82:6473597d706e 340 #define ADC_CLP4_REG(base) ((base)->CLP4)
bogdanm 82:6473597d706e 341 #define ADC_CLP3_REG(base) ((base)->CLP3)
bogdanm 82:6473597d706e 342 #define ADC_CLP2_REG(base) ((base)->CLP2)
bogdanm 82:6473597d706e 343 #define ADC_CLP1_REG(base) ((base)->CLP1)
bogdanm 82:6473597d706e 344 #define ADC_CLP0_REG(base) ((base)->CLP0)
bogdanm 82:6473597d706e 345 #define ADC_CLMD_REG(base) ((base)->CLMD)
bogdanm 82:6473597d706e 346 #define ADC_CLMS_REG(base) ((base)->CLMS)
bogdanm 82:6473597d706e 347 #define ADC_CLM4_REG(base) ((base)->CLM4)
bogdanm 82:6473597d706e 348 #define ADC_CLM3_REG(base) ((base)->CLM3)
bogdanm 82:6473597d706e 349 #define ADC_CLM2_REG(base) ((base)->CLM2)
bogdanm 82:6473597d706e 350 #define ADC_CLM1_REG(base) ((base)->CLM1)
bogdanm 82:6473597d706e 351 #define ADC_CLM0_REG(base) ((base)->CLM0)
bogdanm 82:6473597d706e 352
bogdanm 82:6473597d706e 353 /*!
bogdanm 82:6473597d706e 354 * @}
bogdanm 82:6473597d706e 355 */ /* end of group ADC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 356
bogdanm 82:6473597d706e 357
bogdanm 82:6473597d706e 358 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 359 -- ADC Register Masks
bogdanm 82:6473597d706e 360 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 361
bogdanm 82:6473597d706e 362 /*!
bogdanm 82:6473597d706e 363 * @addtogroup ADC_Register_Masks ADC Register Masks
bogdanm 82:6473597d706e 364 * @{
bogdanm 82:6473597d706e 365 */
bogdanm 82:6473597d706e 366
bogdanm 82:6473597d706e 367 /* SC1 Bit Fields */
bogdanm 82:6473597d706e 368 #define ADC_SC1_ADCH_MASK 0x1Fu
bogdanm 82:6473597d706e 369 #define ADC_SC1_ADCH_SHIFT 0
bogdanm 82:6473597d706e 370 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
bogdanm 82:6473597d706e 371 #define ADC_SC1_DIFF_MASK 0x20u
bogdanm 82:6473597d706e 372 #define ADC_SC1_DIFF_SHIFT 5
bogdanm 82:6473597d706e 373 #define ADC_SC1_AIEN_MASK 0x40u
bogdanm 82:6473597d706e 374 #define ADC_SC1_AIEN_SHIFT 6
bogdanm 82:6473597d706e 375 #define ADC_SC1_COCO_MASK 0x80u
bogdanm 82:6473597d706e 376 #define ADC_SC1_COCO_SHIFT 7
bogdanm 82:6473597d706e 377 /* CFG1 Bit Fields */
bogdanm 82:6473597d706e 378 #define ADC_CFG1_ADICLK_MASK 0x3u
bogdanm 82:6473597d706e 379 #define ADC_CFG1_ADICLK_SHIFT 0
bogdanm 82:6473597d706e 380 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
bogdanm 82:6473597d706e 381 #define ADC_CFG1_MODE_MASK 0xCu
bogdanm 82:6473597d706e 382 #define ADC_CFG1_MODE_SHIFT 2
bogdanm 82:6473597d706e 383 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
bogdanm 82:6473597d706e 384 #define ADC_CFG1_ADLSMP_MASK 0x10u
bogdanm 82:6473597d706e 385 #define ADC_CFG1_ADLSMP_SHIFT 4
bogdanm 82:6473597d706e 386 #define ADC_CFG1_ADIV_MASK 0x60u
bogdanm 82:6473597d706e 387 #define ADC_CFG1_ADIV_SHIFT 5
bogdanm 82:6473597d706e 388 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
bogdanm 82:6473597d706e 389 #define ADC_CFG1_ADLPC_MASK 0x80u
bogdanm 82:6473597d706e 390 #define ADC_CFG1_ADLPC_SHIFT 7
bogdanm 82:6473597d706e 391 /* CFG2 Bit Fields */
bogdanm 82:6473597d706e 392 #define ADC_CFG2_ADLSTS_MASK 0x3u
bogdanm 82:6473597d706e 393 #define ADC_CFG2_ADLSTS_SHIFT 0
bogdanm 82:6473597d706e 394 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
bogdanm 82:6473597d706e 395 #define ADC_CFG2_ADHSC_MASK 0x4u
bogdanm 82:6473597d706e 396 #define ADC_CFG2_ADHSC_SHIFT 2
bogdanm 82:6473597d706e 397 #define ADC_CFG2_ADACKEN_MASK 0x8u
bogdanm 82:6473597d706e 398 #define ADC_CFG2_ADACKEN_SHIFT 3
bogdanm 82:6473597d706e 399 #define ADC_CFG2_MUXSEL_MASK 0x10u
bogdanm 82:6473597d706e 400 #define ADC_CFG2_MUXSEL_SHIFT 4
bogdanm 82:6473597d706e 401 /* R Bit Fields */
bogdanm 82:6473597d706e 402 #define ADC_R_D_MASK 0xFFFFu
bogdanm 82:6473597d706e 403 #define ADC_R_D_SHIFT 0
bogdanm 82:6473597d706e 404 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
bogdanm 82:6473597d706e 405 /* CV1 Bit Fields */
bogdanm 82:6473597d706e 406 #define ADC_CV1_CV_MASK 0xFFFFu
bogdanm 82:6473597d706e 407 #define ADC_CV1_CV_SHIFT 0
bogdanm 82:6473597d706e 408 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
bogdanm 82:6473597d706e 409 /* CV2 Bit Fields */
bogdanm 82:6473597d706e 410 #define ADC_CV2_CV_MASK 0xFFFFu
bogdanm 82:6473597d706e 411 #define ADC_CV2_CV_SHIFT 0
bogdanm 82:6473597d706e 412 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
bogdanm 82:6473597d706e 413 /* SC2 Bit Fields */
bogdanm 82:6473597d706e 414 #define ADC_SC2_REFSEL_MASK 0x3u
bogdanm 82:6473597d706e 415 #define ADC_SC2_REFSEL_SHIFT 0
bogdanm 82:6473597d706e 416 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
bogdanm 82:6473597d706e 417 #define ADC_SC2_DMAEN_MASK 0x4u
bogdanm 82:6473597d706e 418 #define ADC_SC2_DMAEN_SHIFT 2
bogdanm 82:6473597d706e 419 #define ADC_SC2_ACREN_MASK 0x8u
bogdanm 82:6473597d706e 420 #define ADC_SC2_ACREN_SHIFT 3
bogdanm 82:6473597d706e 421 #define ADC_SC2_ACFGT_MASK 0x10u
bogdanm 82:6473597d706e 422 #define ADC_SC2_ACFGT_SHIFT 4
bogdanm 82:6473597d706e 423 #define ADC_SC2_ACFE_MASK 0x20u
bogdanm 82:6473597d706e 424 #define ADC_SC2_ACFE_SHIFT 5
bogdanm 82:6473597d706e 425 #define ADC_SC2_ADTRG_MASK 0x40u
bogdanm 82:6473597d706e 426 #define ADC_SC2_ADTRG_SHIFT 6
bogdanm 82:6473597d706e 427 #define ADC_SC2_ADACT_MASK 0x80u
bogdanm 82:6473597d706e 428 #define ADC_SC2_ADACT_SHIFT 7
bogdanm 82:6473597d706e 429 /* SC3 Bit Fields */
bogdanm 82:6473597d706e 430 #define ADC_SC3_AVGS_MASK 0x3u
bogdanm 82:6473597d706e 431 #define ADC_SC3_AVGS_SHIFT 0
bogdanm 82:6473597d706e 432 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
bogdanm 82:6473597d706e 433 #define ADC_SC3_AVGE_MASK 0x4u
bogdanm 82:6473597d706e 434 #define ADC_SC3_AVGE_SHIFT 2
bogdanm 82:6473597d706e 435 #define ADC_SC3_ADCO_MASK 0x8u
bogdanm 82:6473597d706e 436 #define ADC_SC3_ADCO_SHIFT 3
bogdanm 82:6473597d706e 437 #define ADC_SC3_CALF_MASK 0x40u
bogdanm 82:6473597d706e 438 #define ADC_SC3_CALF_SHIFT 6
bogdanm 82:6473597d706e 439 #define ADC_SC3_CAL_MASK 0x80u
bogdanm 82:6473597d706e 440 #define ADC_SC3_CAL_SHIFT 7
bogdanm 82:6473597d706e 441 /* OFS Bit Fields */
bogdanm 82:6473597d706e 442 #define ADC_OFS_OFS_MASK 0xFFFFu
bogdanm 82:6473597d706e 443 #define ADC_OFS_OFS_SHIFT 0
bogdanm 82:6473597d706e 444 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
bogdanm 82:6473597d706e 445 /* PG Bit Fields */
bogdanm 82:6473597d706e 446 #define ADC_PG_PG_MASK 0xFFFFu
bogdanm 82:6473597d706e 447 #define ADC_PG_PG_SHIFT 0
bogdanm 82:6473597d706e 448 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
bogdanm 82:6473597d706e 449 /* MG Bit Fields */
bogdanm 82:6473597d706e 450 #define ADC_MG_MG_MASK 0xFFFFu
bogdanm 82:6473597d706e 451 #define ADC_MG_MG_SHIFT 0
bogdanm 82:6473597d706e 452 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
bogdanm 82:6473597d706e 453 /* CLPD Bit Fields */
bogdanm 82:6473597d706e 454 #define ADC_CLPD_CLPD_MASK 0x3Fu
bogdanm 82:6473597d706e 455 #define ADC_CLPD_CLPD_SHIFT 0
bogdanm 82:6473597d706e 456 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
bogdanm 82:6473597d706e 457 /* CLPS Bit Fields */
bogdanm 82:6473597d706e 458 #define ADC_CLPS_CLPS_MASK 0x3Fu
bogdanm 82:6473597d706e 459 #define ADC_CLPS_CLPS_SHIFT 0
bogdanm 82:6473597d706e 460 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
bogdanm 82:6473597d706e 461 /* CLP4 Bit Fields */
bogdanm 82:6473597d706e 462 #define ADC_CLP4_CLP4_MASK 0x3FFu
bogdanm 82:6473597d706e 463 #define ADC_CLP4_CLP4_SHIFT 0
bogdanm 82:6473597d706e 464 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
bogdanm 82:6473597d706e 465 /* CLP3 Bit Fields */
bogdanm 82:6473597d706e 466 #define ADC_CLP3_CLP3_MASK 0x1FFu
bogdanm 82:6473597d706e 467 #define ADC_CLP3_CLP3_SHIFT 0
bogdanm 82:6473597d706e 468 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
bogdanm 82:6473597d706e 469 /* CLP2 Bit Fields */
bogdanm 82:6473597d706e 470 #define ADC_CLP2_CLP2_MASK 0xFFu
bogdanm 82:6473597d706e 471 #define ADC_CLP2_CLP2_SHIFT 0
bogdanm 82:6473597d706e 472 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
bogdanm 82:6473597d706e 473 /* CLP1 Bit Fields */
bogdanm 82:6473597d706e 474 #define ADC_CLP1_CLP1_MASK 0x7Fu
bogdanm 82:6473597d706e 475 #define ADC_CLP1_CLP1_SHIFT 0
bogdanm 82:6473597d706e 476 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
bogdanm 82:6473597d706e 477 /* CLP0 Bit Fields */
bogdanm 82:6473597d706e 478 #define ADC_CLP0_CLP0_MASK 0x3Fu
bogdanm 82:6473597d706e 479 #define ADC_CLP0_CLP0_SHIFT 0
bogdanm 82:6473597d706e 480 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
bogdanm 82:6473597d706e 481 /* CLMD Bit Fields */
bogdanm 82:6473597d706e 482 #define ADC_CLMD_CLMD_MASK 0x3Fu
bogdanm 82:6473597d706e 483 #define ADC_CLMD_CLMD_SHIFT 0
bogdanm 82:6473597d706e 484 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
bogdanm 82:6473597d706e 485 /* CLMS Bit Fields */
bogdanm 82:6473597d706e 486 #define ADC_CLMS_CLMS_MASK 0x3Fu
bogdanm 82:6473597d706e 487 #define ADC_CLMS_CLMS_SHIFT 0
bogdanm 82:6473597d706e 488 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
bogdanm 82:6473597d706e 489 /* CLM4 Bit Fields */
bogdanm 82:6473597d706e 490 #define ADC_CLM4_CLM4_MASK 0x3FFu
bogdanm 82:6473597d706e 491 #define ADC_CLM4_CLM4_SHIFT 0
bogdanm 82:6473597d706e 492 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
bogdanm 82:6473597d706e 493 /* CLM3 Bit Fields */
bogdanm 82:6473597d706e 494 #define ADC_CLM3_CLM3_MASK 0x1FFu
bogdanm 82:6473597d706e 495 #define ADC_CLM3_CLM3_SHIFT 0
bogdanm 82:6473597d706e 496 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
bogdanm 82:6473597d706e 497 /* CLM2 Bit Fields */
bogdanm 82:6473597d706e 498 #define ADC_CLM2_CLM2_MASK 0xFFu
bogdanm 82:6473597d706e 499 #define ADC_CLM2_CLM2_SHIFT 0
bogdanm 82:6473597d706e 500 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
bogdanm 82:6473597d706e 501 /* CLM1 Bit Fields */
bogdanm 82:6473597d706e 502 #define ADC_CLM1_CLM1_MASK 0x7Fu
bogdanm 82:6473597d706e 503 #define ADC_CLM1_CLM1_SHIFT 0
bogdanm 82:6473597d706e 504 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
bogdanm 82:6473597d706e 505 /* CLM0 Bit Fields */
bogdanm 82:6473597d706e 506 #define ADC_CLM0_CLM0_MASK 0x3Fu
bogdanm 82:6473597d706e 507 #define ADC_CLM0_CLM0_SHIFT 0
bogdanm 82:6473597d706e 508 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
bogdanm 82:6473597d706e 509
bogdanm 82:6473597d706e 510 /*!
bogdanm 82:6473597d706e 511 * @}
bogdanm 82:6473597d706e 512 */ /* end of group ADC_Register_Masks */
bogdanm 82:6473597d706e 513
bogdanm 82:6473597d706e 514
bogdanm 82:6473597d706e 515 /* ADC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 516 /** Peripheral ADC0 base address */
bogdanm 82:6473597d706e 517 #define ADC0_BASE (0x4003B000u)
bogdanm 82:6473597d706e 518 /** Peripheral ADC0 base pointer */
bogdanm 82:6473597d706e 519 #define ADC0 ((ADC_Type *)ADC0_BASE)
bogdanm 82:6473597d706e 520 #define ADC0_BASE_PTR (ADC0)
bogdanm 82:6473597d706e 521 /** Peripheral ADC1 base address */
bogdanm 82:6473597d706e 522 #define ADC1_BASE (0x400BB000u)
bogdanm 82:6473597d706e 523 /** Peripheral ADC1 base pointer */
bogdanm 82:6473597d706e 524 #define ADC1 ((ADC_Type *)ADC1_BASE)
bogdanm 82:6473597d706e 525 #define ADC1_BASE_PTR (ADC1)
bogdanm 82:6473597d706e 526 /** Array initializer of ADC peripheral base pointers */
bogdanm 82:6473597d706e 527 #define ADC_BASES { ADC0, ADC1 }
bogdanm 82:6473597d706e 528
bogdanm 82:6473597d706e 529 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 530 -- ADC - Register accessor macros
bogdanm 82:6473597d706e 531 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 532
bogdanm 82:6473597d706e 533 /*!
bogdanm 82:6473597d706e 534 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
bogdanm 82:6473597d706e 535 * @{
bogdanm 82:6473597d706e 536 */
bogdanm 82:6473597d706e 537
bogdanm 82:6473597d706e 538
bogdanm 82:6473597d706e 539 /* ADC - Register instance definitions */
bogdanm 82:6473597d706e 540 /* ADC0 */
bogdanm 82:6473597d706e 541 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
bogdanm 82:6473597d706e 542 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
bogdanm 82:6473597d706e 543 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
bogdanm 82:6473597d706e 544 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
bogdanm 82:6473597d706e 545 #define ADC0_RA ADC_R_REG(ADC0,0)
bogdanm 82:6473597d706e 546 #define ADC0_RB ADC_R_REG(ADC0,1)
bogdanm 82:6473597d706e 547 #define ADC0_CV1 ADC_CV1_REG(ADC0)
bogdanm 82:6473597d706e 548 #define ADC0_CV2 ADC_CV2_REG(ADC0)
bogdanm 82:6473597d706e 549 #define ADC0_SC2 ADC_SC2_REG(ADC0)
bogdanm 82:6473597d706e 550 #define ADC0_SC3 ADC_SC3_REG(ADC0)
bogdanm 82:6473597d706e 551 #define ADC0_OFS ADC_OFS_REG(ADC0)
bogdanm 82:6473597d706e 552 #define ADC0_PG ADC_PG_REG(ADC0)
bogdanm 82:6473597d706e 553 #define ADC0_MG ADC_MG_REG(ADC0)
bogdanm 82:6473597d706e 554 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
bogdanm 82:6473597d706e 555 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
bogdanm 82:6473597d706e 556 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
bogdanm 82:6473597d706e 557 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
bogdanm 82:6473597d706e 558 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
bogdanm 82:6473597d706e 559 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
bogdanm 82:6473597d706e 560 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
bogdanm 82:6473597d706e 561 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
bogdanm 82:6473597d706e 562 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
bogdanm 82:6473597d706e 563 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
bogdanm 82:6473597d706e 564 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
bogdanm 82:6473597d706e 565 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
bogdanm 82:6473597d706e 566 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
bogdanm 82:6473597d706e 567 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
bogdanm 82:6473597d706e 568 /* ADC1 */
bogdanm 82:6473597d706e 569 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
bogdanm 82:6473597d706e 570 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
bogdanm 82:6473597d706e 571 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
bogdanm 82:6473597d706e 572 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
bogdanm 82:6473597d706e 573 #define ADC1_RA ADC_R_REG(ADC1,0)
bogdanm 82:6473597d706e 574 #define ADC1_RB ADC_R_REG(ADC1,1)
bogdanm 82:6473597d706e 575 #define ADC1_CV1 ADC_CV1_REG(ADC1)
bogdanm 82:6473597d706e 576 #define ADC1_CV2 ADC_CV2_REG(ADC1)
bogdanm 82:6473597d706e 577 #define ADC1_SC2 ADC_SC2_REG(ADC1)
bogdanm 82:6473597d706e 578 #define ADC1_SC3 ADC_SC3_REG(ADC1)
bogdanm 82:6473597d706e 579 #define ADC1_OFS ADC_OFS_REG(ADC1)
bogdanm 82:6473597d706e 580 #define ADC1_PG ADC_PG_REG(ADC1)
bogdanm 82:6473597d706e 581 #define ADC1_MG ADC_MG_REG(ADC1)
bogdanm 82:6473597d706e 582 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
bogdanm 82:6473597d706e 583 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
bogdanm 82:6473597d706e 584 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
bogdanm 82:6473597d706e 585 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
bogdanm 82:6473597d706e 586 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
bogdanm 82:6473597d706e 587 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
bogdanm 82:6473597d706e 588 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
bogdanm 82:6473597d706e 589 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
bogdanm 82:6473597d706e 590 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
bogdanm 82:6473597d706e 591 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
bogdanm 82:6473597d706e 592 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
bogdanm 82:6473597d706e 593 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
bogdanm 82:6473597d706e 594 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
bogdanm 82:6473597d706e 595 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
bogdanm 82:6473597d706e 596
bogdanm 82:6473597d706e 597 /* ADC - Register array accessors */
bogdanm 82:6473597d706e 598 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
bogdanm 82:6473597d706e 599 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
bogdanm 82:6473597d706e 600 #define ADC0_R(index) ADC_R_REG(ADC0,index)
bogdanm 82:6473597d706e 601 #define ADC1_R(index) ADC_R_REG(ADC1,index)
bogdanm 82:6473597d706e 602
bogdanm 82:6473597d706e 603 /*!
bogdanm 82:6473597d706e 604 * @}
bogdanm 82:6473597d706e 605 */ /* end of group ADC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 606
bogdanm 82:6473597d706e 607
bogdanm 82:6473597d706e 608 /*!
bogdanm 82:6473597d706e 609 * @}
bogdanm 82:6473597d706e 610 */ /* end of group ADC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 611
bogdanm 82:6473597d706e 612
bogdanm 82:6473597d706e 613 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 614 -- AIPS Peripheral Access Layer
bogdanm 82:6473597d706e 615 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 616
bogdanm 82:6473597d706e 617 /*!
bogdanm 82:6473597d706e 618 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
bogdanm 82:6473597d706e 619 * @{
bogdanm 82:6473597d706e 620 */
bogdanm 82:6473597d706e 621
bogdanm 82:6473597d706e 622 /** AIPS - Register Layout Typedef */
bogdanm 82:6473597d706e 623 typedef struct {
bogdanm 82:6473597d706e 624 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
bogdanm 82:6473597d706e 625 uint8_t RESERVED_0[28];
bogdanm 82:6473597d706e 626 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
bogdanm 82:6473597d706e 627 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
bogdanm 82:6473597d706e 628 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
bogdanm 82:6473597d706e 629 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
bogdanm 82:6473597d706e 630 uint8_t RESERVED_1[16];
bogdanm 82:6473597d706e 631 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
bogdanm 82:6473597d706e 632 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
bogdanm 82:6473597d706e 633 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
bogdanm 82:6473597d706e 634 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
bogdanm 82:6473597d706e 635 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
bogdanm 82:6473597d706e 636 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
bogdanm 82:6473597d706e 637 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
bogdanm 82:6473597d706e 638 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
bogdanm 82:6473597d706e 639 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
bogdanm 82:6473597d706e 640 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
bogdanm 82:6473597d706e 641 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
bogdanm 82:6473597d706e 642 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
bogdanm 82:6473597d706e 643 uint8_t RESERVED_2[16];
bogdanm 82:6473597d706e 644 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
bogdanm 82:6473597d706e 645 } AIPS_Type, *AIPS_MemMapPtr;
bogdanm 82:6473597d706e 646
bogdanm 82:6473597d706e 647 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 648 -- AIPS - Register accessor macros
bogdanm 82:6473597d706e 649 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 650
bogdanm 82:6473597d706e 651 /*!
bogdanm 82:6473597d706e 652 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
bogdanm 82:6473597d706e 653 * @{
bogdanm 82:6473597d706e 654 */
bogdanm 82:6473597d706e 655
bogdanm 82:6473597d706e 656
bogdanm 82:6473597d706e 657 /* AIPS - Register accessors */
bogdanm 82:6473597d706e 658 #define AIPS_MPRA_REG(base) ((base)->MPRA)
bogdanm 82:6473597d706e 659 #define AIPS_PACRA_REG(base) ((base)->PACRA)
bogdanm 82:6473597d706e 660 #define AIPS_PACRB_REG(base) ((base)->PACRB)
bogdanm 82:6473597d706e 661 #define AIPS_PACRC_REG(base) ((base)->PACRC)
bogdanm 82:6473597d706e 662 #define AIPS_PACRD_REG(base) ((base)->PACRD)
bogdanm 82:6473597d706e 663 #define AIPS_PACRE_REG(base) ((base)->PACRE)
bogdanm 82:6473597d706e 664 #define AIPS_PACRF_REG(base) ((base)->PACRF)
bogdanm 82:6473597d706e 665 #define AIPS_PACRG_REG(base) ((base)->PACRG)
bogdanm 82:6473597d706e 666 #define AIPS_PACRH_REG(base) ((base)->PACRH)
bogdanm 82:6473597d706e 667 #define AIPS_PACRI_REG(base) ((base)->PACRI)
bogdanm 82:6473597d706e 668 #define AIPS_PACRJ_REG(base) ((base)->PACRJ)
bogdanm 82:6473597d706e 669 #define AIPS_PACRK_REG(base) ((base)->PACRK)
bogdanm 82:6473597d706e 670 #define AIPS_PACRL_REG(base) ((base)->PACRL)
bogdanm 82:6473597d706e 671 #define AIPS_PACRM_REG(base) ((base)->PACRM)
bogdanm 82:6473597d706e 672 #define AIPS_PACRN_REG(base) ((base)->PACRN)
bogdanm 82:6473597d706e 673 #define AIPS_PACRO_REG(base) ((base)->PACRO)
bogdanm 82:6473597d706e 674 #define AIPS_PACRP_REG(base) ((base)->PACRP)
bogdanm 82:6473597d706e 675 #define AIPS_PACRU_REG(base) ((base)->PACRU)
bogdanm 82:6473597d706e 676
bogdanm 82:6473597d706e 677 /*!
bogdanm 82:6473597d706e 678 * @}
bogdanm 82:6473597d706e 679 */ /* end of group AIPS_Register_Accessor_Macros */
bogdanm 82:6473597d706e 680
bogdanm 82:6473597d706e 681
bogdanm 82:6473597d706e 682 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 683 -- AIPS Register Masks
bogdanm 82:6473597d706e 684 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 685
bogdanm 82:6473597d706e 686 /*!
bogdanm 82:6473597d706e 687 * @addtogroup AIPS_Register_Masks AIPS Register Masks
bogdanm 82:6473597d706e 688 * @{
bogdanm 82:6473597d706e 689 */
bogdanm 82:6473597d706e 690
bogdanm 82:6473597d706e 691 /* PACRA Bit Fields */
bogdanm 82:6473597d706e 692 #define AIPS_PACRA_TP7_MASK 0x1u
bogdanm 82:6473597d706e 693 #define AIPS_PACRA_TP7_SHIFT 0
bogdanm 82:6473597d706e 694 #define AIPS_PACRA_WP7_MASK 0x2u
bogdanm 82:6473597d706e 695 #define AIPS_PACRA_WP7_SHIFT 1
bogdanm 82:6473597d706e 696 #define AIPS_PACRA_SP7_MASK 0x4u
bogdanm 82:6473597d706e 697 #define AIPS_PACRA_SP7_SHIFT 2
bogdanm 82:6473597d706e 698 #define AIPS_PACRA_TP6_MASK 0x10u
bogdanm 82:6473597d706e 699 #define AIPS_PACRA_TP6_SHIFT 4
bogdanm 82:6473597d706e 700 #define AIPS_PACRA_WP6_MASK 0x20u
bogdanm 82:6473597d706e 701 #define AIPS_PACRA_WP6_SHIFT 5
bogdanm 82:6473597d706e 702 #define AIPS_PACRA_SP6_MASK 0x40u
bogdanm 82:6473597d706e 703 #define AIPS_PACRA_SP6_SHIFT 6
bogdanm 82:6473597d706e 704 #define AIPS_PACRA_TP5_MASK 0x100u
bogdanm 82:6473597d706e 705 #define AIPS_PACRA_TP5_SHIFT 8
bogdanm 82:6473597d706e 706 #define AIPS_PACRA_WP5_MASK 0x200u
bogdanm 82:6473597d706e 707 #define AIPS_PACRA_WP5_SHIFT 9
bogdanm 82:6473597d706e 708 #define AIPS_PACRA_SP5_MASK 0x400u
bogdanm 82:6473597d706e 709 #define AIPS_PACRA_SP5_SHIFT 10
bogdanm 82:6473597d706e 710 #define AIPS_PACRA_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 711 #define AIPS_PACRA_TP4_SHIFT 12
bogdanm 82:6473597d706e 712 #define AIPS_PACRA_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 713 #define AIPS_PACRA_WP4_SHIFT 13
bogdanm 82:6473597d706e 714 #define AIPS_PACRA_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 715 #define AIPS_PACRA_SP4_SHIFT 14
bogdanm 82:6473597d706e 716 #define AIPS_PACRA_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 717 #define AIPS_PACRA_TP3_SHIFT 16
bogdanm 82:6473597d706e 718 #define AIPS_PACRA_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 719 #define AIPS_PACRA_WP3_SHIFT 17
bogdanm 82:6473597d706e 720 #define AIPS_PACRA_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 721 #define AIPS_PACRA_SP3_SHIFT 18
bogdanm 82:6473597d706e 722 #define AIPS_PACRA_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 723 #define AIPS_PACRA_TP2_SHIFT 20
bogdanm 82:6473597d706e 724 #define AIPS_PACRA_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 725 #define AIPS_PACRA_WP2_SHIFT 21
bogdanm 82:6473597d706e 726 #define AIPS_PACRA_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 727 #define AIPS_PACRA_SP2_SHIFT 22
bogdanm 82:6473597d706e 728 #define AIPS_PACRA_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 729 #define AIPS_PACRA_TP1_SHIFT 24
bogdanm 82:6473597d706e 730 #define AIPS_PACRA_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 731 #define AIPS_PACRA_WP1_SHIFT 25
bogdanm 82:6473597d706e 732 #define AIPS_PACRA_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 733 #define AIPS_PACRA_SP1_SHIFT 26
bogdanm 82:6473597d706e 734 #define AIPS_PACRA_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 735 #define AIPS_PACRA_TP0_SHIFT 28
bogdanm 82:6473597d706e 736 #define AIPS_PACRA_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 737 #define AIPS_PACRA_WP0_SHIFT 29
bogdanm 82:6473597d706e 738 #define AIPS_PACRA_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 739 #define AIPS_PACRA_SP0_SHIFT 30
bogdanm 82:6473597d706e 740 /* PACRB Bit Fields */
bogdanm 82:6473597d706e 741 #define AIPS_PACRB_TP7_MASK 0x1u
bogdanm 82:6473597d706e 742 #define AIPS_PACRB_TP7_SHIFT 0
bogdanm 82:6473597d706e 743 #define AIPS_PACRB_WP7_MASK 0x2u
bogdanm 82:6473597d706e 744 #define AIPS_PACRB_WP7_SHIFT 1
bogdanm 82:6473597d706e 745 #define AIPS_PACRB_SP7_MASK 0x4u
bogdanm 82:6473597d706e 746 #define AIPS_PACRB_SP7_SHIFT 2
bogdanm 82:6473597d706e 747 #define AIPS_PACRB_TP6_MASK 0x10u
bogdanm 82:6473597d706e 748 #define AIPS_PACRB_TP6_SHIFT 4
bogdanm 82:6473597d706e 749 #define AIPS_PACRB_WP6_MASK 0x20u
bogdanm 82:6473597d706e 750 #define AIPS_PACRB_WP6_SHIFT 5
bogdanm 82:6473597d706e 751 #define AIPS_PACRB_SP6_MASK 0x40u
bogdanm 82:6473597d706e 752 #define AIPS_PACRB_SP6_SHIFT 6
bogdanm 82:6473597d706e 753 #define AIPS_PACRB_TP5_MASK 0x100u
bogdanm 82:6473597d706e 754 #define AIPS_PACRB_TP5_SHIFT 8
bogdanm 82:6473597d706e 755 #define AIPS_PACRB_WP5_MASK 0x200u
bogdanm 82:6473597d706e 756 #define AIPS_PACRB_WP5_SHIFT 9
bogdanm 82:6473597d706e 757 #define AIPS_PACRB_SP5_MASK 0x400u
bogdanm 82:6473597d706e 758 #define AIPS_PACRB_SP5_SHIFT 10
bogdanm 82:6473597d706e 759 #define AIPS_PACRB_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 760 #define AIPS_PACRB_TP4_SHIFT 12
bogdanm 82:6473597d706e 761 #define AIPS_PACRB_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 762 #define AIPS_PACRB_WP4_SHIFT 13
bogdanm 82:6473597d706e 763 #define AIPS_PACRB_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 764 #define AIPS_PACRB_SP4_SHIFT 14
bogdanm 82:6473597d706e 765 #define AIPS_PACRB_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 766 #define AIPS_PACRB_TP3_SHIFT 16
bogdanm 82:6473597d706e 767 #define AIPS_PACRB_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 768 #define AIPS_PACRB_WP3_SHIFT 17
bogdanm 82:6473597d706e 769 #define AIPS_PACRB_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 770 #define AIPS_PACRB_SP3_SHIFT 18
bogdanm 82:6473597d706e 771 #define AIPS_PACRB_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 772 #define AIPS_PACRB_TP2_SHIFT 20
bogdanm 82:6473597d706e 773 #define AIPS_PACRB_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 774 #define AIPS_PACRB_WP2_SHIFT 21
bogdanm 82:6473597d706e 775 #define AIPS_PACRB_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 776 #define AIPS_PACRB_SP2_SHIFT 22
bogdanm 82:6473597d706e 777 #define AIPS_PACRB_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 778 #define AIPS_PACRB_TP1_SHIFT 24
bogdanm 82:6473597d706e 779 #define AIPS_PACRB_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 780 #define AIPS_PACRB_WP1_SHIFT 25
bogdanm 82:6473597d706e 781 #define AIPS_PACRB_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 782 #define AIPS_PACRB_SP1_SHIFT 26
bogdanm 82:6473597d706e 783 #define AIPS_PACRB_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 784 #define AIPS_PACRB_TP0_SHIFT 28
bogdanm 82:6473597d706e 785 #define AIPS_PACRB_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 786 #define AIPS_PACRB_WP0_SHIFT 29
bogdanm 82:6473597d706e 787 #define AIPS_PACRB_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 788 #define AIPS_PACRB_SP0_SHIFT 30
bogdanm 82:6473597d706e 789 /* PACRC Bit Fields */
bogdanm 82:6473597d706e 790 #define AIPS_PACRC_TP7_MASK 0x1u
bogdanm 82:6473597d706e 791 #define AIPS_PACRC_TP7_SHIFT 0
bogdanm 82:6473597d706e 792 #define AIPS_PACRC_WP7_MASK 0x2u
bogdanm 82:6473597d706e 793 #define AIPS_PACRC_WP7_SHIFT 1
bogdanm 82:6473597d706e 794 #define AIPS_PACRC_SP7_MASK 0x4u
bogdanm 82:6473597d706e 795 #define AIPS_PACRC_SP7_SHIFT 2
bogdanm 82:6473597d706e 796 #define AIPS_PACRC_TP6_MASK 0x10u
bogdanm 82:6473597d706e 797 #define AIPS_PACRC_TP6_SHIFT 4
bogdanm 82:6473597d706e 798 #define AIPS_PACRC_WP6_MASK 0x20u
bogdanm 82:6473597d706e 799 #define AIPS_PACRC_WP6_SHIFT 5
bogdanm 82:6473597d706e 800 #define AIPS_PACRC_SP6_MASK 0x40u
bogdanm 82:6473597d706e 801 #define AIPS_PACRC_SP6_SHIFT 6
bogdanm 82:6473597d706e 802 #define AIPS_PACRC_TP5_MASK 0x100u
bogdanm 82:6473597d706e 803 #define AIPS_PACRC_TP5_SHIFT 8
bogdanm 82:6473597d706e 804 #define AIPS_PACRC_WP5_MASK 0x200u
bogdanm 82:6473597d706e 805 #define AIPS_PACRC_WP5_SHIFT 9
bogdanm 82:6473597d706e 806 #define AIPS_PACRC_SP5_MASK 0x400u
bogdanm 82:6473597d706e 807 #define AIPS_PACRC_SP5_SHIFT 10
bogdanm 82:6473597d706e 808 #define AIPS_PACRC_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 809 #define AIPS_PACRC_TP4_SHIFT 12
bogdanm 82:6473597d706e 810 #define AIPS_PACRC_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 811 #define AIPS_PACRC_WP4_SHIFT 13
bogdanm 82:6473597d706e 812 #define AIPS_PACRC_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 813 #define AIPS_PACRC_SP4_SHIFT 14
bogdanm 82:6473597d706e 814 #define AIPS_PACRC_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 815 #define AIPS_PACRC_TP3_SHIFT 16
bogdanm 82:6473597d706e 816 #define AIPS_PACRC_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 817 #define AIPS_PACRC_WP3_SHIFT 17
bogdanm 82:6473597d706e 818 #define AIPS_PACRC_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 819 #define AIPS_PACRC_SP3_SHIFT 18
bogdanm 82:6473597d706e 820 #define AIPS_PACRC_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 821 #define AIPS_PACRC_TP2_SHIFT 20
bogdanm 82:6473597d706e 822 #define AIPS_PACRC_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 823 #define AIPS_PACRC_WP2_SHIFT 21
bogdanm 82:6473597d706e 824 #define AIPS_PACRC_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 825 #define AIPS_PACRC_SP2_SHIFT 22
bogdanm 82:6473597d706e 826 #define AIPS_PACRC_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 827 #define AIPS_PACRC_TP1_SHIFT 24
bogdanm 82:6473597d706e 828 #define AIPS_PACRC_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 829 #define AIPS_PACRC_WP1_SHIFT 25
bogdanm 82:6473597d706e 830 #define AIPS_PACRC_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 831 #define AIPS_PACRC_SP1_SHIFT 26
bogdanm 82:6473597d706e 832 #define AIPS_PACRC_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 833 #define AIPS_PACRC_TP0_SHIFT 28
bogdanm 82:6473597d706e 834 #define AIPS_PACRC_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 835 #define AIPS_PACRC_WP0_SHIFT 29
bogdanm 82:6473597d706e 836 #define AIPS_PACRC_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 837 #define AIPS_PACRC_SP0_SHIFT 30
bogdanm 82:6473597d706e 838 /* PACRD Bit Fields */
bogdanm 82:6473597d706e 839 #define AIPS_PACRD_TP7_MASK 0x1u
bogdanm 82:6473597d706e 840 #define AIPS_PACRD_TP7_SHIFT 0
bogdanm 82:6473597d706e 841 #define AIPS_PACRD_WP7_MASK 0x2u
bogdanm 82:6473597d706e 842 #define AIPS_PACRD_WP7_SHIFT 1
bogdanm 82:6473597d706e 843 #define AIPS_PACRD_SP7_MASK 0x4u
bogdanm 82:6473597d706e 844 #define AIPS_PACRD_SP7_SHIFT 2
bogdanm 82:6473597d706e 845 #define AIPS_PACRD_TP6_MASK 0x10u
bogdanm 82:6473597d706e 846 #define AIPS_PACRD_TP6_SHIFT 4
bogdanm 82:6473597d706e 847 #define AIPS_PACRD_WP6_MASK 0x20u
bogdanm 82:6473597d706e 848 #define AIPS_PACRD_WP6_SHIFT 5
bogdanm 82:6473597d706e 849 #define AIPS_PACRD_SP6_MASK 0x40u
bogdanm 82:6473597d706e 850 #define AIPS_PACRD_SP6_SHIFT 6
bogdanm 82:6473597d706e 851 #define AIPS_PACRD_TP5_MASK 0x100u
bogdanm 82:6473597d706e 852 #define AIPS_PACRD_TP5_SHIFT 8
bogdanm 82:6473597d706e 853 #define AIPS_PACRD_WP5_MASK 0x200u
bogdanm 82:6473597d706e 854 #define AIPS_PACRD_WP5_SHIFT 9
bogdanm 82:6473597d706e 855 #define AIPS_PACRD_SP5_MASK 0x400u
bogdanm 82:6473597d706e 856 #define AIPS_PACRD_SP5_SHIFT 10
bogdanm 82:6473597d706e 857 #define AIPS_PACRD_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 858 #define AIPS_PACRD_TP4_SHIFT 12
bogdanm 82:6473597d706e 859 #define AIPS_PACRD_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 860 #define AIPS_PACRD_WP4_SHIFT 13
bogdanm 82:6473597d706e 861 #define AIPS_PACRD_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 862 #define AIPS_PACRD_SP4_SHIFT 14
bogdanm 82:6473597d706e 863 #define AIPS_PACRD_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 864 #define AIPS_PACRD_TP3_SHIFT 16
bogdanm 82:6473597d706e 865 #define AIPS_PACRD_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 866 #define AIPS_PACRD_WP3_SHIFT 17
bogdanm 82:6473597d706e 867 #define AIPS_PACRD_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 868 #define AIPS_PACRD_SP3_SHIFT 18
bogdanm 82:6473597d706e 869 #define AIPS_PACRD_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 870 #define AIPS_PACRD_TP2_SHIFT 20
bogdanm 82:6473597d706e 871 #define AIPS_PACRD_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 872 #define AIPS_PACRD_WP2_SHIFT 21
bogdanm 82:6473597d706e 873 #define AIPS_PACRD_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 874 #define AIPS_PACRD_SP2_SHIFT 22
bogdanm 82:6473597d706e 875 #define AIPS_PACRD_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 876 #define AIPS_PACRD_TP1_SHIFT 24
bogdanm 82:6473597d706e 877 #define AIPS_PACRD_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 878 #define AIPS_PACRD_WP1_SHIFT 25
bogdanm 82:6473597d706e 879 #define AIPS_PACRD_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 880 #define AIPS_PACRD_SP1_SHIFT 26
bogdanm 82:6473597d706e 881 #define AIPS_PACRD_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 882 #define AIPS_PACRD_TP0_SHIFT 28
bogdanm 82:6473597d706e 883 #define AIPS_PACRD_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 884 #define AIPS_PACRD_WP0_SHIFT 29
bogdanm 82:6473597d706e 885 #define AIPS_PACRD_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 886 #define AIPS_PACRD_SP0_SHIFT 30
bogdanm 82:6473597d706e 887 /* PACRE Bit Fields */
bogdanm 82:6473597d706e 888 #define AIPS_PACRE_TP7_MASK 0x1u
bogdanm 82:6473597d706e 889 #define AIPS_PACRE_TP7_SHIFT 0
bogdanm 82:6473597d706e 890 #define AIPS_PACRE_WP7_MASK 0x2u
bogdanm 82:6473597d706e 891 #define AIPS_PACRE_WP7_SHIFT 1
bogdanm 82:6473597d706e 892 #define AIPS_PACRE_SP7_MASK 0x4u
bogdanm 82:6473597d706e 893 #define AIPS_PACRE_SP7_SHIFT 2
bogdanm 82:6473597d706e 894 #define AIPS_PACRE_TP6_MASK 0x10u
bogdanm 82:6473597d706e 895 #define AIPS_PACRE_TP6_SHIFT 4
bogdanm 82:6473597d706e 896 #define AIPS_PACRE_WP6_MASK 0x20u
bogdanm 82:6473597d706e 897 #define AIPS_PACRE_WP6_SHIFT 5
bogdanm 82:6473597d706e 898 #define AIPS_PACRE_SP6_MASK 0x40u
bogdanm 82:6473597d706e 899 #define AIPS_PACRE_SP6_SHIFT 6
bogdanm 82:6473597d706e 900 #define AIPS_PACRE_TP5_MASK 0x100u
bogdanm 82:6473597d706e 901 #define AIPS_PACRE_TP5_SHIFT 8
bogdanm 82:6473597d706e 902 #define AIPS_PACRE_WP5_MASK 0x200u
bogdanm 82:6473597d706e 903 #define AIPS_PACRE_WP5_SHIFT 9
bogdanm 82:6473597d706e 904 #define AIPS_PACRE_SP5_MASK 0x400u
bogdanm 82:6473597d706e 905 #define AIPS_PACRE_SP5_SHIFT 10
bogdanm 82:6473597d706e 906 #define AIPS_PACRE_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 907 #define AIPS_PACRE_TP4_SHIFT 12
bogdanm 82:6473597d706e 908 #define AIPS_PACRE_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 909 #define AIPS_PACRE_WP4_SHIFT 13
bogdanm 82:6473597d706e 910 #define AIPS_PACRE_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 911 #define AIPS_PACRE_SP4_SHIFT 14
bogdanm 82:6473597d706e 912 #define AIPS_PACRE_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 913 #define AIPS_PACRE_TP3_SHIFT 16
bogdanm 82:6473597d706e 914 #define AIPS_PACRE_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 915 #define AIPS_PACRE_WP3_SHIFT 17
bogdanm 82:6473597d706e 916 #define AIPS_PACRE_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 917 #define AIPS_PACRE_SP3_SHIFT 18
bogdanm 82:6473597d706e 918 #define AIPS_PACRE_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 919 #define AIPS_PACRE_TP2_SHIFT 20
bogdanm 82:6473597d706e 920 #define AIPS_PACRE_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 921 #define AIPS_PACRE_WP2_SHIFT 21
bogdanm 82:6473597d706e 922 #define AIPS_PACRE_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 923 #define AIPS_PACRE_SP2_SHIFT 22
bogdanm 82:6473597d706e 924 #define AIPS_PACRE_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 925 #define AIPS_PACRE_TP1_SHIFT 24
bogdanm 82:6473597d706e 926 #define AIPS_PACRE_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 927 #define AIPS_PACRE_WP1_SHIFT 25
bogdanm 82:6473597d706e 928 #define AIPS_PACRE_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 929 #define AIPS_PACRE_SP1_SHIFT 26
bogdanm 82:6473597d706e 930 #define AIPS_PACRE_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 931 #define AIPS_PACRE_TP0_SHIFT 28
bogdanm 82:6473597d706e 932 #define AIPS_PACRE_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 933 #define AIPS_PACRE_WP0_SHIFT 29
bogdanm 82:6473597d706e 934 #define AIPS_PACRE_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 935 #define AIPS_PACRE_SP0_SHIFT 30
bogdanm 82:6473597d706e 936 /* PACRF Bit Fields */
bogdanm 82:6473597d706e 937 #define AIPS_PACRF_TP7_MASK 0x1u
bogdanm 82:6473597d706e 938 #define AIPS_PACRF_TP7_SHIFT 0
bogdanm 82:6473597d706e 939 #define AIPS_PACRF_WP7_MASK 0x2u
bogdanm 82:6473597d706e 940 #define AIPS_PACRF_WP7_SHIFT 1
bogdanm 82:6473597d706e 941 #define AIPS_PACRF_SP7_MASK 0x4u
bogdanm 82:6473597d706e 942 #define AIPS_PACRF_SP7_SHIFT 2
bogdanm 82:6473597d706e 943 #define AIPS_PACRF_TP6_MASK 0x10u
bogdanm 82:6473597d706e 944 #define AIPS_PACRF_TP6_SHIFT 4
bogdanm 82:6473597d706e 945 #define AIPS_PACRF_WP6_MASK 0x20u
bogdanm 82:6473597d706e 946 #define AIPS_PACRF_WP6_SHIFT 5
bogdanm 82:6473597d706e 947 #define AIPS_PACRF_SP6_MASK 0x40u
bogdanm 82:6473597d706e 948 #define AIPS_PACRF_SP6_SHIFT 6
bogdanm 82:6473597d706e 949 #define AIPS_PACRF_TP5_MASK 0x100u
bogdanm 82:6473597d706e 950 #define AIPS_PACRF_TP5_SHIFT 8
bogdanm 82:6473597d706e 951 #define AIPS_PACRF_WP5_MASK 0x200u
bogdanm 82:6473597d706e 952 #define AIPS_PACRF_WP5_SHIFT 9
bogdanm 82:6473597d706e 953 #define AIPS_PACRF_SP5_MASK 0x400u
bogdanm 82:6473597d706e 954 #define AIPS_PACRF_SP5_SHIFT 10
bogdanm 82:6473597d706e 955 #define AIPS_PACRF_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 956 #define AIPS_PACRF_TP4_SHIFT 12
bogdanm 82:6473597d706e 957 #define AIPS_PACRF_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 958 #define AIPS_PACRF_WP4_SHIFT 13
bogdanm 82:6473597d706e 959 #define AIPS_PACRF_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 960 #define AIPS_PACRF_SP4_SHIFT 14
bogdanm 82:6473597d706e 961 #define AIPS_PACRF_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 962 #define AIPS_PACRF_TP3_SHIFT 16
bogdanm 82:6473597d706e 963 #define AIPS_PACRF_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 964 #define AIPS_PACRF_WP3_SHIFT 17
bogdanm 82:6473597d706e 965 #define AIPS_PACRF_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 966 #define AIPS_PACRF_SP3_SHIFT 18
bogdanm 82:6473597d706e 967 #define AIPS_PACRF_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 968 #define AIPS_PACRF_TP2_SHIFT 20
bogdanm 82:6473597d706e 969 #define AIPS_PACRF_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 970 #define AIPS_PACRF_WP2_SHIFT 21
bogdanm 82:6473597d706e 971 #define AIPS_PACRF_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 972 #define AIPS_PACRF_SP2_SHIFT 22
bogdanm 82:6473597d706e 973 #define AIPS_PACRF_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 974 #define AIPS_PACRF_TP1_SHIFT 24
bogdanm 82:6473597d706e 975 #define AIPS_PACRF_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 976 #define AIPS_PACRF_WP1_SHIFT 25
bogdanm 82:6473597d706e 977 #define AIPS_PACRF_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 978 #define AIPS_PACRF_SP1_SHIFT 26
bogdanm 82:6473597d706e 979 #define AIPS_PACRF_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 980 #define AIPS_PACRF_TP0_SHIFT 28
bogdanm 82:6473597d706e 981 #define AIPS_PACRF_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 982 #define AIPS_PACRF_WP0_SHIFT 29
bogdanm 82:6473597d706e 983 #define AIPS_PACRF_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 984 #define AIPS_PACRF_SP0_SHIFT 30
bogdanm 82:6473597d706e 985 /* PACRG Bit Fields */
bogdanm 82:6473597d706e 986 #define AIPS_PACRG_TP7_MASK 0x1u
bogdanm 82:6473597d706e 987 #define AIPS_PACRG_TP7_SHIFT 0
bogdanm 82:6473597d706e 988 #define AIPS_PACRG_WP7_MASK 0x2u
bogdanm 82:6473597d706e 989 #define AIPS_PACRG_WP7_SHIFT 1
bogdanm 82:6473597d706e 990 #define AIPS_PACRG_SP7_MASK 0x4u
bogdanm 82:6473597d706e 991 #define AIPS_PACRG_SP7_SHIFT 2
bogdanm 82:6473597d706e 992 #define AIPS_PACRG_TP6_MASK 0x10u
bogdanm 82:6473597d706e 993 #define AIPS_PACRG_TP6_SHIFT 4
bogdanm 82:6473597d706e 994 #define AIPS_PACRG_WP6_MASK 0x20u
bogdanm 82:6473597d706e 995 #define AIPS_PACRG_WP6_SHIFT 5
bogdanm 82:6473597d706e 996 #define AIPS_PACRG_SP6_MASK 0x40u
bogdanm 82:6473597d706e 997 #define AIPS_PACRG_SP6_SHIFT 6
bogdanm 82:6473597d706e 998 #define AIPS_PACRG_TP5_MASK 0x100u
bogdanm 82:6473597d706e 999 #define AIPS_PACRG_TP5_SHIFT 8
bogdanm 82:6473597d706e 1000 #define AIPS_PACRG_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1001 #define AIPS_PACRG_WP5_SHIFT 9
bogdanm 82:6473597d706e 1002 #define AIPS_PACRG_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1003 #define AIPS_PACRG_SP5_SHIFT 10
bogdanm 82:6473597d706e 1004 #define AIPS_PACRG_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1005 #define AIPS_PACRG_TP4_SHIFT 12
bogdanm 82:6473597d706e 1006 #define AIPS_PACRG_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1007 #define AIPS_PACRG_WP4_SHIFT 13
bogdanm 82:6473597d706e 1008 #define AIPS_PACRG_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1009 #define AIPS_PACRG_SP4_SHIFT 14
bogdanm 82:6473597d706e 1010 #define AIPS_PACRG_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1011 #define AIPS_PACRG_TP3_SHIFT 16
bogdanm 82:6473597d706e 1012 #define AIPS_PACRG_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1013 #define AIPS_PACRG_WP3_SHIFT 17
bogdanm 82:6473597d706e 1014 #define AIPS_PACRG_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1015 #define AIPS_PACRG_SP3_SHIFT 18
bogdanm 82:6473597d706e 1016 #define AIPS_PACRG_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1017 #define AIPS_PACRG_TP2_SHIFT 20
bogdanm 82:6473597d706e 1018 #define AIPS_PACRG_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1019 #define AIPS_PACRG_WP2_SHIFT 21
bogdanm 82:6473597d706e 1020 #define AIPS_PACRG_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1021 #define AIPS_PACRG_SP2_SHIFT 22
bogdanm 82:6473597d706e 1022 #define AIPS_PACRG_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1023 #define AIPS_PACRG_TP1_SHIFT 24
bogdanm 82:6473597d706e 1024 #define AIPS_PACRG_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1025 #define AIPS_PACRG_WP1_SHIFT 25
bogdanm 82:6473597d706e 1026 #define AIPS_PACRG_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1027 #define AIPS_PACRG_SP1_SHIFT 26
bogdanm 82:6473597d706e 1028 #define AIPS_PACRG_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1029 #define AIPS_PACRG_TP0_SHIFT 28
bogdanm 82:6473597d706e 1030 #define AIPS_PACRG_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1031 #define AIPS_PACRG_WP0_SHIFT 29
bogdanm 82:6473597d706e 1032 #define AIPS_PACRG_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1033 #define AIPS_PACRG_SP0_SHIFT 30
bogdanm 82:6473597d706e 1034 /* PACRH Bit Fields */
bogdanm 82:6473597d706e 1035 #define AIPS_PACRH_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1036 #define AIPS_PACRH_TP7_SHIFT 0
bogdanm 82:6473597d706e 1037 #define AIPS_PACRH_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1038 #define AIPS_PACRH_WP7_SHIFT 1
bogdanm 82:6473597d706e 1039 #define AIPS_PACRH_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1040 #define AIPS_PACRH_SP7_SHIFT 2
bogdanm 82:6473597d706e 1041 #define AIPS_PACRH_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1042 #define AIPS_PACRH_TP6_SHIFT 4
bogdanm 82:6473597d706e 1043 #define AIPS_PACRH_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1044 #define AIPS_PACRH_WP6_SHIFT 5
bogdanm 82:6473597d706e 1045 #define AIPS_PACRH_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1046 #define AIPS_PACRH_SP6_SHIFT 6
bogdanm 82:6473597d706e 1047 #define AIPS_PACRH_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1048 #define AIPS_PACRH_TP5_SHIFT 8
bogdanm 82:6473597d706e 1049 #define AIPS_PACRH_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1050 #define AIPS_PACRH_WP5_SHIFT 9
bogdanm 82:6473597d706e 1051 #define AIPS_PACRH_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1052 #define AIPS_PACRH_SP5_SHIFT 10
bogdanm 82:6473597d706e 1053 #define AIPS_PACRH_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1054 #define AIPS_PACRH_TP4_SHIFT 12
bogdanm 82:6473597d706e 1055 #define AIPS_PACRH_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1056 #define AIPS_PACRH_WP4_SHIFT 13
bogdanm 82:6473597d706e 1057 #define AIPS_PACRH_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1058 #define AIPS_PACRH_SP4_SHIFT 14
bogdanm 82:6473597d706e 1059 #define AIPS_PACRH_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1060 #define AIPS_PACRH_TP3_SHIFT 16
bogdanm 82:6473597d706e 1061 #define AIPS_PACRH_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1062 #define AIPS_PACRH_WP3_SHIFT 17
bogdanm 82:6473597d706e 1063 #define AIPS_PACRH_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1064 #define AIPS_PACRH_SP3_SHIFT 18
bogdanm 82:6473597d706e 1065 #define AIPS_PACRH_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1066 #define AIPS_PACRH_TP2_SHIFT 20
bogdanm 82:6473597d706e 1067 #define AIPS_PACRH_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1068 #define AIPS_PACRH_WP2_SHIFT 21
bogdanm 82:6473597d706e 1069 #define AIPS_PACRH_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1070 #define AIPS_PACRH_SP2_SHIFT 22
bogdanm 82:6473597d706e 1071 #define AIPS_PACRH_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1072 #define AIPS_PACRH_TP1_SHIFT 24
bogdanm 82:6473597d706e 1073 #define AIPS_PACRH_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1074 #define AIPS_PACRH_WP1_SHIFT 25
bogdanm 82:6473597d706e 1075 #define AIPS_PACRH_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1076 #define AIPS_PACRH_SP1_SHIFT 26
bogdanm 82:6473597d706e 1077 #define AIPS_PACRH_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1078 #define AIPS_PACRH_TP0_SHIFT 28
bogdanm 82:6473597d706e 1079 #define AIPS_PACRH_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1080 #define AIPS_PACRH_WP0_SHIFT 29
bogdanm 82:6473597d706e 1081 #define AIPS_PACRH_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1082 #define AIPS_PACRH_SP0_SHIFT 30
bogdanm 82:6473597d706e 1083 /* PACRI Bit Fields */
bogdanm 82:6473597d706e 1084 #define AIPS_PACRI_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1085 #define AIPS_PACRI_TP7_SHIFT 0
bogdanm 82:6473597d706e 1086 #define AIPS_PACRI_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1087 #define AIPS_PACRI_WP7_SHIFT 1
bogdanm 82:6473597d706e 1088 #define AIPS_PACRI_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1089 #define AIPS_PACRI_SP7_SHIFT 2
bogdanm 82:6473597d706e 1090 #define AIPS_PACRI_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1091 #define AIPS_PACRI_TP6_SHIFT 4
bogdanm 82:6473597d706e 1092 #define AIPS_PACRI_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1093 #define AIPS_PACRI_WP6_SHIFT 5
bogdanm 82:6473597d706e 1094 #define AIPS_PACRI_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1095 #define AIPS_PACRI_SP6_SHIFT 6
bogdanm 82:6473597d706e 1096 #define AIPS_PACRI_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1097 #define AIPS_PACRI_TP5_SHIFT 8
bogdanm 82:6473597d706e 1098 #define AIPS_PACRI_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1099 #define AIPS_PACRI_WP5_SHIFT 9
bogdanm 82:6473597d706e 1100 #define AIPS_PACRI_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1101 #define AIPS_PACRI_SP5_SHIFT 10
bogdanm 82:6473597d706e 1102 #define AIPS_PACRI_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1103 #define AIPS_PACRI_TP4_SHIFT 12
bogdanm 82:6473597d706e 1104 #define AIPS_PACRI_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1105 #define AIPS_PACRI_WP4_SHIFT 13
bogdanm 82:6473597d706e 1106 #define AIPS_PACRI_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1107 #define AIPS_PACRI_SP4_SHIFT 14
bogdanm 82:6473597d706e 1108 #define AIPS_PACRI_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1109 #define AIPS_PACRI_TP3_SHIFT 16
bogdanm 82:6473597d706e 1110 #define AIPS_PACRI_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1111 #define AIPS_PACRI_WP3_SHIFT 17
bogdanm 82:6473597d706e 1112 #define AIPS_PACRI_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1113 #define AIPS_PACRI_SP3_SHIFT 18
bogdanm 82:6473597d706e 1114 #define AIPS_PACRI_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1115 #define AIPS_PACRI_TP2_SHIFT 20
bogdanm 82:6473597d706e 1116 #define AIPS_PACRI_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1117 #define AIPS_PACRI_WP2_SHIFT 21
bogdanm 82:6473597d706e 1118 #define AIPS_PACRI_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1119 #define AIPS_PACRI_SP2_SHIFT 22
bogdanm 82:6473597d706e 1120 #define AIPS_PACRI_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1121 #define AIPS_PACRI_TP1_SHIFT 24
bogdanm 82:6473597d706e 1122 #define AIPS_PACRI_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1123 #define AIPS_PACRI_WP1_SHIFT 25
bogdanm 82:6473597d706e 1124 #define AIPS_PACRI_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1125 #define AIPS_PACRI_SP1_SHIFT 26
bogdanm 82:6473597d706e 1126 #define AIPS_PACRI_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1127 #define AIPS_PACRI_TP0_SHIFT 28
bogdanm 82:6473597d706e 1128 #define AIPS_PACRI_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1129 #define AIPS_PACRI_WP0_SHIFT 29
bogdanm 82:6473597d706e 1130 #define AIPS_PACRI_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1131 #define AIPS_PACRI_SP0_SHIFT 30
bogdanm 82:6473597d706e 1132 /* PACRJ Bit Fields */
bogdanm 82:6473597d706e 1133 #define AIPS_PACRJ_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1134 #define AIPS_PACRJ_TP7_SHIFT 0
bogdanm 82:6473597d706e 1135 #define AIPS_PACRJ_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1136 #define AIPS_PACRJ_WP7_SHIFT 1
bogdanm 82:6473597d706e 1137 #define AIPS_PACRJ_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1138 #define AIPS_PACRJ_SP7_SHIFT 2
bogdanm 82:6473597d706e 1139 #define AIPS_PACRJ_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1140 #define AIPS_PACRJ_TP6_SHIFT 4
bogdanm 82:6473597d706e 1141 #define AIPS_PACRJ_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1142 #define AIPS_PACRJ_WP6_SHIFT 5
bogdanm 82:6473597d706e 1143 #define AIPS_PACRJ_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1144 #define AIPS_PACRJ_SP6_SHIFT 6
bogdanm 82:6473597d706e 1145 #define AIPS_PACRJ_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1146 #define AIPS_PACRJ_TP5_SHIFT 8
bogdanm 82:6473597d706e 1147 #define AIPS_PACRJ_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1148 #define AIPS_PACRJ_WP5_SHIFT 9
bogdanm 82:6473597d706e 1149 #define AIPS_PACRJ_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1150 #define AIPS_PACRJ_SP5_SHIFT 10
bogdanm 82:6473597d706e 1151 #define AIPS_PACRJ_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1152 #define AIPS_PACRJ_TP4_SHIFT 12
bogdanm 82:6473597d706e 1153 #define AIPS_PACRJ_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1154 #define AIPS_PACRJ_WP4_SHIFT 13
bogdanm 82:6473597d706e 1155 #define AIPS_PACRJ_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1156 #define AIPS_PACRJ_SP4_SHIFT 14
bogdanm 82:6473597d706e 1157 #define AIPS_PACRJ_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1158 #define AIPS_PACRJ_TP3_SHIFT 16
bogdanm 82:6473597d706e 1159 #define AIPS_PACRJ_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1160 #define AIPS_PACRJ_WP3_SHIFT 17
bogdanm 82:6473597d706e 1161 #define AIPS_PACRJ_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1162 #define AIPS_PACRJ_SP3_SHIFT 18
bogdanm 82:6473597d706e 1163 #define AIPS_PACRJ_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1164 #define AIPS_PACRJ_TP2_SHIFT 20
bogdanm 82:6473597d706e 1165 #define AIPS_PACRJ_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1166 #define AIPS_PACRJ_WP2_SHIFT 21
bogdanm 82:6473597d706e 1167 #define AIPS_PACRJ_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1168 #define AIPS_PACRJ_SP2_SHIFT 22
bogdanm 82:6473597d706e 1169 #define AIPS_PACRJ_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1170 #define AIPS_PACRJ_TP1_SHIFT 24
bogdanm 82:6473597d706e 1171 #define AIPS_PACRJ_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1172 #define AIPS_PACRJ_WP1_SHIFT 25
bogdanm 82:6473597d706e 1173 #define AIPS_PACRJ_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1174 #define AIPS_PACRJ_SP1_SHIFT 26
bogdanm 82:6473597d706e 1175 #define AIPS_PACRJ_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1176 #define AIPS_PACRJ_TP0_SHIFT 28
bogdanm 82:6473597d706e 1177 #define AIPS_PACRJ_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1178 #define AIPS_PACRJ_WP0_SHIFT 29
bogdanm 82:6473597d706e 1179 #define AIPS_PACRJ_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1180 #define AIPS_PACRJ_SP0_SHIFT 30
bogdanm 82:6473597d706e 1181 /* PACRK Bit Fields */
bogdanm 82:6473597d706e 1182 #define AIPS_PACRK_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1183 #define AIPS_PACRK_TP7_SHIFT 0
bogdanm 82:6473597d706e 1184 #define AIPS_PACRK_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1185 #define AIPS_PACRK_WP7_SHIFT 1
bogdanm 82:6473597d706e 1186 #define AIPS_PACRK_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1187 #define AIPS_PACRK_SP7_SHIFT 2
bogdanm 82:6473597d706e 1188 #define AIPS_PACRK_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1189 #define AIPS_PACRK_TP6_SHIFT 4
bogdanm 82:6473597d706e 1190 #define AIPS_PACRK_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1191 #define AIPS_PACRK_WP6_SHIFT 5
bogdanm 82:6473597d706e 1192 #define AIPS_PACRK_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1193 #define AIPS_PACRK_SP6_SHIFT 6
bogdanm 82:6473597d706e 1194 #define AIPS_PACRK_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1195 #define AIPS_PACRK_TP5_SHIFT 8
bogdanm 82:6473597d706e 1196 #define AIPS_PACRK_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1197 #define AIPS_PACRK_WP5_SHIFT 9
bogdanm 82:6473597d706e 1198 #define AIPS_PACRK_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1199 #define AIPS_PACRK_SP5_SHIFT 10
bogdanm 82:6473597d706e 1200 #define AIPS_PACRK_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1201 #define AIPS_PACRK_TP4_SHIFT 12
bogdanm 82:6473597d706e 1202 #define AIPS_PACRK_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1203 #define AIPS_PACRK_WP4_SHIFT 13
bogdanm 82:6473597d706e 1204 #define AIPS_PACRK_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1205 #define AIPS_PACRK_SP4_SHIFT 14
bogdanm 82:6473597d706e 1206 #define AIPS_PACRK_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1207 #define AIPS_PACRK_TP3_SHIFT 16
bogdanm 82:6473597d706e 1208 #define AIPS_PACRK_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1209 #define AIPS_PACRK_WP3_SHIFT 17
bogdanm 82:6473597d706e 1210 #define AIPS_PACRK_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1211 #define AIPS_PACRK_SP3_SHIFT 18
bogdanm 82:6473597d706e 1212 #define AIPS_PACRK_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1213 #define AIPS_PACRK_TP2_SHIFT 20
bogdanm 82:6473597d706e 1214 #define AIPS_PACRK_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1215 #define AIPS_PACRK_WP2_SHIFT 21
bogdanm 82:6473597d706e 1216 #define AIPS_PACRK_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1217 #define AIPS_PACRK_SP2_SHIFT 22
bogdanm 82:6473597d706e 1218 #define AIPS_PACRK_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1219 #define AIPS_PACRK_TP1_SHIFT 24
bogdanm 82:6473597d706e 1220 #define AIPS_PACRK_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1221 #define AIPS_PACRK_WP1_SHIFT 25
bogdanm 82:6473597d706e 1222 #define AIPS_PACRK_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1223 #define AIPS_PACRK_SP1_SHIFT 26
bogdanm 82:6473597d706e 1224 #define AIPS_PACRK_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1225 #define AIPS_PACRK_TP0_SHIFT 28
bogdanm 82:6473597d706e 1226 #define AIPS_PACRK_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1227 #define AIPS_PACRK_WP0_SHIFT 29
bogdanm 82:6473597d706e 1228 #define AIPS_PACRK_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1229 #define AIPS_PACRK_SP0_SHIFT 30
bogdanm 82:6473597d706e 1230 /* PACRL Bit Fields */
bogdanm 82:6473597d706e 1231 #define AIPS_PACRL_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1232 #define AIPS_PACRL_TP7_SHIFT 0
bogdanm 82:6473597d706e 1233 #define AIPS_PACRL_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1234 #define AIPS_PACRL_WP7_SHIFT 1
bogdanm 82:6473597d706e 1235 #define AIPS_PACRL_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1236 #define AIPS_PACRL_SP7_SHIFT 2
bogdanm 82:6473597d706e 1237 #define AIPS_PACRL_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1238 #define AIPS_PACRL_TP6_SHIFT 4
bogdanm 82:6473597d706e 1239 #define AIPS_PACRL_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1240 #define AIPS_PACRL_WP6_SHIFT 5
bogdanm 82:6473597d706e 1241 #define AIPS_PACRL_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1242 #define AIPS_PACRL_SP6_SHIFT 6
bogdanm 82:6473597d706e 1243 #define AIPS_PACRL_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1244 #define AIPS_PACRL_TP5_SHIFT 8
bogdanm 82:6473597d706e 1245 #define AIPS_PACRL_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1246 #define AIPS_PACRL_WP5_SHIFT 9
bogdanm 82:6473597d706e 1247 #define AIPS_PACRL_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1248 #define AIPS_PACRL_SP5_SHIFT 10
bogdanm 82:6473597d706e 1249 #define AIPS_PACRL_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1250 #define AIPS_PACRL_TP4_SHIFT 12
bogdanm 82:6473597d706e 1251 #define AIPS_PACRL_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1252 #define AIPS_PACRL_WP4_SHIFT 13
bogdanm 82:6473597d706e 1253 #define AIPS_PACRL_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1254 #define AIPS_PACRL_SP4_SHIFT 14
bogdanm 82:6473597d706e 1255 #define AIPS_PACRL_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1256 #define AIPS_PACRL_TP3_SHIFT 16
bogdanm 82:6473597d706e 1257 #define AIPS_PACRL_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1258 #define AIPS_PACRL_WP3_SHIFT 17
bogdanm 82:6473597d706e 1259 #define AIPS_PACRL_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1260 #define AIPS_PACRL_SP3_SHIFT 18
bogdanm 82:6473597d706e 1261 #define AIPS_PACRL_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1262 #define AIPS_PACRL_TP2_SHIFT 20
bogdanm 82:6473597d706e 1263 #define AIPS_PACRL_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1264 #define AIPS_PACRL_WP2_SHIFT 21
bogdanm 82:6473597d706e 1265 #define AIPS_PACRL_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1266 #define AIPS_PACRL_SP2_SHIFT 22
bogdanm 82:6473597d706e 1267 #define AIPS_PACRL_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1268 #define AIPS_PACRL_TP1_SHIFT 24
bogdanm 82:6473597d706e 1269 #define AIPS_PACRL_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1270 #define AIPS_PACRL_WP1_SHIFT 25
bogdanm 82:6473597d706e 1271 #define AIPS_PACRL_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1272 #define AIPS_PACRL_SP1_SHIFT 26
bogdanm 82:6473597d706e 1273 #define AIPS_PACRL_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1274 #define AIPS_PACRL_TP0_SHIFT 28
bogdanm 82:6473597d706e 1275 #define AIPS_PACRL_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1276 #define AIPS_PACRL_WP0_SHIFT 29
bogdanm 82:6473597d706e 1277 #define AIPS_PACRL_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1278 #define AIPS_PACRL_SP0_SHIFT 30
bogdanm 82:6473597d706e 1279 /* PACRM Bit Fields */
bogdanm 82:6473597d706e 1280 #define AIPS_PACRM_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1281 #define AIPS_PACRM_TP7_SHIFT 0
bogdanm 82:6473597d706e 1282 #define AIPS_PACRM_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1283 #define AIPS_PACRM_WP7_SHIFT 1
bogdanm 82:6473597d706e 1284 #define AIPS_PACRM_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1285 #define AIPS_PACRM_SP7_SHIFT 2
bogdanm 82:6473597d706e 1286 #define AIPS_PACRM_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1287 #define AIPS_PACRM_TP6_SHIFT 4
bogdanm 82:6473597d706e 1288 #define AIPS_PACRM_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1289 #define AIPS_PACRM_WP6_SHIFT 5
bogdanm 82:6473597d706e 1290 #define AIPS_PACRM_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1291 #define AIPS_PACRM_SP6_SHIFT 6
bogdanm 82:6473597d706e 1292 #define AIPS_PACRM_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1293 #define AIPS_PACRM_TP5_SHIFT 8
bogdanm 82:6473597d706e 1294 #define AIPS_PACRM_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1295 #define AIPS_PACRM_WP5_SHIFT 9
bogdanm 82:6473597d706e 1296 #define AIPS_PACRM_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1297 #define AIPS_PACRM_SP5_SHIFT 10
bogdanm 82:6473597d706e 1298 #define AIPS_PACRM_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1299 #define AIPS_PACRM_TP4_SHIFT 12
bogdanm 82:6473597d706e 1300 #define AIPS_PACRM_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1301 #define AIPS_PACRM_WP4_SHIFT 13
bogdanm 82:6473597d706e 1302 #define AIPS_PACRM_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1303 #define AIPS_PACRM_SP4_SHIFT 14
bogdanm 82:6473597d706e 1304 #define AIPS_PACRM_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1305 #define AIPS_PACRM_TP3_SHIFT 16
bogdanm 82:6473597d706e 1306 #define AIPS_PACRM_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1307 #define AIPS_PACRM_WP3_SHIFT 17
bogdanm 82:6473597d706e 1308 #define AIPS_PACRM_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1309 #define AIPS_PACRM_SP3_SHIFT 18
bogdanm 82:6473597d706e 1310 #define AIPS_PACRM_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1311 #define AIPS_PACRM_TP2_SHIFT 20
bogdanm 82:6473597d706e 1312 #define AIPS_PACRM_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1313 #define AIPS_PACRM_WP2_SHIFT 21
bogdanm 82:6473597d706e 1314 #define AIPS_PACRM_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1315 #define AIPS_PACRM_SP2_SHIFT 22
bogdanm 82:6473597d706e 1316 #define AIPS_PACRM_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1317 #define AIPS_PACRM_TP1_SHIFT 24
bogdanm 82:6473597d706e 1318 #define AIPS_PACRM_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1319 #define AIPS_PACRM_WP1_SHIFT 25
bogdanm 82:6473597d706e 1320 #define AIPS_PACRM_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1321 #define AIPS_PACRM_SP1_SHIFT 26
bogdanm 82:6473597d706e 1322 #define AIPS_PACRM_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1323 #define AIPS_PACRM_TP0_SHIFT 28
bogdanm 82:6473597d706e 1324 #define AIPS_PACRM_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1325 #define AIPS_PACRM_WP0_SHIFT 29
bogdanm 82:6473597d706e 1326 #define AIPS_PACRM_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1327 #define AIPS_PACRM_SP0_SHIFT 30
bogdanm 82:6473597d706e 1328 /* PACRN Bit Fields */
bogdanm 82:6473597d706e 1329 #define AIPS_PACRN_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1330 #define AIPS_PACRN_TP7_SHIFT 0
bogdanm 82:6473597d706e 1331 #define AIPS_PACRN_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1332 #define AIPS_PACRN_WP7_SHIFT 1
bogdanm 82:6473597d706e 1333 #define AIPS_PACRN_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1334 #define AIPS_PACRN_SP7_SHIFT 2
bogdanm 82:6473597d706e 1335 #define AIPS_PACRN_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1336 #define AIPS_PACRN_TP6_SHIFT 4
bogdanm 82:6473597d706e 1337 #define AIPS_PACRN_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1338 #define AIPS_PACRN_WP6_SHIFT 5
bogdanm 82:6473597d706e 1339 #define AIPS_PACRN_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1340 #define AIPS_PACRN_SP6_SHIFT 6
bogdanm 82:6473597d706e 1341 #define AIPS_PACRN_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1342 #define AIPS_PACRN_TP5_SHIFT 8
bogdanm 82:6473597d706e 1343 #define AIPS_PACRN_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1344 #define AIPS_PACRN_WP5_SHIFT 9
bogdanm 82:6473597d706e 1345 #define AIPS_PACRN_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1346 #define AIPS_PACRN_SP5_SHIFT 10
bogdanm 82:6473597d706e 1347 #define AIPS_PACRN_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1348 #define AIPS_PACRN_TP4_SHIFT 12
bogdanm 82:6473597d706e 1349 #define AIPS_PACRN_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1350 #define AIPS_PACRN_WP4_SHIFT 13
bogdanm 82:6473597d706e 1351 #define AIPS_PACRN_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1352 #define AIPS_PACRN_SP4_SHIFT 14
bogdanm 82:6473597d706e 1353 #define AIPS_PACRN_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1354 #define AIPS_PACRN_TP3_SHIFT 16
bogdanm 82:6473597d706e 1355 #define AIPS_PACRN_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1356 #define AIPS_PACRN_WP3_SHIFT 17
bogdanm 82:6473597d706e 1357 #define AIPS_PACRN_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1358 #define AIPS_PACRN_SP3_SHIFT 18
bogdanm 82:6473597d706e 1359 #define AIPS_PACRN_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1360 #define AIPS_PACRN_TP2_SHIFT 20
bogdanm 82:6473597d706e 1361 #define AIPS_PACRN_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1362 #define AIPS_PACRN_WP2_SHIFT 21
bogdanm 82:6473597d706e 1363 #define AIPS_PACRN_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1364 #define AIPS_PACRN_SP2_SHIFT 22
bogdanm 82:6473597d706e 1365 #define AIPS_PACRN_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1366 #define AIPS_PACRN_TP1_SHIFT 24
bogdanm 82:6473597d706e 1367 #define AIPS_PACRN_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1368 #define AIPS_PACRN_WP1_SHIFT 25
bogdanm 82:6473597d706e 1369 #define AIPS_PACRN_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1370 #define AIPS_PACRN_SP1_SHIFT 26
bogdanm 82:6473597d706e 1371 #define AIPS_PACRN_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1372 #define AIPS_PACRN_TP0_SHIFT 28
bogdanm 82:6473597d706e 1373 #define AIPS_PACRN_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1374 #define AIPS_PACRN_WP0_SHIFT 29
bogdanm 82:6473597d706e 1375 #define AIPS_PACRN_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1376 #define AIPS_PACRN_SP0_SHIFT 30
bogdanm 82:6473597d706e 1377 /* PACRO Bit Fields */
bogdanm 82:6473597d706e 1378 #define AIPS_PACRO_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1379 #define AIPS_PACRO_TP7_SHIFT 0
bogdanm 82:6473597d706e 1380 #define AIPS_PACRO_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1381 #define AIPS_PACRO_WP7_SHIFT 1
bogdanm 82:6473597d706e 1382 #define AIPS_PACRO_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1383 #define AIPS_PACRO_SP7_SHIFT 2
bogdanm 82:6473597d706e 1384 #define AIPS_PACRO_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1385 #define AIPS_PACRO_TP6_SHIFT 4
bogdanm 82:6473597d706e 1386 #define AIPS_PACRO_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1387 #define AIPS_PACRO_WP6_SHIFT 5
bogdanm 82:6473597d706e 1388 #define AIPS_PACRO_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1389 #define AIPS_PACRO_SP6_SHIFT 6
bogdanm 82:6473597d706e 1390 #define AIPS_PACRO_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1391 #define AIPS_PACRO_TP5_SHIFT 8
bogdanm 82:6473597d706e 1392 #define AIPS_PACRO_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1393 #define AIPS_PACRO_WP5_SHIFT 9
bogdanm 82:6473597d706e 1394 #define AIPS_PACRO_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1395 #define AIPS_PACRO_SP5_SHIFT 10
bogdanm 82:6473597d706e 1396 #define AIPS_PACRO_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1397 #define AIPS_PACRO_TP4_SHIFT 12
bogdanm 82:6473597d706e 1398 #define AIPS_PACRO_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1399 #define AIPS_PACRO_WP4_SHIFT 13
bogdanm 82:6473597d706e 1400 #define AIPS_PACRO_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1401 #define AIPS_PACRO_SP4_SHIFT 14
bogdanm 82:6473597d706e 1402 #define AIPS_PACRO_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1403 #define AIPS_PACRO_TP3_SHIFT 16
bogdanm 82:6473597d706e 1404 #define AIPS_PACRO_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1405 #define AIPS_PACRO_WP3_SHIFT 17
bogdanm 82:6473597d706e 1406 #define AIPS_PACRO_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1407 #define AIPS_PACRO_SP3_SHIFT 18
bogdanm 82:6473597d706e 1408 #define AIPS_PACRO_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1409 #define AIPS_PACRO_TP2_SHIFT 20
bogdanm 82:6473597d706e 1410 #define AIPS_PACRO_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1411 #define AIPS_PACRO_WP2_SHIFT 21
bogdanm 82:6473597d706e 1412 #define AIPS_PACRO_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1413 #define AIPS_PACRO_SP2_SHIFT 22
bogdanm 82:6473597d706e 1414 #define AIPS_PACRO_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1415 #define AIPS_PACRO_TP1_SHIFT 24
bogdanm 82:6473597d706e 1416 #define AIPS_PACRO_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1417 #define AIPS_PACRO_WP1_SHIFT 25
bogdanm 82:6473597d706e 1418 #define AIPS_PACRO_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1419 #define AIPS_PACRO_SP1_SHIFT 26
bogdanm 82:6473597d706e 1420 #define AIPS_PACRO_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1421 #define AIPS_PACRO_TP0_SHIFT 28
bogdanm 82:6473597d706e 1422 #define AIPS_PACRO_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1423 #define AIPS_PACRO_WP0_SHIFT 29
bogdanm 82:6473597d706e 1424 #define AIPS_PACRO_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1425 #define AIPS_PACRO_SP0_SHIFT 30
bogdanm 82:6473597d706e 1426 /* PACRP Bit Fields */
bogdanm 82:6473597d706e 1427 #define AIPS_PACRP_TP7_MASK 0x1u
bogdanm 82:6473597d706e 1428 #define AIPS_PACRP_TP7_SHIFT 0
bogdanm 82:6473597d706e 1429 #define AIPS_PACRP_WP7_MASK 0x2u
bogdanm 82:6473597d706e 1430 #define AIPS_PACRP_WP7_SHIFT 1
bogdanm 82:6473597d706e 1431 #define AIPS_PACRP_SP7_MASK 0x4u
bogdanm 82:6473597d706e 1432 #define AIPS_PACRP_SP7_SHIFT 2
bogdanm 82:6473597d706e 1433 #define AIPS_PACRP_TP6_MASK 0x10u
bogdanm 82:6473597d706e 1434 #define AIPS_PACRP_TP6_SHIFT 4
bogdanm 82:6473597d706e 1435 #define AIPS_PACRP_WP6_MASK 0x20u
bogdanm 82:6473597d706e 1436 #define AIPS_PACRP_WP6_SHIFT 5
bogdanm 82:6473597d706e 1437 #define AIPS_PACRP_SP6_MASK 0x40u
bogdanm 82:6473597d706e 1438 #define AIPS_PACRP_SP6_SHIFT 6
bogdanm 82:6473597d706e 1439 #define AIPS_PACRP_TP5_MASK 0x100u
bogdanm 82:6473597d706e 1440 #define AIPS_PACRP_TP5_SHIFT 8
bogdanm 82:6473597d706e 1441 #define AIPS_PACRP_WP5_MASK 0x200u
bogdanm 82:6473597d706e 1442 #define AIPS_PACRP_WP5_SHIFT 9
bogdanm 82:6473597d706e 1443 #define AIPS_PACRP_SP5_MASK 0x400u
bogdanm 82:6473597d706e 1444 #define AIPS_PACRP_SP5_SHIFT 10
bogdanm 82:6473597d706e 1445 #define AIPS_PACRP_TP4_MASK 0x1000u
bogdanm 82:6473597d706e 1446 #define AIPS_PACRP_TP4_SHIFT 12
bogdanm 82:6473597d706e 1447 #define AIPS_PACRP_WP4_MASK 0x2000u
bogdanm 82:6473597d706e 1448 #define AIPS_PACRP_WP4_SHIFT 13
bogdanm 82:6473597d706e 1449 #define AIPS_PACRP_SP4_MASK 0x4000u
bogdanm 82:6473597d706e 1450 #define AIPS_PACRP_SP4_SHIFT 14
bogdanm 82:6473597d706e 1451 #define AIPS_PACRP_TP3_MASK 0x10000u
bogdanm 82:6473597d706e 1452 #define AIPS_PACRP_TP3_SHIFT 16
bogdanm 82:6473597d706e 1453 #define AIPS_PACRP_WP3_MASK 0x20000u
bogdanm 82:6473597d706e 1454 #define AIPS_PACRP_WP3_SHIFT 17
bogdanm 82:6473597d706e 1455 #define AIPS_PACRP_SP3_MASK 0x40000u
bogdanm 82:6473597d706e 1456 #define AIPS_PACRP_SP3_SHIFT 18
bogdanm 82:6473597d706e 1457 #define AIPS_PACRP_TP2_MASK 0x100000u
bogdanm 82:6473597d706e 1458 #define AIPS_PACRP_TP2_SHIFT 20
bogdanm 82:6473597d706e 1459 #define AIPS_PACRP_WP2_MASK 0x200000u
bogdanm 82:6473597d706e 1460 #define AIPS_PACRP_WP2_SHIFT 21
bogdanm 82:6473597d706e 1461 #define AIPS_PACRP_SP2_MASK 0x400000u
bogdanm 82:6473597d706e 1462 #define AIPS_PACRP_SP2_SHIFT 22
bogdanm 82:6473597d706e 1463 #define AIPS_PACRP_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1464 #define AIPS_PACRP_TP1_SHIFT 24
bogdanm 82:6473597d706e 1465 #define AIPS_PACRP_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1466 #define AIPS_PACRP_WP1_SHIFT 25
bogdanm 82:6473597d706e 1467 #define AIPS_PACRP_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1468 #define AIPS_PACRP_SP1_SHIFT 26
bogdanm 82:6473597d706e 1469 #define AIPS_PACRP_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1470 #define AIPS_PACRP_TP0_SHIFT 28
bogdanm 82:6473597d706e 1471 #define AIPS_PACRP_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1472 #define AIPS_PACRP_WP0_SHIFT 29
bogdanm 82:6473597d706e 1473 #define AIPS_PACRP_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1474 #define AIPS_PACRP_SP0_SHIFT 30
bogdanm 82:6473597d706e 1475 /* PACRU Bit Fields */
bogdanm 82:6473597d706e 1476 #define AIPS_PACRU_TP1_MASK 0x1000000u
bogdanm 82:6473597d706e 1477 #define AIPS_PACRU_TP1_SHIFT 24
bogdanm 82:6473597d706e 1478 #define AIPS_PACRU_WP1_MASK 0x2000000u
bogdanm 82:6473597d706e 1479 #define AIPS_PACRU_WP1_SHIFT 25
bogdanm 82:6473597d706e 1480 #define AIPS_PACRU_SP1_MASK 0x4000000u
bogdanm 82:6473597d706e 1481 #define AIPS_PACRU_SP1_SHIFT 26
bogdanm 82:6473597d706e 1482 #define AIPS_PACRU_TP0_MASK 0x10000000u
bogdanm 82:6473597d706e 1483 #define AIPS_PACRU_TP0_SHIFT 28
bogdanm 82:6473597d706e 1484 #define AIPS_PACRU_WP0_MASK 0x20000000u
bogdanm 82:6473597d706e 1485 #define AIPS_PACRU_WP0_SHIFT 29
bogdanm 82:6473597d706e 1486 #define AIPS_PACRU_SP0_MASK 0x40000000u
bogdanm 82:6473597d706e 1487 #define AIPS_PACRU_SP0_SHIFT 30
bogdanm 82:6473597d706e 1488
bogdanm 82:6473597d706e 1489 /*!
bogdanm 82:6473597d706e 1490 * @}
bogdanm 82:6473597d706e 1491 */ /* end of group AIPS_Register_Masks */
bogdanm 82:6473597d706e 1492
bogdanm 82:6473597d706e 1493
bogdanm 82:6473597d706e 1494 /* AIPS - Peripheral instance base addresses */
bogdanm 82:6473597d706e 1495 /** Peripheral AIPS0 base address */
bogdanm 82:6473597d706e 1496 #define AIPS0_BASE (0x40000000u)
bogdanm 82:6473597d706e 1497 /** Peripheral AIPS0 base pointer */
bogdanm 82:6473597d706e 1498 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
bogdanm 82:6473597d706e 1499 #define AIPS0_BASE_PTR (AIPS0)
bogdanm 82:6473597d706e 1500 /** Peripheral AIPS1 base address */
bogdanm 82:6473597d706e 1501 #define AIPS1_BASE (0x40080000u)
bogdanm 82:6473597d706e 1502 /** Peripheral AIPS1 base pointer */
bogdanm 82:6473597d706e 1503 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
bogdanm 82:6473597d706e 1504 #define AIPS1_BASE_PTR (AIPS1)
bogdanm 82:6473597d706e 1505 /** Array initializer of AIPS peripheral base pointers */
bogdanm 82:6473597d706e 1506 #define AIPS_BASES { AIPS0, AIPS1 }
bogdanm 82:6473597d706e 1507
bogdanm 82:6473597d706e 1508 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 1509 -- AIPS - Register accessor macros
bogdanm 82:6473597d706e 1510 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 1511
bogdanm 82:6473597d706e 1512 /*!
bogdanm 82:6473597d706e 1513 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
bogdanm 82:6473597d706e 1514 * @{
bogdanm 82:6473597d706e 1515 */
bogdanm 82:6473597d706e 1516
bogdanm 82:6473597d706e 1517
bogdanm 82:6473597d706e 1518 /* AIPS - Register instance definitions */
bogdanm 82:6473597d706e 1519 /* AIPS0 */
bogdanm 82:6473597d706e 1520 #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
bogdanm 82:6473597d706e 1521 #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
bogdanm 82:6473597d706e 1522 #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
bogdanm 82:6473597d706e 1523 #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
bogdanm 82:6473597d706e 1524 #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
bogdanm 82:6473597d706e 1525 #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
bogdanm 82:6473597d706e 1526 #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
bogdanm 82:6473597d706e 1527 #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
bogdanm 82:6473597d706e 1528 #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
bogdanm 82:6473597d706e 1529 #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
bogdanm 82:6473597d706e 1530 #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
bogdanm 82:6473597d706e 1531 #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
bogdanm 82:6473597d706e 1532 #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
bogdanm 82:6473597d706e 1533 #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
bogdanm 82:6473597d706e 1534 #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
bogdanm 82:6473597d706e 1535 #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
bogdanm 82:6473597d706e 1536 #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
bogdanm 82:6473597d706e 1537 #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
bogdanm 82:6473597d706e 1538 /* AIPS1 */
bogdanm 82:6473597d706e 1539 #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
bogdanm 82:6473597d706e 1540 #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
bogdanm 82:6473597d706e 1541 #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
bogdanm 82:6473597d706e 1542 #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
bogdanm 82:6473597d706e 1543 #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
bogdanm 82:6473597d706e 1544 #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
bogdanm 82:6473597d706e 1545 #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
bogdanm 82:6473597d706e 1546 #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
bogdanm 82:6473597d706e 1547 #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
bogdanm 82:6473597d706e 1548 #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
bogdanm 82:6473597d706e 1549 #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
bogdanm 82:6473597d706e 1550 #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
bogdanm 82:6473597d706e 1551 #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
bogdanm 82:6473597d706e 1552 #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
bogdanm 82:6473597d706e 1553 #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
bogdanm 82:6473597d706e 1554 #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
bogdanm 82:6473597d706e 1555 #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
bogdanm 82:6473597d706e 1556 #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
bogdanm 82:6473597d706e 1557
bogdanm 82:6473597d706e 1558 /*!
bogdanm 82:6473597d706e 1559 * @}
bogdanm 82:6473597d706e 1560 */ /* end of group AIPS_Register_Accessor_Macros */
bogdanm 82:6473597d706e 1561
bogdanm 82:6473597d706e 1562
bogdanm 82:6473597d706e 1563 /*!
bogdanm 82:6473597d706e 1564 * @}
bogdanm 82:6473597d706e 1565 */ /* end of group AIPS_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 1566
bogdanm 82:6473597d706e 1567
bogdanm 82:6473597d706e 1568 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 1569 -- AXBS Peripheral Access Layer
bogdanm 82:6473597d706e 1570 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 1571
bogdanm 82:6473597d706e 1572 /*!
bogdanm 82:6473597d706e 1573 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
bogdanm 82:6473597d706e 1574 * @{
bogdanm 82:6473597d706e 1575 */
bogdanm 82:6473597d706e 1576
bogdanm 82:6473597d706e 1577 /** AXBS - Register Layout Typedef */
bogdanm 82:6473597d706e 1578 typedef struct {
bogdanm 82:6473597d706e 1579 struct { /* offset: 0x0, array step: 0x100 */
bogdanm 82:6473597d706e 1580 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
bogdanm 82:6473597d706e 1581 uint8_t RESERVED_0[12];
bogdanm 82:6473597d706e 1582 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
bogdanm 82:6473597d706e 1583 uint8_t RESERVED_1[236];
bogdanm 82:6473597d706e 1584 } SLAVE[5];
bogdanm 82:6473597d706e 1585 uint8_t RESERVED_0[768];
bogdanm 82:6473597d706e 1586 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
bogdanm 82:6473597d706e 1587 uint8_t RESERVED_1[252];
bogdanm 82:6473597d706e 1588 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
bogdanm 82:6473597d706e 1589 uint8_t RESERVED_2[252];
bogdanm 82:6473597d706e 1590 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
bogdanm 82:6473597d706e 1591 uint8_t RESERVED_3[252];
bogdanm 82:6473597d706e 1592 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
bogdanm 82:6473597d706e 1593 uint8_t RESERVED_4[252];
bogdanm 82:6473597d706e 1594 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
bogdanm 82:6473597d706e 1595 uint8_t RESERVED_5[252];
bogdanm 82:6473597d706e 1596 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
bogdanm 82:6473597d706e 1597 } AXBS_Type, *AXBS_MemMapPtr;
bogdanm 82:6473597d706e 1598
bogdanm 82:6473597d706e 1599 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 1600 -- AXBS - Register accessor macros
bogdanm 82:6473597d706e 1601 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 1602
bogdanm 82:6473597d706e 1603 /*!
bogdanm 82:6473597d706e 1604 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
bogdanm 82:6473597d706e 1605 * @{
bogdanm 82:6473597d706e 1606 */
bogdanm 82:6473597d706e 1607
bogdanm 82:6473597d706e 1608
bogdanm 82:6473597d706e 1609 /* AXBS - Register accessors */
bogdanm 82:6473597d706e 1610 #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
bogdanm 82:6473597d706e 1611 #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
bogdanm 82:6473597d706e 1612 #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
bogdanm 82:6473597d706e 1613 #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
bogdanm 82:6473597d706e 1614 #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
bogdanm 82:6473597d706e 1615 #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
bogdanm 82:6473597d706e 1616 #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
bogdanm 82:6473597d706e 1617 #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
bogdanm 82:6473597d706e 1618
bogdanm 82:6473597d706e 1619 /*!
bogdanm 82:6473597d706e 1620 * @}
bogdanm 82:6473597d706e 1621 */ /* end of group AXBS_Register_Accessor_Macros */
bogdanm 82:6473597d706e 1622
bogdanm 82:6473597d706e 1623
bogdanm 82:6473597d706e 1624 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 1625 -- AXBS Register Masks
bogdanm 82:6473597d706e 1626 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 1627
bogdanm 82:6473597d706e 1628 /*!
bogdanm 82:6473597d706e 1629 * @addtogroup AXBS_Register_Masks AXBS Register Masks
bogdanm 82:6473597d706e 1630 * @{
bogdanm 82:6473597d706e 1631 */
bogdanm 82:6473597d706e 1632
bogdanm 82:6473597d706e 1633 /* PRS Bit Fields */
bogdanm 82:6473597d706e 1634 #define AXBS_PRS_M0_MASK 0x7u
bogdanm 82:6473597d706e 1635 #define AXBS_PRS_M0_SHIFT 0
bogdanm 82:6473597d706e 1636 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
bogdanm 82:6473597d706e 1637 #define AXBS_PRS_M1_MASK 0x70u
bogdanm 82:6473597d706e 1638 #define AXBS_PRS_M1_SHIFT 4
bogdanm 82:6473597d706e 1639 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
bogdanm 82:6473597d706e 1640 #define AXBS_PRS_M2_MASK 0x700u
bogdanm 82:6473597d706e 1641 #define AXBS_PRS_M2_SHIFT 8
bogdanm 82:6473597d706e 1642 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
bogdanm 82:6473597d706e 1643 #define AXBS_PRS_M3_MASK 0x7000u
bogdanm 82:6473597d706e 1644 #define AXBS_PRS_M3_SHIFT 12
bogdanm 82:6473597d706e 1645 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
bogdanm 82:6473597d706e 1646 #define AXBS_PRS_M4_MASK 0x70000u
bogdanm 82:6473597d706e 1647 #define AXBS_PRS_M4_SHIFT 16
bogdanm 82:6473597d706e 1648 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
bogdanm 82:6473597d706e 1649 #define AXBS_PRS_M5_MASK 0x700000u
bogdanm 82:6473597d706e 1650 #define AXBS_PRS_M5_SHIFT 20
bogdanm 82:6473597d706e 1651 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
bogdanm 82:6473597d706e 1652 /* CRS Bit Fields */
bogdanm 82:6473597d706e 1653 #define AXBS_CRS_PARK_MASK 0x7u
bogdanm 82:6473597d706e 1654 #define AXBS_CRS_PARK_SHIFT 0
bogdanm 82:6473597d706e 1655 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
bogdanm 82:6473597d706e 1656 #define AXBS_CRS_PCTL_MASK 0x30u
bogdanm 82:6473597d706e 1657 #define AXBS_CRS_PCTL_SHIFT 4
bogdanm 82:6473597d706e 1658 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
bogdanm 82:6473597d706e 1659 #define AXBS_CRS_ARB_MASK 0x300u
bogdanm 82:6473597d706e 1660 #define AXBS_CRS_ARB_SHIFT 8
bogdanm 82:6473597d706e 1661 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
bogdanm 82:6473597d706e 1662 #define AXBS_CRS_HLP_MASK 0x40000000u
bogdanm 82:6473597d706e 1663 #define AXBS_CRS_HLP_SHIFT 30
bogdanm 82:6473597d706e 1664 #define AXBS_CRS_RO_MASK 0x80000000u
bogdanm 82:6473597d706e 1665 #define AXBS_CRS_RO_SHIFT 31
bogdanm 82:6473597d706e 1666 /* MGPCR0 Bit Fields */
bogdanm 82:6473597d706e 1667 #define AXBS_MGPCR0_AULB_MASK 0x7u
bogdanm 82:6473597d706e 1668 #define AXBS_MGPCR0_AULB_SHIFT 0
bogdanm 82:6473597d706e 1669 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
bogdanm 82:6473597d706e 1670 /* MGPCR1 Bit Fields */
bogdanm 82:6473597d706e 1671 #define AXBS_MGPCR1_AULB_MASK 0x7u
bogdanm 82:6473597d706e 1672 #define AXBS_MGPCR1_AULB_SHIFT 0
bogdanm 82:6473597d706e 1673 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
bogdanm 82:6473597d706e 1674 /* MGPCR2 Bit Fields */
bogdanm 82:6473597d706e 1675 #define AXBS_MGPCR2_AULB_MASK 0x7u
bogdanm 82:6473597d706e 1676 #define AXBS_MGPCR2_AULB_SHIFT 0
bogdanm 82:6473597d706e 1677 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
bogdanm 82:6473597d706e 1678 /* MGPCR3 Bit Fields */
bogdanm 82:6473597d706e 1679 #define AXBS_MGPCR3_AULB_MASK 0x7u
bogdanm 82:6473597d706e 1680 #define AXBS_MGPCR3_AULB_SHIFT 0
bogdanm 82:6473597d706e 1681 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
bogdanm 82:6473597d706e 1682 /* MGPCR4 Bit Fields */
bogdanm 82:6473597d706e 1683 #define AXBS_MGPCR4_AULB_MASK 0x7u
bogdanm 82:6473597d706e 1684 #define AXBS_MGPCR4_AULB_SHIFT 0
bogdanm 82:6473597d706e 1685 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
bogdanm 82:6473597d706e 1686 /* MGPCR5 Bit Fields */
bogdanm 82:6473597d706e 1687 #define AXBS_MGPCR5_AULB_MASK 0x7u
bogdanm 82:6473597d706e 1688 #define AXBS_MGPCR5_AULB_SHIFT 0
bogdanm 82:6473597d706e 1689 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
bogdanm 82:6473597d706e 1690
bogdanm 82:6473597d706e 1691 /*!
bogdanm 82:6473597d706e 1692 * @}
bogdanm 82:6473597d706e 1693 */ /* end of group AXBS_Register_Masks */
bogdanm 82:6473597d706e 1694
bogdanm 82:6473597d706e 1695
bogdanm 82:6473597d706e 1696 /* AXBS - Peripheral instance base addresses */
bogdanm 82:6473597d706e 1697 /** Peripheral AXBS base address */
bogdanm 82:6473597d706e 1698 #define AXBS_BASE (0x40004000u)
bogdanm 82:6473597d706e 1699 /** Peripheral AXBS base pointer */
bogdanm 82:6473597d706e 1700 #define AXBS ((AXBS_Type *)AXBS_BASE)
bogdanm 82:6473597d706e 1701 #define AXBS_BASE_PTR (AXBS)
bogdanm 82:6473597d706e 1702 /** Array initializer of AXBS peripheral base pointers */
bogdanm 82:6473597d706e 1703 #define AXBS_BASES { AXBS }
bogdanm 82:6473597d706e 1704
bogdanm 82:6473597d706e 1705 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 1706 -- AXBS - Register accessor macros
bogdanm 82:6473597d706e 1707 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 1708
bogdanm 82:6473597d706e 1709 /*!
bogdanm 82:6473597d706e 1710 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
bogdanm 82:6473597d706e 1711 * @{
bogdanm 82:6473597d706e 1712 */
bogdanm 82:6473597d706e 1713
bogdanm 82:6473597d706e 1714
bogdanm 82:6473597d706e 1715 /* AXBS - Register instance definitions */
bogdanm 82:6473597d706e 1716 /* AXBS */
bogdanm 82:6473597d706e 1717 #define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
bogdanm 82:6473597d706e 1718 #define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
bogdanm 82:6473597d706e 1719 #define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
bogdanm 82:6473597d706e 1720 #define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
bogdanm 82:6473597d706e 1721 #define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
bogdanm 82:6473597d706e 1722 #define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
bogdanm 82:6473597d706e 1723 #define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
bogdanm 82:6473597d706e 1724 #define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
bogdanm 82:6473597d706e 1725 #define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
bogdanm 82:6473597d706e 1726 #define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
bogdanm 82:6473597d706e 1727 #define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
bogdanm 82:6473597d706e 1728 #define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
bogdanm 82:6473597d706e 1729 #define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
bogdanm 82:6473597d706e 1730 #define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
bogdanm 82:6473597d706e 1731 #define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
bogdanm 82:6473597d706e 1732 #define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
bogdanm 82:6473597d706e 1733
bogdanm 82:6473597d706e 1734 /* AXBS - Register array accessors */
bogdanm 82:6473597d706e 1735 #define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
bogdanm 82:6473597d706e 1736 #define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
bogdanm 82:6473597d706e 1737
bogdanm 82:6473597d706e 1738 /*!
bogdanm 82:6473597d706e 1739 * @}
bogdanm 82:6473597d706e 1740 */ /* end of group AXBS_Register_Accessor_Macros */
bogdanm 82:6473597d706e 1741
bogdanm 82:6473597d706e 1742
bogdanm 82:6473597d706e 1743 /*!
bogdanm 82:6473597d706e 1744 * @}
bogdanm 82:6473597d706e 1745 */ /* end of group AXBS_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 1746
bogdanm 82:6473597d706e 1747
bogdanm 82:6473597d706e 1748 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 1749 -- CAN Peripheral Access Layer
bogdanm 82:6473597d706e 1750 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 1751
bogdanm 82:6473597d706e 1752 /*!
bogdanm 82:6473597d706e 1753 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
bogdanm 82:6473597d706e 1754 * @{
bogdanm 82:6473597d706e 1755 */
bogdanm 82:6473597d706e 1756
bogdanm 82:6473597d706e 1757 /** CAN - Register Layout Typedef */
bogdanm 82:6473597d706e 1758 typedef struct {
bogdanm 82:6473597d706e 1759 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
bogdanm 82:6473597d706e 1760 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
bogdanm 82:6473597d706e 1761 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
bogdanm 82:6473597d706e 1762 uint8_t RESERVED_0[4];
bogdanm 82:6473597d706e 1763 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
bogdanm 82:6473597d706e 1764 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
bogdanm 82:6473597d706e 1765 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
bogdanm 82:6473597d706e 1766 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
bogdanm 82:6473597d706e 1767 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
bogdanm 82:6473597d706e 1768 uint8_t RESERVED_1[4];
bogdanm 82:6473597d706e 1769 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
bogdanm 82:6473597d706e 1770 uint8_t RESERVED_2[4];
bogdanm 82:6473597d706e 1771 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
bogdanm 82:6473597d706e 1772 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
bogdanm 82:6473597d706e 1773 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
bogdanm 82:6473597d706e 1774 uint8_t RESERVED_3[8];
bogdanm 82:6473597d706e 1775 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
bogdanm 82:6473597d706e 1776 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
bogdanm 82:6473597d706e 1777 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
bogdanm 82:6473597d706e 1778 uint8_t RESERVED_4[48];
bogdanm 82:6473597d706e 1779 struct { /* offset: 0x80, array step: 0x10 */
bogdanm 82:6473597d706e 1780 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
bogdanm 82:6473597d706e 1781 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
bogdanm 82:6473597d706e 1782 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
bogdanm 82:6473597d706e 1783 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
bogdanm 82:6473597d706e 1784 } MB[16];
bogdanm 82:6473597d706e 1785 uint8_t RESERVED_5[1792];
bogdanm 82:6473597d706e 1786 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
bogdanm 82:6473597d706e 1787 } CAN_Type, *CAN_MemMapPtr;
bogdanm 82:6473597d706e 1788
bogdanm 82:6473597d706e 1789 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 1790 -- CAN - Register accessor macros
bogdanm 82:6473597d706e 1791 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 1792
bogdanm 82:6473597d706e 1793 /*!
bogdanm 82:6473597d706e 1794 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
bogdanm 82:6473597d706e 1795 * @{
bogdanm 82:6473597d706e 1796 */
bogdanm 82:6473597d706e 1797
bogdanm 82:6473597d706e 1798
bogdanm 82:6473597d706e 1799 /* CAN - Register accessors */
bogdanm 82:6473597d706e 1800 #define CAN_MCR_REG(base) ((base)->MCR)
bogdanm 82:6473597d706e 1801 #define CAN_CTRL1_REG(base) ((base)->CTRL1)
bogdanm 82:6473597d706e 1802 #define CAN_TIMER_REG(base) ((base)->TIMER)
bogdanm 82:6473597d706e 1803 #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
bogdanm 82:6473597d706e 1804 #define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
bogdanm 82:6473597d706e 1805 #define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
bogdanm 82:6473597d706e 1806 #define CAN_ECR_REG(base) ((base)->ECR)
bogdanm 82:6473597d706e 1807 #define CAN_ESR1_REG(base) ((base)->ESR1)
bogdanm 82:6473597d706e 1808 #define CAN_IMASK1_REG(base) ((base)->IMASK1)
bogdanm 82:6473597d706e 1809 #define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
bogdanm 82:6473597d706e 1810 #define CAN_CTRL2_REG(base) ((base)->CTRL2)
bogdanm 82:6473597d706e 1811 #define CAN_ESR2_REG(base) ((base)->ESR2)
bogdanm 82:6473597d706e 1812 #define CAN_CRCR_REG(base) ((base)->CRCR)
bogdanm 82:6473597d706e 1813 #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
bogdanm 82:6473597d706e 1814 #define CAN_RXFIR_REG(base) ((base)->RXFIR)
bogdanm 82:6473597d706e 1815 #define CAN_CS_REG(base,index) ((base)->MB[index].CS)
bogdanm 82:6473597d706e 1816 #define CAN_ID_REG(base,index) ((base)->MB[index].ID)
bogdanm 82:6473597d706e 1817 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
bogdanm 82:6473597d706e 1818 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
bogdanm 82:6473597d706e 1819 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
bogdanm 82:6473597d706e 1820
bogdanm 82:6473597d706e 1821 /*!
bogdanm 82:6473597d706e 1822 * @}
bogdanm 82:6473597d706e 1823 */ /* end of group CAN_Register_Accessor_Macros */
bogdanm 82:6473597d706e 1824
bogdanm 82:6473597d706e 1825
bogdanm 82:6473597d706e 1826 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 1827 -- CAN Register Masks
bogdanm 82:6473597d706e 1828 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 1829
bogdanm 82:6473597d706e 1830 /*!
bogdanm 82:6473597d706e 1831 * @addtogroup CAN_Register_Masks CAN Register Masks
bogdanm 82:6473597d706e 1832 * @{
bogdanm 82:6473597d706e 1833 */
bogdanm 82:6473597d706e 1834
bogdanm 82:6473597d706e 1835 /* MCR Bit Fields */
bogdanm 82:6473597d706e 1836 #define CAN_MCR_MAXMB_MASK 0x7Fu
bogdanm 82:6473597d706e 1837 #define CAN_MCR_MAXMB_SHIFT 0
bogdanm 82:6473597d706e 1838 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
bogdanm 82:6473597d706e 1839 #define CAN_MCR_IDAM_MASK 0x300u
bogdanm 82:6473597d706e 1840 #define CAN_MCR_IDAM_SHIFT 8
bogdanm 82:6473597d706e 1841 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
bogdanm 82:6473597d706e 1842 #define CAN_MCR_AEN_MASK 0x1000u
bogdanm 82:6473597d706e 1843 #define CAN_MCR_AEN_SHIFT 12
bogdanm 82:6473597d706e 1844 #define CAN_MCR_LPRIOEN_MASK 0x2000u
bogdanm 82:6473597d706e 1845 #define CAN_MCR_LPRIOEN_SHIFT 13
bogdanm 82:6473597d706e 1846 #define CAN_MCR_IRMQ_MASK 0x10000u
bogdanm 82:6473597d706e 1847 #define CAN_MCR_IRMQ_SHIFT 16
bogdanm 82:6473597d706e 1848 #define CAN_MCR_SRXDIS_MASK 0x20000u
bogdanm 82:6473597d706e 1849 #define CAN_MCR_SRXDIS_SHIFT 17
bogdanm 82:6473597d706e 1850 #define CAN_MCR_WAKSRC_MASK 0x80000u
bogdanm 82:6473597d706e 1851 #define CAN_MCR_WAKSRC_SHIFT 19
bogdanm 82:6473597d706e 1852 #define CAN_MCR_LPMACK_MASK 0x100000u
bogdanm 82:6473597d706e 1853 #define CAN_MCR_LPMACK_SHIFT 20
bogdanm 82:6473597d706e 1854 #define CAN_MCR_WRNEN_MASK 0x200000u
bogdanm 82:6473597d706e 1855 #define CAN_MCR_WRNEN_SHIFT 21
bogdanm 82:6473597d706e 1856 #define CAN_MCR_SLFWAK_MASK 0x400000u
bogdanm 82:6473597d706e 1857 #define CAN_MCR_SLFWAK_SHIFT 22
bogdanm 82:6473597d706e 1858 #define CAN_MCR_SUPV_MASK 0x800000u
bogdanm 82:6473597d706e 1859 #define CAN_MCR_SUPV_SHIFT 23
bogdanm 82:6473597d706e 1860 #define CAN_MCR_FRZACK_MASK 0x1000000u
bogdanm 82:6473597d706e 1861 #define CAN_MCR_FRZACK_SHIFT 24
bogdanm 82:6473597d706e 1862 #define CAN_MCR_SOFTRST_MASK 0x2000000u
bogdanm 82:6473597d706e 1863 #define CAN_MCR_SOFTRST_SHIFT 25
bogdanm 82:6473597d706e 1864 #define CAN_MCR_WAKMSK_MASK 0x4000000u
bogdanm 82:6473597d706e 1865 #define CAN_MCR_WAKMSK_SHIFT 26
bogdanm 82:6473597d706e 1866 #define CAN_MCR_NOTRDY_MASK 0x8000000u
bogdanm 82:6473597d706e 1867 #define CAN_MCR_NOTRDY_SHIFT 27
bogdanm 82:6473597d706e 1868 #define CAN_MCR_HALT_MASK 0x10000000u
bogdanm 82:6473597d706e 1869 #define CAN_MCR_HALT_SHIFT 28
bogdanm 82:6473597d706e 1870 #define CAN_MCR_RFEN_MASK 0x20000000u
bogdanm 82:6473597d706e 1871 #define CAN_MCR_RFEN_SHIFT 29
bogdanm 82:6473597d706e 1872 #define CAN_MCR_FRZ_MASK 0x40000000u
bogdanm 82:6473597d706e 1873 #define CAN_MCR_FRZ_SHIFT 30
bogdanm 82:6473597d706e 1874 #define CAN_MCR_MDIS_MASK 0x80000000u
bogdanm 82:6473597d706e 1875 #define CAN_MCR_MDIS_SHIFT 31
bogdanm 82:6473597d706e 1876 /* CTRL1 Bit Fields */
bogdanm 82:6473597d706e 1877 #define CAN_CTRL1_PROPSEG_MASK 0x7u
bogdanm 82:6473597d706e 1878 #define CAN_CTRL1_PROPSEG_SHIFT 0
bogdanm 82:6473597d706e 1879 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
bogdanm 82:6473597d706e 1880 #define CAN_CTRL1_LOM_MASK 0x8u
bogdanm 82:6473597d706e 1881 #define CAN_CTRL1_LOM_SHIFT 3
bogdanm 82:6473597d706e 1882 #define CAN_CTRL1_LBUF_MASK 0x10u
bogdanm 82:6473597d706e 1883 #define CAN_CTRL1_LBUF_SHIFT 4
bogdanm 82:6473597d706e 1884 #define CAN_CTRL1_TSYN_MASK 0x20u
bogdanm 82:6473597d706e 1885 #define CAN_CTRL1_TSYN_SHIFT 5
bogdanm 82:6473597d706e 1886 #define CAN_CTRL1_BOFFREC_MASK 0x40u
bogdanm 82:6473597d706e 1887 #define CAN_CTRL1_BOFFREC_SHIFT 6
bogdanm 82:6473597d706e 1888 #define CAN_CTRL1_SMP_MASK 0x80u
bogdanm 82:6473597d706e 1889 #define CAN_CTRL1_SMP_SHIFT 7
bogdanm 82:6473597d706e 1890 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
bogdanm 82:6473597d706e 1891 #define CAN_CTRL1_RWRNMSK_SHIFT 10
bogdanm 82:6473597d706e 1892 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
bogdanm 82:6473597d706e 1893 #define CAN_CTRL1_TWRNMSK_SHIFT 11
bogdanm 82:6473597d706e 1894 #define CAN_CTRL1_LPB_MASK 0x1000u
bogdanm 82:6473597d706e 1895 #define CAN_CTRL1_LPB_SHIFT 12
bogdanm 82:6473597d706e 1896 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
bogdanm 82:6473597d706e 1897 #define CAN_CTRL1_CLKSRC_SHIFT 13
bogdanm 82:6473597d706e 1898 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
bogdanm 82:6473597d706e 1899 #define CAN_CTRL1_ERRMSK_SHIFT 14
bogdanm 82:6473597d706e 1900 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
bogdanm 82:6473597d706e 1901 #define CAN_CTRL1_BOFFMSK_SHIFT 15
bogdanm 82:6473597d706e 1902 #define CAN_CTRL1_PSEG2_MASK 0x70000u
bogdanm 82:6473597d706e 1903 #define CAN_CTRL1_PSEG2_SHIFT 16
bogdanm 82:6473597d706e 1904 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
bogdanm 82:6473597d706e 1905 #define CAN_CTRL1_PSEG1_MASK 0x380000u
bogdanm 82:6473597d706e 1906 #define CAN_CTRL1_PSEG1_SHIFT 19
bogdanm 82:6473597d706e 1907 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
bogdanm 82:6473597d706e 1908 #define CAN_CTRL1_RJW_MASK 0xC00000u
bogdanm 82:6473597d706e 1909 #define CAN_CTRL1_RJW_SHIFT 22
bogdanm 82:6473597d706e 1910 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
bogdanm 82:6473597d706e 1911 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
bogdanm 82:6473597d706e 1912 #define CAN_CTRL1_PRESDIV_SHIFT 24
bogdanm 82:6473597d706e 1913 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
bogdanm 82:6473597d706e 1914 /* TIMER Bit Fields */
bogdanm 82:6473597d706e 1915 #define CAN_TIMER_TIMER_MASK 0xFFFFu
bogdanm 82:6473597d706e 1916 #define CAN_TIMER_TIMER_SHIFT 0
bogdanm 82:6473597d706e 1917 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
bogdanm 82:6473597d706e 1918 /* RXMGMASK Bit Fields */
bogdanm 82:6473597d706e 1919 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 1920 #define CAN_RXMGMASK_MG_SHIFT 0
bogdanm 82:6473597d706e 1921 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
bogdanm 82:6473597d706e 1922 /* RX14MASK Bit Fields */
bogdanm 82:6473597d706e 1923 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 1924 #define CAN_RX14MASK_RX14M_SHIFT 0
bogdanm 82:6473597d706e 1925 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
bogdanm 82:6473597d706e 1926 /* RX15MASK Bit Fields */
bogdanm 82:6473597d706e 1927 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 1928 #define CAN_RX15MASK_RX15M_SHIFT 0
bogdanm 82:6473597d706e 1929 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
bogdanm 82:6473597d706e 1930 /* ECR Bit Fields */
bogdanm 82:6473597d706e 1931 #define CAN_ECR_TXERRCNT_MASK 0xFFu
bogdanm 82:6473597d706e 1932 #define CAN_ECR_TXERRCNT_SHIFT 0
bogdanm 82:6473597d706e 1933 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
bogdanm 82:6473597d706e 1934 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
bogdanm 82:6473597d706e 1935 #define CAN_ECR_RXERRCNT_SHIFT 8
bogdanm 82:6473597d706e 1936 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
bogdanm 82:6473597d706e 1937 /* ESR1 Bit Fields */
bogdanm 82:6473597d706e 1938 #define CAN_ESR1_WAKINT_MASK 0x1u
bogdanm 82:6473597d706e 1939 #define CAN_ESR1_WAKINT_SHIFT 0
bogdanm 82:6473597d706e 1940 #define CAN_ESR1_ERRINT_MASK 0x2u
bogdanm 82:6473597d706e 1941 #define CAN_ESR1_ERRINT_SHIFT 1
bogdanm 82:6473597d706e 1942 #define CAN_ESR1_BOFFINT_MASK 0x4u
bogdanm 82:6473597d706e 1943 #define CAN_ESR1_BOFFINT_SHIFT 2
bogdanm 82:6473597d706e 1944 #define CAN_ESR1_RX_MASK 0x8u
bogdanm 82:6473597d706e 1945 #define CAN_ESR1_RX_SHIFT 3
bogdanm 82:6473597d706e 1946 #define CAN_ESR1_FLTCONF_MASK 0x30u
bogdanm 82:6473597d706e 1947 #define CAN_ESR1_FLTCONF_SHIFT 4
bogdanm 82:6473597d706e 1948 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
bogdanm 82:6473597d706e 1949 #define CAN_ESR1_TX_MASK 0x40u
bogdanm 82:6473597d706e 1950 #define CAN_ESR1_TX_SHIFT 6
bogdanm 82:6473597d706e 1951 #define CAN_ESR1_IDLE_MASK 0x80u
bogdanm 82:6473597d706e 1952 #define CAN_ESR1_IDLE_SHIFT 7
bogdanm 82:6473597d706e 1953 #define CAN_ESR1_RXWRN_MASK 0x100u
bogdanm 82:6473597d706e 1954 #define CAN_ESR1_RXWRN_SHIFT 8
bogdanm 82:6473597d706e 1955 #define CAN_ESR1_TXWRN_MASK 0x200u
bogdanm 82:6473597d706e 1956 #define CAN_ESR1_TXWRN_SHIFT 9
bogdanm 82:6473597d706e 1957 #define CAN_ESR1_STFERR_MASK 0x400u
bogdanm 82:6473597d706e 1958 #define CAN_ESR1_STFERR_SHIFT 10
bogdanm 82:6473597d706e 1959 #define CAN_ESR1_FRMERR_MASK 0x800u
bogdanm 82:6473597d706e 1960 #define CAN_ESR1_FRMERR_SHIFT 11
bogdanm 82:6473597d706e 1961 #define CAN_ESR1_CRCERR_MASK 0x1000u
bogdanm 82:6473597d706e 1962 #define CAN_ESR1_CRCERR_SHIFT 12
bogdanm 82:6473597d706e 1963 #define CAN_ESR1_ACKERR_MASK 0x2000u
bogdanm 82:6473597d706e 1964 #define CAN_ESR1_ACKERR_SHIFT 13
bogdanm 82:6473597d706e 1965 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
bogdanm 82:6473597d706e 1966 #define CAN_ESR1_BIT0ERR_SHIFT 14
bogdanm 82:6473597d706e 1967 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
bogdanm 82:6473597d706e 1968 #define CAN_ESR1_BIT1ERR_SHIFT 15
bogdanm 82:6473597d706e 1969 #define CAN_ESR1_RWRNINT_MASK 0x10000u
bogdanm 82:6473597d706e 1970 #define CAN_ESR1_RWRNINT_SHIFT 16
bogdanm 82:6473597d706e 1971 #define CAN_ESR1_TWRNINT_MASK 0x20000u
bogdanm 82:6473597d706e 1972 #define CAN_ESR1_TWRNINT_SHIFT 17
bogdanm 82:6473597d706e 1973 #define CAN_ESR1_SYNCH_MASK 0x40000u
bogdanm 82:6473597d706e 1974 #define CAN_ESR1_SYNCH_SHIFT 18
bogdanm 82:6473597d706e 1975 /* IMASK1 Bit Fields */
bogdanm 82:6473597d706e 1976 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 1977 #define CAN_IMASK1_BUFLM_SHIFT 0
bogdanm 82:6473597d706e 1978 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
bogdanm 82:6473597d706e 1979 /* IFLAG1 Bit Fields */
bogdanm 82:6473597d706e 1980 #define CAN_IFLAG1_BUF0I_MASK 0x1u
bogdanm 82:6473597d706e 1981 #define CAN_IFLAG1_BUF0I_SHIFT 0
bogdanm 82:6473597d706e 1982 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
bogdanm 82:6473597d706e 1983 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1
bogdanm 82:6473597d706e 1984 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
bogdanm 82:6473597d706e 1985 #define CAN_IFLAG1_BUF5I_MASK 0x20u
bogdanm 82:6473597d706e 1986 #define CAN_IFLAG1_BUF5I_SHIFT 5
bogdanm 82:6473597d706e 1987 #define CAN_IFLAG1_BUF6I_MASK 0x40u
bogdanm 82:6473597d706e 1988 #define CAN_IFLAG1_BUF6I_SHIFT 6
bogdanm 82:6473597d706e 1989 #define CAN_IFLAG1_BUF7I_MASK 0x80u
bogdanm 82:6473597d706e 1990 #define CAN_IFLAG1_BUF7I_SHIFT 7
bogdanm 82:6473597d706e 1991 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
bogdanm 82:6473597d706e 1992 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
bogdanm 82:6473597d706e 1993 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
bogdanm 82:6473597d706e 1994 /* CTRL2 Bit Fields */
bogdanm 82:6473597d706e 1995 #define CAN_CTRL2_EACEN_MASK 0x10000u
bogdanm 82:6473597d706e 1996 #define CAN_CTRL2_EACEN_SHIFT 16
bogdanm 82:6473597d706e 1997 #define CAN_CTRL2_RRS_MASK 0x20000u
bogdanm 82:6473597d706e 1998 #define CAN_CTRL2_RRS_SHIFT 17
bogdanm 82:6473597d706e 1999 #define CAN_CTRL2_MRP_MASK 0x40000u
bogdanm 82:6473597d706e 2000 #define CAN_CTRL2_MRP_SHIFT 18
bogdanm 82:6473597d706e 2001 #define CAN_CTRL2_TASD_MASK 0xF80000u
bogdanm 82:6473597d706e 2002 #define CAN_CTRL2_TASD_SHIFT 19
bogdanm 82:6473597d706e 2003 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
bogdanm 82:6473597d706e 2004 #define CAN_CTRL2_RFFN_MASK 0xF000000u
bogdanm 82:6473597d706e 2005 #define CAN_CTRL2_RFFN_SHIFT 24
bogdanm 82:6473597d706e 2006 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
bogdanm 82:6473597d706e 2007 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
bogdanm 82:6473597d706e 2008 #define CAN_CTRL2_WRMFRZ_SHIFT 28
bogdanm 82:6473597d706e 2009 /* ESR2 Bit Fields */
bogdanm 82:6473597d706e 2010 #define CAN_ESR2_IMB_MASK 0x2000u
bogdanm 82:6473597d706e 2011 #define CAN_ESR2_IMB_SHIFT 13
bogdanm 82:6473597d706e 2012 #define CAN_ESR2_VPS_MASK 0x4000u
bogdanm 82:6473597d706e 2013 #define CAN_ESR2_VPS_SHIFT 14
bogdanm 82:6473597d706e 2014 #define CAN_ESR2_LPTM_MASK 0x7F0000u
bogdanm 82:6473597d706e 2015 #define CAN_ESR2_LPTM_SHIFT 16
bogdanm 82:6473597d706e 2016 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
bogdanm 82:6473597d706e 2017 /* CRCR Bit Fields */
bogdanm 82:6473597d706e 2018 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
bogdanm 82:6473597d706e 2019 #define CAN_CRCR_TXCRC_SHIFT 0
bogdanm 82:6473597d706e 2020 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
bogdanm 82:6473597d706e 2021 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
bogdanm 82:6473597d706e 2022 #define CAN_CRCR_MBCRC_SHIFT 16
bogdanm 82:6473597d706e 2023 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
bogdanm 82:6473597d706e 2024 /* RXFGMASK Bit Fields */
bogdanm 82:6473597d706e 2025 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 2026 #define CAN_RXFGMASK_FGM_SHIFT 0
bogdanm 82:6473597d706e 2027 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
bogdanm 82:6473597d706e 2028 /* RXFIR Bit Fields */
bogdanm 82:6473597d706e 2029 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
bogdanm 82:6473597d706e 2030 #define CAN_RXFIR_IDHIT_SHIFT 0
bogdanm 82:6473597d706e 2031 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
bogdanm 82:6473597d706e 2032 /* CS Bit Fields */
bogdanm 82:6473597d706e 2033 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
bogdanm 82:6473597d706e 2034 #define CAN_CS_TIME_STAMP_SHIFT 0
bogdanm 82:6473597d706e 2035 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
bogdanm 82:6473597d706e 2036 #define CAN_CS_DLC_MASK 0xF0000u
bogdanm 82:6473597d706e 2037 #define CAN_CS_DLC_SHIFT 16
bogdanm 82:6473597d706e 2038 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
bogdanm 82:6473597d706e 2039 #define CAN_CS_RTR_MASK 0x100000u
bogdanm 82:6473597d706e 2040 #define CAN_CS_RTR_SHIFT 20
bogdanm 82:6473597d706e 2041 #define CAN_CS_IDE_MASK 0x200000u
bogdanm 82:6473597d706e 2042 #define CAN_CS_IDE_SHIFT 21
bogdanm 82:6473597d706e 2043 #define CAN_CS_SRR_MASK 0x400000u
bogdanm 82:6473597d706e 2044 #define CAN_CS_SRR_SHIFT 22
bogdanm 82:6473597d706e 2045 #define CAN_CS_CODE_MASK 0xF000000u
bogdanm 82:6473597d706e 2046 #define CAN_CS_CODE_SHIFT 24
bogdanm 82:6473597d706e 2047 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
bogdanm 82:6473597d706e 2048 /* ID Bit Fields */
bogdanm 82:6473597d706e 2049 #define CAN_ID_EXT_MASK 0x3FFFFu
bogdanm 82:6473597d706e 2050 #define CAN_ID_EXT_SHIFT 0
bogdanm 82:6473597d706e 2051 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
bogdanm 82:6473597d706e 2052 #define CAN_ID_STD_MASK 0x1FFC0000u
bogdanm 82:6473597d706e 2053 #define CAN_ID_STD_SHIFT 18
bogdanm 82:6473597d706e 2054 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
bogdanm 82:6473597d706e 2055 #define CAN_ID_PRIO_MASK 0xE0000000u
bogdanm 82:6473597d706e 2056 #define CAN_ID_PRIO_SHIFT 29
bogdanm 82:6473597d706e 2057 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
bogdanm 82:6473597d706e 2058 /* WORD0 Bit Fields */
bogdanm 82:6473597d706e 2059 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
bogdanm 82:6473597d706e 2060 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
bogdanm 82:6473597d706e 2061 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
bogdanm 82:6473597d706e 2062 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
bogdanm 82:6473597d706e 2063 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
bogdanm 82:6473597d706e 2064 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
bogdanm 82:6473597d706e 2065 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
bogdanm 82:6473597d706e 2066 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
bogdanm 82:6473597d706e 2067 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
bogdanm 82:6473597d706e 2068 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
bogdanm 82:6473597d706e 2069 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
bogdanm 82:6473597d706e 2070 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
bogdanm 82:6473597d706e 2071 /* WORD1 Bit Fields */
bogdanm 82:6473597d706e 2072 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
bogdanm 82:6473597d706e 2073 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
bogdanm 82:6473597d706e 2074 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
bogdanm 82:6473597d706e 2075 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
bogdanm 82:6473597d706e 2076 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
bogdanm 82:6473597d706e 2077 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
bogdanm 82:6473597d706e 2078 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
bogdanm 82:6473597d706e 2079 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
bogdanm 82:6473597d706e 2080 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
bogdanm 82:6473597d706e 2081 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
bogdanm 82:6473597d706e 2082 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
bogdanm 82:6473597d706e 2083 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
bogdanm 82:6473597d706e 2084 /* RXIMR Bit Fields */
bogdanm 82:6473597d706e 2085 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 2086 #define CAN_RXIMR_MI_SHIFT 0
bogdanm 82:6473597d706e 2087 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
bogdanm 82:6473597d706e 2088
bogdanm 82:6473597d706e 2089 /*!
bogdanm 82:6473597d706e 2090 * @}
bogdanm 82:6473597d706e 2091 */ /* end of group CAN_Register_Masks */
bogdanm 82:6473597d706e 2092
bogdanm 82:6473597d706e 2093
bogdanm 82:6473597d706e 2094 /* CAN - Peripheral instance base addresses */
bogdanm 82:6473597d706e 2095 /** Peripheral CAN0 base address */
bogdanm 82:6473597d706e 2096 #define CAN0_BASE (0x40024000u)
bogdanm 82:6473597d706e 2097 /** Peripheral CAN0 base pointer */
bogdanm 82:6473597d706e 2098 #define CAN0 ((CAN_Type *)CAN0_BASE)
bogdanm 82:6473597d706e 2099 #define CAN0_BASE_PTR (CAN0)
bogdanm 82:6473597d706e 2100 /** Array initializer of CAN peripheral base pointers */
bogdanm 82:6473597d706e 2101 #define CAN_BASES { CAN0 }
bogdanm 82:6473597d706e 2102
bogdanm 82:6473597d706e 2103 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2104 -- CAN - Register accessor macros
bogdanm 82:6473597d706e 2105 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2106
bogdanm 82:6473597d706e 2107 /*!
bogdanm 82:6473597d706e 2108 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
bogdanm 82:6473597d706e 2109 * @{
bogdanm 82:6473597d706e 2110 */
bogdanm 82:6473597d706e 2111
bogdanm 82:6473597d706e 2112
bogdanm 82:6473597d706e 2113 /* CAN - Register instance definitions */
bogdanm 82:6473597d706e 2114 /* CAN0 */
bogdanm 82:6473597d706e 2115 #define CAN0_MCR CAN_MCR_REG(CAN0)
bogdanm 82:6473597d706e 2116 #define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
bogdanm 82:6473597d706e 2117 #define CAN0_TIMER CAN_TIMER_REG(CAN0)
bogdanm 82:6473597d706e 2118 #define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
bogdanm 82:6473597d706e 2119 #define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
bogdanm 82:6473597d706e 2120 #define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
bogdanm 82:6473597d706e 2121 #define CAN0_ECR CAN_ECR_REG(CAN0)
bogdanm 82:6473597d706e 2122 #define CAN0_ESR1 CAN_ESR1_REG(CAN0)
bogdanm 82:6473597d706e 2123 #define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
bogdanm 82:6473597d706e 2124 #define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
bogdanm 82:6473597d706e 2125 #define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
bogdanm 82:6473597d706e 2126 #define CAN0_ESR2 CAN_ESR2_REG(CAN0)
bogdanm 82:6473597d706e 2127 #define CAN0_CRCR CAN_CRCR_REG(CAN0)
bogdanm 82:6473597d706e 2128 #define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
bogdanm 82:6473597d706e 2129 #define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
bogdanm 82:6473597d706e 2130 #define CAN0_CS0 CAN_CS_REG(CAN0,0)
bogdanm 82:6473597d706e 2131 #define CAN0_ID0 CAN_ID_REG(CAN0,0)
bogdanm 82:6473597d706e 2132 #define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
bogdanm 82:6473597d706e 2133 #define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
bogdanm 82:6473597d706e 2134 #define CAN0_CS1 CAN_CS_REG(CAN0,1)
bogdanm 82:6473597d706e 2135 #define CAN0_ID1 CAN_ID_REG(CAN0,1)
bogdanm 82:6473597d706e 2136 #define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
bogdanm 82:6473597d706e 2137 #define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
bogdanm 82:6473597d706e 2138 #define CAN0_CS2 CAN_CS_REG(CAN0,2)
bogdanm 82:6473597d706e 2139 #define CAN0_ID2 CAN_ID_REG(CAN0,2)
bogdanm 82:6473597d706e 2140 #define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
bogdanm 82:6473597d706e 2141 #define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
bogdanm 82:6473597d706e 2142 #define CAN0_CS3 CAN_CS_REG(CAN0,3)
bogdanm 82:6473597d706e 2143 #define CAN0_ID3 CAN_ID_REG(CAN0,3)
bogdanm 82:6473597d706e 2144 #define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
bogdanm 82:6473597d706e 2145 #define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
bogdanm 82:6473597d706e 2146 #define CAN0_CS4 CAN_CS_REG(CAN0,4)
bogdanm 82:6473597d706e 2147 #define CAN0_ID4 CAN_ID_REG(CAN0,4)
bogdanm 82:6473597d706e 2148 #define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
bogdanm 82:6473597d706e 2149 #define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
bogdanm 82:6473597d706e 2150 #define CAN0_CS5 CAN_CS_REG(CAN0,5)
bogdanm 82:6473597d706e 2151 #define CAN0_ID5 CAN_ID_REG(CAN0,5)
bogdanm 82:6473597d706e 2152 #define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
bogdanm 82:6473597d706e 2153 #define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
bogdanm 82:6473597d706e 2154 #define CAN0_CS6 CAN_CS_REG(CAN0,6)
bogdanm 82:6473597d706e 2155 #define CAN0_ID6 CAN_ID_REG(CAN0,6)
bogdanm 82:6473597d706e 2156 #define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
bogdanm 82:6473597d706e 2157 #define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
bogdanm 82:6473597d706e 2158 #define CAN0_CS7 CAN_CS_REG(CAN0,7)
bogdanm 82:6473597d706e 2159 #define CAN0_ID7 CAN_ID_REG(CAN0,7)
bogdanm 82:6473597d706e 2160 #define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
bogdanm 82:6473597d706e 2161 #define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
bogdanm 82:6473597d706e 2162 #define CAN0_CS8 CAN_CS_REG(CAN0,8)
bogdanm 82:6473597d706e 2163 #define CAN0_ID8 CAN_ID_REG(CAN0,8)
bogdanm 82:6473597d706e 2164 #define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
bogdanm 82:6473597d706e 2165 #define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
bogdanm 82:6473597d706e 2166 #define CAN0_CS9 CAN_CS_REG(CAN0,9)
bogdanm 82:6473597d706e 2167 #define CAN0_ID9 CAN_ID_REG(CAN0,9)
bogdanm 82:6473597d706e 2168 #define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
bogdanm 82:6473597d706e 2169 #define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
bogdanm 82:6473597d706e 2170 #define CAN0_CS10 CAN_CS_REG(CAN0,10)
bogdanm 82:6473597d706e 2171 #define CAN0_ID10 CAN_ID_REG(CAN0,10)
bogdanm 82:6473597d706e 2172 #define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
bogdanm 82:6473597d706e 2173 #define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
bogdanm 82:6473597d706e 2174 #define CAN0_CS11 CAN_CS_REG(CAN0,11)
bogdanm 82:6473597d706e 2175 #define CAN0_ID11 CAN_ID_REG(CAN0,11)
bogdanm 82:6473597d706e 2176 #define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
bogdanm 82:6473597d706e 2177 #define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
bogdanm 82:6473597d706e 2178 #define CAN0_CS12 CAN_CS_REG(CAN0,12)
bogdanm 82:6473597d706e 2179 #define CAN0_ID12 CAN_ID_REG(CAN0,12)
bogdanm 82:6473597d706e 2180 #define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
bogdanm 82:6473597d706e 2181 #define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
bogdanm 82:6473597d706e 2182 #define CAN0_CS13 CAN_CS_REG(CAN0,13)
bogdanm 82:6473597d706e 2183 #define CAN0_ID13 CAN_ID_REG(CAN0,13)
bogdanm 82:6473597d706e 2184 #define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
bogdanm 82:6473597d706e 2185 #define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
bogdanm 82:6473597d706e 2186 #define CAN0_CS14 CAN_CS_REG(CAN0,14)
bogdanm 82:6473597d706e 2187 #define CAN0_ID14 CAN_ID_REG(CAN0,14)
bogdanm 82:6473597d706e 2188 #define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
bogdanm 82:6473597d706e 2189 #define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
bogdanm 82:6473597d706e 2190 #define CAN0_CS15 CAN_CS_REG(CAN0,15)
bogdanm 82:6473597d706e 2191 #define CAN0_ID15 CAN_ID_REG(CAN0,15)
bogdanm 82:6473597d706e 2192 #define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
bogdanm 82:6473597d706e 2193 #define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
bogdanm 82:6473597d706e 2194 #define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
bogdanm 82:6473597d706e 2195 #define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
bogdanm 82:6473597d706e 2196 #define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
bogdanm 82:6473597d706e 2197 #define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
bogdanm 82:6473597d706e 2198 #define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
bogdanm 82:6473597d706e 2199 #define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
bogdanm 82:6473597d706e 2200 #define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
bogdanm 82:6473597d706e 2201 #define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
bogdanm 82:6473597d706e 2202 #define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
bogdanm 82:6473597d706e 2203 #define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
bogdanm 82:6473597d706e 2204 #define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
bogdanm 82:6473597d706e 2205 #define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
bogdanm 82:6473597d706e 2206 #define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
bogdanm 82:6473597d706e 2207 #define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
bogdanm 82:6473597d706e 2208 #define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
bogdanm 82:6473597d706e 2209 #define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
bogdanm 82:6473597d706e 2210
bogdanm 82:6473597d706e 2211 /* CAN - Register array accessors */
bogdanm 82:6473597d706e 2212 #define CAN0_CS(index) CAN_CS_REG(CAN0,index)
bogdanm 82:6473597d706e 2213 #define CAN0_ID(index) CAN_ID_REG(CAN0,index)
bogdanm 82:6473597d706e 2214 #define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
bogdanm 82:6473597d706e 2215 #define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
bogdanm 82:6473597d706e 2216 #define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
bogdanm 82:6473597d706e 2217
bogdanm 82:6473597d706e 2218 /*!
bogdanm 82:6473597d706e 2219 * @}
bogdanm 82:6473597d706e 2220 */ /* end of group CAN_Register_Accessor_Macros */
bogdanm 82:6473597d706e 2221
bogdanm 82:6473597d706e 2222
bogdanm 82:6473597d706e 2223 /*!
bogdanm 82:6473597d706e 2224 * @}
bogdanm 82:6473597d706e 2225 */ /* end of group CAN_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 2226
bogdanm 82:6473597d706e 2227
bogdanm 82:6473597d706e 2228 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2229 -- CAU Peripheral Access Layer
bogdanm 82:6473597d706e 2230 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2231
bogdanm 82:6473597d706e 2232 /*!
bogdanm 82:6473597d706e 2233 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
bogdanm 82:6473597d706e 2234 * @{
bogdanm 82:6473597d706e 2235 */
bogdanm 82:6473597d706e 2236
bogdanm 82:6473597d706e 2237 /** CAU - Register Layout Typedef */
bogdanm 82:6473597d706e 2238 typedef struct {
bogdanm 82:6473597d706e 2239 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
bogdanm 82:6473597d706e 2240 uint8_t RESERVED_0[2048];
bogdanm 82:6473597d706e 2241 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
bogdanm 82:6473597d706e 2242 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
bogdanm 82:6473597d706e 2243 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
bogdanm 82:6473597d706e 2244 uint8_t RESERVED_1[20];
bogdanm 82:6473597d706e 2245 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
bogdanm 82:6473597d706e 2246 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
bogdanm 82:6473597d706e 2247 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
bogdanm 82:6473597d706e 2248 uint8_t RESERVED_2[20];
bogdanm 82:6473597d706e 2249 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
bogdanm 82:6473597d706e 2250 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
bogdanm 82:6473597d706e 2251 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
bogdanm 82:6473597d706e 2252 uint8_t RESERVED_3[20];
bogdanm 82:6473597d706e 2253 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
bogdanm 82:6473597d706e 2254 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
bogdanm 82:6473597d706e 2255 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
bogdanm 82:6473597d706e 2256 uint8_t RESERVED_4[84];
bogdanm 82:6473597d706e 2257 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
bogdanm 82:6473597d706e 2258 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
bogdanm 82:6473597d706e 2259 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
bogdanm 82:6473597d706e 2260 uint8_t RESERVED_5[20];
bogdanm 82:6473597d706e 2261 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
bogdanm 82:6473597d706e 2262 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
bogdanm 82:6473597d706e 2263 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
bogdanm 82:6473597d706e 2264 uint8_t RESERVED_6[276];
bogdanm 82:6473597d706e 2265 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
bogdanm 82:6473597d706e 2266 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
bogdanm 82:6473597d706e 2267 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
bogdanm 82:6473597d706e 2268 uint8_t RESERVED_7[20];
bogdanm 82:6473597d706e 2269 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
bogdanm 82:6473597d706e 2270 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
bogdanm 82:6473597d706e 2271 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
bogdanm 82:6473597d706e 2272 } CAU_Type, *CAU_MemMapPtr;
bogdanm 82:6473597d706e 2273
bogdanm 82:6473597d706e 2274 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2275 -- CAU - Register accessor macros
bogdanm 82:6473597d706e 2276 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2277
bogdanm 82:6473597d706e 2278 /*!
bogdanm 82:6473597d706e 2279 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
bogdanm 82:6473597d706e 2280 * @{
bogdanm 82:6473597d706e 2281 */
bogdanm 82:6473597d706e 2282
bogdanm 82:6473597d706e 2283
bogdanm 82:6473597d706e 2284 /* CAU - Register accessors */
bogdanm 82:6473597d706e 2285 #define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
bogdanm 82:6473597d706e 2286 #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
bogdanm 82:6473597d706e 2287 #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
bogdanm 82:6473597d706e 2288 #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
bogdanm 82:6473597d706e 2289 #define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
bogdanm 82:6473597d706e 2290 #define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
bogdanm 82:6473597d706e 2291 #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
bogdanm 82:6473597d706e 2292 #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
bogdanm 82:6473597d706e 2293 #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
bogdanm 82:6473597d706e 2294 #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
bogdanm 82:6473597d706e 2295 #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
bogdanm 82:6473597d706e 2296 #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
bogdanm 82:6473597d706e 2297 #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
bogdanm 82:6473597d706e 2298 #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
bogdanm 82:6473597d706e 2299 #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
bogdanm 82:6473597d706e 2300 #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
bogdanm 82:6473597d706e 2301 #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
bogdanm 82:6473597d706e 2302 #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
bogdanm 82:6473597d706e 2303 #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
bogdanm 82:6473597d706e 2304 #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
bogdanm 82:6473597d706e 2305 #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
bogdanm 82:6473597d706e 2306 #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
bogdanm 82:6473597d706e 2307 #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
bogdanm 82:6473597d706e 2308 #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
bogdanm 82:6473597d706e 2309 #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
bogdanm 82:6473597d706e 2310
bogdanm 82:6473597d706e 2311 /*!
bogdanm 82:6473597d706e 2312 * @}
bogdanm 82:6473597d706e 2313 */ /* end of group CAU_Register_Accessor_Macros */
bogdanm 82:6473597d706e 2314
bogdanm 82:6473597d706e 2315
bogdanm 82:6473597d706e 2316 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2317 -- CAU Register Masks
bogdanm 82:6473597d706e 2318 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2319
bogdanm 82:6473597d706e 2320 /*!
bogdanm 82:6473597d706e 2321 * @addtogroup CAU_Register_Masks CAU Register Masks
bogdanm 82:6473597d706e 2322 * @{
bogdanm 82:6473597d706e 2323 */
bogdanm 82:6473597d706e 2324
bogdanm 82:6473597d706e 2325 /* LDR_CASR Bit Fields */
bogdanm 82:6473597d706e 2326 #define CAU_LDR_CASR_IC_MASK 0x1u
bogdanm 82:6473597d706e 2327 #define CAU_LDR_CASR_IC_SHIFT 0
bogdanm 82:6473597d706e 2328 #define CAU_LDR_CASR_DPE_MASK 0x2u
bogdanm 82:6473597d706e 2329 #define CAU_LDR_CASR_DPE_SHIFT 1
bogdanm 82:6473597d706e 2330 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
bogdanm 82:6473597d706e 2331 #define CAU_LDR_CASR_VER_SHIFT 28
bogdanm 82:6473597d706e 2332 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
bogdanm 82:6473597d706e 2333 /* STR_CASR Bit Fields */
bogdanm 82:6473597d706e 2334 #define CAU_STR_CASR_IC_MASK 0x1u
bogdanm 82:6473597d706e 2335 #define CAU_STR_CASR_IC_SHIFT 0
bogdanm 82:6473597d706e 2336 #define CAU_STR_CASR_DPE_MASK 0x2u
bogdanm 82:6473597d706e 2337 #define CAU_STR_CASR_DPE_SHIFT 1
bogdanm 82:6473597d706e 2338 #define CAU_STR_CASR_VER_MASK 0xF0000000u
bogdanm 82:6473597d706e 2339 #define CAU_STR_CASR_VER_SHIFT 28
bogdanm 82:6473597d706e 2340 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
bogdanm 82:6473597d706e 2341 /* ADR_CASR Bit Fields */
bogdanm 82:6473597d706e 2342 #define CAU_ADR_CASR_IC_MASK 0x1u
bogdanm 82:6473597d706e 2343 #define CAU_ADR_CASR_IC_SHIFT 0
bogdanm 82:6473597d706e 2344 #define CAU_ADR_CASR_DPE_MASK 0x2u
bogdanm 82:6473597d706e 2345 #define CAU_ADR_CASR_DPE_SHIFT 1
bogdanm 82:6473597d706e 2346 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
bogdanm 82:6473597d706e 2347 #define CAU_ADR_CASR_VER_SHIFT 28
bogdanm 82:6473597d706e 2348 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
bogdanm 82:6473597d706e 2349 /* RADR_CASR Bit Fields */
bogdanm 82:6473597d706e 2350 #define CAU_RADR_CASR_IC_MASK 0x1u
bogdanm 82:6473597d706e 2351 #define CAU_RADR_CASR_IC_SHIFT 0
bogdanm 82:6473597d706e 2352 #define CAU_RADR_CASR_DPE_MASK 0x2u
bogdanm 82:6473597d706e 2353 #define CAU_RADR_CASR_DPE_SHIFT 1
bogdanm 82:6473597d706e 2354 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
bogdanm 82:6473597d706e 2355 #define CAU_RADR_CASR_VER_SHIFT 28
bogdanm 82:6473597d706e 2356 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
bogdanm 82:6473597d706e 2357 /* XOR_CASR Bit Fields */
bogdanm 82:6473597d706e 2358 #define CAU_XOR_CASR_IC_MASK 0x1u
bogdanm 82:6473597d706e 2359 #define CAU_XOR_CASR_IC_SHIFT 0
bogdanm 82:6473597d706e 2360 #define CAU_XOR_CASR_DPE_MASK 0x2u
bogdanm 82:6473597d706e 2361 #define CAU_XOR_CASR_DPE_SHIFT 1
bogdanm 82:6473597d706e 2362 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
bogdanm 82:6473597d706e 2363 #define CAU_XOR_CASR_VER_SHIFT 28
bogdanm 82:6473597d706e 2364 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
bogdanm 82:6473597d706e 2365 /* ROTL_CASR Bit Fields */
bogdanm 82:6473597d706e 2366 #define CAU_ROTL_CASR_IC_MASK 0x1u
bogdanm 82:6473597d706e 2367 #define CAU_ROTL_CASR_IC_SHIFT 0
bogdanm 82:6473597d706e 2368 #define CAU_ROTL_CASR_DPE_MASK 0x2u
bogdanm 82:6473597d706e 2369 #define CAU_ROTL_CASR_DPE_SHIFT 1
bogdanm 82:6473597d706e 2370 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
bogdanm 82:6473597d706e 2371 #define CAU_ROTL_CASR_VER_SHIFT 28
bogdanm 82:6473597d706e 2372 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
bogdanm 82:6473597d706e 2373 /* AESC_CASR Bit Fields */
bogdanm 82:6473597d706e 2374 #define CAU_AESC_CASR_IC_MASK 0x1u
bogdanm 82:6473597d706e 2375 #define CAU_AESC_CASR_IC_SHIFT 0
bogdanm 82:6473597d706e 2376 #define CAU_AESC_CASR_DPE_MASK 0x2u
bogdanm 82:6473597d706e 2377 #define CAU_AESC_CASR_DPE_SHIFT 1
bogdanm 82:6473597d706e 2378 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
bogdanm 82:6473597d706e 2379 #define CAU_AESC_CASR_VER_SHIFT 28
bogdanm 82:6473597d706e 2380 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
bogdanm 82:6473597d706e 2381 /* AESIC_CASR Bit Fields */
bogdanm 82:6473597d706e 2382 #define CAU_AESIC_CASR_IC_MASK 0x1u
bogdanm 82:6473597d706e 2383 #define CAU_AESIC_CASR_IC_SHIFT 0
bogdanm 82:6473597d706e 2384 #define CAU_AESIC_CASR_DPE_MASK 0x2u
bogdanm 82:6473597d706e 2385 #define CAU_AESIC_CASR_DPE_SHIFT 1
bogdanm 82:6473597d706e 2386 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
bogdanm 82:6473597d706e 2387 #define CAU_AESIC_CASR_VER_SHIFT 28
bogdanm 82:6473597d706e 2388 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
bogdanm 82:6473597d706e 2389
bogdanm 82:6473597d706e 2390 /*!
bogdanm 82:6473597d706e 2391 * @}
bogdanm 82:6473597d706e 2392 */ /* end of group CAU_Register_Masks */
bogdanm 82:6473597d706e 2393
bogdanm 82:6473597d706e 2394
bogdanm 82:6473597d706e 2395 /* CAU - Peripheral instance base addresses */
bogdanm 82:6473597d706e 2396 /** Peripheral CAU base address */
bogdanm 82:6473597d706e 2397 #define CAU_BASE (0xE0081000u)
bogdanm 82:6473597d706e 2398 /** Peripheral CAU base pointer */
bogdanm 82:6473597d706e 2399 #define CAU ((CAU_Type *)CAU_BASE)
bogdanm 82:6473597d706e 2400 #define CAU_BASE_PTR (CAU)
bogdanm 82:6473597d706e 2401 /** Array initializer of CAU peripheral base pointers */
bogdanm 82:6473597d706e 2402 #define CAU_BASES { CAU }
bogdanm 82:6473597d706e 2403
bogdanm 82:6473597d706e 2404 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2405 -- CAU - Register accessor macros
bogdanm 82:6473597d706e 2406 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2407
bogdanm 82:6473597d706e 2408 /*!
bogdanm 82:6473597d706e 2409 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
bogdanm 82:6473597d706e 2410 * @{
bogdanm 82:6473597d706e 2411 */
bogdanm 82:6473597d706e 2412
bogdanm 82:6473597d706e 2413
bogdanm 82:6473597d706e 2414 /* CAU - Register instance definitions */
bogdanm 82:6473597d706e 2415 /* CAU */
bogdanm 82:6473597d706e 2416 #define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
bogdanm 82:6473597d706e 2417 #define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
bogdanm 82:6473597d706e 2418 #define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
bogdanm 82:6473597d706e 2419 #define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
bogdanm 82:6473597d706e 2420 #define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
bogdanm 82:6473597d706e 2421 #define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
bogdanm 82:6473597d706e 2422 #define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
bogdanm 82:6473597d706e 2423 #define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
bogdanm 82:6473597d706e 2424 #define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
bogdanm 82:6473597d706e 2425 #define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
bogdanm 82:6473597d706e 2426 #define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
bogdanm 82:6473597d706e 2427 #define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
bogdanm 82:6473597d706e 2428 #define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
bogdanm 82:6473597d706e 2429 #define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
bogdanm 82:6473597d706e 2430 #define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
bogdanm 82:6473597d706e 2431 #define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
bogdanm 82:6473597d706e 2432 #define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
bogdanm 82:6473597d706e 2433 #define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
bogdanm 82:6473597d706e 2434 #define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
bogdanm 82:6473597d706e 2435 #define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
bogdanm 82:6473597d706e 2436 #define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
bogdanm 82:6473597d706e 2437 #define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
bogdanm 82:6473597d706e 2438 #define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
bogdanm 82:6473597d706e 2439 #define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
bogdanm 82:6473597d706e 2440 #define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
bogdanm 82:6473597d706e 2441 #define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
bogdanm 82:6473597d706e 2442 #define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
bogdanm 82:6473597d706e 2443 #define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
bogdanm 82:6473597d706e 2444 #define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
bogdanm 82:6473597d706e 2445 #define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
bogdanm 82:6473597d706e 2446 #define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
bogdanm 82:6473597d706e 2447 #define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
bogdanm 82:6473597d706e 2448 #define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
bogdanm 82:6473597d706e 2449 #define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
bogdanm 82:6473597d706e 2450 #define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
bogdanm 82:6473597d706e 2451 #define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
bogdanm 82:6473597d706e 2452 #define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
bogdanm 82:6473597d706e 2453 #define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
bogdanm 82:6473597d706e 2454 #define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
bogdanm 82:6473597d706e 2455 #define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
bogdanm 82:6473597d706e 2456 #define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
bogdanm 82:6473597d706e 2457 #define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
bogdanm 82:6473597d706e 2458 #define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
bogdanm 82:6473597d706e 2459 #define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
bogdanm 82:6473597d706e 2460 #define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
bogdanm 82:6473597d706e 2461 #define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
bogdanm 82:6473597d706e 2462 #define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
bogdanm 82:6473597d706e 2463 #define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
bogdanm 82:6473597d706e 2464 #define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
bogdanm 82:6473597d706e 2465 #define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
bogdanm 82:6473597d706e 2466 #define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
bogdanm 82:6473597d706e 2467 #define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
bogdanm 82:6473597d706e 2468 #define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
bogdanm 82:6473597d706e 2469 #define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
bogdanm 82:6473597d706e 2470 #define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
bogdanm 82:6473597d706e 2471 #define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
bogdanm 82:6473597d706e 2472 #define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
bogdanm 82:6473597d706e 2473 #define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
bogdanm 82:6473597d706e 2474 #define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
bogdanm 82:6473597d706e 2475 #define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
bogdanm 82:6473597d706e 2476 #define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
bogdanm 82:6473597d706e 2477 #define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
bogdanm 82:6473597d706e 2478 #define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
bogdanm 82:6473597d706e 2479 #define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
bogdanm 82:6473597d706e 2480 #define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
bogdanm 82:6473597d706e 2481 #define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
bogdanm 82:6473597d706e 2482 #define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
bogdanm 82:6473597d706e 2483 #define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
bogdanm 82:6473597d706e 2484 #define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
bogdanm 82:6473597d706e 2485 #define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
bogdanm 82:6473597d706e 2486 #define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
bogdanm 82:6473597d706e 2487 #define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
bogdanm 82:6473597d706e 2488 #define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
bogdanm 82:6473597d706e 2489 #define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
bogdanm 82:6473597d706e 2490 #define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
bogdanm 82:6473597d706e 2491 #define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
bogdanm 82:6473597d706e 2492 #define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
bogdanm 82:6473597d706e 2493 #define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
bogdanm 82:6473597d706e 2494 #define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
bogdanm 82:6473597d706e 2495 #define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
bogdanm 82:6473597d706e 2496 #define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
bogdanm 82:6473597d706e 2497 #define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
bogdanm 82:6473597d706e 2498 #define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
bogdanm 82:6473597d706e 2499 #define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
bogdanm 82:6473597d706e 2500 #define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
bogdanm 82:6473597d706e 2501 #define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
bogdanm 82:6473597d706e 2502 #define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
bogdanm 82:6473597d706e 2503 #define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
bogdanm 82:6473597d706e 2504 #define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
bogdanm 82:6473597d706e 2505 #define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
bogdanm 82:6473597d706e 2506 #define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
bogdanm 82:6473597d706e 2507 #define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
bogdanm 82:6473597d706e 2508 #define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
bogdanm 82:6473597d706e 2509 #define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
bogdanm 82:6473597d706e 2510 #define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
bogdanm 82:6473597d706e 2511 #define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
bogdanm 82:6473597d706e 2512 #define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
bogdanm 82:6473597d706e 2513 #define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
bogdanm 82:6473597d706e 2514 #define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
bogdanm 82:6473597d706e 2515 #define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
bogdanm 82:6473597d706e 2516 #define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
bogdanm 82:6473597d706e 2517 #define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
bogdanm 82:6473597d706e 2518 #define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
bogdanm 82:6473597d706e 2519 #define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
bogdanm 82:6473597d706e 2520
bogdanm 82:6473597d706e 2521 /* CAU - Register array accessors */
bogdanm 82:6473597d706e 2522 #define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
bogdanm 82:6473597d706e 2523 #define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
bogdanm 82:6473597d706e 2524 #define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
bogdanm 82:6473597d706e 2525 #define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
bogdanm 82:6473597d706e 2526 #define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
bogdanm 82:6473597d706e 2527 #define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
bogdanm 82:6473597d706e 2528 #define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
bogdanm 82:6473597d706e 2529 #define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
bogdanm 82:6473597d706e 2530 #define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
bogdanm 82:6473597d706e 2531
bogdanm 82:6473597d706e 2532 /*!
bogdanm 82:6473597d706e 2533 * @}
bogdanm 82:6473597d706e 2534 */ /* end of group CAU_Register_Accessor_Macros */
bogdanm 82:6473597d706e 2535
bogdanm 82:6473597d706e 2536
bogdanm 82:6473597d706e 2537 /*!
bogdanm 82:6473597d706e 2538 * @}
bogdanm 82:6473597d706e 2539 */ /* end of group CAU_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 2540
bogdanm 82:6473597d706e 2541
bogdanm 82:6473597d706e 2542 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2543 -- CMP Peripheral Access Layer
bogdanm 82:6473597d706e 2544 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2545
bogdanm 82:6473597d706e 2546 /*!
bogdanm 82:6473597d706e 2547 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
bogdanm 82:6473597d706e 2548 * @{
bogdanm 82:6473597d706e 2549 */
bogdanm 82:6473597d706e 2550
bogdanm 82:6473597d706e 2551 /** CMP - Register Layout Typedef */
bogdanm 82:6473597d706e 2552 typedef struct {
bogdanm 82:6473597d706e 2553 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
bogdanm 82:6473597d706e 2554 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
bogdanm 82:6473597d706e 2555 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
bogdanm 82:6473597d706e 2556 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
bogdanm 82:6473597d706e 2557 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
bogdanm 82:6473597d706e 2558 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
bogdanm 82:6473597d706e 2559 } CMP_Type, *CMP_MemMapPtr;
bogdanm 82:6473597d706e 2560
bogdanm 82:6473597d706e 2561 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2562 -- CMP - Register accessor macros
bogdanm 82:6473597d706e 2563 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2564
bogdanm 82:6473597d706e 2565 /*!
bogdanm 82:6473597d706e 2566 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
bogdanm 82:6473597d706e 2567 * @{
bogdanm 82:6473597d706e 2568 */
bogdanm 82:6473597d706e 2569
bogdanm 82:6473597d706e 2570
bogdanm 82:6473597d706e 2571 /* CMP - Register accessors */
bogdanm 82:6473597d706e 2572 #define CMP_CR0_REG(base) ((base)->CR0)
bogdanm 82:6473597d706e 2573 #define CMP_CR1_REG(base) ((base)->CR1)
bogdanm 82:6473597d706e 2574 #define CMP_FPR_REG(base) ((base)->FPR)
bogdanm 82:6473597d706e 2575 #define CMP_SCR_REG(base) ((base)->SCR)
bogdanm 82:6473597d706e 2576 #define CMP_DACCR_REG(base) ((base)->DACCR)
bogdanm 82:6473597d706e 2577 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
bogdanm 82:6473597d706e 2578
bogdanm 82:6473597d706e 2579 /*!
bogdanm 82:6473597d706e 2580 * @}
bogdanm 82:6473597d706e 2581 */ /* end of group CMP_Register_Accessor_Macros */
bogdanm 82:6473597d706e 2582
bogdanm 82:6473597d706e 2583
bogdanm 82:6473597d706e 2584 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2585 -- CMP Register Masks
bogdanm 82:6473597d706e 2586 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2587
bogdanm 82:6473597d706e 2588 /*!
bogdanm 82:6473597d706e 2589 * @addtogroup CMP_Register_Masks CMP Register Masks
bogdanm 82:6473597d706e 2590 * @{
bogdanm 82:6473597d706e 2591 */
bogdanm 82:6473597d706e 2592
bogdanm 82:6473597d706e 2593 /* CR0 Bit Fields */
bogdanm 82:6473597d706e 2594 #define CMP_CR0_HYSTCTR_MASK 0x3u
bogdanm 82:6473597d706e 2595 #define CMP_CR0_HYSTCTR_SHIFT 0
bogdanm 82:6473597d706e 2596 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
bogdanm 82:6473597d706e 2597 #define CMP_CR0_FILTER_CNT_MASK 0x70u
bogdanm 82:6473597d706e 2598 #define CMP_CR0_FILTER_CNT_SHIFT 4
bogdanm 82:6473597d706e 2599 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
bogdanm 82:6473597d706e 2600 /* CR1 Bit Fields */
bogdanm 82:6473597d706e 2601 #define CMP_CR1_EN_MASK 0x1u
bogdanm 82:6473597d706e 2602 #define CMP_CR1_EN_SHIFT 0
bogdanm 82:6473597d706e 2603 #define CMP_CR1_OPE_MASK 0x2u
bogdanm 82:6473597d706e 2604 #define CMP_CR1_OPE_SHIFT 1
bogdanm 82:6473597d706e 2605 #define CMP_CR1_COS_MASK 0x4u
bogdanm 82:6473597d706e 2606 #define CMP_CR1_COS_SHIFT 2
bogdanm 82:6473597d706e 2607 #define CMP_CR1_INV_MASK 0x8u
bogdanm 82:6473597d706e 2608 #define CMP_CR1_INV_SHIFT 3
bogdanm 82:6473597d706e 2609 #define CMP_CR1_PMODE_MASK 0x10u
bogdanm 82:6473597d706e 2610 #define CMP_CR1_PMODE_SHIFT 4
bogdanm 82:6473597d706e 2611 #define CMP_CR1_WE_MASK 0x40u
bogdanm 82:6473597d706e 2612 #define CMP_CR1_WE_SHIFT 6
bogdanm 82:6473597d706e 2613 #define CMP_CR1_SE_MASK 0x80u
bogdanm 82:6473597d706e 2614 #define CMP_CR1_SE_SHIFT 7
bogdanm 82:6473597d706e 2615 /* FPR Bit Fields */
bogdanm 82:6473597d706e 2616 #define CMP_FPR_FILT_PER_MASK 0xFFu
bogdanm 82:6473597d706e 2617 #define CMP_FPR_FILT_PER_SHIFT 0
bogdanm 82:6473597d706e 2618 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
bogdanm 82:6473597d706e 2619 /* SCR Bit Fields */
bogdanm 82:6473597d706e 2620 #define CMP_SCR_COUT_MASK 0x1u
bogdanm 82:6473597d706e 2621 #define CMP_SCR_COUT_SHIFT 0
bogdanm 82:6473597d706e 2622 #define CMP_SCR_CFF_MASK 0x2u
bogdanm 82:6473597d706e 2623 #define CMP_SCR_CFF_SHIFT 1
bogdanm 82:6473597d706e 2624 #define CMP_SCR_CFR_MASK 0x4u
bogdanm 82:6473597d706e 2625 #define CMP_SCR_CFR_SHIFT 2
bogdanm 82:6473597d706e 2626 #define CMP_SCR_IEF_MASK 0x8u
bogdanm 82:6473597d706e 2627 #define CMP_SCR_IEF_SHIFT 3
bogdanm 82:6473597d706e 2628 #define CMP_SCR_IER_MASK 0x10u
bogdanm 82:6473597d706e 2629 #define CMP_SCR_IER_SHIFT 4
bogdanm 82:6473597d706e 2630 #define CMP_SCR_DMAEN_MASK 0x40u
bogdanm 82:6473597d706e 2631 #define CMP_SCR_DMAEN_SHIFT 6
bogdanm 82:6473597d706e 2632 /* DACCR Bit Fields */
bogdanm 82:6473597d706e 2633 #define CMP_DACCR_VOSEL_MASK 0x3Fu
bogdanm 82:6473597d706e 2634 #define CMP_DACCR_VOSEL_SHIFT 0
bogdanm 82:6473597d706e 2635 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
bogdanm 82:6473597d706e 2636 #define CMP_DACCR_VRSEL_MASK 0x40u
bogdanm 82:6473597d706e 2637 #define CMP_DACCR_VRSEL_SHIFT 6
bogdanm 82:6473597d706e 2638 #define CMP_DACCR_DACEN_MASK 0x80u
bogdanm 82:6473597d706e 2639 #define CMP_DACCR_DACEN_SHIFT 7
bogdanm 82:6473597d706e 2640 /* MUXCR Bit Fields */
bogdanm 82:6473597d706e 2641 #define CMP_MUXCR_MSEL_MASK 0x7u
bogdanm 82:6473597d706e 2642 #define CMP_MUXCR_MSEL_SHIFT 0
bogdanm 82:6473597d706e 2643 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
bogdanm 82:6473597d706e 2644 #define CMP_MUXCR_PSEL_MASK 0x38u
bogdanm 82:6473597d706e 2645 #define CMP_MUXCR_PSEL_SHIFT 3
bogdanm 82:6473597d706e 2646 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
bogdanm 82:6473597d706e 2647 #define CMP_MUXCR_PSTM_MASK 0x80u
bogdanm 82:6473597d706e 2648 #define CMP_MUXCR_PSTM_SHIFT 7
bogdanm 82:6473597d706e 2649
bogdanm 82:6473597d706e 2650 /*!
bogdanm 82:6473597d706e 2651 * @}
bogdanm 82:6473597d706e 2652 */ /* end of group CMP_Register_Masks */
bogdanm 82:6473597d706e 2653
bogdanm 82:6473597d706e 2654
bogdanm 82:6473597d706e 2655 /* CMP - Peripheral instance base addresses */
bogdanm 82:6473597d706e 2656 /** Peripheral CMP0 base address */
bogdanm 82:6473597d706e 2657 #define CMP0_BASE (0x40073000u)
bogdanm 82:6473597d706e 2658 /** Peripheral CMP0 base pointer */
bogdanm 82:6473597d706e 2659 #define CMP0 ((CMP_Type *)CMP0_BASE)
bogdanm 82:6473597d706e 2660 #define CMP0_BASE_PTR (CMP0)
bogdanm 82:6473597d706e 2661 /** Peripheral CMP1 base address */
bogdanm 82:6473597d706e 2662 #define CMP1_BASE (0x40073008u)
bogdanm 82:6473597d706e 2663 /** Peripheral CMP1 base pointer */
bogdanm 82:6473597d706e 2664 #define CMP1 ((CMP_Type *)CMP1_BASE)
bogdanm 82:6473597d706e 2665 #define CMP1_BASE_PTR (CMP1)
bogdanm 82:6473597d706e 2666 /** Peripheral CMP2 base address */
bogdanm 82:6473597d706e 2667 #define CMP2_BASE (0x40073010u)
bogdanm 82:6473597d706e 2668 /** Peripheral CMP2 base pointer */
bogdanm 82:6473597d706e 2669 #define CMP2 ((CMP_Type *)CMP2_BASE)
bogdanm 82:6473597d706e 2670 #define CMP2_BASE_PTR (CMP2)
bogdanm 82:6473597d706e 2671 /** Array initializer of CMP peripheral base pointers */
bogdanm 82:6473597d706e 2672 #define CMP_BASES { CMP0, CMP1, CMP2 }
bogdanm 82:6473597d706e 2673
bogdanm 82:6473597d706e 2674 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2675 -- CMP - Register accessor macros
bogdanm 82:6473597d706e 2676 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2677
bogdanm 82:6473597d706e 2678 /*!
bogdanm 82:6473597d706e 2679 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
bogdanm 82:6473597d706e 2680 * @{
bogdanm 82:6473597d706e 2681 */
bogdanm 82:6473597d706e 2682
bogdanm 82:6473597d706e 2683
bogdanm 82:6473597d706e 2684 /* CMP - Register instance definitions */
bogdanm 82:6473597d706e 2685 /* CMP0 */
bogdanm 82:6473597d706e 2686 #define CMP0_CR0 CMP_CR0_REG(CMP0)
bogdanm 82:6473597d706e 2687 #define CMP0_CR1 CMP_CR1_REG(CMP0)
bogdanm 82:6473597d706e 2688 #define CMP0_FPR CMP_FPR_REG(CMP0)
bogdanm 82:6473597d706e 2689 #define CMP0_SCR CMP_SCR_REG(CMP0)
bogdanm 82:6473597d706e 2690 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
bogdanm 82:6473597d706e 2691 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
bogdanm 82:6473597d706e 2692 /* CMP1 */
bogdanm 82:6473597d706e 2693 #define CMP1_CR0 CMP_CR0_REG(CMP1)
bogdanm 82:6473597d706e 2694 #define CMP1_CR1 CMP_CR1_REG(CMP1)
bogdanm 82:6473597d706e 2695 #define CMP1_FPR CMP_FPR_REG(CMP1)
bogdanm 82:6473597d706e 2696 #define CMP1_SCR CMP_SCR_REG(CMP1)
bogdanm 82:6473597d706e 2697 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
bogdanm 82:6473597d706e 2698 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
bogdanm 82:6473597d706e 2699 /* CMP2 */
bogdanm 82:6473597d706e 2700 #define CMP2_CR0 CMP_CR0_REG(CMP2)
bogdanm 82:6473597d706e 2701 #define CMP2_CR1 CMP_CR1_REG(CMP2)
bogdanm 82:6473597d706e 2702 #define CMP2_FPR CMP_FPR_REG(CMP2)
bogdanm 82:6473597d706e 2703 #define CMP2_SCR CMP_SCR_REG(CMP2)
bogdanm 82:6473597d706e 2704 #define CMP2_DACCR CMP_DACCR_REG(CMP2)
bogdanm 82:6473597d706e 2705 #define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
bogdanm 82:6473597d706e 2706
bogdanm 82:6473597d706e 2707 /*!
bogdanm 82:6473597d706e 2708 * @}
bogdanm 82:6473597d706e 2709 */ /* end of group CMP_Register_Accessor_Macros */
bogdanm 82:6473597d706e 2710
bogdanm 82:6473597d706e 2711
bogdanm 82:6473597d706e 2712 /*!
bogdanm 82:6473597d706e 2713 * @}
bogdanm 82:6473597d706e 2714 */ /* end of group CMP_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 2715
bogdanm 82:6473597d706e 2716
bogdanm 82:6473597d706e 2717 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2718 -- CMT Peripheral Access Layer
bogdanm 82:6473597d706e 2719 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2720
bogdanm 82:6473597d706e 2721 /*!
bogdanm 82:6473597d706e 2722 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
bogdanm 82:6473597d706e 2723 * @{
bogdanm 82:6473597d706e 2724 */
bogdanm 82:6473597d706e 2725
bogdanm 82:6473597d706e 2726 /** CMT - Register Layout Typedef */
bogdanm 82:6473597d706e 2727 typedef struct {
bogdanm 82:6473597d706e 2728 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
bogdanm 82:6473597d706e 2729 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
bogdanm 82:6473597d706e 2730 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
bogdanm 82:6473597d706e 2731 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
bogdanm 82:6473597d706e 2732 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
bogdanm 82:6473597d706e 2733 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
bogdanm 82:6473597d706e 2734 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
bogdanm 82:6473597d706e 2735 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
bogdanm 82:6473597d706e 2736 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
bogdanm 82:6473597d706e 2737 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
bogdanm 82:6473597d706e 2738 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
bogdanm 82:6473597d706e 2739 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
bogdanm 82:6473597d706e 2740 } CMT_Type, *CMT_MemMapPtr;
bogdanm 82:6473597d706e 2741
bogdanm 82:6473597d706e 2742 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2743 -- CMT - Register accessor macros
bogdanm 82:6473597d706e 2744 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2745
bogdanm 82:6473597d706e 2746 /*!
bogdanm 82:6473597d706e 2747 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
bogdanm 82:6473597d706e 2748 * @{
bogdanm 82:6473597d706e 2749 */
bogdanm 82:6473597d706e 2750
bogdanm 82:6473597d706e 2751
bogdanm 82:6473597d706e 2752 /* CMT - Register accessors */
bogdanm 82:6473597d706e 2753 #define CMT_CGH1_REG(base) ((base)->CGH1)
bogdanm 82:6473597d706e 2754 #define CMT_CGL1_REG(base) ((base)->CGL1)
bogdanm 82:6473597d706e 2755 #define CMT_CGH2_REG(base) ((base)->CGH2)
bogdanm 82:6473597d706e 2756 #define CMT_CGL2_REG(base) ((base)->CGL2)
bogdanm 82:6473597d706e 2757 #define CMT_OC_REG(base) ((base)->OC)
bogdanm 82:6473597d706e 2758 #define CMT_MSC_REG(base) ((base)->MSC)
bogdanm 82:6473597d706e 2759 #define CMT_CMD1_REG(base) ((base)->CMD1)
bogdanm 82:6473597d706e 2760 #define CMT_CMD2_REG(base) ((base)->CMD2)
bogdanm 82:6473597d706e 2761 #define CMT_CMD3_REG(base) ((base)->CMD3)
bogdanm 82:6473597d706e 2762 #define CMT_CMD4_REG(base) ((base)->CMD4)
bogdanm 82:6473597d706e 2763 #define CMT_PPS_REG(base) ((base)->PPS)
bogdanm 82:6473597d706e 2764 #define CMT_DMA_REG(base) ((base)->DMA)
bogdanm 82:6473597d706e 2765
bogdanm 82:6473597d706e 2766 /*!
bogdanm 82:6473597d706e 2767 * @}
bogdanm 82:6473597d706e 2768 */ /* end of group CMT_Register_Accessor_Macros */
bogdanm 82:6473597d706e 2769
bogdanm 82:6473597d706e 2770
bogdanm 82:6473597d706e 2771 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2772 -- CMT Register Masks
bogdanm 82:6473597d706e 2773 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2774
bogdanm 82:6473597d706e 2775 /*!
bogdanm 82:6473597d706e 2776 * @addtogroup CMT_Register_Masks CMT Register Masks
bogdanm 82:6473597d706e 2777 * @{
bogdanm 82:6473597d706e 2778 */
bogdanm 82:6473597d706e 2779
bogdanm 82:6473597d706e 2780 /* CGH1 Bit Fields */
bogdanm 82:6473597d706e 2781 #define CMT_CGH1_PH_MASK 0xFFu
bogdanm 82:6473597d706e 2782 #define CMT_CGH1_PH_SHIFT 0
bogdanm 82:6473597d706e 2783 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
bogdanm 82:6473597d706e 2784 /* CGL1 Bit Fields */
bogdanm 82:6473597d706e 2785 #define CMT_CGL1_PL_MASK 0xFFu
bogdanm 82:6473597d706e 2786 #define CMT_CGL1_PL_SHIFT 0
bogdanm 82:6473597d706e 2787 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
bogdanm 82:6473597d706e 2788 /* CGH2 Bit Fields */
bogdanm 82:6473597d706e 2789 #define CMT_CGH2_SH_MASK 0xFFu
bogdanm 82:6473597d706e 2790 #define CMT_CGH2_SH_SHIFT 0
bogdanm 82:6473597d706e 2791 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
bogdanm 82:6473597d706e 2792 /* CGL2 Bit Fields */
bogdanm 82:6473597d706e 2793 #define CMT_CGL2_SL_MASK 0xFFu
bogdanm 82:6473597d706e 2794 #define CMT_CGL2_SL_SHIFT 0
bogdanm 82:6473597d706e 2795 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
bogdanm 82:6473597d706e 2796 /* OC Bit Fields */
bogdanm 82:6473597d706e 2797 #define CMT_OC_IROPEN_MASK 0x20u
bogdanm 82:6473597d706e 2798 #define CMT_OC_IROPEN_SHIFT 5
bogdanm 82:6473597d706e 2799 #define CMT_OC_CMTPOL_MASK 0x40u
bogdanm 82:6473597d706e 2800 #define CMT_OC_CMTPOL_SHIFT 6
bogdanm 82:6473597d706e 2801 #define CMT_OC_IROL_MASK 0x80u
bogdanm 82:6473597d706e 2802 #define CMT_OC_IROL_SHIFT 7
bogdanm 82:6473597d706e 2803 /* MSC Bit Fields */
bogdanm 82:6473597d706e 2804 #define CMT_MSC_MCGEN_MASK 0x1u
bogdanm 82:6473597d706e 2805 #define CMT_MSC_MCGEN_SHIFT 0
bogdanm 82:6473597d706e 2806 #define CMT_MSC_EOCIE_MASK 0x2u
bogdanm 82:6473597d706e 2807 #define CMT_MSC_EOCIE_SHIFT 1
bogdanm 82:6473597d706e 2808 #define CMT_MSC_FSK_MASK 0x4u
bogdanm 82:6473597d706e 2809 #define CMT_MSC_FSK_SHIFT 2
bogdanm 82:6473597d706e 2810 #define CMT_MSC_BASE_MASK 0x8u
bogdanm 82:6473597d706e 2811 #define CMT_MSC_BASE_SHIFT 3
bogdanm 82:6473597d706e 2812 #define CMT_MSC_EXSPC_MASK 0x10u
bogdanm 82:6473597d706e 2813 #define CMT_MSC_EXSPC_SHIFT 4
bogdanm 82:6473597d706e 2814 #define CMT_MSC_CMTDIV_MASK 0x60u
bogdanm 82:6473597d706e 2815 #define CMT_MSC_CMTDIV_SHIFT 5
bogdanm 82:6473597d706e 2816 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
bogdanm 82:6473597d706e 2817 #define CMT_MSC_EOCF_MASK 0x80u
bogdanm 82:6473597d706e 2818 #define CMT_MSC_EOCF_SHIFT 7
bogdanm 82:6473597d706e 2819 /* CMD1 Bit Fields */
bogdanm 82:6473597d706e 2820 #define CMT_CMD1_MB_MASK 0xFFu
bogdanm 82:6473597d706e 2821 #define CMT_CMD1_MB_SHIFT 0
bogdanm 82:6473597d706e 2822 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
bogdanm 82:6473597d706e 2823 /* CMD2 Bit Fields */
bogdanm 82:6473597d706e 2824 #define CMT_CMD2_MB_MASK 0xFFu
bogdanm 82:6473597d706e 2825 #define CMT_CMD2_MB_SHIFT 0
bogdanm 82:6473597d706e 2826 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
bogdanm 82:6473597d706e 2827 /* CMD3 Bit Fields */
bogdanm 82:6473597d706e 2828 #define CMT_CMD3_SB_MASK 0xFFu
bogdanm 82:6473597d706e 2829 #define CMT_CMD3_SB_SHIFT 0
bogdanm 82:6473597d706e 2830 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
bogdanm 82:6473597d706e 2831 /* CMD4 Bit Fields */
bogdanm 82:6473597d706e 2832 #define CMT_CMD4_SB_MASK 0xFFu
bogdanm 82:6473597d706e 2833 #define CMT_CMD4_SB_SHIFT 0
bogdanm 82:6473597d706e 2834 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
bogdanm 82:6473597d706e 2835 /* PPS Bit Fields */
bogdanm 82:6473597d706e 2836 #define CMT_PPS_PPSDIV_MASK 0xFu
bogdanm 82:6473597d706e 2837 #define CMT_PPS_PPSDIV_SHIFT 0
bogdanm 82:6473597d706e 2838 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
bogdanm 82:6473597d706e 2839 /* DMA Bit Fields */
bogdanm 82:6473597d706e 2840 #define CMT_DMA_DMA_MASK 0x1u
bogdanm 82:6473597d706e 2841 #define CMT_DMA_DMA_SHIFT 0
bogdanm 82:6473597d706e 2842
bogdanm 82:6473597d706e 2843 /*!
bogdanm 82:6473597d706e 2844 * @}
bogdanm 82:6473597d706e 2845 */ /* end of group CMT_Register_Masks */
bogdanm 82:6473597d706e 2846
bogdanm 82:6473597d706e 2847
bogdanm 82:6473597d706e 2848 /* CMT - Peripheral instance base addresses */
bogdanm 82:6473597d706e 2849 /** Peripheral CMT base address */
bogdanm 82:6473597d706e 2850 #define CMT_BASE (0x40062000u)
bogdanm 82:6473597d706e 2851 /** Peripheral CMT base pointer */
bogdanm 82:6473597d706e 2852 #define CMT ((CMT_Type *)CMT_BASE)
bogdanm 82:6473597d706e 2853 #define CMT_BASE_PTR (CMT)
bogdanm 82:6473597d706e 2854 /** Array initializer of CMT peripheral base pointers */
bogdanm 82:6473597d706e 2855 #define CMT_BASES { CMT }
bogdanm 82:6473597d706e 2856
bogdanm 82:6473597d706e 2857 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2858 -- CMT - Register accessor macros
bogdanm 82:6473597d706e 2859 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2860
bogdanm 82:6473597d706e 2861 /*!
bogdanm 82:6473597d706e 2862 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
bogdanm 82:6473597d706e 2863 * @{
bogdanm 82:6473597d706e 2864 */
bogdanm 82:6473597d706e 2865
bogdanm 82:6473597d706e 2866
bogdanm 82:6473597d706e 2867 /* CMT - Register instance definitions */
bogdanm 82:6473597d706e 2868 /* CMT */
bogdanm 82:6473597d706e 2869 #define CMT_CGH1 CMT_CGH1_REG(CMT)
bogdanm 82:6473597d706e 2870 #define CMT_CGL1 CMT_CGL1_REG(CMT)
bogdanm 82:6473597d706e 2871 #define CMT_CGH2 CMT_CGH2_REG(CMT)
bogdanm 82:6473597d706e 2872 #define CMT_CGL2 CMT_CGL2_REG(CMT)
bogdanm 82:6473597d706e 2873 #define CMT_OC CMT_OC_REG(CMT)
bogdanm 82:6473597d706e 2874 #define CMT_MSC CMT_MSC_REG(CMT)
bogdanm 82:6473597d706e 2875 #define CMT_CMD1 CMT_CMD1_REG(CMT)
bogdanm 82:6473597d706e 2876 #define CMT_CMD2 CMT_CMD2_REG(CMT)
bogdanm 82:6473597d706e 2877 #define CMT_CMD3 CMT_CMD3_REG(CMT)
bogdanm 82:6473597d706e 2878 #define CMT_CMD4 CMT_CMD4_REG(CMT)
bogdanm 82:6473597d706e 2879 #define CMT_PPS CMT_PPS_REG(CMT)
bogdanm 82:6473597d706e 2880 #define CMT_DMA CMT_DMA_REG(CMT)
bogdanm 82:6473597d706e 2881
bogdanm 82:6473597d706e 2882 /*!
bogdanm 82:6473597d706e 2883 * @}
bogdanm 82:6473597d706e 2884 */ /* end of group CMT_Register_Accessor_Macros */
bogdanm 82:6473597d706e 2885
bogdanm 82:6473597d706e 2886
bogdanm 82:6473597d706e 2887 /*!
bogdanm 82:6473597d706e 2888 * @}
bogdanm 82:6473597d706e 2889 */ /* end of group CMT_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 2890
bogdanm 82:6473597d706e 2891
bogdanm 82:6473597d706e 2892 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2893 -- CRC Peripheral Access Layer
bogdanm 82:6473597d706e 2894 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2895
bogdanm 82:6473597d706e 2896 /*!
bogdanm 82:6473597d706e 2897 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
bogdanm 82:6473597d706e 2898 * @{
bogdanm 82:6473597d706e 2899 */
bogdanm 82:6473597d706e 2900
bogdanm 82:6473597d706e 2901 /** CRC - Register Layout Typedef */
bogdanm 82:6473597d706e 2902 typedef struct {
bogdanm 82:6473597d706e 2903 union { /* offset: 0x0 */
bogdanm 82:6473597d706e 2904 struct { /* offset: 0x0 */
bogdanm 82:6473597d706e 2905 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
bogdanm 82:6473597d706e 2906 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
bogdanm 82:6473597d706e 2907 } ACCESS16BIT;
bogdanm 82:6473597d706e 2908 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
bogdanm 82:6473597d706e 2909 struct { /* offset: 0x0 */
bogdanm 82:6473597d706e 2910 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
bogdanm 82:6473597d706e 2911 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
bogdanm 82:6473597d706e 2912 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
bogdanm 82:6473597d706e 2913 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
bogdanm 82:6473597d706e 2914 } ACCESS8BIT;
bogdanm 82:6473597d706e 2915 };
bogdanm 82:6473597d706e 2916 union { /* offset: 0x4 */
bogdanm 82:6473597d706e 2917 struct { /* offset: 0x4 */
bogdanm 82:6473597d706e 2918 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
bogdanm 82:6473597d706e 2919 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
bogdanm 82:6473597d706e 2920 } GPOLY_ACCESS16BIT;
bogdanm 82:6473597d706e 2921 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
bogdanm 82:6473597d706e 2922 struct { /* offset: 0x4 */
bogdanm 82:6473597d706e 2923 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
bogdanm 82:6473597d706e 2924 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
bogdanm 82:6473597d706e 2925 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
bogdanm 82:6473597d706e 2926 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
bogdanm 82:6473597d706e 2927 } GPOLY_ACCESS8BIT;
bogdanm 82:6473597d706e 2928 };
bogdanm 82:6473597d706e 2929 union { /* offset: 0x8 */
bogdanm 82:6473597d706e 2930 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
bogdanm 82:6473597d706e 2931 struct { /* offset: 0x8 */
bogdanm 82:6473597d706e 2932 uint8_t RESERVED_0[3];
bogdanm 82:6473597d706e 2933 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
bogdanm 82:6473597d706e 2934 } CTRL_ACCESS8BIT;
bogdanm 82:6473597d706e 2935 };
bogdanm 82:6473597d706e 2936 } CRC_Type, *CRC_MemMapPtr;
bogdanm 82:6473597d706e 2937
bogdanm 82:6473597d706e 2938 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2939 -- CRC - Register accessor macros
bogdanm 82:6473597d706e 2940 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2941
bogdanm 82:6473597d706e 2942 /*!
bogdanm 82:6473597d706e 2943 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
bogdanm 82:6473597d706e 2944 * @{
bogdanm 82:6473597d706e 2945 */
bogdanm 82:6473597d706e 2946
bogdanm 82:6473597d706e 2947
bogdanm 82:6473597d706e 2948 /* CRC - Register accessors */
bogdanm 82:6473597d706e 2949 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
bogdanm 82:6473597d706e 2950 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
bogdanm 82:6473597d706e 2951 #define CRC_DATA_REG(base) ((base)->DATA)
bogdanm 82:6473597d706e 2952 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
bogdanm 82:6473597d706e 2953 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
bogdanm 82:6473597d706e 2954 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
bogdanm 82:6473597d706e 2955 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
bogdanm 82:6473597d706e 2956 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
bogdanm 82:6473597d706e 2957 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
bogdanm 82:6473597d706e 2958 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
bogdanm 82:6473597d706e 2959 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
bogdanm 82:6473597d706e 2960 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
bogdanm 82:6473597d706e 2961 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
bogdanm 82:6473597d706e 2962 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
bogdanm 82:6473597d706e 2963 #define CRC_CTRL_REG(base) ((base)->CTRL)
bogdanm 82:6473597d706e 2964 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
bogdanm 82:6473597d706e 2965
bogdanm 82:6473597d706e 2966 /*!
bogdanm 82:6473597d706e 2967 * @}
bogdanm 82:6473597d706e 2968 */ /* end of group CRC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 2969
bogdanm 82:6473597d706e 2970
bogdanm 82:6473597d706e 2971 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 2972 -- CRC Register Masks
bogdanm 82:6473597d706e 2973 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 2974
bogdanm 82:6473597d706e 2975 /*!
bogdanm 82:6473597d706e 2976 * @addtogroup CRC_Register_Masks CRC Register Masks
bogdanm 82:6473597d706e 2977 * @{
bogdanm 82:6473597d706e 2978 */
bogdanm 82:6473597d706e 2979
bogdanm 82:6473597d706e 2980 /* DATAL Bit Fields */
bogdanm 82:6473597d706e 2981 #define CRC_DATAL_DATAL_MASK 0xFFFFu
bogdanm 82:6473597d706e 2982 #define CRC_DATAL_DATAL_SHIFT 0
bogdanm 82:6473597d706e 2983 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
bogdanm 82:6473597d706e 2984 /* DATAH Bit Fields */
bogdanm 82:6473597d706e 2985 #define CRC_DATAH_DATAH_MASK 0xFFFFu
bogdanm 82:6473597d706e 2986 #define CRC_DATAH_DATAH_SHIFT 0
bogdanm 82:6473597d706e 2987 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
bogdanm 82:6473597d706e 2988 /* DATA Bit Fields */
bogdanm 82:6473597d706e 2989 #define CRC_DATA_LL_MASK 0xFFu
bogdanm 82:6473597d706e 2990 #define CRC_DATA_LL_SHIFT 0
bogdanm 82:6473597d706e 2991 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
bogdanm 82:6473597d706e 2992 #define CRC_DATA_LU_MASK 0xFF00u
bogdanm 82:6473597d706e 2993 #define CRC_DATA_LU_SHIFT 8
bogdanm 82:6473597d706e 2994 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
bogdanm 82:6473597d706e 2995 #define CRC_DATA_HL_MASK 0xFF0000u
bogdanm 82:6473597d706e 2996 #define CRC_DATA_HL_SHIFT 16
bogdanm 82:6473597d706e 2997 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
bogdanm 82:6473597d706e 2998 #define CRC_DATA_HU_MASK 0xFF000000u
bogdanm 82:6473597d706e 2999 #define CRC_DATA_HU_SHIFT 24
bogdanm 82:6473597d706e 3000 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
bogdanm 82:6473597d706e 3001 /* DATALL Bit Fields */
bogdanm 82:6473597d706e 3002 #define CRC_DATALL_DATALL_MASK 0xFFu
bogdanm 82:6473597d706e 3003 #define CRC_DATALL_DATALL_SHIFT 0
bogdanm 82:6473597d706e 3004 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
bogdanm 82:6473597d706e 3005 /* DATALU Bit Fields */
bogdanm 82:6473597d706e 3006 #define CRC_DATALU_DATALU_MASK 0xFFu
bogdanm 82:6473597d706e 3007 #define CRC_DATALU_DATALU_SHIFT 0
bogdanm 82:6473597d706e 3008 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
bogdanm 82:6473597d706e 3009 /* DATAHL Bit Fields */
bogdanm 82:6473597d706e 3010 #define CRC_DATAHL_DATAHL_MASK 0xFFu
bogdanm 82:6473597d706e 3011 #define CRC_DATAHL_DATAHL_SHIFT 0
bogdanm 82:6473597d706e 3012 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
bogdanm 82:6473597d706e 3013 /* DATAHU Bit Fields */
bogdanm 82:6473597d706e 3014 #define CRC_DATAHU_DATAHU_MASK 0xFFu
bogdanm 82:6473597d706e 3015 #define CRC_DATAHU_DATAHU_SHIFT 0
bogdanm 82:6473597d706e 3016 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
bogdanm 82:6473597d706e 3017 /* GPOLYL Bit Fields */
bogdanm 82:6473597d706e 3018 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
bogdanm 82:6473597d706e 3019 #define CRC_GPOLYL_GPOLYL_SHIFT 0
bogdanm 82:6473597d706e 3020 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
bogdanm 82:6473597d706e 3021 /* GPOLYH Bit Fields */
bogdanm 82:6473597d706e 3022 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
bogdanm 82:6473597d706e 3023 #define CRC_GPOLYH_GPOLYH_SHIFT 0
bogdanm 82:6473597d706e 3024 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
bogdanm 82:6473597d706e 3025 /* GPOLY Bit Fields */
bogdanm 82:6473597d706e 3026 #define CRC_GPOLY_LOW_MASK 0xFFFFu
bogdanm 82:6473597d706e 3027 #define CRC_GPOLY_LOW_SHIFT 0
bogdanm 82:6473597d706e 3028 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
bogdanm 82:6473597d706e 3029 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 3030 #define CRC_GPOLY_HIGH_SHIFT 16
bogdanm 82:6473597d706e 3031 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
bogdanm 82:6473597d706e 3032 /* GPOLYLL Bit Fields */
bogdanm 82:6473597d706e 3033 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
bogdanm 82:6473597d706e 3034 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
bogdanm 82:6473597d706e 3035 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
bogdanm 82:6473597d706e 3036 /* GPOLYLU Bit Fields */
bogdanm 82:6473597d706e 3037 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
bogdanm 82:6473597d706e 3038 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
bogdanm 82:6473597d706e 3039 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
bogdanm 82:6473597d706e 3040 /* GPOLYHL Bit Fields */
bogdanm 82:6473597d706e 3041 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
bogdanm 82:6473597d706e 3042 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
bogdanm 82:6473597d706e 3043 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
bogdanm 82:6473597d706e 3044 /* GPOLYHU Bit Fields */
bogdanm 82:6473597d706e 3045 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
bogdanm 82:6473597d706e 3046 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
bogdanm 82:6473597d706e 3047 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
bogdanm 82:6473597d706e 3048 /* CTRL Bit Fields */
bogdanm 82:6473597d706e 3049 #define CRC_CTRL_TCRC_MASK 0x1000000u
bogdanm 82:6473597d706e 3050 #define CRC_CTRL_TCRC_SHIFT 24
bogdanm 82:6473597d706e 3051 #define CRC_CTRL_WAS_MASK 0x2000000u
bogdanm 82:6473597d706e 3052 #define CRC_CTRL_WAS_SHIFT 25
bogdanm 82:6473597d706e 3053 #define CRC_CTRL_FXOR_MASK 0x4000000u
bogdanm 82:6473597d706e 3054 #define CRC_CTRL_FXOR_SHIFT 26
bogdanm 82:6473597d706e 3055 #define CRC_CTRL_TOTR_MASK 0x30000000u
bogdanm 82:6473597d706e 3056 #define CRC_CTRL_TOTR_SHIFT 28
bogdanm 82:6473597d706e 3057 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
bogdanm 82:6473597d706e 3058 #define CRC_CTRL_TOT_MASK 0xC0000000u
bogdanm 82:6473597d706e 3059 #define CRC_CTRL_TOT_SHIFT 30
bogdanm 82:6473597d706e 3060 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
bogdanm 82:6473597d706e 3061 /* CTRLHU Bit Fields */
bogdanm 82:6473597d706e 3062 #define CRC_CTRLHU_TCRC_MASK 0x1u
bogdanm 82:6473597d706e 3063 #define CRC_CTRLHU_TCRC_SHIFT 0
bogdanm 82:6473597d706e 3064 #define CRC_CTRLHU_WAS_MASK 0x2u
bogdanm 82:6473597d706e 3065 #define CRC_CTRLHU_WAS_SHIFT 1
bogdanm 82:6473597d706e 3066 #define CRC_CTRLHU_FXOR_MASK 0x4u
bogdanm 82:6473597d706e 3067 #define CRC_CTRLHU_FXOR_SHIFT 2
bogdanm 82:6473597d706e 3068 #define CRC_CTRLHU_TOTR_MASK 0x30u
bogdanm 82:6473597d706e 3069 #define CRC_CTRLHU_TOTR_SHIFT 4
bogdanm 82:6473597d706e 3070 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
bogdanm 82:6473597d706e 3071 #define CRC_CTRLHU_TOT_MASK 0xC0u
bogdanm 82:6473597d706e 3072 #define CRC_CTRLHU_TOT_SHIFT 6
bogdanm 82:6473597d706e 3073 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
bogdanm 82:6473597d706e 3074
bogdanm 82:6473597d706e 3075 /*!
bogdanm 82:6473597d706e 3076 * @}
bogdanm 82:6473597d706e 3077 */ /* end of group CRC_Register_Masks */
bogdanm 82:6473597d706e 3078
bogdanm 82:6473597d706e 3079
bogdanm 82:6473597d706e 3080 /* CRC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 3081 /** Peripheral CRC base address */
bogdanm 82:6473597d706e 3082 #define CRC_BASE (0x40032000u)
bogdanm 82:6473597d706e 3083 /** Peripheral CRC base pointer */
bogdanm 82:6473597d706e 3084 #define CRC0 ((CRC_Type *)CRC_BASE)
bogdanm 82:6473597d706e 3085 #define CRC_BASE_PTR (CRC0)
bogdanm 82:6473597d706e 3086 /** Array initializer of CRC peripheral base pointers */
bogdanm 82:6473597d706e 3087 #define CRC_BASES { CRC0 }
bogdanm 82:6473597d706e 3088
bogdanm 82:6473597d706e 3089 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 3090 -- CRC - Register accessor macros
bogdanm 82:6473597d706e 3091 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 3092
bogdanm 82:6473597d706e 3093 /*!
bogdanm 82:6473597d706e 3094 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
bogdanm 82:6473597d706e 3095 * @{
bogdanm 82:6473597d706e 3096 */
bogdanm 82:6473597d706e 3097
bogdanm 82:6473597d706e 3098
bogdanm 82:6473597d706e 3099 /* CRC - Register instance definitions */
bogdanm 82:6473597d706e 3100 /* CRC */
bogdanm 82:6473597d706e 3101 #define CRC_DATA CRC_DATA_REG(CRC0)
bogdanm 82:6473597d706e 3102 #define CRC_DATAL CRC_DATAL_REG(CRC0)
bogdanm 82:6473597d706e 3103 #define CRC_DATALL CRC_DATALL_REG(CRC0)
bogdanm 82:6473597d706e 3104 #define CRC_DATALU CRC_DATALU_REG(CRC0)
bogdanm 82:6473597d706e 3105 #define CRC_DATAH CRC_DATAH_REG(CRC0)
bogdanm 82:6473597d706e 3106 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
bogdanm 82:6473597d706e 3107 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
bogdanm 82:6473597d706e 3108 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
bogdanm 82:6473597d706e 3109 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
bogdanm 82:6473597d706e 3110 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
bogdanm 82:6473597d706e 3111 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
bogdanm 82:6473597d706e 3112 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
bogdanm 82:6473597d706e 3113 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
bogdanm 82:6473597d706e 3114 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
bogdanm 82:6473597d706e 3115 #define CRC_CTRL CRC_CTRL_REG(CRC0)
bogdanm 82:6473597d706e 3116 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
bogdanm 82:6473597d706e 3117
bogdanm 82:6473597d706e 3118 /*!
bogdanm 82:6473597d706e 3119 * @}
bogdanm 82:6473597d706e 3120 */ /* end of group CRC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 3121
bogdanm 82:6473597d706e 3122
bogdanm 82:6473597d706e 3123 /*!
bogdanm 82:6473597d706e 3124 * @}
bogdanm 82:6473597d706e 3125 */ /* end of group CRC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 3126
bogdanm 82:6473597d706e 3127
bogdanm 82:6473597d706e 3128 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 3129 -- DAC Peripheral Access Layer
bogdanm 82:6473597d706e 3130 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 3131
bogdanm 82:6473597d706e 3132 /*!
bogdanm 82:6473597d706e 3133 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
bogdanm 82:6473597d706e 3134 * @{
bogdanm 82:6473597d706e 3135 */
bogdanm 82:6473597d706e 3136
bogdanm 82:6473597d706e 3137 /** DAC - Register Layout Typedef */
bogdanm 82:6473597d706e 3138 typedef struct {
bogdanm 82:6473597d706e 3139 struct { /* offset: 0x0, array step: 0x2 */
bogdanm 82:6473597d706e 3140 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
bogdanm 82:6473597d706e 3141 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
bogdanm 82:6473597d706e 3142 } DAT[16];
bogdanm 82:6473597d706e 3143 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
bogdanm 82:6473597d706e 3144 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
bogdanm 82:6473597d706e 3145 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
bogdanm 82:6473597d706e 3146 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
bogdanm 82:6473597d706e 3147 } DAC_Type, *DAC_MemMapPtr;
bogdanm 82:6473597d706e 3148
bogdanm 82:6473597d706e 3149 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 3150 -- DAC - Register accessor macros
bogdanm 82:6473597d706e 3151 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 3152
bogdanm 82:6473597d706e 3153 /*!
bogdanm 82:6473597d706e 3154 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
bogdanm 82:6473597d706e 3155 * @{
bogdanm 82:6473597d706e 3156 */
bogdanm 82:6473597d706e 3157
bogdanm 82:6473597d706e 3158
bogdanm 82:6473597d706e 3159 /* DAC - Register accessors */
bogdanm 82:6473597d706e 3160 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
bogdanm 82:6473597d706e 3161 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
bogdanm 82:6473597d706e 3162 #define DAC_SR_REG(base) ((base)->SR)
bogdanm 82:6473597d706e 3163 #define DAC_C0_REG(base) ((base)->C0)
bogdanm 82:6473597d706e 3164 #define DAC_C1_REG(base) ((base)->C1)
bogdanm 82:6473597d706e 3165 #define DAC_C2_REG(base) ((base)->C2)
bogdanm 82:6473597d706e 3166
bogdanm 82:6473597d706e 3167 /*!
bogdanm 82:6473597d706e 3168 * @}
bogdanm 82:6473597d706e 3169 */ /* end of group DAC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 3170
bogdanm 82:6473597d706e 3171
bogdanm 82:6473597d706e 3172 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 3173 -- DAC Register Masks
bogdanm 82:6473597d706e 3174 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 3175
bogdanm 82:6473597d706e 3176 /*!
bogdanm 82:6473597d706e 3177 * @addtogroup DAC_Register_Masks DAC Register Masks
bogdanm 82:6473597d706e 3178 * @{
bogdanm 82:6473597d706e 3179 */
bogdanm 82:6473597d706e 3180
bogdanm 82:6473597d706e 3181 /* DATL Bit Fields */
bogdanm 82:6473597d706e 3182 #define DAC_DATL_DATA0_MASK 0xFFu
bogdanm 82:6473597d706e 3183 #define DAC_DATL_DATA0_SHIFT 0
bogdanm 82:6473597d706e 3184 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
bogdanm 82:6473597d706e 3185 /* DATH Bit Fields */
bogdanm 82:6473597d706e 3186 #define DAC_DATH_DATA1_MASK 0xFu
bogdanm 82:6473597d706e 3187 #define DAC_DATH_DATA1_SHIFT 0
bogdanm 82:6473597d706e 3188 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
bogdanm 82:6473597d706e 3189 /* SR Bit Fields */
bogdanm 82:6473597d706e 3190 #define DAC_SR_DACBFRPBF_MASK 0x1u
bogdanm 82:6473597d706e 3191 #define DAC_SR_DACBFRPBF_SHIFT 0
bogdanm 82:6473597d706e 3192 #define DAC_SR_DACBFRPTF_MASK 0x2u
bogdanm 82:6473597d706e 3193 #define DAC_SR_DACBFRPTF_SHIFT 1
bogdanm 82:6473597d706e 3194 #define DAC_SR_DACBFWMF_MASK 0x4u
bogdanm 82:6473597d706e 3195 #define DAC_SR_DACBFWMF_SHIFT 2
bogdanm 82:6473597d706e 3196 /* C0 Bit Fields */
bogdanm 82:6473597d706e 3197 #define DAC_C0_DACBBIEN_MASK 0x1u
bogdanm 82:6473597d706e 3198 #define DAC_C0_DACBBIEN_SHIFT 0
bogdanm 82:6473597d706e 3199 #define DAC_C0_DACBTIEN_MASK 0x2u
bogdanm 82:6473597d706e 3200 #define DAC_C0_DACBTIEN_SHIFT 1
bogdanm 82:6473597d706e 3201 #define DAC_C0_DACBWIEN_MASK 0x4u
bogdanm 82:6473597d706e 3202 #define DAC_C0_DACBWIEN_SHIFT 2
bogdanm 82:6473597d706e 3203 #define DAC_C0_LPEN_MASK 0x8u
bogdanm 82:6473597d706e 3204 #define DAC_C0_LPEN_SHIFT 3
bogdanm 82:6473597d706e 3205 #define DAC_C0_DACSWTRG_MASK 0x10u
bogdanm 82:6473597d706e 3206 #define DAC_C0_DACSWTRG_SHIFT 4
bogdanm 82:6473597d706e 3207 #define DAC_C0_DACTRGSEL_MASK 0x20u
bogdanm 82:6473597d706e 3208 #define DAC_C0_DACTRGSEL_SHIFT 5
bogdanm 82:6473597d706e 3209 #define DAC_C0_DACRFS_MASK 0x40u
bogdanm 82:6473597d706e 3210 #define DAC_C0_DACRFS_SHIFT 6
bogdanm 82:6473597d706e 3211 #define DAC_C0_DACEN_MASK 0x80u
bogdanm 82:6473597d706e 3212 #define DAC_C0_DACEN_SHIFT 7
bogdanm 82:6473597d706e 3213 /* C1 Bit Fields */
bogdanm 82:6473597d706e 3214 #define DAC_C1_DACBFEN_MASK 0x1u
bogdanm 82:6473597d706e 3215 #define DAC_C1_DACBFEN_SHIFT 0
bogdanm 82:6473597d706e 3216 #define DAC_C1_DACBFMD_MASK 0x6u
bogdanm 82:6473597d706e 3217 #define DAC_C1_DACBFMD_SHIFT 1
bogdanm 82:6473597d706e 3218 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
bogdanm 82:6473597d706e 3219 #define DAC_C1_DACBFWM_MASK 0x18u
bogdanm 82:6473597d706e 3220 #define DAC_C1_DACBFWM_SHIFT 3
bogdanm 82:6473597d706e 3221 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
bogdanm 82:6473597d706e 3222 #define DAC_C1_DMAEN_MASK 0x80u
bogdanm 82:6473597d706e 3223 #define DAC_C1_DMAEN_SHIFT 7
bogdanm 82:6473597d706e 3224 /* C2 Bit Fields */
bogdanm 82:6473597d706e 3225 #define DAC_C2_DACBFUP_MASK 0xFu
bogdanm 82:6473597d706e 3226 #define DAC_C2_DACBFUP_SHIFT 0
bogdanm 82:6473597d706e 3227 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
bogdanm 82:6473597d706e 3228 #define DAC_C2_DACBFRP_MASK 0xF0u
bogdanm 82:6473597d706e 3229 #define DAC_C2_DACBFRP_SHIFT 4
bogdanm 82:6473597d706e 3230 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
bogdanm 82:6473597d706e 3231
bogdanm 82:6473597d706e 3232 /*!
bogdanm 82:6473597d706e 3233 * @}
bogdanm 82:6473597d706e 3234 */ /* end of group DAC_Register_Masks */
bogdanm 82:6473597d706e 3235
bogdanm 82:6473597d706e 3236
bogdanm 82:6473597d706e 3237 /* DAC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 3238 /** Peripheral DAC0 base address */
bogdanm 82:6473597d706e 3239 #define DAC0_BASE (0x400CC000u)
bogdanm 82:6473597d706e 3240 /** Peripheral DAC0 base pointer */
bogdanm 82:6473597d706e 3241 #define DAC0 ((DAC_Type *)DAC0_BASE)
bogdanm 82:6473597d706e 3242 #define DAC0_BASE_PTR (DAC0)
bogdanm 82:6473597d706e 3243 /** Peripheral DAC1 base address */
bogdanm 82:6473597d706e 3244 #define DAC1_BASE (0x400CD000u)
bogdanm 82:6473597d706e 3245 /** Peripheral DAC1 base pointer */
bogdanm 82:6473597d706e 3246 #define DAC1 ((DAC_Type *)DAC1_BASE)
bogdanm 82:6473597d706e 3247 #define DAC1_BASE_PTR (DAC1)
bogdanm 82:6473597d706e 3248 /** Array initializer of DAC peripheral base pointers */
bogdanm 82:6473597d706e 3249 #define DAC_BASES { DAC0, DAC1 }
bogdanm 82:6473597d706e 3250
bogdanm 82:6473597d706e 3251 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 3252 -- DAC - Register accessor macros
bogdanm 82:6473597d706e 3253 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 3254
bogdanm 82:6473597d706e 3255 /*!
bogdanm 82:6473597d706e 3256 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
bogdanm 82:6473597d706e 3257 * @{
bogdanm 82:6473597d706e 3258 */
bogdanm 82:6473597d706e 3259
bogdanm 82:6473597d706e 3260
bogdanm 82:6473597d706e 3261 /* DAC - Register instance definitions */
bogdanm 82:6473597d706e 3262 /* DAC0 */
bogdanm 82:6473597d706e 3263 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
bogdanm 82:6473597d706e 3264 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
bogdanm 82:6473597d706e 3265 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
bogdanm 82:6473597d706e 3266 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
bogdanm 82:6473597d706e 3267 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
bogdanm 82:6473597d706e 3268 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
bogdanm 82:6473597d706e 3269 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
bogdanm 82:6473597d706e 3270 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
bogdanm 82:6473597d706e 3271 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
bogdanm 82:6473597d706e 3272 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
bogdanm 82:6473597d706e 3273 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
bogdanm 82:6473597d706e 3274 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
bogdanm 82:6473597d706e 3275 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
bogdanm 82:6473597d706e 3276 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
bogdanm 82:6473597d706e 3277 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
bogdanm 82:6473597d706e 3278 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
bogdanm 82:6473597d706e 3279 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
bogdanm 82:6473597d706e 3280 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
bogdanm 82:6473597d706e 3281 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
bogdanm 82:6473597d706e 3282 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
bogdanm 82:6473597d706e 3283 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
bogdanm 82:6473597d706e 3284 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
bogdanm 82:6473597d706e 3285 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
bogdanm 82:6473597d706e 3286 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
bogdanm 82:6473597d706e 3287 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
bogdanm 82:6473597d706e 3288 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
bogdanm 82:6473597d706e 3289 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
bogdanm 82:6473597d706e 3290 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
bogdanm 82:6473597d706e 3291 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
bogdanm 82:6473597d706e 3292 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
bogdanm 82:6473597d706e 3293 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
bogdanm 82:6473597d706e 3294 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
bogdanm 82:6473597d706e 3295 #define DAC0_SR DAC_SR_REG(DAC0)
bogdanm 82:6473597d706e 3296 #define DAC0_C0 DAC_C0_REG(DAC0)
bogdanm 82:6473597d706e 3297 #define DAC0_C1 DAC_C1_REG(DAC0)
bogdanm 82:6473597d706e 3298 #define DAC0_C2 DAC_C2_REG(DAC0)
bogdanm 82:6473597d706e 3299 /* DAC1 */
bogdanm 82:6473597d706e 3300 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
bogdanm 82:6473597d706e 3301 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
bogdanm 82:6473597d706e 3302 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
bogdanm 82:6473597d706e 3303 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
bogdanm 82:6473597d706e 3304 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
bogdanm 82:6473597d706e 3305 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
bogdanm 82:6473597d706e 3306 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
bogdanm 82:6473597d706e 3307 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
bogdanm 82:6473597d706e 3308 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
bogdanm 82:6473597d706e 3309 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
bogdanm 82:6473597d706e 3310 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
bogdanm 82:6473597d706e 3311 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
bogdanm 82:6473597d706e 3312 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
bogdanm 82:6473597d706e 3313 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
bogdanm 82:6473597d706e 3314 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
bogdanm 82:6473597d706e 3315 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
bogdanm 82:6473597d706e 3316 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
bogdanm 82:6473597d706e 3317 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
bogdanm 82:6473597d706e 3318 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
bogdanm 82:6473597d706e 3319 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
bogdanm 82:6473597d706e 3320 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
bogdanm 82:6473597d706e 3321 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
bogdanm 82:6473597d706e 3322 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
bogdanm 82:6473597d706e 3323 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
bogdanm 82:6473597d706e 3324 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
bogdanm 82:6473597d706e 3325 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
bogdanm 82:6473597d706e 3326 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
bogdanm 82:6473597d706e 3327 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
bogdanm 82:6473597d706e 3328 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
bogdanm 82:6473597d706e 3329 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
bogdanm 82:6473597d706e 3330 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
bogdanm 82:6473597d706e 3331 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
bogdanm 82:6473597d706e 3332 #define DAC1_SR DAC_SR_REG(DAC1)
bogdanm 82:6473597d706e 3333 #define DAC1_C0 DAC_C0_REG(DAC1)
bogdanm 82:6473597d706e 3334 #define DAC1_C1 DAC_C1_REG(DAC1)
bogdanm 82:6473597d706e 3335 #define DAC1_C2 DAC_C2_REG(DAC1)
bogdanm 82:6473597d706e 3336
bogdanm 82:6473597d706e 3337 /* DAC - Register array accessors */
bogdanm 82:6473597d706e 3338 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
bogdanm 82:6473597d706e 3339 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
bogdanm 82:6473597d706e 3340 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
bogdanm 82:6473597d706e 3341 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
bogdanm 82:6473597d706e 3342
bogdanm 82:6473597d706e 3343 /*!
bogdanm 82:6473597d706e 3344 * @}
bogdanm 82:6473597d706e 3345 */ /* end of group DAC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 3346
bogdanm 82:6473597d706e 3347
bogdanm 82:6473597d706e 3348 /*!
bogdanm 82:6473597d706e 3349 * @}
bogdanm 82:6473597d706e 3350 */ /* end of group DAC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 3351
bogdanm 82:6473597d706e 3352
bogdanm 82:6473597d706e 3353 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 3354 -- DMA Peripheral Access Layer
bogdanm 82:6473597d706e 3355 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 3356
bogdanm 82:6473597d706e 3357 /*!
bogdanm 82:6473597d706e 3358 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
bogdanm 82:6473597d706e 3359 * @{
bogdanm 82:6473597d706e 3360 */
bogdanm 82:6473597d706e 3361
bogdanm 82:6473597d706e 3362 /** DMA - Register Layout Typedef */
bogdanm 82:6473597d706e 3363 typedef struct {
bogdanm 82:6473597d706e 3364 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
bogdanm 82:6473597d706e 3365 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
bogdanm 82:6473597d706e 3366 uint8_t RESERVED_0[4];
bogdanm 82:6473597d706e 3367 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
bogdanm 82:6473597d706e 3368 uint8_t RESERVED_1[4];
bogdanm 82:6473597d706e 3369 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
bogdanm 82:6473597d706e 3370 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
bogdanm 82:6473597d706e 3371 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
bogdanm 82:6473597d706e 3372 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
bogdanm 82:6473597d706e 3373 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
bogdanm 82:6473597d706e 3374 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
bogdanm 82:6473597d706e 3375 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
bogdanm 82:6473597d706e 3376 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
bogdanm 82:6473597d706e 3377 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
bogdanm 82:6473597d706e 3378 uint8_t RESERVED_2[4];
bogdanm 82:6473597d706e 3379 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
bogdanm 82:6473597d706e 3380 uint8_t RESERVED_3[4];
bogdanm 82:6473597d706e 3381 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
bogdanm 82:6473597d706e 3382 uint8_t RESERVED_4[4];
bogdanm 82:6473597d706e 3383 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
bogdanm 82:6473597d706e 3384 uint8_t RESERVED_5[12];
bogdanm 82:6473597d706e 3385 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
bogdanm 82:6473597d706e 3386 uint8_t RESERVED_6[184];
bogdanm 82:6473597d706e 3387 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
bogdanm 82:6473597d706e 3388 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
bogdanm 82:6473597d706e 3389 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
bogdanm 82:6473597d706e 3390 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
bogdanm 82:6473597d706e 3391 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
bogdanm 82:6473597d706e 3392 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
bogdanm 82:6473597d706e 3393 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
bogdanm 82:6473597d706e 3394 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
bogdanm 82:6473597d706e 3395 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
bogdanm 82:6473597d706e 3396 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
bogdanm 82:6473597d706e 3397 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
bogdanm 82:6473597d706e 3398 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
bogdanm 82:6473597d706e 3399 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
bogdanm 82:6473597d706e 3400 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
bogdanm 82:6473597d706e 3401 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
bogdanm 82:6473597d706e 3402 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
bogdanm 82:6473597d706e 3403 uint8_t RESERVED_7[3824];
bogdanm 82:6473597d706e 3404 struct { /* offset: 0x1000, array step: 0x20 */
bogdanm 82:6473597d706e 3405 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
bogdanm 82:6473597d706e 3406 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
bogdanm 82:6473597d706e 3407 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
bogdanm 82:6473597d706e 3408 union { /* offset: 0x1008, array step: 0x20 */
bogdanm 82:6473597d706e 3409 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
bogdanm 82:6473597d706e 3410 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
bogdanm 82:6473597d706e 3411 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
bogdanm 82:6473597d706e 3412 };
bogdanm 82:6473597d706e 3413 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
bogdanm 82:6473597d706e 3414 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
bogdanm 82:6473597d706e 3415 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
bogdanm 82:6473597d706e 3416 union { /* offset: 0x1016, array step: 0x20 */
bogdanm 82:6473597d706e 3417 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
bogdanm 82:6473597d706e 3418 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
bogdanm 82:6473597d706e 3419 };
bogdanm 82:6473597d706e 3420 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
bogdanm 82:6473597d706e 3421 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
bogdanm 82:6473597d706e 3422 union { /* offset: 0x101E, array step: 0x20 */
bogdanm 82:6473597d706e 3423 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
bogdanm 82:6473597d706e 3424 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
bogdanm 82:6473597d706e 3425 };
bogdanm 82:6473597d706e 3426 } TCD[16];
bogdanm 82:6473597d706e 3427 } DMA_Type, *DMA_MemMapPtr;
bogdanm 82:6473597d706e 3428
bogdanm 82:6473597d706e 3429 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 3430 -- DMA - Register accessor macros
bogdanm 82:6473597d706e 3431 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 3432
bogdanm 82:6473597d706e 3433 /*!
bogdanm 82:6473597d706e 3434 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
bogdanm 82:6473597d706e 3435 * @{
bogdanm 82:6473597d706e 3436 */
bogdanm 82:6473597d706e 3437
bogdanm 82:6473597d706e 3438
bogdanm 82:6473597d706e 3439 /* DMA - Register accessors */
bogdanm 82:6473597d706e 3440 #define DMA_CR_REG(base) ((base)->CR)
bogdanm 82:6473597d706e 3441 #define DMA_ES_REG(base) ((base)->ES)
bogdanm 82:6473597d706e 3442 #define DMA_ERQ_REG(base) ((base)->ERQ)
bogdanm 82:6473597d706e 3443 #define DMA_EEI_REG(base) ((base)->EEI)
bogdanm 82:6473597d706e 3444 #define DMA_CEEI_REG(base) ((base)->CEEI)
bogdanm 82:6473597d706e 3445 #define DMA_SEEI_REG(base) ((base)->SEEI)
bogdanm 82:6473597d706e 3446 #define DMA_CERQ_REG(base) ((base)->CERQ)
bogdanm 82:6473597d706e 3447 #define DMA_SERQ_REG(base) ((base)->SERQ)
bogdanm 82:6473597d706e 3448 #define DMA_CDNE_REG(base) ((base)->CDNE)
bogdanm 82:6473597d706e 3449 #define DMA_SSRT_REG(base) ((base)->SSRT)
bogdanm 82:6473597d706e 3450 #define DMA_CERR_REG(base) ((base)->CERR)
bogdanm 82:6473597d706e 3451 #define DMA_CINT_REG(base) ((base)->CINT)
bogdanm 82:6473597d706e 3452 #define DMA_INT_REG(base) ((base)->INT)
bogdanm 82:6473597d706e 3453 #define DMA_ERR_REG(base) ((base)->ERR)
bogdanm 82:6473597d706e 3454 #define DMA_HRS_REG(base) ((base)->HRS)
bogdanm 82:6473597d706e 3455 #define DMA_EARS_REG(base) ((base)->EARS)
bogdanm 82:6473597d706e 3456 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
bogdanm 82:6473597d706e 3457 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
bogdanm 82:6473597d706e 3458 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
bogdanm 82:6473597d706e 3459 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
bogdanm 82:6473597d706e 3460 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
bogdanm 82:6473597d706e 3461 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
bogdanm 82:6473597d706e 3462 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
bogdanm 82:6473597d706e 3463 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
bogdanm 82:6473597d706e 3464 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
bogdanm 82:6473597d706e 3465 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
bogdanm 82:6473597d706e 3466 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
bogdanm 82:6473597d706e 3467 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
bogdanm 82:6473597d706e 3468 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
bogdanm 82:6473597d706e 3469 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
bogdanm 82:6473597d706e 3470 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
bogdanm 82:6473597d706e 3471 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
bogdanm 82:6473597d706e 3472 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
bogdanm 82:6473597d706e 3473 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
bogdanm 82:6473597d706e 3474 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
bogdanm 82:6473597d706e 3475 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
bogdanm 82:6473597d706e 3476 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
bogdanm 82:6473597d706e 3477 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
bogdanm 82:6473597d706e 3478 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
bogdanm 82:6473597d706e 3479 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
bogdanm 82:6473597d706e 3480 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
bogdanm 82:6473597d706e 3481 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
bogdanm 82:6473597d706e 3482 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
bogdanm 82:6473597d706e 3483 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
bogdanm 82:6473597d706e 3484 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
bogdanm 82:6473597d706e 3485 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
bogdanm 82:6473597d706e 3486 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
bogdanm 82:6473597d706e 3487
bogdanm 82:6473597d706e 3488 /*!
bogdanm 82:6473597d706e 3489 * @}
bogdanm 82:6473597d706e 3490 */ /* end of group DMA_Register_Accessor_Macros */
bogdanm 82:6473597d706e 3491
bogdanm 82:6473597d706e 3492
bogdanm 82:6473597d706e 3493 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 3494 -- DMA Register Masks
bogdanm 82:6473597d706e 3495 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 3496
bogdanm 82:6473597d706e 3497 /*!
bogdanm 82:6473597d706e 3498 * @addtogroup DMA_Register_Masks DMA Register Masks
bogdanm 82:6473597d706e 3499 * @{
bogdanm 82:6473597d706e 3500 */
bogdanm 82:6473597d706e 3501
bogdanm 82:6473597d706e 3502 /* CR Bit Fields */
bogdanm 82:6473597d706e 3503 #define DMA_CR_EDBG_MASK 0x2u
bogdanm 82:6473597d706e 3504 #define DMA_CR_EDBG_SHIFT 1
bogdanm 82:6473597d706e 3505 #define DMA_CR_ERCA_MASK 0x4u
bogdanm 82:6473597d706e 3506 #define DMA_CR_ERCA_SHIFT 2
bogdanm 82:6473597d706e 3507 #define DMA_CR_HOE_MASK 0x10u
bogdanm 82:6473597d706e 3508 #define DMA_CR_HOE_SHIFT 4
bogdanm 82:6473597d706e 3509 #define DMA_CR_HALT_MASK 0x20u
bogdanm 82:6473597d706e 3510 #define DMA_CR_HALT_SHIFT 5
bogdanm 82:6473597d706e 3511 #define DMA_CR_CLM_MASK 0x40u
bogdanm 82:6473597d706e 3512 #define DMA_CR_CLM_SHIFT 6
bogdanm 82:6473597d706e 3513 #define DMA_CR_EMLM_MASK 0x80u
bogdanm 82:6473597d706e 3514 #define DMA_CR_EMLM_SHIFT 7
bogdanm 82:6473597d706e 3515 #define DMA_CR_ECX_MASK 0x10000u
bogdanm 82:6473597d706e 3516 #define DMA_CR_ECX_SHIFT 16
bogdanm 82:6473597d706e 3517 #define DMA_CR_CX_MASK 0x20000u
bogdanm 82:6473597d706e 3518 #define DMA_CR_CX_SHIFT 17
bogdanm 82:6473597d706e 3519 /* ES Bit Fields */
bogdanm 82:6473597d706e 3520 #define DMA_ES_DBE_MASK 0x1u
bogdanm 82:6473597d706e 3521 #define DMA_ES_DBE_SHIFT 0
bogdanm 82:6473597d706e 3522 #define DMA_ES_SBE_MASK 0x2u
bogdanm 82:6473597d706e 3523 #define DMA_ES_SBE_SHIFT 1
bogdanm 82:6473597d706e 3524 #define DMA_ES_SGE_MASK 0x4u
bogdanm 82:6473597d706e 3525 #define DMA_ES_SGE_SHIFT 2
bogdanm 82:6473597d706e 3526 #define DMA_ES_NCE_MASK 0x8u
bogdanm 82:6473597d706e 3527 #define DMA_ES_NCE_SHIFT 3
bogdanm 82:6473597d706e 3528 #define DMA_ES_DOE_MASK 0x10u
bogdanm 82:6473597d706e 3529 #define DMA_ES_DOE_SHIFT 4
bogdanm 82:6473597d706e 3530 #define DMA_ES_DAE_MASK 0x20u
bogdanm 82:6473597d706e 3531 #define DMA_ES_DAE_SHIFT 5
bogdanm 82:6473597d706e 3532 #define DMA_ES_SOE_MASK 0x40u
bogdanm 82:6473597d706e 3533 #define DMA_ES_SOE_SHIFT 6
bogdanm 82:6473597d706e 3534 #define DMA_ES_SAE_MASK 0x80u
bogdanm 82:6473597d706e 3535 #define DMA_ES_SAE_SHIFT 7
bogdanm 82:6473597d706e 3536 #define DMA_ES_ERRCHN_MASK 0xF00u
bogdanm 82:6473597d706e 3537 #define DMA_ES_ERRCHN_SHIFT 8
bogdanm 82:6473597d706e 3538 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
bogdanm 82:6473597d706e 3539 #define DMA_ES_CPE_MASK 0x4000u
bogdanm 82:6473597d706e 3540 #define DMA_ES_CPE_SHIFT 14
bogdanm 82:6473597d706e 3541 #define DMA_ES_ECX_MASK 0x10000u
bogdanm 82:6473597d706e 3542 #define DMA_ES_ECX_SHIFT 16
bogdanm 82:6473597d706e 3543 #define DMA_ES_VLD_MASK 0x80000000u
bogdanm 82:6473597d706e 3544 #define DMA_ES_VLD_SHIFT 31
bogdanm 82:6473597d706e 3545 /* ERQ Bit Fields */
bogdanm 82:6473597d706e 3546 #define DMA_ERQ_ERQ0_MASK 0x1u
bogdanm 82:6473597d706e 3547 #define DMA_ERQ_ERQ0_SHIFT 0
bogdanm 82:6473597d706e 3548 #define DMA_ERQ_ERQ1_MASK 0x2u
bogdanm 82:6473597d706e 3549 #define DMA_ERQ_ERQ1_SHIFT 1
bogdanm 82:6473597d706e 3550 #define DMA_ERQ_ERQ2_MASK 0x4u
bogdanm 82:6473597d706e 3551 #define DMA_ERQ_ERQ2_SHIFT 2
bogdanm 82:6473597d706e 3552 #define DMA_ERQ_ERQ3_MASK 0x8u
bogdanm 82:6473597d706e 3553 #define DMA_ERQ_ERQ3_SHIFT 3
bogdanm 82:6473597d706e 3554 #define DMA_ERQ_ERQ4_MASK 0x10u
bogdanm 82:6473597d706e 3555 #define DMA_ERQ_ERQ4_SHIFT 4
bogdanm 82:6473597d706e 3556 #define DMA_ERQ_ERQ5_MASK 0x20u
bogdanm 82:6473597d706e 3557 #define DMA_ERQ_ERQ5_SHIFT 5
bogdanm 82:6473597d706e 3558 #define DMA_ERQ_ERQ6_MASK 0x40u
bogdanm 82:6473597d706e 3559 #define DMA_ERQ_ERQ6_SHIFT 6
bogdanm 82:6473597d706e 3560 #define DMA_ERQ_ERQ7_MASK 0x80u
bogdanm 82:6473597d706e 3561 #define DMA_ERQ_ERQ7_SHIFT 7
bogdanm 82:6473597d706e 3562 #define DMA_ERQ_ERQ8_MASK 0x100u
bogdanm 82:6473597d706e 3563 #define DMA_ERQ_ERQ8_SHIFT 8
bogdanm 82:6473597d706e 3564 #define DMA_ERQ_ERQ9_MASK 0x200u
bogdanm 82:6473597d706e 3565 #define DMA_ERQ_ERQ9_SHIFT 9
bogdanm 82:6473597d706e 3566 #define DMA_ERQ_ERQ10_MASK 0x400u
bogdanm 82:6473597d706e 3567 #define DMA_ERQ_ERQ10_SHIFT 10
bogdanm 82:6473597d706e 3568 #define DMA_ERQ_ERQ11_MASK 0x800u
bogdanm 82:6473597d706e 3569 #define DMA_ERQ_ERQ11_SHIFT 11
bogdanm 82:6473597d706e 3570 #define DMA_ERQ_ERQ12_MASK 0x1000u
bogdanm 82:6473597d706e 3571 #define DMA_ERQ_ERQ12_SHIFT 12
bogdanm 82:6473597d706e 3572 #define DMA_ERQ_ERQ13_MASK 0x2000u
bogdanm 82:6473597d706e 3573 #define DMA_ERQ_ERQ13_SHIFT 13
bogdanm 82:6473597d706e 3574 #define DMA_ERQ_ERQ14_MASK 0x4000u
bogdanm 82:6473597d706e 3575 #define DMA_ERQ_ERQ14_SHIFT 14
bogdanm 82:6473597d706e 3576 #define DMA_ERQ_ERQ15_MASK 0x8000u
bogdanm 82:6473597d706e 3577 #define DMA_ERQ_ERQ15_SHIFT 15
bogdanm 82:6473597d706e 3578 /* EEI Bit Fields */
bogdanm 82:6473597d706e 3579 #define DMA_EEI_EEI0_MASK 0x1u
bogdanm 82:6473597d706e 3580 #define DMA_EEI_EEI0_SHIFT 0
bogdanm 82:6473597d706e 3581 #define DMA_EEI_EEI1_MASK 0x2u
bogdanm 82:6473597d706e 3582 #define DMA_EEI_EEI1_SHIFT 1
bogdanm 82:6473597d706e 3583 #define DMA_EEI_EEI2_MASK 0x4u
bogdanm 82:6473597d706e 3584 #define DMA_EEI_EEI2_SHIFT 2
bogdanm 82:6473597d706e 3585 #define DMA_EEI_EEI3_MASK 0x8u
bogdanm 82:6473597d706e 3586 #define DMA_EEI_EEI3_SHIFT 3
bogdanm 82:6473597d706e 3587 #define DMA_EEI_EEI4_MASK 0x10u
bogdanm 82:6473597d706e 3588 #define DMA_EEI_EEI4_SHIFT 4
bogdanm 82:6473597d706e 3589 #define DMA_EEI_EEI5_MASK 0x20u
bogdanm 82:6473597d706e 3590 #define DMA_EEI_EEI5_SHIFT 5
bogdanm 82:6473597d706e 3591 #define DMA_EEI_EEI6_MASK 0x40u
bogdanm 82:6473597d706e 3592 #define DMA_EEI_EEI6_SHIFT 6
bogdanm 82:6473597d706e 3593 #define DMA_EEI_EEI7_MASK 0x80u
bogdanm 82:6473597d706e 3594 #define DMA_EEI_EEI7_SHIFT 7
bogdanm 82:6473597d706e 3595 #define DMA_EEI_EEI8_MASK 0x100u
bogdanm 82:6473597d706e 3596 #define DMA_EEI_EEI8_SHIFT 8
bogdanm 82:6473597d706e 3597 #define DMA_EEI_EEI9_MASK 0x200u
bogdanm 82:6473597d706e 3598 #define DMA_EEI_EEI9_SHIFT 9
bogdanm 82:6473597d706e 3599 #define DMA_EEI_EEI10_MASK 0x400u
bogdanm 82:6473597d706e 3600 #define DMA_EEI_EEI10_SHIFT 10
bogdanm 82:6473597d706e 3601 #define DMA_EEI_EEI11_MASK 0x800u
bogdanm 82:6473597d706e 3602 #define DMA_EEI_EEI11_SHIFT 11
bogdanm 82:6473597d706e 3603 #define DMA_EEI_EEI12_MASK 0x1000u
bogdanm 82:6473597d706e 3604 #define DMA_EEI_EEI12_SHIFT 12
bogdanm 82:6473597d706e 3605 #define DMA_EEI_EEI13_MASK 0x2000u
bogdanm 82:6473597d706e 3606 #define DMA_EEI_EEI13_SHIFT 13
bogdanm 82:6473597d706e 3607 #define DMA_EEI_EEI14_MASK 0x4000u
bogdanm 82:6473597d706e 3608 #define DMA_EEI_EEI14_SHIFT 14
bogdanm 82:6473597d706e 3609 #define DMA_EEI_EEI15_MASK 0x8000u
bogdanm 82:6473597d706e 3610 #define DMA_EEI_EEI15_SHIFT 15
bogdanm 82:6473597d706e 3611 /* CEEI Bit Fields */
bogdanm 82:6473597d706e 3612 #define DMA_CEEI_CEEI_MASK 0xFu
bogdanm 82:6473597d706e 3613 #define DMA_CEEI_CEEI_SHIFT 0
bogdanm 82:6473597d706e 3614 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
bogdanm 82:6473597d706e 3615 #define DMA_CEEI_CAEE_MASK 0x40u
bogdanm 82:6473597d706e 3616 #define DMA_CEEI_CAEE_SHIFT 6
bogdanm 82:6473597d706e 3617 #define DMA_CEEI_NOP_MASK 0x80u
bogdanm 82:6473597d706e 3618 #define DMA_CEEI_NOP_SHIFT 7
bogdanm 82:6473597d706e 3619 /* SEEI Bit Fields */
bogdanm 82:6473597d706e 3620 #define DMA_SEEI_SEEI_MASK 0xFu
bogdanm 82:6473597d706e 3621 #define DMA_SEEI_SEEI_SHIFT 0
bogdanm 82:6473597d706e 3622 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
bogdanm 82:6473597d706e 3623 #define DMA_SEEI_SAEE_MASK 0x40u
bogdanm 82:6473597d706e 3624 #define DMA_SEEI_SAEE_SHIFT 6
bogdanm 82:6473597d706e 3625 #define DMA_SEEI_NOP_MASK 0x80u
bogdanm 82:6473597d706e 3626 #define DMA_SEEI_NOP_SHIFT 7
bogdanm 82:6473597d706e 3627 /* CERQ Bit Fields */
bogdanm 82:6473597d706e 3628 #define DMA_CERQ_CERQ_MASK 0xFu
bogdanm 82:6473597d706e 3629 #define DMA_CERQ_CERQ_SHIFT 0
bogdanm 82:6473597d706e 3630 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
bogdanm 82:6473597d706e 3631 #define DMA_CERQ_CAER_MASK 0x40u
bogdanm 82:6473597d706e 3632 #define DMA_CERQ_CAER_SHIFT 6
bogdanm 82:6473597d706e 3633 #define DMA_CERQ_NOP_MASK 0x80u
bogdanm 82:6473597d706e 3634 #define DMA_CERQ_NOP_SHIFT 7
bogdanm 82:6473597d706e 3635 /* SERQ Bit Fields */
bogdanm 82:6473597d706e 3636 #define DMA_SERQ_SERQ_MASK 0xFu
bogdanm 82:6473597d706e 3637 #define DMA_SERQ_SERQ_SHIFT 0
bogdanm 82:6473597d706e 3638 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
bogdanm 82:6473597d706e 3639 #define DMA_SERQ_SAER_MASK 0x40u
bogdanm 82:6473597d706e 3640 #define DMA_SERQ_SAER_SHIFT 6
bogdanm 82:6473597d706e 3641 #define DMA_SERQ_NOP_MASK 0x80u
bogdanm 82:6473597d706e 3642 #define DMA_SERQ_NOP_SHIFT 7
bogdanm 82:6473597d706e 3643 /* CDNE Bit Fields */
bogdanm 82:6473597d706e 3644 #define DMA_CDNE_CDNE_MASK 0xFu
bogdanm 82:6473597d706e 3645 #define DMA_CDNE_CDNE_SHIFT 0
bogdanm 82:6473597d706e 3646 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
bogdanm 82:6473597d706e 3647 #define DMA_CDNE_CADN_MASK 0x40u
bogdanm 82:6473597d706e 3648 #define DMA_CDNE_CADN_SHIFT 6
bogdanm 82:6473597d706e 3649 #define DMA_CDNE_NOP_MASK 0x80u
bogdanm 82:6473597d706e 3650 #define DMA_CDNE_NOP_SHIFT 7
bogdanm 82:6473597d706e 3651 /* SSRT Bit Fields */
bogdanm 82:6473597d706e 3652 #define DMA_SSRT_SSRT_MASK 0xFu
bogdanm 82:6473597d706e 3653 #define DMA_SSRT_SSRT_SHIFT 0
bogdanm 82:6473597d706e 3654 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
bogdanm 82:6473597d706e 3655 #define DMA_SSRT_SAST_MASK 0x40u
bogdanm 82:6473597d706e 3656 #define DMA_SSRT_SAST_SHIFT 6
bogdanm 82:6473597d706e 3657 #define DMA_SSRT_NOP_MASK 0x80u
bogdanm 82:6473597d706e 3658 #define DMA_SSRT_NOP_SHIFT 7
bogdanm 82:6473597d706e 3659 /* CERR Bit Fields */
bogdanm 82:6473597d706e 3660 #define DMA_CERR_CERR_MASK 0xFu
bogdanm 82:6473597d706e 3661 #define DMA_CERR_CERR_SHIFT 0
bogdanm 82:6473597d706e 3662 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
bogdanm 82:6473597d706e 3663 #define DMA_CERR_CAEI_MASK 0x40u
bogdanm 82:6473597d706e 3664 #define DMA_CERR_CAEI_SHIFT 6
bogdanm 82:6473597d706e 3665 #define DMA_CERR_NOP_MASK 0x80u
bogdanm 82:6473597d706e 3666 #define DMA_CERR_NOP_SHIFT 7
bogdanm 82:6473597d706e 3667 /* CINT Bit Fields */
bogdanm 82:6473597d706e 3668 #define DMA_CINT_CINT_MASK 0xFu
bogdanm 82:6473597d706e 3669 #define DMA_CINT_CINT_SHIFT 0
bogdanm 82:6473597d706e 3670 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
bogdanm 82:6473597d706e 3671 #define DMA_CINT_CAIR_MASK 0x40u
bogdanm 82:6473597d706e 3672 #define DMA_CINT_CAIR_SHIFT 6
bogdanm 82:6473597d706e 3673 #define DMA_CINT_NOP_MASK 0x80u
bogdanm 82:6473597d706e 3674 #define DMA_CINT_NOP_SHIFT 7
bogdanm 82:6473597d706e 3675 /* INT Bit Fields */
bogdanm 82:6473597d706e 3676 #define DMA_INT_INT0_MASK 0x1u
bogdanm 82:6473597d706e 3677 #define DMA_INT_INT0_SHIFT 0
bogdanm 82:6473597d706e 3678 #define DMA_INT_INT1_MASK 0x2u
bogdanm 82:6473597d706e 3679 #define DMA_INT_INT1_SHIFT 1
bogdanm 82:6473597d706e 3680 #define DMA_INT_INT2_MASK 0x4u
bogdanm 82:6473597d706e 3681 #define DMA_INT_INT2_SHIFT 2
bogdanm 82:6473597d706e 3682 #define DMA_INT_INT3_MASK 0x8u
bogdanm 82:6473597d706e 3683 #define DMA_INT_INT3_SHIFT 3
bogdanm 82:6473597d706e 3684 #define DMA_INT_INT4_MASK 0x10u
bogdanm 82:6473597d706e 3685 #define DMA_INT_INT4_SHIFT 4
bogdanm 82:6473597d706e 3686 #define DMA_INT_INT5_MASK 0x20u
bogdanm 82:6473597d706e 3687 #define DMA_INT_INT5_SHIFT 5
bogdanm 82:6473597d706e 3688 #define DMA_INT_INT6_MASK 0x40u
bogdanm 82:6473597d706e 3689 #define DMA_INT_INT6_SHIFT 6
bogdanm 82:6473597d706e 3690 #define DMA_INT_INT7_MASK 0x80u
bogdanm 82:6473597d706e 3691 #define DMA_INT_INT7_SHIFT 7
bogdanm 82:6473597d706e 3692 #define DMA_INT_INT8_MASK 0x100u
bogdanm 82:6473597d706e 3693 #define DMA_INT_INT8_SHIFT 8
bogdanm 82:6473597d706e 3694 #define DMA_INT_INT9_MASK 0x200u
bogdanm 82:6473597d706e 3695 #define DMA_INT_INT9_SHIFT 9
bogdanm 82:6473597d706e 3696 #define DMA_INT_INT10_MASK 0x400u
bogdanm 82:6473597d706e 3697 #define DMA_INT_INT10_SHIFT 10
bogdanm 82:6473597d706e 3698 #define DMA_INT_INT11_MASK 0x800u
bogdanm 82:6473597d706e 3699 #define DMA_INT_INT11_SHIFT 11
bogdanm 82:6473597d706e 3700 #define DMA_INT_INT12_MASK 0x1000u
bogdanm 82:6473597d706e 3701 #define DMA_INT_INT12_SHIFT 12
bogdanm 82:6473597d706e 3702 #define DMA_INT_INT13_MASK 0x2000u
bogdanm 82:6473597d706e 3703 #define DMA_INT_INT13_SHIFT 13
bogdanm 82:6473597d706e 3704 #define DMA_INT_INT14_MASK 0x4000u
bogdanm 82:6473597d706e 3705 #define DMA_INT_INT14_SHIFT 14
bogdanm 82:6473597d706e 3706 #define DMA_INT_INT15_MASK 0x8000u
bogdanm 82:6473597d706e 3707 #define DMA_INT_INT15_SHIFT 15
bogdanm 82:6473597d706e 3708 /* ERR Bit Fields */
bogdanm 82:6473597d706e 3709 #define DMA_ERR_ERR0_MASK 0x1u
bogdanm 82:6473597d706e 3710 #define DMA_ERR_ERR0_SHIFT 0
bogdanm 82:6473597d706e 3711 #define DMA_ERR_ERR1_MASK 0x2u
bogdanm 82:6473597d706e 3712 #define DMA_ERR_ERR1_SHIFT 1
bogdanm 82:6473597d706e 3713 #define DMA_ERR_ERR2_MASK 0x4u
bogdanm 82:6473597d706e 3714 #define DMA_ERR_ERR2_SHIFT 2
bogdanm 82:6473597d706e 3715 #define DMA_ERR_ERR3_MASK 0x8u
bogdanm 82:6473597d706e 3716 #define DMA_ERR_ERR3_SHIFT 3
bogdanm 82:6473597d706e 3717 #define DMA_ERR_ERR4_MASK 0x10u
bogdanm 82:6473597d706e 3718 #define DMA_ERR_ERR4_SHIFT 4
bogdanm 82:6473597d706e 3719 #define DMA_ERR_ERR5_MASK 0x20u
bogdanm 82:6473597d706e 3720 #define DMA_ERR_ERR5_SHIFT 5
bogdanm 82:6473597d706e 3721 #define DMA_ERR_ERR6_MASK 0x40u
bogdanm 82:6473597d706e 3722 #define DMA_ERR_ERR6_SHIFT 6
bogdanm 82:6473597d706e 3723 #define DMA_ERR_ERR7_MASK 0x80u
bogdanm 82:6473597d706e 3724 #define DMA_ERR_ERR7_SHIFT 7
bogdanm 82:6473597d706e 3725 #define DMA_ERR_ERR8_MASK 0x100u
bogdanm 82:6473597d706e 3726 #define DMA_ERR_ERR8_SHIFT 8
bogdanm 82:6473597d706e 3727 #define DMA_ERR_ERR9_MASK 0x200u
bogdanm 82:6473597d706e 3728 #define DMA_ERR_ERR9_SHIFT 9
bogdanm 82:6473597d706e 3729 #define DMA_ERR_ERR10_MASK 0x400u
bogdanm 82:6473597d706e 3730 #define DMA_ERR_ERR10_SHIFT 10
bogdanm 82:6473597d706e 3731 #define DMA_ERR_ERR11_MASK 0x800u
bogdanm 82:6473597d706e 3732 #define DMA_ERR_ERR11_SHIFT 11
bogdanm 82:6473597d706e 3733 #define DMA_ERR_ERR12_MASK 0x1000u
bogdanm 82:6473597d706e 3734 #define DMA_ERR_ERR12_SHIFT 12
bogdanm 82:6473597d706e 3735 #define DMA_ERR_ERR13_MASK 0x2000u
bogdanm 82:6473597d706e 3736 #define DMA_ERR_ERR13_SHIFT 13
bogdanm 82:6473597d706e 3737 #define DMA_ERR_ERR14_MASK 0x4000u
bogdanm 82:6473597d706e 3738 #define DMA_ERR_ERR14_SHIFT 14
bogdanm 82:6473597d706e 3739 #define DMA_ERR_ERR15_MASK 0x8000u
bogdanm 82:6473597d706e 3740 #define DMA_ERR_ERR15_SHIFT 15
bogdanm 82:6473597d706e 3741 /* HRS Bit Fields */
bogdanm 82:6473597d706e 3742 #define DMA_HRS_HRS0_MASK 0x1u
bogdanm 82:6473597d706e 3743 #define DMA_HRS_HRS0_SHIFT 0
bogdanm 82:6473597d706e 3744 #define DMA_HRS_HRS1_MASK 0x2u
bogdanm 82:6473597d706e 3745 #define DMA_HRS_HRS1_SHIFT 1
bogdanm 82:6473597d706e 3746 #define DMA_HRS_HRS2_MASK 0x4u
bogdanm 82:6473597d706e 3747 #define DMA_HRS_HRS2_SHIFT 2
bogdanm 82:6473597d706e 3748 #define DMA_HRS_HRS3_MASK 0x8u
bogdanm 82:6473597d706e 3749 #define DMA_HRS_HRS3_SHIFT 3
bogdanm 82:6473597d706e 3750 #define DMA_HRS_HRS4_MASK 0x10u
bogdanm 82:6473597d706e 3751 #define DMA_HRS_HRS4_SHIFT 4
bogdanm 82:6473597d706e 3752 #define DMA_HRS_HRS5_MASK 0x20u
bogdanm 82:6473597d706e 3753 #define DMA_HRS_HRS5_SHIFT 5
bogdanm 82:6473597d706e 3754 #define DMA_HRS_HRS6_MASK 0x40u
bogdanm 82:6473597d706e 3755 #define DMA_HRS_HRS6_SHIFT 6
bogdanm 82:6473597d706e 3756 #define DMA_HRS_HRS7_MASK 0x80u
bogdanm 82:6473597d706e 3757 #define DMA_HRS_HRS7_SHIFT 7
bogdanm 82:6473597d706e 3758 #define DMA_HRS_HRS8_MASK 0x100u
bogdanm 82:6473597d706e 3759 #define DMA_HRS_HRS8_SHIFT 8
bogdanm 82:6473597d706e 3760 #define DMA_HRS_HRS9_MASK 0x200u
bogdanm 82:6473597d706e 3761 #define DMA_HRS_HRS9_SHIFT 9
bogdanm 82:6473597d706e 3762 #define DMA_HRS_HRS10_MASK 0x400u
bogdanm 82:6473597d706e 3763 #define DMA_HRS_HRS10_SHIFT 10
bogdanm 82:6473597d706e 3764 #define DMA_HRS_HRS11_MASK 0x800u
bogdanm 82:6473597d706e 3765 #define DMA_HRS_HRS11_SHIFT 11
bogdanm 82:6473597d706e 3766 #define DMA_HRS_HRS12_MASK 0x1000u
bogdanm 82:6473597d706e 3767 #define DMA_HRS_HRS12_SHIFT 12
bogdanm 82:6473597d706e 3768 #define DMA_HRS_HRS13_MASK 0x2000u
bogdanm 82:6473597d706e 3769 #define DMA_HRS_HRS13_SHIFT 13
bogdanm 82:6473597d706e 3770 #define DMA_HRS_HRS14_MASK 0x4000u
bogdanm 82:6473597d706e 3771 #define DMA_HRS_HRS14_SHIFT 14
bogdanm 82:6473597d706e 3772 #define DMA_HRS_HRS15_MASK 0x8000u
bogdanm 82:6473597d706e 3773 #define DMA_HRS_HRS15_SHIFT 15
bogdanm 82:6473597d706e 3774 /* EARS Bit Fields */
bogdanm 82:6473597d706e 3775 #define DMA_EARS_EDREQ_0_MASK 0x1u
bogdanm 82:6473597d706e 3776 #define DMA_EARS_EDREQ_0_SHIFT 0
bogdanm 82:6473597d706e 3777 #define DMA_EARS_EDREQ_1_MASK 0x2u
bogdanm 82:6473597d706e 3778 #define DMA_EARS_EDREQ_1_SHIFT 1
bogdanm 82:6473597d706e 3779 #define DMA_EARS_EDREQ_2_MASK 0x4u
bogdanm 82:6473597d706e 3780 #define DMA_EARS_EDREQ_2_SHIFT 2
bogdanm 82:6473597d706e 3781 #define DMA_EARS_EDREQ_3_MASK 0x8u
bogdanm 82:6473597d706e 3782 #define DMA_EARS_EDREQ_3_SHIFT 3
bogdanm 82:6473597d706e 3783 #define DMA_EARS_EDREQ_4_MASK 0x10u
bogdanm 82:6473597d706e 3784 #define DMA_EARS_EDREQ_4_SHIFT 4
bogdanm 82:6473597d706e 3785 #define DMA_EARS_EDREQ_5_MASK 0x20u
bogdanm 82:6473597d706e 3786 #define DMA_EARS_EDREQ_5_SHIFT 5
bogdanm 82:6473597d706e 3787 #define DMA_EARS_EDREQ_6_MASK 0x40u
bogdanm 82:6473597d706e 3788 #define DMA_EARS_EDREQ_6_SHIFT 6
bogdanm 82:6473597d706e 3789 #define DMA_EARS_EDREQ_7_MASK 0x80u
bogdanm 82:6473597d706e 3790 #define DMA_EARS_EDREQ_7_SHIFT 7
bogdanm 82:6473597d706e 3791 #define DMA_EARS_EDREQ_8_MASK 0x100u
bogdanm 82:6473597d706e 3792 #define DMA_EARS_EDREQ_8_SHIFT 8
bogdanm 82:6473597d706e 3793 #define DMA_EARS_EDREQ_9_MASK 0x200u
bogdanm 82:6473597d706e 3794 #define DMA_EARS_EDREQ_9_SHIFT 9
bogdanm 82:6473597d706e 3795 #define DMA_EARS_EDREQ_10_MASK 0x400u
bogdanm 82:6473597d706e 3796 #define DMA_EARS_EDREQ_10_SHIFT 10
bogdanm 82:6473597d706e 3797 #define DMA_EARS_EDREQ_11_MASK 0x800u
bogdanm 82:6473597d706e 3798 #define DMA_EARS_EDREQ_11_SHIFT 11
bogdanm 82:6473597d706e 3799 #define DMA_EARS_EDREQ_12_MASK 0x1000u
bogdanm 82:6473597d706e 3800 #define DMA_EARS_EDREQ_12_SHIFT 12
bogdanm 82:6473597d706e 3801 #define DMA_EARS_EDREQ_13_MASK 0x2000u
bogdanm 82:6473597d706e 3802 #define DMA_EARS_EDREQ_13_SHIFT 13
bogdanm 82:6473597d706e 3803 #define DMA_EARS_EDREQ_14_MASK 0x4000u
bogdanm 82:6473597d706e 3804 #define DMA_EARS_EDREQ_14_SHIFT 14
bogdanm 82:6473597d706e 3805 #define DMA_EARS_EDREQ_15_MASK 0x8000u
bogdanm 82:6473597d706e 3806 #define DMA_EARS_EDREQ_15_SHIFT 15
bogdanm 82:6473597d706e 3807 /* DCHPRI3 Bit Fields */
bogdanm 82:6473597d706e 3808 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3809 #define DMA_DCHPRI3_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3810 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
bogdanm 82:6473597d706e 3811 #define DMA_DCHPRI3_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3812 #define DMA_DCHPRI3_DPA_SHIFT 6
bogdanm 82:6473597d706e 3813 #define DMA_DCHPRI3_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3814 #define DMA_DCHPRI3_ECP_SHIFT 7
bogdanm 82:6473597d706e 3815 /* DCHPRI2 Bit Fields */
bogdanm 82:6473597d706e 3816 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3817 #define DMA_DCHPRI2_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3818 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
bogdanm 82:6473597d706e 3819 #define DMA_DCHPRI2_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3820 #define DMA_DCHPRI2_DPA_SHIFT 6
bogdanm 82:6473597d706e 3821 #define DMA_DCHPRI2_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3822 #define DMA_DCHPRI2_ECP_SHIFT 7
bogdanm 82:6473597d706e 3823 /* DCHPRI1 Bit Fields */
bogdanm 82:6473597d706e 3824 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3825 #define DMA_DCHPRI1_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3826 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
bogdanm 82:6473597d706e 3827 #define DMA_DCHPRI1_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3828 #define DMA_DCHPRI1_DPA_SHIFT 6
bogdanm 82:6473597d706e 3829 #define DMA_DCHPRI1_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3830 #define DMA_DCHPRI1_ECP_SHIFT 7
bogdanm 82:6473597d706e 3831 /* DCHPRI0 Bit Fields */
bogdanm 82:6473597d706e 3832 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3833 #define DMA_DCHPRI0_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3834 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
bogdanm 82:6473597d706e 3835 #define DMA_DCHPRI0_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3836 #define DMA_DCHPRI0_DPA_SHIFT 6
bogdanm 82:6473597d706e 3837 #define DMA_DCHPRI0_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3838 #define DMA_DCHPRI0_ECP_SHIFT 7
bogdanm 82:6473597d706e 3839 /* DCHPRI7 Bit Fields */
bogdanm 82:6473597d706e 3840 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3841 #define DMA_DCHPRI7_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3842 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
bogdanm 82:6473597d706e 3843 #define DMA_DCHPRI7_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3844 #define DMA_DCHPRI7_DPA_SHIFT 6
bogdanm 82:6473597d706e 3845 #define DMA_DCHPRI7_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3846 #define DMA_DCHPRI7_ECP_SHIFT 7
bogdanm 82:6473597d706e 3847 /* DCHPRI6 Bit Fields */
bogdanm 82:6473597d706e 3848 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3849 #define DMA_DCHPRI6_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3850 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
bogdanm 82:6473597d706e 3851 #define DMA_DCHPRI6_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3852 #define DMA_DCHPRI6_DPA_SHIFT 6
bogdanm 82:6473597d706e 3853 #define DMA_DCHPRI6_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3854 #define DMA_DCHPRI6_ECP_SHIFT 7
bogdanm 82:6473597d706e 3855 /* DCHPRI5 Bit Fields */
bogdanm 82:6473597d706e 3856 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3857 #define DMA_DCHPRI5_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3858 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
bogdanm 82:6473597d706e 3859 #define DMA_DCHPRI5_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3860 #define DMA_DCHPRI5_DPA_SHIFT 6
bogdanm 82:6473597d706e 3861 #define DMA_DCHPRI5_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3862 #define DMA_DCHPRI5_ECP_SHIFT 7
bogdanm 82:6473597d706e 3863 /* DCHPRI4 Bit Fields */
bogdanm 82:6473597d706e 3864 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3865 #define DMA_DCHPRI4_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3866 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
bogdanm 82:6473597d706e 3867 #define DMA_DCHPRI4_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3868 #define DMA_DCHPRI4_DPA_SHIFT 6
bogdanm 82:6473597d706e 3869 #define DMA_DCHPRI4_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3870 #define DMA_DCHPRI4_ECP_SHIFT 7
bogdanm 82:6473597d706e 3871 /* DCHPRI11 Bit Fields */
bogdanm 82:6473597d706e 3872 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3873 #define DMA_DCHPRI11_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3874 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
bogdanm 82:6473597d706e 3875 #define DMA_DCHPRI11_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3876 #define DMA_DCHPRI11_DPA_SHIFT 6
bogdanm 82:6473597d706e 3877 #define DMA_DCHPRI11_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3878 #define DMA_DCHPRI11_ECP_SHIFT 7
bogdanm 82:6473597d706e 3879 /* DCHPRI10 Bit Fields */
bogdanm 82:6473597d706e 3880 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3881 #define DMA_DCHPRI10_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3882 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
bogdanm 82:6473597d706e 3883 #define DMA_DCHPRI10_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3884 #define DMA_DCHPRI10_DPA_SHIFT 6
bogdanm 82:6473597d706e 3885 #define DMA_DCHPRI10_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3886 #define DMA_DCHPRI10_ECP_SHIFT 7
bogdanm 82:6473597d706e 3887 /* DCHPRI9 Bit Fields */
bogdanm 82:6473597d706e 3888 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3889 #define DMA_DCHPRI9_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3890 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
bogdanm 82:6473597d706e 3891 #define DMA_DCHPRI9_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3892 #define DMA_DCHPRI9_DPA_SHIFT 6
bogdanm 82:6473597d706e 3893 #define DMA_DCHPRI9_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3894 #define DMA_DCHPRI9_ECP_SHIFT 7
bogdanm 82:6473597d706e 3895 /* DCHPRI8 Bit Fields */
bogdanm 82:6473597d706e 3896 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3897 #define DMA_DCHPRI8_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3898 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
bogdanm 82:6473597d706e 3899 #define DMA_DCHPRI8_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3900 #define DMA_DCHPRI8_DPA_SHIFT 6
bogdanm 82:6473597d706e 3901 #define DMA_DCHPRI8_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3902 #define DMA_DCHPRI8_ECP_SHIFT 7
bogdanm 82:6473597d706e 3903 /* DCHPRI15 Bit Fields */
bogdanm 82:6473597d706e 3904 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3905 #define DMA_DCHPRI15_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3906 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
bogdanm 82:6473597d706e 3907 #define DMA_DCHPRI15_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3908 #define DMA_DCHPRI15_DPA_SHIFT 6
bogdanm 82:6473597d706e 3909 #define DMA_DCHPRI15_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3910 #define DMA_DCHPRI15_ECP_SHIFT 7
bogdanm 82:6473597d706e 3911 /* DCHPRI14 Bit Fields */
bogdanm 82:6473597d706e 3912 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3913 #define DMA_DCHPRI14_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3914 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
bogdanm 82:6473597d706e 3915 #define DMA_DCHPRI14_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3916 #define DMA_DCHPRI14_DPA_SHIFT 6
bogdanm 82:6473597d706e 3917 #define DMA_DCHPRI14_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3918 #define DMA_DCHPRI14_ECP_SHIFT 7
bogdanm 82:6473597d706e 3919 /* DCHPRI13 Bit Fields */
bogdanm 82:6473597d706e 3920 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3921 #define DMA_DCHPRI13_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3922 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
bogdanm 82:6473597d706e 3923 #define DMA_DCHPRI13_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3924 #define DMA_DCHPRI13_DPA_SHIFT 6
bogdanm 82:6473597d706e 3925 #define DMA_DCHPRI13_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3926 #define DMA_DCHPRI13_ECP_SHIFT 7
bogdanm 82:6473597d706e 3927 /* DCHPRI12 Bit Fields */
bogdanm 82:6473597d706e 3928 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
bogdanm 82:6473597d706e 3929 #define DMA_DCHPRI12_CHPRI_SHIFT 0
bogdanm 82:6473597d706e 3930 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
bogdanm 82:6473597d706e 3931 #define DMA_DCHPRI12_DPA_MASK 0x40u
bogdanm 82:6473597d706e 3932 #define DMA_DCHPRI12_DPA_SHIFT 6
bogdanm 82:6473597d706e 3933 #define DMA_DCHPRI12_ECP_MASK 0x80u
bogdanm 82:6473597d706e 3934 #define DMA_DCHPRI12_ECP_SHIFT 7
bogdanm 82:6473597d706e 3935 /* SADDR Bit Fields */
bogdanm 82:6473597d706e 3936 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 3937 #define DMA_SADDR_SADDR_SHIFT 0
bogdanm 82:6473597d706e 3938 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
bogdanm 82:6473597d706e 3939 /* SOFF Bit Fields */
bogdanm 82:6473597d706e 3940 #define DMA_SOFF_SOFF_MASK 0xFFFFu
bogdanm 82:6473597d706e 3941 #define DMA_SOFF_SOFF_SHIFT 0
bogdanm 82:6473597d706e 3942 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
bogdanm 82:6473597d706e 3943 /* ATTR Bit Fields */
bogdanm 82:6473597d706e 3944 #define DMA_ATTR_DSIZE_MASK 0x7u
bogdanm 82:6473597d706e 3945 #define DMA_ATTR_DSIZE_SHIFT 0
bogdanm 82:6473597d706e 3946 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
bogdanm 82:6473597d706e 3947 #define DMA_ATTR_DMOD_MASK 0xF8u
bogdanm 82:6473597d706e 3948 #define DMA_ATTR_DMOD_SHIFT 3
bogdanm 82:6473597d706e 3949 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
bogdanm 82:6473597d706e 3950 #define DMA_ATTR_SSIZE_MASK 0x700u
bogdanm 82:6473597d706e 3951 #define DMA_ATTR_SSIZE_SHIFT 8
bogdanm 82:6473597d706e 3952 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
bogdanm 82:6473597d706e 3953 #define DMA_ATTR_SMOD_MASK 0xF800u
bogdanm 82:6473597d706e 3954 #define DMA_ATTR_SMOD_SHIFT 11
bogdanm 82:6473597d706e 3955 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
bogdanm 82:6473597d706e 3956 /* NBYTES_MLNO Bit Fields */
bogdanm 82:6473597d706e 3957 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 3958 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
bogdanm 82:6473597d706e 3959 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
bogdanm 82:6473597d706e 3960 /* NBYTES_MLOFFNO Bit Fields */
bogdanm 82:6473597d706e 3961 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
bogdanm 82:6473597d706e 3962 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
bogdanm 82:6473597d706e 3963 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
bogdanm 82:6473597d706e 3964 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
bogdanm 82:6473597d706e 3965 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
bogdanm 82:6473597d706e 3966 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
bogdanm 82:6473597d706e 3967 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
bogdanm 82:6473597d706e 3968 /* NBYTES_MLOFFYES Bit Fields */
bogdanm 82:6473597d706e 3969 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
bogdanm 82:6473597d706e 3970 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
bogdanm 82:6473597d706e 3971 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
bogdanm 82:6473597d706e 3972 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
bogdanm 82:6473597d706e 3973 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
bogdanm 82:6473597d706e 3974 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
bogdanm 82:6473597d706e 3975 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
bogdanm 82:6473597d706e 3976 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
bogdanm 82:6473597d706e 3977 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
bogdanm 82:6473597d706e 3978 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
bogdanm 82:6473597d706e 3979 /* SLAST Bit Fields */
bogdanm 82:6473597d706e 3980 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 3981 #define DMA_SLAST_SLAST_SHIFT 0
bogdanm 82:6473597d706e 3982 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
bogdanm 82:6473597d706e 3983 /* DADDR Bit Fields */
bogdanm 82:6473597d706e 3984 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 3985 #define DMA_DADDR_DADDR_SHIFT 0
bogdanm 82:6473597d706e 3986 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
bogdanm 82:6473597d706e 3987 /* DOFF Bit Fields */
bogdanm 82:6473597d706e 3988 #define DMA_DOFF_DOFF_MASK 0xFFFFu
bogdanm 82:6473597d706e 3989 #define DMA_DOFF_DOFF_SHIFT 0
bogdanm 82:6473597d706e 3990 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
bogdanm 82:6473597d706e 3991 /* CITER_ELINKNO Bit Fields */
bogdanm 82:6473597d706e 3992 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
bogdanm 82:6473597d706e 3993 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
bogdanm 82:6473597d706e 3994 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
bogdanm 82:6473597d706e 3995 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
bogdanm 82:6473597d706e 3996 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
bogdanm 82:6473597d706e 3997 /* CITER_ELINKYES Bit Fields */
bogdanm 82:6473597d706e 3998 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
bogdanm 82:6473597d706e 3999 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
bogdanm 82:6473597d706e 4000 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
bogdanm 82:6473597d706e 4001 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
bogdanm 82:6473597d706e 4002 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
bogdanm 82:6473597d706e 4003 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
bogdanm 82:6473597d706e 4004 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
bogdanm 82:6473597d706e 4005 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
bogdanm 82:6473597d706e 4006 /* DLAST_SGA Bit Fields */
bogdanm 82:6473597d706e 4007 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 4008 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
bogdanm 82:6473597d706e 4009 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
bogdanm 82:6473597d706e 4010 /* CSR Bit Fields */
bogdanm 82:6473597d706e 4011 #define DMA_CSR_START_MASK 0x1u
bogdanm 82:6473597d706e 4012 #define DMA_CSR_START_SHIFT 0
bogdanm 82:6473597d706e 4013 #define DMA_CSR_INTMAJOR_MASK 0x2u
bogdanm 82:6473597d706e 4014 #define DMA_CSR_INTMAJOR_SHIFT 1
bogdanm 82:6473597d706e 4015 #define DMA_CSR_INTHALF_MASK 0x4u
bogdanm 82:6473597d706e 4016 #define DMA_CSR_INTHALF_SHIFT 2
bogdanm 82:6473597d706e 4017 #define DMA_CSR_DREQ_MASK 0x8u
bogdanm 82:6473597d706e 4018 #define DMA_CSR_DREQ_SHIFT 3
bogdanm 82:6473597d706e 4019 #define DMA_CSR_ESG_MASK 0x10u
bogdanm 82:6473597d706e 4020 #define DMA_CSR_ESG_SHIFT 4
bogdanm 82:6473597d706e 4021 #define DMA_CSR_MAJORELINK_MASK 0x20u
bogdanm 82:6473597d706e 4022 #define DMA_CSR_MAJORELINK_SHIFT 5
bogdanm 82:6473597d706e 4023 #define DMA_CSR_ACTIVE_MASK 0x40u
bogdanm 82:6473597d706e 4024 #define DMA_CSR_ACTIVE_SHIFT 6
bogdanm 82:6473597d706e 4025 #define DMA_CSR_DONE_MASK 0x80u
bogdanm 82:6473597d706e 4026 #define DMA_CSR_DONE_SHIFT 7
bogdanm 82:6473597d706e 4027 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
bogdanm 82:6473597d706e 4028 #define DMA_CSR_MAJORLINKCH_SHIFT 8
bogdanm 82:6473597d706e 4029 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
bogdanm 82:6473597d706e 4030 #define DMA_CSR_BWC_MASK 0xC000u
bogdanm 82:6473597d706e 4031 #define DMA_CSR_BWC_SHIFT 14
bogdanm 82:6473597d706e 4032 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
bogdanm 82:6473597d706e 4033 /* BITER_ELINKNO Bit Fields */
bogdanm 82:6473597d706e 4034 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
bogdanm 82:6473597d706e 4035 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
bogdanm 82:6473597d706e 4036 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
bogdanm 82:6473597d706e 4037 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
bogdanm 82:6473597d706e 4038 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
bogdanm 82:6473597d706e 4039 /* BITER_ELINKYES Bit Fields */
bogdanm 82:6473597d706e 4040 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
bogdanm 82:6473597d706e 4041 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
bogdanm 82:6473597d706e 4042 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
bogdanm 82:6473597d706e 4043 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
bogdanm 82:6473597d706e 4044 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
bogdanm 82:6473597d706e 4045 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
bogdanm 82:6473597d706e 4046 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
bogdanm 82:6473597d706e 4047 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
bogdanm 82:6473597d706e 4048
bogdanm 82:6473597d706e 4049 /*!
bogdanm 82:6473597d706e 4050 * @}
bogdanm 82:6473597d706e 4051 */ /* end of group DMA_Register_Masks */
bogdanm 82:6473597d706e 4052
bogdanm 82:6473597d706e 4053
bogdanm 82:6473597d706e 4054 /* DMA - Peripheral instance base addresses */
bogdanm 82:6473597d706e 4055 /** Peripheral DMA base address */
bogdanm 82:6473597d706e 4056 #define DMA_BASE (0x40008000u)
bogdanm 82:6473597d706e 4057 /** Peripheral DMA base pointer */
bogdanm 82:6473597d706e 4058 #define DMA0 ((DMA_Type *)DMA_BASE)
bogdanm 82:6473597d706e 4059 #define DMA_BASE_PTR (DMA0)
bogdanm 82:6473597d706e 4060 /** Array initializer of DMA peripheral base pointers */
bogdanm 82:6473597d706e 4061 #define DMA_BASES { DMA0 }
bogdanm 82:6473597d706e 4062
bogdanm 82:6473597d706e 4063 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 4064 -- DMA - Register accessor macros
bogdanm 82:6473597d706e 4065 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 4066
bogdanm 82:6473597d706e 4067 /*!
bogdanm 82:6473597d706e 4068 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
bogdanm 82:6473597d706e 4069 * @{
bogdanm 82:6473597d706e 4070 */
bogdanm 82:6473597d706e 4071
bogdanm 82:6473597d706e 4072
bogdanm 82:6473597d706e 4073 /* DMA - Register instance definitions */
bogdanm 82:6473597d706e 4074 /* DMA */
bogdanm 82:6473597d706e 4075 #define DMA_CR DMA_CR_REG(DMA0)
bogdanm 82:6473597d706e 4076 #define DMA_ES DMA_ES_REG(DMA0)
bogdanm 82:6473597d706e 4077 #define DMA_ERQ DMA_ERQ_REG(DMA0)
bogdanm 82:6473597d706e 4078 #define DMA_EEI DMA_EEI_REG(DMA0)
bogdanm 82:6473597d706e 4079 #define DMA_CEEI DMA_CEEI_REG(DMA0)
bogdanm 82:6473597d706e 4080 #define DMA_SEEI DMA_SEEI_REG(DMA0)
bogdanm 82:6473597d706e 4081 #define DMA_CERQ DMA_CERQ_REG(DMA0)
bogdanm 82:6473597d706e 4082 #define DMA_SERQ DMA_SERQ_REG(DMA0)
bogdanm 82:6473597d706e 4083 #define DMA_CDNE DMA_CDNE_REG(DMA0)
bogdanm 82:6473597d706e 4084 #define DMA_SSRT DMA_SSRT_REG(DMA0)
bogdanm 82:6473597d706e 4085 #define DMA_CERR DMA_CERR_REG(DMA0)
bogdanm 82:6473597d706e 4086 #define DMA_CINT DMA_CINT_REG(DMA0)
bogdanm 82:6473597d706e 4087 #define DMA_INT DMA_INT_REG(DMA0)
bogdanm 82:6473597d706e 4088 #define DMA_ERR DMA_ERR_REG(DMA0)
bogdanm 82:6473597d706e 4089 #define DMA_HRS DMA_HRS_REG(DMA0)
bogdanm 82:6473597d706e 4090 #define DMA_EARS DMA_EARS_REG(DMA0)
bogdanm 82:6473597d706e 4091 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
bogdanm 82:6473597d706e 4092 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
bogdanm 82:6473597d706e 4093 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
bogdanm 82:6473597d706e 4094 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
bogdanm 82:6473597d706e 4095 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
bogdanm 82:6473597d706e 4096 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
bogdanm 82:6473597d706e 4097 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
bogdanm 82:6473597d706e 4098 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
bogdanm 82:6473597d706e 4099 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
bogdanm 82:6473597d706e 4100 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
bogdanm 82:6473597d706e 4101 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
bogdanm 82:6473597d706e 4102 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
bogdanm 82:6473597d706e 4103 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
bogdanm 82:6473597d706e 4104 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
bogdanm 82:6473597d706e 4105 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
bogdanm 82:6473597d706e 4106 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
bogdanm 82:6473597d706e 4107 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
bogdanm 82:6473597d706e 4108 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
bogdanm 82:6473597d706e 4109 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
bogdanm 82:6473597d706e 4110 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
bogdanm 82:6473597d706e 4111 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
bogdanm 82:6473597d706e 4112 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
bogdanm 82:6473597d706e 4113 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
bogdanm 82:6473597d706e 4114 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
bogdanm 82:6473597d706e 4115 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
bogdanm 82:6473597d706e 4116 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
bogdanm 82:6473597d706e 4117 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
bogdanm 82:6473597d706e 4118 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
bogdanm 82:6473597d706e 4119 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
bogdanm 82:6473597d706e 4120 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
bogdanm 82:6473597d706e 4121 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
bogdanm 82:6473597d706e 4122 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
bogdanm 82:6473597d706e 4123 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
bogdanm 82:6473597d706e 4124 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
bogdanm 82:6473597d706e 4125 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
bogdanm 82:6473597d706e 4126 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
bogdanm 82:6473597d706e 4127 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
bogdanm 82:6473597d706e 4128 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
bogdanm 82:6473597d706e 4129 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
bogdanm 82:6473597d706e 4130 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
bogdanm 82:6473597d706e 4131 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
bogdanm 82:6473597d706e 4132 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
bogdanm 82:6473597d706e 4133 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
bogdanm 82:6473597d706e 4134 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
bogdanm 82:6473597d706e 4135 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
bogdanm 82:6473597d706e 4136 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
bogdanm 82:6473597d706e 4137 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
bogdanm 82:6473597d706e 4138 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
bogdanm 82:6473597d706e 4139 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
bogdanm 82:6473597d706e 4140 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
bogdanm 82:6473597d706e 4141 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
bogdanm 82:6473597d706e 4142 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
bogdanm 82:6473597d706e 4143 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
bogdanm 82:6473597d706e 4144 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
bogdanm 82:6473597d706e 4145 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
bogdanm 82:6473597d706e 4146 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
bogdanm 82:6473597d706e 4147 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
bogdanm 82:6473597d706e 4148 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
bogdanm 82:6473597d706e 4149 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
bogdanm 82:6473597d706e 4150 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
bogdanm 82:6473597d706e 4151 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
bogdanm 82:6473597d706e 4152 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
bogdanm 82:6473597d706e 4153 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
bogdanm 82:6473597d706e 4154 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
bogdanm 82:6473597d706e 4155 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
bogdanm 82:6473597d706e 4156 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
bogdanm 82:6473597d706e 4157 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
bogdanm 82:6473597d706e 4158 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
bogdanm 82:6473597d706e 4159 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
bogdanm 82:6473597d706e 4160 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
bogdanm 82:6473597d706e 4161 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
bogdanm 82:6473597d706e 4162 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
bogdanm 82:6473597d706e 4163 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
bogdanm 82:6473597d706e 4164 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
bogdanm 82:6473597d706e 4165 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
bogdanm 82:6473597d706e 4166 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
bogdanm 82:6473597d706e 4167 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
bogdanm 82:6473597d706e 4168 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
bogdanm 82:6473597d706e 4169 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
bogdanm 82:6473597d706e 4170 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
bogdanm 82:6473597d706e 4171 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
bogdanm 82:6473597d706e 4172 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
bogdanm 82:6473597d706e 4173 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
bogdanm 82:6473597d706e 4174 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
bogdanm 82:6473597d706e 4175 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
bogdanm 82:6473597d706e 4176 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
bogdanm 82:6473597d706e 4177 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
bogdanm 82:6473597d706e 4178 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
bogdanm 82:6473597d706e 4179 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
bogdanm 82:6473597d706e 4180 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
bogdanm 82:6473597d706e 4181 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
bogdanm 82:6473597d706e 4182 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
bogdanm 82:6473597d706e 4183 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
bogdanm 82:6473597d706e 4184 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
bogdanm 82:6473597d706e 4185 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
bogdanm 82:6473597d706e 4186 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
bogdanm 82:6473597d706e 4187 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
bogdanm 82:6473597d706e 4188 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
bogdanm 82:6473597d706e 4189 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
bogdanm 82:6473597d706e 4190 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
bogdanm 82:6473597d706e 4191 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
bogdanm 82:6473597d706e 4192 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
bogdanm 82:6473597d706e 4193 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
bogdanm 82:6473597d706e 4194 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
bogdanm 82:6473597d706e 4195 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
bogdanm 82:6473597d706e 4196 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
bogdanm 82:6473597d706e 4197 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
bogdanm 82:6473597d706e 4198 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
bogdanm 82:6473597d706e 4199 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
bogdanm 82:6473597d706e 4200 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
bogdanm 82:6473597d706e 4201 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
bogdanm 82:6473597d706e 4202 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
bogdanm 82:6473597d706e 4203 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
bogdanm 82:6473597d706e 4204 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
bogdanm 82:6473597d706e 4205 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
bogdanm 82:6473597d706e 4206 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
bogdanm 82:6473597d706e 4207 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
bogdanm 82:6473597d706e 4208 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
bogdanm 82:6473597d706e 4209 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
bogdanm 82:6473597d706e 4210 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
bogdanm 82:6473597d706e 4211 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
bogdanm 82:6473597d706e 4212 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
bogdanm 82:6473597d706e 4213 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
bogdanm 82:6473597d706e 4214 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
bogdanm 82:6473597d706e 4215 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
bogdanm 82:6473597d706e 4216 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
bogdanm 82:6473597d706e 4217 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
bogdanm 82:6473597d706e 4218 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
bogdanm 82:6473597d706e 4219 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
bogdanm 82:6473597d706e 4220 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
bogdanm 82:6473597d706e 4221 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
bogdanm 82:6473597d706e 4222 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
bogdanm 82:6473597d706e 4223 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
bogdanm 82:6473597d706e 4224 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
bogdanm 82:6473597d706e 4225 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
bogdanm 82:6473597d706e 4226 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
bogdanm 82:6473597d706e 4227 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
bogdanm 82:6473597d706e 4228 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
bogdanm 82:6473597d706e 4229 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
bogdanm 82:6473597d706e 4230 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
bogdanm 82:6473597d706e 4231 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
bogdanm 82:6473597d706e 4232 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
bogdanm 82:6473597d706e 4233 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
bogdanm 82:6473597d706e 4234 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
bogdanm 82:6473597d706e 4235 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
bogdanm 82:6473597d706e 4236 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
bogdanm 82:6473597d706e 4237 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
bogdanm 82:6473597d706e 4238 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
bogdanm 82:6473597d706e 4239 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
bogdanm 82:6473597d706e 4240 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
bogdanm 82:6473597d706e 4241 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
bogdanm 82:6473597d706e 4242 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
bogdanm 82:6473597d706e 4243 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
bogdanm 82:6473597d706e 4244 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
bogdanm 82:6473597d706e 4245 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
bogdanm 82:6473597d706e 4246 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
bogdanm 82:6473597d706e 4247 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
bogdanm 82:6473597d706e 4248 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
bogdanm 82:6473597d706e 4249 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
bogdanm 82:6473597d706e 4250 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
bogdanm 82:6473597d706e 4251 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
bogdanm 82:6473597d706e 4252 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
bogdanm 82:6473597d706e 4253 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
bogdanm 82:6473597d706e 4254 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
bogdanm 82:6473597d706e 4255 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
bogdanm 82:6473597d706e 4256 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
bogdanm 82:6473597d706e 4257 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
bogdanm 82:6473597d706e 4258 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
bogdanm 82:6473597d706e 4259 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
bogdanm 82:6473597d706e 4260 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
bogdanm 82:6473597d706e 4261 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
bogdanm 82:6473597d706e 4262 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
bogdanm 82:6473597d706e 4263 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
bogdanm 82:6473597d706e 4264 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
bogdanm 82:6473597d706e 4265 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
bogdanm 82:6473597d706e 4266 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
bogdanm 82:6473597d706e 4267 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
bogdanm 82:6473597d706e 4268 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
bogdanm 82:6473597d706e 4269 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
bogdanm 82:6473597d706e 4270 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
bogdanm 82:6473597d706e 4271 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
bogdanm 82:6473597d706e 4272 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
bogdanm 82:6473597d706e 4273 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
bogdanm 82:6473597d706e 4274 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
bogdanm 82:6473597d706e 4275 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
bogdanm 82:6473597d706e 4276 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
bogdanm 82:6473597d706e 4277 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
bogdanm 82:6473597d706e 4278 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
bogdanm 82:6473597d706e 4279 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
bogdanm 82:6473597d706e 4280 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
bogdanm 82:6473597d706e 4281 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
bogdanm 82:6473597d706e 4282 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
bogdanm 82:6473597d706e 4283 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
bogdanm 82:6473597d706e 4284 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
bogdanm 82:6473597d706e 4285 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
bogdanm 82:6473597d706e 4286 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
bogdanm 82:6473597d706e 4287 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
bogdanm 82:6473597d706e 4288 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
bogdanm 82:6473597d706e 4289 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
bogdanm 82:6473597d706e 4290 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
bogdanm 82:6473597d706e 4291 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
bogdanm 82:6473597d706e 4292 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
bogdanm 82:6473597d706e 4293 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
bogdanm 82:6473597d706e 4294 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
bogdanm 82:6473597d706e 4295 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
bogdanm 82:6473597d706e 4296 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
bogdanm 82:6473597d706e 4297 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
bogdanm 82:6473597d706e 4298 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
bogdanm 82:6473597d706e 4299 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
bogdanm 82:6473597d706e 4300 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
bogdanm 82:6473597d706e 4301 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
bogdanm 82:6473597d706e 4302 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
bogdanm 82:6473597d706e 4303 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
bogdanm 82:6473597d706e 4304 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
bogdanm 82:6473597d706e 4305 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
bogdanm 82:6473597d706e 4306 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
bogdanm 82:6473597d706e 4307 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
bogdanm 82:6473597d706e 4308 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
bogdanm 82:6473597d706e 4309 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
bogdanm 82:6473597d706e 4310 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
bogdanm 82:6473597d706e 4311 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
bogdanm 82:6473597d706e 4312 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
bogdanm 82:6473597d706e 4313 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
bogdanm 82:6473597d706e 4314 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
bogdanm 82:6473597d706e 4315 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
bogdanm 82:6473597d706e 4316 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
bogdanm 82:6473597d706e 4317 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
bogdanm 82:6473597d706e 4318 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
bogdanm 82:6473597d706e 4319 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
bogdanm 82:6473597d706e 4320 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
bogdanm 82:6473597d706e 4321 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
bogdanm 82:6473597d706e 4322 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
bogdanm 82:6473597d706e 4323 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
bogdanm 82:6473597d706e 4324 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
bogdanm 82:6473597d706e 4325 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
bogdanm 82:6473597d706e 4326 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
bogdanm 82:6473597d706e 4327 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
bogdanm 82:6473597d706e 4328 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
bogdanm 82:6473597d706e 4329 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
bogdanm 82:6473597d706e 4330 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
bogdanm 82:6473597d706e 4331 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
bogdanm 82:6473597d706e 4332 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
bogdanm 82:6473597d706e 4333 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
bogdanm 82:6473597d706e 4334 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
bogdanm 82:6473597d706e 4335 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
bogdanm 82:6473597d706e 4336 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
bogdanm 82:6473597d706e 4337 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
bogdanm 82:6473597d706e 4338 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
bogdanm 82:6473597d706e 4339 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
bogdanm 82:6473597d706e 4340 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
bogdanm 82:6473597d706e 4341 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
bogdanm 82:6473597d706e 4342 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
bogdanm 82:6473597d706e 4343 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
bogdanm 82:6473597d706e 4344 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
bogdanm 82:6473597d706e 4345 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
bogdanm 82:6473597d706e 4346 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
bogdanm 82:6473597d706e 4347
bogdanm 82:6473597d706e 4348 /* DMA - Register array accessors */
bogdanm 82:6473597d706e 4349 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
bogdanm 82:6473597d706e 4350 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
bogdanm 82:6473597d706e 4351 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
bogdanm 82:6473597d706e 4352 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
bogdanm 82:6473597d706e 4353 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
bogdanm 82:6473597d706e 4354 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
bogdanm 82:6473597d706e 4355 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
bogdanm 82:6473597d706e 4356 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
bogdanm 82:6473597d706e 4357 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
bogdanm 82:6473597d706e 4358 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
bogdanm 82:6473597d706e 4359 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
bogdanm 82:6473597d706e 4360 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
bogdanm 82:6473597d706e 4361 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
bogdanm 82:6473597d706e 4362 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
bogdanm 82:6473597d706e 4363 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
bogdanm 82:6473597d706e 4364
bogdanm 82:6473597d706e 4365 /*!
bogdanm 82:6473597d706e 4366 * @}
bogdanm 82:6473597d706e 4367 */ /* end of group DMA_Register_Accessor_Macros */
bogdanm 82:6473597d706e 4368
bogdanm 82:6473597d706e 4369
bogdanm 82:6473597d706e 4370 /*!
bogdanm 82:6473597d706e 4371 * @}
bogdanm 82:6473597d706e 4372 */ /* end of group DMA_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 4373
bogdanm 82:6473597d706e 4374
bogdanm 82:6473597d706e 4375 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 4376 -- DMAMUX Peripheral Access Layer
bogdanm 82:6473597d706e 4377 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 4378
bogdanm 82:6473597d706e 4379 /*!
bogdanm 82:6473597d706e 4380 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
bogdanm 82:6473597d706e 4381 * @{
bogdanm 82:6473597d706e 4382 */
bogdanm 82:6473597d706e 4383
bogdanm 82:6473597d706e 4384 /** DMAMUX - Register Layout Typedef */
bogdanm 82:6473597d706e 4385 typedef struct {
bogdanm 82:6473597d706e 4386 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
bogdanm 82:6473597d706e 4387 } DMAMUX_Type, *DMAMUX_MemMapPtr;
bogdanm 82:6473597d706e 4388
bogdanm 82:6473597d706e 4389 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 4390 -- DMAMUX - Register accessor macros
bogdanm 82:6473597d706e 4391 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 4392
bogdanm 82:6473597d706e 4393 /*!
bogdanm 82:6473597d706e 4394 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
bogdanm 82:6473597d706e 4395 * @{
bogdanm 82:6473597d706e 4396 */
bogdanm 82:6473597d706e 4397
bogdanm 82:6473597d706e 4398
bogdanm 82:6473597d706e 4399 /* DMAMUX - Register accessors */
bogdanm 82:6473597d706e 4400 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
bogdanm 82:6473597d706e 4401
bogdanm 82:6473597d706e 4402 /*!
bogdanm 82:6473597d706e 4403 * @}
bogdanm 82:6473597d706e 4404 */ /* end of group DMAMUX_Register_Accessor_Macros */
bogdanm 82:6473597d706e 4405
bogdanm 82:6473597d706e 4406
bogdanm 82:6473597d706e 4407 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 4408 -- DMAMUX Register Masks
bogdanm 82:6473597d706e 4409 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 4410
bogdanm 82:6473597d706e 4411 /*!
bogdanm 82:6473597d706e 4412 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
bogdanm 82:6473597d706e 4413 * @{
bogdanm 82:6473597d706e 4414 */
bogdanm 82:6473597d706e 4415
bogdanm 82:6473597d706e 4416 /* CHCFG Bit Fields */
bogdanm 82:6473597d706e 4417 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
bogdanm 82:6473597d706e 4418 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
bogdanm 82:6473597d706e 4419 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
bogdanm 82:6473597d706e 4420 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
bogdanm 82:6473597d706e 4421 #define DMAMUX_CHCFG_TRIG_SHIFT 6
bogdanm 82:6473597d706e 4422 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
bogdanm 82:6473597d706e 4423 #define DMAMUX_CHCFG_ENBL_SHIFT 7
bogdanm 82:6473597d706e 4424
bogdanm 82:6473597d706e 4425 /*!
bogdanm 82:6473597d706e 4426 * @}
bogdanm 82:6473597d706e 4427 */ /* end of group DMAMUX_Register_Masks */
bogdanm 82:6473597d706e 4428
bogdanm 82:6473597d706e 4429
bogdanm 82:6473597d706e 4430 /* DMAMUX - Peripheral instance base addresses */
bogdanm 82:6473597d706e 4431 /** Peripheral DMAMUX base address */
bogdanm 82:6473597d706e 4432 #define DMAMUX_BASE (0x40021000u)
bogdanm 82:6473597d706e 4433 /** Peripheral DMAMUX base pointer */
bogdanm 82:6473597d706e 4434 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
bogdanm 82:6473597d706e 4435 #define DMAMUX_BASE_PTR (DMAMUX)
bogdanm 82:6473597d706e 4436 /** Array initializer of DMAMUX peripheral base pointers */
bogdanm 82:6473597d706e 4437 #define DMAMUX_BASES { DMAMUX }
bogdanm 82:6473597d706e 4438
bogdanm 82:6473597d706e 4439 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 4440 -- DMAMUX - Register accessor macros
bogdanm 82:6473597d706e 4441 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 4442
bogdanm 82:6473597d706e 4443 /*!
bogdanm 82:6473597d706e 4444 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
bogdanm 82:6473597d706e 4445 * @{
bogdanm 82:6473597d706e 4446 */
bogdanm 82:6473597d706e 4447
bogdanm 82:6473597d706e 4448
bogdanm 82:6473597d706e 4449 /* DMAMUX - Register instance definitions */
bogdanm 82:6473597d706e 4450 /* DMAMUX */
bogdanm 82:6473597d706e 4451 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
bogdanm 82:6473597d706e 4452 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
bogdanm 82:6473597d706e 4453 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
bogdanm 82:6473597d706e 4454 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
bogdanm 82:6473597d706e 4455 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
bogdanm 82:6473597d706e 4456 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
bogdanm 82:6473597d706e 4457 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
bogdanm 82:6473597d706e 4458 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
bogdanm 82:6473597d706e 4459 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
bogdanm 82:6473597d706e 4460 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
bogdanm 82:6473597d706e 4461 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
bogdanm 82:6473597d706e 4462 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
bogdanm 82:6473597d706e 4463 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
bogdanm 82:6473597d706e 4464 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
bogdanm 82:6473597d706e 4465 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
bogdanm 82:6473597d706e 4466 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
bogdanm 82:6473597d706e 4467
bogdanm 82:6473597d706e 4468 /* DMAMUX - Register array accessors */
bogdanm 82:6473597d706e 4469 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
bogdanm 82:6473597d706e 4470
bogdanm 82:6473597d706e 4471 /*!
bogdanm 82:6473597d706e 4472 * @}
bogdanm 82:6473597d706e 4473 */ /* end of group DMAMUX_Register_Accessor_Macros */
bogdanm 82:6473597d706e 4474
bogdanm 82:6473597d706e 4475
bogdanm 82:6473597d706e 4476 /*!
bogdanm 82:6473597d706e 4477 * @}
bogdanm 82:6473597d706e 4478 */ /* end of group DMAMUX_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 4479
bogdanm 82:6473597d706e 4480
bogdanm 82:6473597d706e 4481 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 4482 -- ENET Peripheral Access Layer
bogdanm 82:6473597d706e 4483 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 4484
bogdanm 82:6473597d706e 4485 /*!
bogdanm 82:6473597d706e 4486 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
bogdanm 82:6473597d706e 4487 * @{
bogdanm 82:6473597d706e 4488 */
bogdanm 82:6473597d706e 4489
bogdanm 82:6473597d706e 4490 /** ENET - Register Layout Typedef */
bogdanm 82:6473597d706e 4491 typedef struct {
bogdanm 82:6473597d706e 4492 uint8_t RESERVED_0[4];
bogdanm 82:6473597d706e 4493 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
bogdanm 82:6473597d706e 4494 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
bogdanm 82:6473597d706e 4495 uint8_t RESERVED_1[4];
bogdanm 82:6473597d706e 4496 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
bogdanm 82:6473597d706e 4497 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
bogdanm 82:6473597d706e 4498 uint8_t RESERVED_2[12];
bogdanm 82:6473597d706e 4499 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
bogdanm 82:6473597d706e 4500 uint8_t RESERVED_3[24];
bogdanm 82:6473597d706e 4501 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
bogdanm 82:6473597d706e 4502 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
bogdanm 82:6473597d706e 4503 uint8_t RESERVED_4[28];
bogdanm 82:6473597d706e 4504 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
bogdanm 82:6473597d706e 4505 uint8_t RESERVED_5[28];
bogdanm 82:6473597d706e 4506 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
bogdanm 82:6473597d706e 4507 uint8_t RESERVED_6[60];
bogdanm 82:6473597d706e 4508 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
bogdanm 82:6473597d706e 4509 uint8_t RESERVED_7[28];
bogdanm 82:6473597d706e 4510 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
bogdanm 82:6473597d706e 4511 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
bogdanm 82:6473597d706e 4512 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
bogdanm 82:6473597d706e 4513 uint8_t RESERVED_8[40];
bogdanm 82:6473597d706e 4514 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
bogdanm 82:6473597d706e 4515 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
bogdanm 82:6473597d706e 4516 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
bogdanm 82:6473597d706e 4517 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
bogdanm 82:6473597d706e 4518 uint8_t RESERVED_9[28];
bogdanm 82:6473597d706e 4519 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
bogdanm 82:6473597d706e 4520 uint8_t RESERVED_10[56];
bogdanm 82:6473597d706e 4521 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
bogdanm 82:6473597d706e 4522 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
bogdanm 82:6473597d706e 4523 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
bogdanm 82:6473597d706e 4524 uint8_t RESERVED_11[4];
bogdanm 82:6473597d706e 4525 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
bogdanm 82:6473597d706e 4526 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
bogdanm 82:6473597d706e 4527 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
bogdanm 82:6473597d706e 4528 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
bogdanm 82:6473597d706e 4529 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
bogdanm 82:6473597d706e 4530 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
bogdanm 82:6473597d706e 4531 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
bogdanm 82:6473597d706e 4532 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
bogdanm 82:6473597d706e 4533 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
bogdanm 82:6473597d706e 4534 uint8_t RESERVED_12[12];
bogdanm 82:6473597d706e 4535 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
bogdanm 82:6473597d706e 4536 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
bogdanm 82:6473597d706e 4537 uint8_t RESERVED_13[56];
bogdanm 82:6473597d706e 4538 __IO uint32_t RMON_T_DROP; /**< Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200 */
bogdanm 82:6473597d706e 4539 __IO uint32_t RMON_T_PACKETS; /**< RMON Tx packet count (RMON_T_PACKETS), offset: 0x204 */
bogdanm 82:6473597d706e 4540 __IO uint32_t RMON_T_BC_PKT; /**< RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208 */
bogdanm 82:6473597d706e 4541 __IO uint32_t RMON_T_MC_PKT; /**< RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C */
bogdanm 82:6473597d706e 4542 __IO uint32_t RMON_T_CRC_ALIGN; /**< RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210 */
bogdanm 82:6473597d706e 4543 __IO uint32_t RMON_T_UNDERSIZE; /**< RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214 */
bogdanm 82:6473597d706e 4544 __IO uint32_t RMON_T_OVERSIZE; /**< RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */
bogdanm 82:6473597d706e 4545 __IO uint32_t RMON_T_FRAG; /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */
bogdanm 82:6473597d706e 4546 __IO uint32_t RMON_T_JAB; /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */
bogdanm 82:6473597d706e 4547 __IO uint32_t RMON_T_COL; /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */
bogdanm 82:6473597d706e 4548 __IO uint32_t RMON_T_P64; /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */
bogdanm 82:6473597d706e 4549 __IO uint32_t RMON_T_P65TO127; /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */
bogdanm 82:6473597d706e 4550 __IO uint32_t RMON_T_P128TO255; /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */
bogdanm 82:6473597d706e 4551 __IO uint32_t RMON_T_P256TO511; /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */
bogdanm 82:6473597d706e 4552 __IO uint32_t RMON_T_P512TO1023; /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */
bogdanm 82:6473597d706e 4553 __IO uint32_t RMON_T_P1024TO2047; /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */
bogdanm 82:6473597d706e 4554 __IO uint32_t RMON_T_P_GTE2048; /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */
bogdanm 82:6473597d706e 4555 __IO uint32_t RMON_T_OCTETS; /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */
bogdanm 82:6473597d706e 4556 __IO uint32_t IEEE_T_DROP; /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */
bogdanm 82:6473597d706e 4557 __IO uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */
bogdanm 82:6473597d706e 4558 __IO uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */
bogdanm 82:6473597d706e 4559 __IO uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */
bogdanm 82:6473597d706e 4560 __IO uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */
bogdanm 82:6473597d706e 4561 __IO uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */
bogdanm 82:6473597d706e 4562 __IO uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */
bogdanm 82:6473597d706e 4563 __IO uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */
bogdanm 82:6473597d706e 4564 __IO uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */
bogdanm 82:6473597d706e 4565 __IO uint32_t IEEE_T_SQE; /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */
bogdanm 82:6473597d706e 4566 __IO uint32_t IEEE_T_FDXFC; /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */
bogdanm 82:6473597d706e 4567 __IO uint32_t IEEE_T_OCTETS_OK; /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */
bogdanm 82:6473597d706e 4568 uint8_t RESERVED_14[12];
bogdanm 82:6473597d706e 4569 __IO uint32_t RMON_R_PACKETS; /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */
bogdanm 82:6473597d706e 4570 __IO uint32_t RMON_R_BC_PKT; /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */
bogdanm 82:6473597d706e 4571 __IO uint32_t RMON_R_MC_PKT; /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */
bogdanm 82:6473597d706e 4572 __IO uint32_t RMON_R_CRC_ALIGN; /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */
bogdanm 82:6473597d706e 4573 __IO uint32_t RMON_R_UNDERSIZE; /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */
bogdanm 82:6473597d706e 4574 __IO uint32_t RMON_R_OVERSIZE; /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */
bogdanm 82:6473597d706e 4575 __IO uint32_t RMON_R_FRAG; /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */
bogdanm 82:6473597d706e 4576 __IO uint32_t RMON_R_JAB; /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */
bogdanm 82:6473597d706e 4577 __IO uint32_t RMON_R_RESVD_0; /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */
bogdanm 82:6473597d706e 4578 __IO uint32_t RMON_R_P64; /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */
bogdanm 82:6473597d706e 4579 __IO uint32_t RMON_R_P65TO127; /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */
bogdanm 82:6473597d706e 4580 __IO uint32_t RMON_R_P128TO255; /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */
bogdanm 82:6473597d706e 4581 __IO uint32_t RMON_R_P256TO511; /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */
bogdanm 82:6473597d706e 4582 __IO uint32_t RMON_R_P512TO1023; /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */
bogdanm 82:6473597d706e 4583 __IO uint32_t RMON_R_P1024TO2047; /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */
bogdanm 82:6473597d706e 4584 __IO uint32_t RMON_R_P_GTE2048; /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */
bogdanm 82:6473597d706e 4585 __IO uint32_t RMON_R_OCTETS; /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */
bogdanm 82:6473597d706e 4586 __IO uint32_t RMON_R_DROP; /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */
bogdanm 82:6473597d706e 4587 __IO uint32_t RMON_R_FRAME_OK; /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */
bogdanm 82:6473597d706e 4588 __IO uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */
bogdanm 82:6473597d706e 4589 __IO uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */
bogdanm 82:6473597d706e 4590 __IO uint32_t IEEE_R_MACERR; /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */
bogdanm 82:6473597d706e 4591 __IO uint32_t IEEE_R_FDXFC; /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */
bogdanm 82:6473597d706e 4592 __IO uint32_t IEEE_R_OCTETS_OK; /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */
bogdanm 82:6473597d706e 4593 uint8_t RESERVED_15[284];
bogdanm 82:6473597d706e 4594 __IO uint32_t ATCR; /**< Timer Control Register, offset: 0x400 */
bogdanm 82:6473597d706e 4595 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
bogdanm 82:6473597d706e 4596 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
bogdanm 82:6473597d706e 4597 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
bogdanm 82:6473597d706e 4598 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
bogdanm 82:6473597d706e 4599 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
bogdanm 82:6473597d706e 4600 __IO uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
bogdanm 82:6473597d706e 4601 uint8_t RESERVED_16[488];
bogdanm 82:6473597d706e 4602 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
bogdanm 82:6473597d706e 4603 struct { /* offset: 0x608, array step: 0x8 */
bogdanm 82:6473597d706e 4604 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
bogdanm 82:6473597d706e 4605 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
bogdanm 82:6473597d706e 4606 } CHANNEL[4];
bogdanm 82:6473597d706e 4607 } ENET_Type, *ENET_MemMapPtr;
bogdanm 82:6473597d706e 4608
bogdanm 82:6473597d706e 4609 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 4610 -- ENET - Register accessor macros
bogdanm 82:6473597d706e 4611 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 4612
bogdanm 82:6473597d706e 4613 /*!
bogdanm 82:6473597d706e 4614 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
bogdanm 82:6473597d706e 4615 * @{
bogdanm 82:6473597d706e 4616 */
bogdanm 82:6473597d706e 4617
bogdanm 82:6473597d706e 4618
bogdanm 82:6473597d706e 4619 /* ENET - Register accessors */
bogdanm 82:6473597d706e 4620 #define ENET_EIR_REG(base) ((base)->EIR)
bogdanm 82:6473597d706e 4621 #define ENET_EIMR_REG(base) ((base)->EIMR)
bogdanm 82:6473597d706e 4622 #define ENET_RDAR_REG(base) ((base)->RDAR)
bogdanm 82:6473597d706e 4623 #define ENET_TDAR_REG(base) ((base)->TDAR)
bogdanm 82:6473597d706e 4624 #define ENET_ECR_REG(base) ((base)->ECR)
bogdanm 82:6473597d706e 4625 #define ENET_MMFR_REG(base) ((base)->MMFR)
bogdanm 82:6473597d706e 4626 #define ENET_MSCR_REG(base) ((base)->MSCR)
bogdanm 82:6473597d706e 4627 #define ENET_MIBC_REG(base) ((base)->MIBC)
bogdanm 82:6473597d706e 4628 #define ENET_RCR_REG(base) ((base)->RCR)
bogdanm 82:6473597d706e 4629 #define ENET_TCR_REG(base) ((base)->TCR)
bogdanm 82:6473597d706e 4630 #define ENET_PALR_REG(base) ((base)->PALR)
bogdanm 82:6473597d706e 4631 #define ENET_PAUR_REG(base) ((base)->PAUR)
bogdanm 82:6473597d706e 4632 #define ENET_OPD_REG(base) ((base)->OPD)
bogdanm 82:6473597d706e 4633 #define ENET_IAUR_REG(base) ((base)->IAUR)
bogdanm 82:6473597d706e 4634 #define ENET_IALR_REG(base) ((base)->IALR)
bogdanm 82:6473597d706e 4635 #define ENET_GAUR_REG(base) ((base)->GAUR)
bogdanm 82:6473597d706e 4636 #define ENET_GALR_REG(base) ((base)->GALR)
bogdanm 82:6473597d706e 4637 #define ENET_TFWR_REG(base) ((base)->TFWR)
bogdanm 82:6473597d706e 4638 #define ENET_RDSR_REG(base) ((base)->RDSR)
bogdanm 82:6473597d706e 4639 #define ENET_TDSR_REG(base) ((base)->TDSR)
bogdanm 82:6473597d706e 4640 #define ENET_MRBR_REG(base) ((base)->MRBR)
bogdanm 82:6473597d706e 4641 #define ENET_RSFL_REG(base) ((base)->RSFL)
bogdanm 82:6473597d706e 4642 #define ENET_RSEM_REG(base) ((base)->RSEM)
bogdanm 82:6473597d706e 4643 #define ENET_RAEM_REG(base) ((base)->RAEM)
bogdanm 82:6473597d706e 4644 #define ENET_RAFL_REG(base) ((base)->RAFL)
bogdanm 82:6473597d706e 4645 #define ENET_TSEM_REG(base) ((base)->TSEM)
bogdanm 82:6473597d706e 4646 #define ENET_TAEM_REG(base) ((base)->TAEM)
bogdanm 82:6473597d706e 4647 #define ENET_TAFL_REG(base) ((base)->TAFL)
bogdanm 82:6473597d706e 4648 #define ENET_TIPG_REG(base) ((base)->TIPG)
bogdanm 82:6473597d706e 4649 #define ENET_FTRL_REG(base) ((base)->FTRL)
bogdanm 82:6473597d706e 4650 #define ENET_TACC_REG(base) ((base)->TACC)
bogdanm 82:6473597d706e 4651 #define ENET_RACC_REG(base) ((base)->RACC)
bogdanm 82:6473597d706e 4652 #define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP)
bogdanm 82:6473597d706e 4653 #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
bogdanm 82:6473597d706e 4654 #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
bogdanm 82:6473597d706e 4655 #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
bogdanm 82:6473597d706e 4656 #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
bogdanm 82:6473597d706e 4657 #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
bogdanm 82:6473597d706e 4658 #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
bogdanm 82:6473597d706e 4659 #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
bogdanm 82:6473597d706e 4660 #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
bogdanm 82:6473597d706e 4661 #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
bogdanm 82:6473597d706e 4662 #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
bogdanm 82:6473597d706e 4663 #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
bogdanm 82:6473597d706e 4664 #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
bogdanm 82:6473597d706e 4665 #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
bogdanm 82:6473597d706e 4666 #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
bogdanm 82:6473597d706e 4667 #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
bogdanm 82:6473597d706e 4668 #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
bogdanm 82:6473597d706e 4669 #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
bogdanm 82:6473597d706e 4670 #define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP)
bogdanm 82:6473597d706e 4671 #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
bogdanm 82:6473597d706e 4672 #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
bogdanm 82:6473597d706e 4673 #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
bogdanm 82:6473597d706e 4674 #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
bogdanm 82:6473597d706e 4675 #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
bogdanm 82:6473597d706e 4676 #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
bogdanm 82:6473597d706e 4677 #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
bogdanm 82:6473597d706e 4678 #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
bogdanm 82:6473597d706e 4679 #define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE)
bogdanm 82:6473597d706e 4680 #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
bogdanm 82:6473597d706e 4681 #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
bogdanm 82:6473597d706e 4682 #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
bogdanm 82:6473597d706e 4683 #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
bogdanm 82:6473597d706e 4684 #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
bogdanm 82:6473597d706e 4685 #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
bogdanm 82:6473597d706e 4686 #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
bogdanm 82:6473597d706e 4687 #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
bogdanm 82:6473597d706e 4688 #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
bogdanm 82:6473597d706e 4689 #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
bogdanm 82:6473597d706e 4690 #define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0)
bogdanm 82:6473597d706e 4691 #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
bogdanm 82:6473597d706e 4692 #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
bogdanm 82:6473597d706e 4693 #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
bogdanm 82:6473597d706e 4694 #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
bogdanm 82:6473597d706e 4695 #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
bogdanm 82:6473597d706e 4696 #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
bogdanm 82:6473597d706e 4697 #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)
bogdanm 82:6473597d706e 4698 #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
bogdanm 82:6473597d706e 4699 #define ENET_RMON_R_DROP_REG(base) ((base)->RMON_R_DROP)
bogdanm 82:6473597d706e 4700 #define ENET_RMON_R_FRAME_OK_REG(base) ((base)->RMON_R_FRAME_OK)
bogdanm 82:6473597d706e 4701 #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
bogdanm 82:6473597d706e 4702 #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
bogdanm 82:6473597d706e 4703 #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
bogdanm 82:6473597d706e 4704 #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
bogdanm 82:6473597d706e 4705 #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
bogdanm 82:6473597d706e 4706 #define ENET_ATCR_REG(base) ((base)->ATCR)
bogdanm 82:6473597d706e 4707 #define ENET_ATVR_REG(base) ((base)->ATVR)
bogdanm 82:6473597d706e 4708 #define ENET_ATOFF_REG(base) ((base)->ATOFF)
bogdanm 82:6473597d706e 4709 #define ENET_ATPER_REG(base) ((base)->ATPER)
bogdanm 82:6473597d706e 4710 #define ENET_ATCOR_REG(base) ((base)->ATCOR)
bogdanm 82:6473597d706e 4711 #define ENET_ATINC_REG(base) ((base)->ATINC)
bogdanm 82:6473597d706e 4712 #define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
bogdanm 82:6473597d706e 4713 #define ENET_TGSR_REG(base) ((base)->TGSR)
bogdanm 82:6473597d706e 4714 #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
bogdanm 82:6473597d706e 4715 #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
bogdanm 82:6473597d706e 4716
bogdanm 82:6473597d706e 4717 /*!
bogdanm 82:6473597d706e 4718 * @}
bogdanm 82:6473597d706e 4719 */ /* end of group ENET_Register_Accessor_Macros */
bogdanm 82:6473597d706e 4720
bogdanm 82:6473597d706e 4721
bogdanm 82:6473597d706e 4722 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 4723 -- ENET Register Masks
bogdanm 82:6473597d706e 4724 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 4725
bogdanm 82:6473597d706e 4726 /*!
bogdanm 82:6473597d706e 4727 * @addtogroup ENET_Register_Masks ENET Register Masks
bogdanm 82:6473597d706e 4728 * @{
bogdanm 82:6473597d706e 4729 */
bogdanm 82:6473597d706e 4730
bogdanm 82:6473597d706e 4731 /* EIR Bit Fields */
bogdanm 82:6473597d706e 4732 #define ENET_EIR_TS_TIMER_MASK 0x8000u
bogdanm 82:6473597d706e 4733 #define ENET_EIR_TS_TIMER_SHIFT 15
bogdanm 82:6473597d706e 4734 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
bogdanm 82:6473597d706e 4735 #define ENET_EIR_TS_AVAIL_SHIFT 16
bogdanm 82:6473597d706e 4736 #define ENET_EIR_WAKEUP_MASK 0x20000u
bogdanm 82:6473597d706e 4737 #define ENET_EIR_WAKEUP_SHIFT 17
bogdanm 82:6473597d706e 4738 #define ENET_EIR_PLR_MASK 0x40000u
bogdanm 82:6473597d706e 4739 #define ENET_EIR_PLR_SHIFT 18
bogdanm 82:6473597d706e 4740 #define ENET_EIR_UN_MASK 0x80000u
bogdanm 82:6473597d706e 4741 #define ENET_EIR_UN_SHIFT 19
bogdanm 82:6473597d706e 4742 #define ENET_EIR_RL_MASK 0x100000u
bogdanm 82:6473597d706e 4743 #define ENET_EIR_RL_SHIFT 20
bogdanm 82:6473597d706e 4744 #define ENET_EIR_LC_MASK 0x200000u
bogdanm 82:6473597d706e 4745 #define ENET_EIR_LC_SHIFT 21
bogdanm 82:6473597d706e 4746 #define ENET_EIR_EBERR_MASK 0x400000u
bogdanm 82:6473597d706e 4747 #define ENET_EIR_EBERR_SHIFT 22
bogdanm 82:6473597d706e 4748 #define ENET_EIR_MII_MASK 0x800000u
bogdanm 82:6473597d706e 4749 #define ENET_EIR_MII_SHIFT 23
bogdanm 82:6473597d706e 4750 #define ENET_EIR_RXB_MASK 0x1000000u
bogdanm 82:6473597d706e 4751 #define ENET_EIR_RXB_SHIFT 24
bogdanm 82:6473597d706e 4752 #define ENET_EIR_RXF_MASK 0x2000000u
bogdanm 82:6473597d706e 4753 #define ENET_EIR_RXF_SHIFT 25
bogdanm 82:6473597d706e 4754 #define ENET_EIR_TXB_MASK 0x4000000u
bogdanm 82:6473597d706e 4755 #define ENET_EIR_TXB_SHIFT 26
bogdanm 82:6473597d706e 4756 #define ENET_EIR_TXF_MASK 0x8000000u
bogdanm 82:6473597d706e 4757 #define ENET_EIR_TXF_SHIFT 27
bogdanm 82:6473597d706e 4758 #define ENET_EIR_GRA_MASK 0x10000000u
bogdanm 82:6473597d706e 4759 #define ENET_EIR_GRA_SHIFT 28
bogdanm 82:6473597d706e 4760 #define ENET_EIR_BABT_MASK 0x20000000u
bogdanm 82:6473597d706e 4761 #define ENET_EIR_BABT_SHIFT 29
bogdanm 82:6473597d706e 4762 #define ENET_EIR_BABR_MASK 0x40000000u
bogdanm 82:6473597d706e 4763 #define ENET_EIR_BABR_SHIFT 30
bogdanm 82:6473597d706e 4764 /* EIMR Bit Fields */
bogdanm 82:6473597d706e 4765 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
bogdanm 82:6473597d706e 4766 #define ENET_EIMR_TS_TIMER_SHIFT 15
bogdanm 82:6473597d706e 4767 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
bogdanm 82:6473597d706e 4768 #define ENET_EIMR_TS_AVAIL_SHIFT 16
bogdanm 82:6473597d706e 4769 #define ENET_EIMR_WAKEUP_MASK 0x20000u
bogdanm 82:6473597d706e 4770 #define ENET_EIMR_WAKEUP_SHIFT 17
bogdanm 82:6473597d706e 4771 #define ENET_EIMR_PLR_MASK 0x40000u
bogdanm 82:6473597d706e 4772 #define ENET_EIMR_PLR_SHIFT 18
bogdanm 82:6473597d706e 4773 #define ENET_EIMR_UN_MASK 0x80000u
bogdanm 82:6473597d706e 4774 #define ENET_EIMR_UN_SHIFT 19
bogdanm 82:6473597d706e 4775 #define ENET_EIMR_RL_MASK 0x100000u
bogdanm 82:6473597d706e 4776 #define ENET_EIMR_RL_SHIFT 20
bogdanm 82:6473597d706e 4777 #define ENET_EIMR_LC_MASK 0x200000u
bogdanm 82:6473597d706e 4778 #define ENET_EIMR_LC_SHIFT 21
bogdanm 82:6473597d706e 4779 #define ENET_EIMR_EBERR_MASK 0x400000u
bogdanm 82:6473597d706e 4780 #define ENET_EIMR_EBERR_SHIFT 22
bogdanm 82:6473597d706e 4781 #define ENET_EIMR_MII_MASK 0x800000u
bogdanm 82:6473597d706e 4782 #define ENET_EIMR_MII_SHIFT 23
bogdanm 82:6473597d706e 4783 #define ENET_EIMR_RXB_MASK 0x1000000u
bogdanm 82:6473597d706e 4784 #define ENET_EIMR_RXB_SHIFT 24
bogdanm 82:6473597d706e 4785 #define ENET_EIMR_RXF_MASK 0x2000000u
bogdanm 82:6473597d706e 4786 #define ENET_EIMR_RXF_SHIFT 25
bogdanm 82:6473597d706e 4787 #define ENET_EIMR_TXB_MASK 0x4000000u
bogdanm 82:6473597d706e 4788 #define ENET_EIMR_TXB_SHIFT 26
bogdanm 82:6473597d706e 4789 #define ENET_EIMR_TXF_MASK 0x8000000u
bogdanm 82:6473597d706e 4790 #define ENET_EIMR_TXF_SHIFT 27
bogdanm 82:6473597d706e 4791 #define ENET_EIMR_GRA_MASK 0x10000000u
bogdanm 82:6473597d706e 4792 #define ENET_EIMR_GRA_SHIFT 28
bogdanm 82:6473597d706e 4793 #define ENET_EIMR_BABT_MASK 0x20000000u
bogdanm 82:6473597d706e 4794 #define ENET_EIMR_BABT_SHIFT 29
bogdanm 82:6473597d706e 4795 #define ENET_EIMR_BABR_MASK 0x40000000u
bogdanm 82:6473597d706e 4796 #define ENET_EIMR_BABR_SHIFT 30
bogdanm 82:6473597d706e 4797 /* RDAR Bit Fields */
bogdanm 82:6473597d706e 4798 #define ENET_RDAR_RDAR_MASK 0x1000000u
bogdanm 82:6473597d706e 4799 #define ENET_RDAR_RDAR_SHIFT 24
bogdanm 82:6473597d706e 4800 /* TDAR Bit Fields */
bogdanm 82:6473597d706e 4801 #define ENET_TDAR_TDAR_MASK 0x1000000u
bogdanm 82:6473597d706e 4802 #define ENET_TDAR_TDAR_SHIFT 24
bogdanm 82:6473597d706e 4803 /* ECR Bit Fields */
bogdanm 82:6473597d706e 4804 #define ENET_ECR_RESET_MASK 0x1u
bogdanm 82:6473597d706e 4805 #define ENET_ECR_RESET_SHIFT 0
bogdanm 82:6473597d706e 4806 #define ENET_ECR_ETHEREN_MASK 0x2u
bogdanm 82:6473597d706e 4807 #define ENET_ECR_ETHEREN_SHIFT 1
bogdanm 82:6473597d706e 4808 #define ENET_ECR_MAGICEN_MASK 0x4u
bogdanm 82:6473597d706e 4809 #define ENET_ECR_MAGICEN_SHIFT 2
bogdanm 82:6473597d706e 4810 #define ENET_ECR_SLEEP_MASK 0x8u
bogdanm 82:6473597d706e 4811 #define ENET_ECR_SLEEP_SHIFT 3
bogdanm 82:6473597d706e 4812 #define ENET_ECR_EN1588_MASK 0x10u
bogdanm 82:6473597d706e 4813 #define ENET_ECR_EN1588_SHIFT 4
bogdanm 82:6473597d706e 4814 #define ENET_ECR_DBGEN_MASK 0x40u
bogdanm 82:6473597d706e 4815 #define ENET_ECR_DBGEN_SHIFT 6
bogdanm 82:6473597d706e 4816 #define ENET_ECR_STOPEN_MASK 0x80u
bogdanm 82:6473597d706e 4817 #define ENET_ECR_STOPEN_SHIFT 7
bogdanm 82:6473597d706e 4818 #define ENET_ECR_DBSWP_MASK 0x100u
bogdanm 82:6473597d706e 4819 #define ENET_ECR_DBSWP_SHIFT 8
bogdanm 82:6473597d706e 4820 /* MMFR Bit Fields */
bogdanm 82:6473597d706e 4821 #define ENET_MMFR_DATA_MASK 0xFFFFu
bogdanm 82:6473597d706e 4822 #define ENET_MMFR_DATA_SHIFT 0
bogdanm 82:6473597d706e 4823 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
bogdanm 82:6473597d706e 4824 #define ENET_MMFR_TA_MASK 0x30000u
bogdanm 82:6473597d706e 4825 #define ENET_MMFR_TA_SHIFT 16
bogdanm 82:6473597d706e 4826 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
bogdanm 82:6473597d706e 4827 #define ENET_MMFR_RA_MASK 0x7C0000u
bogdanm 82:6473597d706e 4828 #define ENET_MMFR_RA_SHIFT 18
bogdanm 82:6473597d706e 4829 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
bogdanm 82:6473597d706e 4830 #define ENET_MMFR_PA_MASK 0xF800000u
bogdanm 82:6473597d706e 4831 #define ENET_MMFR_PA_SHIFT 23
bogdanm 82:6473597d706e 4832 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
bogdanm 82:6473597d706e 4833 #define ENET_MMFR_OP_MASK 0x30000000u
bogdanm 82:6473597d706e 4834 #define ENET_MMFR_OP_SHIFT 28
bogdanm 82:6473597d706e 4835 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
bogdanm 82:6473597d706e 4836 #define ENET_MMFR_ST_MASK 0xC0000000u
bogdanm 82:6473597d706e 4837 #define ENET_MMFR_ST_SHIFT 30
bogdanm 82:6473597d706e 4838 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
bogdanm 82:6473597d706e 4839 /* MSCR Bit Fields */
bogdanm 82:6473597d706e 4840 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
bogdanm 82:6473597d706e 4841 #define ENET_MSCR_MII_SPEED_SHIFT 1
bogdanm 82:6473597d706e 4842 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
bogdanm 82:6473597d706e 4843 #define ENET_MSCR_DIS_PRE_MASK 0x80u
bogdanm 82:6473597d706e 4844 #define ENET_MSCR_DIS_PRE_SHIFT 7
bogdanm 82:6473597d706e 4845 #define ENET_MSCR_HOLDTIME_MASK 0x700u
bogdanm 82:6473597d706e 4846 #define ENET_MSCR_HOLDTIME_SHIFT 8
bogdanm 82:6473597d706e 4847 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
bogdanm 82:6473597d706e 4848 /* MIBC Bit Fields */
bogdanm 82:6473597d706e 4849 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
bogdanm 82:6473597d706e 4850 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
bogdanm 82:6473597d706e 4851 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
bogdanm 82:6473597d706e 4852 #define ENET_MIBC_MIB_IDLE_SHIFT 30
bogdanm 82:6473597d706e 4853 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
bogdanm 82:6473597d706e 4854 #define ENET_MIBC_MIB_DIS_SHIFT 31
bogdanm 82:6473597d706e 4855 /* RCR Bit Fields */
bogdanm 82:6473597d706e 4856 #define ENET_RCR_LOOP_MASK 0x1u
bogdanm 82:6473597d706e 4857 #define ENET_RCR_LOOP_SHIFT 0
bogdanm 82:6473597d706e 4858 #define ENET_RCR_DRT_MASK 0x2u
bogdanm 82:6473597d706e 4859 #define ENET_RCR_DRT_SHIFT 1
bogdanm 82:6473597d706e 4860 #define ENET_RCR_MII_MODE_MASK 0x4u
bogdanm 82:6473597d706e 4861 #define ENET_RCR_MII_MODE_SHIFT 2
bogdanm 82:6473597d706e 4862 #define ENET_RCR_PROM_MASK 0x8u
bogdanm 82:6473597d706e 4863 #define ENET_RCR_PROM_SHIFT 3
bogdanm 82:6473597d706e 4864 #define ENET_RCR_BC_REJ_MASK 0x10u
bogdanm 82:6473597d706e 4865 #define ENET_RCR_BC_REJ_SHIFT 4
bogdanm 82:6473597d706e 4866 #define ENET_RCR_FCE_MASK 0x20u
bogdanm 82:6473597d706e 4867 #define ENET_RCR_FCE_SHIFT 5
bogdanm 82:6473597d706e 4868 #define ENET_RCR_RMII_MODE_MASK 0x100u
bogdanm 82:6473597d706e 4869 #define ENET_RCR_RMII_MODE_SHIFT 8
bogdanm 82:6473597d706e 4870 #define ENET_RCR_RMII_10T_MASK 0x200u
bogdanm 82:6473597d706e 4871 #define ENET_RCR_RMII_10T_SHIFT 9
bogdanm 82:6473597d706e 4872 #define ENET_RCR_PADEN_MASK 0x1000u
bogdanm 82:6473597d706e 4873 #define ENET_RCR_PADEN_SHIFT 12
bogdanm 82:6473597d706e 4874 #define ENET_RCR_PAUFWD_MASK 0x2000u
bogdanm 82:6473597d706e 4875 #define ENET_RCR_PAUFWD_SHIFT 13
bogdanm 82:6473597d706e 4876 #define ENET_RCR_CRCFWD_MASK 0x4000u
bogdanm 82:6473597d706e 4877 #define ENET_RCR_CRCFWD_SHIFT 14
bogdanm 82:6473597d706e 4878 #define ENET_RCR_CFEN_MASK 0x8000u
bogdanm 82:6473597d706e 4879 #define ENET_RCR_CFEN_SHIFT 15
bogdanm 82:6473597d706e 4880 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
bogdanm 82:6473597d706e 4881 #define ENET_RCR_MAX_FL_SHIFT 16
bogdanm 82:6473597d706e 4882 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
bogdanm 82:6473597d706e 4883 #define ENET_RCR_NLC_MASK 0x40000000u
bogdanm 82:6473597d706e 4884 #define ENET_RCR_NLC_SHIFT 30
bogdanm 82:6473597d706e 4885 #define ENET_RCR_GRS_MASK 0x80000000u
bogdanm 82:6473597d706e 4886 #define ENET_RCR_GRS_SHIFT 31
bogdanm 82:6473597d706e 4887 /* TCR Bit Fields */
bogdanm 82:6473597d706e 4888 #define ENET_TCR_GTS_MASK 0x1u
bogdanm 82:6473597d706e 4889 #define ENET_TCR_GTS_SHIFT 0
bogdanm 82:6473597d706e 4890 #define ENET_TCR_FDEN_MASK 0x4u
bogdanm 82:6473597d706e 4891 #define ENET_TCR_FDEN_SHIFT 2
bogdanm 82:6473597d706e 4892 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
bogdanm 82:6473597d706e 4893 #define ENET_TCR_TFC_PAUSE_SHIFT 3
bogdanm 82:6473597d706e 4894 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
bogdanm 82:6473597d706e 4895 #define ENET_TCR_RFC_PAUSE_SHIFT 4
bogdanm 82:6473597d706e 4896 #define ENET_TCR_ADDSEL_MASK 0xE0u
bogdanm 82:6473597d706e 4897 #define ENET_TCR_ADDSEL_SHIFT 5
bogdanm 82:6473597d706e 4898 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
bogdanm 82:6473597d706e 4899 #define ENET_TCR_ADDINS_MASK 0x100u
bogdanm 82:6473597d706e 4900 #define ENET_TCR_ADDINS_SHIFT 8
bogdanm 82:6473597d706e 4901 #define ENET_TCR_CRCFWD_MASK 0x200u
bogdanm 82:6473597d706e 4902 #define ENET_TCR_CRCFWD_SHIFT 9
bogdanm 82:6473597d706e 4903 /* PALR Bit Fields */
bogdanm 82:6473597d706e 4904 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 4905 #define ENET_PALR_PADDR1_SHIFT 0
bogdanm 82:6473597d706e 4906 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
bogdanm 82:6473597d706e 4907 /* PAUR Bit Fields */
bogdanm 82:6473597d706e 4908 #define ENET_PAUR_TYPE_MASK 0xFFFFu
bogdanm 82:6473597d706e 4909 #define ENET_PAUR_TYPE_SHIFT 0
bogdanm 82:6473597d706e 4910 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
bogdanm 82:6473597d706e 4911 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 4912 #define ENET_PAUR_PADDR2_SHIFT 16
bogdanm 82:6473597d706e 4913 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
bogdanm 82:6473597d706e 4914 /* OPD Bit Fields */
bogdanm 82:6473597d706e 4915 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
bogdanm 82:6473597d706e 4916 #define ENET_OPD_PAUSE_DUR_SHIFT 0
bogdanm 82:6473597d706e 4917 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
bogdanm 82:6473597d706e 4918 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 4919 #define ENET_OPD_OPCODE_SHIFT 16
bogdanm 82:6473597d706e 4920 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
bogdanm 82:6473597d706e 4921 /* IAUR Bit Fields */
bogdanm 82:6473597d706e 4922 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 4923 #define ENET_IAUR_IADDR1_SHIFT 0
bogdanm 82:6473597d706e 4924 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
bogdanm 82:6473597d706e 4925 /* IALR Bit Fields */
bogdanm 82:6473597d706e 4926 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 4927 #define ENET_IALR_IADDR2_SHIFT 0
bogdanm 82:6473597d706e 4928 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
bogdanm 82:6473597d706e 4929 /* GAUR Bit Fields */
bogdanm 82:6473597d706e 4930 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 4931 #define ENET_GAUR_GADDR1_SHIFT 0
bogdanm 82:6473597d706e 4932 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
bogdanm 82:6473597d706e 4933 /* GALR Bit Fields */
bogdanm 82:6473597d706e 4934 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 4935 #define ENET_GALR_GADDR2_SHIFT 0
bogdanm 82:6473597d706e 4936 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
bogdanm 82:6473597d706e 4937 /* TFWR Bit Fields */
bogdanm 82:6473597d706e 4938 #define ENET_TFWR_TFWR_MASK 0x3Fu
bogdanm 82:6473597d706e 4939 #define ENET_TFWR_TFWR_SHIFT 0
bogdanm 82:6473597d706e 4940 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
bogdanm 82:6473597d706e 4941 #define ENET_TFWR_STRFWD_MASK 0x100u
bogdanm 82:6473597d706e 4942 #define ENET_TFWR_STRFWD_SHIFT 8
bogdanm 82:6473597d706e 4943 /* RDSR Bit Fields */
bogdanm 82:6473597d706e 4944 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
bogdanm 82:6473597d706e 4945 #define ENET_RDSR_R_DES_START_SHIFT 3
bogdanm 82:6473597d706e 4946 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
bogdanm 82:6473597d706e 4947 /* TDSR Bit Fields */
bogdanm 82:6473597d706e 4948 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
bogdanm 82:6473597d706e 4949 #define ENET_TDSR_X_DES_START_SHIFT 3
bogdanm 82:6473597d706e 4950 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
bogdanm 82:6473597d706e 4951 /* MRBR Bit Fields */
bogdanm 82:6473597d706e 4952 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
bogdanm 82:6473597d706e 4953 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
bogdanm 82:6473597d706e 4954 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
bogdanm 82:6473597d706e 4955 /* RSFL Bit Fields */
bogdanm 82:6473597d706e 4956 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
bogdanm 82:6473597d706e 4957 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
bogdanm 82:6473597d706e 4958 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
bogdanm 82:6473597d706e 4959 /* RSEM Bit Fields */
bogdanm 82:6473597d706e 4960 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
bogdanm 82:6473597d706e 4961 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
bogdanm 82:6473597d706e 4962 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
bogdanm 82:6473597d706e 4963 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
bogdanm 82:6473597d706e 4964 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
bogdanm 82:6473597d706e 4965 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
bogdanm 82:6473597d706e 4966 /* RAEM Bit Fields */
bogdanm 82:6473597d706e 4967 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
bogdanm 82:6473597d706e 4968 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
bogdanm 82:6473597d706e 4969 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
bogdanm 82:6473597d706e 4970 /* RAFL Bit Fields */
bogdanm 82:6473597d706e 4971 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
bogdanm 82:6473597d706e 4972 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
bogdanm 82:6473597d706e 4973 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
bogdanm 82:6473597d706e 4974 /* TSEM Bit Fields */
bogdanm 82:6473597d706e 4975 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
bogdanm 82:6473597d706e 4976 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
bogdanm 82:6473597d706e 4977 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
bogdanm 82:6473597d706e 4978 /* TAEM Bit Fields */
bogdanm 82:6473597d706e 4979 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
bogdanm 82:6473597d706e 4980 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
bogdanm 82:6473597d706e 4981 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
bogdanm 82:6473597d706e 4982 /* TAFL Bit Fields */
bogdanm 82:6473597d706e 4983 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
bogdanm 82:6473597d706e 4984 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
bogdanm 82:6473597d706e 4985 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
bogdanm 82:6473597d706e 4986 /* TIPG Bit Fields */
bogdanm 82:6473597d706e 4987 #define ENET_TIPG_IPG_MASK 0x1Fu
bogdanm 82:6473597d706e 4988 #define ENET_TIPG_IPG_SHIFT 0
bogdanm 82:6473597d706e 4989 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
bogdanm 82:6473597d706e 4990 /* FTRL Bit Fields */
bogdanm 82:6473597d706e 4991 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
bogdanm 82:6473597d706e 4992 #define ENET_FTRL_TRUNC_FL_SHIFT 0
bogdanm 82:6473597d706e 4993 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
bogdanm 82:6473597d706e 4994 /* TACC Bit Fields */
bogdanm 82:6473597d706e 4995 #define ENET_TACC_SHIFT16_MASK 0x1u
bogdanm 82:6473597d706e 4996 #define ENET_TACC_SHIFT16_SHIFT 0
bogdanm 82:6473597d706e 4997 #define ENET_TACC_IPCHK_MASK 0x8u
bogdanm 82:6473597d706e 4998 #define ENET_TACC_IPCHK_SHIFT 3
bogdanm 82:6473597d706e 4999 #define ENET_TACC_PROCHK_MASK 0x10u
bogdanm 82:6473597d706e 5000 #define ENET_TACC_PROCHK_SHIFT 4
bogdanm 82:6473597d706e 5001 /* RACC Bit Fields */
bogdanm 82:6473597d706e 5002 #define ENET_RACC_PADREM_MASK 0x1u
bogdanm 82:6473597d706e 5003 #define ENET_RACC_PADREM_SHIFT 0
bogdanm 82:6473597d706e 5004 #define ENET_RACC_IPDIS_MASK 0x2u
bogdanm 82:6473597d706e 5005 #define ENET_RACC_IPDIS_SHIFT 1
bogdanm 82:6473597d706e 5006 #define ENET_RACC_PRODIS_MASK 0x4u
bogdanm 82:6473597d706e 5007 #define ENET_RACC_PRODIS_SHIFT 2
bogdanm 82:6473597d706e 5008 #define ENET_RACC_LINEDIS_MASK 0x40u
bogdanm 82:6473597d706e 5009 #define ENET_RACC_LINEDIS_SHIFT 6
bogdanm 82:6473597d706e 5010 #define ENET_RACC_SHIFT16_MASK 0x80u
bogdanm 82:6473597d706e 5011 #define ENET_RACC_SHIFT16_SHIFT 7
bogdanm 82:6473597d706e 5012 /* ATCR Bit Fields */
bogdanm 82:6473597d706e 5013 #define ENET_ATCR_EN_MASK 0x1u
bogdanm 82:6473597d706e 5014 #define ENET_ATCR_EN_SHIFT 0
bogdanm 82:6473597d706e 5015 #define ENET_ATCR_OFFEN_MASK 0x4u
bogdanm 82:6473597d706e 5016 #define ENET_ATCR_OFFEN_SHIFT 2
bogdanm 82:6473597d706e 5017 #define ENET_ATCR_OFFRST_MASK 0x8u
bogdanm 82:6473597d706e 5018 #define ENET_ATCR_OFFRST_SHIFT 3
bogdanm 82:6473597d706e 5019 #define ENET_ATCR_PEREN_MASK 0x10u
bogdanm 82:6473597d706e 5020 #define ENET_ATCR_PEREN_SHIFT 4
bogdanm 82:6473597d706e 5021 #define ENET_ATCR_PINPER_MASK 0x80u
bogdanm 82:6473597d706e 5022 #define ENET_ATCR_PINPER_SHIFT 7
bogdanm 82:6473597d706e 5023 #define ENET_ATCR_RESTART_MASK 0x200u
bogdanm 82:6473597d706e 5024 #define ENET_ATCR_RESTART_SHIFT 9
bogdanm 82:6473597d706e 5025 #define ENET_ATCR_CAPTURE_MASK 0x800u
bogdanm 82:6473597d706e 5026 #define ENET_ATCR_CAPTURE_SHIFT 11
bogdanm 82:6473597d706e 5027 #define ENET_ATCR_SLAVE_MASK 0x2000u
bogdanm 82:6473597d706e 5028 #define ENET_ATCR_SLAVE_SHIFT 13
bogdanm 82:6473597d706e 5029 /* ATVR Bit Fields */
bogdanm 82:6473597d706e 5030 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 5031 #define ENET_ATVR_ATIME_SHIFT 0
bogdanm 82:6473597d706e 5032 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
bogdanm 82:6473597d706e 5033 /* ATOFF Bit Fields */
bogdanm 82:6473597d706e 5034 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 5035 #define ENET_ATOFF_OFFSET_SHIFT 0
bogdanm 82:6473597d706e 5036 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
bogdanm 82:6473597d706e 5037 /* ATPER Bit Fields */
bogdanm 82:6473597d706e 5038 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 5039 #define ENET_ATPER_PERIOD_SHIFT 0
bogdanm 82:6473597d706e 5040 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
bogdanm 82:6473597d706e 5041 /* ATCOR Bit Fields */
bogdanm 82:6473597d706e 5042 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
bogdanm 82:6473597d706e 5043 #define ENET_ATCOR_COR_SHIFT 0
bogdanm 82:6473597d706e 5044 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
bogdanm 82:6473597d706e 5045 /* ATINC Bit Fields */
bogdanm 82:6473597d706e 5046 #define ENET_ATINC_INC_MASK 0x7Fu
bogdanm 82:6473597d706e 5047 #define ENET_ATINC_INC_SHIFT 0
bogdanm 82:6473597d706e 5048 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
bogdanm 82:6473597d706e 5049 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
bogdanm 82:6473597d706e 5050 #define ENET_ATINC_INC_CORR_SHIFT 8
bogdanm 82:6473597d706e 5051 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
bogdanm 82:6473597d706e 5052 /* ATSTMP Bit Fields */
bogdanm 82:6473597d706e 5053 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 5054 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
bogdanm 82:6473597d706e 5055 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
bogdanm 82:6473597d706e 5056 /* TGSR Bit Fields */
bogdanm 82:6473597d706e 5057 #define ENET_TGSR_TF0_MASK 0x1u
bogdanm 82:6473597d706e 5058 #define ENET_TGSR_TF0_SHIFT 0
bogdanm 82:6473597d706e 5059 #define ENET_TGSR_TF1_MASK 0x2u
bogdanm 82:6473597d706e 5060 #define ENET_TGSR_TF1_SHIFT 1
bogdanm 82:6473597d706e 5061 #define ENET_TGSR_TF2_MASK 0x4u
bogdanm 82:6473597d706e 5062 #define ENET_TGSR_TF2_SHIFT 2
bogdanm 82:6473597d706e 5063 #define ENET_TGSR_TF3_MASK 0x8u
bogdanm 82:6473597d706e 5064 #define ENET_TGSR_TF3_SHIFT 3
bogdanm 82:6473597d706e 5065 /* TCSR Bit Fields */
bogdanm 82:6473597d706e 5066 #define ENET_TCSR_TDRE_MASK 0x1u
bogdanm 82:6473597d706e 5067 #define ENET_TCSR_TDRE_SHIFT 0
bogdanm 82:6473597d706e 5068 #define ENET_TCSR_TMODE_MASK 0x3Cu
bogdanm 82:6473597d706e 5069 #define ENET_TCSR_TMODE_SHIFT 2
bogdanm 82:6473597d706e 5070 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
bogdanm 82:6473597d706e 5071 #define ENET_TCSR_TIE_MASK 0x40u
bogdanm 82:6473597d706e 5072 #define ENET_TCSR_TIE_SHIFT 6
bogdanm 82:6473597d706e 5073 #define ENET_TCSR_TF_MASK 0x80u
bogdanm 82:6473597d706e 5074 #define ENET_TCSR_TF_SHIFT 7
bogdanm 82:6473597d706e 5075 /* TCCR Bit Fields */
bogdanm 82:6473597d706e 5076 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 5077 #define ENET_TCCR_TCC_SHIFT 0
bogdanm 82:6473597d706e 5078 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
bogdanm 82:6473597d706e 5079
bogdanm 82:6473597d706e 5080 /*!
bogdanm 82:6473597d706e 5081 * @}
bogdanm 82:6473597d706e 5082 */ /* end of group ENET_Register_Masks */
bogdanm 82:6473597d706e 5083
bogdanm 82:6473597d706e 5084
bogdanm 82:6473597d706e 5085 /* ENET - Peripheral instance base addresses */
bogdanm 82:6473597d706e 5086 /** Peripheral ENET base address */
bogdanm 82:6473597d706e 5087 #define ENET_BASE (0x400C0000u)
bogdanm 82:6473597d706e 5088 /** Peripheral ENET base pointer */
bogdanm 82:6473597d706e 5089 #define ENET ((ENET_Type *)ENET_BASE)
bogdanm 82:6473597d706e 5090 #define ENET_BASE_PTR (ENET)
bogdanm 82:6473597d706e 5091 /** Array initializer of ENET peripheral base pointers */
bogdanm 82:6473597d706e 5092 #define ENET_BASES { ENET }
bogdanm 82:6473597d706e 5093
bogdanm 82:6473597d706e 5094 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5095 -- ENET - Register accessor macros
bogdanm 82:6473597d706e 5096 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5097
bogdanm 82:6473597d706e 5098 /*!
bogdanm 82:6473597d706e 5099 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
bogdanm 82:6473597d706e 5100 * @{
bogdanm 82:6473597d706e 5101 */
bogdanm 82:6473597d706e 5102
bogdanm 82:6473597d706e 5103
bogdanm 82:6473597d706e 5104 /* ENET - Register instance definitions */
bogdanm 82:6473597d706e 5105 /* ENET */
bogdanm 82:6473597d706e 5106 #define ENET_EIR ENET_EIR_REG(ENET)
bogdanm 82:6473597d706e 5107 #define ENET_EIMR ENET_EIMR_REG(ENET)
bogdanm 82:6473597d706e 5108 #define ENET_RDAR ENET_RDAR_REG(ENET)
bogdanm 82:6473597d706e 5109 #define ENET_TDAR ENET_TDAR_REG(ENET)
bogdanm 82:6473597d706e 5110 #define ENET_ECR ENET_ECR_REG(ENET)
bogdanm 82:6473597d706e 5111 #define ENET_MMFR ENET_MMFR_REG(ENET)
bogdanm 82:6473597d706e 5112 #define ENET_MSCR ENET_MSCR_REG(ENET)
bogdanm 82:6473597d706e 5113 #define ENET_MIBC ENET_MIBC_REG(ENET)
bogdanm 82:6473597d706e 5114 #define ENET_RCR ENET_RCR_REG(ENET)
bogdanm 82:6473597d706e 5115 #define ENET_TCR ENET_TCR_REG(ENET)
bogdanm 82:6473597d706e 5116 #define ENET_PALR ENET_PALR_REG(ENET)
bogdanm 82:6473597d706e 5117 #define ENET_PAUR ENET_PAUR_REG(ENET)
bogdanm 82:6473597d706e 5118 #define ENET_OPD ENET_OPD_REG(ENET)
bogdanm 82:6473597d706e 5119 #define ENET_IAUR ENET_IAUR_REG(ENET)
bogdanm 82:6473597d706e 5120 #define ENET_IALR ENET_IALR_REG(ENET)
bogdanm 82:6473597d706e 5121 #define ENET_GAUR ENET_GAUR_REG(ENET)
bogdanm 82:6473597d706e 5122 #define ENET_GALR ENET_GALR_REG(ENET)
bogdanm 82:6473597d706e 5123 #define ENET_TFWR ENET_TFWR_REG(ENET)
bogdanm 82:6473597d706e 5124 #define ENET_RDSR ENET_RDSR_REG(ENET)
bogdanm 82:6473597d706e 5125 #define ENET_TDSR ENET_TDSR_REG(ENET)
bogdanm 82:6473597d706e 5126 #define ENET_MRBR ENET_MRBR_REG(ENET)
bogdanm 82:6473597d706e 5127 #define ENET_RSFL ENET_RSFL_REG(ENET)
bogdanm 82:6473597d706e 5128 #define ENET_RSEM ENET_RSEM_REG(ENET)
bogdanm 82:6473597d706e 5129 #define ENET_RAEM ENET_RAEM_REG(ENET)
bogdanm 82:6473597d706e 5130 #define ENET_RAFL ENET_RAFL_REG(ENET)
bogdanm 82:6473597d706e 5131 #define ENET_TSEM ENET_TSEM_REG(ENET)
bogdanm 82:6473597d706e 5132 #define ENET_TAEM ENET_TAEM_REG(ENET)
bogdanm 82:6473597d706e 5133 #define ENET_TAFL ENET_TAFL_REG(ENET)
bogdanm 82:6473597d706e 5134 #define ENET_TIPG ENET_TIPG_REG(ENET)
bogdanm 82:6473597d706e 5135 #define ENET_FTRL ENET_FTRL_REG(ENET)
bogdanm 82:6473597d706e 5136 #define ENET_TACC ENET_TACC_REG(ENET)
bogdanm 82:6473597d706e 5137 #define ENET_RACC ENET_RACC_REG(ENET)
bogdanm 82:6473597d706e 5138 #define ENET_RMON_T_DROP ENET_RMON_T_DROP_REG(ENET)
bogdanm 82:6473597d706e 5139 #define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
bogdanm 82:6473597d706e 5140 #define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
bogdanm 82:6473597d706e 5141 #define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
bogdanm 82:6473597d706e 5142 #define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
bogdanm 82:6473597d706e 5143 #define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
bogdanm 82:6473597d706e 5144 #define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
bogdanm 82:6473597d706e 5145 #define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
bogdanm 82:6473597d706e 5146 #define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
bogdanm 82:6473597d706e 5147 #define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
bogdanm 82:6473597d706e 5148 #define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
bogdanm 82:6473597d706e 5149 #define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
bogdanm 82:6473597d706e 5150 #define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
bogdanm 82:6473597d706e 5151 #define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
bogdanm 82:6473597d706e 5152 #define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
bogdanm 82:6473597d706e 5153 #define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
bogdanm 82:6473597d706e 5154 #define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
bogdanm 82:6473597d706e 5155 #define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
bogdanm 82:6473597d706e 5156 #define ENET_IEEE_T_DROP ENET_IEEE_T_DROP_REG(ENET)
bogdanm 82:6473597d706e 5157 #define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
bogdanm 82:6473597d706e 5158 #define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
bogdanm 82:6473597d706e 5159 #define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
bogdanm 82:6473597d706e 5160 #define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
bogdanm 82:6473597d706e 5161 #define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
bogdanm 82:6473597d706e 5162 #define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
bogdanm 82:6473597d706e 5163 #define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
bogdanm 82:6473597d706e 5164 #define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
bogdanm 82:6473597d706e 5165 #define ENET_IEEE_T_SQE ENET_IEEE_T_SQE_REG(ENET)
bogdanm 82:6473597d706e 5166 #define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
bogdanm 82:6473597d706e 5167 #define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
bogdanm 82:6473597d706e 5168 #define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
bogdanm 82:6473597d706e 5169 #define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
bogdanm 82:6473597d706e 5170 #define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
bogdanm 82:6473597d706e 5171 #define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
bogdanm 82:6473597d706e 5172 #define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
bogdanm 82:6473597d706e 5173 #define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
bogdanm 82:6473597d706e 5174 #define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
bogdanm 82:6473597d706e 5175 #define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
bogdanm 82:6473597d706e 5176 #define ENET_RMON_R_RESVD_0 ENET_RMON_R_RESVD_0_REG(ENET)
bogdanm 82:6473597d706e 5177 #define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
bogdanm 82:6473597d706e 5178 #define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
bogdanm 82:6473597d706e 5179 #define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
bogdanm 82:6473597d706e 5180 #define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
bogdanm 82:6473597d706e 5181 #define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
bogdanm 82:6473597d706e 5182 #define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
bogdanm 82:6473597d706e 5183 #define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET)
bogdanm 82:6473597d706e 5184 #define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
bogdanm 82:6473597d706e 5185 #define ENET_IEEE_R_DROP ENET_RMON_R_DROP_REG(ENET)
bogdanm 82:6473597d706e 5186 #define ENET_IEEE_R_FRAME_OK ENET_RMON_R_FRAME_OK_REG(ENET)
bogdanm 82:6473597d706e 5187 #define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
bogdanm 82:6473597d706e 5188 #define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
bogdanm 82:6473597d706e 5189 #define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
bogdanm 82:6473597d706e 5190 #define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
bogdanm 82:6473597d706e 5191 #define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
bogdanm 82:6473597d706e 5192 #define ENET_ATCR ENET_ATCR_REG(ENET)
bogdanm 82:6473597d706e 5193 #define ENET_ATVR ENET_ATVR_REG(ENET)
bogdanm 82:6473597d706e 5194 #define ENET_ATOFF ENET_ATOFF_REG(ENET)
bogdanm 82:6473597d706e 5195 #define ENET_ATPER ENET_ATPER_REG(ENET)
bogdanm 82:6473597d706e 5196 #define ENET_ATCOR ENET_ATCOR_REG(ENET)
bogdanm 82:6473597d706e 5197 #define ENET_ATINC ENET_ATINC_REG(ENET)
bogdanm 82:6473597d706e 5198 #define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
bogdanm 82:6473597d706e 5199 #define ENET_TGSR ENET_TGSR_REG(ENET)
bogdanm 82:6473597d706e 5200 #define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
bogdanm 82:6473597d706e 5201 #define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
bogdanm 82:6473597d706e 5202 #define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
bogdanm 82:6473597d706e 5203 #define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
bogdanm 82:6473597d706e 5204 #define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
bogdanm 82:6473597d706e 5205 #define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
bogdanm 82:6473597d706e 5206 #define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
bogdanm 82:6473597d706e 5207 #define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
bogdanm 82:6473597d706e 5208
bogdanm 82:6473597d706e 5209 /* ENET - Register array accessors */
bogdanm 82:6473597d706e 5210 #define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
bogdanm 82:6473597d706e 5211 #define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
bogdanm 82:6473597d706e 5212
bogdanm 82:6473597d706e 5213 /*!
bogdanm 82:6473597d706e 5214 * @}
bogdanm 82:6473597d706e 5215 */ /* end of group ENET_Register_Accessor_Macros */
bogdanm 82:6473597d706e 5216
bogdanm 82:6473597d706e 5217
bogdanm 82:6473597d706e 5218 /*!
bogdanm 82:6473597d706e 5219 * @}
bogdanm 82:6473597d706e 5220 */ /* end of group ENET_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 5221
bogdanm 82:6473597d706e 5222
bogdanm 82:6473597d706e 5223 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5224 -- EWM Peripheral Access Layer
bogdanm 82:6473597d706e 5225 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5226
bogdanm 82:6473597d706e 5227 /*!
bogdanm 82:6473597d706e 5228 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
bogdanm 82:6473597d706e 5229 * @{
bogdanm 82:6473597d706e 5230 */
bogdanm 82:6473597d706e 5231
bogdanm 82:6473597d706e 5232 /** EWM - Register Layout Typedef */
bogdanm 82:6473597d706e 5233 typedef struct {
bogdanm 82:6473597d706e 5234 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
bogdanm 82:6473597d706e 5235 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
bogdanm 82:6473597d706e 5236 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
bogdanm 82:6473597d706e 5237 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
bogdanm 82:6473597d706e 5238 } EWM_Type, *EWM_MemMapPtr;
bogdanm 82:6473597d706e 5239
bogdanm 82:6473597d706e 5240 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5241 -- EWM - Register accessor macros
bogdanm 82:6473597d706e 5242 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5243
bogdanm 82:6473597d706e 5244 /*!
bogdanm 82:6473597d706e 5245 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
bogdanm 82:6473597d706e 5246 * @{
bogdanm 82:6473597d706e 5247 */
bogdanm 82:6473597d706e 5248
bogdanm 82:6473597d706e 5249
bogdanm 82:6473597d706e 5250 /* EWM - Register accessors */
bogdanm 82:6473597d706e 5251 #define EWM_CTRL_REG(base) ((base)->CTRL)
bogdanm 82:6473597d706e 5252 #define EWM_SERV_REG(base) ((base)->SERV)
bogdanm 82:6473597d706e 5253 #define EWM_CMPL_REG(base) ((base)->CMPL)
bogdanm 82:6473597d706e 5254 #define EWM_CMPH_REG(base) ((base)->CMPH)
bogdanm 82:6473597d706e 5255
bogdanm 82:6473597d706e 5256 /*!
bogdanm 82:6473597d706e 5257 * @}
bogdanm 82:6473597d706e 5258 */ /* end of group EWM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 5259
bogdanm 82:6473597d706e 5260
bogdanm 82:6473597d706e 5261 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5262 -- EWM Register Masks
bogdanm 82:6473597d706e 5263 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5264
bogdanm 82:6473597d706e 5265 /*!
bogdanm 82:6473597d706e 5266 * @addtogroup EWM_Register_Masks EWM Register Masks
bogdanm 82:6473597d706e 5267 * @{
bogdanm 82:6473597d706e 5268 */
bogdanm 82:6473597d706e 5269
bogdanm 82:6473597d706e 5270 /* CTRL Bit Fields */
bogdanm 82:6473597d706e 5271 #define EWM_CTRL_EWMEN_MASK 0x1u
bogdanm 82:6473597d706e 5272 #define EWM_CTRL_EWMEN_SHIFT 0
bogdanm 82:6473597d706e 5273 #define EWM_CTRL_ASSIN_MASK 0x2u
bogdanm 82:6473597d706e 5274 #define EWM_CTRL_ASSIN_SHIFT 1
bogdanm 82:6473597d706e 5275 #define EWM_CTRL_INEN_MASK 0x4u
bogdanm 82:6473597d706e 5276 #define EWM_CTRL_INEN_SHIFT 2
bogdanm 82:6473597d706e 5277 #define EWM_CTRL_INTEN_MASK 0x8u
bogdanm 82:6473597d706e 5278 #define EWM_CTRL_INTEN_SHIFT 3
bogdanm 82:6473597d706e 5279 /* SERV Bit Fields */
bogdanm 82:6473597d706e 5280 #define EWM_SERV_SERVICE_MASK 0xFFu
bogdanm 82:6473597d706e 5281 #define EWM_SERV_SERVICE_SHIFT 0
bogdanm 82:6473597d706e 5282 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
bogdanm 82:6473597d706e 5283 /* CMPL Bit Fields */
bogdanm 82:6473597d706e 5284 #define EWM_CMPL_COMPAREL_MASK 0xFFu
bogdanm 82:6473597d706e 5285 #define EWM_CMPL_COMPAREL_SHIFT 0
bogdanm 82:6473597d706e 5286 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
bogdanm 82:6473597d706e 5287 /* CMPH Bit Fields */
bogdanm 82:6473597d706e 5288 #define EWM_CMPH_COMPAREH_MASK 0xFFu
bogdanm 82:6473597d706e 5289 #define EWM_CMPH_COMPAREH_SHIFT 0
bogdanm 82:6473597d706e 5290 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
bogdanm 82:6473597d706e 5291
bogdanm 82:6473597d706e 5292 /*!
bogdanm 82:6473597d706e 5293 * @}
bogdanm 82:6473597d706e 5294 */ /* end of group EWM_Register_Masks */
bogdanm 82:6473597d706e 5295
bogdanm 82:6473597d706e 5296
bogdanm 82:6473597d706e 5297 /* EWM - Peripheral instance base addresses */
bogdanm 82:6473597d706e 5298 /** Peripheral EWM base address */
bogdanm 82:6473597d706e 5299 #define EWM_BASE (0x40061000u)
bogdanm 82:6473597d706e 5300 /** Peripheral EWM base pointer */
bogdanm 82:6473597d706e 5301 #define EWM ((EWM_Type *)EWM_BASE)
bogdanm 82:6473597d706e 5302 #define EWM_BASE_PTR (EWM)
bogdanm 82:6473597d706e 5303 /** Array initializer of EWM peripheral base pointers */
bogdanm 82:6473597d706e 5304 #define EWM_BASES { EWM }
bogdanm 82:6473597d706e 5305
bogdanm 82:6473597d706e 5306 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5307 -- EWM - Register accessor macros
bogdanm 82:6473597d706e 5308 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5309
bogdanm 82:6473597d706e 5310 /*!
bogdanm 82:6473597d706e 5311 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
bogdanm 82:6473597d706e 5312 * @{
bogdanm 82:6473597d706e 5313 */
bogdanm 82:6473597d706e 5314
bogdanm 82:6473597d706e 5315
bogdanm 82:6473597d706e 5316 /* EWM - Register instance definitions */
bogdanm 82:6473597d706e 5317 /* EWM */
bogdanm 82:6473597d706e 5318 #define EWM_CTRL EWM_CTRL_REG(EWM)
bogdanm 82:6473597d706e 5319 #define EWM_SERV EWM_SERV_REG(EWM)
bogdanm 82:6473597d706e 5320 #define EWM_CMPL EWM_CMPL_REG(EWM)
bogdanm 82:6473597d706e 5321 #define EWM_CMPH EWM_CMPH_REG(EWM)
bogdanm 82:6473597d706e 5322
bogdanm 82:6473597d706e 5323 /*!
bogdanm 82:6473597d706e 5324 * @}
bogdanm 82:6473597d706e 5325 */ /* end of group EWM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 5326
bogdanm 82:6473597d706e 5327
bogdanm 82:6473597d706e 5328 /*!
bogdanm 82:6473597d706e 5329 * @}
bogdanm 82:6473597d706e 5330 */ /* end of group EWM_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 5331
bogdanm 82:6473597d706e 5332
bogdanm 82:6473597d706e 5333 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5334 -- FB Peripheral Access Layer
bogdanm 82:6473597d706e 5335 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5336
bogdanm 82:6473597d706e 5337 /*!
bogdanm 82:6473597d706e 5338 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
bogdanm 82:6473597d706e 5339 * @{
bogdanm 82:6473597d706e 5340 */
bogdanm 82:6473597d706e 5341
bogdanm 82:6473597d706e 5342 /** FB - Register Layout Typedef */
bogdanm 82:6473597d706e 5343 typedef struct {
bogdanm 82:6473597d706e 5344 struct { /* offset: 0x0, array step: 0xC */
bogdanm 82:6473597d706e 5345 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
bogdanm 82:6473597d706e 5346 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
bogdanm 82:6473597d706e 5347 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
bogdanm 82:6473597d706e 5348 } CS[6];
bogdanm 82:6473597d706e 5349 uint8_t RESERVED_0[24];
bogdanm 82:6473597d706e 5350 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
bogdanm 82:6473597d706e 5351 } FB_Type, *FB_MemMapPtr;
bogdanm 82:6473597d706e 5352
bogdanm 82:6473597d706e 5353 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5354 -- FB - Register accessor macros
bogdanm 82:6473597d706e 5355 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5356
bogdanm 82:6473597d706e 5357 /*!
bogdanm 82:6473597d706e 5358 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
bogdanm 82:6473597d706e 5359 * @{
bogdanm 82:6473597d706e 5360 */
bogdanm 82:6473597d706e 5361
bogdanm 82:6473597d706e 5362
bogdanm 82:6473597d706e 5363 /* FB - Register accessors */
bogdanm 82:6473597d706e 5364 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
bogdanm 82:6473597d706e 5365 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
bogdanm 82:6473597d706e 5366 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
bogdanm 82:6473597d706e 5367 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
bogdanm 82:6473597d706e 5368
bogdanm 82:6473597d706e 5369 /*!
bogdanm 82:6473597d706e 5370 * @}
bogdanm 82:6473597d706e 5371 */ /* end of group FB_Register_Accessor_Macros */
bogdanm 82:6473597d706e 5372
bogdanm 82:6473597d706e 5373
bogdanm 82:6473597d706e 5374 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5375 -- FB Register Masks
bogdanm 82:6473597d706e 5376 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5377
bogdanm 82:6473597d706e 5378 /*!
bogdanm 82:6473597d706e 5379 * @addtogroup FB_Register_Masks FB Register Masks
bogdanm 82:6473597d706e 5380 * @{
bogdanm 82:6473597d706e 5381 */
bogdanm 82:6473597d706e 5382
bogdanm 82:6473597d706e 5383 /* CSAR Bit Fields */
bogdanm 82:6473597d706e 5384 #define FB_CSAR_BA_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 5385 #define FB_CSAR_BA_SHIFT 16
bogdanm 82:6473597d706e 5386 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
bogdanm 82:6473597d706e 5387 /* CSMR Bit Fields */
bogdanm 82:6473597d706e 5388 #define FB_CSMR_V_MASK 0x1u
bogdanm 82:6473597d706e 5389 #define FB_CSMR_V_SHIFT 0
bogdanm 82:6473597d706e 5390 #define FB_CSMR_WP_MASK 0x100u
bogdanm 82:6473597d706e 5391 #define FB_CSMR_WP_SHIFT 8
bogdanm 82:6473597d706e 5392 #define FB_CSMR_BAM_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 5393 #define FB_CSMR_BAM_SHIFT 16
bogdanm 82:6473597d706e 5394 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
bogdanm 82:6473597d706e 5395 /* CSCR Bit Fields */
bogdanm 82:6473597d706e 5396 #define FB_CSCR_BSTW_MASK 0x8u
bogdanm 82:6473597d706e 5397 #define FB_CSCR_BSTW_SHIFT 3
bogdanm 82:6473597d706e 5398 #define FB_CSCR_BSTR_MASK 0x10u
bogdanm 82:6473597d706e 5399 #define FB_CSCR_BSTR_SHIFT 4
bogdanm 82:6473597d706e 5400 #define FB_CSCR_BEM_MASK 0x20u
bogdanm 82:6473597d706e 5401 #define FB_CSCR_BEM_SHIFT 5
bogdanm 82:6473597d706e 5402 #define FB_CSCR_PS_MASK 0xC0u
bogdanm 82:6473597d706e 5403 #define FB_CSCR_PS_SHIFT 6
bogdanm 82:6473597d706e 5404 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
bogdanm 82:6473597d706e 5405 #define FB_CSCR_AA_MASK 0x100u
bogdanm 82:6473597d706e 5406 #define FB_CSCR_AA_SHIFT 8
bogdanm 82:6473597d706e 5407 #define FB_CSCR_BLS_MASK 0x200u
bogdanm 82:6473597d706e 5408 #define FB_CSCR_BLS_SHIFT 9
bogdanm 82:6473597d706e 5409 #define FB_CSCR_WS_MASK 0xFC00u
bogdanm 82:6473597d706e 5410 #define FB_CSCR_WS_SHIFT 10
bogdanm 82:6473597d706e 5411 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
bogdanm 82:6473597d706e 5412 #define FB_CSCR_WRAH_MASK 0x30000u
bogdanm 82:6473597d706e 5413 #define FB_CSCR_WRAH_SHIFT 16
bogdanm 82:6473597d706e 5414 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
bogdanm 82:6473597d706e 5415 #define FB_CSCR_RDAH_MASK 0xC0000u
bogdanm 82:6473597d706e 5416 #define FB_CSCR_RDAH_SHIFT 18
bogdanm 82:6473597d706e 5417 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
bogdanm 82:6473597d706e 5418 #define FB_CSCR_ASET_MASK 0x300000u
bogdanm 82:6473597d706e 5419 #define FB_CSCR_ASET_SHIFT 20
bogdanm 82:6473597d706e 5420 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
bogdanm 82:6473597d706e 5421 #define FB_CSCR_EXTS_MASK 0x400000u
bogdanm 82:6473597d706e 5422 #define FB_CSCR_EXTS_SHIFT 22
bogdanm 82:6473597d706e 5423 #define FB_CSCR_SWSEN_MASK 0x800000u
bogdanm 82:6473597d706e 5424 #define FB_CSCR_SWSEN_SHIFT 23
bogdanm 82:6473597d706e 5425 #define FB_CSCR_SWS_MASK 0xFC000000u
bogdanm 82:6473597d706e 5426 #define FB_CSCR_SWS_SHIFT 26
bogdanm 82:6473597d706e 5427 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
bogdanm 82:6473597d706e 5428 /* CSPMCR Bit Fields */
bogdanm 82:6473597d706e 5429 #define FB_CSPMCR_GROUP5_MASK 0xF000u
bogdanm 82:6473597d706e 5430 #define FB_CSPMCR_GROUP5_SHIFT 12
bogdanm 82:6473597d706e 5431 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
bogdanm 82:6473597d706e 5432 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
bogdanm 82:6473597d706e 5433 #define FB_CSPMCR_GROUP4_SHIFT 16
bogdanm 82:6473597d706e 5434 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
bogdanm 82:6473597d706e 5435 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
bogdanm 82:6473597d706e 5436 #define FB_CSPMCR_GROUP3_SHIFT 20
bogdanm 82:6473597d706e 5437 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
bogdanm 82:6473597d706e 5438 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
bogdanm 82:6473597d706e 5439 #define FB_CSPMCR_GROUP2_SHIFT 24
bogdanm 82:6473597d706e 5440 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
bogdanm 82:6473597d706e 5441 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
bogdanm 82:6473597d706e 5442 #define FB_CSPMCR_GROUP1_SHIFT 28
bogdanm 82:6473597d706e 5443 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
bogdanm 82:6473597d706e 5444
bogdanm 82:6473597d706e 5445 /*!
bogdanm 82:6473597d706e 5446 * @}
bogdanm 82:6473597d706e 5447 */ /* end of group FB_Register_Masks */
bogdanm 82:6473597d706e 5448
bogdanm 82:6473597d706e 5449
bogdanm 82:6473597d706e 5450 /* FB - Peripheral instance base addresses */
bogdanm 82:6473597d706e 5451 /** Peripheral FB base address */
bogdanm 82:6473597d706e 5452 #define FB_BASE (0x4000C000u)
bogdanm 82:6473597d706e 5453 /** Peripheral FB base pointer */
bogdanm 82:6473597d706e 5454 #define FB ((FB_Type *)FB_BASE)
bogdanm 82:6473597d706e 5455 #define FB_BASE_PTR (FB)
bogdanm 82:6473597d706e 5456 /** Array initializer of FB peripheral base pointers */
bogdanm 82:6473597d706e 5457 #define FB_BASES { FB }
bogdanm 82:6473597d706e 5458
bogdanm 82:6473597d706e 5459 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5460 -- FB - Register accessor macros
bogdanm 82:6473597d706e 5461 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5462
bogdanm 82:6473597d706e 5463 /*!
bogdanm 82:6473597d706e 5464 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
bogdanm 82:6473597d706e 5465 * @{
bogdanm 82:6473597d706e 5466 */
bogdanm 82:6473597d706e 5467
bogdanm 82:6473597d706e 5468
bogdanm 82:6473597d706e 5469 /* FB - Register instance definitions */
bogdanm 82:6473597d706e 5470 /* FB */
bogdanm 82:6473597d706e 5471 #define FB_CSAR0 FB_CSAR_REG(FB,0)
bogdanm 82:6473597d706e 5472 #define FB_CSMR0 FB_CSMR_REG(FB,0)
bogdanm 82:6473597d706e 5473 #define FB_CSCR0 FB_CSCR_REG(FB,0)
bogdanm 82:6473597d706e 5474 #define FB_CSAR1 FB_CSAR_REG(FB,1)
bogdanm 82:6473597d706e 5475 #define FB_CSMR1 FB_CSMR_REG(FB,1)
bogdanm 82:6473597d706e 5476 #define FB_CSCR1 FB_CSCR_REG(FB,1)
bogdanm 82:6473597d706e 5477 #define FB_CSAR2 FB_CSAR_REG(FB,2)
bogdanm 82:6473597d706e 5478 #define FB_CSMR2 FB_CSMR_REG(FB,2)
bogdanm 82:6473597d706e 5479 #define FB_CSCR2 FB_CSCR_REG(FB,2)
bogdanm 82:6473597d706e 5480 #define FB_CSAR3 FB_CSAR_REG(FB,3)
bogdanm 82:6473597d706e 5481 #define FB_CSMR3 FB_CSMR_REG(FB,3)
bogdanm 82:6473597d706e 5482 #define FB_CSCR3 FB_CSCR_REG(FB,3)
bogdanm 82:6473597d706e 5483 #define FB_CSAR4 FB_CSAR_REG(FB,4)
bogdanm 82:6473597d706e 5484 #define FB_CSMR4 FB_CSMR_REG(FB,4)
bogdanm 82:6473597d706e 5485 #define FB_CSCR4 FB_CSCR_REG(FB,4)
bogdanm 82:6473597d706e 5486 #define FB_CSAR5 FB_CSAR_REG(FB,5)
bogdanm 82:6473597d706e 5487 #define FB_CSMR5 FB_CSMR_REG(FB,5)
bogdanm 82:6473597d706e 5488 #define FB_CSCR5 FB_CSCR_REG(FB,5)
bogdanm 82:6473597d706e 5489 #define FB_CSPMCR FB_CSPMCR_REG(FB)
bogdanm 82:6473597d706e 5490
bogdanm 82:6473597d706e 5491 /* FB - Register array accessors */
bogdanm 82:6473597d706e 5492 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
bogdanm 82:6473597d706e 5493 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
bogdanm 82:6473597d706e 5494 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
bogdanm 82:6473597d706e 5495
bogdanm 82:6473597d706e 5496 /*!
bogdanm 82:6473597d706e 5497 * @}
bogdanm 82:6473597d706e 5498 */ /* end of group FB_Register_Accessor_Macros */
bogdanm 82:6473597d706e 5499
bogdanm 82:6473597d706e 5500
bogdanm 82:6473597d706e 5501 /*!
bogdanm 82:6473597d706e 5502 * @}
bogdanm 82:6473597d706e 5503 */ /* end of group FB_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 5504
bogdanm 82:6473597d706e 5505
bogdanm 82:6473597d706e 5506 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5507 -- FMC Peripheral Access Layer
bogdanm 82:6473597d706e 5508 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5509
bogdanm 82:6473597d706e 5510 /*!
bogdanm 82:6473597d706e 5511 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
bogdanm 82:6473597d706e 5512 * @{
bogdanm 82:6473597d706e 5513 */
bogdanm 82:6473597d706e 5514
bogdanm 82:6473597d706e 5515 /** FMC - Register Layout Typedef */
bogdanm 82:6473597d706e 5516 typedef struct {
bogdanm 82:6473597d706e 5517 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
bogdanm 82:6473597d706e 5518 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
bogdanm 82:6473597d706e 5519 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
bogdanm 82:6473597d706e 5520 uint8_t RESERVED_0[244];
bogdanm 82:6473597d706e 5521 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
bogdanm 82:6473597d706e 5522 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
bogdanm 82:6473597d706e 5523 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
bogdanm 82:6473597d706e 5524 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
bogdanm 82:6473597d706e 5525 uint8_t RESERVED_1[192];
bogdanm 82:6473597d706e 5526 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
bogdanm 82:6473597d706e 5527 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
bogdanm 82:6473597d706e 5528 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
bogdanm 82:6473597d706e 5529 } SET[4][4];
bogdanm 82:6473597d706e 5530 } FMC_Type, *FMC_MemMapPtr;
bogdanm 82:6473597d706e 5531
bogdanm 82:6473597d706e 5532 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5533 -- FMC - Register accessor macros
bogdanm 82:6473597d706e 5534 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5535
bogdanm 82:6473597d706e 5536 /*!
bogdanm 82:6473597d706e 5537 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
bogdanm 82:6473597d706e 5538 * @{
bogdanm 82:6473597d706e 5539 */
bogdanm 82:6473597d706e 5540
bogdanm 82:6473597d706e 5541
bogdanm 82:6473597d706e 5542 /* FMC - Register accessors */
bogdanm 82:6473597d706e 5543 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
bogdanm 82:6473597d706e 5544 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
bogdanm 82:6473597d706e 5545 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
bogdanm 82:6473597d706e 5546 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
bogdanm 82:6473597d706e 5547 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
bogdanm 82:6473597d706e 5548 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
bogdanm 82:6473597d706e 5549 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
bogdanm 82:6473597d706e 5550 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
bogdanm 82:6473597d706e 5551 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
bogdanm 82:6473597d706e 5552
bogdanm 82:6473597d706e 5553 /*!
bogdanm 82:6473597d706e 5554 * @}
bogdanm 82:6473597d706e 5555 */ /* end of group FMC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 5556
bogdanm 82:6473597d706e 5557
bogdanm 82:6473597d706e 5558 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5559 -- FMC Register Masks
bogdanm 82:6473597d706e 5560 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5561
bogdanm 82:6473597d706e 5562 /*!
bogdanm 82:6473597d706e 5563 * @addtogroup FMC_Register_Masks FMC Register Masks
bogdanm 82:6473597d706e 5564 * @{
bogdanm 82:6473597d706e 5565 */
bogdanm 82:6473597d706e 5566
bogdanm 82:6473597d706e 5567 /* PFAPR Bit Fields */
bogdanm 82:6473597d706e 5568 #define FMC_PFAPR_M0AP_MASK 0x3u
bogdanm 82:6473597d706e 5569 #define FMC_PFAPR_M0AP_SHIFT 0
bogdanm 82:6473597d706e 5570 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
bogdanm 82:6473597d706e 5571 #define FMC_PFAPR_M1AP_MASK 0xCu
bogdanm 82:6473597d706e 5572 #define FMC_PFAPR_M1AP_SHIFT 2
bogdanm 82:6473597d706e 5573 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
bogdanm 82:6473597d706e 5574 #define FMC_PFAPR_M2AP_MASK 0x30u
bogdanm 82:6473597d706e 5575 #define FMC_PFAPR_M2AP_SHIFT 4
bogdanm 82:6473597d706e 5576 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
bogdanm 82:6473597d706e 5577 #define FMC_PFAPR_M3AP_MASK 0xC0u
bogdanm 82:6473597d706e 5578 #define FMC_PFAPR_M3AP_SHIFT 6
bogdanm 82:6473597d706e 5579 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
bogdanm 82:6473597d706e 5580 #define FMC_PFAPR_M4AP_MASK 0x300u
bogdanm 82:6473597d706e 5581 #define FMC_PFAPR_M4AP_SHIFT 8
bogdanm 82:6473597d706e 5582 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
bogdanm 82:6473597d706e 5583 #define FMC_PFAPR_M5AP_MASK 0xC00u
bogdanm 82:6473597d706e 5584 #define FMC_PFAPR_M5AP_SHIFT 10
bogdanm 82:6473597d706e 5585 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
bogdanm 82:6473597d706e 5586 #define FMC_PFAPR_M6AP_MASK 0x3000u
bogdanm 82:6473597d706e 5587 #define FMC_PFAPR_M6AP_SHIFT 12
bogdanm 82:6473597d706e 5588 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
bogdanm 82:6473597d706e 5589 #define FMC_PFAPR_M7AP_MASK 0xC000u
bogdanm 82:6473597d706e 5590 #define FMC_PFAPR_M7AP_SHIFT 14
bogdanm 82:6473597d706e 5591 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
bogdanm 82:6473597d706e 5592 #define FMC_PFAPR_M0PFD_MASK 0x10000u
bogdanm 82:6473597d706e 5593 #define FMC_PFAPR_M0PFD_SHIFT 16
bogdanm 82:6473597d706e 5594 #define FMC_PFAPR_M1PFD_MASK 0x20000u
bogdanm 82:6473597d706e 5595 #define FMC_PFAPR_M1PFD_SHIFT 17
bogdanm 82:6473597d706e 5596 #define FMC_PFAPR_M2PFD_MASK 0x40000u
bogdanm 82:6473597d706e 5597 #define FMC_PFAPR_M2PFD_SHIFT 18
bogdanm 82:6473597d706e 5598 #define FMC_PFAPR_M3PFD_MASK 0x80000u
bogdanm 82:6473597d706e 5599 #define FMC_PFAPR_M3PFD_SHIFT 19
bogdanm 82:6473597d706e 5600 #define FMC_PFAPR_M4PFD_MASK 0x100000u
bogdanm 82:6473597d706e 5601 #define FMC_PFAPR_M4PFD_SHIFT 20
bogdanm 82:6473597d706e 5602 #define FMC_PFAPR_M5PFD_MASK 0x200000u
bogdanm 82:6473597d706e 5603 #define FMC_PFAPR_M5PFD_SHIFT 21
bogdanm 82:6473597d706e 5604 #define FMC_PFAPR_M6PFD_MASK 0x400000u
bogdanm 82:6473597d706e 5605 #define FMC_PFAPR_M6PFD_SHIFT 22
bogdanm 82:6473597d706e 5606 #define FMC_PFAPR_M7PFD_MASK 0x800000u
bogdanm 82:6473597d706e 5607 #define FMC_PFAPR_M7PFD_SHIFT 23
bogdanm 82:6473597d706e 5608 /* PFB0CR Bit Fields */
bogdanm 82:6473597d706e 5609 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
bogdanm 82:6473597d706e 5610 #define FMC_PFB0CR_B0SEBE_SHIFT 0
bogdanm 82:6473597d706e 5611 #define FMC_PFB0CR_B0IPE_MASK 0x2u
bogdanm 82:6473597d706e 5612 #define FMC_PFB0CR_B0IPE_SHIFT 1
bogdanm 82:6473597d706e 5613 #define FMC_PFB0CR_B0DPE_MASK 0x4u
bogdanm 82:6473597d706e 5614 #define FMC_PFB0CR_B0DPE_SHIFT 2
bogdanm 82:6473597d706e 5615 #define FMC_PFB0CR_B0ICE_MASK 0x8u
bogdanm 82:6473597d706e 5616 #define FMC_PFB0CR_B0ICE_SHIFT 3
bogdanm 82:6473597d706e 5617 #define FMC_PFB0CR_B0DCE_MASK 0x10u
bogdanm 82:6473597d706e 5618 #define FMC_PFB0CR_B0DCE_SHIFT 4
bogdanm 82:6473597d706e 5619 #define FMC_PFB0CR_CRC_MASK 0xE0u
bogdanm 82:6473597d706e 5620 #define FMC_PFB0CR_CRC_SHIFT 5
bogdanm 82:6473597d706e 5621 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
bogdanm 82:6473597d706e 5622 #define FMC_PFB0CR_B0MW_MASK 0x60000u
bogdanm 82:6473597d706e 5623 #define FMC_PFB0CR_B0MW_SHIFT 17
bogdanm 82:6473597d706e 5624 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
bogdanm 82:6473597d706e 5625 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
bogdanm 82:6473597d706e 5626 #define FMC_PFB0CR_S_B_INV_SHIFT 19
bogdanm 82:6473597d706e 5627 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
bogdanm 82:6473597d706e 5628 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
bogdanm 82:6473597d706e 5629 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
bogdanm 82:6473597d706e 5630 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
bogdanm 82:6473597d706e 5631 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
bogdanm 82:6473597d706e 5632 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
bogdanm 82:6473597d706e 5633 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
bogdanm 82:6473597d706e 5634 #define FMC_PFB0CR_B0RWSC_SHIFT 28
bogdanm 82:6473597d706e 5635 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
bogdanm 82:6473597d706e 5636 /* PFB1CR Bit Fields */
bogdanm 82:6473597d706e 5637 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
bogdanm 82:6473597d706e 5638 #define FMC_PFB1CR_B1SEBE_SHIFT 0
bogdanm 82:6473597d706e 5639 #define FMC_PFB1CR_B1IPE_MASK 0x2u
bogdanm 82:6473597d706e 5640 #define FMC_PFB1CR_B1IPE_SHIFT 1
bogdanm 82:6473597d706e 5641 #define FMC_PFB1CR_B1DPE_MASK 0x4u
bogdanm 82:6473597d706e 5642 #define FMC_PFB1CR_B1DPE_SHIFT 2
bogdanm 82:6473597d706e 5643 #define FMC_PFB1CR_B1ICE_MASK 0x8u
bogdanm 82:6473597d706e 5644 #define FMC_PFB1CR_B1ICE_SHIFT 3
bogdanm 82:6473597d706e 5645 #define FMC_PFB1CR_B1DCE_MASK 0x10u
bogdanm 82:6473597d706e 5646 #define FMC_PFB1CR_B1DCE_SHIFT 4
bogdanm 82:6473597d706e 5647 #define FMC_PFB1CR_B1MW_MASK 0x60000u
bogdanm 82:6473597d706e 5648 #define FMC_PFB1CR_B1MW_SHIFT 17
bogdanm 82:6473597d706e 5649 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
bogdanm 82:6473597d706e 5650 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
bogdanm 82:6473597d706e 5651 #define FMC_PFB1CR_B1RWSC_SHIFT 28
bogdanm 82:6473597d706e 5652 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
bogdanm 82:6473597d706e 5653 /* TAGVDW0S Bit Fields */
bogdanm 82:6473597d706e 5654 #define FMC_TAGVDW0S_valid_MASK 0x1u
bogdanm 82:6473597d706e 5655 #define FMC_TAGVDW0S_valid_SHIFT 0
bogdanm 82:6473597d706e 5656 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
bogdanm 82:6473597d706e 5657 #define FMC_TAGVDW0S_tag_SHIFT 5
bogdanm 82:6473597d706e 5658 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
bogdanm 82:6473597d706e 5659 /* TAGVDW1S Bit Fields */
bogdanm 82:6473597d706e 5660 #define FMC_TAGVDW1S_valid_MASK 0x1u
bogdanm 82:6473597d706e 5661 #define FMC_TAGVDW1S_valid_SHIFT 0
bogdanm 82:6473597d706e 5662 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
bogdanm 82:6473597d706e 5663 #define FMC_TAGVDW1S_tag_SHIFT 5
bogdanm 82:6473597d706e 5664 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
bogdanm 82:6473597d706e 5665 /* TAGVDW2S Bit Fields */
bogdanm 82:6473597d706e 5666 #define FMC_TAGVDW2S_valid_MASK 0x1u
bogdanm 82:6473597d706e 5667 #define FMC_TAGVDW2S_valid_SHIFT 0
bogdanm 82:6473597d706e 5668 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
bogdanm 82:6473597d706e 5669 #define FMC_TAGVDW2S_tag_SHIFT 5
bogdanm 82:6473597d706e 5670 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
bogdanm 82:6473597d706e 5671 /* TAGVDW3S Bit Fields */
bogdanm 82:6473597d706e 5672 #define FMC_TAGVDW3S_valid_MASK 0x1u
bogdanm 82:6473597d706e 5673 #define FMC_TAGVDW3S_valid_SHIFT 0
bogdanm 82:6473597d706e 5674 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
bogdanm 82:6473597d706e 5675 #define FMC_TAGVDW3S_tag_SHIFT 5
bogdanm 82:6473597d706e 5676 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
bogdanm 82:6473597d706e 5677 /* DATA_U Bit Fields */
bogdanm 82:6473597d706e 5678 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 5679 #define FMC_DATA_U_data_SHIFT 0
bogdanm 82:6473597d706e 5680 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
bogdanm 82:6473597d706e 5681 /* DATA_L Bit Fields */
bogdanm 82:6473597d706e 5682 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 5683 #define FMC_DATA_L_data_SHIFT 0
bogdanm 82:6473597d706e 5684 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
bogdanm 82:6473597d706e 5685
bogdanm 82:6473597d706e 5686 /*!
bogdanm 82:6473597d706e 5687 * @}
bogdanm 82:6473597d706e 5688 */ /* end of group FMC_Register_Masks */
bogdanm 82:6473597d706e 5689
bogdanm 82:6473597d706e 5690
bogdanm 82:6473597d706e 5691 /* FMC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 5692 /** Peripheral FMC base address */
bogdanm 82:6473597d706e 5693 #define FMC_BASE (0x4001F000u)
bogdanm 82:6473597d706e 5694 /** Peripheral FMC base pointer */
bogdanm 82:6473597d706e 5695 #define FMC ((FMC_Type *)FMC_BASE)
bogdanm 82:6473597d706e 5696 #define FMC_BASE_PTR (FMC)
bogdanm 82:6473597d706e 5697 /** Array initializer of FMC peripheral base pointers */
bogdanm 82:6473597d706e 5698 #define FMC_BASES { FMC }
bogdanm 82:6473597d706e 5699
bogdanm 82:6473597d706e 5700 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5701 -- FMC - Register accessor macros
bogdanm 82:6473597d706e 5702 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5703
bogdanm 82:6473597d706e 5704 /*!
bogdanm 82:6473597d706e 5705 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
bogdanm 82:6473597d706e 5706 * @{
bogdanm 82:6473597d706e 5707 */
bogdanm 82:6473597d706e 5708
bogdanm 82:6473597d706e 5709
bogdanm 82:6473597d706e 5710 /* FMC - Register instance definitions */
bogdanm 82:6473597d706e 5711 /* FMC */
bogdanm 82:6473597d706e 5712 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
bogdanm 82:6473597d706e 5713 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
bogdanm 82:6473597d706e 5714 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
bogdanm 82:6473597d706e 5715 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
bogdanm 82:6473597d706e 5716 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
bogdanm 82:6473597d706e 5717 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
bogdanm 82:6473597d706e 5718 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
bogdanm 82:6473597d706e 5719 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
bogdanm 82:6473597d706e 5720 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
bogdanm 82:6473597d706e 5721 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
bogdanm 82:6473597d706e 5722 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
bogdanm 82:6473597d706e 5723 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
bogdanm 82:6473597d706e 5724 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
bogdanm 82:6473597d706e 5725 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
bogdanm 82:6473597d706e 5726 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
bogdanm 82:6473597d706e 5727 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
bogdanm 82:6473597d706e 5728 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
bogdanm 82:6473597d706e 5729 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
bogdanm 82:6473597d706e 5730 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
bogdanm 82:6473597d706e 5731 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
bogdanm 82:6473597d706e 5732 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
bogdanm 82:6473597d706e 5733 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
bogdanm 82:6473597d706e 5734 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
bogdanm 82:6473597d706e 5735 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
bogdanm 82:6473597d706e 5736 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
bogdanm 82:6473597d706e 5737 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
bogdanm 82:6473597d706e 5738 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
bogdanm 82:6473597d706e 5739 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
bogdanm 82:6473597d706e 5740 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
bogdanm 82:6473597d706e 5741 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
bogdanm 82:6473597d706e 5742 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
bogdanm 82:6473597d706e 5743 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
bogdanm 82:6473597d706e 5744 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
bogdanm 82:6473597d706e 5745 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
bogdanm 82:6473597d706e 5746 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
bogdanm 82:6473597d706e 5747 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
bogdanm 82:6473597d706e 5748 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
bogdanm 82:6473597d706e 5749 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
bogdanm 82:6473597d706e 5750 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
bogdanm 82:6473597d706e 5751 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
bogdanm 82:6473597d706e 5752 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
bogdanm 82:6473597d706e 5753 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
bogdanm 82:6473597d706e 5754 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
bogdanm 82:6473597d706e 5755 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
bogdanm 82:6473597d706e 5756 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
bogdanm 82:6473597d706e 5757 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
bogdanm 82:6473597d706e 5758 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
bogdanm 82:6473597d706e 5759 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
bogdanm 82:6473597d706e 5760 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
bogdanm 82:6473597d706e 5761 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
bogdanm 82:6473597d706e 5762 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
bogdanm 82:6473597d706e 5763
bogdanm 82:6473597d706e 5764 /* FMC - Register array accessors */
bogdanm 82:6473597d706e 5765 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
bogdanm 82:6473597d706e 5766 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
bogdanm 82:6473597d706e 5767 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
bogdanm 82:6473597d706e 5768 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
bogdanm 82:6473597d706e 5769 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
bogdanm 82:6473597d706e 5770 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
bogdanm 82:6473597d706e 5771
bogdanm 82:6473597d706e 5772 /*!
bogdanm 82:6473597d706e 5773 * @}
bogdanm 82:6473597d706e 5774 */ /* end of group FMC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 5775
bogdanm 82:6473597d706e 5776
bogdanm 82:6473597d706e 5777 /*!
bogdanm 82:6473597d706e 5778 * @}
bogdanm 82:6473597d706e 5779 */ /* end of group FMC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 5780
bogdanm 82:6473597d706e 5781
bogdanm 82:6473597d706e 5782 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5783 -- FTFE Peripheral Access Layer
bogdanm 82:6473597d706e 5784 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5785
bogdanm 82:6473597d706e 5786 /*!
bogdanm 82:6473597d706e 5787 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
bogdanm 82:6473597d706e 5788 * @{
bogdanm 82:6473597d706e 5789 */
bogdanm 82:6473597d706e 5790
bogdanm 82:6473597d706e 5791 /** FTFE - Register Layout Typedef */
bogdanm 82:6473597d706e 5792 typedef struct {
bogdanm 82:6473597d706e 5793 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
bogdanm 82:6473597d706e 5794 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
bogdanm 82:6473597d706e 5795 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
bogdanm 82:6473597d706e 5796 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
bogdanm 82:6473597d706e 5797 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
bogdanm 82:6473597d706e 5798 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
bogdanm 82:6473597d706e 5799 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
bogdanm 82:6473597d706e 5800 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
bogdanm 82:6473597d706e 5801 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
bogdanm 82:6473597d706e 5802 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
bogdanm 82:6473597d706e 5803 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
bogdanm 82:6473597d706e 5804 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
bogdanm 82:6473597d706e 5805 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
bogdanm 82:6473597d706e 5806 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
bogdanm 82:6473597d706e 5807 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
bogdanm 82:6473597d706e 5808 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
bogdanm 82:6473597d706e 5809 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
bogdanm 82:6473597d706e 5810 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
bogdanm 82:6473597d706e 5811 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
bogdanm 82:6473597d706e 5812 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
bogdanm 82:6473597d706e 5813 uint8_t RESERVED_0[2];
bogdanm 82:6473597d706e 5814 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
bogdanm 82:6473597d706e 5815 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
bogdanm 82:6473597d706e 5816 } FTFE_Type, *FTFE_MemMapPtr;
bogdanm 82:6473597d706e 5817
bogdanm 82:6473597d706e 5818 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5819 -- FTFE - Register accessor macros
bogdanm 82:6473597d706e 5820 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5821
bogdanm 82:6473597d706e 5822 /*!
bogdanm 82:6473597d706e 5823 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
bogdanm 82:6473597d706e 5824 * @{
bogdanm 82:6473597d706e 5825 */
bogdanm 82:6473597d706e 5826
bogdanm 82:6473597d706e 5827
bogdanm 82:6473597d706e 5828 /* FTFE - Register accessors */
bogdanm 82:6473597d706e 5829 #define FTFE_FSTAT_REG(base) ((base)->FSTAT)
bogdanm 82:6473597d706e 5830 #define FTFE_FCNFG_REG(base) ((base)->FCNFG)
bogdanm 82:6473597d706e 5831 #define FTFE_FSEC_REG(base) ((base)->FSEC)
bogdanm 82:6473597d706e 5832 #define FTFE_FOPT_REG(base) ((base)->FOPT)
bogdanm 82:6473597d706e 5833 #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
bogdanm 82:6473597d706e 5834 #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
bogdanm 82:6473597d706e 5835 #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
bogdanm 82:6473597d706e 5836 #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
bogdanm 82:6473597d706e 5837 #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
bogdanm 82:6473597d706e 5838 #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
bogdanm 82:6473597d706e 5839 #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
bogdanm 82:6473597d706e 5840 #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
bogdanm 82:6473597d706e 5841 #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
bogdanm 82:6473597d706e 5842 #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
bogdanm 82:6473597d706e 5843 #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
bogdanm 82:6473597d706e 5844 #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
bogdanm 82:6473597d706e 5845 #define FTFE_FPROT3_REG(base) ((base)->FPROT3)
bogdanm 82:6473597d706e 5846 #define FTFE_FPROT2_REG(base) ((base)->FPROT2)
bogdanm 82:6473597d706e 5847 #define FTFE_FPROT1_REG(base) ((base)->FPROT1)
bogdanm 82:6473597d706e 5848 #define FTFE_FPROT0_REG(base) ((base)->FPROT0)
bogdanm 82:6473597d706e 5849 #define FTFE_FEPROT_REG(base) ((base)->FEPROT)
bogdanm 82:6473597d706e 5850 #define FTFE_FDPROT_REG(base) ((base)->FDPROT)
bogdanm 82:6473597d706e 5851
bogdanm 82:6473597d706e 5852 /*!
bogdanm 82:6473597d706e 5853 * @}
bogdanm 82:6473597d706e 5854 */ /* end of group FTFE_Register_Accessor_Macros */
bogdanm 82:6473597d706e 5855
bogdanm 82:6473597d706e 5856
bogdanm 82:6473597d706e 5857 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5858 -- FTFE Register Masks
bogdanm 82:6473597d706e 5859 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 5860
bogdanm 82:6473597d706e 5861 /*!
bogdanm 82:6473597d706e 5862 * @addtogroup FTFE_Register_Masks FTFE Register Masks
bogdanm 82:6473597d706e 5863 * @{
bogdanm 82:6473597d706e 5864 */
bogdanm 82:6473597d706e 5865
bogdanm 82:6473597d706e 5866 /* FSTAT Bit Fields */
bogdanm 82:6473597d706e 5867 #define FTFE_FSTAT_MGSTAT0_MASK 0x1u
bogdanm 82:6473597d706e 5868 #define FTFE_FSTAT_MGSTAT0_SHIFT 0
bogdanm 82:6473597d706e 5869 #define FTFE_FSTAT_FPVIOL_MASK 0x10u
bogdanm 82:6473597d706e 5870 #define FTFE_FSTAT_FPVIOL_SHIFT 4
bogdanm 82:6473597d706e 5871 #define FTFE_FSTAT_ACCERR_MASK 0x20u
bogdanm 82:6473597d706e 5872 #define FTFE_FSTAT_ACCERR_SHIFT 5
bogdanm 82:6473597d706e 5873 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u
bogdanm 82:6473597d706e 5874 #define FTFE_FSTAT_RDCOLERR_SHIFT 6
bogdanm 82:6473597d706e 5875 #define FTFE_FSTAT_CCIF_MASK 0x80u
bogdanm 82:6473597d706e 5876 #define FTFE_FSTAT_CCIF_SHIFT 7
bogdanm 82:6473597d706e 5877 /* FCNFG Bit Fields */
bogdanm 82:6473597d706e 5878 #define FTFE_FCNFG_EEERDY_MASK 0x1u
bogdanm 82:6473597d706e 5879 #define FTFE_FCNFG_EEERDY_SHIFT 0
bogdanm 82:6473597d706e 5880 #define FTFE_FCNFG_RAMRDY_MASK 0x2u
bogdanm 82:6473597d706e 5881 #define FTFE_FCNFG_RAMRDY_SHIFT 1
bogdanm 82:6473597d706e 5882 #define FTFE_FCNFG_PFLSH_MASK 0x4u
bogdanm 82:6473597d706e 5883 #define FTFE_FCNFG_PFLSH_SHIFT 2
bogdanm 82:6473597d706e 5884 #define FTFE_FCNFG_SWAP_MASK 0x8u
bogdanm 82:6473597d706e 5885 #define FTFE_FCNFG_SWAP_SHIFT 3
bogdanm 82:6473597d706e 5886 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u
bogdanm 82:6473597d706e 5887 #define FTFE_FCNFG_ERSSUSP_SHIFT 4
bogdanm 82:6473597d706e 5888 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u
bogdanm 82:6473597d706e 5889 #define FTFE_FCNFG_ERSAREQ_SHIFT 5
bogdanm 82:6473597d706e 5890 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
bogdanm 82:6473597d706e 5891 #define FTFE_FCNFG_RDCOLLIE_SHIFT 6
bogdanm 82:6473597d706e 5892 #define FTFE_FCNFG_CCIE_MASK 0x80u
bogdanm 82:6473597d706e 5893 #define FTFE_FCNFG_CCIE_SHIFT 7
bogdanm 82:6473597d706e 5894 /* FSEC Bit Fields */
bogdanm 82:6473597d706e 5895 #define FTFE_FSEC_SEC_MASK 0x3u
bogdanm 82:6473597d706e 5896 #define FTFE_FSEC_SEC_SHIFT 0
bogdanm 82:6473597d706e 5897 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
bogdanm 82:6473597d706e 5898 #define FTFE_FSEC_FSLACC_MASK 0xCu
bogdanm 82:6473597d706e 5899 #define FTFE_FSEC_FSLACC_SHIFT 2
bogdanm 82:6473597d706e 5900 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
bogdanm 82:6473597d706e 5901 #define FTFE_FSEC_MEEN_MASK 0x30u
bogdanm 82:6473597d706e 5902 #define FTFE_FSEC_MEEN_SHIFT 4
bogdanm 82:6473597d706e 5903 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
bogdanm 82:6473597d706e 5904 #define FTFE_FSEC_KEYEN_MASK 0xC0u
bogdanm 82:6473597d706e 5905 #define FTFE_FSEC_KEYEN_SHIFT 6
bogdanm 82:6473597d706e 5906 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
bogdanm 82:6473597d706e 5907 /* FOPT Bit Fields */
bogdanm 82:6473597d706e 5908 #define FTFE_FOPT_OPT_MASK 0xFFu
bogdanm 82:6473597d706e 5909 #define FTFE_FOPT_OPT_SHIFT 0
bogdanm 82:6473597d706e 5910 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
bogdanm 82:6473597d706e 5911 /* FCCOB3 Bit Fields */
bogdanm 82:6473597d706e 5912 #define FTFE_FCCOB3_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5913 #define FTFE_FCCOB3_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5914 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
bogdanm 82:6473597d706e 5915 /* FCCOB2 Bit Fields */
bogdanm 82:6473597d706e 5916 #define FTFE_FCCOB2_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5917 #define FTFE_FCCOB2_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5918 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
bogdanm 82:6473597d706e 5919 /* FCCOB1 Bit Fields */
bogdanm 82:6473597d706e 5920 #define FTFE_FCCOB1_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5921 #define FTFE_FCCOB1_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5922 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
bogdanm 82:6473597d706e 5923 /* FCCOB0 Bit Fields */
bogdanm 82:6473597d706e 5924 #define FTFE_FCCOB0_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5925 #define FTFE_FCCOB0_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5926 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
bogdanm 82:6473597d706e 5927 /* FCCOB7 Bit Fields */
bogdanm 82:6473597d706e 5928 #define FTFE_FCCOB7_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5929 #define FTFE_FCCOB7_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5930 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
bogdanm 82:6473597d706e 5931 /* FCCOB6 Bit Fields */
bogdanm 82:6473597d706e 5932 #define FTFE_FCCOB6_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5933 #define FTFE_FCCOB6_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5934 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
bogdanm 82:6473597d706e 5935 /* FCCOB5 Bit Fields */
bogdanm 82:6473597d706e 5936 #define FTFE_FCCOB5_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5937 #define FTFE_FCCOB5_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5938 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
bogdanm 82:6473597d706e 5939 /* FCCOB4 Bit Fields */
bogdanm 82:6473597d706e 5940 #define FTFE_FCCOB4_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5941 #define FTFE_FCCOB4_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5942 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
bogdanm 82:6473597d706e 5943 /* FCCOBB Bit Fields */
bogdanm 82:6473597d706e 5944 #define FTFE_FCCOBB_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5945 #define FTFE_FCCOBB_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5946 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
bogdanm 82:6473597d706e 5947 /* FCCOBA Bit Fields */
bogdanm 82:6473597d706e 5948 #define FTFE_FCCOBA_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5949 #define FTFE_FCCOBA_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5950 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
bogdanm 82:6473597d706e 5951 /* FCCOB9 Bit Fields */
bogdanm 82:6473597d706e 5952 #define FTFE_FCCOB9_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5953 #define FTFE_FCCOB9_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5954 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
bogdanm 82:6473597d706e 5955 /* FCCOB8 Bit Fields */
bogdanm 82:6473597d706e 5956 #define FTFE_FCCOB8_CCOBn_MASK 0xFFu
bogdanm 82:6473597d706e 5957 #define FTFE_FCCOB8_CCOBn_SHIFT 0
bogdanm 82:6473597d706e 5958 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
bogdanm 82:6473597d706e 5959 /* FPROT3 Bit Fields */
bogdanm 82:6473597d706e 5960 #define FTFE_FPROT3_PROT_MASK 0xFFu
bogdanm 82:6473597d706e 5961 #define FTFE_FPROT3_PROT_SHIFT 0
bogdanm 82:6473597d706e 5962 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
bogdanm 82:6473597d706e 5963 /* FPROT2 Bit Fields */
bogdanm 82:6473597d706e 5964 #define FTFE_FPROT2_PROT_MASK 0xFFu
bogdanm 82:6473597d706e 5965 #define FTFE_FPROT2_PROT_SHIFT 0
bogdanm 82:6473597d706e 5966 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
bogdanm 82:6473597d706e 5967 /* FPROT1 Bit Fields */
bogdanm 82:6473597d706e 5968 #define FTFE_FPROT1_PROT_MASK 0xFFu
bogdanm 82:6473597d706e 5969 #define FTFE_FPROT1_PROT_SHIFT 0
bogdanm 82:6473597d706e 5970 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
bogdanm 82:6473597d706e 5971 /* FPROT0 Bit Fields */
bogdanm 82:6473597d706e 5972 #define FTFE_FPROT0_PROT_MASK 0xFFu
bogdanm 82:6473597d706e 5973 #define FTFE_FPROT0_PROT_SHIFT 0
bogdanm 82:6473597d706e 5974 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
bogdanm 82:6473597d706e 5975 /* FEPROT Bit Fields */
bogdanm 82:6473597d706e 5976 #define FTFE_FEPROT_EPROT_MASK 0xFFu
bogdanm 82:6473597d706e 5977 #define FTFE_FEPROT_EPROT_SHIFT 0
bogdanm 82:6473597d706e 5978 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
bogdanm 82:6473597d706e 5979 /* FDPROT Bit Fields */
bogdanm 82:6473597d706e 5980 #define FTFE_FDPROT_DPROT_MASK 0xFFu
bogdanm 82:6473597d706e 5981 #define FTFE_FDPROT_DPROT_SHIFT 0
bogdanm 82:6473597d706e 5982 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
bogdanm 82:6473597d706e 5983
bogdanm 82:6473597d706e 5984 /*!
bogdanm 82:6473597d706e 5985 * @}
bogdanm 82:6473597d706e 5986 */ /* end of group FTFE_Register_Masks */
bogdanm 82:6473597d706e 5987
bogdanm 82:6473597d706e 5988
bogdanm 82:6473597d706e 5989 /* FTFE - Peripheral instance base addresses */
bogdanm 82:6473597d706e 5990 /** Peripheral FTFE base address */
bogdanm 82:6473597d706e 5991 #define FTFE_BASE (0x40020000u)
bogdanm 82:6473597d706e 5992 /** Peripheral FTFE base pointer */
bogdanm 82:6473597d706e 5993 #define FTFE ((FTFE_Type *)FTFE_BASE)
bogdanm 82:6473597d706e 5994 #define FTFE_BASE_PTR (FTFE)
bogdanm 82:6473597d706e 5995 /** Array initializer of FTFE peripheral base pointers */
bogdanm 82:6473597d706e 5996 #define FTFE_BASES { FTFE }
bogdanm 82:6473597d706e 5997
bogdanm 82:6473597d706e 5998 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 5999 -- FTFE - Register accessor macros
bogdanm 82:6473597d706e 6000 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6001
bogdanm 82:6473597d706e 6002 /*!
bogdanm 82:6473597d706e 6003 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
bogdanm 82:6473597d706e 6004 * @{
bogdanm 82:6473597d706e 6005 */
bogdanm 82:6473597d706e 6006
bogdanm 82:6473597d706e 6007
bogdanm 82:6473597d706e 6008 /* FTFE - Register instance definitions */
bogdanm 82:6473597d706e 6009 /* FTFE */
bogdanm 82:6473597d706e 6010 #define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
bogdanm 82:6473597d706e 6011 #define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
bogdanm 82:6473597d706e 6012 #define FTFE_FSEC FTFE_FSEC_REG(FTFE)
bogdanm 82:6473597d706e 6013 #define FTFE_FOPT FTFE_FOPT_REG(FTFE)
bogdanm 82:6473597d706e 6014 #define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
bogdanm 82:6473597d706e 6015 #define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
bogdanm 82:6473597d706e 6016 #define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
bogdanm 82:6473597d706e 6017 #define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
bogdanm 82:6473597d706e 6018 #define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
bogdanm 82:6473597d706e 6019 #define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
bogdanm 82:6473597d706e 6020 #define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
bogdanm 82:6473597d706e 6021 #define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
bogdanm 82:6473597d706e 6022 #define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
bogdanm 82:6473597d706e 6023 #define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
bogdanm 82:6473597d706e 6024 #define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
bogdanm 82:6473597d706e 6025 #define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
bogdanm 82:6473597d706e 6026 #define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
bogdanm 82:6473597d706e 6027 #define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
bogdanm 82:6473597d706e 6028 #define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
bogdanm 82:6473597d706e 6029 #define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
bogdanm 82:6473597d706e 6030 #define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
bogdanm 82:6473597d706e 6031 #define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
bogdanm 82:6473597d706e 6032
bogdanm 82:6473597d706e 6033 /*!
bogdanm 82:6473597d706e 6034 * @}
bogdanm 82:6473597d706e 6035 */ /* end of group FTFE_Register_Accessor_Macros */
bogdanm 82:6473597d706e 6036
bogdanm 82:6473597d706e 6037
bogdanm 82:6473597d706e 6038 /*!
bogdanm 82:6473597d706e 6039 * @}
bogdanm 82:6473597d706e 6040 */ /* end of group FTFE_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 6041
bogdanm 82:6473597d706e 6042
bogdanm 82:6473597d706e 6043 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6044 -- FTM Peripheral Access Layer
bogdanm 82:6473597d706e 6045 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6046
bogdanm 82:6473597d706e 6047 /*!
bogdanm 82:6473597d706e 6048 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
bogdanm 82:6473597d706e 6049 * @{
bogdanm 82:6473597d706e 6050 */
bogdanm 82:6473597d706e 6051
bogdanm 82:6473597d706e 6052 /** FTM - Register Layout Typedef */
bogdanm 82:6473597d706e 6053 typedef struct {
bogdanm 82:6473597d706e 6054 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
bogdanm 82:6473597d706e 6055 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
bogdanm 82:6473597d706e 6056 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
bogdanm 82:6473597d706e 6057 struct { /* offset: 0xC, array step: 0x8 */
bogdanm 82:6473597d706e 6058 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
bogdanm 82:6473597d706e 6059 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
bogdanm 82:6473597d706e 6060 } CONTROLS[8];
bogdanm 82:6473597d706e 6061 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
bogdanm 82:6473597d706e 6062 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
bogdanm 82:6473597d706e 6063 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
bogdanm 82:6473597d706e 6064 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
bogdanm 82:6473597d706e 6065 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
bogdanm 82:6473597d706e 6066 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
bogdanm 82:6473597d706e 6067 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
bogdanm 82:6473597d706e 6068 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
bogdanm 82:6473597d706e 6069 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
bogdanm 82:6473597d706e 6070 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
bogdanm 82:6473597d706e 6071 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
bogdanm 82:6473597d706e 6072 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
bogdanm 82:6473597d706e 6073 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
bogdanm 82:6473597d706e 6074 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
bogdanm 82:6473597d706e 6075 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
bogdanm 82:6473597d706e 6076 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
bogdanm 82:6473597d706e 6077 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
bogdanm 82:6473597d706e 6078 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
bogdanm 82:6473597d706e 6079 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
bogdanm 82:6473597d706e 6080 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
bogdanm 82:6473597d706e 6081 } FTM_Type, *FTM_MemMapPtr;
bogdanm 82:6473597d706e 6082
bogdanm 82:6473597d706e 6083 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6084 -- FTM - Register accessor macros
bogdanm 82:6473597d706e 6085 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6086
bogdanm 82:6473597d706e 6087 /*!
bogdanm 82:6473597d706e 6088 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
bogdanm 82:6473597d706e 6089 * @{
bogdanm 82:6473597d706e 6090 */
bogdanm 82:6473597d706e 6091
bogdanm 82:6473597d706e 6092
bogdanm 82:6473597d706e 6093 /* FTM - Register accessors */
bogdanm 82:6473597d706e 6094 #define FTM_SC_REG(base) ((base)->SC)
bogdanm 82:6473597d706e 6095 #define FTM_CNT_REG(base) ((base)->CNT)
bogdanm 82:6473597d706e 6096 #define FTM_MOD_REG(base) ((base)->MOD)
bogdanm 82:6473597d706e 6097 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
bogdanm 82:6473597d706e 6098 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
bogdanm 82:6473597d706e 6099 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
bogdanm 82:6473597d706e 6100 #define FTM_STATUS_REG(base) ((base)->STATUS)
bogdanm 82:6473597d706e 6101 #define FTM_MODE_REG(base) ((base)->MODE)
bogdanm 82:6473597d706e 6102 #define FTM_SYNC_REG(base) ((base)->SYNC)
bogdanm 82:6473597d706e 6103 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
bogdanm 82:6473597d706e 6104 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
bogdanm 82:6473597d706e 6105 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
bogdanm 82:6473597d706e 6106 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
bogdanm 82:6473597d706e 6107 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
bogdanm 82:6473597d706e 6108 #define FTM_POL_REG(base) ((base)->POL)
bogdanm 82:6473597d706e 6109 #define FTM_FMS_REG(base) ((base)->FMS)
bogdanm 82:6473597d706e 6110 #define FTM_FILTER_REG(base) ((base)->FILTER)
bogdanm 82:6473597d706e 6111 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
bogdanm 82:6473597d706e 6112 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
bogdanm 82:6473597d706e 6113 #define FTM_CONF_REG(base) ((base)->CONF)
bogdanm 82:6473597d706e 6114 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
bogdanm 82:6473597d706e 6115 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
bogdanm 82:6473597d706e 6116 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
bogdanm 82:6473597d706e 6117 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
bogdanm 82:6473597d706e 6118 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
bogdanm 82:6473597d706e 6119
bogdanm 82:6473597d706e 6120 /*!
bogdanm 82:6473597d706e 6121 * @}
bogdanm 82:6473597d706e 6122 */ /* end of group FTM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 6123
bogdanm 82:6473597d706e 6124
bogdanm 82:6473597d706e 6125 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6126 -- FTM Register Masks
bogdanm 82:6473597d706e 6127 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6128
bogdanm 82:6473597d706e 6129 /*!
bogdanm 82:6473597d706e 6130 * @addtogroup FTM_Register_Masks FTM Register Masks
bogdanm 82:6473597d706e 6131 * @{
bogdanm 82:6473597d706e 6132 */
bogdanm 82:6473597d706e 6133
bogdanm 82:6473597d706e 6134 /* SC Bit Fields */
bogdanm 82:6473597d706e 6135 #define FTM_SC_PS_MASK 0x7u
bogdanm 82:6473597d706e 6136 #define FTM_SC_PS_SHIFT 0
bogdanm 82:6473597d706e 6137 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
bogdanm 82:6473597d706e 6138 #define FTM_SC_CLKS_MASK 0x18u
bogdanm 82:6473597d706e 6139 #define FTM_SC_CLKS_SHIFT 3
bogdanm 82:6473597d706e 6140 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
bogdanm 82:6473597d706e 6141 #define FTM_SC_CPWMS_MASK 0x20u
bogdanm 82:6473597d706e 6142 #define FTM_SC_CPWMS_SHIFT 5
bogdanm 82:6473597d706e 6143 #define FTM_SC_TOIE_MASK 0x40u
bogdanm 82:6473597d706e 6144 #define FTM_SC_TOIE_SHIFT 6
bogdanm 82:6473597d706e 6145 #define FTM_SC_TOF_MASK 0x80u
bogdanm 82:6473597d706e 6146 #define FTM_SC_TOF_SHIFT 7
bogdanm 82:6473597d706e 6147 /* CNT Bit Fields */
bogdanm 82:6473597d706e 6148 #define FTM_CNT_COUNT_MASK 0xFFFFu
bogdanm 82:6473597d706e 6149 #define FTM_CNT_COUNT_SHIFT 0
bogdanm 82:6473597d706e 6150 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
bogdanm 82:6473597d706e 6151 /* MOD Bit Fields */
bogdanm 82:6473597d706e 6152 #define FTM_MOD_MOD_MASK 0xFFFFu
bogdanm 82:6473597d706e 6153 #define FTM_MOD_MOD_SHIFT 0
bogdanm 82:6473597d706e 6154 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
bogdanm 82:6473597d706e 6155 /* CnSC Bit Fields */
bogdanm 82:6473597d706e 6156 #define FTM_CnSC_DMA_MASK 0x1u
bogdanm 82:6473597d706e 6157 #define FTM_CnSC_DMA_SHIFT 0
bogdanm 82:6473597d706e 6158 #define FTM_CnSC_ELSA_MASK 0x4u
bogdanm 82:6473597d706e 6159 #define FTM_CnSC_ELSA_SHIFT 2
bogdanm 82:6473597d706e 6160 #define FTM_CnSC_ELSB_MASK 0x8u
bogdanm 82:6473597d706e 6161 #define FTM_CnSC_ELSB_SHIFT 3
bogdanm 82:6473597d706e 6162 #define FTM_CnSC_MSA_MASK 0x10u
bogdanm 82:6473597d706e 6163 #define FTM_CnSC_MSA_SHIFT 4
bogdanm 82:6473597d706e 6164 #define FTM_CnSC_MSB_MASK 0x20u
bogdanm 82:6473597d706e 6165 #define FTM_CnSC_MSB_SHIFT 5
bogdanm 82:6473597d706e 6166 #define FTM_CnSC_CHIE_MASK 0x40u
bogdanm 82:6473597d706e 6167 #define FTM_CnSC_CHIE_SHIFT 6
bogdanm 82:6473597d706e 6168 #define FTM_CnSC_CHF_MASK 0x80u
bogdanm 82:6473597d706e 6169 #define FTM_CnSC_CHF_SHIFT 7
bogdanm 82:6473597d706e 6170 /* CnV Bit Fields */
bogdanm 82:6473597d706e 6171 #define FTM_CnV_VAL_MASK 0xFFFFu
bogdanm 82:6473597d706e 6172 #define FTM_CnV_VAL_SHIFT 0
bogdanm 82:6473597d706e 6173 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
bogdanm 82:6473597d706e 6174 /* CNTIN Bit Fields */
bogdanm 82:6473597d706e 6175 #define FTM_CNTIN_INIT_MASK 0xFFFFu
bogdanm 82:6473597d706e 6176 #define FTM_CNTIN_INIT_SHIFT 0
bogdanm 82:6473597d706e 6177 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
bogdanm 82:6473597d706e 6178 /* STATUS Bit Fields */
bogdanm 82:6473597d706e 6179 #define FTM_STATUS_CH0F_MASK 0x1u
bogdanm 82:6473597d706e 6180 #define FTM_STATUS_CH0F_SHIFT 0
bogdanm 82:6473597d706e 6181 #define FTM_STATUS_CH1F_MASK 0x2u
bogdanm 82:6473597d706e 6182 #define FTM_STATUS_CH1F_SHIFT 1
bogdanm 82:6473597d706e 6183 #define FTM_STATUS_CH2F_MASK 0x4u
bogdanm 82:6473597d706e 6184 #define FTM_STATUS_CH2F_SHIFT 2
bogdanm 82:6473597d706e 6185 #define FTM_STATUS_CH3F_MASK 0x8u
bogdanm 82:6473597d706e 6186 #define FTM_STATUS_CH3F_SHIFT 3
bogdanm 82:6473597d706e 6187 #define FTM_STATUS_CH4F_MASK 0x10u
bogdanm 82:6473597d706e 6188 #define FTM_STATUS_CH4F_SHIFT 4
bogdanm 82:6473597d706e 6189 #define FTM_STATUS_CH5F_MASK 0x20u
bogdanm 82:6473597d706e 6190 #define FTM_STATUS_CH5F_SHIFT 5
bogdanm 82:6473597d706e 6191 #define FTM_STATUS_CH6F_MASK 0x40u
bogdanm 82:6473597d706e 6192 #define FTM_STATUS_CH6F_SHIFT 6
bogdanm 82:6473597d706e 6193 #define FTM_STATUS_CH7F_MASK 0x80u
bogdanm 82:6473597d706e 6194 #define FTM_STATUS_CH7F_SHIFT 7
bogdanm 82:6473597d706e 6195 /* MODE Bit Fields */
bogdanm 82:6473597d706e 6196 #define FTM_MODE_FTMEN_MASK 0x1u
bogdanm 82:6473597d706e 6197 #define FTM_MODE_FTMEN_SHIFT 0
bogdanm 82:6473597d706e 6198 #define FTM_MODE_INIT_MASK 0x2u
bogdanm 82:6473597d706e 6199 #define FTM_MODE_INIT_SHIFT 1
bogdanm 82:6473597d706e 6200 #define FTM_MODE_WPDIS_MASK 0x4u
bogdanm 82:6473597d706e 6201 #define FTM_MODE_WPDIS_SHIFT 2
bogdanm 82:6473597d706e 6202 #define FTM_MODE_PWMSYNC_MASK 0x8u
bogdanm 82:6473597d706e 6203 #define FTM_MODE_PWMSYNC_SHIFT 3
bogdanm 82:6473597d706e 6204 #define FTM_MODE_CAPTEST_MASK 0x10u
bogdanm 82:6473597d706e 6205 #define FTM_MODE_CAPTEST_SHIFT 4
bogdanm 82:6473597d706e 6206 #define FTM_MODE_FAULTM_MASK 0x60u
bogdanm 82:6473597d706e 6207 #define FTM_MODE_FAULTM_SHIFT 5
bogdanm 82:6473597d706e 6208 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
bogdanm 82:6473597d706e 6209 #define FTM_MODE_FAULTIE_MASK 0x80u
bogdanm 82:6473597d706e 6210 #define FTM_MODE_FAULTIE_SHIFT 7
bogdanm 82:6473597d706e 6211 /* SYNC Bit Fields */
bogdanm 82:6473597d706e 6212 #define FTM_SYNC_CNTMIN_MASK 0x1u
bogdanm 82:6473597d706e 6213 #define FTM_SYNC_CNTMIN_SHIFT 0
bogdanm 82:6473597d706e 6214 #define FTM_SYNC_CNTMAX_MASK 0x2u
bogdanm 82:6473597d706e 6215 #define FTM_SYNC_CNTMAX_SHIFT 1
bogdanm 82:6473597d706e 6216 #define FTM_SYNC_REINIT_MASK 0x4u
bogdanm 82:6473597d706e 6217 #define FTM_SYNC_REINIT_SHIFT 2
bogdanm 82:6473597d706e 6218 #define FTM_SYNC_SYNCHOM_MASK 0x8u
bogdanm 82:6473597d706e 6219 #define FTM_SYNC_SYNCHOM_SHIFT 3
bogdanm 82:6473597d706e 6220 #define FTM_SYNC_TRIG0_MASK 0x10u
bogdanm 82:6473597d706e 6221 #define FTM_SYNC_TRIG0_SHIFT 4
bogdanm 82:6473597d706e 6222 #define FTM_SYNC_TRIG1_MASK 0x20u
bogdanm 82:6473597d706e 6223 #define FTM_SYNC_TRIG1_SHIFT 5
bogdanm 82:6473597d706e 6224 #define FTM_SYNC_TRIG2_MASK 0x40u
bogdanm 82:6473597d706e 6225 #define FTM_SYNC_TRIG2_SHIFT 6
bogdanm 82:6473597d706e 6226 #define FTM_SYNC_SWSYNC_MASK 0x80u
bogdanm 82:6473597d706e 6227 #define FTM_SYNC_SWSYNC_SHIFT 7
bogdanm 82:6473597d706e 6228 /* OUTINIT Bit Fields */
bogdanm 82:6473597d706e 6229 #define FTM_OUTINIT_CH0OI_MASK 0x1u
bogdanm 82:6473597d706e 6230 #define FTM_OUTINIT_CH0OI_SHIFT 0
bogdanm 82:6473597d706e 6231 #define FTM_OUTINIT_CH1OI_MASK 0x2u
bogdanm 82:6473597d706e 6232 #define FTM_OUTINIT_CH1OI_SHIFT 1
bogdanm 82:6473597d706e 6233 #define FTM_OUTINIT_CH2OI_MASK 0x4u
bogdanm 82:6473597d706e 6234 #define FTM_OUTINIT_CH2OI_SHIFT 2
bogdanm 82:6473597d706e 6235 #define FTM_OUTINIT_CH3OI_MASK 0x8u
bogdanm 82:6473597d706e 6236 #define FTM_OUTINIT_CH3OI_SHIFT 3
bogdanm 82:6473597d706e 6237 #define FTM_OUTINIT_CH4OI_MASK 0x10u
bogdanm 82:6473597d706e 6238 #define FTM_OUTINIT_CH4OI_SHIFT 4
bogdanm 82:6473597d706e 6239 #define FTM_OUTINIT_CH5OI_MASK 0x20u
bogdanm 82:6473597d706e 6240 #define FTM_OUTINIT_CH5OI_SHIFT 5
bogdanm 82:6473597d706e 6241 #define FTM_OUTINIT_CH6OI_MASK 0x40u
bogdanm 82:6473597d706e 6242 #define FTM_OUTINIT_CH6OI_SHIFT 6
bogdanm 82:6473597d706e 6243 #define FTM_OUTINIT_CH7OI_MASK 0x80u
bogdanm 82:6473597d706e 6244 #define FTM_OUTINIT_CH7OI_SHIFT 7
bogdanm 82:6473597d706e 6245 /* OUTMASK Bit Fields */
bogdanm 82:6473597d706e 6246 #define FTM_OUTMASK_CH0OM_MASK 0x1u
bogdanm 82:6473597d706e 6247 #define FTM_OUTMASK_CH0OM_SHIFT 0
bogdanm 82:6473597d706e 6248 #define FTM_OUTMASK_CH1OM_MASK 0x2u
bogdanm 82:6473597d706e 6249 #define FTM_OUTMASK_CH1OM_SHIFT 1
bogdanm 82:6473597d706e 6250 #define FTM_OUTMASK_CH2OM_MASK 0x4u
bogdanm 82:6473597d706e 6251 #define FTM_OUTMASK_CH2OM_SHIFT 2
bogdanm 82:6473597d706e 6252 #define FTM_OUTMASK_CH3OM_MASK 0x8u
bogdanm 82:6473597d706e 6253 #define FTM_OUTMASK_CH3OM_SHIFT 3
bogdanm 82:6473597d706e 6254 #define FTM_OUTMASK_CH4OM_MASK 0x10u
bogdanm 82:6473597d706e 6255 #define FTM_OUTMASK_CH4OM_SHIFT 4
bogdanm 82:6473597d706e 6256 #define FTM_OUTMASK_CH5OM_MASK 0x20u
bogdanm 82:6473597d706e 6257 #define FTM_OUTMASK_CH5OM_SHIFT 5
bogdanm 82:6473597d706e 6258 #define FTM_OUTMASK_CH6OM_MASK 0x40u
bogdanm 82:6473597d706e 6259 #define FTM_OUTMASK_CH6OM_SHIFT 6
bogdanm 82:6473597d706e 6260 #define FTM_OUTMASK_CH7OM_MASK 0x80u
bogdanm 82:6473597d706e 6261 #define FTM_OUTMASK_CH7OM_SHIFT 7
bogdanm 82:6473597d706e 6262 /* COMBINE Bit Fields */
bogdanm 82:6473597d706e 6263 #define FTM_COMBINE_COMBINE0_MASK 0x1u
bogdanm 82:6473597d706e 6264 #define FTM_COMBINE_COMBINE0_SHIFT 0
bogdanm 82:6473597d706e 6265 #define FTM_COMBINE_COMP0_MASK 0x2u
bogdanm 82:6473597d706e 6266 #define FTM_COMBINE_COMP0_SHIFT 1
bogdanm 82:6473597d706e 6267 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
bogdanm 82:6473597d706e 6268 #define FTM_COMBINE_DECAPEN0_SHIFT 2
bogdanm 82:6473597d706e 6269 #define FTM_COMBINE_DECAP0_MASK 0x8u
bogdanm 82:6473597d706e 6270 #define FTM_COMBINE_DECAP0_SHIFT 3
bogdanm 82:6473597d706e 6271 #define FTM_COMBINE_DTEN0_MASK 0x10u
bogdanm 82:6473597d706e 6272 #define FTM_COMBINE_DTEN0_SHIFT 4
bogdanm 82:6473597d706e 6273 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
bogdanm 82:6473597d706e 6274 #define FTM_COMBINE_SYNCEN0_SHIFT 5
bogdanm 82:6473597d706e 6275 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
bogdanm 82:6473597d706e 6276 #define FTM_COMBINE_FAULTEN0_SHIFT 6
bogdanm 82:6473597d706e 6277 #define FTM_COMBINE_COMBINE1_MASK 0x100u
bogdanm 82:6473597d706e 6278 #define FTM_COMBINE_COMBINE1_SHIFT 8
bogdanm 82:6473597d706e 6279 #define FTM_COMBINE_COMP1_MASK 0x200u
bogdanm 82:6473597d706e 6280 #define FTM_COMBINE_COMP1_SHIFT 9
bogdanm 82:6473597d706e 6281 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
bogdanm 82:6473597d706e 6282 #define FTM_COMBINE_DECAPEN1_SHIFT 10
bogdanm 82:6473597d706e 6283 #define FTM_COMBINE_DECAP1_MASK 0x800u
bogdanm 82:6473597d706e 6284 #define FTM_COMBINE_DECAP1_SHIFT 11
bogdanm 82:6473597d706e 6285 #define FTM_COMBINE_DTEN1_MASK 0x1000u
bogdanm 82:6473597d706e 6286 #define FTM_COMBINE_DTEN1_SHIFT 12
bogdanm 82:6473597d706e 6287 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
bogdanm 82:6473597d706e 6288 #define FTM_COMBINE_SYNCEN1_SHIFT 13
bogdanm 82:6473597d706e 6289 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
bogdanm 82:6473597d706e 6290 #define FTM_COMBINE_FAULTEN1_SHIFT 14
bogdanm 82:6473597d706e 6291 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
bogdanm 82:6473597d706e 6292 #define FTM_COMBINE_COMBINE2_SHIFT 16
bogdanm 82:6473597d706e 6293 #define FTM_COMBINE_COMP2_MASK 0x20000u
bogdanm 82:6473597d706e 6294 #define FTM_COMBINE_COMP2_SHIFT 17
bogdanm 82:6473597d706e 6295 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
bogdanm 82:6473597d706e 6296 #define FTM_COMBINE_DECAPEN2_SHIFT 18
bogdanm 82:6473597d706e 6297 #define FTM_COMBINE_DECAP2_MASK 0x80000u
bogdanm 82:6473597d706e 6298 #define FTM_COMBINE_DECAP2_SHIFT 19
bogdanm 82:6473597d706e 6299 #define FTM_COMBINE_DTEN2_MASK 0x100000u
bogdanm 82:6473597d706e 6300 #define FTM_COMBINE_DTEN2_SHIFT 20
bogdanm 82:6473597d706e 6301 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
bogdanm 82:6473597d706e 6302 #define FTM_COMBINE_SYNCEN2_SHIFT 21
bogdanm 82:6473597d706e 6303 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
bogdanm 82:6473597d706e 6304 #define FTM_COMBINE_FAULTEN2_SHIFT 22
bogdanm 82:6473597d706e 6305 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
bogdanm 82:6473597d706e 6306 #define FTM_COMBINE_COMBINE3_SHIFT 24
bogdanm 82:6473597d706e 6307 #define FTM_COMBINE_COMP3_MASK 0x2000000u
bogdanm 82:6473597d706e 6308 #define FTM_COMBINE_COMP3_SHIFT 25
bogdanm 82:6473597d706e 6309 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
bogdanm 82:6473597d706e 6310 #define FTM_COMBINE_DECAPEN3_SHIFT 26
bogdanm 82:6473597d706e 6311 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
bogdanm 82:6473597d706e 6312 #define FTM_COMBINE_DECAP3_SHIFT 27
bogdanm 82:6473597d706e 6313 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
bogdanm 82:6473597d706e 6314 #define FTM_COMBINE_DTEN3_SHIFT 28
bogdanm 82:6473597d706e 6315 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
bogdanm 82:6473597d706e 6316 #define FTM_COMBINE_SYNCEN3_SHIFT 29
bogdanm 82:6473597d706e 6317 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
bogdanm 82:6473597d706e 6318 #define FTM_COMBINE_FAULTEN3_SHIFT 30
bogdanm 82:6473597d706e 6319 /* DEADTIME Bit Fields */
bogdanm 82:6473597d706e 6320 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
bogdanm 82:6473597d706e 6321 #define FTM_DEADTIME_DTVAL_SHIFT 0
bogdanm 82:6473597d706e 6322 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
bogdanm 82:6473597d706e 6323 #define FTM_DEADTIME_DTPS_MASK 0xC0u
bogdanm 82:6473597d706e 6324 #define FTM_DEADTIME_DTPS_SHIFT 6
bogdanm 82:6473597d706e 6325 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
bogdanm 82:6473597d706e 6326 /* EXTTRIG Bit Fields */
bogdanm 82:6473597d706e 6327 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
bogdanm 82:6473597d706e 6328 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
bogdanm 82:6473597d706e 6329 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
bogdanm 82:6473597d706e 6330 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
bogdanm 82:6473597d706e 6331 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
bogdanm 82:6473597d706e 6332 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
bogdanm 82:6473597d706e 6333 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
bogdanm 82:6473597d706e 6334 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
bogdanm 82:6473597d706e 6335 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
bogdanm 82:6473597d706e 6336 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
bogdanm 82:6473597d706e 6337 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
bogdanm 82:6473597d706e 6338 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
bogdanm 82:6473597d706e 6339 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
bogdanm 82:6473597d706e 6340 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
bogdanm 82:6473597d706e 6341 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
bogdanm 82:6473597d706e 6342 #define FTM_EXTTRIG_TRIGF_SHIFT 7
bogdanm 82:6473597d706e 6343 /* POL Bit Fields */
bogdanm 82:6473597d706e 6344 #define FTM_POL_POL0_MASK 0x1u
bogdanm 82:6473597d706e 6345 #define FTM_POL_POL0_SHIFT 0
bogdanm 82:6473597d706e 6346 #define FTM_POL_POL1_MASK 0x2u
bogdanm 82:6473597d706e 6347 #define FTM_POL_POL1_SHIFT 1
bogdanm 82:6473597d706e 6348 #define FTM_POL_POL2_MASK 0x4u
bogdanm 82:6473597d706e 6349 #define FTM_POL_POL2_SHIFT 2
bogdanm 82:6473597d706e 6350 #define FTM_POL_POL3_MASK 0x8u
bogdanm 82:6473597d706e 6351 #define FTM_POL_POL3_SHIFT 3
bogdanm 82:6473597d706e 6352 #define FTM_POL_POL4_MASK 0x10u
bogdanm 82:6473597d706e 6353 #define FTM_POL_POL4_SHIFT 4
bogdanm 82:6473597d706e 6354 #define FTM_POL_POL5_MASK 0x20u
bogdanm 82:6473597d706e 6355 #define FTM_POL_POL5_SHIFT 5
bogdanm 82:6473597d706e 6356 #define FTM_POL_POL6_MASK 0x40u
bogdanm 82:6473597d706e 6357 #define FTM_POL_POL6_SHIFT 6
bogdanm 82:6473597d706e 6358 #define FTM_POL_POL7_MASK 0x80u
bogdanm 82:6473597d706e 6359 #define FTM_POL_POL7_SHIFT 7
bogdanm 82:6473597d706e 6360 /* FMS Bit Fields */
bogdanm 82:6473597d706e 6361 #define FTM_FMS_FAULTF0_MASK 0x1u
bogdanm 82:6473597d706e 6362 #define FTM_FMS_FAULTF0_SHIFT 0
bogdanm 82:6473597d706e 6363 #define FTM_FMS_FAULTF1_MASK 0x2u
bogdanm 82:6473597d706e 6364 #define FTM_FMS_FAULTF1_SHIFT 1
bogdanm 82:6473597d706e 6365 #define FTM_FMS_FAULTF2_MASK 0x4u
bogdanm 82:6473597d706e 6366 #define FTM_FMS_FAULTF2_SHIFT 2
bogdanm 82:6473597d706e 6367 #define FTM_FMS_FAULTF3_MASK 0x8u
bogdanm 82:6473597d706e 6368 #define FTM_FMS_FAULTF3_SHIFT 3
bogdanm 82:6473597d706e 6369 #define FTM_FMS_FAULTIN_MASK 0x20u
bogdanm 82:6473597d706e 6370 #define FTM_FMS_FAULTIN_SHIFT 5
bogdanm 82:6473597d706e 6371 #define FTM_FMS_WPEN_MASK 0x40u
bogdanm 82:6473597d706e 6372 #define FTM_FMS_WPEN_SHIFT 6
bogdanm 82:6473597d706e 6373 #define FTM_FMS_FAULTF_MASK 0x80u
bogdanm 82:6473597d706e 6374 #define FTM_FMS_FAULTF_SHIFT 7
bogdanm 82:6473597d706e 6375 /* FILTER Bit Fields */
bogdanm 82:6473597d706e 6376 #define FTM_FILTER_CH0FVAL_MASK 0xFu
bogdanm 82:6473597d706e 6377 #define FTM_FILTER_CH0FVAL_SHIFT 0
bogdanm 82:6473597d706e 6378 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
bogdanm 82:6473597d706e 6379 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
bogdanm 82:6473597d706e 6380 #define FTM_FILTER_CH1FVAL_SHIFT 4
bogdanm 82:6473597d706e 6381 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
bogdanm 82:6473597d706e 6382 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
bogdanm 82:6473597d706e 6383 #define FTM_FILTER_CH2FVAL_SHIFT 8
bogdanm 82:6473597d706e 6384 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
bogdanm 82:6473597d706e 6385 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
bogdanm 82:6473597d706e 6386 #define FTM_FILTER_CH3FVAL_SHIFT 12
bogdanm 82:6473597d706e 6387 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
bogdanm 82:6473597d706e 6388 /* FLTCTRL Bit Fields */
bogdanm 82:6473597d706e 6389 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
bogdanm 82:6473597d706e 6390 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
bogdanm 82:6473597d706e 6391 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
bogdanm 82:6473597d706e 6392 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
bogdanm 82:6473597d706e 6393 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
bogdanm 82:6473597d706e 6394 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
bogdanm 82:6473597d706e 6395 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
bogdanm 82:6473597d706e 6396 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
bogdanm 82:6473597d706e 6397 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
bogdanm 82:6473597d706e 6398 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
bogdanm 82:6473597d706e 6399 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
bogdanm 82:6473597d706e 6400 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
bogdanm 82:6473597d706e 6401 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
bogdanm 82:6473597d706e 6402 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
bogdanm 82:6473597d706e 6403 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
bogdanm 82:6473597d706e 6404 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
bogdanm 82:6473597d706e 6405 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
bogdanm 82:6473597d706e 6406 #define FTM_FLTCTRL_FFVAL_SHIFT 8
bogdanm 82:6473597d706e 6407 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
bogdanm 82:6473597d706e 6408 /* QDCTRL Bit Fields */
bogdanm 82:6473597d706e 6409 #define FTM_QDCTRL_QUADEN_MASK 0x1u
bogdanm 82:6473597d706e 6410 #define FTM_QDCTRL_QUADEN_SHIFT 0
bogdanm 82:6473597d706e 6411 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
bogdanm 82:6473597d706e 6412 #define FTM_QDCTRL_TOFDIR_SHIFT 1
bogdanm 82:6473597d706e 6413 #define FTM_QDCTRL_QUADIR_MASK 0x4u
bogdanm 82:6473597d706e 6414 #define FTM_QDCTRL_QUADIR_SHIFT 2
bogdanm 82:6473597d706e 6415 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
bogdanm 82:6473597d706e 6416 #define FTM_QDCTRL_QUADMODE_SHIFT 3
bogdanm 82:6473597d706e 6417 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
bogdanm 82:6473597d706e 6418 #define FTM_QDCTRL_PHBPOL_SHIFT 4
bogdanm 82:6473597d706e 6419 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
bogdanm 82:6473597d706e 6420 #define FTM_QDCTRL_PHAPOL_SHIFT 5
bogdanm 82:6473597d706e 6421 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
bogdanm 82:6473597d706e 6422 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
bogdanm 82:6473597d706e 6423 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
bogdanm 82:6473597d706e 6424 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
bogdanm 82:6473597d706e 6425 /* CONF Bit Fields */
bogdanm 82:6473597d706e 6426 #define FTM_CONF_NUMTOF_MASK 0x1Fu
bogdanm 82:6473597d706e 6427 #define FTM_CONF_NUMTOF_SHIFT 0
bogdanm 82:6473597d706e 6428 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
bogdanm 82:6473597d706e 6429 #define FTM_CONF_BDMMODE_MASK 0xC0u
bogdanm 82:6473597d706e 6430 #define FTM_CONF_BDMMODE_SHIFT 6
bogdanm 82:6473597d706e 6431 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
bogdanm 82:6473597d706e 6432 #define FTM_CONF_GTBEEN_MASK 0x200u
bogdanm 82:6473597d706e 6433 #define FTM_CONF_GTBEEN_SHIFT 9
bogdanm 82:6473597d706e 6434 #define FTM_CONF_GTBEOUT_MASK 0x400u
bogdanm 82:6473597d706e 6435 #define FTM_CONF_GTBEOUT_SHIFT 10
bogdanm 82:6473597d706e 6436 /* FLTPOL Bit Fields */
bogdanm 82:6473597d706e 6437 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
bogdanm 82:6473597d706e 6438 #define FTM_FLTPOL_FLT0POL_SHIFT 0
bogdanm 82:6473597d706e 6439 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
bogdanm 82:6473597d706e 6440 #define FTM_FLTPOL_FLT1POL_SHIFT 1
bogdanm 82:6473597d706e 6441 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
bogdanm 82:6473597d706e 6442 #define FTM_FLTPOL_FLT2POL_SHIFT 2
bogdanm 82:6473597d706e 6443 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
bogdanm 82:6473597d706e 6444 #define FTM_FLTPOL_FLT3POL_SHIFT 3
bogdanm 82:6473597d706e 6445 /* SYNCONF Bit Fields */
bogdanm 82:6473597d706e 6446 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
bogdanm 82:6473597d706e 6447 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
bogdanm 82:6473597d706e 6448 #define FTM_SYNCONF_CNTINC_MASK 0x4u
bogdanm 82:6473597d706e 6449 #define FTM_SYNCONF_CNTINC_SHIFT 2
bogdanm 82:6473597d706e 6450 #define FTM_SYNCONF_INVC_MASK 0x10u
bogdanm 82:6473597d706e 6451 #define FTM_SYNCONF_INVC_SHIFT 4
bogdanm 82:6473597d706e 6452 #define FTM_SYNCONF_SWOC_MASK 0x20u
bogdanm 82:6473597d706e 6453 #define FTM_SYNCONF_SWOC_SHIFT 5
bogdanm 82:6473597d706e 6454 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
bogdanm 82:6473597d706e 6455 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
bogdanm 82:6473597d706e 6456 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
bogdanm 82:6473597d706e 6457 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
bogdanm 82:6473597d706e 6458 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
bogdanm 82:6473597d706e 6459 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
bogdanm 82:6473597d706e 6460 #define FTM_SYNCONF_SWOM_MASK 0x400u
bogdanm 82:6473597d706e 6461 #define FTM_SYNCONF_SWOM_SHIFT 10
bogdanm 82:6473597d706e 6462 #define FTM_SYNCONF_SWINVC_MASK 0x800u
bogdanm 82:6473597d706e 6463 #define FTM_SYNCONF_SWINVC_SHIFT 11
bogdanm 82:6473597d706e 6464 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
bogdanm 82:6473597d706e 6465 #define FTM_SYNCONF_SWSOC_SHIFT 12
bogdanm 82:6473597d706e 6466 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
bogdanm 82:6473597d706e 6467 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
bogdanm 82:6473597d706e 6468 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
bogdanm 82:6473597d706e 6469 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
bogdanm 82:6473597d706e 6470 #define FTM_SYNCONF_HWOM_MASK 0x40000u
bogdanm 82:6473597d706e 6471 #define FTM_SYNCONF_HWOM_SHIFT 18
bogdanm 82:6473597d706e 6472 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
bogdanm 82:6473597d706e 6473 #define FTM_SYNCONF_HWINVC_SHIFT 19
bogdanm 82:6473597d706e 6474 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
bogdanm 82:6473597d706e 6475 #define FTM_SYNCONF_HWSOC_SHIFT 20
bogdanm 82:6473597d706e 6476 /* INVCTRL Bit Fields */
bogdanm 82:6473597d706e 6477 #define FTM_INVCTRL_INV0EN_MASK 0x1u
bogdanm 82:6473597d706e 6478 #define FTM_INVCTRL_INV0EN_SHIFT 0
bogdanm 82:6473597d706e 6479 #define FTM_INVCTRL_INV1EN_MASK 0x2u
bogdanm 82:6473597d706e 6480 #define FTM_INVCTRL_INV1EN_SHIFT 1
bogdanm 82:6473597d706e 6481 #define FTM_INVCTRL_INV2EN_MASK 0x4u
bogdanm 82:6473597d706e 6482 #define FTM_INVCTRL_INV2EN_SHIFT 2
bogdanm 82:6473597d706e 6483 #define FTM_INVCTRL_INV3EN_MASK 0x8u
bogdanm 82:6473597d706e 6484 #define FTM_INVCTRL_INV3EN_SHIFT 3
bogdanm 82:6473597d706e 6485 /* SWOCTRL Bit Fields */
bogdanm 82:6473597d706e 6486 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
bogdanm 82:6473597d706e 6487 #define FTM_SWOCTRL_CH0OC_SHIFT 0
bogdanm 82:6473597d706e 6488 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
bogdanm 82:6473597d706e 6489 #define FTM_SWOCTRL_CH1OC_SHIFT 1
bogdanm 82:6473597d706e 6490 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
bogdanm 82:6473597d706e 6491 #define FTM_SWOCTRL_CH2OC_SHIFT 2
bogdanm 82:6473597d706e 6492 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
bogdanm 82:6473597d706e 6493 #define FTM_SWOCTRL_CH3OC_SHIFT 3
bogdanm 82:6473597d706e 6494 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
bogdanm 82:6473597d706e 6495 #define FTM_SWOCTRL_CH4OC_SHIFT 4
bogdanm 82:6473597d706e 6496 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
bogdanm 82:6473597d706e 6497 #define FTM_SWOCTRL_CH5OC_SHIFT 5
bogdanm 82:6473597d706e 6498 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
bogdanm 82:6473597d706e 6499 #define FTM_SWOCTRL_CH6OC_SHIFT 6
bogdanm 82:6473597d706e 6500 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
bogdanm 82:6473597d706e 6501 #define FTM_SWOCTRL_CH7OC_SHIFT 7
bogdanm 82:6473597d706e 6502 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
bogdanm 82:6473597d706e 6503 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
bogdanm 82:6473597d706e 6504 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
bogdanm 82:6473597d706e 6505 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
bogdanm 82:6473597d706e 6506 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
bogdanm 82:6473597d706e 6507 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
bogdanm 82:6473597d706e 6508 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
bogdanm 82:6473597d706e 6509 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
bogdanm 82:6473597d706e 6510 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
bogdanm 82:6473597d706e 6511 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
bogdanm 82:6473597d706e 6512 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
bogdanm 82:6473597d706e 6513 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
bogdanm 82:6473597d706e 6514 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
bogdanm 82:6473597d706e 6515 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
bogdanm 82:6473597d706e 6516 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
bogdanm 82:6473597d706e 6517 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
bogdanm 82:6473597d706e 6518 /* PWMLOAD Bit Fields */
bogdanm 82:6473597d706e 6519 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
bogdanm 82:6473597d706e 6520 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
bogdanm 82:6473597d706e 6521 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
bogdanm 82:6473597d706e 6522 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
bogdanm 82:6473597d706e 6523 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
bogdanm 82:6473597d706e 6524 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
bogdanm 82:6473597d706e 6525 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
bogdanm 82:6473597d706e 6526 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
bogdanm 82:6473597d706e 6527 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
bogdanm 82:6473597d706e 6528 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
bogdanm 82:6473597d706e 6529 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
bogdanm 82:6473597d706e 6530 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
bogdanm 82:6473597d706e 6531 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
bogdanm 82:6473597d706e 6532 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
bogdanm 82:6473597d706e 6533 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
bogdanm 82:6473597d706e 6534 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
bogdanm 82:6473597d706e 6535 #define FTM_PWMLOAD_LDOK_MASK 0x200u
bogdanm 82:6473597d706e 6536 #define FTM_PWMLOAD_LDOK_SHIFT 9
bogdanm 82:6473597d706e 6537
bogdanm 82:6473597d706e 6538 /*!
bogdanm 82:6473597d706e 6539 * @}
bogdanm 82:6473597d706e 6540 */ /* end of group FTM_Register_Masks */
bogdanm 82:6473597d706e 6541
bogdanm 82:6473597d706e 6542
bogdanm 82:6473597d706e 6543 /* FTM - Peripheral instance base addresses */
bogdanm 82:6473597d706e 6544 /** Peripheral FTM0 base address */
bogdanm 82:6473597d706e 6545 #define FTM0_BASE (0x40038000u)
bogdanm 82:6473597d706e 6546 /** Peripheral FTM0 base pointer */
bogdanm 82:6473597d706e 6547 #define FTM0 ((FTM_Type *)FTM0_BASE)
bogdanm 82:6473597d706e 6548 #define FTM0_BASE_PTR (FTM0)
bogdanm 82:6473597d706e 6549 /** Peripheral FTM1 base address */
bogdanm 82:6473597d706e 6550 #define FTM1_BASE (0x40039000u)
bogdanm 82:6473597d706e 6551 /** Peripheral FTM1 base pointer */
bogdanm 82:6473597d706e 6552 #define FTM1 ((FTM_Type *)FTM1_BASE)
bogdanm 82:6473597d706e 6553 #define FTM1_BASE_PTR (FTM1)
bogdanm 82:6473597d706e 6554 /** Peripheral FTM2 base address */
bogdanm 82:6473597d706e 6555 #define FTM2_BASE (0x4003A000u)
bogdanm 82:6473597d706e 6556 /** Peripheral FTM2 base pointer */
bogdanm 82:6473597d706e 6557 #define FTM2 ((FTM_Type *)FTM2_BASE)
bogdanm 82:6473597d706e 6558 #define FTM2_BASE_PTR (FTM2)
bogdanm 82:6473597d706e 6559 /** Peripheral FTM3 base address */
bogdanm 82:6473597d706e 6560 #define FTM3_BASE (0x400B9000u)
bogdanm 82:6473597d706e 6561 /** Peripheral FTM3 base pointer */
bogdanm 82:6473597d706e 6562 #define FTM3 ((FTM_Type *)FTM3_BASE)
bogdanm 82:6473597d706e 6563 #define FTM3_BASE_PTR (FTM3)
bogdanm 82:6473597d706e 6564 /** Array initializer of FTM peripheral base pointers */
bogdanm 82:6473597d706e 6565 #define FTM_BASES { FTM0, FTM1, FTM2, FTM3 }
bogdanm 82:6473597d706e 6566
bogdanm 82:6473597d706e 6567 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6568 -- FTM - Register accessor macros
bogdanm 82:6473597d706e 6569 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6570
bogdanm 82:6473597d706e 6571 /*!
bogdanm 82:6473597d706e 6572 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
bogdanm 82:6473597d706e 6573 * @{
bogdanm 82:6473597d706e 6574 */
bogdanm 82:6473597d706e 6575
bogdanm 82:6473597d706e 6576
bogdanm 82:6473597d706e 6577 /* FTM - Register instance definitions */
bogdanm 82:6473597d706e 6578 /* FTM0 */
bogdanm 82:6473597d706e 6579 #define FTM0_SC FTM_SC_REG(FTM0)
bogdanm 82:6473597d706e 6580 #define FTM0_CNT FTM_CNT_REG(FTM0)
bogdanm 82:6473597d706e 6581 #define FTM0_MOD FTM_MOD_REG(FTM0)
bogdanm 82:6473597d706e 6582 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
bogdanm 82:6473597d706e 6583 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
bogdanm 82:6473597d706e 6584 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
bogdanm 82:6473597d706e 6585 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
bogdanm 82:6473597d706e 6586 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
bogdanm 82:6473597d706e 6587 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
bogdanm 82:6473597d706e 6588 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
bogdanm 82:6473597d706e 6589 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
bogdanm 82:6473597d706e 6590 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
bogdanm 82:6473597d706e 6591 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
bogdanm 82:6473597d706e 6592 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
bogdanm 82:6473597d706e 6593 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
bogdanm 82:6473597d706e 6594 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
bogdanm 82:6473597d706e 6595 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
bogdanm 82:6473597d706e 6596 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
bogdanm 82:6473597d706e 6597 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
bogdanm 82:6473597d706e 6598 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
bogdanm 82:6473597d706e 6599 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
bogdanm 82:6473597d706e 6600 #define FTM0_MODE FTM_MODE_REG(FTM0)
bogdanm 82:6473597d706e 6601 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
bogdanm 82:6473597d706e 6602 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
bogdanm 82:6473597d706e 6603 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
bogdanm 82:6473597d706e 6604 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
bogdanm 82:6473597d706e 6605 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
bogdanm 82:6473597d706e 6606 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
bogdanm 82:6473597d706e 6607 #define FTM0_POL FTM_POL_REG(FTM0)
bogdanm 82:6473597d706e 6608 #define FTM0_FMS FTM_FMS_REG(FTM0)
bogdanm 82:6473597d706e 6609 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
bogdanm 82:6473597d706e 6610 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
bogdanm 82:6473597d706e 6611 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
bogdanm 82:6473597d706e 6612 #define FTM0_CONF FTM_CONF_REG(FTM0)
bogdanm 82:6473597d706e 6613 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
bogdanm 82:6473597d706e 6614 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
bogdanm 82:6473597d706e 6615 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
bogdanm 82:6473597d706e 6616 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
bogdanm 82:6473597d706e 6617 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
bogdanm 82:6473597d706e 6618 /* FTM1 */
bogdanm 82:6473597d706e 6619 #define FTM1_SC FTM_SC_REG(FTM1)
bogdanm 82:6473597d706e 6620 #define FTM1_CNT FTM_CNT_REG(FTM1)
bogdanm 82:6473597d706e 6621 #define FTM1_MOD FTM_MOD_REG(FTM1)
bogdanm 82:6473597d706e 6622 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
bogdanm 82:6473597d706e 6623 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
bogdanm 82:6473597d706e 6624 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
bogdanm 82:6473597d706e 6625 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
bogdanm 82:6473597d706e 6626 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
bogdanm 82:6473597d706e 6627 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
bogdanm 82:6473597d706e 6628 #define FTM1_MODE FTM_MODE_REG(FTM1)
bogdanm 82:6473597d706e 6629 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
bogdanm 82:6473597d706e 6630 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
bogdanm 82:6473597d706e 6631 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
bogdanm 82:6473597d706e 6632 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
bogdanm 82:6473597d706e 6633 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
bogdanm 82:6473597d706e 6634 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
bogdanm 82:6473597d706e 6635 #define FTM1_POL FTM_POL_REG(FTM1)
bogdanm 82:6473597d706e 6636 #define FTM1_FMS FTM_FMS_REG(FTM1)
bogdanm 82:6473597d706e 6637 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
bogdanm 82:6473597d706e 6638 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
bogdanm 82:6473597d706e 6639 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
bogdanm 82:6473597d706e 6640 #define FTM1_CONF FTM_CONF_REG(FTM1)
bogdanm 82:6473597d706e 6641 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
bogdanm 82:6473597d706e 6642 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
bogdanm 82:6473597d706e 6643 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
bogdanm 82:6473597d706e 6644 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
bogdanm 82:6473597d706e 6645 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
bogdanm 82:6473597d706e 6646 /* FTM2 */
bogdanm 82:6473597d706e 6647 #define FTM2_SC FTM_SC_REG(FTM2)
bogdanm 82:6473597d706e 6648 #define FTM2_CNT FTM_CNT_REG(FTM2)
bogdanm 82:6473597d706e 6649 #define FTM2_MOD FTM_MOD_REG(FTM2)
bogdanm 82:6473597d706e 6650 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
bogdanm 82:6473597d706e 6651 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
bogdanm 82:6473597d706e 6652 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
bogdanm 82:6473597d706e 6653 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
bogdanm 82:6473597d706e 6654 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
bogdanm 82:6473597d706e 6655 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
bogdanm 82:6473597d706e 6656 #define FTM2_MODE FTM_MODE_REG(FTM2)
bogdanm 82:6473597d706e 6657 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
bogdanm 82:6473597d706e 6658 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
bogdanm 82:6473597d706e 6659 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
bogdanm 82:6473597d706e 6660 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
bogdanm 82:6473597d706e 6661 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
bogdanm 82:6473597d706e 6662 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
bogdanm 82:6473597d706e 6663 #define FTM2_POL FTM_POL_REG(FTM2)
bogdanm 82:6473597d706e 6664 #define FTM2_FMS FTM_FMS_REG(FTM2)
bogdanm 82:6473597d706e 6665 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
bogdanm 82:6473597d706e 6666 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
bogdanm 82:6473597d706e 6667 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
bogdanm 82:6473597d706e 6668 #define FTM2_CONF FTM_CONF_REG(FTM2)
bogdanm 82:6473597d706e 6669 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
bogdanm 82:6473597d706e 6670 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
bogdanm 82:6473597d706e 6671 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
bogdanm 82:6473597d706e 6672 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
bogdanm 82:6473597d706e 6673 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
bogdanm 82:6473597d706e 6674 /* FTM3 */
bogdanm 82:6473597d706e 6675 #define FTM3_SC FTM_SC_REG(FTM3)
bogdanm 82:6473597d706e 6676 #define FTM3_CNT FTM_CNT_REG(FTM3)
bogdanm 82:6473597d706e 6677 #define FTM3_MOD FTM_MOD_REG(FTM3)
bogdanm 82:6473597d706e 6678 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
bogdanm 82:6473597d706e 6679 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
bogdanm 82:6473597d706e 6680 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
bogdanm 82:6473597d706e 6681 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
bogdanm 82:6473597d706e 6682 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
bogdanm 82:6473597d706e 6683 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
bogdanm 82:6473597d706e 6684 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
bogdanm 82:6473597d706e 6685 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
bogdanm 82:6473597d706e 6686 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
bogdanm 82:6473597d706e 6687 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
bogdanm 82:6473597d706e 6688 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
bogdanm 82:6473597d706e 6689 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
bogdanm 82:6473597d706e 6690 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
bogdanm 82:6473597d706e 6691 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
bogdanm 82:6473597d706e 6692 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
bogdanm 82:6473597d706e 6693 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
bogdanm 82:6473597d706e 6694 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
bogdanm 82:6473597d706e 6695 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
bogdanm 82:6473597d706e 6696 #define FTM3_MODE FTM_MODE_REG(FTM3)
bogdanm 82:6473597d706e 6697 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
bogdanm 82:6473597d706e 6698 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
bogdanm 82:6473597d706e 6699 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
bogdanm 82:6473597d706e 6700 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
bogdanm 82:6473597d706e 6701 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
bogdanm 82:6473597d706e 6702 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
bogdanm 82:6473597d706e 6703 #define FTM3_POL FTM_POL_REG(FTM3)
bogdanm 82:6473597d706e 6704 #define FTM3_FMS FTM_FMS_REG(FTM3)
bogdanm 82:6473597d706e 6705 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
bogdanm 82:6473597d706e 6706 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
bogdanm 82:6473597d706e 6707 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
bogdanm 82:6473597d706e 6708 #define FTM3_CONF FTM_CONF_REG(FTM3)
bogdanm 82:6473597d706e 6709 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
bogdanm 82:6473597d706e 6710 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
bogdanm 82:6473597d706e 6711 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
bogdanm 82:6473597d706e 6712 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
bogdanm 82:6473597d706e 6713 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
bogdanm 82:6473597d706e 6714
bogdanm 82:6473597d706e 6715 /* FTM - Register array accessors */
bogdanm 82:6473597d706e 6716 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
bogdanm 82:6473597d706e 6717 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
bogdanm 82:6473597d706e 6718 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
bogdanm 82:6473597d706e 6719 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
bogdanm 82:6473597d706e 6720 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
bogdanm 82:6473597d706e 6721 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
bogdanm 82:6473597d706e 6722 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
bogdanm 82:6473597d706e 6723 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
bogdanm 82:6473597d706e 6724
bogdanm 82:6473597d706e 6725 /*!
bogdanm 82:6473597d706e 6726 * @}
bogdanm 82:6473597d706e 6727 */ /* end of group FTM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 6728
bogdanm 82:6473597d706e 6729
bogdanm 82:6473597d706e 6730 /*!
bogdanm 82:6473597d706e 6731 * @}
bogdanm 82:6473597d706e 6732 */ /* end of group FTM_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 6733
bogdanm 82:6473597d706e 6734
bogdanm 82:6473597d706e 6735 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6736 -- GPIO Peripheral Access Layer
bogdanm 82:6473597d706e 6737 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6738
bogdanm 82:6473597d706e 6739 /*!
bogdanm 82:6473597d706e 6740 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
bogdanm 82:6473597d706e 6741 * @{
bogdanm 82:6473597d706e 6742 */
bogdanm 82:6473597d706e 6743
bogdanm 82:6473597d706e 6744 /** GPIO - Register Layout Typedef */
bogdanm 82:6473597d706e 6745 typedef struct {
bogdanm 82:6473597d706e 6746 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 82:6473597d706e 6747 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 82:6473597d706e 6748 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 82:6473597d706e 6749 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 82:6473597d706e 6750 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 82:6473597d706e 6751 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 82:6473597d706e 6752 } GPIO_Type, *GPIO_MemMapPtr;
bogdanm 82:6473597d706e 6753
bogdanm 82:6473597d706e 6754 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6755 -- GPIO - Register accessor macros
bogdanm 82:6473597d706e 6756 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6757
bogdanm 82:6473597d706e 6758 /*!
bogdanm 82:6473597d706e 6759 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
bogdanm 82:6473597d706e 6760 * @{
bogdanm 82:6473597d706e 6761 */
bogdanm 82:6473597d706e 6762
bogdanm 82:6473597d706e 6763
bogdanm 82:6473597d706e 6764 /* GPIO - Register accessors */
bogdanm 82:6473597d706e 6765 #define GPIO_PDOR_REG(base) ((base)->PDOR)
bogdanm 82:6473597d706e 6766 #define GPIO_PSOR_REG(base) ((base)->PSOR)
bogdanm 82:6473597d706e 6767 #define GPIO_PCOR_REG(base) ((base)->PCOR)
bogdanm 82:6473597d706e 6768 #define GPIO_PTOR_REG(base) ((base)->PTOR)
bogdanm 82:6473597d706e 6769 #define GPIO_PDIR_REG(base) ((base)->PDIR)
bogdanm 82:6473597d706e 6770 #define GPIO_PDDR_REG(base) ((base)->PDDR)
bogdanm 82:6473597d706e 6771
bogdanm 82:6473597d706e 6772 /*!
bogdanm 82:6473597d706e 6773 * @}
bogdanm 82:6473597d706e 6774 */ /* end of group GPIO_Register_Accessor_Macros */
bogdanm 82:6473597d706e 6775
bogdanm 82:6473597d706e 6776
bogdanm 82:6473597d706e 6777 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6778 -- GPIO Register Masks
bogdanm 82:6473597d706e 6779 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6780
bogdanm 82:6473597d706e 6781 /*!
bogdanm 82:6473597d706e 6782 * @addtogroup GPIO_Register_Masks GPIO Register Masks
bogdanm 82:6473597d706e 6783 * @{
bogdanm 82:6473597d706e 6784 */
bogdanm 82:6473597d706e 6785
bogdanm 82:6473597d706e 6786 /* PDOR Bit Fields */
bogdanm 82:6473597d706e 6787 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 6788 #define GPIO_PDOR_PDO_SHIFT 0
bogdanm 82:6473597d706e 6789 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
bogdanm 82:6473597d706e 6790 /* PSOR Bit Fields */
bogdanm 82:6473597d706e 6791 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 6792 #define GPIO_PSOR_PTSO_SHIFT 0
bogdanm 82:6473597d706e 6793 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
bogdanm 82:6473597d706e 6794 /* PCOR Bit Fields */
bogdanm 82:6473597d706e 6795 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 6796 #define GPIO_PCOR_PTCO_SHIFT 0
bogdanm 82:6473597d706e 6797 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
bogdanm 82:6473597d706e 6798 /* PTOR Bit Fields */
bogdanm 82:6473597d706e 6799 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 6800 #define GPIO_PTOR_PTTO_SHIFT 0
bogdanm 82:6473597d706e 6801 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
bogdanm 82:6473597d706e 6802 /* PDIR Bit Fields */
bogdanm 82:6473597d706e 6803 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 6804 #define GPIO_PDIR_PDI_SHIFT 0
bogdanm 82:6473597d706e 6805 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
bogdanm 82:6473597d706e 6806 /* PDDR Bit Fields */
bogdanm 82:6473597d706e 6807 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 6808 #define GPIO_PDDR_PDD_SHIFT 0
bogdanm 82:6473597d706e 6809 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
bogdanm 82:6473597d706e 6810
bogdanm 82:6473597d706e 6811 /*!
bogdanm 82:6473597d706e 6812 * @}
bogdanm 82:6473597d706e 6813 */ /* end of group GPIO_Register_Masks */
bogdanm 82:6473597d706e 6814
bogdanm 82:6473597d706e 6815
bogdanm 82:6473597d706e 6816 /* GPIO - Peripheral instance base addresses */
bogdanm 82:6473597d706e 6817 /** Peripheral PTA base address */
bogdanm 82:6473597d706e 6818 #define PTA_BASE (0x400FF000u)
bogdanm 82:6473597d706e 6819 /** Peripheral PTA base pointer */
bogdanm 82:6473597d706e 6820 #define PTA ((GPIO_Type *)PTA_BASE)
bogdanm 82:6473597d706e 6821 #define PTA_BASE_PTR (PTA)
bogdanm 82:6473597d706e 6822 /** Peripheral PTB base address */
bogdanm 82:6473597d706e 6823 #define PTB_BASE (0x400FF040u)
bogdanm 82:6473597d706e 6824 /** Peripheral PTB base pointer */
bogdanm 82:6473597d706e 6825 #define PTB ((GPIO_Type *)PTB_BASE)
bogdanm 82:6473597d706e 6826 #define PTB_BASE_PTR (PTB)
bogdanm 82:6473597d706e 6827 /** Peripheral PTC base address */
bogdanm 82:6473597d706e 6828 #define PTC_BASE (0x400FF080u)
bogdanm 82:6473597d706e 6829 /** Peripheral PTC base pointer */
bogdanm 82:6473597d706e 6830 #define PTC ((GPIO_Type *)PTC_BASE)
bogdanm 82:6473597d706e 6831 #define PTC_BASE_PTR (PTC)
bogdanm 82:6473597d706e 6832 /** Peripheral PTD base address */
bogdanm 82:6473597d706e 6833 #define PTD_BASE (0x400FF0C0u)
bogdanm 82:6473597d706e 6834 /** Peripheral PTD base pointer */
bogdanm 82:6473597d706e 6835 #define PTD ((GPIO_Type *)PTD_BASE)
bogdanm 82:6473597d706e 6836 #define PTD_BASE_PTR (PTD)
bogdanm 82:6473597d706e 6837 /** Peripheral PTE base address */
bogdanm 82:6473597d706e 6838 #define PTE_BASE (0x400FF100u)
bogdanm 82:6473597d706e 6839 /** Peripheral PTE base pointer */
bogdanm 82:6473597d706e 6840 #define PTE ((GPIO_Type *)PTE_BASE)
bogdanm 82:6473597d706e 6841 #define PTE_BASE_PTR (PTE)
bogdanm 82:6473597d706e 6842 /** Array initializer of GPIO peripheral base pointers */
bogdanm 82:6473597d706e 6843 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
bogdanm 82:6473597d706e 6844
bogdanm 82:6473597d706e 6845 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6846 -- GPIO - Register accessor macros
bogdanm 82:6473597d706e 6847 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6848
bogdanm 82:6473597d706e 6849 /*!
bogdanm 82:6473597d706e 6850 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
bogdanm 82:6473597d706e 6851 * @{
bogdanm 82:6473597d706e 6852 */
bogdanm 82:6473597d706e 6853
bogdanm 82:6473597d706e 6854
bogdanm 82:6473597d706e 6855 /* GPIO - Register instance definitions */
bogdanm 82:6473597d706e 6856 /* PTA */
bogdanm 82:6473597d706e 6857 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
bogdanm 82:6473597d706e 6858 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
bogdanm 82:6473597d706e 6859 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
bogdanm 82:6473597d706e 6860 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
bogdanm 82:6473597d706e 6861 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
bogdanm 82:6473597d706e 6862 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
bogdanm 82:6473597d706e 6863 /* PTB */
bogdanm 82:6473597d706e 6864 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
bogdanm 82:6473597d706e 6865 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
bogdanm 82:6473597d706e 6866 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
bogdanm 82:6473597d706e 6867 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
bogdanm 82:6473597d706e 6868 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
bogdanm 82:6473597d706e 6869 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
bogdanm 82:6473597d706e 6870 /* PTC */
bogdanm 82:6473597d706e 6871 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
bogdanm 82:6473597d706e 6872 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
bogdanm 82:6473597d706e 6873 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
bogdanm 82:6473597d706e 6874 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
bogdanm 82:6473597d706e 6875 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
bogdanm 82:6473597d706e 6876 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
bogdanm 82:6473597d706e 6877 /* PTD */
bogdanm 82:6473597d706e 6878 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
bogdanm 82:6473597d706e 6879 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
bogdanm 82:6473597d706e 6880 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
bogdanm 82:6473597d706e 6881 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
bogdanm 82:6473597d706e 6882 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
bogdanm 82:6473597d706e 6883 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
bogdanm 82:6473597d706e 6884 /* PTE */
bogdanm 82:6473597d706e 6885 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
bogdanm 82:6473597d706e 6886 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
bogdanm 82:6473597d706e 6887 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
bogdanm 82:6473597d706e 6888 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
bogdanm 82:6473597d706e 6889 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
bogdanm 82:6473597d706e 6890 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
bogdanm 82:6473597d706e 6891
bogdanm 82:6473597d706e 6892 /*!
bogdanm 82:6473597d706e 6893 * @}
bogdanm 82:6473597d706e 6894 */ /* end of group GPIO_Register_Accessor_Macros */
bogdanm 82:6473597d706e 6895
bogdanm 82:6473597d706e 6896
bogdanm 82:6473597d706e 6897 /*!
bogdanm 82:6473597d706e 6898 * @}
bogdanm 82:6473597d706e 6899 */ /* end of group GPIO_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 6900
bogdanm 82:6473597d706e 6901
bogdanm 82:6473597d706e 6902 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6903 -- I2C Peripheral Access Layer
bogdanm 82:6473597d706e 6904 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6905
bogdanm 82:6473597d706e 6906 /*!
bogdanm 82:6473597d706e 6907 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
bogdanm 82:6473597d706e 6908 * @{
bogdanm 82:6473597d706e 6909 */
bogdanm 82:6473597d706e 6910
bogdanm 82:6473597d706e 6911 /** I2C - Register Layout Typedef */
bogdanm 82:6473597d706e 6912 typedef struct {
bogdanm 82:6473597d706e 6913 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
bogdanm 82:6473597d706e 6914 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
bogdanm 82:6473597d706e 6915 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
bogdanm 82:6473597d706e 6916 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
bogdanm 82:6473597d706e 6917 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
bogdanm 82:6473597d706e 6918 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
bogdanm 82:6473597d706e 6919 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
bogdanm 82:6473597d706e 6920 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
bogdanm 82:6473597d706e 6921 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
bogdanm 82:6473597d706e 6922 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
bogdanm 82:6473597d706e 6923 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
bogdanm 82:6473597d706e 6924 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
bogdanm 82:6473597d706e 6925 } I2C_Type, *I2C_MemMapPtr;
bogdanm 82:6473597d706e 6926
bogdanm 82:6473597d706e 6927 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6928 -- I2C - Register accessor macros
bogdanm 82:6473597d706e 6929 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6930
bogdanm 82:6473597d706e 6931 /*!
bogdanm 82:6473597d706e 6932 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
bogdanm 82:6473597d706e 6933 * @{
bogdanm 82:6473597d706e 6934 */
bogdanm 82:6473597d706e 6935
bogdanm 82:6473597d706e 6936
bogdanm 82:6473597d706e 6937 /* I2C - Register accessors */
bogdanm 82:6473597d706e 6938 #define I2C_A1_REG(base) ((base)->A1)
bogdanm 82:6473597d706e 6939 #define I2C_F_REG(base) ((base)->F)
bogdanm 82:6473597d706e 6940 #define I2C_C1_REG(base) ((base)->C1)
bogdanm 82:6473597d706e 6941 #define I2C_S_REG(base) ((base)->S)
bogdanm 82:6473597d706e 6942 #define I2C_D_REG(base) ((base)->D)
bogdanm 82:6473597d706e 6943 #define I2C_C2_REG(base) ((base)->C2)
bogdanm 82:6473597d706e 6944 #define I2C_FLT_REG(base) ((base)->FLT)
bogdanm 82:6473597d706e 6945 #define I2C_RA_REG(base) ((base)->RA)
bogdanm 82:6473597d706e 6946 #define I2C_SMB_REG(base) ((base)->SMB)
bogdanm 82:6473597d706e 6947 #define I2C_A2_REG(base) ((base)->A2)
bogdanm 82:6473597d706e 6948 #define I2C_SLTH_REG(base) ((base)->SLTH)
bogdanm 82:6473597d706e 6949 #define I2C_SLTL_REG(base) ((base)->SLTL)
bogdanm 82:6473597d706e 6950
bogdanm 82:6473597d706e 6951 /*!
bogdanm 82:6473597d706e 6952 * @}
bogdanm 82:6473597d706e 6953 */ /* end of group I2C_Register_Accessor_Macros */
bogdanm 82:6473597d706e 6954
bogdanm 82:6473597d706e 6955
bogdanm 82:6473597d706e 6956 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 6957 -- I2C Register Masks
bogdanm 82:6473597d706e 6958 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 6959
bogdanm 82:6473597d706e 6960 /*!
bogdanm 82:6473597d706e 6961 * @addtogroup I2C_Register_Masks I2C Register Masks
bogdanm 82:6473597d706e 6962 * @{
bogdanm 82:6473597d706e 6963 */
bogdanm 82:6473597d706e 6964
bogdanm 82:6473597d706e 6965 /* A1 Bit Fields */
bogdanm 82:6473597d706e 6966 #define I2C_A1_AD_MASK 0xFEu
bogdanm 82:6473597d706e 6967 #define I2C_A1_AD_SHIFT 1
bogdanm 82:6473597d706e 6968 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
bogdanm 82:6473597d706e 6969 /* F Bit Fields */
bogdanm 82:6473597d706e 6970 #define I2C_F_ICR_MASK 0x3Fu
bogdanm 82:6473597d706e 6971 #define I2C_F_ICR_SHIFT 0
bogdanm 82:6473597d706e 6972 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
bogdanm 82:6473597d706e 6973 #define I2C_F_MULT_MASK 0xC0u
bogdanm 82:6473597d706e 6974 #define I2C_F_MULT_SHIFT 6
bogdanm 82:6473597d706e 6975 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
bogdanm 82:6473597d706e 6976 /* C1 Bit Fields */
bogdanm 82:6473597d706e 6977 #define I2C_C1_DMAEN_MASK 0x1u
bogdanm 82:6473597d706e 6978 #define I2C_C1_DMAEN_SHIFT 0
bogdanm 82:6473597d706e 6979 #define I2C_C1_WUEN_MASK 0x2u
bogdanm 82:6473597d706e 6980 #define I2C_C1_WUEN_SHIFT 1
bogdanm 82:6473597d706e 6981 #define I2C_C1_RSTA_MASK 0x4u
bogdanm 82:6473597d706e 6982 #define I2C_C1_RSTA_SHIFT 2
bogdanm 82:6473597d706e 6983 #define I2C_C1_TXAK_MASK 0x8u
bogdanm 82:6473597d706e 6984 #define I2C_C1_TXAK_SHIFT 3
bogdanm 82:6473597d706e 6985 #define I2C_C1_TX_MASK 0x10u
bogdanm 82:6473597d706e 6986 #define I2C_C1_TX_SHIFT 4
bogdanm 82:6473597d706e 6987 #define I2C_C1_MST_MASK 0x20u
bogdanm 82:6473597d706e 6988 #define I2C_C1_MST_SHIFT 5
bogdanm 82:6473597d706e 6989 #define I2C_C1_IICIE_MASK 0x40u
bogdanm 82:6473597d706e 6990 #define I2C_C1_IICIE_SHIFT 6
bogdanm 82:6473597d706e 6991 #define I2C_C1_IICEN_MASK 0x80u
bogdanm 82:6473597d706e 6992 #define I2C_C1_IICEN_SHIFT 7
bogdanm 82:6473597d706e 6993 /* S Bit Fields */
bogdanm 82:6473597d706e 6994 #define I2C_S_RXAK_MASK 0x1u
bogdanm 82:6473597d706e 6995 #define I2C_S_RXAK_SHIFT 0
bogdanm 82:6473597d706e 6996 #define I2C_S_IICIF_MASK 0x2u
bogdanm 82:6473597d706e 6997 #define I2C_S_IICIF_SHIFT 1
bogdanm 82:6473597d706e 6998 #define I2C_S_SRW_MASK 0x4u
bogdanm 82:6473597d706e 6999 #define I2C_S_SRW_SHIFT 2
bogdanm 82:6473597d706e 7000 #define I2C_S_RAM_MASK 0x8u
bogdanm 82:6473597d706e 7001 #define I2C_S_RAM_SHIFT 3
bogdanm 82:6473597d706e 7002 #define I2C_S_ARBL_MASK 0x10u
bogdanm 82:6473597d706e 7003 #define I2C_S_ARBL_SHIFT 4
bogdanm 82:6473597d706e 7004 #define I2C_S_BUSY_MASK 0x20u
bogdanm 82:6473597d706e 7005 #define I2C_S_BUSY_SHIFT 5
bogdanm 82:6473597d706e 7006 #define I2C_S_IAAS_MASK 0x40u
bogdanm 82:6473597d706e 7007 #define I2C_S_IAAS_SHIFT 6
bogdanm 82:6473597d706e 7008 #define I2C_S_TCF_MASK 0x80u
bogdanm 82:6473597d706e 7009 #define I2C_S_TCF_SHIFT 7
bogdanm 82:6473597d706e 7010 /* D Bit Fields */
bogdanm 82:6473597d706e 7011 #define I2C_D_DATA_MASK 0xFFu
bogdanm 82:6473597d706e 7012 #define I2C_D_DATA_SHIFT 0
bogdanm 82:6473597d706e 7013 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
bogdanm 82:6473597d706e 7014 /* C2 Bit Fields */
bogdanm 82:6473597d706e 7015 #define I2C_C2_AD_MASK 0x7u
bogdanm 82:6473597d706e 7016 #define I2C_C2_AD_SHIFT 0
bogdanm 82:6473597d706e 7017 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
bogdanm 82:6473597d706e 7018 #define I2C_C2_RMEN_MASK 0x8u
bogdanm 82:6473597d706e 7019 #define I2C_C2_RMEN_SHIFT 3
bogdanm 82:6473597d706e 7020 #define I2C_C2_SBRC_MASK 0x10u
bogdanm 82:6473597d706e 7021 #define I2C_C2_SBRC_SHIFT 4
bogdanm 82:6473597d706e 7022 #define I2C_C2_HDRS_MASK 0x20u
bogdanm 82:6473597d706e 7023 #define I2C_C2_HDRS_SHIFT 5
bogdanm 82:6473597d706e 7024 #define I2C_C2_ADEXT_MASK 0x40u
bogdanm 82:6473597d706e 7025 #define I2C_C2_ADEXT_SHIFT 6
bogdanm 82:6473597d706e 7026 #define I2C_C2_GCAEN_MASK 0x80u
bogdanm 82:6473597d706e 7027 #define I2C_C2_GCAEN_SHIFT 7
bogdanm 82:6473597d706e 7028 /* FLT Bit Fields */
bogdanm 82:6473597d706e 7029 #define I2C_FLT_FLT_MASK 0xFu
bogdanm 82:6473597d706e 7030 #define I2C_FLT_FLT_SHIFT 0
bogdanm 82:6473597d706e 7031 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
bogdanm 82:6473597d706e 7032 #define I2C_FLT_STARTF_MASK 0x10u
bogdanm 82:6473597d706e 7033 #define I2C_FLT_STARTF_SHIFT 4
bogdanm 82:6473597d706e 7034 #define I2C_FLT_SSIE_MASK 0x20u
bogdanm 82:6473597d706e 7035 #define I2C_FLT_SSIE_SHIFT 5
bogdanm 82:6473597d706e 7036 #define I2C_FLT_STOPF_MASK 0x40u
bogdanm 82:6473597d706e 7037 #define I2C_FLT_STOPF_SHIFT 6
bogdanm 82:6473597d706e 7038 #define I2C_FLT_SHEN_MASK 0x80u
bogdanm 82:6473597d706e 7039 #define I2C_FLT_SHEN_SHIFT 7
bogdanm 82:6473597d706e 7040 /* RA Bit Fields */
bogdanm 82:6473597d706e 7041 #define I2C_RA_RAD_MASK 0xFEu
bogdanm 82:6473597d706e 7042 #define I2C_RA_RAD_SHIFT 1
bogdanm 82:6473597d706e 7043 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
bogdanm 82:6473597d706e 7044 /* SMB Bit Fields */
bogdanm 82:6473597d706e 7045 #define I2C_SMB_SHTF2IE_MASK 0x1u
bogdanm 82:6473597d706e 7046 #define I2C_SMB_SHTF2IE_SHIFT 0
bogdanm 82:6473597d706e 7047 #define I2C_SMB_SHTF2_MASK 0x2u
bogdanm 82:6473597d706e 7048 #define I2C_SMB_SHTF2_SHIFT 1
bogdanm 82:6473597d706e 7049 #define I2C_SMB_SHTF1_MASK 0x4u
bogdanm 82:6473597d706e 7050 #define I2C_SMB_SHTF1_SHIFT 2
bogdanm 82:6473597d706e 7051 #define I2C_SMB_SLTF_MASK 0x8u
bogdanm 82:6473597d706e 7052 #define I2C_SMB_SLTF_SHIFT 3
bogdanm 82:6473597d706e 7053 #define I2C_SMB_TCKSEL_MASK 0x10u
bogdanm 82:6473597d706e 7054 #define I2C_SMB_TCKSEL_SHIFT 4
bogdanm 82:6473597d706e 7055 #define I2C_SMB_SIICAEN_MASK 0x20u
bogdanm 82:6473597d706e 7056 #define I2C_SMB_SIICAEN_SHIFT 5
bogdanm 82:6473597d706e 7057 #define I2C_SMB_ALERTEN_MASK 0x40u
bogdanm 82:6473597d706e 7058 #define I2C_SMB_ALERTEN_SHIFT 6
bogdanm 82:6473597d706e 7059 #define I2C_SMB_FACK_MASK 0x80u
bogdanm 82:6473597d706e 7060 #define I2C_SMB_FACK_SHIFT 7
bogdanm 82:6473597d706e 7061 /* A2 Bit Fields */
bogdanm 82:6473597d706e 7062 #define I2C_A2_SAD_MASK 0xFEu
bogdanm 82:6473597d706e 7063 #define I2C_A2_SAD_SHIFT 1
bogdanm 82:6473597d706e 7064 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
bogdanm 82:6473597d706e 7065 /* SLTH Bit Fields */
bogdanm 82:6473597d706e 7066 #define I2C_SLTH_SSLT_MASK 0xFFu
bogdanm 82:6473597d706e 7067 #define I2C_SLTH_SSLT_SHIFT 0
bogdanm 82:6473597d706e 7068 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
bogdanm 82:6473597d706e 7069 /* SLTL Bit Fields */
bogdanm 82:6473597d706e 7070 #define I2C_SLTL_SSLT_MASK 0xFFu
bogdanm 82:6473597d706e 7071 #define I2C_SLTL_SSLT_SHIFT 0
bogdanm 82:6473597d706e 7072 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
bogdanm 82:6473597d706e 7073
bogdanm 82:6473597d706e 7074 /*!
bogdanm 82:6473597d706e 7075 * @}
bogdanm 82:6473597d706e 7076 */ /* end of group I2C_Register_Masks */
bogdanm 82:6473597d706e 7077
bogdanm 82:6473597d706e 7078
bogdanm 82:6473597d706e 7079 /* I2C - Peripheral instance base addresses */
bogdanm 82:6473597d706e 7080 /** Peripheral I2C0 base address */
bogdanm 82:6473597d706e 7081 #define I2C0_BASE (0x40066000u)
bogdanm 82:6473597d706e 7082 /** Peripheral I2C0 base pointer */
bogdanm 82:6473597d706e 7083 #define I2C0 ((I2C_Type *)I2C0_BASE)
bogdanm 82:6473597d706e 7084 #define I2C0_BASE_PTR (I2C0)
bogdanm 82:6473597d706e 7085 /** Peripheral I2C1 base address */
bogdanm 82:6473597d706e 7086 #define I2C1_BASE (0x40067000u)
bogdanm 82:6473597d706e 7087 /** Peripheral I2C1 base pointer */
bogdanm 82:6473597d706e 7088 #define I2C1 ((I2C_Type *)I2C1_BASE)
bogdanm 82:6473597d706e 7089 #define I2C1_BASE_PTR (I2C1)
bogdanm 82:6473597d706e 7090 /** Peripheral I2C2 base address */
bogdanm 82:6473597d706e 7091 #define I2C2_BASE (0x400E6000u)
bogdanm 82:6473597d706e 7092 /** Peripheral I2C2 base pointer */
bogdanm 82:6473597d706e 7093 #define I2C2 ((I2C_Type *)I2C2_BASE)
bogdanm 82:6473597d706e 7094 #define I2C2_BASE_PTR (I2C2)
bogdanm 82:6473597d706e 7095 /** Array initializer of I2C peripheral base pointers */
bogdanm 82:6473597d706e 7096 #define I2C_BASES { I2C0, I2C1, I2C2 }
bogdanm 82:6473597d706e 7097
bogdanm 82:6473597d706e 7098 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7099 -- I2C - Register accessor macros
bogdanm 82:6473597d706e 7100 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7101
bogdanm 82:6473597d706e 7102 /*!
bogdanm 82:6473597d706e 7103 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
bogdanm 82:6473597d706e 7104 * @{
bogdanm 82:6473597d706e 7105 */
bogdanm 82:6473597d706e 7106
bogdanm 82:6473597d706e 7107
bogdanm 82:6473597d706e 7108 /* I2C - Register instance definitions */
bogdanm 82:6473597d706e 7109 /* I2C0 */
bogdanm 82:6473597d706e 7110 #define I2C0_A1 I2C_A1_REG(I2C0)
bogdanm 82:6473597d706e 7111 #define I2C0_F I2C_F_REG(I2C0)
bogdanm 82:6473597d706e 7112 #define I2C0_C1 I2C_C1_REG(I2C0)
bogdanm 82:6473597d706e 7113 #define I2C0_S I2C_S_REG(I2C0)
bogdanm 82:6473597d706e 7114 #define I2C0_D I2C_D_REG(I2C0)
bogdanm 82:6473597d706e 7115 #define I2C0_C2 I2C_C2_REG(I2C0)
bogdanm 82:6473597d706e 7116 #define I2C0_FLT I2C_FLT_REG(I2C0)
bogdanm 82:6473597d706e 7117 #define I2C0_RA I2C_RA_REG(I2C0)
bogdanm 82:6473597d706e 7118 #define I2C0_SMB I2C_SMB_REG(I2C0)
bogdanm 82:6473597d706e 7119 #define I2C0_A2 I2C_A2_REG(I2C0)
bogdanm 82:6473597d706e 7120 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
bogdanm 82:6473597d706e 7121 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
bogdanm 82:6473597d706e 7122 /* I2C1 */
bogdanm 82:6473597d706e 7123 #define I2C1_A1 I2C_A1_REG(I2C1)
bogdanm 82:6473597d706e 7124 #define I2C1_F I2C_F_REG(I2C1)
bogdanm 82:6473597d706e 7125 #define I2C1_C1 I2C_C1_REG(I2C1)
bogdanm 82:6473597d706e 7126 #define I2C1_S I2C_S_REG(I2C1)
bogdanm 82:6473597d706e 7127 #define I2C1_D I2C_D_REG(I2C1)
bogdanm 82:6473597d706e 7128 #define I2C1_C2 I2C_C2_REG(I2C1)
bogdanm 82:6473597d706e 7129 #define I2C1_FLT I2C_FLT_REG(I2C1)
bogdanm 82:6473597d706e 7130 #define I2C1_RA I2C_RA_REG(I2C1)
bogdanm 82:6473597d706e 7131 #define I2C1_SMB I2C_SMB_REG(I2C1)
bogdanm 82:6473597d706e 7132 #define I2C1_A2 I2C_A2_REG(I2C1)
bogdanm 82:6473597d706e 7133 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
bogdanm 82:6473597d706e 7134 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
bogdanm 82:6473597d706e 7135 /* I2C2 */
bogdanm 82:6473597d706e 7136 #define I2C2_A1 I2C_A1_REG(I2C2)
bogdanm 82:6473597d706e 7137 #define I2C2_F I2C_F_REG(I2C2)
bogdanm 82:6473597d706e 7138 #define I2C2_C1 I2C_C1_REG(I2C2)
bogdanm 82:6473597d706e 7139 #define I2C2_S I2C_S_REG(I2C2)
bogdanm 82:6473597d706e 7140 #define I2C2_D I2C_D_REG(I2C2)
bogdanm 82:6473597d706e 7141 #define I2C2_C2 I2C_C2_REG(I2C2)
bogdanm 82:6473597d706e 7142 #define I2C2_FLT I2C_FLT_REG(I2C2)
bogdanm 82:6473597d706e 7143 #define I2C2_RA I2C_RA_REG(I2C2)
bogdanm 82:6473597d706e 7144 #define I2C2_SMB I2C_SMB_REG(I2C2)
bogdanm 82:6473597d706e 7145 #define I2C2_A2 I2C_A2_REG(I2C2)
bogdanm 82:6473597d706e 7146 #define I2C2_SLTH I2C_SLTH_REG(I2C2)
bogdanm 82:6473597d706e 7147 #define I2C2_SLTL I2C_SLTL_REG(I2C2)
bogdanm 82:6473597d706e 7148
bogdanm 82:6473597d706e 7149 /*!
bogdanm 82:6473597d706e 7150 * @}
bogdanm 82:6473597d706e 7151 */ /* end of group I2C_Register_Accessor_Macros */
bogdanm 82:6473597d706e 7152
bogdanm 82:6473597d706e 7153
bogdanm 82:6473597d706e 7154 /*!
bogdanm 82:6473597d706e 7155 * @}
bogdanm 82:6473597d706e 7156 */ /* end of group I2C_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 7157
bogdanm 82:6473597d706e 7158
bogdanm 82:6473597d706e 7159 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7160 -- I2S Peripheral Access Layer
bogdanm 82:6473597d706e 7161 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7162
bogdanm 82:6473597d706e 7163 /*!
bogdanm 82:6473597d706e 7164 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
bogdanm 82:6473597d706e 7165 * @{
bogdanm 82:6473597d706e 7166 */
bogdanm 82:6473597d706e 7167
bogdanm 82:6473597d706e 7168 /** I2S - Register Layout Typedef */
bogdanm 82:6473597d706e 7169 typedef struct {
bogdanm 82:6473597d706e 7170 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
bogdanm 82:6473597d706e 7171 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
bogdanm 82:6473597d706e 7172 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
bogdanm 82:6473597d706e 7173 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
bogdanm 82:6473597d706e 7174 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
bogdanm 82:6473597d706e 7175 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
bogdanm 82:6473597d706e 7176 uint8_t RESERVED_0[8];
bogdanm 82:6473597d706e 7177 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
bogdanm 82:6473597d706e 7178 uint8_t RESERVED_1[24];
bogdanm 82:6473597d706e 7179 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
bogdanm 82:6473597d706e 7180 uint8_t RESERVED_2[24];
bogdanm 82:6473597d706e 7181 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
bogdanm 82:6473597d706e 7182 uint8_t RESERVED_3[28];
bogdanm 82:6473597d706e 7183 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
bogdanm 82:6473597d706e 7184 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
bogdanm 82:6473597d706e 7185 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
bogdanm 82:6473597d706e 7186 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
bogdanm 82:6473597d706e 7187 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
bogdanm 82:6473597d706e 7188 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
bogdanm 82:6473597d706e 7189 uint8_t RESERVED_4[8];
bogdanm 82:6473597d706e 7190 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
bogdanm 82:6473597d706e 7191 uint8_t RESERVED_5[24];
bogdanm 82:6473597d706e 7192 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
bogdanm 82:6473597d706e 7193 uint8_t RESERVED_6[24];
bogdanm 82:6473597d706e 7194 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
bogdanm 82:6473597d706e 7195 uint8_t RESERVED_7[28];
bogdanm 82:6473597d706e 7196 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
bogdanm 82:6473597d706e 7197 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
bogdanm 82:6473597d706e 7198 } I2S_Type, *I2S_MemMapPtr;
bogdanm 82:6473597d706e 7199
bogdanm 82:6473597d706e 7200 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7201 -- I2S - Register accessor macros
bogdanm 82:6473597d706e 7202 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7203
bogdanm 82:6473597d706e 7204 /*!
bogdanm 82:6473597d706e 7205 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
bogdanm 82:6473597d706e 7206 * @{
bogdanm 82:6473597d706e 7207 */
bogdanm 82:6473597d706e 7208
bogdanm 82:6473597d706e 7209
bogdanm 82:6473597d706e 7210 /* I2S - Register accessors */
bogdanm 82:6473597d706e 7211 #define I2S_TCSR_REG(base) ((base)->TCSR)
bogdanm 82:6473597d706e 7212 #define I2S_TCR1_REG(base) ((base)->TCR1)
bogdanm 82:6473597d706e 7213 #define I2S_TCR2_REG(base) ((base)->TCR2)
bogdanm 82:6473597d706e 7214 #define I2S_TCR3_REG(base) ((base)->TCR3)
bogdanm 82:6473597d706e 7215 #define I2S_TCR4_REG(base) ((base)->TCR4)
bogdanm 82:6473597d706e 7216 #define I2S_TCR5_REG(base) ((base)->TCR5)
bogdanm 82:6473597d706e 7217 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
bogdanm 82:6473597d706e 7218 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
bogdanm 82:6473597d706e 7219 #define I2S_TMR_REG(base) ((base)->TMR)
bogdanm 82:6473597d706e 7220 #define I2S_RCSR_REG(base) ((base)->RCSR)
bogdanm 82:6473597d706e 7221 #define I2S_RCR1_REG(base) ((base)->RCR1)
bogdanm 82:6473597d706e 7222 #define I2S_RCR2_REG(base) ((base)->RCR2)
bogdanm 82:6473597d706e 7223 #define I2S_RCR3_REG(base) ((base)->RCR3)
bogdanm 82:6473597d706e 7224 #define I2S_RCR4_REG(base) ((base)->RCR4)
bogdanm 82:6473597d706e 7225 #define I2S_RCR5_REG(base) ((base)->RCR5)
bogdanm 82:6473597d706e 7226 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
bogdanm 82:6473597d706e 7227 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
bogdanm 82:6473597d706e 7228 #define I2S_RMR_REG(base) ((base)->RMR)
bogdanm 82:6473597d706e 7229 #define I2S_MCR_REG(base) ((base)->MCR)
bogdanm 82:6473597d706e 7230 #define I2S_MDR_REG(base) ((base)->MDR)
bogdanm 82:6473597d706e 7231
bogdanm 82:6473597d706e 7232 /*!
bogdanm 82:6473597d706e 7233 * @}
bogdanm 82:6473597d706e 7234 */ /* end of group I2S_Register_Accessor_Macros */
bogdanm 82:6473597d706e 7235
bogdanm 82:6473597d706e 7236
bogdanm 82:6473597d706e 7237 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7238 -- I2S Register Masks
bogdanm 82:6473597d706e 7239 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7240
bogdanm 82:6473597d706e 7241 /*!
bogdanm 82:6473597d706e 7242 * @addtogroup I2S_Register_Masks I2S Register Masks
bogdanm 82:6473597d706e 7243 * @{
bogdanm 82:6473597d706e 7244 */
bogdanm 82:6473597d706e 7245
bogdanm 82:6473597d706e 7246 /* TCSR Bit Fields */
bogdanm 82:6473597d706e 7247 #define I2S_TCSR_FRDE_MASK 0x1u
bogdanm 82:6473597d706e 7248 #define I2S_TCSR_FRDE_SHIFT 0
bogdanm 82:6473597d706e 7249 #define I2S_TCSR_FWDE_MASK 0x2u
bogdanm 82:6473597d706e 7250 #define I2S_TCSR_FWDE_SHIFT 1
bogdanm 82:6473597d706e 7251 #define I2S_TCSR_FRIE_MASK 0x100u
bogdanm 82:6473597d706e 7252 #define I2S_TCSR_FRIE_SHIFT 8
bogdanm 82:6473597d706e 7253 #define I2S_TCSR_FWIE_MASK 0x200u
bogdanm 82:6473597d706e 7254 #define I2S_TCSR_FWIE_SHIFT 9
bogdanm 82:6473597d706e 7255 #define I2S_TCSR_FEIE_MASK 0x400u
bogdanm 82:6473597d706e 7256 #define I2S_TCSR_FEIE_SHIFT 10
bogdanm 82:6473597d706e 7257 #define I2S_TCSR_SEIE_MASK 0x800u
bogdanm 82:6473597d706e 7258 #define I2S_TCSR_SEIE_SHIFT 11
bogdanm 82:6473597d706e 7259 #define I2S_TCSR_WSIE_MASK 0x1000u
bogdanm 82:6473597d706e 7260 #define I2S_TCSR_WSIE_SHIFT 12
bogdanm 82:6473597d706e 7261 #define I2S_TCSR_FRF_MASK 0x10000u
bogdanm 82:6473597d706e 7262 #define I2S_TCSR_FRF_SHIFT 16
bogdanm 82:6473597d706e 7263 #define I2S_TCSR_FWF_MASK 0x20000u
bogdanm 82:6473597d706e 7264 #define I2S_TCSR_FWF_SHIFT 17
bogdanm 82:6473597d706e 7265 #define I2S_TCSR_FEF_MASK 0x40000u
bogdanm 82:6473597d706e 7266 #define I2S_TCSR_FEF_SHIFT 18
bogdanm 82:6473597d706e 7267 #define I2S_TCSR_SEF_MASK 0x80000u
bogdanm 82:6473597d706e 7268 #define I2S_TCSR_SEF_SHIFT 19
bogdanm 82:6473597d706e 7269 #define I2S_TCSR_WSF_MASK 0x100000u
bogdanm 82:6473597d706e 7270 #define I2S_TCSR_WSF_SHIFT 20
bogdanm 82:6473597d706e 7271 #define I2S_TCSR_SR_MASK 0x1000000u
bogdanm 82:6473597d706e 7272 #define I2S_TCSR_SR_SHIFT 24
bogdanm 82:6473597d706e 7273 #define I2S_TCSR_FR_MASK 0x2000000u
bogdanm 82:6473597d706e 7274 #define I2S_TCSR_FR_SHIFT 25
bogdanm 82:6473597d706e 7275 #define I2S_TCSR_BCE_MASK 0x10000000u
bogdanm 82:6473597d706e 7276 #define I2S_TCSR_BCE_SHIFT 28
bogdanm 82:6473597d706e 7277 #define I2S_TCSR_DBGE_MASK 0x20000000u
bogdanm 82:6473597d706e 7278 #define I2S_TCSR_DBGE_SHIFT 29
bogdanm 82:6473597d706e 7279 #define I2S_TCSR_STOPE_MASK 0x40000000u
bogdanm 82:6473597d706e 7280 #define I2S_TCSR_STOPE_SHIFT 30
bogdanm 82:6473597d706e 7281 #define I2S_TCSR_TE_MASK 0x80000000u
bogdanm 82:6473597d706e 7282 #define I2S_TCSR_TE_SHIFT 31
bogdanm 82:6473597d706e 7283 /* TCR1 Bit Fields */
bogdanm 82:6473597d706e 7284 #define I2S_TCR1_TFW_MASK 0x7u
bogdanm 82:6473597d706e 7285 #define I2S_TCR1_TFW_SHIFT 0
bogdanm 82:6473597d706e 7286 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
bogdanm 82:6473597d706e 7287 /* TCR2 Bit Fields */
bogdanm 82:6473597d706e 7288 #define I2S_TCR2_DIV_MASK 0xFFu
bogdanm 82:6473597d706e 7289 #define I2S_TCR2_DIV_SHIFT 0
bogdanm 82:6473597d706e 7290 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
bogdanm 82:6473597d706e 7291 #define I2S_TCR2_BCD_MASK 0x1000000u
bogdanm 82:6473597d706e 7292 #define I2S_TCR2_BCD_SHIFT 24
bogdanm 82:6473597d706e 7293 #define I2S_TCR2_BCP_MASK 0x2000000u
bogdanm 82:6473597d706e 7294 #define I2S_TCR2_BCP_SHIFT 25
bogdanm 82:6473597d706e 7295 #define I2S_TCR2_MSEL_MASK 0xC000000u
bogdanm 82:6473597d706e 7296 #define I2S_TCR2_MSEL_SHIFT 26
bogdanm 82:6473597d706e 7297 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
bogdanm 82:6473597d706e 7298 #define I2S_TCR2_BCI_MASK 0x10000000u
bogdanm 82:6473597d706e 7299 #define I2S_TCR2_BCI_SHIFT 28
bogdanm 82:6473597d706e 7300 #define I2S_TCR2_BCS_MASK 0x20000000u
bogdanm 82:6473597d706e 7301 #define I2S_TCR2_BCS_SHIFT 29
bogdanm 82:6473597d706e 7302 #define I2S_TCR2_SYNC_MASK 0xC0000000u
bogdanm 82:6473597d706e 7303 #define I2S_TCR2_SYNC_SHIFT 30
bogdanm 82:6473597d706e 7304 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
bogdanm 82:6473597d706e 7305 /* TCR3 Bit Fields */
bogdanm 82:6473597d706e 7306 #define I2S_TCR3_WDFL_MASK 0x1Fu
bogdanm 82:6473597d706e 7307 #define I2S_TCR3_WDFL_SHIFT 0
bogdanm 82:6473597d706e 7308 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
bogdanm 82:6473597d706e 7309 #define I2S_TCR3_TCE_MASK 0x30000u
bogdanm 82:6473597d706e 7310 #define I2S_TCR3_TCE_SHIFT 16
bogdanm 82:6473597d706e 7311 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
bogdanm 82:6473597d706e 7312 /* TCR4 Bit Fields */
bogdanm 82:6473597d706e 7313 #define I2S_TCR4_FSD_MASK 0x1u
bogdanm 82:6473597d706e 7314 #define I2S_TCR4_FSD_SHIFT 0
bogdanm 82:6473597d706e 7315 #define I2S_TCR4_FSP_MASK 0x2u
bogdanm 82:6473597d706e 7316 #define I2S_TCR4_FSP_SHIFT 1
bogdanm 82:6473597d706e 7317 #define I2S_TCR4_FSE_MASK 0x8u
bogdanm 82:6473597d706e 7318 #define I2S_TCR4_FSE_SHIFT 3
bogdanm 82:6473597d706e 7319 #define I2S_TCR4_MF_MASK 0x10u
bogdanm 82:6473597d706e 7320 #define I2S_TCR4_MF_SHIFT 4
bogdanm 82:6473597d706e 7321 #define I2S_TCR4_SYWD_MASK 0x1F00u
bogdanm 82:6473597d706e 7322 #define I2S_TCR4_SYWD_SHIFT 8
bogdanm 82:6473597d706e 7323 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
bogdanm 82:6473597d706e 7324 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
bogdanm 82:6473597d706e 7325 #define I2S_TCR4_FRSZ_SHIFT 16
bogdanm 82:6473597d706e 7326 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
bogdanm 82:6473597d706e 7327 /* TCR5 Bit Fields */
bogdanm 82:6473597d706e 7328 #define I2S_TCR5_FBT_MASK 0x1F00u
bogdanm 82:6473597d706e 7329 #define I2S_TCR5_FBT_SHIFT 8
bogdanm 82:6473597d706e 7330 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
bogdanm 82:6473597d706e 7331 #define I2S_TCR5_W0W_MASK 0x1F0000u
bogdanm 82:6473597d706e 7332 #define I2S_TCR5_W0W_SHIFT 16
bogdanm 82:6473597d706e 7333 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
bogdanm 82:6473597d706e 7334 #define I2S_TCR5_WNW_MASK 0x1F000000u
bogdanm 82:6473597d706e 7335 #define I2S_TCR5_WNW_SHIFT 24
bogdanm 82:6473597d706e 7336 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
bogdanm 82:6473597d706e 7337 /* TDR Bit Fields */
bogdanm 82:6473597d706e 7338 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 7339 #define I2S_TDR_TDR_SHIFT 0
bogdanm 82:6473597d706e 7340 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
bogdanm 82:6473597d706e 7341 /* TFR Bit Fields */
bogdanm 82:6473597d706e 7342 #define I2S_TFR_RFP_MASK 0xFu
bogdanm 82:6473597d706e 7343 #define I2S_TFR_RFP_SHIFT 0
bogdanm 82:6473597d706e 7344 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
bogdanm 82:6473597d706e 7345 #define I2S_TFR_WFP_MASK 0xF0000u
bogdanm 82:6473597d706e 7346 #define I2S_TFR_WFP_SHIFT 16
bogdanm 82:6473597d706e 7347 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
bogdanm 82:6473597d706e 7348 /* TMR Bit Fields */
bogdanm 82:6473597d706e 7349 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 7350 #define I2S_TMR_TWM_SHIFT 0
bogdanm 82:6473597d706e 7351 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
bogdanm 82:6473597d706e 7352 /* RCSR Bit Fields */
bogdanm 82:6473597d706e 7353 #define I2S_RCSR_FRDE_MASK 0x1u
bogdanm 82:6473597d706e 7354 #define I2S_RCSR_FRDE_SHIFT 0
bogdanm 82:6473597d706e 7355 #define I2S_RCSR_FWDE_MASK 0x2u
bogdanm 82:6473597d706e 7356 #define I2S_RCSR_FWDE_SHIFT 1
bogdanm 82:6473597d706e 7357 #define I2S_RCSR_FRIE_MASK 0x100u
bogdanm 82:6473597d706e 7358 #define I2S_RCSR_FRIE_SHIFT 8
bogdanm 82:6473597d706e 7359 #define I2S_RCSR_FWIE_MASK 0x200u
bogdanm 82:6473597d706e 7360 #define I2S_RCSR_FWIE_SHIFT 9
bogdanm 82:6473597d706e 7361 #define I2S_RCSR_FEIE_MASK 0x400u
bogdanm 82:6473597d706e 7362 #define I2S_RCSR_FEIE_SHIFT 10
bogdanm 82:6473597d706e 7363 #define I2S_RCSR_SEIE_MASK 0x800u
bogdanm 82:6473597d706e 7364 #define I2S_RCSR_SEIE_SHIFT 11
bogdanm 82:6473597d706e 7365 #define I2S_RCSR_WSIE_MASK 0x1000u
bogdanm 82:6473597d706e 7366 #define I2S_RCSR_WSIE_SHIFT 12
bogdanm 82:6473597d706e 7367 #define I2S_RCSR_FRF_MASK 0x10000u
bogdanm 82:6473597d706e 7368 #define I2S_RCSR_FRF_SHIFT 16
bogdanm 82:6473597d706e 7369 #define I2S_RCSR_FWF_MASK 0x20000u
bogdanm 82:6473597d706e 7370 #define I2S_RCSR_FWF_SHIFT 17
bogdanm 82:6473597d706e 7371 #define I2S_RCSR_FEF_MASK 0x40000u
bogdanm 82:6473597d706e 7372 #define I2S_RCSR_FEF_SHIFT 18
bogdanm 82:6473597d706e 7373 #define I2S_RCSR_SEF_MASK 0x80000u
bogdanm 82:6473597d706e 7374 #define I2S_RCSR_SEF_SHIFT 19
bogdanm 82:6473597d706e 7375 #define I2S_RCSR_WSF_MASK 0x100000u
bogdanm 82:6473597d706e 7376 #define I2S_RCSR_WSF_SHIFT 20
bogdanm 82:6473597d706e 7377 #define I2S_RCSR_SR_MASK 0x1000000u
bogdanm 82:6473597d706e 7378 #define I2S_RCSR_SR_SHIFT 24
bogdanm 82:6473597d706e 7379 #define I2S_RCSR_FR_MASK 0x2000000u
bogdanm 82:6473597d706e 7380 #define I2S_RCSR_FR_SHIFT 25
bogdanm 82:6473597d706e 7381 #define I2S_RCSR_BCE_MASK 0x10000000u
bogdanm 82:6473597d706e 7382 #define I2S_RCSR_BCE_SHIFT 28
bogdanm 82:6473597d706e 7383 #define I2S_RCSR_DBGE_MASK 0x20000000u
bogdanm 82:6473597d706e 7384 #define I2S_RCSR_DBGE_SHIFT 29
bogdanm 82:6473597d706e 7385 #define I2S_RCSR_STOPE_MASK 0x40000000u
bogdanm 82:6473597d706e 7386 #define I2S_RCSR_STOPE_SHIFT 30
bogdanm 82:6473597d706e 7387 #define I2S_RCSR_RE_MASK 0x80000000u
bogdanm 82:6473597d706e 7388 #define I2S_RCSR_RE_SHIFT 31
bogdanm 82:6473597d706e 7389 /* RCR1 Bit Fields */
bogdanm 82:6473597d706e 7390 #define I2S_RCR1_RFW_MASK 0x7u
bogdanm 82:6473597d706e 7391 #define I2S_RCR1_RFW_SHIFT 0
bogdanm 82:6473597d706e 7392 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
bogdanm 82:6473597d706e 7393 /* RCR2 Bit Fields */
bogdanm 82:6473597d706e 7394 #define I2S_RCR2_DIV_MASK 0xFFu
bogdanm 82:6473597d706e 7395 #define I2S_RCR2_DIV_SHIFT 0
bogdanm 82:6473597d706e 7396 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
bogdanm 82:6473597d706e 7397 #define I2S_RCR2_BCD_MASK 0x1000000u
bogdanm 82:6473597d706e 7398 #define I2S_RCR2_BCD_SHIFT 24
bogdanm 82:6473597d706e 7399 #define I2S_RCR2_BCP_MASK 0x2000000u
bogdanm 82:6473597d706e 7400 #define I2S_RCR2_BCP_SHIFT 25
bogdanm 82:6473597d706e 7401 #define I2S_RCR2_MSEL_MASK 0xC000000u
bogdanm 82:6473597d706e 7402 #define I2S_RCR2_MSEL_SHIFT 26
bogdanm 82:6473597d706e 7403 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
bogdanm 82:6473597d706e 7404 #define I2S_RCR2_BCI_MASK 0x10000000u
bogdanm 82:6473597d706e 7405 #define I2S_RCR2_BCI_SHIFT 28
bogdanm 82:6473597d706e 7406 #define I2S_RCR2_BCS_MASK 0x20000000u
bogdanm 82:6473597d706e 7407 #define I2S_RCR2_BCS_SHIFT 29
bogdanm 82:6473597d706e 7408 #define I2S_RCR2_SYNC_MASK 0xC0000000u
bogdanm 82:6473597d706e 7409 #define I2S_RCR2_SYNC_SHIFT 30
bogdanm 82:6473597d706e 7410 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
bogdanm 82:6473597d706e 7411 /* RCR3 Bit Fields */
bogdanm 82:6473597d706e 7412 #define I2S_RCR3_WDFL_MASK 0x1Fu
bogdanm 82:6473597d706e 7413 #define I2S_RCR3_WDFL_SHIFT 0
bogdanm 82:6473597d706e 7414 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
bogdanm 82:6473597d706e 7415 #define I2S_RCR3_RCE_MASK 0x30000u
bogdanm 82:6473597d706e 7416 #define I2S_RCR3_RCE_SHIFT 16
bogdanm 82:6473597d706e 7417 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
bogdanm 82:6473597d706e 7418 /* RCR4 Bit Fields */
bogdanm 82:6473597d706e 7419 #define I2S_RCR4_FSD_MASK 0x1u
bogdanm 82:6473597d706e 7420 #define I2S_RCR4_FSD_SHIFT 0
bogdanm 82:6473597d706e 7421 #define I2S_RCR4_FSP_MASK 0x2u
bogdanm 82:6473597d706e 7422 #define I2S_RCR4_FSP_SHIFT 1
bogdanm 82:6473597d706e 7423 #define I2S_RCR4_FSE_MASK 0x8u
bogdanm 82:6473597d706e 7424 #define I2S_RCR4_FSE_SHIFT 3
bogdanm 82:6473597d706e 7425 #define I2S_RCR4_MF_MASK 0x10u
bogdanm 82:6473597d706e 7426 #define I2S_RCR4_MF_SHIFT 4
bogdanm 82:6473597d706e 7427 #define I2S_RCR4_SYWD_MASK 0x1F00u
bogdanm 82:6473597d706e 7428 #define I2S_RCR4_SYWD_SHIFT 8
bogdanm 82:6473597d706e 7429 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
bogdanm 82:6473597d706e 7430 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
bogdanm 82:6473597d706e 7431 #define I2S_RCR4_FRSZ_SHIFT 16
bogdanm 82:6473597d706e 7432 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
bogdanm 82:6473597d706e 7433 /* RCR5 Bit Fields */
bogdanm 82:6473597d706e 7434 #define I2S_RCR5_FBT_MASK 0x1F00u
bogdanm 82:6473597d706e 7435 #define I2S_RCR5_FBT_SHIFT 8
bogdanm 82:6473597d706e 7436 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
bogdanm 82:6473597d706e 7437 #define I2S_RCR5_W0W_MASK 0x1F0000u
bogdanm 82:6473597d706e 7438 #define I2S_RCR5_W0W_SHIFT 16
bogdanm 82:6473597d706e 7439 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
bogdanm 82:6473597d706e 7440 #define I2S_RCR5_WNW_MASK 0x1F000000u
bogdanm 82:6473597d706e 7441 #define I2S_RCR5_WNW_SHIFT 24
bogdanm 82:6473597d706e 7442 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
bogdanm 82:6473597d706e 7443 /* RDR Bit Fields */
bogdanm 82:6473597d706e 7444 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 7445 #define I2S_RDR_RDR_SHIFT 0
bogdanm 82:6473597d706e 7446 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
bogdanm 82:6473597d706e 7447 /* RFR Bit Fields */
bogdanm 82:6473597d706e 7448 #define I2S_RFR_RFP_MASK 0xFu
bogdanm 82:6473597d706e 7449 #define I2S_RFR_RFP_SHIFT 0
bogdanm 82:6473597d706e 7450 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
bogdanm 82:6473597d706e 7451 #define I2S_RFR_WFP_MASK 0xF0000u
bogdanm 82:6473597d706e 7452 #define I2S_RFR_WFP_SHIFT 16
bogdanm 82:6473597d706e 7453 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
bogdanm 82:6473597d706e 7454 /* RMR Bit Fields */
bogdanm 82:6473597d706e 7455 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 7456 #define I2S_RMR_RWM_SHIFT 0
bogdanm 82:6473597d706e 7457 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
bogdanm 82:6473597d706e 7458 /* MCR Bit Fields */
bogdanm 82:6473597d706e 7459 #define I2S_MCR_MICS_MASK 0x3000000u
bogdanm 82:6473597d706e 7460 #define I2S_MCR_MICS_SHIFT 24
bogdanm 82:6473597d706e 7461 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
bogdanm 82:6473597d706e 7462 #define I2S_MCR_MOE_MASK 0x40000000u
bogdanm 82:6473597d706e 7463 #define I2S_MCR_MOE_SHIFT 30
bogdanm 82:6473597d706e 7464 #define I2S_MCR_DUF_MASK 0x80000000u
bogdanm 82:6473597d706e 7465 #define I2S_MCR_DUF_SHIFT 31
bogdanm 82:6473597d706e 7466 /* MDR Bit Fields */
bogdanm 82:6473597d706e 7467 #define I2S_MDR_DIVIDE_MASK 0xFFFu
bogdanm 82:6473597d706e 7468 #define I2S_MDR_DIVIDE_SHIFT 0
bogdanm 82:6473597d706e 7469 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
bogdanm 82:6473597d706e 7470 #define I2S_MDR_FRACT_MASK 0xFF000u
bogdanm 82:6473597d706e 7471 #define I2S_MDR_FRACT_SHIFT 12
bogdanm 82:6473597d706e 7472 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
bogdanm 82:6473597d706e 7473
bogdanm 82:6473597d706e 7474 /*!
bogdanm 82:6473597d706e 7475 * @}
bogdanm 82:6473597d706e 7476 */ /* end of group I2S_Register_Masks */
bogdanm 82:6473597d706e 7477
bogdanm 82:6473597d706e 7478
bogdanm 82:6473597d706e 7479 /* I2S - Peripheral instance base addresses */
bogdanm 82:6473597d706e 7480 /** Peripheral I2S0 base address */
bogdanm 82:6473597d706e 7481 #define I2S0_BASE (0x4002F000u)
bogdanm 82:6473597d706e 7482 /** Peripheral I2S0 base pointer */
bogdanm 82:6473597d706e 7483 #define I2S0 ((I2S_Type *)I2S0_BASE)
bogdanm 82:6473597d706e 7484 #define I2S0_BASE_PTR (I2S0)
bogdanm 82:6473597d706e 7485 /** Array initializer of I2S peripheral base pointers */
bogdanm 82:6473597d706e 7486 #define I2S_BASES { I2S0 }
bogdanm 82:6473597d706e 7487
bogdanm 82:6473597d706e 7488 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7489 -- I2S - Register accessor macros
bogdanm 82:6473597d706e 7490 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7491
bogdanm 82:6473597d706e 7492 /*!
bogdanm 82:6473597d706e 7493 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
bogdanm 82:6473597d706e 7494 * @{
bogdanm 82:6473597d706e 7495 */
bogdanm 82:6473597d706e 7496
bogdanm 82:6473597d706e 7497
bogdanm 82:6473597d706e 7498 /* I2S - Register instance definitions */
bogdanm 82:6473597d706e 7499 /* I2S0 */
bogdanm 82:6473597d706e 7500 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
bogdanm 82:6473597d706e 7501 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
bogdanm 82:6473597d706e 7502 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
bogdanm 82:6473597d706e 7503 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
bogdanm 82:6473597d706e 7504 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
bogdanm 82:6473597d706e 7505 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
bogdanm 82:6473597d706e 7506 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
bogdanm 82:6473597d706e 7507 #define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
bogdanm 82:6473597d706e 7508 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
bogdanm 82:6473597d706e 7509 #define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
bogdanm 82:6473597d706e 7510 #define I2S0_TMR I2S_TMR_REG(I2S0)
bogdanm 82:6473597d706e 7511 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
bogdanm 82:6473597d706e 7512 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
bogdanm 82:6473597d706e 7513 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
bogdanm 82:6473597d706e 7514 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
bogdanm 82:6473597d706e 7515 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
bogdanm 82:6473597d706e 7516 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
bogdanm 82:6473597d706e 7517 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
bogdanm 82:6473597d706e 7518 #define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
bogdanm 82:6473597d706e 7519 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
bogdanm 82:6473597d706e 7520 #define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
bogdanm 82:6473597d706e 7521 #define I2S0_RMR I2S_RMR_REG(I2S0)
bogdanm 82:6473597d706e 7522 #define I2S0_MCR I2S_MCR_REG(I2S0)
bogdanm 82:6473597d706e 7523 #define I2S0_MDR I2S_MDR_REG(I2S0)
bogdanm 82:6473597d706e 7524
bogdanm 82:6473597d706e 7525 /* I2S - Register array accessors */
bogdanm 82:6473597d706e 7526 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
bogdanm 82:6473597d706e 7527 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
bogdanm 82:6473597d706e 7528 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
bogdanm 82:6473597d706e 7529 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
bogdanm 82:6473597d706e 7530
bogdanm 82:6473597d706e 7531 /*!
bogdanm 82:6473597d706e 7532 * @}
bogdanm 82:6473597d706e 7533 */ /* end of group I2S_Register_Accessor_Macros */
bogdanm 82:6473597d706e 7534
bogdanm 82:6473597d706e 7535
bogdanm 82:6473597d706e 7536 /*!
bogdanm 82:6473597d706e 7537 * @}
bogdanm 82:6473597d706e 7538 */ /* end of group I2S_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 7539
bogdanm 82:6473597d706e 7540
bogdanm 82:6473597d706e 7541 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7542 -- LLWU Peripheral Access Layer
bogdanm 82:6473597d706e 7543 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7544
bogdanm 82:6473597d706e 7545 /*!
bogdanm 82:6473597d706e 7546 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
bogdanm 82:6473597d706e 7547 * @{
bogdanm 82:6473597d706e 7548 */
bogdanm 82:6473597d706e 7549
bogdanm 82:6473597d706e 7550 /** LLWU - Register Layout Typedef */
bogdanm 82:6473597d706e 7551 typedef struct {
bogdanm 82:6473597d706e 7552 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
bogdanm 82:6473597d706e 7553 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
bogdanm 82:6473597d706e 7554 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
bogdanm 82:6473597d706e 7555 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
bogdanm 82:6473597d706e 7556 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
bogdanm 82:6473597d706e 7557 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
bogdanm 82:6473597d706e 7558 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
bogdanm 82:6473597d706e 7559 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
bogdanm 82:6473597d706e 7560 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
bogdanm 82:6473597d706e 7561 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
bogdanm 82:6473597d706e 7562 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
bogdanm 82:6473597d706e 7563 } LLWU_Type, *LLWU_MemMapPtr;
bogdanm 82:6473597d706e 7564
bogdanm 82:6473597d706e 7565 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7566 -- LLWU - Register accessor macros
bogdanm 82:6473597d706e 7567 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7568
bogdanm 82:6473597d706e 7569 /*!
bogdanm 82:6473597d706e 7570 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
bogdanm 82:6473597d706e 7571 * @{
bogdanm 82:6473597d706e 7572 */
bogdanm 82:6473597d706e 7573
bogdanm 82:6473597d706e 7574
bogdanm 82:6473597d706e 7575 /* LLWU - Register accessors */
bogdanm 82:6473597d706e 7576 #define LLWU_PE1_REG(base) ((base)->PE1)
bogdanm 82:6473597d706e 7577 #define LLWU_PE2_REG(base) ((base)->PE2)
bogdanm 82:6473597d706e 7578 #define LLWU_PE3_REG(base) ((base)->PE3)
bogdanm 82:6473597d706e 7579 #define LLWU_PE4_REG(base) ((base)->PE4)
bogdanm 82:6473597d706e 7580 #define LLWU_ME_REG(base) ((base)->ME)
bogdanm 82:6473597d706e 7581 #define LLWU_F1_REG(base) ((base)->F1)
bogdanm 82:6473597d706e 7582 #define LLWU_F2_REG(base) ((base)->F2)
bogdanm 82:6473597d706e 7583 #define LLWU_F3_REG(base) ((base)->F3)
bogdanm 82:6473597d706e 7584 #define LLWU_FILT1_REG(base) ((base)->FILT1)
bogdanm 82:6473597d706e 7585 #define LLWU_FILT2_REG(base) ((base)->FILT2)
bogdanm 82:6473597d706e 7586 #define LLWU_RST_REG(base) ((base)->RST)
bogdanm 82:6473597d706e 7587
bogdanm 82:6473597d706e 7588 /*!
bogdanm 82:6473597d706e 7589 * @}
bogdanm 82:6473597d706e 7590 */ /* end of group LLWU_Register_Accessor_Macros */
bogdanm 82:6473597d706e 7591
bogdanm 82:6473597d706e 7592
bogdanm 82:6473597d706e 7593 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7594 -- LLWU Register Masks
bogdanm 82:6473597d706e 7595 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7596
bogdanm 82:6473597d706e 7597 /*!
bogdanm 82:6473597d706e 7598 * @addtogroup LLWU_Register_Masks LLWU Register Masks
bogdanm 82:6473597d706e 7599 * @{
bogdanm 82:6473597d706e 7600 */
bogdanm 82:6473597d706e 7601
bogdanm 82:6473597d706e 7602 /* PE1 Bit Fields */
bogdanm 82:6473597d706e 7603 #define LLWU_PE1_WUPE0_MASK 0x3u
bogdanm 82:6473597d706e 7604 #define LLWU_PE1_WUPE0_SHIFT 0
bogdanm 82:6473597d706e 7605 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
bogdanm 82:6473597d706e 7606 #define LLWU_PE1_WUPE1_MASK 0xCu
bogdanm 82:6473597d706e 7607 #define LLWU_PE1_WUPE1_SHIFT 2
bogdanm 82:6473597d706e 7608 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
bogdanm 82:6473597d706e 7609 #define LLWU_PE1_WUPE2_MASK 0x30u
bogdanm 82:6473597d706e 7610 #define LLWU_PE1_WUPE2_SHIFT 4
bogdanm 82:6473597d706e 7611 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
bogdanm 82:6473597d706e 7612 #define LLWU_PE1_WUPE3_MASK 0xC0u
bogdanm 82:6473597d706e 7613 #define LLWU_PE1_WUPE3_SHIFT 6
bogdanm 82:6473597d706e 7614 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
bogdanm 82:6473597d706e 7615 /* PE2 Bit Fields */
bogdanm 82:6473597d706e 7616 #define LLWU_PE2_WUPE4_MASK 0x3u
bogdanm 82:6473597d706e 7617 #define LLWU_PE2_WUPE4_SHIFT 0
bogdanm 82:6473597d706e 7618 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
bogdanm 82:6473597d706e 7619 #define LLWU_PE2_WUPE5_MASK 0xCu
bogdanm 82:6473597d706e 7620 #define LLWU_PE2_WUPE5_SHIFT 2
bogdanm 82:6473597d706e 7621 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
bogdanm 82:6473597d706e 7622 #define LLWU_PE2_WUPE6_MASK 0x30u
bogdanm 82:6473597d706e 7623 #define LLWU_PE2_WUPE6_SHIFT 4
bogdanm 82:6473597d706e 7624 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
bogdanm 82:6473597d706e 7625 #define LLWU_PE2_WUPE7_MASK 0xC0u
bogdanm 82:6473597d706e 7626 #define LLWU_PE2_WUPE7_SHIFT 6
bogdanm 82:6473597d706e 7627 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
bogdanm 82:6473597d706e 7628 /* PE3 Bit Fields */
bogdanm 82:6473597d706e 7629 #define LLWU_PE3_WUPE8_MASK 0x3u
bogdanm 82:6473597d706e 7630 #define LLWU_PE3_WUPE8_SHIFT 0
bogdanm 82:6473597d706e 7631 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
bogdanm 82:6473597d706e 7632 #define LLWU_PE3_WUPE9_MASK 0xCu
bogdanm 82:6473597d706e 7633 #define LLWU_PE3_WUPE9_SHIFT 2
bogdanm 82:6473597d706e 7634 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
bogdanm 82:6473597d706e 7635 #define LLWU_PE3_WUPE10_MASK 0x30u
bogdanm 82:6473597d706e 7636 #define LLWU_PE3_WUPE10_SHIFT 4
bogdanm 82:6473597d706e 7637 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
bogdanm 82:6473597d706e 7638 #define LLWU_PE3_WUPE11_MASK 0xC0u
bogdanm 82:6473597d706e 7639 #define LLWU_PE3_WUPE11_SHIFT 6
bogdanm 82:6473597d706e 7640 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
bogdanm 82:6473597d706e 7641 /* PE4 Bit Fields */
bogdanm 82:6473597d706e 7642 #define LLWU_PE4_WUPE12_MASK 0x3u
bogdanm 82:6473597d706e 7643 #define LLWU_PE4_WUPE12_SHIFT 0
bogdanm 82:6473597d706e 7644 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
bogdanm 82:6473597d706e 7645 #define LLWU_PE4_WUPE13_MASK 0xCu
bogdanm 82:6473597d706e 7646 #define LLWU_PE4_WUPE13_SHIFT 2
bogdanm 82:6473597d706e 7647 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
bogdanm 82:6473597d706e 7648 #define LLWU_PE4_WUPE14_MASK 0x30u
bogdanm 82:6473597d706e 7649 #define LLWU_PE4_WUPE14_SHIFT 4
bogdanm 82:6473597d706e 7650 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
bogdanm 82:6473597d706e 7651 #define LLWU_PE4_WUPE15_MASK 0xC0u
bogdanm 82:6473597d706e 7652 #define LLWU_PE4_WUPE15_SHIFT 6
bogdanm 82:6473597d706e 7653 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
bogdanm 82:6473597d706e 7654 /* ME Bit Fields */
bogdanm 82:6473597d706e 7655 #define LLWU_ME_WUME0_MASK 0x1u
bogdanm 82:6473597d706e 7656 #define LLWU_ME_WUME0_SHIFT 0
bogdanm 82:6473597d706e 7657 #define LLWU_ME_WUME1_MASK 0x2u
bogdanm 82:6473597d706e 7658 #define LLWU_ME_WUME1_SHIFT 1
bogdanm 82:6473597d706e 7659 #define LLWU_ME_WUME2_MASK 0x4u
bogdanm 82:6473597d706e 7660 #define LLWU_ME_WUME2_SHIFT 2
bogdanm 82:6473597d706e 7661 #define LLWU_ME_WUME3_MASK 0x8u
bogdanm 82:6473597d706e 7662 #define LLWU_ME_WUME3_SHIFT 3
bogdanm 82:6473597d706e 7663 #define LLWU_ME_WUME4_MASK 0x10u
bogdanm 82:6473597d706e 7664 #define LLWU_ME_WUME4_SHIFT 4
bogdanm 82:6473597d706e 7665 #define LLWU_ME_WUME5_MASK 0x20u
bogdanm 82:6473597d706e 7666 #define LLWU_ME_WUME5_SHIFT 5
bogdanm 82:6473597d706e 7667 #define LLWU_ME_WUME6_MASK 0x40u
bogdanm 82:6473597d706e 7668 #define LLWU_ME_WUME6_SHIFT 6
bogdanm 82:6473597d706e 7669 #define LLWU_ME_WUME7_MASK 0x80u
bogdanm 82:6473597d706e 7670 #define LLWU_ME_WUME7_SHIFT 7
bogdanm 82:6473597d706e 7671 /* F1 Bit Fields */
bogdanm 82:6473597d706e 7672 #define LLWU_F1_WUF0_MASK 0x1u
bogdanm 82:6473597d706e 7673 #define LLWU_F1_WUF0_SHIFT 0
bogdanm 82:6473597d706e 7674 #define LLWU_F1_WUF1_MASK 0x2u
bogdanm 82:6473597d706e 7675 #define LLWU_F1_WUF1_SHIFT 1
bogdanm 82:6473597d706e 7676 #define LLWU_F1_WUF2_MASK 0x4u
bogdanm 82:6473597d706e 7677 #define LLWU_F1_WUF2_SHIFT 2
bogdanm 82:6473597d706e 7678 #define LLWU_F1_WUF3_MASK 0x8u
bogdanm 82:6473597d706e 7679 #define LLWU_F1_WUF3_SHIFT 3
bogdanm 82:6473597d706e 7680 #define LLWU_F1_WUF4_MASK 0x10u
bogdanm 82:6473597d706e 7681 #define LLWU_F1_WUF4_SHIFT 4
bogdanm 82:6473597d706e 7682 #define LLWU_F1_WUF5_MASK 0x20u
bogdanm 82:6473597d706e 7683 #define LLWU_F1_WUF5_SHIFT 5
bogdanm 82:6473597d706e 7684 #define LLWU_F1_WUF6_MASK 0x40u
bogdanm 82:6473597d706e 7685 #define LLWU_F1_WUF6_SHIFT 6
bogdanm 82:6473597d706e 7686 #define LLWU_F1_WUF7_MASK 0x80u
bogdanm 82:6473597d706e 7687 #define LLWU_F1_WUF7_SHIFT 7
bogdanm 82:6473597d706e 7688 /* F2 Bit Fields */
bogdanm 82:6473597d706e 7689 #define LLWU_F2_WUF8_MASK 0x1u
bogdanm 82:6473597d706e 7690 #define LLWU_F2_WUF8_SHIFT 0
bogdanm 82:6473597d706e 7691 #define LLWU_F2_WUF9_MASK 0x2u
bogdanm 82:6473597d706e 7692 #define LLWU_F2_WUF9_SHIFT 1
bogdanm 82:6473597d706e 7693 #define LLWU_F2_WUF10_MASK 0x4u
bogdanm 82:6473597d706e 7694 #define LLWU_F2_WUF10_SHIFT 2
bogdanm 82:6473597d706e 7695 #define LLWU_F2_WUF11_MASK 0x8u
bogdanm 82:6473597d706e 7696 #define LLWU_F2_WUF11_SHIFT 3
bogdanm 82:6473597d706e 7697 #define LLWU_F2_WUF12_MASK 0x10u
bogdanm 82:6473597d706e 7698 #define LLWU_F2_WUF12_SHIFT 4
bogdanm 82:6473597d706e 7699 #define LLWU_F2_WUF13_MASK 0x20u
bogdanm 82:6473597d706e 7700 #define LLWU_F2_WUF13_SHIFT 5
bogdanm 82:6473597d706e 7701 #define LLWU_F2_WUF14_MASK 0x40u
bogdanm 82:6473597d706e 7702 #define LLWU_F2_WUF14_SHIFT 6
bogdanm 82:6473597d706e 7703 #define LLWU_F2_WUF15_MASK 0x80u
bogdanm 82:6473597d706e 7704 #define LLWU_F2_WUF15_SHIFT 7
bogdanm 82:6473597d706e 7705 /* F3 Bit Fields */
bogdanm 82:6473597d706e 7706 #define LLWU_F3_MWUF0_MASK 0x1u
bogdanm 82:6473597d706e 7707 #define LLWU_F3_MWUF0_SHIFT 0
bogdanm 82:6473597d706e 7708 #define LLWU_F3_MWUF1_MASK 0x2u
bogdanm 82:6473597d706e 7709 #define LLWU_F3_MWUF1_SHIFT 1
bogdanm 82:6473597d706e 7710 #define LLWU_F3_MWUF2_MASK 0x4u
bogdanm 82:6473597d706e 7711 #define LLWU_F3_MWUF2_SHIFT 2
bogdanm 82:6473597d706e 7712 #define LLWU_F3_MWUF3_MASK 0x8u
bogdanm 82:6473597d706e 7713 #define LLWU_F3_MWUF3_SHIFT 3
bogdanm 82:6473597d706e 7714 #define LLWU_F3_MWUF4_MASK 0x10u
bogdanm 82:6473597d706e 7715 #define LLWU_F3_MWUF4_SHIFT 4
bogdanm 82:6473597d706e 7716 #define LLWU_F3_MWUF5_MASK 0x20u
bogdanm 82:6473597d706e 7717 #define LLWU_F3_MWUF5_SHIFT 5
bogdanm 82:6473597d706e 7718 #define LLWU_F3_MWUF6_MASK 0x40u
bogdanm 82:6473597d706e 7719 #define LLWU_F3_MWUF6_SHIFT 6
bogdanm 82:6473597d706e 7720 #define LLWU_F3_MWUF7_MASK 0x80u
bogdanm 82:6473597d706e 7721 #define LLWU_F3_MWUF7_SHIFT 7
bogdanm 82:6473597d706e 7722 /* FILT1 Bit Fields */
bogdanm 82:6473597d706e 7723 #define LLWU_FILT1_FILTSEL_MASK 0xFu
bogdanm 82:6473597d706e 7724 #define LLWU_FILT1_FILTSEL_SHIFT 0
bogdanm 82:6473597d706e 7725 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
bogdanm 82:6473597d706e 7726 #define LLWU_FILT1_FILTE_MASK 0x60u
bogdanm 82:6473597d706e 7727 #define LLWU_FILT1_FILTE_SHIFT 5
bogdanm 82:6473597d706e 7728 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
bogdanm 82:6473597d706e 7729 #define LLWU_FILT1_FILTF_MASK 0x80u
bogdanm 82:6473597d706e 7730 #define LLWU_FILT1_FILTF_SHIFT 7
bogdanm 82:6473597d706e 7731 /* FILT2 Bit Fields */
bogdanm 82:6473597d706e 7732 #define LLWU_FILT2_FILTSEL_MASK 0xFu
bogdanm 82:6473597d706e 7733 #define LLWU_FILT2_FILTSEL_SHIFT 0
bogdanm 82:6473597d706e 7734 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
bogdanm 82:6473597d706e 7735 #define LLWU_FILT2_FILTE_MASK 0x60u
bogdanm 82:6473597d706e 7736 #define LLWU_FILT2_FILTE_SHIFT 5
bogdanm 82:6473597d706e 7737 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
bogdanm 82:6473597d706e 7738 #define LLWU_FILT2_FILTF_MASK 0x80u
bogdanm 82:6473597d706e 7739 #define LLWU_FILT2_FILTF_SHIFT 7
bogdanm 82:6473597d706e 7740 /* RST Bit Fields */
bogdanm 82:6473597d706e 7741 #define LLWU_RST_RSTFILT_MASK 0x1u
bogdanm 82:6473597d706e 7742 #define LLWU_RST_RSTFILT_SHIFT 0
bogdanm 82:6473597d706e 7743 #define LLWU_RST_LLRSTE_MASK 0x2u
bogdanm 82:6473597d706e 7744 #define LLWU_RST_LLRSTE_SHIFT 1
bogdanm 82:6473597d706e 7745
bogdanm 82:6473597d706e 7746 /*!
bogdanm 82:6473597d706e 7747 * @}
bogdanm 82:6473597d706e 7748 */ /* end of group LLWU_Register_Masks */
bogdanm 82:6473597d706e 7749
bogdanm 82:6473597d706e 7750
bogdanm 82:6473597d706e 7751 /* LLWU - Peripheral instance base addresses */
bogdanm 82:6473597d706e 7752 /** Peripheral LLWU base address */
bogdanm 82:6473597d706e 7753 #define LLWU_BASE (0x4007C000u)
bogdanm 82:6473597d706e 7754 /** Peripheral LLWU base pointer */
bogdanm 82:6473597d706e 7755 #define LLWU ((LLWU_Type *)LLWU_BASE)
bogdanm 82:6473597d706e 7756 #define LLWU_BASE_PTR (LLWU)
bogdanm 82:6473597d706e 7757 /** Array initializer of LLWU peripheral base pointers */
bogdanm 82:6473597d706e 7758 #define LLWU_BASES { LLWU }
bogdanm 82:6473597d706e 7759
bogdanm 82:6473597d706e 7760 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7761 -- LLWU - Register accessor macros
bogdanm 82:6473597d706e 7762 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7763
bogdanm 82:6473597d706e 7764 /*!
bogdanm 82:6473597d706e 7765 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
bogdanm 82:6473597d706e 7766 * @{
bogdanm 82:6473597d706e 7767 */
bogdanm 82:6473597d706e 7768
bogdanm 82:6473597d706e 7769
bogdanm 82:6473597d706e 7770 /* LLWU - Register instance definitions */
bogdanm 82:6473597d706e 7771 /* LLWU */
bogdanm 82:6473597d706e 7772 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
bogdanm 82:6473597d706e 7773 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
bogdanm 82:6473597d706e 7774 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
bogdanm 82:6473597d706e 7775 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
bogdanm 82:6473597d706e 7776 #define LLWU_ME LLWU_ME_REG(LLWU)
bogdanm 82:6473597d706e 7777 #define LLWU_F1 LLWU_F1_REG(LLWU)
bogdanm 82:6473597d706e 7778 #define LLWU_F2 LLWU_F2_REG(LLWU)
bogdanm 82:6473597d706e 7779 #define LLWU_F3 LLWU_F3_REG(LLWU)
bogdanm 82:6473597d706e 7780 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
bogdanm 82:6473597d706e 7781 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
bogdanm 82:6473597d706e 7782 #define LLWU_RST LLWU_RST_REG(LLWU)
bogdanm 82:6473597d706e 7783
bogdanm 82:6473597d706e 7784 /*!
bogdanm 82:6473597d706e 7785 * @}
bogdanm 82:6473597d706e 7786 */ /* end of group LLWU_Register_Accessor_Macros */
bogdanm 82:6473597d706e 7787
bogdanm 82:6473597d706e 7788
bogdanm 82:6473597d706e 7789 /*!
bogdanm 82:6473597d706e 7790 * @}
bogdanm 82:6473597d706e 7791 */ /* end of group LLWU_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 7792
bogdanm 82:6473597d706e 7793
bogdanm 82:6473597d706e 7794 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7795 -- LPTMR Peripheral Access Layer
bogdanm 82:6473597d706e 7796 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7797
bogdanm 82:6473597d706e 7798 /*!
bogdanm 82:6473597d706e 7799 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
bogdanm 82:6473597d706e 7800 * @{
bogdanm 82:6473597d706e 7801 */
bogdanm 82:6473597d706e 7802
bogdanm 82:6473597d706e 7803 /** LPTMR - Register Layout Typedef */
bogdanm 82:6473597d706e 7804 typedef struct {
bogdanm 82:6473597d706e 7805 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
bogdanm 82:6473597d706e 7806 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
bogdanm 82:6473597d706e 7807 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
bogdanm 82:6473597d706e 7808 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
bogdanm 82:6473597d706e 7809 } LPTMR_Type, *LPTMR_MemMapPtr;
bogdanm 82:6473597d706e 7810
bogdanm 82:6473597d706e 7811 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7812 -- LPTMR - Register accessor macros
bogdanm 82:6473597d706e 7813 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7814
bogdanm 82:6473597d706e 7815 /*!
bogdanm 82:6473597d706e 7816 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
bogdanm 82:6473597d706e 7817 * @{
bogdanm 82:6473597d706e 7818 */
bogdanm 82:6473597d706e 7819
bogdanm 82:6473597d706e 7820
bogdanm 82:6473597d706e 7821 /* LPTMR - Register accessors */
bogdanm 82:6473597d706e 7822 #define LPTMR_CSR_REG(base) ((base)->CSR)
bogdanm 82:6473597d706e 7823 #define LPTMR_PSR_REG(base) ((base)->PSR)
bogdanm 82:6473597d706e 7824 #define LPTMR_CMR_REG(base) ((base)->CMR)
bogdanm 82:6473597d706e 7825 #define LPTMR_CNR_REG(base) ((base)->CNR)
bogdanm 82:6473597d706e 7826
bogdanm 82:6473597d706e 7827 /*!
bogdanm 82:6473597d706e 7828 * @}
bogdanm 82:6473597d706e 7829 */ /* end of group LPTMR_Register_Accessor_Macros */
bogdanm 82:6473597d706e 7830
bogdanm 82:6473597d706e 7831
bogdanm 82:6473597d706e 7832 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7833 -- LPTMR Register Masks
bogdanm 82:6473597d706e 7834 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7835
bogdanm 82:6473597d706e 7836 /*!
bogdanm 82:6473597d706e 7837 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
bogdanm 82:6473597d706e 7838 * @{
bogdanm 82:6473597d706e 7839 */
bogdanm 82:6473597d706e 7840
bogdanm 82:6473597d706e 7841 /* CSR Bit Fields */
bogdanm 82:6473597d706e 7842 #define LPTMR_CSR_TEN_MASK 0x1u
bogdanm 82:6473597d706e 7843 #define LPTMR_CSR_TEN_SHIFT 0
bogdanm 82:6473597d706e 7844 #define LPTMR_CSR_TMS_MASK 0x2u
bogdanm 82:6473597d706e 7845 #define LPTMR_CSR_TMS_SHIFT 1
bogdanm 82:6473597d706e 7846 #define LPTMR_CSR_TFC_MASK 0x4u
bogdanm 82:6473597d706e 7847 #define LPTMR_CSR_TFC_SHIFT 2
bogdanm 82:6473597d706e 7848 #define LPTMR_CSR_TPP_MASK 0x8u
bogdanm 82:6473597d706e 7849 #define LPTMR_CSR_TPP_SHIFT 3
bogdanm 82:6473597d706e 7850 #define LPTMR_CSR_TPS_MASK 0x30u
bogdanm 82:6473597d706e 7851 #define LPTMR_CSR_TPS_SHIFT 4
bogdanm 82:6473597d706e 7852 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
bogdanm 82:6473597d706e 7853 #define LPTMR_CSR_TIE_MASK 0x40u
bogdanm 82:6473597d706e 7854 #define LPTMR_CSR_TIE_SHIFT 6
bogdanm 82:6473597d706e 7855 #define LPTMR_CSR_TCF_MASK 0x80u
bogdanm 82:6473597d706e 7856 #define LPTMR_CSR_TCF_SHIFT 7
bogdanm 82:6473597d706e 7857 /* PSR Bit Fields */
bogdanm 82:6473597d706e 7858 #define LPTMR_PSR_PCS_MASK 0x3u
bogdanm 82:6473597d706e 7859 #define LPTMR_PSR_PCS_SHIFT 0
bogdanm 82:6473597d706e 7860 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
bogdanm 82:6473597d706e 7861 #define LPTMR_PSR_PBYP_MASK 0x4u
bogdanm 82:6473597d706e 7862 #define LPTMR_PSR_PBYP_SHIFT 2
bogdanm 82:6473597d706e 7863 #define LPTMR_PSR_PRESCALE_MASK 0x78u
bogdanm 82:6473597d706e 7864 #define LPTMR_PSR_PRESCALE_SHIFT 3
bogdanm 82:6473597d706e 7865 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
bogdanm 82:6473597d706e 7866 /* CMR Bit Fields */
bogdanm 82:6473597d706e 7867 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
bogdanm 82:6473597d706e 7868 #define LPTMR_CMR_COMPARE_SHIFT 0
bogdanm 82:6473597d706e 7869 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
bogdanm 82:6473597d706e 7870 /* CNR Bit Fields */
bogdanm 82:6473597d706e 7871 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
bogdanm 82:6473597d706e 7872 #define LPTMR_CNR_COUNTER_SHIFT 0
bogdanm 82:6473597d706e 7873 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
bogdanm 82:6473597d706e 7874
bogdanm 82:6473597d706e 7875 /*!
bogdanm 82:6473597d706e 7876 * @}
bogdanm 82:6473597d706e 7877 */ /* end of group LPTMR_Register_Masks */
bogdanm 82:6473597d706e 7878
bogdanm 82:6473597d706e 7879
bogdanm 82:6473597d706e 7880 /* LPTMR - Peripheral instance base addresses */
bogdanm 82:6473597d706e 7881 /** Peripheral LPTMR0 base address */
bogdanm 82:6473597d706e 7882 #define LPTMR0_BASE (0x40040000u)
bogdanm 82:6473597d706e 7883 /** Peripheral LPTMR0 base pointer */
bogdanm 82:6473597d706e 7884 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
bogdanm 82:6473597d706e 7885 #define LPTMR0_BASE_PTR (LPTMR0)
bogdanm 82:6473597d706e 7886 /** Array initializer of LPTMR peripheral base pointers */
bogdanm 82:6473597d706e 7887 #define LPTMR_BASES { LPTMR0 }
bogdanm 82:6473597d706e 7888
bogdanm 82:6473597d706e 7889 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7890 -- LPTMR - Register accessor macros
bogdanm 82:6473597d706e 7891 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7892
bogdanm 82:6473597d706e 7893 /*!
bogdanm 82:6473597d706e 7894 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
bogdanm 82:6473597d706e 7895 * @{
bogdanm 82:6473597d706e 7896 */
bogdanm 82:6473597d706e 7897
bogdanm 82:6473597d706e 7898
bogdanm 82:6473597d706e 7899 /* LPTMR - Register instance definitions */
bogdanm 82:6473597d706e 7900 /* LPTMR0 */
bogdanm 82:6473597d706e 7901 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
bogdanm 82:6473597d706e 7902 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
bogdanm 82:6473597d706e 7903 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
bogdanm 82:6473597d706e 7904 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
bogdanm 82:6473597d706e 7905
bogdanm 82:6473597d706e 7906 /*!
bogdanm 82:6473597d706e 7907 * @}
bogdanm 82:6473597d706e 7908 */ /* end of group LPTMR_Register_Accessor_Macros */
bogdanm 82:6473597d706e 7909
bogdanm 82:6473597d706e 7910
bogdanm 82:6473597d706e 7911 /*!
bogdanm 82:6473597d706e 7912 * @}
bogdanm 82:6473597d706e 7913 */ /* end of group LPTMR_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 7914
bogdanm 82:6473597d706e 7915
bogdanm 82:6473597d706e 7916 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7917 -- MCG Peripheral Access Layer
bogdanm 82:6473597d706e 7918 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7919
bogdanm 82:6473597d706e 7920 /*!
bogdanm 82:6473597d706e 7921 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
bogdanm 82:6473597d706e 7922 * @{
bogdanm 82:6473597d706e 7923 */
bogdanm 82:6473597d706e 7924
bogdanm 82:6473597d706e 7925 /** MCG - Register Layout Typedef */
bogdanm 82:6473597d706e 7926 typedef struct {
bogdanm 82:6473597d706e 7927 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
bogdanm 82:6473597d706e 7928 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
bogdanm 82:6473597d706e 7929 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
bogdanm 82:6473597d706e 7930 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
bogdanm 82:6473597d706e 7931 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
bogdanm 82:6473597d706e 7932 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
bogdanm 82:6473597d706e 7933 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
bogdanm 82:6473597d706e 7934 uint8_t RESERVED_0[1];
bogdanm 82:6473597d706e 7935 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
bogdanm 82:6473597d706e 7936 uint8_t RESERVED_1[1];
bogdanm 82:6473597d706e 7937 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
bogdanm 82:6473597d706e 7938 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
bogdanm 82:6473597d706e 7939 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
bogdanm 82:6473597d706e 7940 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
bogdanm 82:6473597d706e 7941 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
bogdanm 82:6473597d706e 7942 } MCG_Type, *MCG_MemMapPtr;
bogdanm 82:6473597d706e 7943
bogdanm 82:6473597d706e 7944 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7945 -- MCG - Register accessor macros
bogdanm 82:6473597d706e 7946 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7947
bogdanm 82:6473597d706e 7948 /*!
bogdanm 82:6473597d706e 7949 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
bogdanm 82:6473597d706e 7950 * @{
bogdanm 82:6473597d706e 7951 */
bogdanm 82:6473597d706e 7952
bogdanm 82:6473597d706e 7953
bogdanm 82:6473597d706e 7954 /* MCG - Register accessors */
bogdanm 82:6473597d706e 7955 #define MCG_C1_REG(base) ((base)->C1)
bogdanm 82:6473597d706e 7956 #define MCG_C2_REG(base) ((base)->C2)
bogdanm 82:6473597d706e 7957 #define MCG_C3_REG(base) ((base)->C3)
bogdanm 82:6473597d706e 7958 #define MCG_C4_REG(base) ((base)->C4)
bogdanm 82:6473597d706e 7959 #define MCG_C5_REG(base) ((base)->C5)
bogdanm 82:6473597d706e 7960 #define MCG_C6_REG(base) ((base)->C6)
bogdanm 82:6473597d706e 7961 #define MCG_S_REG(base) ((base)->S)
bogdanm 82:6473597d706e 7962 #define MCG_SC_REG(base) ((base)->SC)
bogdanm 82:6473597d706e 7963 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
bogdanm 82:6473597d706e 7964 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
bogdanm 82:6473597d706e 7965 #define MCG_C7_REG(base) ((base)->C7)
bogdanm 82:6473597d706e 7966 #define MCG_C8_REG(base) ((base)->C8)
bogdanm 82:6473597d706e 7967 #define MCG_C9_REG(base) ((base)->C9)
bogdanm 82:6473597d706e 7968
bogdanm 82:6473597d706e 7969 /*!
bogdanm 82:6473597d706e 7970 * @}
bogdanm 82:6473597d706e 7971 */ /* end of group MCG_Register_Accessor_Macros */
bogdanm 82:6473597d706e 7972
bogdanm 82:6473597d706e 7973
bogdanm 82:6473597d706e 7974 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 7975 -- MCG Register Masks
bogdanm 82:6473597d706e 7976 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 7977
bogdanm 82:6473597d706e 7978 /*!
bogdanm 82:6473597d706e 7979 * @addtogroup MCG_Register_Masks MCG Register Masks
bogdanm 82:6473597d706e 7980 * @{
bogdanm 82:6473597d706e 7981 */
bogdanm 82:6473597d706e 7982
bogdanm 82:6473597d706e 7983 /* C1 Bit Fields */
bogdanm 82:6473597d706e 7984 #define MCG_C1_IREFSTEN_MASK 0x1u
bogdanm 82:6473597d706e 7985 #define MCG_C1_IREFSTEN_SHIFT 0
bogdanm 82:6473597d706e 7986 #define MCG_C1_IRCLKEN_MASK 0x2u
bogdanm 82:6473597d706e 7987 #define MCG_C1_IRCLKEN_SHIFT 1
bogdanm 82:6473597d706e 7988 #define MCG_C1_IREFS_MASK 0x4u
bogdanm 82:6473597d706e 7989 #define MCG_C1_IREFS_SHIFT 2
bogdanm 82:6473597d706e 7990 #define MCG_C1_FRDIV_MASK 0x38u
bogdanm 82:6473597d706e 7991 #define MCG_C1_FRDIV_SHIFT 3
bogdanm 82:6473597d706e 7992 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
bogdanm 82:6473597d706e 7993 #define MCG_C1_CLKS_MASK 0xC0u
bogdanm 82:6473597d706e 7994 #define MCG_C1_CLKS_SHIFT 6
bogdanm 82:6473597d706e 7995 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
bogdanm 82:6473597d706e 7996 /* C2 Bit Fields */
bogdanm 82:6473597d706e 7997 #define MCG_C2_IRCS_MASK 0x1u
bogdanm 82:6473597d706e 7998 #define MCG_C2_IRCS_SHIFT 0
bogdanm 82:6473597d706e 7999 #define MCG_C2_LP_MASK 0x2u
bogdanm 82:6473597d706e 8000 #define MCG_C2_LP_SHIFT 1
bogdanm 82:6473597d706e 8001 #define MCG_C2_EREFS0_MASK 0x4u
bogdanm 82:6473597d706e 8002 #define MCG_C2_EREFS0_SHIFT 2
bogdanm 82:6473597d706e 8003 #define MCG_C2_HGO0_MASK 0x8u
bogdanm 82:6473597d706e 8004 #define MCG_C2_HGO0_SHIFT 3
bogdanm 82:6473597d706e 8005 #define MCG_C2_RANGE0_MASK 0x30u
bogdanm 82:6473597d706e 8006 #define MCG_C2_RANGE0_SHIFT 4
bogdanm 82:6473597d706e 8007 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
bogdanm 82:6473597d706e 8008 #define MCG_C2_FCFTRIM_MASK 0x40u
bogdanm 82:6473597d706e 8009 #define MCG_C2_FCFTRIM_SHIFT 6
bogdanm 82:6473597d706e 8010 #define MCG_C2_LOCRE0_MASK 0x80u
bogdanm 82:6473597d706e 8011 #define MCG_C2_LOCRE0_SHIFT 7
bogdanm 82:6473597d706e 8012 /* C3 Bit Fields */
bogdanm 82:6473597d706e 8013 #define MCG_C3_SCTRIM_MASK 0xFFu
bogdanm 82:6473597d706e 8014 #define MCG_C3_SCTRIM_SHIFT 0
bogdanm 82:6473597d706e 8015 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
bogdanm 82:6473597d706e 8016 /* C4 Bit Fields */
bogdanm 82:6473597d706e 8017 #define MCG_C4_SCFTRIM_MASK 0x1u
bogdanm 82:6473597d706e 8018 #define MCG_C4_SCFTRIM_SHIFT 0
bogdanm 82:6473597d706e 8019 #define MCG_C4_FCTRIM_MASK 0x1Eu
bogdanm 82:6473597d706e 8020 #define MCG_C4_FCTRIM_SHIFT 1
bogdanm 82:6473597d706e 8021 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
bogdanm 82:6473597d706e 8022 #define MCG_C4_DRST_DRS_MASK 0x60u
bogdanm 82:6473597d706e 8023 #define MCG_C4_DRST_DRS_SHIFT 5
bogdanm 82:6473597d706e 8024 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
bogdanm 82:6473597d706e 8025 #define MCG_C4_DMX32_MASK 0x80u
bogdanm 82:6473597d706e 8026 #define MCG_C4_DMX32_SHIFT 7
bogdanm 82:6473597d706e 8027 /* C5 Bit Fields */
bogdanm 82:6473597d706e 8028 #define MCG_C5_PRDIV0_MASK 0x1Fu
bogdanm 82:6473597d706e 8029 #define MCG_C5_PRDIV0_SHIFT 0
bogdanm 82:6473597d706e 8030 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
bogdanm 82:6473597d706e 8031 #define MCG_C5_PLLSTEN0_MASK 0x20u
bogdanm 82:6473597d706e 8032 #define MCG_C5_PLLSTEN0_SHIFT 5
bogdanm 82:6473597d706e 8033 #define MCG_C5_PLLCLKEN0_MASK 0x40u
bogdanm 82:6473597d706e 8034 #define MCG_C5_PLLCLKEN0_SHIFT 6
bogdanm 82:6473597d706e 8035 /* C6 Bit Fields */
bogdanm 82:6473597d706e 8036 #define MCG_C6_VDIV0_MASK 0x1Fu
bogdanm 82:6473597d706e 8037 #define MCG_C6_VDIV0_SHIFT 0
bogdanm 82:6473597d706e 8038 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
bogdanm 82:6473597d706e 8039 #define MCG_C6_CME0_MASK 0x20u
bogdanm 82:6473597d706e 8040 #define MCG_C6_CME0_SHIFT 5
bogdanm 82:6473597d706e 8041 #define MCG_C6_PLLS_MASK 0x40u
bogdanm 82:6473597d706e 8042 #define MCG_C6_PLLS_SHIFT 6
bogdanm 82:6473597d706e 8043 #define MCG_C6_LOLIE0_MASK 0x80u
bogdanm 82:6473597d706e 8044 #define MCG_C6_LOLIE0_SHIFT 7
bogdanm 82:6473597d706e 8045 /* S Bit Fields */
bogdanm 82:6473597d706e 8046 #define MCG_S_IRCST_MASK 0x1u
bogdanm 82:6473597d706e 8047 #define MCG_S_IRCST_SHIFT 0
bogdanm 82:6473597d706e 8048 #define MCG_S_OSCINIT0_MASK 0x2u
bogdanm 82:6473597d706e 8049 #define MCG_S_OSCINIT0_SHIFT 1
bogdanm 82:6473597d706e 8050 #define MCG_S_CLKST_MASK 0xCu
bogdanm 82:6473597d706e 8051 #define MCG_S_CLKST_SHIFT 2
bogdanm 82:6473597d706e 8052 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
bogdanm 82:6473597d706e 8053 #define MCG_S_IREFST_MASK 0x10u
bogdanm 82:6473597d706e 8054 #define MCG_S_IREFST_SHIFT 4
bogdanm 82:6473597d706e 8055 #define MCG_S_PLLST_MASK 0x20u
bogdanm 82:6473597d706e 8056 #define MCG_S_PLLST_SHIFT 5
bogdanm 82:6473597d706e 8057 #define MCG_S_LOCK0_MASK 0x40u
bogdanm 82:6473597d706e 8058 #define MCG_S_LOCK0_SHIFT 6
bogdanm 82:6473597d706e 8059 #define MCG_S_LOLS0_MASK 0x80u
bogdanm 82:6473597d706e 8060 #define MCG_S_LOLS0_SHIFT 7
bogdanm 82:6473597d706e 8061 /* SC Bit Fields */
bogdanm 82:6473597d706e 8062 #define MCG_SC_LOCS0_MASK 0x1u
bogdanm 82:6473597d706e 8063 #define MCG_SC_LOCS0_SHIFT 0
bogdanm 82:6473597d706e 8064 #define MCG_SC_FCRDIV_MASK 0xEu
bogdanm 82:6473597d706e 8065 #define MCG_SC_FCRDIV_SHIFT 1
bogdanm 82:6473597d706e 8066 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
bogdanm 82:6473597d706e 8067 #define MCG_SC_FLTPRSRV_MASK 0x10u
bogdanm 82:6473597d706e 8068 #define MCG_SC_FLTPRSRV_SHIFT 4
bogdanm 82:6473597d706e 8069 #define MCG_SC_ATMF_MASK 0x20u
bogdanm 82:6473597d706e 8070 #define MCG_SC_ATMF_SHIFT 5
bogdanm 82:6473597d706e 8071 #define MCG_SC_ATMS_MASK 0x40u
bogdanm 82:6473597d706e 8072 #define MCG_SC_ATMS_SHIFT 6
bogdanm 82:6473597d706e 8073 #define MCG_SC_ATME_MASK 0x80u
bogdanm 82:6473597d706e 8074 #define MCG_SC_ATME_SHIFT 7
bogdanm 82:6473597d706e 8075 /* ATCVH Bit Fields */
bogdanm 82:6473597d706e 8076 #define MCG_ATCVH_ATCVH_MASK 0xFFu
bogdanm 82:6473597d706e 8077 #define MCG_ATCVH_ATCVH_SHIFT 0
bogdanm 82:6473597d706e 8078 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
bogdanm 82:6473597d706e 8079 /* ATCVL Bit Fields */
bogdanm 82:6473597d706e 8080 #define MCG_ATCVL_ATCVL_MASK 0xFFu
bogdanm 82:6473597d706e 8081 #define MCG_ATCVL_ATCVL_SHIFT 0
bogdanm 82:6473597d706e 8082 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
bogdanm 82:6473597d706e 8083 /* C7 Bit Fields */
bogdanm 82:6473597d706e 8084 #define MCG_C7_OSCSEL_MASK 0x3u
bogdanm 82:6473597d706e 8085 #define MCG_C7_OSCSEL_SHIFT 0
bogdanm 82:6473597d706e 8086 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
bogdanm 82:6473597d706e 8087 /* C8 Bit Fields */
bogdanm 82:6473597d706e 8088 #define MCG_C8_LOCS1_MASK 0x1u
bogdanm 82:6473597d706e 8089 #define MCG_C8_LOCS1_SHIFT 0
bogdanm 82:6473597d706e 8090 #define MCG_C8_CME1_MASK 0x20u
bogdanm 82:6473597d706e 8091 #define MCG_C8_CME1_SHIFT 5
bogdanm 82:6473597d706e 8092 #define MCG_C8_LOLRE_MASK 0x40u
bogdanm 82:6473597d706e 8093 #define MCG_C8_LOLRE_SHIFT 6
bogdanm 82:6473597d706e 8094 #define MCG_C8_LOCRE1_MASK 0x80u
bogdanm 82:6473597d706e 8095 #define MCG_C8_LOCRE1_SHIFT 7
bogdanm 82:6473597d706e 8096
bogdanm 82:6473597d706e 8097 /*!
bogdanm 82:6473597d706e 8098 * @}
bogdanm 82:6473597d706e 8099 */ /* end of group MCG_Register_Masks */
bogdanm 82:6473597d706e 8100
bogdanm 82:6473597d706e 8101
bogdanm 82:6473597d706e 8102 /* MCG - Peripheral instance base addresses */
bogdanm 82:6473597d706e 8103 /** Peripheral MCG base address */
bogdanm 82:6473597d706e 8104 #define MCG_BASE (0x40064000u)
bogdanm 82:6473597d706e 8105 /** Peripheral MCG base pointer */
bogdanm 82:6473597d706e 8106 #define MCG ((MCG_Type *)MCG_BASE)
bogdanm 82:6473597d706e 8107 #define MCG_BASE_PTR (MCG)
bogdanm 82:6473597d706e 8108 /** Array initializer of MCG peripheral base pointers */
bogdanm 82:6473597d706e 8109 #define MCG_BASES { MCG }
bogdanm 82:6473597d706e 8110
bogdanm 82:6473597d706e 8111 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8112 -- MCG - Register accessor macros
bogdanm 82:6473597d706e 8113 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8114
bogdanm 82:6473597d706e 8115 /*!
bogdanm 82:6473597d706e 8116 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
bogdanm 82:6473597d706e 8117 * @{
bogdanm 82:6473597d706e 8118 */
bogdanm 82:6473597d706e 8119
bogdanm 82:6473597d706e 8120
bogdanm 82:6473597d706e 8121 /* MCG - Register instance definitions */
bogdanm 82:6473597d706e 8122 /* MCG */
bogdanm 82:6473597d706e 8123 #define MCG_C1 MCG_C1_REG(MCG)
bogdanm 82:6473597d706e 8124 #define MCG_C2 MCG_C2_REG(MCG)
bogdanm 82:6473597d706e 8125 #define MCG_C3 MCG_C3_REG(MCG)
bogdanm 82:6473597d706e 8126 #define MCG_C4 MCG_C4_REG(MCG)
bogdanm 82:6473597d706e 8127 #define MCG_C5 MCG_C5_REG(MCG)
bogdanm 82:6473597d706e 8128 #define MCG_C6 MCG_C6_REG(MCG)
bogdanm 82:6473597d706e 8129 #define MCG_S MCG_S_REG(MCG)
bogdanm 82:6473597d706e 8130 #define MCG_SC MCG_SC_REG(MCG)
bogdanm 82:6473597d706e 8131 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
bogdanm 82:6473597d706e 8132 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
bogdanm 82:6473597d706e 8133 #define MCG_C7 MCG_C7_REG(MCG)
bogdanm 82:6473597d706e 8134 #define MCG_C8 MCG_C8_REG(MCG)
bogdanm 82:6473597d706e 8135 #define MCG_C9 MCG_C9_REG(MCG)
bogdanm 82:6473597d706e 8136
bogdanm 82:6473597d706e 8137 /*!
bogdanm 82:6473597d706e 8138 * @}
bogdanm 82:6473597d706e 8139 */ /* end of group MCG_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8140
bogdanm 82:6473597d706e 8141
bogdanm 82:6473597d706e 8142 /*!
bogdanm 82:6473597d706e 8143 * @}
bogdanm 82:6473597d706e 8144 */ /* end of group MCG_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 8145
bogdanm 82:6473597d706e 8146
bogdanm 82:6473597d706e 8147 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8148 -- MCM Peripheral Access Layer
bogdanm 82:6473597d706e 8149 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8150
bogdanm 82:6473597d706e 8151 /*!
bogdanm 82:6473597d706e 8152 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
bogdanm 82:6473597d706e 8153 * @{
bogdanm 82:6473597d706e 8154 */
bogdanm 82:6473597d706e 8155
bogdanm 82:6473597d706e 8156 /** MCM - Register Layout Typedef */
bogdanm 82:6473597d706e 8157 typedef struct {
bogdanm 82:6473597d706e 8158 uint8_t RESERVED_0[8];
bogdanm 82:6473597d706e 8159 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
bogdanm 82:6473597d706e 8160 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
bogdanm 82:6473597d706e 8161 __I uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
bogdanm 82:6473597d706e 8162 __IO uint32_t ISR; /**< Interrupt Status Register, offset: 0x10 */
bogdanm 82:6473597d706e 8163 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
bogdanm 82:6473597d706e 8164 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
bogdanm 82:6473597d706e 8165 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
bogdanm 82:6473597d706e 8166 uint8_t RESERVED_1[16];
bogdanm 82:6473597d706e 8167 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
bogdanm 82:6473597d706e 8168 } MCM_Type, *MCM_MemMapPtr;
bogdanm 82:6473597d706e 8169
bogdanm 82:6473597d706e 8170 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8171 -- MCM - Register accessor macros
bogdanm 82:6473597d706e 8172 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8173
bogdanm 82:6473597d706e 8174 /*!
bogdanm 82:6473597d706e 8175 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
bogdanm 82:6473597d706e 8176 * @{
bogdanm 82:6473597d706e 8177 */
bogdanm 82:6473597d706e 8178
bogdanm 82:6473597d706e 8179
bogdanm 82:6473597d706e 8180 /* MCM - Register accessors */
bogdanm 82:6473597d706e 8181 #define MCM_PLASC_REG(base) ((base)->PLASC)
bogdanm 82:6473597d706e 8182 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
bogdanm 82:6473597d706e 8183 #define MCM_PLACR_REG(base) ((base)->PLACR)
bogdanm 82:6473597d706e 8184 #define MCM_ISR_REG(base) ((base)->ISR)
bogdanm 82:6473597d706e 8185 #define MCM_ETBCC_REG(base) ((base)->ETBCC)
bogdanm 82:6473597d706e 8186 #define MCM_ETBRL_REG(base) ((base)->ETBRL)
bogdanm 82:6473597d706e 8187 #define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
bogdanm 82:6473597d706e 8188 #define MCM_PID_REG(base) ((base)->PID)
bogdanm 82:6473597d706e 8189
bogdanm 82:6473597d706e 8190 /*!
bogdanm 82:6473597d706e 8191 * @}
bogdanm 82:6473597d706e 8192 */ /* end of group MCM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8193
bogdanm 82:6473597d706e 8194
bogdanm 82:6473597d706e 8195 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8196 -- MCM Register Masks
bogdanm 82:6473597d706e 8197 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8198
bogdanm 82:6473597d706e 8199 /*!
bogdanm 82:6473597d706e 8200 * @addtogroup MCM_Register_Masks MCM Register Masks
bogdanm 82:6473597d706e 8201 * @{
bogdanm 82:6473597d706e 8202 */
bogdanm 82:6473597d706e 8203
bogdanm 82:6473597d706e 8204 /* PLASC Bit Fields */
bogdanm 82:6473597d706e 8205 #define MCM_PLASC_ASC_MASK 0xFFu
bogdanm 82:6473597d706e 8206 #define MCM_PLASC_ASC_SHIFT 0
bogdanm 82:6473597d706e 8207 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
bogdanm 82:6473597d706e 8208 /* PLAMC Bit Fields */
bogdanm 82:6473597d706e 8209 #define MCM_PLAMC_AMC_MASK 0xFFu
bogdanm 82:6473597d706e 8210 #define MCM_PLAMC_AMC_SHIFT 0
bogdanm 82:6473597d706e 8211 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
bogdanm 82:6473597d706e 8212 /* PLACR Bit Fields */
bogdanm 82:6473597d706e 8213 #define MCM_PLACR_ARB_MASK 0x200u
bogdanm 82:6473597d706e 8214 #define MCM_PLACR_ARB_SHIFT 9
bogdanm 82:6473597d706e 8215 /* ISR Bit Fields */
bogdanm 82:6473597d706e 8216 #define MCM_ISR_IRQ_MASK 0x2u
bogdanm 82:6473597d706e 8217 #define MCM_ISR_IRQ_SHIFT 1
bogdanm 82:6473597d706e 8218 #define MCM_ISR_NMI_MASK 0x4u
bogdanm 82:6473597d706e 8219 #define MCM_ISR_NMI_SHIFT 2
bogdanm 82:6473597d706e 8220 #define MCM_ISR_DHREQ_MASK 0x8u
bogdanm 82:6473597d706e 8221 #define MCM_ISR_DHREQ_SHIFT 3
bogdanm 82:6473597d706e 8222 #define MCM_ISR_FIOC_MASK 0x100u
bogdanm 82:6473597d706e 8223 #define MCM_ISR_FIOC_SHIFT 8
bogdanm 82:6473597d706e 8224 #define MCM_ISR_FDZC_MASK 0x200u
bogdanm 82:6473597d706e 8225 #define MCM_ISR_FDZC_SHIFT 9
bogdanm 82:6473597d706e 8226 #define MCM_ISR_FOFC_MASK 0x400u
bogdanm 82:6473597d706e 8227 #define MCM_ISR_FOFC_SHIFT 10
bogdanm 82:6473597d706e 8228 #define MCM_ISR_FUFC_MASK 0x800u
bogdanm 82:6473597d706e 8229 #define MCM_ISR_FUFC_SHIFT 11
bogdanm 82:6473597d706e 8230 #define MCM_ISR_FIXC_MASK 0x1000u
bogdanm 82:6473597d706e 8231 #define MCM_ISR_FIXC_SHIFT 12
bogdanm 82:6473597d706e 8232 #define MCM_ISR_FIDC_MASK 0x8000u
bogdanm 82:6473597d706e 8233 #define MCM_ISR_FIDC_SHIFT 15
bogdanm 82:6473597d706e 8234 #define MCM_ISR_FIOCE_MASK 0x1000000u
bogdanm 82:6473597d706e 8235 #define MCM_ISR_FIOCE_SHIFT 24
bogdanm 82:6473597d706e 8236 #define MCM_ISR_FDZCE_MASK 0x2000000u
bogdanm 82:6473597d706e 8237 #define MCM_ISR_FDZCE_SHIFT 25
bogdanm 82:6473597d706e 8238 #define MCM_ISR_FOFCE_MASK 0x4000000u
bogdanm 82:6473597d706e 8239 #define MCM_ISR_FOFCE_SHIFT 26
bogdanm 82:6473597d706e 8240 #define MCM_ISR_FUFCE_MASK 0x8000000u
bogdanm 82:6473597d706e 8241 #define MCM_ISR_FUFCE_SHIFT 27
bogdanm 82:6473597d706e 8242 #define MCM_ISR_FIXCE_MASK 0x10000000u
bogdanm 82:6473597d706e 8243 #define MCM_ISR_FIXCE_SHIFT 28
bogdanm 82:6473597d706e 8244 #define MCM_ISR_FIDCE_MASK 0x80000000u
bogdanm 82:6473597d706e 8245 #define MCM_ISR_FIDCE_SHIFT 31
bogdanm 82:6473597d706e 8246 /* ETBCC Bit Fields */
bogdanm 82:6473597d706e 8247 #define MCM_ETBCC_CNTEN_MASK 0x1u
bogdanm 82:6473597d706e 8248 #define MCM_ETBCC_CNTEN_SHIFT 0
bogdanm 82:6473597d706e 8249 #define MCM_ETBCC_RSPT_MASK 0x6u
bogdanm 82:6473597d706e 8250 #define MCM_ETBCC_RSPT_SHIFT 1
bogdanm 82:6473597d706e 8251 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
bogdanm 82:6473597d706e 8252 #define MCM_ETBCC_RLRQ_MASK 0x8u
bogdanm 82:6473597d706e 8253 #define MCM_ETBCC_RLRQ_SHIFT 3
bogdanm 82:6473597d706e 8254 #define MCM_ETBCC_ETDIS_MASK 0x10u
bogdanm 82:6473597d706e 8255 #define MCM_ETBCC_ETDIS_SHIFT 4
bogdanm 82:6473597d706e 8256 #define MCM_ETBCC_ITDIS_MASK 0x20u
bogdanm 82:6473597d706e 8257 #define MCM_ETBCC_ITDIS_SHIFT 5
bogdanm 82:6473597d706e 8258 /* ETBRL Bit Fields */
bogdanm 82:6473597d706e 8259 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
bogdanm 82:6473597d706e 8260 #define MCM_ETBRL_RELOAD_SHIFT 0
bogdanm 82:6473597d706e 8261 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
bogdanm 82:6473597d706e 8262 /* ETBCNT Bit Fields */
bogdanm 82:6473597d706e 8263 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
bogdanm 82:6473597d706e 8264 #define MCM_ETBCNT_COUNTER_SHIFT 0
bogdanm 82:6473597d706e 8265 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
bogdanm 82:6473597d706e 8266 /* PID Bit Fields */
bogdanm 82:6473597d706e 8267 #define MCM_PID_PID_MASK 0xFFu
bogdanm 82:6473597d706e 8268 #define MCM_PID_PID_SHIFT 0
bogdanm 82:6473597d706e 8269 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
bogdanm 82:6473597d706e 8270
bogdanm 82:6473597d706e 8271 /*!
bogdanm 82:6473597d706e 8272 * @}
bogdanm 82:6473597d706e 8273 */ /* end of group MCM_Register_Masks */
bogdanm 82:6473597d706e 8274
bogdanm 82:6473597d706e 8275
bogdanm 82:6473597d706e 8276 /* MCM - Peripheral instance base addresses */
bogdanm 82:6473597d706e 8277 /** Peripheral MCM base address */
bogdanm 82:6473597d706e 8278 #define MCM_BASE (0xE0080000u)
bogdanm 82:6473597d706e 8279 /** Peripheral MCM base pointer */
bogdanm 82:6473597d706e 8280 #define MCM ((MCM_Type *)MCM_BASE)
bogdanm 82:6473597d706e 8281 #define MCM_BASE_PTR (MCM)
bogdanm 82:6473597d706e 8282 /** Array initializer of MCM peripheral base pointers */
bogdanm 82:6473597d706e 8283 #define MCM_BASES { MCM }
bogdanm 82:6473597d706e 8284
bogdanm 82:6473597d706e 8285 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8286 -- MCM - Register accessor macros
bogdanm 82:6473597d706e 8287 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8288
bogdanm 82:6473597d706e 8289 /*!
bogdanm 82:6473597d706e 8290 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
bogdanm 82:6473597d706e 8291 * @{
bogdanm 82:6473597d706e 8292 */
bogdanm 82:6473597d706e 8293
bogdanm 82:6473597d706e 8294
bogdanm 82:6473597d706e 8295 /* MCM - Register instance definitions */
bogdanm 82:6473597d706e 8296 /* MCM */
bogdanm 82:6473597d706e 8297 #define MCM_PLASC MCM_PLASC_REG(MCM)
bogdanm 82:6473597d706e 8298 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
bogdanm 82:6473597d706e 8299 #define MCM_PLACR MCM_PLACR_REG(MCM)
bogdanm 82:6473597d706e 8300 #define MCM_ISCR MCM_ISR_REG(MCM)
bogdanm 82:6473597d706e 8301 #define MCM_ETBCC MCM_ETBCC_REG(MCM)
bogdanm 82:6473597d706e 8302 #define MCM_ETBRL MCM_ETBRL_REG(MCM)
bogdanm 82:6473597d706e 8303 #define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
bogdanm 82:6473597d706e 8304 #define MCM_PID MCM_PID_REG(MCM)
bogdanm 82:6473597d706e 8305
bogdanm 82:6473597d706e 8306 /*!
bogdanm 82:6473597d706e 8307 * @}
bogdanm 82:6473597d706e 8308 */ /* end of group MCM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8309
bogdanm 82:6473597d706e 8310
bogdanm 82:6473597d706e 8311 /*!
bogdanm 82:6473597d706e 8312 * @}
bogdanm 82:6473597d706e 8313 */ /* end of group MCM_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 8314
bogdanm 82:6473597d706e 8315
bogdanm 82:6473597d706e 8316 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8317 -- MPU Peripheral Access Layer
bogdanm 82:6473597d706e 8318 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8319
bogdanm 82:6473597d706e 8320 /*!
bogdanm 82:6473597d706e 8321 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
bogdanm 82:6473597d706e 8322 * @{
bogdanm 82:6473597d706e 8323 */
bogdanm 82:6473597d706e 8324
bogdanm 82:6473597d706e 8325 /** MPU - Register Layout Typedef */
bogdanm 82:6473597d706e 8326 typedef struct {
bogdanm 82:6473597d706e 8327 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
bogdanm 82:6473597d706e 8328 uint8_t RESERVED_0[12];
bogdanm 82:6473597d706e 8329 struct { /* offset: 0x10, array step: 0x8 */
bogdanm 82:6473597d706e 8330 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
bogdanm 82:6473597d706e 8331 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
bogdanm 82:6473597d706e 8332 } SP[5];
bogdanm 82:6473597d706e 8333 uint8_t RESERVED_1[968];
bogdanm 82:6473597d706e 8334 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
bogdanm 82:6473597d706e 8335 uint8_t RESERVED_2[832];
bogdanm 82:6473597d706e 8336 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
bogdanm 82:6473597d706e 8337 } MPU_Type, *MPU_MemMapPtr;
bogdanm 82:6473597d706e 8338
bogdanm 82:6473597d706e 8339 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8340 -- MPU - Register accessor macros
bogdanm 82:6473597d706e 8341 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8342
bogdanm 82:6473597d706e 8343 /*!
bogdanm 82:6473597d706e 8344 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
bogdanm 82:6473597d706e 8345 * @{
bogdanm 82:6473597d706e 8346 */
bogdanm 82:6473597d706e 8347
bogdanm 82:6473597d706e 8348
bogdanm 82:6473597d706e 8349 /* MPU - Register accessors */
bogdanm 82:6473597d706e 8350 #define MPU_CESR_REG(base) ((base)->CESR)
bogdanm 82:6473597d706e 8351 #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
bogdanm 82:6473597d706e 8352 #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
bogdanm 82:6473597d706e 8353 #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
bogdanm 82:6473597d706e 8354 #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
bogdanm 82:6473597d706e 8355
bogdanm 82:6473597d706e 8356 /*!
bogdanm 82:6473597d706e 8357 * @}
bogdanm 82:6473597d706e 8358 */ /* end of group MPU_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8359
bogdanm 82:6473597d706e 8360
bogdanm 82:6473597d706e 8361 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8362 -- MPU Register Masks
bogdanm 82:6473597d706e 8363 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8364
bogdanm 82:6473597d706e 8365 /*!
bogdanm 82:6473597d706e 8366 * @addtogroup MPU_Register_Masks MPU Register Masks
bogdanm 82:6473597d706e 8367 * @{
bogdanm 82:6473597d706e 8368 */
bogdanm 82:6473597d706e 8369
bogdanm 82:6473597d706e 8370 /* CESR Bit Fields */
bogdanm 82:6473597d706e 8371 #define MPU_CESR_VLD_MASK 0x1u
bogdanm 82:6473597d706e 8372 #define MPU_CESR_VLD_SHIFT 0
bogdanm 82:6473597d706e 8373 #define MPU_CESR_NRGD_MASK 0xF00u
bogdanm 82:6473597d706e 8374 #define MPU_CESR_NRGD_SHIFT 8
bogdanm 82:6473597d706e 8375 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
bogdanm 82:6473597d706e 8376 #define MPU_CESR_NSP_MASK 0xF000u
bogdanm 82:6473597d706e 8377 #define MPU_CESR_NSP_SHIFT 12
bogdanm 82:6473597d706e 8378 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
bogdanm 82:6473597d706e 8379 #define MPU_CESR_HRL_MASK 0xF0000u
bogdanm 82:6473597d706e 8380 #define MPU_CESR_HRL_SHIFT 16
bogdanm 82:6473597d706e 8381 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
bogdanm 82:6473597d706e 8382 #define MPU_CESR_SPERR_MASK 0xF8000000u
bogdanm 82:6473597d706e 8383 #define MPU_CESR_SPERR_SHIFT 27
bogdanm 82:6473597d706e 8384 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
bogdanm 82:6473597d706e 8385 /* EAR Bit Fields */
bogdanm 82:6473597d706e 8386 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 8387 #define MPU_EAR_EADDR_SHIFT 0
bogdanm 82:6473597d706e 8388 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
bogdanm 82:6473597d706e 8389 /* EDR Bit Fields */
bogdanm 82:6473597d706e 8390 #define MPU_EDR_ERW_MASK 0x1u
bogdanm 82:6473597d706e 8391 #define MPU_EDR_ERW_SHIFT 0
bogdanm 82:6473597d706e 8392 #define MPU_EDR_EATTR_MASK 0xEu
bogdanm 82:6473597d706e 8393 #define MPU_EDR_EATTR_SHIFT 1
bogdanm 82:6473597d706e 8394 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
bogdanm 82:6473597d706e 8395 #define MPU_EDR_EMN_MASK 0xF0u
bogdanm 82:6473597d706e 8396 #define MPU_EDR_EMN_SHIFT 4
bogdanm 82:6473597d706e 8397 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
bogdanm 82:6473597d706e 8398 #define MPU_EDR_EPID_MASK 0xFF00u
bogdanm 82:6473597d706e 8399 #define MPU_EDR_EPID_SHIFT 8
bogdanm 82:6473597d706e 8400 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
bogdanm 82:6473597d706e 8401 #define MPU_EDR_EACD_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 8402 #define MPU_EDR_EACD_SHIFT 16
bogdanm 82:6473597d706e 8403 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
bogdanm 82:6473597d706e 8404 /* WORD Bit Fields */
bogdanm 82:6473597d706e 8405 #define MPU_WORD_VLD_MASK 0x1u
bogdanm 82:6473597d706e 8406 #define MPU_WORD_VLD_SHIFT 0
bogdanm 82:6473597d706e 8407 #define MPU_WORD_M0UM_MASK 0x7u
bogdanm 82:6473597d706e 8408 #define MPU_WORD_M0UM_SHIFT 0
bogdanm 82:6473597d706e 8409 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
bogdanm 82:6473597d706e 8410 #define MPU_WORD_M0SM_MASK 0x18u
bogdanm 82:6473597d706e 8411 #define MPU_WORD_M0SM_SHIFT 3
bogdanm 82:6473597d706e 8412 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
bogdanm 82:6473597d706e 8413 #define MPU_WORD_M0PE_MASK 0x20u
bogdanm 82:6473597d706e 8414 #define MPU_WORD_M0PE_SHIFT 5
bogdanm 82:6473597d706e 8415 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
bogdanm 82:6473597d706e 8416 #define MPU_WORD_ENDADDR_SHIFT 5
bogdanm 82:6473597d706e 8417 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
bogdanm 82:6473597d706e 8418 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
bogdanm 82:6473597d706e 8419 #define MPU_WORD_SRTADDR_SHIFT 5
bogdanm 82:6473597d706e 8420 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
bogdanm 82:6473597d706e 8421 #define MPU_WORD_M1UM_MASK 0x1C0u
bogdanm 82:6473597d706e 8422 #define MPU_WORD_M1UM_SHIFT 6
bogdanm 82:6473597d706e 8423 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
bogdanm 82:6473597d706e 8424 #define MPU_WORD_M1SM_MASK 0x600u
bogdanm 82:6473597d706e 8425 #define MPU_WORD_M1SM_SHIFT 9
bogdanm 82:6473597d706e 8426 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
bogdanm 82:6473597d706e 8427 #define MPU_WORD_M1PE_MASK 0x800u
bogdanm 82:6473597d706e 8428 #define MPU_WORD_M1PE_SHIFT 11
bogdanm 82:6473597d706e 8429 #define MPU_WORD_M2UM_MASK 0x7000u
bogdanm 82:6473597d706e 8430 #define MPU_WORD_M2UM_SHIFT 12
bogdanm 82:6473597d706e 8431 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
bogdanm 82:6473597d706e 8432 #define MPU_WORD_M2SM_MASK 0x18000u
bogdanm 82:6473597d706e 8433 #define MPU_WORD_M2SM_SHIFT 15
bogdanm 82:6473597d706e 8434 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
bogdanm 82:6473597d706e 8435 #define MPU_WORD_PIDMASK_MASK 0xFF0000u
bogdanm 82:6473597d706e 8436 #define MPU_WORD_PIDMASK_SHIFT 16
bogdanm 82:6473597d706e 8437 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
bogdanm 82:6473597d706e 8438 #define MPU_WORD_M2PE_MASK 0x20000u
bogdanm 82:6473597d706e 8439 #define MPU_WORD_M2PE_SHIFT 17
bogdanm 82:6473597d706e 8440 #define MPU_WORD_M3UM_MASK 0x1C0000u
bogdanm 82:6473597d706e 8441 #define MPU_WORD_M3UM_SHIFT 18
bogdanm 82:6473597d706e 8442 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
bogdanm 82:6473597d706e 8443 #define MPU_WORD_M3SM_MASK 0x600000u
bogdanm 82:6473597d706e 8444 #define MPU_WORD_M3SM_SHIFT 21
bogdanm 82:6473597d706e 8445 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
bogdanm 82:6473597d706e 8446 #define MPU_WORD_M3PE_MASK 0x800000u
bogdanm 82:6473597d706e 8447 #define MPU_WORD_M3PE_SHIFT 23
bogdanm 82:6473597d706e 8448 #define MPU_WORD_PID_MASK 0xFF000000u
bogdanm 82:6473597d706e 8449 #define MPU_WORD_PID_SHIFT 24
bogdanm 82:6473597d706e 8450 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
bogdanm 82:6473597d706e 8451 #define MPU_WORD_M4WE_MASK 0x1000000u
bogdanm 82:6473597d706e 8452 #define MPU_WORD_M4WE_SHIFT 24
bogdanm 82:6473597d706e 8453 #define MPU_WORD_M4RE_MASK 0x2000000u
bogdanm 82:6473597d706e 8454 #define MPU_WORD_M4RE_SHIFT 25
bogdanm 82:6473597d706e 8455 #define MPU_WORD_M5WE_MASK 0x4000000u
bogdanm 82:6473597d706e 8456 #define MPU_WORD_M5WE_SHIFT 26
bogdanm 82:6473597d706e 8457 #define MPU_WORD_M5RE_MASK 0x8000000u
bogdanm 82:6473597d706e 8458 #define MPU_WORD_M5RE_SHIFT 27
bogdanm 82:6473597d706e 8459 #define MPU_WORD_M6WE_MASK 0x10000000u
bogdanm 82:6473597d706e 8460 #define MPU_WORD_M6WE_SHIFT 28
bogdanm 82:6473597d706e 8461 #define MPU_WORD_M6RE_MASK 0x20000000u
bogdanm 82:6473597d706e 8462 #define MPU_WORD_M6RE_SHIFT 29
bogdanm 82:6473597d706e 8463 #define MPU_WORD_M7WE_MASK 0x40000000u
bogdanm 82:6473597d706e 8464 #define MPU_WORD_M7WE_SHIFT 30
bogdanm 82:6473597d706e 8465 #define MPU_WORD_M7RE_MASK 0x80000000u
bogdanm 82:6473597d706e 8466 #define MPU_WORD_M7RE_SHIFT 31
bogdanm 82:6473597d706e 8467 /* RGDAAC Bit Fields */
bogdanm 82:6473597d706e 8468 #define MPU_RGDAAC_M0UM_MASK 0x7u
bogdanm 82:6473597d706e 8469 #define MPU_RGDAAC_M0UM_SHIFT 0
bogdanm 82:6473597d706e 8470 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
bogdanm 82:6473597d706e 8471 #define MPU_RGDAAC_M0SM_MASK 0x18u
bogdanm 82:6473597d706e 8472 #define MPU_RGDAAC_M0SM_SHIFT 3
bogdanm 82:6473597d706e 8473 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
bogdanm 82:6473597d706e 8474 #define MPU_RGDAAC_M0PE_MASK 0x20u
bogdanm 82:6473597d706e 8475 #define MPU_RGDAAC_M0PE_SHIFT 5
bogdanm 82:6473597d706e 8476 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
bogdanm 82:6473597d706e 8477 #define MPU_RGDAAC_M1UM_SHIFT 6
bogdanm 82:6473597d706e 8478 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
bogdanm 82:6473597d706e 8479 #define MPU_RGDAAC_M1SM_MASK 0x600u
bogdanm 82:6473597d706e 8480 #define MPU_RGDAAC_M1SM_SHIFT 9
bogdanm 82:6473597d706e 8481 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
bogdanm 82:6473597d706e 8482 #define MPU_RGDAAC_M1PE_MASK 0x800u
bogdanm 82:6473597d706e 8483 #define MPU_RGDAAC_M1PE_SHIFT 11
bogdanm 82:6473597d706e 8484 #define MPU_RGDAAC_M2UM_MASK 0x7000u
bogdanm 82:6473597d706e 8485 #define MPU_RGDAAC_M2UM_SHIFT 12
bogdanm 82:6473597d706e 8486 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
bogdanm 82:6473597d706e 8487 #define MPU_RGDAAC_M2SM_MASK 0x18000u
bogdanm 82:6473597d706e 8488 #define MPU_RGDAAC_M2SM_SHIFT 15
bogdanm 82:6473597d706e 8489 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
bogdanm 82:6473597d706e 8490 #define MPU_RGDAAC_M2PE_MASK 0x20000u
bogdanm 82:6473597d706e 8491 #define MPU_RGDAAC_M2PE_SHIFT 17
bogdanm 82:6473597d706e 8492 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
bogdanm 82:6473597d706e 8493 #define MPU_RGDAAC_M3UM_SHIFT 18
bogdanm 82:6473597d706e 8494 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
bogdanm 82:6473597d706e 8495 #define MPU_RGDAAC_M3SM_MASK 0x600000u
bogdanm 82:6473597d706e 8496 #define MPU_RGDAAC_M3SM_SHIFT 21
bogdanm 82:6473597d706e 8497 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
bogdanm 82:6473597d706e 8498 #define MPU_RGDAAC_M3PE_MASK 0x800000u
bogdanm 82:6473597d706e 8499 #define MPU_RGDAAC_M3PE_SHIFT 23
bogdanm 82:6473597d706e 8500 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
bogdanm 82:6473597d706e 8501 #define MPU_RGDAAC_M4WE_SHIFT 24
bogdanm 82:6473597d706e 8502 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
bogdanm 82:6473597d706e 8503 #define MPU_RGDAAC_M4RE_SHIFT 25
bogdanm 82:6473597d706e 8504 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
bogdanm 82:6473597d706e 8505 #define MPU_RGDAAC_M5WE_SHIFT 26
bogdanm 82:6473597d706e 8506 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
bogdanm 82:6473597d706e 8507 #define MPU_RGDAAC_M5RE_SHIFT 27
bogdanm 82:6473597d706e 8508 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
bogdanm 82:6473597d706e 8509 #define MPU_RGDAAC_M6WE_SHIFT 28
bogdanm 82:6473597d706e 8510 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
bogdanm 82:6473597d706e 8511 #define MPU_RGDAAC_M6RE_SHIFT 29
bogdanm 82:6473597d706e 8512 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
bogdanm 82:6473597d706e 8513 #define MPU_RGDAAC_M7WE_SHIFT 30
bogdanm 82:6473597d706e 8514 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
bogdanm 82:6473597d706e 8515 #define MPU_RGDAAC_M7RE_SHIFT 31
bogdanm 82:6473597d706e 8516
bogdanm 82:6473597d706e 8517 /*!
bogdanm 82:6473597d706e 8518 * @}
bogdanm 82:6473597d706e 8519 */ /* end of group MPU_Register_Masks */
bogdanm 82:6473597d706e 8520
bogdanm 82:6473597d706e 8521
bogdanm 82:6473597d706e 8522 /* MPU - Peripheral instance base addresses */
bogdanm 82:6473597d706e 8523 /** Peripheral MPU base address */
bogdanm 82:6473597d706e 8524 #define MPU_BASE (0x4000D000u)
bogdanm 82:6473597d706e 8525 /** Peripheral MPU base pointer */
bogdanm 82:6473597d706e 8526 #define MPU ((MPU_Type *)MPU_BASE)
bogdanm 82:6473597d706e 8527 #define MPU_BASE_PTR (MPU)
bogdanm 82:6473597d706e 8528 /** Array initializer of MPU peripheral base pointers */
bogdanm 82:6473597d706e 8529 #define MPU_BASES { MPU }
bogdanm 82:6473597d706e 8530
bogdanm 82:6473597d706e 8531 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8532 -- MPU - Register accessor macros
bogdanm 82:6473597d706e 8533 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8534
bogdanm 82:6473597d706e 8535 /*!
bogdanm 82:6473597d706e 8536 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
bogdanm 82:6473597d706e 8537 * @{
bogdanm 82:6473597d706e 8538 */
bogdanm 82:6473597d706e 8539
bogdanm 82:6473597d706e 8540
bogdanm 82:6473597d706e 8541 /* MPU - Register instance definitions */
bogdanm 82:6473597d706e 8542 /* MPU */
bogdanm 82:6473597d706e 8543 #define MPU_CESR MPU_CESR_REG(MPU)
bogdanm 82:6473597d706e 8544 #define MPU_EAR0 MPU_EAR_REG(MPU,0)
bogdanm 82:6473597d706e 8545 #define MPU_EDR0 MPU_EDR_REG(MPU,0)
bogdanm 82:6473597d706e 8546 #define MPU_EAR1 MPU_EAR_REG(MPU,1)
bogdanm 82:6473597d706e 8547 #define MPU_EDR1 MPU_EDR_REG(MPU,1)
bogdanm 82:6473597d706e 8548 #define MPU_EAR2 MPU_EAR_REG(MPU,2)
bogdanm 82:6473597d706e 8549 #define MPU_EDR2 MPU_EDR_REG(MPU,2)
bogdanm 82:6473597d706e 8550 #define MPU_EAR3 MPU_EAR_REG(MPU,3)
bogdanm 82:6473597d706e 8551 #define MPU_EDR3 MPU_EDR_REG(MPU,3)
bogdanm 82:6473597d706e 8552 #define MPU_EAR4 MPU_EAR_REG(MPU,4)
bogdanm 82:6473597d706e 8553 #define MPU_EDR4 MPU_EDR_REG(MPU,4)
bogdanm 82:6473597d706e 8554 #define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
bogdanm 82:6473597d706e 8555 #define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
bogdanm 82:6473597d706e 8556 #define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
bogdanm 82:6473597d706e 8557 #define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
bogdanm 82:6473597d706e 8558 #define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
bogdanm 82:6473597d706e 8559 #define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
bogdanm 82:6473597d706e 8560 #define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
bogdanm 82:6473597d706e 8561 #define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
bogdanm 82:6473597d706e 8562 #define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
bogdanm 82:6473597d706e 8563 #define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
bogdanm 82:6473597d706e 8564 #define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
bogdanm 82:6473597d706e 8565 #define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
bogdanm 82:6473597d706e 8566 #define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
bogdanm 82:6473597d706e 8567 #define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
bogdanm 82:6473597d706e 8568 #define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
bogdanm 82:6473597d706e 8569 #define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
bogdanm 82:6473597d706e 8570 #define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
bogdanm 82:6473597d706e 8571 #define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
bogdanm 82:6473597d706e 8572 #define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
bogdanm 82:6473597d706e 8573 #define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
bogdanm 82:6473597d706e 8574 #define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
bogdanm 82:6473597d706e 8575 #define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
bogdanm 82:6473597d706e 8576 #define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
bogdanm 82:6473597d706e 8577 #define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
bogdanm 82:6473597d706e 8578 #define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
bogdanm 82:6473597d706e 8579 #define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
bogdanm 82:6473597d706e 8580 #define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
bogdanm 82:6473597d706e 8581 #define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
bogdanm 82:6473597d706e 8582 #define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
bogdanm 82:6473597d706e 8583 #define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
bogdanm 82:6473597d706e 8584 #define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
bogdanm 82:6473597d706e 8585 #define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
bogdanm 82:6473597d706e 8586 #define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
bogdanm 82:6473597d706e 8587 #define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
bogdanm 82:6473597d706e 8588 #define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
bogdanm 82:6473597d706e 8589 #define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
bogdanm 82:6473597d706e 8590 #define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
bogdanm 82:6473597d706e 8591 #define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
bogdanm 82:6473597d706e 8592 #define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
bogdanm 82:6473597d706e 8593 #define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
bogdanm 82:6473597d706e 8594 #define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
bogdanm 82:6473597d706e 8595 #define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
bogdanm 82:6473597d706e 8596 #define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
bogdanm 82:6473597d706e 8597 #define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
bogdanm 82:6473597d706e 8598 #define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
bogdanm 82:6473597d706e 8599 #define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
bogdanm 82:6473597d706e 8600 #define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
bogdanm 82:6473597d706e 8601 #define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
bogdanm 82:6473597d706e 8602 #define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
bogdanm 82:6473597d706e 8603 #define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
bogdanm 82:6473597d706e 8604 #define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
bogdanm 82:6473597d706e 8605 #define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
bogdanm 82:6473597d706e 8606 #define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
bogdanm 82:6473597d706e 8607 #define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
bogdanm 82:6473597d706e 8608 #define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
bogdanm 82:6473597d706e 8609 #define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
bogdanm 82:6473597d706e 8610 #define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
bogdanm 82:6473597d706e 8611 #define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
bogdanm 82:6473597d706e 8612 #define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
bogdanm 82:6473597d706e 8613 #define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
bogdanm 82:6473597d706e 8614
bogdanm 82:6473597d706e 8615 /* MPU - Register array accessors */
bogdanm 82:6473597d706e 8616 #define MPU_EAR(index) MPU_EAR_REG(MPU,index)
bogdanm 82:6473597d706e 8617 #define MPU_EDR(index) MPU_EDR_REG(MPU,index)
bogdanm 82:6473597d706e 8618 #define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
bogdanm 82:6473597d706e 8619 #define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
bogdanm 82:6473597d706e 8620
bogdanm 82:6473597d706e 8621 /*!
bogdanm 82:6473597d706e 8622 * @}
bogdanm 82:6473597d706e 8623 */ /* end of group MPU_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8624
bogdanm 82:6473597d706e 8625
bogdanm 82:6473597d706e 8626 /*!
bogdanm 82:6473597d706e 8627 * @}
bogdanm 82:6473597d706e 8628 */ /* end of group MPU_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 8629
bogdanm 82:6473597d706e 8630
bogdanm 82:6473597d706e 8631 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8632 -- NV Peripheral Access Layer
bogdanm 82:6473597d706e 8633 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8634
bogdanm 82:6473597d706e 8635 /*!
bogdanm 82:6473597d706e 8636 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
bogdanm 82:6473597d706e 8637 * @{
bogdanm 82:6473597d706e 8638 */
bogdanm 82:6473597d706e 8639
bogdanm 82:6473597d706e 8640 /** NV - Register Layout Typedef */
bogdanm 82:6473597d706e 8641 typedef struct {
bogdanm 82:6473597d706e 8642 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
bogdanm 82:6473597d706e 8643 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
bogdanm 82:6473597d706e 8644 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
bogdanm 82:6473597d706e 8645 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
bogdanm 82:6473597d706e 8646 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
bogdanm 82:6473597d706e 8647 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
bogdanm 82:6473597d706e 8648 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
bogdanm 82:6473597d706e 8649 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
bogdanm 82:6473597d706e 8650 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
bogdanm 82:6473597d706e 8651 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
bogdanm 82:6473597d706e 8652 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
bogdanm 82:6473597d706e 8653 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
bogdanm 82:6473597d706e 8654 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
bogdanm 82:6473597d706e 8655 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
bogdanm 82:6473597d706e 8656 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
bogdanm 82:6473597d706e 8657 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
bogdanm 82:6473597d706e 8658 } NV_Type, *NV_MemMapPtr;
bogdanm 82:6473597d706e 8659
bogdanm 82:6473597d706e 8660 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8661 -- NV - Register accessor macros
bogdanm 82:6473597d706e 8662 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8663
bogdanm 82:6473597d706e 8664 /*!
bogdanm 82:6473597d706e 8665 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
bogdanm 82:6473597d706e 8666 * @{
bogdanm 82:6473597d706e 8667 */
bogdanm 82:6473597d706e 8668
bogdanm 82:6473597d706e 8669
bogdanm 82:6473597d706e 8670 /* NV - Register accessors */
bogdanm 82:6473597d706e 8671 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
bogdanm 82:6473597d706e 8672 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
bogdanm 82:6473597d706e 8673 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
bogdanm 82:6473597d706e 8674 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
bogdanm 82:6473597d706e 8675 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
bogdanm 82:6473597d706e 8676 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
bogdanm 82:6473597d706e 8677 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
bogdanm 82:6473597d706e 8678 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
bogdanm 82:6473597d706e 8679 #define NV_FPROT3_REG(base) ((base)->FPROT3)
bogdanm 82:6473597d706e 8680 #define NV_FPROT2_REG(base) ((base)->FPROT2)
bogdanm 82:6473597d706e 8681 #define NV_FPROT1_REG(base) ((base)->FPROT1)
bogdanm 82:6473597d706e 8682 #define NV_FPROT0_REG(base) ((base)->FPROT0)
bogdanm 82:6473597d706e 8683 #define NV_FSEC_REG(base) ((base)->FSEC)
bogdanm 82:6473597d706e 8684 #define NV_FOPT_REG(base) ((base)->FOPT)
bogdanm 82:6473597d706e 8685 #define NV_FEPROT_REG(base) ((base)->FEPROT)
bogdanm 82:6473597d706e 8686 #define NV_FDPROT_REG(base) ((base)->FDPROT)
bogdanm 82:6473597d706e 8687
bogdanm 82:6473597d706e 8688 /*!
bogdanm 82:6473597d706e 8689 * @}
bogdanm 82:6473597d706e 8690 */ /* end of group NV_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8691
bogdanm 82:6473597d706e 8692
bogdanm 82:6473597d706e 8693 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8694 -- NV Register Masks
bogdanm 82:6473597d706e 8695 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8696
bogdanm 82:6473597d706e 8697 /*!
bogdanm 82:6473597d706e 8698 * @addtogroup NV_Register_Masks NV Register Masks
bogdanm 82:6473597d706e 8699 * @{
bogdanm 82:6473597d706e 8700 */
bogdanm 82:6473597d706e 8701
bogdanm 82:6473597d706e 8702 /* BACKKEY3 Bit Fields */
bogdanm 82:6473597d706e 8703 #define NV_BACKKEY3_KEY_MASK 0xFFu
bogdanm 82:6473597d706e 8704 #define NV_BACKKEY3_KEY_SHIFT 0
bogdanm 82:6473597d706e 8705 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
bogdanm 82:6473597d706e 8706 /* BACKKEY2 Bit Fields */
bogdanm 82:6473597d706e 8707 #define NV_BACKKEY2_KEY_MASK 0xFFu
bogdanm 82:6473597d706e 8708 #define NV_BACKKEY2_KEY_SHIFT 0
bogdanm 82:6473597d706e 8709 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
bogdanm 82:6473597d706e 8710 /* BACKKEY1 Bit Fields */
bogdanm 82:6473597d706e 8711 #define NV_BACKKEY1_KEY_MASK 0xFFu
bogdanm 82:6473597d706e 8712 #define NV_BACKKEY1_KEY_SHIFT 0
bogdanm 82:6473597d706e 8713 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
bogdanm 82:6473597d706e 8714 /* BACKKEY0 Bit Fields */
bogdanm 82:6473597d706e 8715 #define NV_BACKKEY0_KEY_MASK 0xFFu
bogdanm 82:6473597d706e 8716 #define NV_BACKKEY0_KEY_SHIFT 0
bogdanm 82:6473597d706e 8717 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
bogdanm 82:6473597d706e 8718 /* BACKKEY7 Bit Fields */
bogdanm 82:6473597d706e 8719 #define NV_BACKKEY7_KEY_MASK 0xFFu
bogdanm 82:6473597d706e 8720 #define NV_BACKKEY7_KEY_SHIFT 0
bogdanm 82:6473597d706e 8721 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
bogdanm 82:6473597d706e 8722 /* BACKKEY6 Bit Fields */
bogdanm 82:6473597d706e 8723 #define NV_BACKKEY6_KEY_MASK 0xFFu
bogdanm 82:6473597d706e 8724 #define NV_BACKKEY6_KEY_SHIFT 0
bogdanm 82:6473597d706e 8725 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
bogdanm 82:6473597d706e 8726 /* BACKKEY5 Bit Fields */
bogdanm 82:6473597d706e 8727 #define NV_BACKKEY5_KEY_MASK 0xFFu
bogdanm 82:6473597d706e 8728 #define NV_BACKKEY5_KEY_SHIFT 0
bogdanm 82:6473597d706e 8729 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
bogdanm 82:6473597d706e 8730 /* BACKKEY4 Bit Fields */
bogdanm 82:6473597d706e 8731 #define NV_BACKKEY4_KEY_MASK 0xFFu
bogdanm 82:6473597d706e 8732 #define NV_BACKKEY4_KEY_SHIFT 0
bogdanm 82:6473597d706e 8733 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
bogdanm 82:6473597d706e 8734 /* FPROT3 Bit Fields */
bogdanm 82:6473597d706e 8735 #define NV_FPROT3_PROT_MASK 0xFFu
bogdanm 82:6473597d706e 8736 #define NV_FPROT3_PROT_SHIFT 0
bogdanm 82:6473597d706e 8737 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
bogdanm 82:6473597d706e 8738 /* FPROT2 Bit Fields */
bogdanm 82:6473597d706e 8739 #define NV_FPROT2_PROT_MASK 0xFFu
bogdanm 82:6473597d706e 8740 #define NV_FPROT2_PROT_SHIFT 0
bogdanm 82:6473597d706e 8741 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
bogdanm 82:6473597d706e 8742 /* FPROT1 Bit Fields */
bogdanm 82:6473597d706e 8743 #define NV_FPROT1_PROT_MASK 0xFFu
bogdanm 82:6473597d706e 8744 #define NV_FPROT1_PROT_SHIFT 0
bogdanm 82:6473597d706e 8745 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
bogdanm 82:6473597d706e 8746 /* FPROT0 Bit Fields */
bogdanm 82:6473597d706e 8747 #define NV_FPROT0_PROT_MASK 0xFFu
bogdanm 82:6473597d706e 8748 #define NV_FPROT0_PROT_SHIFT 0
bogdanm 82:6473597d706e 8749 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
bogdanm 82:6473597d706e 8750 /* FSEC Bit Fields */
bogdanm 82:6473597d706e 8751 #define NV_FSEC_SEC_MASK 0x3u
bogdanm 82:6473597d706e 8752 #define NV_FSEC_SEC_SHIFT 0
bogdanm 82:6473597d706e 8753 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
bogdanm 82:6473597d706e 8754 #define NV_FSEC_FSLACC_MASK 0xCu
bogdanm 82:6473597d706e 8755 #define NV_FSEC_FSLACC_SHIFT 2
bogdanm 82:6473597d706e 8756 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
bogdanm 82:6473597d706e 8757 #define NV_FSEC_MEEN_MASK 0x30u
bogdanm 82:6473597d706e 8758 #define NV_FSEC_MEEN_SHIFT 4
bogdanm 82:6473597d706e 8759 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
bogdanm 82:6473597d706e 8760 #define NV_FSEC_KEYEN_MASK 0xC0u
bogdanm 82:6473597d706e 8761 #define NV_FSEC_KEYEN_SHIFT 6
bogdanm 82:6473597d706e 8762 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
bogdanm 82:6473597d706e 8763 /* FOPT Bit Fields */
bogdanm 82:6473597d706e 8764 #define NV_FOPT_LPBOOT_MASK 0x1u
bogdanm 82:6473597d706e 8765 #define NV_FOPT_LPBOOT_SHIFT 0
bogdanm 82:6473597d706e 8766 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
bogdanm 82:6473597d706e 8767 #define NV_FOPT_EZPORT_DIS_SHIFT 1
bogdanm 82:6473597d706e 8768 /* FEPROT Bit Fields */
bogdanm 82:6473597d706e 8769 #define NV_FEPROT_EPROT_MASK 0xFFu
bogdanm 82:6473597d706e 8770 #define NV_FEPROT_EPROT_SHIFT 0
bogdanm 82:6473597d706e 8771 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
bogdanm 82:6473597d706e 8772 /* FDPROT Bit Fields */
bogdanm 82:6473597d706e 8773 #define NV_FDPROT_DPROT_MASK 0xFFu
bogdanm 82:6473597d706e 8774 #define NV_FDPROT_DPROT_SHIFT 0
bogdanm 82:6473597d706e 8775 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
bogdanm 82:6473597d706e 8776
bogdanm 82:6473597d706e 8777 /*!
bogdanm 82:6473597d706e 8778 * @}
bogdanm 82:6473597d706e 8779 */ /* end of group NV_Register_Masks */
bogdanm 82:6473597d706e 8780
bogdanm 82:6473597d706e 8781
bogdanm 82:6473597d706e 8782 /* NV - Peripheral instance base addresses */
bogdanm 82:6473597d706e 8783 /** Peripheral FTFE_FlashConfig base address */
bogdanm 82:6473597d706e 8784 #define FTFE_FlashConfig_BASE (0x400u)
bogdanm 82:6473597d706e 8785 /** Peripheral FTFE_FlashConfig base pointer */
bogdanm 82:6473597d706e 8786 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
bogdanm 82:6473597d706e 8787 #define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
bogdanm 82:6473597d706e 8788 /** Array initializer of NV peripheral base pointers */
bogdanm 82:6473597d706e 8789 #define NV_BASES { FTFE_FlashConfig }
bogdanm 82:6473597d706e 8790
bogdanm 82:6473597d706e 8791 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8792 -- NV - Register accessor macros
bogdanm 82:6473597d706e 8793 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8794
bogdanm 82:6473597d706e 8795 /*!
bogdanm 82:6473597d706e 8796 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
bogdanm 82:6473597d706e 8797 * @{
bogdanm 82:6473597d706e 8798 */
bogdanm 82:6473597d706e 8799
bogdanm 82:6473597d706e 8800
bogdanm 82:6473597d706e 8801 /* NV - Register instance definitions */
bogdanm 82:6473597d706e 8802 /* FTFE_FlashConfig */
bogdanm 82:6473597d706e 8803 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8804 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8805 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8806 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8807 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8808 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8809 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8810 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8811 #define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8812 #define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8813 #define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8814 #define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8815 #define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8816 #define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8817 #define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8818 #define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
bogdanm 82:6473597d706e 8819
bogdanm 82:6473597d706e 8820 /*!
bogdanm 82:6473597d706e 8821 * @}
bogdanm 82:6473597d706e 8822 */ /* end of group NV_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8823
bogdanm 82:6473597d706e 8824
bogdanm 82:6473597d706e 8825 /*!
bogdanm 82:6473597d706e 8826 * @}
bogdanm 82:6473597d706e 8827 */ /* end of group NV_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 8828
bogdanm 82:6473597d706e 8829
bogdanm 82:6473597d706e 8830 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8831 -- OSC Peripheral Access Layer
bogdanm 82:6473597d706e 8832 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8833
bogdanm 82:6473597d706e 8834 /*!
bogdanm 82:6473597d706e 8835 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
bogdanm 82:6473597d706e 8836 * @{
bogdanm 82:6473597d706e 8837 */
bogdanm 82:6473597d706e 8838
bogdanm 82:6473597d706e 8839 /** OSC - Register Layout Typedef */
bogdanm 82:6473597d706e 8840 typedef struct {
bogdanm 82:6473597d706e 8841 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
bogdanm 82:6473597d706e 8842 } OSC_Type, *OSC_MemMapPtr;
bogdanm 82:6473597d706e 8843
bogdanm 82:6473597d706e 8844 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8845 -- OSC - Register accessor macros
bogdanm 82:6473597d706e 8846 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8847
bogdanm 82:6473597d706e 8848 /*!
bogdanm 82:6473597d706e 8849 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
bogdanm 82:6473597d706e 8850 * @{
bogdanm 82:6473597d706e 8851 */
bogdanm 82:6473597d706e 8852
bogdanm 82:6473597d706e 8853
bogdanm 82:6473597d706e 8854 /* OSC - Register accessors */
bogdanm 82:6473597d706e 8855 #define OSC_CR_REG(base) ((base)->CR)
bogdanm 82:6473597d706e 8856
bogdanm 82:6473597d706e 8857 /*!
bogdanm 82:6473597d706e 8858 * @}
bogdanm 82:6473597d706e 8859 */ /* end of group OSC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8860
bogdanm 82:6473597d706e 8861
bogdanm 82:6473597d706e 8862 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8863 -- OSC Register Masks
bogdanm 82:6473597d706e 8864 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8865
bogdanm 82:6473597d706e 8866 /*!
bogdanm 82:6473597d706e 8867 * @addtogroup OSC_Register_Masks OSC Register Masks
bogdanm 82:6473597d706e 8868 * @{
bogdanm 82:6473597d706e 8869 */
bogdanm 82:6473597d706e 8870
bogdanm 82:6473597d706e 8871 /* CR Bit Fields */
bogdanm 82:6473597d706e 8872 #define OSC_CR_SC16P_MASK 0x1u
bogdanm 82:6473597d706e 8873 #define OSC_CR_SC16P_SHIFT 0
bogdanm 82:6473597d706e 8874 #define OSC_CR_SC8P_MASK 0x2u
bogdanm 82:6473597d706e 8875 #define OSC_CR_SC8P_SHIFT 1
bogdanm 82:6473597d706e 8876 #define OSC_CR_SC4P_MASK 0x4u
bogdanm 82:6473597d706e 8877 #define OSC_CR_SC4P_SHIFT 2
bogdanm 82:6473597d706e 8878 #define OSC_CR_SC2P_MASK 0x8u
bogdanm 82:6473597d706e 8879 #define OSC_CR_SC2P_SHIFT 3
bogdanm 82:6473597d706e 8880 #define OSC_CR_EREFSTEN_MASK 0x20u
bogdanm 82:6473597d706e 8881 #define OSC_CR_EREFSTEN_SHIFT 5
bogdanm 82:6473597d706e 8882 #define OSC_CR_ERCLKEN_MASK 0x80u
bogdanm 82:6473597d706e 8883 #define OSC_CR_ERCLKEN_SHIFT 7
bogdanm 82:6473597d706e 8884
bogdanm 82:6473597d706e 8885 /*!
bogdanm 82:6473597d706e 8886 * @}
bogdanm 82:6473597d706e 8887 */ /* end of group OSC_Register_Masks */
bogdanm 82:6473597d706e 8888
bogdanm 82:6473597d706e 8889
bogdanm 82:6473597d706e 8890 /* OSC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 8891 /** Peripheral OSC base address */
bogdanm 82:6473597d706e 8892 #define OSC_BASE (0x40065000u)
bogdanm 82:6473597d706e 8893 /** Peripheral OSC base pointer */
bogdanm 82:6473597d706e 8894 #define OSC ((OSC_Type *)OSC_BASE)
bogdanm 82:6473597d706e 8895 #define OSC_BASE_PTR (OSC)
bogdanm 82:6473597d706e 8896 /** Array initializer of OSC peripheral base pointers */
bogdanm 82:6473597d706e 8897 #define OSC_BASES { OSC }
bogdanm 82:6473597d706e 8898
bogdanm 82:6473597d706e 8899 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8900 -- OSC - Register accessor macros
bogdanm 82:6473597d706e 8901 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8902
bogdanm 82:6473597d706e 8903 /*!
bogdanm 82:6473597d706e 8904 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
bogdanm 82:6473597d706e 8905 * @{
bogdanm 82:6473597d706e 8906 */
bogdanm 82:6473597d706e 8907
bogdanm 82:6473597d706e 8908
bogdanm 82:6473597d706e 8909 /* OSC - Register instance definitions */
bogdanm 82:6473597d706e 8910 /* OSC */
bogdanm 82:6473597d706e 8911 #define OSC_CR OSC_CR_REG(OSC)
bogdanm 82:6473597d706e 8912
bogdanm 82:6473597d706e 8913 /*!
bogdanm 82:6473597d706e 8914 * @}
bogdanm 82:6473597d706e 8915 */ /* end of group OSC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8916
bogdanm 82:6473597d706e 8917
bogdanm 82:6473597d706e 8918 /*!
bogdanm 82:6473597d706e 8919 * @}
bogdanm 82:6473597d706e 8920 */ /* end of group OSC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 8921
bogdanm 82:6473597d706e 8922
bogdanm 82:6473597d706e 8923 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8924 -- PDB Peripheral Access Layer
bogdanm 82:6473597d706e 8925 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8926
bogdanm 82:6473597d706e 8927 /*!
bogdanm 82:6473597d706e 8928 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
bogdanm 82:6473597d706e 8929 * @{
bogdanm 82:6473597d706e 8930 */
bogdanm 82:6473597d706e 8931
bogdanm 82:6473597d706e 8932 /** PDB - Register Layout Typedef */
bogdanm 82:6473597d706e 8933 typedef struct {
bogdanm 82:6473597d706e 8934 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
bogdanm 82:6473597d706e 8935 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
bogdanm 82:6473597d706e 8936 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
bogdanm 82:6473597d706e 8937 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
bogdanm 82:6473597d706e 8938 struct { /* offset: 0x10, array step: 0x28 */
bogdanm 82:6473597d706e 8939 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
bogdanm 82:6473597d706e 8940 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
bogdanm 82:6473597d706e 8941 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
bogdanm 82:6473597d706e 8942 uint8_t RESERVED_0[24];
bogdanm 82:6473597d706e 8943 } CH[2];
bogdanm 82:6473597d706e 8944 uint8_t RESERVED_0[240];
bogdanm 82:6473597d706e 8945 struct { /* offset: 0x150, array step: 0x8 */
bogdanm 82:6473597d706e 8946 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
bogdanm 82:6473597d706e 8947 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
bogdanm 82:6473597d706e 8948 } DAC[2];
bogdanm 82:6473597d706e 8949 uint8_t RESERVED_1[48];
bogdanm 82:6473597d706e 8950 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
bogdanm 82:6473597d706e 8951 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
bogdanm 82:6473597d706e 8952 } PDB_Type, *PDB_MemMapPtr;
bogdanm 82:6473597d706e 8953
bogdanm 82:6473597d706e 8954 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8955 -- PDB - Register accessor macros
bogdanm 82:6473597d706e 8956 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8957
bogdanm 82:6473597d706e 8958 /*!
bogdanm 82:6473597d706e 8959 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
bogdanm 82:6473597d706e 8960 * @{
bogdanm 82:6473597d706e 8961 */
bogdanm 82:6473597d706e 8962
bogdanm 82:6473597d706e 8963
bogdanm 82:6473597d706e 8964 /* PDB - Register accessors */
bogdanm 82:6473597d706e 8965 #define PDB_SC_REG(base) ((base)->SC)
bogdanm 82:6473597d706e 8966 #define PDB_MOD_REG(base) ((base)->MOD)
bogdanm 82:6473597d706e 8967 #define PDB_CNT_REG(base) ((base)->CNT)
bogdanm 82:6473597d706e 8968 #define PDB_IDLY_REG(base) ((base)->IDLY)
bogdanm 82:6473597d706e 8969 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
bogdanm 82:6473597d706e 8970 #define PDB_S_REG(base,index) ((base)->CH[index].S)
bogdanm 82:6473597d706e 8971 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
bogdanm 82:6473597d706e 8972 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
bogdanm 82:6473597d706e 8973 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
bogdanm 82:6473597d706e 8974 #define PDB_POEN_REG(base) ((base)->POEN)
bogdanm 82:6473597d706e 8975 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
bogdanm 82:6473597d706e 8976
bogdanm 82:6473597d706e 8977 /*!
bogdanm 82:6473597d706e 8978 * @}
bogdanm 82:6473597d706e 8979 */ /* end of group PDB_Register_Accessor_Macros */
bogdanm 82:6473597d706e 8980
bogdanm 82:6473597d706e 8981
bogdanm 82:6473597d706e 8982 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 8983 -- PDB Register Masks
bogdanm 82:6473597d706e 8984 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 8985
bogdanm 82:6473597d706e 8986 /*!
bogdanm 82:6473597d706e 8987 * @addtogroup PDB_Register_Masks PDB Register Masks
bogdanm 82:6473597d706e 8988 * @{
bogdanm 82:6473597d706e 8989 */
bogdanm 82:6473597d706e 8990
bogdanm 82:6473597d706e 8991 /* SC Bit Fields */
bogdanm 82:6473597d706e 8992 #define PDB_SC_LDOK_MASK 0x1u
bogdanm 82:6473597d706e 8993 #define PDB_SC_LDOK_SHIFT 0
bogdanm 82:6473597d706e 8994 #define PDB_SC_CONT_MASK 0x2u
bogdanm 82:6473597d706e 8995 #define PDB_SC_CONT_SHIFT 1
bogdanm 82:6473597d706e 8996 #define PDB_SC_MULT_MASK 0xCu
bogdanm 82:6473597d706e 8997 #define PDB_SC_MULT_SHIFT 2
bogdanm 82:6473597d706e 8998 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
bogdanm 82:6473597d706e 8999 #define PDB_SC_PDBIE_MASK 0x20u
bogdanm 82:6473597d706e 9000 #define PDB_SC_PDBIE_SHIFT 5
bogdanm 82:6473597d706e 9001 #define PDB_SC_PDBIF_MASK 0x40u
bogdanm 82:6473597d706e 9002 #define PDB_SC_PDBIF_SHIFT 6
bogdanm 82:6473597d706e 9003 #define PDB_SC_PDBEN_MASK 0x80u
bogdanm 82:6473597d706e 9004 #define PDB_SC_PDBEN_SHIFT 7
bogdanm 82:6473597d706e 9005 #define PDB_SC_TRGSEL_MASK 0xF00u
bogdanm 82:6473597d706e 9006 #define PDB_SC_TRGSEL_SHIFT 8
bogdanm 82:6473597d706e 9007 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
bogdanm 82:6473597d706e 9008 #define PDB_SC_PRESCALER_MASK 0x7000u
bogdanm 82:6473597d706e 9009 #define PDB_SC_PRESCALER_SHIFT 12
bogdanm 82:6473597d706e 9010 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
bogdanm 82:6473597d706e 9011 #define PDB_SC_DMAEN_MASK 0x8000u
bogdanm 82:6473597d706e 9012 #define PDB_SC_DMAEN_SHIFT 15
bogdanm 82:6473597d706e 9013 #define PDB_SC_SWTRIG_MASK 0x10000u
bogdanm 82:6473597d706e 9014 #define PDB_SC_SWTRIG_SHIFT 16
bogdanm 82:6473597d706e 9015 #define PDB_SC_PDBEIE_MASK 0x20000u
bogdanm 82:6473597d706e 9016 #define PDB_SC_PDBEIE_SHIFT 17
bogdanm 82:6473597d706e 9017 #define PDB_SC_LDMOD_MASK 0xC0000u
bogdanm 82:6473597d706e 9018 #define PDB_SC_LDMOD_SHIFT 18
bogdanm 82:6473597d706e 9019 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
bogdanm 82:6473597d706e 9020 /* MOD Bit Fields */
bogdanm 82:6473597d706e 9021 #define PDB_MOD_MOD_MASK 0xFFFFu
bogdanm 82:6473597d706e 9022 #define PDB_MOD_MOD_SHIFT 0
bogdanm 82:6473597d706e 9023 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
bogdanm 82:6473597d706e 9024 /* CNT Bit Fields */
bogdanm 82:6473597d706e 9025 #define PDB_CNT_CNT_MASK 0xFFFFu
bogdanm 82:6473597d706e 9026 #define PDB_CNT_CNT_SHIFT 0
bogdanm 82:6473597d706e 9027 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
bogdanm 82:6473597d706e 9028 /* IDLY Bit Fields */
bogdanm 82:6473597d706e 9029 #define PDB_IDLY_IDLY_MASK 0xFFFFu
bogdanm 82:6473597d706e 9030 #define PDB_IDLY_IDLY_SHIFT 0
bogdanm 82:6473597d706e 9031 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
bogdanm 82:6473597d706e 9032 /* C1 Bit Fields */
bogdanm 82:6473597d706e 9033 #define PDB_C1_EN_MASK 0xFFu
bogdanm 82:6473597d706e 9034 #define PDB_C1_EN_SHIFT 0
bogdanm 82:6473597d706e 9035 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
bogdanm 82:6473597d706e 9036 #define PDB_C1_TOS_MASK 0xFF00u
bogdanm 82:6473597d706e 9037 #define PDB_C1_TOS_SHIFT 8
bogdanm 82:6473597d706e 9038 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
bogdanm 82:6473597d706e 9039 #define PDB_C1_BB_MASK 0xFF0000u
bogdanm 82:6473597d706e 9040 #define PDB_C1_BB_SHIFT 16
bogdanm 82:6473597d706e 9041 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
bogdanm 82:6473597d706e 9042 /* S Bit Fields */
bogdanm 82:6473597d706e 9043 #define PDB_S_ERR_MASK 0xFFu
bogdanm 82:6473597d706e 9044 #define PDB_S_ERR_SHIFT 0
bogdanm 82:6473597d706e 9045 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
bogdanm 82:6473597d706e 9046 #define PDB_S_CF_MASK 0xFF0000u
bogdanm 82:6473597d706e 9047 #define PDB_S_CF_SHIFT 16
bogdanm 82:6473597d706e 9048 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
bogdanm 82:6473597d706e 9049 /* DLY Bit Fields */
bogdanm 82:6473597d706e 9050 #define PDB_DLY_DLY_MASK 0xFFFFu
bogdanm 82:6473597d706e 9051 #define PDB_DLY_DLY_SHIFT 0
bogdanm 82:6473597d706e 9052 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
bogdanm 82:6473597d706e 9053 /* INTC Bit Fields */
bogdanm 82:6473597d706e 9054 #define PDB_INTC_TOE_MASK 0x1u
bogdanm 82:6473597d706e 9055 #define PDB_INTC_TOE_SHIFT 0
bogdanm 82:6473597d706e 9056 #define PDB_INTC_EXT_MASK 0x2u
bogdanm 82:6473597d706e 9057 #define PDB_INTC_EXT_SHIFT 1
bogdanm 82:6473597d706e 9058 /* INT Bit Fields */
bogdanm 82:6473597d706e 9059 #define PDB_INT_INT_MASK 0xFFFFu
bogdanm 82:6473597d706e 9060 #define PDB_INT_INT_SHIFT 0
bogdanm 82:6473597d706e 9061 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
bogdanm 82:6473597d706e 9062 /* POEN Bit Fields */
bogdanm 82:6473597d706e 9063 #define PDB_POEN_POEN_MASK 0xFFu
bogdanm 82:6473597d706e 9064 #define PDB_POEN_POEN_SHIFT 0
bogdanm 82:6473597d706e 9065 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
bogdanm 82:6473597d706e 9066 /* PODLY Bit Fields */
bogdanm 82:6473597d706e 9067 #define PDB_PODLY_DLY2_MASK 0xFFFFu
bogdanm 82:6473597d706e 9068 #define PDB_PODLY_DLY2_SHIFT 0
bogdanm 82:6473597d706e 9069 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
bogdanm 82:6473597d706e 9070 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 9071 #define PDB_PODLY_DLY1_SHIFT 16
bogdanm 82:6473597d706e 9072 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
bogdanm 82:6473597d706e 9073
bogdanm 82:6473597d706e 9074 /*!
bogdanm 82:6473597d706e 9075 * @}
bogdanm 82:6473597d706e 9076 */ /* end of group PDB_Register_Masks */
bogdanm 82:6473597d706e 9077
bogdanm 82:6473597d706e 9078
bogdanm 82:6473597d706e 9079 /* PDB - Peripheral instance base addresses */
bogdanm 82:6473597d706e 9080 /** Peripheral PDB0 base address */
bogdanm 82:6473597d706e 9081 #define PDB0_BASE (0x40036000u)
bogdanm 82:6473597d706e 9082 /** Peripheral PDB0 base pointer */
bogdanm 82:6473597d706e 9083 #define PDB0 ((PDB_Type *)PDB0_BASE)
bogdanm 82:6473597d706e 9084 #define PDB0_BASE_PTR (PDB0)
bogdanm 82:6473597d706e 9085 /** Array initializer of PDB peripheral base pointers */
bogdanm 82:6473597d706e 9086 #define PDB_BASES { PDB0 }
bogdanm 82:6473597d706e 9087
bogdanm 82:6473597d706e 9088 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9089 -- PDB - Register accessor macros
bogdanm 82:6473597d706e 9090 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9091
bogdanm 82:6473597d706e 9092 /*!
bogdanm 82:6473597d706e 9093 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
bogdanm 82:6473597d706e 9094 * @{
bogdanm 82:6473597d706e 9095 */
bogdanm 82:6473597d706e 9096
bogdanm 82:6473597d706e 9097
bogdanm 82:6473597d706e 9098 /* PDB - Register instance definitions */
bogdanm 82:6473597d706e 9099 /* PDB0 */
bogdanm 82:6473597d706e 9100 #define PDB0_SC PDB_SC_REG(PDB0)
bogdanm 82:6473597d706e 9101 #define PDB0_MOD PDB_MOD_REG(PDB0)
bogdanm 82:6473597d706e 9102 #define PDB0_CNT PDB_CNT_REG(PDB0)
bogdanm 82:6473597d706e 9103 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
bogdanm 82:6473597d706e 9104 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
bogdanm 82:6473597d706e 9105 #define PDB0_CH0S PDB_S_REG(PDB0,0)
bogdanm 82:6473597d706e 9106 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
bogdanm 82:6473597d706e 9107 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
bogdanm 82:6473597d706e 9108 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
bogdanm 82:6473597d706e 9109 #define PDB0_CH1S PDB_S_REG(PDB0,1)
bogdanm 82:6473597d706e 9110 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
bogdanm 82:6473597d706e 9111 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
bogdanm 82:6473597d706e 9112 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
bogdanm 82:6473597d706e 9113 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
bogdanm 82:6473597d706e 9114 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
bogdanm 82:6473597d706e 9115 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
bogdanm 82:6473597d706e 9116 #define PDB0_POEN PDB_POEN_REG(PDB0)
bogdanm 82:6473597d706e 9117 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
bogdanm 82:6473597d706e 9118 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
bogdanm 82:6473597d706e 9119 #define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
bogdanm 82:6473597d706e 9120
bogdanm 82:6473597d706e 9121 /* PDB - Register array accessors */
bogdanm 82:6473597d706e 9122 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
bogdanm 82:6473597d706e 9123 #define PDB0_S(index) PDB_S_REG(PDB0,index)
bogdanm 82:6473597d706e 9124 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
bogdanm 82:6473597d706e 9125 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
bogdanm 82:6473597d706e 9126 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
bogdanm 82:6473597d706e 9127 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
bogdanm 82:6473597d706e 9128
bogdanm 82:6473597d706e 9129 /*!
bogdanm 82:6473597d706e 9130 * @}
bogdanm 82:6473597d706e 9131 */ /* end of group PDB_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9132
bogdanm 82:6473597d706e 9133
bogdanm 82:6473597d706e 9134 /*!
bogdanm 82:6473597d706e 9135 * @}
bogdanm 82:6473597d706e 9136 */ /* end of group PDB_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 9137
bogdanm 82:6473597d706e 9138
bogdanm 82:6473597d706e 9139 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9140 -- PIT Peripheral Access Layer
bogdanm 82:6473597d706e 9141 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9142
bogdanm 82:6473597d706e 9143 /*!
bogdanm 82:6473597d706e 9144 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
bogdanm 82:6473597d706e 9145 * @{
bogdanm 82:6473597d706e 9146 */
bogdanm 82:6473597d706e 9147
bogdanm 82:6473597d706e 9148 /** PIT - Register Layout Typedef */
bogdanm 82:6473597d706e 9149 typedef struct {
bogdanm 82:6473597d706e 9150 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
bogdanm 82:6473597d706e 9151 uint8_t RESERVED_0[252];
bogdanm 82:6473597d706e 9152 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 82:6473597d706e 9153 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
bogdanm 82:6473597d706e 9154 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
bogdanm 82:6473597d706e 9155 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
bogdanm 82:6473597d706e 9156 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
bogdanm 82:6473597d706e 9157 } CHANNEL[4];
bogdanm 82:6473597d706e 9158 } PIT_Type, *PIT_MemMapPtr;
bogdanm 82:6473597d706e 9159
bogdanm 82:6473597d706e 9160 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9161 -- PIT - Register accessor macros
bogdanm 82:6473597d706e 9162 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9163
bogdanm 82:6473597d706e 9164 /*!
bogdanm 82:6473597d706e 9165 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
bogdanm 82:6473597d706e 9166 * @{
bogdanm 82:6473597d706e 9167 */
bogdanm 82:6473597d706e 9168
bogdanm 82:6473597d706e 9169
bogdanm 82:6473597d706e 9170 /* PIT - Register accessors */
bogdanm 82:6473597d706e 9171 #define PIT_MCR_REG(base) ((base)->MCR)
bogdanm 82:6473597d706e 9172 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
bogdanm 82:6473597d706e 9173 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
bogdanm 82:6473597d706e 9174 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
bogdanm 82:6473597d706e 9175 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
bogdanm 82:6473597d706e 9176
bogdanm 82:6473597d706e 9177 /*!
bogdanm 82:6473597d706e 9178 * @}
bogdanm 82:6473597d706e 9179 */ /* end of group PIT_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9180
bogdanm 82:6473597d706e 9181
bogdanm 82:6473597d706e 9182 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9183 -- PIT Register Masks
bogdanm 82:6473597d706e 9184 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9185
bogdanm 82:6473597d706e 9186 /*!
bogdanm 82:6473597d706e 9187 * @addtogroup PIT_Register_Masks PIT Register Masks
bogdanm 82:6473597d706e 9188 * @{
bogdanm 82:6473597d706e 9189 */
bogdanm 82:6473597d706e 9190
bogdanm 82:6473597d706e 9191 /* MCR Bit Fields */
bogdanm 82:6473597d706e 9192 #define PIT_MCR_FRZ_MASK 0x1u
bogdanm 82:6473597d706e 9193 #define PIT_MCR_FRZ_SHIFT 0
bogdanm 82:6473597d706e 9194 #define PIT_MCR_MDIS_MASK 0x2u
bogdanm 82:6473597d706e 9195 #define PIT_MCR_MDIS_SHIFT 1
bogdanm 82:6473597d706e 9196 /* LDVAL Bit Fields */
bogdanm 82:6473597d706e 9197 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 9198 #define PIT_LDVAL_TSV_SHIFT 0
bogdanm 82:6473597d706e 9199 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
bogdanm 82:6473597d706e 9200 /* CVAL Bit Fields */
bogdanm 82:6473597d706e 9201 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 9202 #define PIT_CVAL_TVL_SHIFT 0
bogdanm 82:6473597d706e 9203 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
bogdanm 82:6473597d706e 9204 /* TCTRL Bit Fields */
bogdanm 82:6473597d706e 9205 #define PIT_TCTRL_TEN_MASK 0x1u
bogdanm 82:6473597d706e 9206 #define PIT_TCTRL_TEN_SHIFT 0
bogdanm 82:6473597d706e 9207 #define PIT_TCTRL_TIE_MASK 0x2u
bogdanm 82:6473597d706e 9208 #define PIT_TCTRL_TIE_SHIFT 1
bogdanm 82:6473597d706e 9209 #define PIT_TCTRL_CHN_MASK 0x4u
bogdanm 82:6473597d706e 9210 #define PIT_TCTRL_CHN_SHIFT 2
bogdanm 82:6473597d706e 9211 /* TFLG Bit Fields */
bogdanm 82:6473597d706e 9212 #define PIT_TFLG_TIF_MASK 0x1u
bogdanm 82:6473597d706e 9213 #define PIT_TFLG_TIF_SHIFT 0
bogdanm 82:6473597d706e 9214
bogdanm 82:6473597d706e 9215 /*!
bogdanm 82:6473597d706e 9216 * @}
bogdanm 82:6473597d706e 9217 */ /* end of group PIT_Register_Masks */
bogdanm 82:6473597d706e 9218
bogdanm 82:6473597d706e 9219
bogdanm 82:6473597d706e 9220 /* PIT - Peripheral instance base addresses */
bogdanm 82:6473597d706e 9221 /** Peripheral PIT base address */
bogdanm 82:6473597d706e 9222 #define PIT_BASE (0x40037000u)
bogdanm 82:6473597d706e 9223 /** Peripheral PIT base pointer */
bogdanm 82:6473597d706e 9224 #define PIT ((PIT_Type *)PIT_BASE)
bogdanm 82:6473597d706e 9225 #define PIT_BASE_PTR (PIT)
bogdanm 82:6473597d706e 9226 /** Array initializer of PIT peripheral base pointers */
bogdanm 82:6473597d706e 9227 #define PIT_BASES { PIT }
bogdanm 82:6473597d706e 9228
bogdanm 82:6473597d706e 9229 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9230 -- PIT - Register accessor macros
bogdanm 82:6473597d706e 9231 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9232
bogdanm 82:6473597d706e 9233 /*!
bogdanm 82:6473597d706e 9234 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
bogdanm 82:6473597d706e 9235 * @{
bogdanm 82:6473597d706e 9236 */
bogdanm 82:6473597d706e 9237
bogdanm 82:6473597d706e 9238
bogdanm 82:6473597d706e 9239 /* PIT - Register instance definitions */
bogdanm 82:6473597d706e 9240 /* PIT */
bogdanm 82:6473597d706e 9241 #define PIT_MCR PIT_MCR_REG(PIT)
bogdanm 82:6473597d706e 9242 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
bogdanm 82:6473597d706e 9243 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
bogdanm 82:6473597d706e 9244 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
bogdanm 82:6473597d706e 9245 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
bogdanm 82:6473597d706e 9246 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
bogdanm 82:6473597d706e 9247 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
bogdanm 82:6473597d706e 9248 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
bogdanm 82:6473597d706e 9249 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
bogdanm 82:6473597d706e 9250 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
bogdanm 82:6473597d706e 9251 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
bogdanm 82:6473597d706e 9252 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
bogdanm 82:6473597d706e 9253 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
bogdanm 82:6473597d706e 9254 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
bogdanm 82:6473597d706e 9255 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
bogdanm 82:6473597d706e 9256 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
bogdanm 82:6473597d706e 9257 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
bogdanm 82:6473597d706e 9258
bogdanm 82:6473597d706e 9259 /* PIT - Register array accessors */
bogdanm 82:6473597d706e 9260 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
bogdanm 82:6473597d706e 9261 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
bogdanm 82:6473597d706e 9262 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
bogdanm 82:6473597d706e 9263 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
bogdanm 82:6473597d706e 9264
bogdanm 82:6473597d706e 9265 /*!
bogdanm 82:6473597d706e 9266 * @}
bogdanm 82:6473597d706e 9267 */ /* end of group PIT_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9268
bogdanm 82:6473597d706e 9269
bogdanm 82:6473597d706e 9270 /*!
bogdanm 82:6473597d706e 9271 * @}
bogdanm 82:6473597d706e 9272 */ /* end of group PIT_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 9273
bogdanm 82:6473597d706e 9274
bogdanm 82:6473597d706e 9275 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9276 -- PMC Peripheral Access Layer
bogdanm 82:6473597d706e 9277 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9278
bogdanm 82:6473597d706e 9279 /*!
bogdanm 82:6473597d706e 9280 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
bogdanm 82:6473597d706e 9281 * @{
bogdanm 82:6473597d706e 9282 */
bogdanm 82:6473597d706e 9283
bogdanm 82:6473597d706e 9284 /** PMC - Register Layout Typedef */
bogdanm 82:6473597d706e 9285 typedef struct {
bogdanm 82:6473597d706e 9286 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
bogdanm 82:6473597d706e 9287 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
bogdanm 82:6473597d706e 9288 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
bogdanm 82:6473597d706e 9289 } PMC_Type, *PMC_MemMapPtr;
bogdanm 82:6473597d706e 9290
bogdanm 82:6473597d706e 9291 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9292 -- PMC - Register accessor macros
bogdanm 82:6473597d706e 9293 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9294
bogdanm 82:6473597d706e 9295 /*!
bogdanm 82:6473597d706e 9296 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
bogdanm 82:6473597d706e 9297 * @{
bogdanm 82:6473597d706e 9298 */
bogdanm 82:6473597d706e 9299
bogdanm 82:6473597d706e 9300
bogdanm 82:6473597d706e 9301 /* PMC - Register accessors */
bogdanm 82:6473597d706e 9302 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
bogdanm 82:6473597d706e 9303 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
bogdanm 82:6473597d706e 9304 #define PMC_REGSC_REG(base) ((base)->REGSC)
bogdanm 82:6473597d706e 9305
bogdanm 82:6473597d706e 9306 /*!
bogdanm 82:6473597d706e 9307 * @}
bogdanm 82:6473597d706e 9308 */ /* end of group PMC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9309
bogdanm 82:6473597d706e 9310
bogdanm 82:6473597d706e 9311 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9312 -- PMC Register Masks
bogdanm 82:6473597d706e 9313 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9314
bogdanm 82:6473597d706e 9315 /*!
bogdanm 82:6473597d706e 9316 * @addtogroup PMC_Register_Masks PMC Register Masks
bogdanm 82:6473597d706e 9317 * @{
bogdanm 82:6473597d706e 9318 */
bogdanm 82:6473597d706e 9319
bogdanm 82:6473597d706e 9320 /* LVDSC1 Bit Fields */
bogdanm 82:6473597d706e 9321 #define PMC_LVDSC1_LVDV_MASK 0x3u
bogdanm 82:6473597d706e 9322 #define PMC_LVDSC1_LVDV_SHIFT 0
bogdanm 82:6473597d706e 9323 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
bogdanm 82:6473597d706e 9324 #define PMC_LVDSC1_LVDRE_MASK 0x10u
bogdanm 82:6473597d706e 9325 #define PMC_LVDSC1_LVDRE_SHIFT 4
bogdanm 82:6473597d706e 9326 #define PMC_LVDSC1_LVDIE_MASK 0x20u
bogdanm 82:6473597d706e 9327 #define PMC_LVDSC1_LVDIE_SHIFT 5
bogdanm 82:6473597d706e 9328 #define PMC_LVDSC1_LVDACK_MASK 0x40u
bogdanm 82:6473597d706e 9329 #define PMC_LVDSC1_LVDACK_SHIFT 6
bogdanm 82:6473597d706e 9330 #define PMC_LVDSC1_LVDF_MASK 0x80u
bogdanm 82:6473597d706e 9331 #define PMC_LVDSC1_LVDF_SHIFT 7
bogdanm 82:6473597d706e 9332 /* LVDSC2 Bit Fields */
bogdanm 82:6473597d706e 9333 #define PMC_LVDSC2_LVWV_MASK 0x3u
bogdanm 82:6473597d706e 9334 #define PMC_LVDSC2_LVWV_SHIFT 0
bogdanm 82:6473597d706e 9335 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
bogdanm 82:6473597d706e 9336 #define PMC_LVDSC2_LVWIE_MASK 0x20u
bogdanm 82:6473597d706e 9337 #define PMC_LVDSC2_LVWIE_SHIFT 5
bogdanm 82:6473597d706e 9338 #define PMC_LVDSC2_LVWACK_MASK 0x40u
bogdanm 82:6473597d706e 9339 #define PMC_LVDSC2_LVWACK_SHIFT 6
bogdanm 82:6473597d706e 9340 #define PMC_LVDSC2_LVWF_MASK 0x80u
bogdanm 82:6473597d706e 9341 #define PMC_LVDSC2_LVWF_SHIFT 7
bogdanm 82:6473597d706e 9342 /* REGSC Bit Fields */
bogdanm 82:6473597d706e 9343 #define PMC_REGSC_BGBE_MASK 0x1u
bogdanm 82:6473597d706e 9344 #define PMC_REGSC_BGBE_SHIFT 0
bogdanm 82:6473597d706e 9345 #define PMC_REGSC_REGONS_MASK 0x4u
bogdanm 82:6473597d706e 9346 #define PMC_REGSC_REGONS_SHIFT 2
bogdanm 82:6473597d706e 9347 #define PMC_REGSC_ACKISO_MASK 0x8u
bogdanm 82:6473597d706e 9348 #define PMC_REGSC_ACKISO_SHIFT 3
bogdanm 82:6473597d706e 9349 #define PMC_REGSC_BGEN_MASK 0x10u
bogdanm 82:6473597d706e 9350 #define PMC_REGSC_BGEN_SHIFT 4
bogdanm 82:6473597d706e 9351
bogdanm 82:6473597d706e 9352 /*!
bogdanm 82:6473597d706e 9353 * @}
bogdanm 82:6473597d706e 9354 */ /* end of group PMC_Register_Masks */
bogdanm 82:6473597d706e 9355
bogdanm 82:6473597d706e 9356
bogdanm 82:6473597d706e 9357 /* PMC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 9358 /** Peripheral PMC base address */
bogdanm 82:6473597d706e 9359 #define PMC_BASE (0x4007D000u)
bogdanm 82:6473597d706e 9360 /** Peripheral PMC base pointer */
bogdanm 82:6473597d706e 9361 #define PMC ((PMC_Type *)PMC_BASE)
bogdanm 82:6473597d706e 9362 #define PMC_BASE_PTR (PMC)
bogdanm 82:6473597d706e 9363 /** Array initializer of PMC peripheral base pointers */
bogdanm 82:6473597d706e 9364 #define PMC_BASES { PMC }
bogdanm 82:6473597d706e 9365
bogdanm 82:6473597d706e 9366 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9367 -- PMC - Register accessor macros
bogdanm 82:6473597d706e 9368 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9369
bogdanm 82:6473597d706e 9370 /*!
bogdanm 82:6473597d706e 9371 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
bogdanm 82:6473597d706e 9372 * @{
bogdanm 82:6473597d706e 9373 */
bogdanm 82:6473597d706e 9374
bogdanm 82:6473597d706e 9375
bogdanm 82:6473597d706e 9376 /* PMC - Register instance definitions */
bogdanm 82:6473597d706e 9377 /* PMC */
bogdanm 82:6473597d706e 9378 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
bogdanm 82:6473597d706e 9379 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
bogdanm 82:6473597d706e 9380 #define PMC_REGSC PMC_REGSC_REG(PMC)
bogdanm 82:6473597d706e 9381
bogdanm 82:6473597d706e 9382 /*!
bogdanm 82:6473597d706e 9383 * @}
bogdanm 82:6473597d706e 9384 */ /* end of group PMC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9385
bogdanm 82:6473597d706e 9386
bogdanm 82:6473597d706e 9387 /*!
bogdanm 82:6473597d706e 9388 * @}
bogdanm 82:6473597d706e 9389 */ /* end of group PMC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 9390
bogdanm 82:6473597d706e 9391
bogdanm 82:6473597d706e 9392 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9393 -- PORT Peripheral Access Layer
bogdanm 82:6473597d706e 9394 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9395
bogdanm 82:6473597d706e 9396 /*!
bogdanm 82:6473597d706e 9397 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
bogdanm 82:6473597d706e 9398 * @{
bogdanm 82:6473597d706e 9399 */
bogdanm 82:6473597d706e 9400
bogdanm 82:6473597d706e 9401 /** PORT - Register Layout Typedef */
bogdanm 82:6473597d706e 9402 typedef struct {
bogdanm 82:6473597d706e 9403 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
bogdanm 82:6473597d706e 9404 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
bogdanm 82:6473597d706e 9405 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
bogdanm 82:6473597d706e 9406 uint8_t RESERVED_0[24];
bogdanm 82:6473597d706e 9407 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
bogdanm 82:6473597d706e 9408 uint8_t RESERVED_1[28];
bogdanm 82:6473597d706e 9409 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
bogdanm 82:6473597d706e 9410 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
bogdanm 82:6473597d706e 9411 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
bogdanm 82:6473597d706e 9412 } PORT_Type, *PORT_MemMapPtr;
bogdanm 82:6473597d706e 9413
bogdanm 82:6473597d706e 9414 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9415 -- PORT - Register accessor macros
bogdanm 82:6473597d706e 9416 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9417
bogdanm 82:6473597d706e 9418 /*!
bogdanm 82:6473597d706e 9419 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
bogdanm 82:6473597d706e 9420 * @{
bogdanm 82:6473597d706e 9421 */
bogdanm 82:6473597d706e 9422
bogdanm 82:6473597d706e 9423
bogdanm 82:6473597d706e 9424 /* PORT - Register accessors */
bogdanm 82:6473597d706e 9425 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
bogdanm 82:6473597d706e 9426 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
bogdanm 82:6473597d706e 9427 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
bogdanm 82:6473597d706e 9428 #define PORT_ISFR_REG(base) ((base)->ISFR)
bogdanm 82:6473597d706e 9429 #define PORT_DFER_REG(base) ((base)->DFER)
bogdanm 82:6473597d706e 9430 #define PORT_DFCR_REG(base) ((base)->DFCR)
bogdanm 82:6473597d706e 9431 #define PORT_DFWR_REG(base) ((base)->DFWR)
bogdanm 82:6473597d706e 9432
bogdanm 82:6473597d706e 9433 /*!
bogdanm 82:6473597d706e 9434 * @}
bogdanm 82:6473597d706e 9435 */ /* end of group PORT_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9436
bogdanm 82:6473597d706e 9437
bogdanm 82:6473597d706e 9438 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9439 -- PORT Register Masks
bogdanm 82:6473597d706e 9440 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9441
bogdanm 82:6473597d706e 9442 /*!
bogdanm 82:6473597d706e 9443 * @addtogroup PORT_Register_Masks PORT Register Masks
bogdanm 82:6473597d706e 9444 * @{
bogdanm 82:6473597d706e 9445 */
bogdanm 82:6473597d706e 9446
bogdanm 82:6473597d706e 9447 /* PCR Bit Fields */
bogdanm 82:6473597d706e 9448 #define PORT_PCR_PS_MASK 0x1u
bogdanm 82:6473597d706e 9449 #define PORT_PCR_PS_SHIFT 0
bogdanm 82:6473597d706e 9450 #define PORT_PCR_PE_MASK 0x2u
bogdanm 82:6473597d706e 9451 #define PORT_PCR_PE_SHIFT 1
bogdanm 82:6473597d706e 9452 #define PORT_PCR_SRE_MASK 0x4u
bogdanm 82:6473597d706e 9453 #define PORT_PCR_SRE_SHIFT 2
bogdanm 82:6473597d706e 9454 #define PORT_PCR_PFE_MASK 0x10u
bogdanm 82:6473597d706e 9455 #define PORT_PCR_PFE_SHIFT 4
bogdanm 82:6473597d706e 9456 #define PORT_PCR_ODE_MASK 0x20u
bogdanm 82:6473597d706e 9457 #define PORT_PCR_ODE_SHIFT 5
bogdanm 82:6473597d706e 9458 #define PORT_PCR_DSE_MASK 0x40u
bogdanm 82:6473597d706e 9459 #define PORT_PCR_DSE_SHIFT 6
bogdanm 82:6473597d706e 9460 #define PORT_PCR_MUX_MASK 0x700u
bogdanm 82:6473597d706e 9461 #define PORT_PCR_MUX_SHIFT 8
bogdanm 82:6473597d706e 9462 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
bogdanm 82:6473597d706e 9463 #define PORT_PCR_LK_MASK 0x8000u
bogdanm 82:6473597d706e 9464 #define PORT_PCR_LK_SHIFT 15
bogdanm 82:6473597d706e 9465 #define PORT_PCR_IRQC_MASK 0xF0000u
bogdanm 82:6473597d706e 9466 #define PORT_PCR_IRQC_SHIFT 16
bogdanm 82:6473597d706e 9467 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
bogdanm 82:6473597d706e 9468 #define PORT_PCR_ISF_MASK 0x1000000u
bogdanm 82:6473597d706e 9469 #define PORT_PCR_ISF_SHIFT 24
bogdanm 82:6473597d706e 9470 /* GPCLR Bit Fields */
bogdanm 82:6473597d706e 9471 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
bogdanm 82:6473597d706e 9472 #define PORT_GPCLR_GPWD_SHIFT 0
bogdanm 82:6473597d706e 9473 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
bogdanm 82:6473597d706e 9474 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 9475 #define PORT_GPCLR_GPWE_SHIFT 16
bogdanm 82:6473597d706e 9476 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
bogdanm 82:6473597d706e 9477 /* GPCHR Bit Fields */
bogdanm 82:6473597d706e 9478 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
bogdanm 82:6473597d706e 9479 #define PORT_GPCHR_GPWD_SHIFT 0
bogdanm 82:6473597d706e 9480 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
bogdanm 82:6473597d706e 9481 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 9482 #define PORT_GPCHR_GPWE_SHIFT 16
bogdanm 82:6473597d706e 9483 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
bogdanm 82:6473597d706e 9484 /* ISFR Bit Fields */
bogdanm 82:6473597d706e 9485 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 9486 #define PORT_ISFR_ISF_SHIFT 0
bogdanm 82:6473597d706e 9487 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
bogdanm 82:6473597d706e 9488 /* DFER Bit Fields */
bogdanm 82:6473597d706e 9489 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 9490 #define PORT_DFER_DFE_SHIFT 0
bogdanm 82:6473597d706e 9491 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
bogdanm 82:6473597d706e 9492 /* DFCR Bit Fields */
bogdanm 82:6473597d706e 9493 #define PORT_DFCR_CS_MASK 0x1u
bogdanm 82:6473597d706e 9494 #define PORT_DFCR_CS_SHIFT 0
bogdanm 82:6473597d706e 9495 /* DFWR Bit Fields */
bogdanm 82:6473597d706e 9496 #define PORT_DFWR_FILT_MASK 0x1Fu
bogdanm 82:6473597d706e 9497 #define PORT_DFWR_FILT_SHIFT 0
bogdanm 82:6473597d706e 9498 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
bogdanm 82:6473597d706e 9499
bogdanm 82:6473597d706e 9500 /*!
bogdanm 82:6473597d706e 9501 * @}
bogdanm 82:6473597d706e 9502 */ /* end of group PORT_Register_Masks */
bogdanm 82:6473597d706e 9503
bogdanm 82:6473597d706e 9504
bogdanm 82:6473597d706e 9505 /* PORT - Peripheral instance base addresses */
bogdanm 82:6473597d706e 9506 /** Peripheral PORTA base address */
bogdanm 82:6473597d706e 9507 #define PORTA_BASE (0x40049000u)
bogdanm 82:6473597d706e 9508 /** Peripheral PORTA base pointer */
bogdanm 82:6473597d706e 9509 #define PORTA ((PORT_Type *)PORTA_BASE)
bogdanm 82:6473597d706e 9510 #define PORTA_BASE_PTR (PORTA)
bogdanm 82:6473597d706e 9511 /** Peripheral PORTB base address */
bogdanm 82:6473597d706e 9512 #define PORTB_BASE (0x4004A000u)
bogdanm 82:6473597d706e 9513 /** Peripheral PORTB base pointer */
bogdanm 82:6473597d706e 9514 #define PORTB ((PORT_Type *)PORTB_BASE)
bogdanm 82:6473597d706e 9515 #define PORTB_BASE_PTR (PORTB)
bogdanm 82:6473597d706e 9516 /** Peripheral PORTC base address */
bogdanm 82:6473597d706e 9517 #define PORTC_BASE (0x4004B000u)
bogdanm 82:6473597d706e 9518 /** Peripheral PORTC base pointer */
bogdanm 82:6473597d706e 9519 #define PORTC ((PORT_Type *)PORTC_BASE)
bogdanm 82:6473597d706e 9520 #define PORTC_BASE_PTR (PORTC)
bogdanm 82:6473597d706e 9521 /** Peripheral PORTD base address */
bogdanm 82:6473597d706e 9522 #define PORTD_BASE (0x4004C000u)
bogdanm 82:6473597d706e 9523 /** Peripheral PORTD base pointer */
bogdanm 82:6473597d706e 9524 #define PORTD ((PORT_Type *)PORTD_BASE)
bogdanm 82:6473597d706e 9525 #define PORTD_BASE_PTR (PORTD)
bogdanm 82:6473597d706e 9526 /** Peripheral PORTE base address */
bogdanm 82:6473597d706e 9527 #define PORTE_BASE (0x4004D000u)
bogdanm 82:6473597d706e 9528 /** Peripheral PORTE base pointer */
bogdanm 82:6473597d706e 9529 #define PORTE ((PORT_Type *)PORTE_BASE)
bogdanm 82:6473597d706e 9530 #define PORTE_BASE_PTR (PORTE)
bogdanm 82:6473597d706e 9531 /** Array initializer of PORT peripheral base pointers */
bogdanm 82:6473597d706e 9532 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
bogdanm 82:6473597d706e 9533
bogdanm 82:6473597d706e 9534 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9535 -- PORT - Register accessor macros
bogdanm 82:6473597d706e 9536 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9537
bogdanm 82:6473597d706e 9538 /*!
bogdanm 82:6473597d706e 9539 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
bogdanm 82:6473597d706e 9540 * @{
bogdanm 82:6473597d706e 9541 */
bogdanm 82:6473597d706e 9542
bogdanm 82:6473597d706e 9543
bogdanm 82:6473597d706e 9544 /* PORT - Register instance definitions */
bogdanm 82:6473597d706e 9545 /* PORTA */
bogdanm 82:6473597d706e 9546 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
bogdanm 82:6473597d706e 9547 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
bogdanm 82:6473597d706e 9548 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
bogdanm 82:6473597d706e 9549 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
bogdanm 82:6473597d706e 9550 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
bogdanm 82:6473597d706e 9551 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
bogdanm 82:6473597d706e 9552 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
bogdanm 82:6473597d706e 9553 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
bogdanm 82:6473597d706e 9554 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
bogdanm 82:6473597d706e 9555 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
bogdanm 82:6473597d706e 9556 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
bogdanm 82:6473597d706e 9557 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
bogdanm 82:6473597d706e 9558 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
bogdanm 82:6473597d706e 9559 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
bogdanm 82:6473597d706e 9560 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
bogdanm 82:6473597d706e 9561 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
bogdanm 82:6473597d706e 9562 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
bogdanm 82:6473597d706e 9563 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
bogdanm 82:6473597d706e 9564 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
bogdanm 82:6473597d706e 9565 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
bogdanm 82:6473597d706e 9566 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
bogdanm 82:6473597d706e 9567 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
bogdanm 82:6473597d706e 9568 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
bogdanm 82:6473597d706e 9569 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
bogdanm 82:6473597d706e 9570 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
bogdanm 82:6473597d706e 9571 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
bogdanm 82:6473597d706e 9572 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
bogdanm 82:6473597d706e 9573 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
bogdanm 82:6473597d706e 9574 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
bogdanm 82:6473597d706e 9575 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
bogdanm 82:6473597d706e 9576 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
bogdanm 82:6473597d706e 9577 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
bogdanm 82:6473597d706e 9578 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
bogdanm 82:6473597d706e 9579 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
bogdanm 82:6473597d706e 9580 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
bogdanm 82:6473597d706e 9581 /* PORTB */
bogdanm 82:6473597d706e 9582 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
bogdanm 82:6473597d706e 9583 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
bogdanm 82:6473597d706e 9584 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
bogdanm 82:6473597d706e 9585 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
bogdanm 82:6473597d706e 9586 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
bogdanm 82:6473597d706e 9587 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
bogdanm 82:6473597d706e 9588 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
bogdanm 82:6473597d706e 9589 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
bogdanm 82:6473597d706e 9590 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
bogdanm 82:6473597d706e 9591 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
bogdanm 82:6473597d706e 9592 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
bogdanm 82:6473597d706e 9593 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
bogdanm 82:6473597d706e 9594 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
bogdanm 82:6473597d706e 9595 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
bogdanm 82:6473597d706e 9596 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
bogdanm 82:6473597d706e 9597 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
bogdanm 82:6473597d706e 9598 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
bogdanm 82:6473597d706e 9599 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
bogdanm 82:6473597d706e 9600 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
bogdanm 82:6473597d706e 9601 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
bogdanm 82:6473597d706e 9602 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
bogdanm 82:6473597d706e 9603 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
bogdanm 82:6473597d706e 9604 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
bogdanm 82:6473597d706e 9605 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
bogdanm 82:6473597d706e 9606 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
bogdanm 82:6473597d706e 9607 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
bogdanm 82:6473597d706e 9608 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
bogdanm 82:6473597d706e 9609 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
bogdanm 82:6473597d706e 9610 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
bogdanm 82:6473597d706e 9611 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
bogdanm 82:6473597d706e 9612 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
bogdanm 82:6473597d706e 9613 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
bogdanm 82:6473597d706e 9614 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
bogdanm 82:6473597d706e 9615 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
bogdanm 82:6473597d706e 9616 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
bogdanm 82:6473597d706e 9617 /* PORTC */
bogdanm 82:6473597d706e 9618 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
bogdanm 82:6473597d706e 9619 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
bogdanm 82:6473597d706e 9620 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
bogdanm 82:6473597d706e 9621 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
bogdanm 82:6473597d706e 9622 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
bogdanm 82:6473597d706e 9623 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
bogdanm 82:6473597d706e 9624 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
bogdanm 82:6473597d706e 9625 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
bogdanm 82:6473597d706e 9626 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
bogdanm 82:6473597d706e 9627 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
bogdanm 82:6473597d706e 9628 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
bogdanm 82:6473597d706e 9629 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
bogdanm 82:6473597d706e 9630 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
bogdanm 82:6473597d706e 9631 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
bogdanm 82:6473597d706e 9632 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
bogdanm 82:6473597d706e 9633 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
bogdanm 82:6473597d706e 9634 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
bogdanm 82:6473597d706e 9635 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
bogdanm 82:6473597d706e 9636 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
bogdanm 82:6473597d706e 9637 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
bogdanm 82:6473597d706e 9638 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
bogdanm 82:6473597d706e 9639 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
bogdanm 82:6473597d706e 9640 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
bogdanm 82:6473597d706e 9641 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
bogdanm 82:6473597d706e 9642 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
bogdanm 82:6473597d706e 9643 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
bogdanm 82:6473597d706e 9644 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
bogdanm 82:6473597d706e 9645 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
bogdanm 82:6473597d706e 9646 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
bogdanm 82:6473597d706e 9647 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
bogdanm 82:6473597d706e 9648 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
bogdanm 82:6473597d706e 9649 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
bogdanm 82:6473597d706e 9650 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
bogdanm 82:6473597d706e 9651 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
bogdanm 82:6473597d706e 9652 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
bogdanm 82:6473597d706e 9653 /* PORTD */
bogdanm 82:6473597d706e 9654 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
bogdanm 82:6473597d706e 9655 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
bogdanm 82:6473597d706e 9656 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
bogdanm 82:6473597d706e 9657 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
bogdanm 82:6473597d706e 9658 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
bogdanm 82:6473597d706e 9659 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
bogdanm 82:6473597d706e 9660 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
bogdanm 82:6473597d706e 9661 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
bogdanm 82:6473597d706e 9662 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
bogdanm 82:6473597d706e 9663 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
bogdanm 82:6473597d706e 9664 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
bogdanm 82:6473597d706e 9665 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
bogdanm 82:6473597d706e 9666 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
bogdanm 82:6473597d706e 9667 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
bogdanm 82:6473597d706e 9668 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
bogdanm 82:6473597d706e 9669 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
bogdanm 82:6473597d706e 9670 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
bogdanm 82:6473597d706e 9671 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
bogdanm 82:6473597d706e 9672 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
bogdanm 82:6473597d706e 9673 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
bogdanm 82:6473597d706e 9674 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
bogdanm 82:6473597d706e 9675 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
bogdanm 82:6473597d706e 9676 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
bogdanm 82:6473597d706e 9677 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
bogdanm 82:6473597d706e 9678 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
bogdanm 82:6473597d706e 9679 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
bogdanm 82:6473597d706e 9680 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
bogdanm 82:6473597d706e 9681 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
bogdanm 82:6473597d706e 9682 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
bogdanm 82:6473597d706e 9683 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
bogdanm 82:6473597d706e 9684 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
bogdanm 82:6473597d706e 9685 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
bogdanm 82:6473597d706e 9686 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
bogdanm 82:6473597d706e 9687 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
bogdanm 82:6473597d706e 9688 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
bogdanm 82:6473597d706e 9689 #define PORTD_DFER PORT_DFER_REG(PORTD)
bogdanm 82:6473597d706e 9690 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
bogdanm 82:6473597d706e 9691 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
bogdanm 82:6473597d706e 9692 /* PORTE */
bogdanm 82:6473597d706e 9693 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
bogdanm 82:6473597d706e 9694 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
bogdanm 82:6473597d706e 9695 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
bogdanm 82:6473597d706e 9696 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
bogdanm 82:6473597d706e 9697 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
bogdanm 82:6473597d706e 9698 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
bogdanm 82:6473597d706e 9699 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
bogdanm 82:6473597d706e 9700 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
bogdanm 82:6473597d706e 9701 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
bogdanm 82:6473597d706e 9702 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
bogdanm 82:6473597d706e 9703 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
bogdanm 82:6473597d706e 9704 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
bogdanm 82:6473597d706e 9705 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
bogdanm 82:6473597d706e 9706 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
bogdanm 82:6473597d706e 9707 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
bogdanm 82:6473597d706e 9708 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
bogdanm 82:6473597d706e 9709 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
bogdanm 82:6473597d706e 9710 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
bogdanm 82:6473597d706e 9711 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
bogdanm 82:6473597d706e 9712 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
bogdanm 82:6473597d706e 9713 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
bogdanm 82:6473597d706e 9714 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
bogdanm 82:6473597d706e 9715 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
bogdanm 82:6473597d706e 9716 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
bogdanm 82:6473597d706e 9717 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
bogdanm 82:6473597d706e 9718 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
bogdanm 82:6473597d706e 9719 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
bogdanm 82:6473597d706e 9720 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
bogdanm 82:6473597d706e 9721 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
bogdanm 82:6473597d706e 9722 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
bogdanm 82:6473597d706e 9723 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
bogdanm 82:6473597d706e 9724 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
bogdanm 82:6473597d706e 9725 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
bogdanm 82:6473597d706e 9726 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
bogdanm 82:6473597d706e 9727 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
bogdanm 82:6473597d706e 9728
bogdanm 82:6473597d706e 9729 /* PORT - Register array accessors */
bogdanm 82:6473597d706e 9730 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
bogdanm 82:6473597d706e 9731 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
bogdanm 82:6473597d706e 9732 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
bogdanm 82:6473597d706e 9733 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
bogdanm 82:6473597d706e 9734 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
bogdanm 82:6473597d706e 9735
bogdanm 82:6473597d706e 9736 /*!
bogdanm 82:6473597d706e 9737 * @}
bogdanm 82:6473597d706e 9738 */ /* end of group PORT_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9739
bogdanm 82:6473597d706e 9740
bogdanm 82:6473597d706e 9741 /*!
bogdanm 82:6473597d706e 9742 * @}
bogdanm 82:6473597d706e 9743 */ /* end of group PORT_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 9744
bogdanm 82:6473597d706e 9745
bogdanm 82:6473597d706e 9746 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9747 -- RCM Peripheral Access Layer
bogdanm 82:6473597d706e 9748 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9749
bogdanm 82:6473597d706e 9750 /*!
bogdanm 82:6473597d706e 9751 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
bogdanm 82:6473597d706e 9752 * @{
bogdanm 82:6473597d706e 9753 */
bogdanm 82:6473597d706e 9754
bogdanm 82:6473597d706e 9755 /** RCM - Register Layout Typedef */
bogdanm 82:6473597d706e 9756 typedef struct {
bogdanm 82:6473597d706e 9757 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
bogdanm 82:6473597d706e 9758 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
bogdanm 82:6473597d706e 9759 uint8_t RESERVED_0[2];
bogdanm 82:6473597d706e 9760 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
bogdanm 82:6473597d706e 9761 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
bogdanm 82:6473597d706e 9762 uint8_t RESERVED_1[1];
bogdanm 82:6473597d706e 9763 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
bogdanm 82:6473597d706e 9764 } RCM_Type, *RCM_MemMapPtr;
bogdanm 82:6473597d706e 9765
bogdanm 82:6473597d706e 9766 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9767 -- RCM - Register accessor macros
bogdanm 82:6473597d706e 9768 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9769
bogdanm 82:6473597d706e 9770 /*!
bogdanm 82:6473597d706e 9771 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
bogdanm 82:6473597d706e 9772 * @{
bogdanm 82:6473597d706e 9773 */
bogdanm 82:6473597d706e 9774
bogdanm 82:6473597d706e 9775
bogdanm 82:6473597d706e 9776 /* RCM - Register accessors */
bogdanm 82:6473597d706e 9777 #define RCM_SRS0_REG(base) ((base)->SRS0)
bogdanm 82:6473597d706e 9778 #define RCM_SRS1_REG(base) ((base)->SRS1)
bogdanm 82:6473597d706e 9779 #define RCM_RPFC_REG(base) ((base)->RPFC)
bogdanm 82:6473597d706e 9780 #define RCM_RPFW_REG(base) ((base)->RPFW)
bogdanm 82:6473597d706e 9781 #define RCM_MR_REG(base) ((base)->MR)
bogdanm 82:6473597d706e 9782
bogdanm 82:6473597d706e 9783 /*!
bogdanm 82:6473597d706e 9784 * @}
bogdanm 82:6473597d706e 9785 */ /* end of group RCM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9786
bogdanm 82:6473597d706e 9787
bogdanm 82:6473597d706e 9788 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9789 -- RCM Register Masks
bogdanm 82:6473597d706e 9790 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9791
bogdanm 82:6473597d706e 9792 /*!
bogdanm 82:6473597d706e 9793 * @addtogroup RCM_Register_Masks RCM Register Masks
bogdanm 82:6473597d706e 9794 * @{
bogdanm 82:6473597d706e 9795 */
bogdanm 82:6473597d706e 9796
bogdanm 82:6473597d706e 9797 /* SRS0 Bit Fields */
bogdanm 82:6473597d706e 9798 #define RCM_SRS0_WAKEUP_MASK 0x1u
bogdanm 82:6473597d706e 9799 #define RCM_SRS0_WAKEUP_SHIFT 0
bogdanm 82:6473597d706e 9800 #define RCM_SRS0_LVD_MASK 0x2u
bogdanm 82:6473597d706e 9801 #define RCM_SRS0_LVD_SHIFT 1
bogdanm 82:6473597d706e 9802 #define RCM_SRS0_LOC_MASK 0x4u
bogdanm 82:6473597d706e 9803 #define RCM_SRS0_LOC_SHIFT 2
bogdanm 82:6473597d706e 9804 #define RCM_SRS0_LOL_MASK 0x8u
bogdanm 82:6473597d706e 9805 #define RCM_SRS0_LOL_SHIFT 3
bogdanm 82:6473597d706e 9806 #define RCM_SRS0_WDOG_MASK 0x20u
bogdanm 82:6473597d706e 9807 #define RCM_SRS0_WDOG_SHIFT 5
bogdanm 82:6473597d706e 9808 #define RCM_SRS0_PIN_MASK 0x40u
bogdanm 82:6473597d706e 9809 #define RCM_SRS0_PIN_SHIFT 6
bogdanm 82:6473597d706e 9810 #define RCM_SRS0_POR_MASK 0x80u
bogdanm 82:6473597d706e 9811 #define RCM_SRS0_POR_SHIFT 7
bogdanm 82:6473597d706e 9812 /* SRS1 Bit Fields */
bogdanm 82:6473597d706e 9813 #define RCM_SRS1_JTAG_MASK 0x1u
bogdanm 82:6473597d706e 9814 #define RCM_SRS1_JTAG_SHIFT 0
bogdanm 82:6473597d706e 9815 #define RCM_SRS1_LOCKUP_MASK 0x2u
bogdanm 82:6473597d706e 9816 #define RCM_SRS1_LOCKUP_SHIFT 1
bogdanm 82:6473597d706e 9817 #define RCM_SRS1_SW_MASK 0x4u
bogdanm 82:6473597d706e 9818 #define RCM_SRS1_SW_SHIFT 2
bogdanm 82:6473597d706e 9819 #define RCM_SRS1_MDM_AP_MASK 0x8u
bogdanm 82:6473597d706e 9820 #define RCM_SRS1_MDM_AP_SHIFT 3
bogdanm 82:6473597d706e 9821 #define RCM_SRS1_EZPT_MASK 0x10u
bogdanm 82:6473597d706e 9822 #define RCM_SRS1_EZPT_SHIFT 4
bogdanm 82:6473597d706e 9823 #define RCM_SRS1_SACKERR_MASK 0x20u
bogdanm 82:6473597d706e 9824 #define RCM_SRS1_SACKERR_SHIFT 5
bogdanm 82:6473597d706e 9825 /* RPFC Bit Fields */
bogdanm 82:6473597d706e 9826 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
bogdanm 82:6473597d706e 9827 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
bogdanm 82:6473597d706e 9828 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
bogdanm 82:6473597d706e 9829 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
bogdanm 82:6473597d706e 9830 #define RCM_RPFC_RSTFLTSS_SHIFT 2
bogdanm 82:6473597d706e 9831 /* RPFW Bit Fields */
bogdanm 82:6473597d706e 9832 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
bogdanm 82:6473597d706e 9833 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
bogdanm 82:6473597d706e 9834 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
bogdanm 82:6473597d706e 9835 /* MR Bit Fields */
bogdanm 82:6473597d706e 9836 #define RCM_MR_EZP_MS_MASK 0x2u
bogdanm 82:6473597d706e 9837 #define RCM_MR_EZP_MS_SHIFT 1
bogdanm 82:6473597d706e 9838
bogdanm 82:6473597d706e 9839 /*!
bogdanm 82:6473597d706e 9840 * @}
bogdanm 82:6473597d706e 9841 */ /* end of group RCM_Register_Masks */
bogdanm 82:6473597d706e 9842
bogdanm 82:6473597d706e 9843
bogdanm 82:6473597d706e 9844 /* RCM - Peripheral instance base addresses */
bogdanm 82:6473597d706e 9845 /** Peripheral RCM base address */
bogdanm 82:6473597d706e 9846 #define RCM_BASE (0x4007F000u)
bogdanm 82:6473597d706e 9847 /** Peripheral RCM base pointer */
bogdanm 82:6473597d706e 9848 #define RCM ((RCM_Type *)RCM_BASE)
bogdanm 82:6473597d706e 9849 #define RCM_BASE_PTR (RCM)
bogdanm 82:6473597d706e 9850 /** Array initializer of RCM peripheral base pointers */
bogdanm 82:6473597d706e 9851 #define RCM_BASES { RCM }
bogdanm 82:6473597d706e 9852
bogdanm 82:6473597d706e 9853 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9854 -- RCM - Register accessor macros
bogdanm 82:6473597d706e 9855 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9856
bogdanm 82:6473597d706e 9857 /*!
bogdanm 82:6473597d706e 9858 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
bogdanm 82:6473597d706e 9859 * @{
bogdanm 82:6473597d706e 9860 */
bogdanm 82:6473597d706e 9861
bogdanm 82:6473597d706e 9862
bogdanm 82:6473597d706e 9863 /* RCM - Register instance definitions */
bogdanm 82:6473597d706e 9864 /* RCM */
bogdanm 82:6473597d706e 9865 #define RCM_SRS0 RCM_SRS0_REG(RCM)
bogdanm 82:6473597d706e 9866 #define RCM_SRS1 RCM_SRS1_REG(RCM)
bogdanm 82:6473597d706e 9867 #define RCM_RPFC RCM_RPFC_REG(RCM)
bogdanm 82:6473597d706e 9868 #define RCM_RPFW RCM_RPFW_REG(RCM)
bogdanm 82:6473597d706e 9869 #define RCM_MR RCM_MR_REG(RCM)
bogdanm 82:6473597d706e 9870
bogdanm 82:6473597d706e 9871 /*!
bogdanm 82:6473597d706e 9872 * @}
bogdanm 82:6473597d706e 9873 */ /* end of group RCM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9874
bogdanm 82:6473597d706e 9875
bogdanm 82:6473597d706e 9876 /*!
bogdanm 82:6473597d706e 9877 * @}
bogdanm 82:6473597d706e 9878 */ /* end of group RCM_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 9879
bogdanm 82:6473597d706e 9880
bogdanm 82:6473597d706e 9881 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9882 -- RFSYS Peripheral Access Layer
bogdanm 82:6473597d706e 9883 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9884
bogdanm 82:6473597d706e 9885 /*!
bogdanm 82:6473597d706e 9886 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
bogdanm 82:6473597d706e 9887 * @{
bogdanm 82:6473597d706e 9888 */
bogdanm 82:6473597d706e 9889
bogdanm 82:6473597d706e 9890 /** RFSYS - Register Layout Typedef */
bogdanm 82:6473597d706e 9891 typedef struct {
bogdanm 82:6473597d706e 9892 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
bogdanm 82:6473597d706e 9893 } RFSYS_Type, *RFSYS_MemMapPtr;
bogdanm 82:6473597d706e 9894
bogdanm 82:6473597d706e 9895 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9896 -- RFSYS - Register accessor macros
bogdanm 82:6473597d706e 9897 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9898
bogdanm 82:6473597d706e 9899 /*!
bogdanm 82:6473597d706e 9900 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
bogdanm 82:6473597d706e 9901 * @{
bogdanm 82:6473597d706e 9902 */
bogdanm 82:6473597d706e 9903
bogdanm 82:6473597d706e 9904
bogdanm 82:6473597d706e 9905 /* RFSYS - Register accessors */
bogdanm 82:6473597d706e 9906 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
bogdanm 82:6473597d706e 9907
bogdanm 82:6473597d706e 9908 /*!
bogdanm 82:6473597d706e 9909 * @}
bogdanm 82:6473597d706e 9910 */ /* end of group RFSYS_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9911
bogdanm 82:6473597d706e 9912
bogdanm 82:6473597d706e 9913 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9914 -- RFSYS Register Masks
bogdanm 82:6473597d706e 9915 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9916
bogdanm 82:6473597d706e 9917 /*!
bogdanm 82:6473597d706e 9918 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
bogdanm 82:6473597d706e 9919 * @{
bogdanm 82:6473597d706e 9920 */
bogdanm 82:6473597d706e 9921
bogdanm 82:6473597d706e 9922 /* REG Bit Fields */
bogdanm 82:6473597d706e 9923 #define RFSYS_REG_LL_MASK 0xFFu
bogdanm 82:6473597d706e 9924 #define RFSYS_REG_LL_SHIFT 0
bogdanm 82:6473597d706e 9925 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
bogdanm 82:6473597d706e 9926 #define RFSYS_REG_LH_MASK 0xFF00u
bogdanm 82:6473597d706e 9927 #define RFSYS_REG_LH_SHIFT 8
bogdanm 82:6473597d706e 9928 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
bogdanm 82:6473597d706e 9929 #define RFSYS_REG_HL_MASK 0xFF0000u
bogdanm 82:6473597d706e 9930 #define RFSYS_REG_HL_SHIFT 16
bogdanm 82:6473597d706e 9931 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
bogdanm 82:6473597d706e 9932 #define RFSYS_REG_HH_MASK 0xFF000000u
bogdanm 82:6473597d706e 9933 #define RFSYS_REG_HH_SHIFT 24
bogdanm 82:6473597d706e 9934 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
bogdanm 82:6473597d706e 9935
bogdanm 82:6473597d706e 9936 /*!
bogdanm 82:6473597d706e 9937 * @}
bogdanm 82:6473597d706e 9938 */ /* end of group RFSYS_Register_Masks */
bogdanm 82:6473597d706e 9939
bogdanm 82:6473597d706e 9940
bogdanm 82:6473597d706e 9941 /* RFSYS - Peripheral instance base addresses */
bogdanm 82:6473597d706e 9942 /** Peripheral RFSYS base address */
bogdanm 82:6473597d706e 9943 #define RFSYS_BASE (0x40041000u)
bogdanm 82:6473597d706e 9944 /** Peripheral RFSYS base pointer */
bogdanm 82:6473597d706e 9945 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
bogdanm 82:6473597d706e 9946 #define RFSYS_BASE_PTR (RFSYS)
bogdanm 82:6473597d706e 9947 /** Array initializer of RFSYS peripheral base pointers */
bogdanm 82:6473597d706e 9948 #define RFSYS_BASES { RFSYS }
bogdanm 82:6473597d706e 9949
bogdanm 82:6473597d706e 9950 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9951 -- RFSYS - Register accessor macros
bogdanm 82:6473597d706e 9952 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9953
bogdanm 82:6473597d706e 9954 /*!
bogdanm 82:6473597d706e 9955 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
bogdanm 82:6473597d706e 9956 * @{
bogdanm 82:6473597d706e 9957 */
bogdanm 82:6473597d706e 9958
bogdanm 82:6473597d706e 9959
bogdanm 82:6473597d706e 9960 /* RFSYS - Register instance definitions */
bogdanm 82:6473597d706e 9961 /* RFSYS */
bogdanm 82:6473597d706e 9962 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
bogdanm 82:6473597d706e 9963 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
bogdanm 82:6473597d706e 9964 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
bogdanm 82:6473597d706e 9965 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
bogdanm 82:6473597d706e 9966 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
bogdanm 82:6473597d706e 9967 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
bogdanm 82:6473597d706e 9968 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
bogdanm 82:6473597d706e 9969 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
bogdanm 82:6473597d706e 9970
bogdanm 82:6473597d706e 9971 /* RFSYS - Register array accessors */
bogdanm 82:6473597d706e 9972 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
bogdanm 82:6473597d706e 9973
bogdanm 82:6473597d706e 9974 /*!
bogdanm 82:6473597d706e 9975 * @}
bogdanm 82:6473597d706e 9976 */ /* end of group RFSYS_Register_Accessor_Macros */
bogdanm 82:6473597d706e 9977
bogdanm 82:6473597d706e 9978
bogdanm 82:6473597d706e 9979 /*!
bogdanm 82:6473597d706e 9980 * @}
bogdanm 82:6473597d706e 9981 */ /* end of group RFSYS_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 9982
bogdanm 82:6473597d706e 9983
bogdanm 82:6473597d706e 9984 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9985 -- RFVBAT Peripheral Access Layer
bogdanm 82:6473597d706e 9986 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 9987
bogdanm 82:6473597d706e 9988 /*!
bogdanm 82:6473597d706e 9989 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
bogdanm 82:6473597d706e 9990 * @{
bogdanm 82:6473597d706e 9991 */
bogdanm 82:6473597d706e 9992
bogdanm 82:6473597d706e 9993 /** RFVBAT - Register Layout Typedef */
bogdanm 82:6473597d706e 9994 typedef struct {
bogdanm 82:6473597d706e 9995 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
bogdanm 82:6473597d706e 9996 } RFVBAT_Type, *RFVBAT_MemMapPtr;
bogdanm 82:6473597d706e 9997
bogdanm 82:6473597d706e 9998 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 9999 -- RFVBAT - Register accessor macros
bogdanm 82:6473597d706e 10000 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10001
bogdanm 82:6473597d706e 10002 /*!
bogdanm 82:6473597d706e 10003 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
bogdanm 82:6473597d706e 10004 * @{
bogdanm 82:6473597d706e 10005 */
bogdanm 82:6473597d706e 10006
bogdanm 82:6473597d706e 10007
bogdanm 82:6473597d706e 10008 /* RFVBAT - Register accessors */
bogdanm 82:6473597d706e 10009 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
bogdanm 82:6473597d706e 10010
bogdanm 82:6473597d706e 10011 /*!
bogdanm 82:6473597d706e 10012 * @}
bogdanm 82:6473597d706e 10013 */ /* end of group RFVBAT_Register_Accessor_Macros */
bogdanm 82:6473597d706e 10014
bogdanm 82:6473597d706e 10015
bogdanm 82:6473597d706e 10016 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10017 -- RFVBAT Register Masks
bogdanm 82:6473597d706e 10018 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10019
bogdanm 82:6473597d706e 10020 /*!
bogdanm 82:6473597d706e 10021 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
bogdanm 82:6473597d706e 10022 * @{
bogdanm 82:6473597d706e 10023 */
bogdanm 82:6473597d706e 10024
bogdanm 82:6473597d706e 10025 /* REG Bit Fields */
bogdanm 82:6473597d706e 10026 #define RFVBAT_REG_LL_MASK 0xFFu
bogdanm 82:6473597d706e 10027 #define RFVBAT_REG_LL_SHIFT 0
bogdanm 82:6473597d706e 10028 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
bogdanm 82:6473597d706e 10029 #define RFVBAT_REG_LH_MASK 0xFF00u
bogdanm 82:6473597d706e 10030 #define RFVBAT_REG_LH_SHIFT 8
bogdanm 82:6473597d706e 10031 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
bogdanm 82:6473597d706e 10032 #define RFVBAT_REG_HL_MASK 0xFF0000u
bogdanm 82:6473597d706e 10033 #define RFVBAT_REG_HL_SHIFT 16
bogdanm 82:6473597d706e 10034 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
bogdanm 82:6473597d706e 10035 #define RFVBAT_REG_HH_MASK 0xFF000000u
bogdanm 82:6473597d706e 10036 #define RFVBAT_REG_HH_SHIFT 24
bogdanm 82:6473597d706e 10037 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
bogdanm 82:6473597d706e 10038
bogdanm 82:6473597d706e 10039 /*!
bogdanm 82:6473597d706e 10040 * @}
bogdanm 82:6473597d706e 10041 */ /* end of group RFVBAT_Register_Masks */
bogdanm 82:6473597d706e 10042
bogdanm 82:6473597d706e 10043
bogdanm 82:6473597d706e 10044 /* RFVBAT - Peripheral instance base addresses */
bogdanm 82:6473597d706e 10045 /** Peripheral RFVBAT base address */
bogdanm 82:6473597d706e 10046 #define RFVBAT_BASE (0x4003E000u)
bogdanm 82:6473597d706e 10047 /** Peripheral RFVBAT base pointer */
bogdanm 82:6473597d706e 10048 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
bogdanm 82:6473597d706e 10049 #define RFVBAT_BASE_PTR (RFVBAT)
bogdanm 82:6473597d706e 10050 /** Array initializer of RFVBAT peripheral base pointers */
bogdanm 82:6473597d706e 10051 #define RFVBAT_BASES { RFVBAT }
bogdanm 82:6473597d706e 10052
bogdanm 82:6473597d706e 10053 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10054 -- RFVBAT - Register accessor macros
bogdanm 82:6473597d706e 10055 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10056
bogdanm 82:6473597d706e 10057 /*!
bogdanm 82:6473597d706e 10058 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
bogdanm 82:6473597d706e 10059 * @{
bogdanm 82:6473597d706e 10060 */
bogdanm 82:6473597d706e 10061
bogdanm 82:6473597d706e 10062
bogdanm 82:6473597d706e 10063 /* RFVBAT - Register instance definitions */
bogdanm 82:6473597d706e 10064 /* RFVBAT */
bogdanm 82:6473597d706e 10065 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
bogdanm 82:6473597d706e 10066 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
bogdanm 82:6473597d706e 10067 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
bogdanm 82:6473597d706e 10068 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
bogdanm 82:6473597d706e 10069 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
bogdanm 82:6473597d706e 10070 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
bogdanm 82:6473597d706e 10071 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
bogdanm 82:6473597d706e 10072 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
bogdanm 82:6473597d706e 10073
bogdanm 82:6473597d706e 10074 /* RFVBAT - Register array accessors */
bogdanm 82:6473597d706e 10075 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
bogdanm 82:6473597d706e 10076
bogdanm 82:6473597d706e 10077 /*!
bogdanm 82:6473597d706e 10078 * @}
bogdanm 82:6473597d706e 10079 */ /* end of group RFVBAT_Register_Accessor_Macros */
bogdanm 82:6473597d706e 10080
bogdanm 82:6473597d706e 10081
bogdanm 82:6473597d706e 10082 /*!
bogdanm 82:6473597d706e 10083 * @}
bogdanm 82:6473597d706e 10084 */ /* end of group RFVBAT_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 10085
bogdanm 82:6473597d706e 10086
bogdanm 82:6473597d706e 10087 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10088 -- RNG Peripheral Access Layer
bogdanm 82:6473597d706e 10089 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10090
bogdanm 82:6473597d706e 10091 /*!
bogdanm 82:6473597d706e 10092 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
bogdanm 82:6473597d706e 10093 * @{
bogdanm 82:6473597d706e 10094 */
bogdanm 82:6473597d706e 10095
bogdanm 82:6473597d706e 10096 /** RNG - Register Layout Typedef */
bogdanm 82:6473597d706e 10097 typedef struct {
bogdanm 82:6473597d706e 10098 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
bogdanm 82:6473597d706e 10099 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
bogdanm 82:6473597d706e 10100 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
bogdanm 82:6473597d706e 10101 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
bogdanm 82:6473597d706e 10102 } RNG_Type, *RNG_MemMapPtr;
bogdanm 82:6473597d706e 10103
bogdanm 82:6473597d706e 10104 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10105 -- RNG - Register accessor macros
bogdanm 82:6473597d706e 10106 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10107
bogdanm 82:6473597d706e 10108 /*!
bogdanm 82:6473597d706e 10109 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
bogdanm 82:6473597d706e 10110 * @{
bogdanm 82:6473597d706e 10111 */
bogdanm 82:6473597d706e 10112
bogdanm 82:6473597d706e 10113
bogdanm 82:6473597d706e 10114 /* RNG - Register accessors */
bogdanm 82:6473597d706e 10115 #define RNG_CR_REG(base) ((base)->CR)
bogdanm 82:6473597d706e 10116 #define RNG_SR_REG(base) ((base)->SR)
bogdanm 82:6473597d706e 10117 #define RNG_ER_REG(base) ((base)->ER)
bogdanm 82:6473597d706e 10118 #define RNG_OR_REG(base) ((base)->OR)
bogdanm 82:6473597d706e 10119
bogdanm 82:6473597d706e 10120 /*!
bogdanm 82:6473597d706e 10121 * @}
bogdanm 82:6473597d706e 10122 */ /* end of group RNG_Register_Accessor_Macros */
bogdanm 82:6473597d706e 10123
bogdanm 82:6473597d706e 10124
bogdanm 82:6473597d706e 10125 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10126 -- RNG Register Masks
bogdanm 82:6473597d706e 10127 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10128
bogdanm 82:6473597d706e 10129 /*!
bogdanm 82:6473597d706e 10130 * @addtogroup RNG_Register_Masks RNG Register Masks
bogdanm 82:6473597d706e 10131 * @{
bogdanm 82:6473597d706e 10132 */
bogdanm 82:6473597d706e 10133
bogdanm 82:6473597d706e 10134 /* CR Bit Fields */
bogdanm 82:6473597d706e 10135 #define RNG_CR_GO_MASK 0x1u
bogdanm 82:6473597d706e 10136 #define RNG_CR_GO_SHIFT 0
bogdanm 82:6473597d706e 10137 #define RNG_CR_HA_MASK 0x2u
bogdanm 82:6473597d706e 10138 #define RNG_CR_HA_SHIFT 1
bogdanm 82:6473597d706e 10139 #define RNG_CR_INTM_MASK 0x4u
bogdanm 82:6473597d706e 10140 #define RNG_CR_INTM_SHIFT 2
bogdanm 82:6473597d706e 10141 #define RNG_CR_CLRI_MASK 0x8u
bogdanm 82:6473597d706e 10142 #define RNG_CR_CLRI_SHIFT 3
bogdanm 82:6473597d706e 10143 #define RNG_CR_SLP_MASK 0x10u
bogdanm 82:6473597d706e 10144 #define RNG_CR_SLP_SHIFT 4
bogdanm 82:6473597d706e 10145 /* SR Bit Fields */
bogdanm 82:6473597d706e 10146 #define RNG_SR_SECV_MASK 0x1u
bogdanm 82:6473597d706e 10147 #define RNG_SR_SECV_SHIFT 0
bogdanm 82:6473597d706e 10148 #define RNG_SR_LRS_MASK 0x2u
bogdanm 82:6473597d706e 10149 #define RNG_SR_LRS_SHIFT 1
bogdanm 82:6473597d706e 10150 #define RNG_SR_ORU_MASK 0x4u
bogdanm 82:6473597d706e 10151 #define RNG_SR_ORU_SHIFT 2
bogdanm 82:6473597d706e 10152 #define RNG_SR_ERRI_MASK 0x8u
bogdanm 82:6473597d706e 10153 #define RNG_SR_ERRI_SHIFT 3
bogdanm 82:6473597d706e 10154 #define RNG_SR_SLP_MASK 0x10u
bogdanm 82:6473597d706e 10155 #define RNG_SR_SLP_SHIFT 4
bogdanm 82:6473597d706e 10156 #define RNG_SR_OREG_LVL_MASK 0xFF00u
bogdanm 82:6473597d706e 10157 #define RNG_SR_OREG_LVL_SHIFT 8
bogdanm 82:6473597d706e 10158 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
bogdanm 82:6473597d706e 10159 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
bogdanm 82:6473597d706e 10160 #define RNG_SR_OREG_SIZE_SHIFT 16
bogdanm 82:6473597d706e 10161 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
bogdanm 82:6473597d706e 10162 /* ER Bit Fields */
bogdanm 82:6473597d706e 10163 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10164 #define RNG_ER_EXT_ENT_SHIFT 0
bogdanm 82:6473597d706e 10165 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
bogdanm 82:6473597d706e 10166 /* OR Bit Fields */
bogdanm 82:6473597d706e 10167 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10168 #define RNG_OR_RANDOUT_SHIFT 0
bogdanm 82:6473597d706e 10169 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
bogdanm 82:6473597d706e 10170
bogdanm 82:6473597d706e 10171 /*!
bogdanm 82:6473597d706e 10172 * @}
bogdanm 82:6473597d706e 10173 */ /* end of group RNG_Register_Masks */
bogdanm 82:6473597d706e 10174
bogdanm 82:6473597d706e 10175
bogdanm 82:6473597d706e 10176 /* RNG - Peripheral instance base addresses */
bogdanm 82:6473597d706e 10177 /** Peripheral RNG base address */
bogdanm 82:6473597d706e 10178 #define RNG_BASE (0x40029000u)
bogdanm 82:6473597d706e 10179 /** Peripheral RNG base pointer */
bogdanm 82:6473597d706e 10180 #define RNG ((RNG_Type *)RNG_BASE)
bogdanm 82:6473597d706e 10181 #define RNG_BASE_PTR (RNG)
bogdanm 82:6473597d706e 10182 /** Array initializer of RNG peripheral base pointers */
bogdanm 82:6473597d706e 10183 #define RNG_BASES { RNG }
bogdanm 82:6473597d706e 10184
bogdanm 82:6473597d706e 10185 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10186 -- RNG - Register accessor macros
bogdanm 82:6473597d706e 10187 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10188
bogdanm 82:6473597d706e 10189 /*!
bogdanm 82:6473597d706e 10190 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
bogdanm 82:6473597d706e 10191 * @{
bogdanm 82:6473597d706e 10192 */
bogdanm 82:6473597d706e 10193
bogdanm 82:6473597d706e 10194
bogdanm 82:6473597d706e 10195 /* RNG - Register instance definitions */
bogdanm 82:6473597d706e 10196 /* RNG */
bogdanm 82:6473597d706e 10197 #define RNG_CR RNG_CR_REG(RNG)
bogdanm 82:6473597d706e 10198 #define RNG_SR RNG_SR_REG(RNG)
bogdanm 82:6473597d706e 10199 #define RNG_ER RNG_ER_REG(RNG)
bogdanm 82:6473597d706e 10200 #define RNG_OR RNG_OR_REG(RNG)
bogdanm 82:6473597d706e 10201
bogdanm 82:6473597d706e 10202 /*!
bogdanm 82:6473597d706e 10203 * @}
bogdanm 82:6473597d706e 10204 */ /* end of group RNG_Register_Accessor_Macros */
bogdanm 82:6473597d706e 10205
bogdanm 82:6473597d706e 10206
bogdanm 82:6473597d706e 10207 /*!
bogdanm 82:6473597d706e 10208 * @}
bogdanm 82:6473597d706e 10209 */ /* end of group RNG_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 10210
bogdanm 82:6473597d706e 10211
bogdanm 82:6473597d706e 10212 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10213 -- RTC Peripheral Access Layer
bogdanm 82:6473597d706e 10214 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10215
bogdanm 82:6473597d706e 10216 /*!
bogdanm 82:6473597d706e 10217 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
bogdanm 82:6473597d706e 10218 * @{
bogdanm 82:6473597d706e 10219 */
bogdanm 82:6473597d706e 10220
bogdanm 82:6473597d706e 10221 /** RTC - Register Layout Typedef */
bogdanm 82:6473597d706e 10222 typedef struct {
bogdanm 82:6473597d706e 10223 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
bogdanm 82:6473597d706e 10224 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
bogdanm 82:6473597d706e 10225 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
bogdanm 82:6473597d706e 10226 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
bogdanm 82:6473597d706e 10227 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
bogdanm 82:6473597d706e 10228 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
bogdanm 82:6473597d706e 10229 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
bogdanm 82:6473597d706e 10230 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
bogdanm 82:6473597d706e 10231 uint8_t RESERVED_0[2016];
bogdanm 82:6473597d706e 10232 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
bogdanm 82:6473597d706e 10233 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
bogdanm 82:6473597d706e 10234 } RTC_Type, *RTC_MemMapPtr;
bogdanm 82:6473597d706e 10235
bogdanm 82:6473597d706e 10236 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10237 -- RTC - Register accessor macros
bogdanm 82:6473597d706e 10238 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10239
bogdanm 82:6473597d706e 10240 /*!
bogdanm 82:6473597d706e 10241 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
bogdanm 82:6473597d706e 10242 * @{
bogdanm 82:6473597d706e 10243 */
bogdanm 82:6473597d706e 10244
bogdanm 82:6473597d706e 10245
bogdanm 82:6473597d706e 10246 /* RTC - Register accessors */
bogdanm 82:6473597d706e 10247 #define RTC_TSR_REG(base) ((base)->TSR)
bogdanm 82:6473597d706e 10248 #define RTC_TPR_REG(base) ((base)->TPR)
bogdanm 82:6473597d706e 10249 #define RTC_TAR_REG(base) ((base)->TAR)
bogdanm 82:6473597d706e 10250 #define RTC_TCR_REG(base) ((base)->TCR)
bogdanm 82:6473597d706e 10251 #define RTC_CR_REG(base) ((base)->CR)
bogdanm 82:6473597d706e 10252 #define RTC_SR_REG(base) ((base)->SR)
bogdanm 82:6473597d706e 10253 #define RTC_LR_REG(base) ((base)->LR)
bogdanm 82:6473597d706e 10254 #define RTC_IER_REG(base) ((base)->IER)
bogdanm 82:6473597d706e 10255 #define RTC_WAR_REG(base) ((base)->WAR)
bogdanm 82:6473597d706e 10256 #define RTC_RAR_REG(base) ((base)->RAR)
bogdanm 82:6473597d706e 10257
bogdanm 82:6473597d706e 10258 /*!
bogdanm 82:6473597d706e 10259 * @}
bogdanm 82:6473597d706e 10260 */ /* end of group RTC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 10261
bogdanm 82:6473597d706e 10262
bogdanm 82:6473597d706e 10263 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10264 -- RTC Register Masks
bogdanm 82:6473597d706e 10265 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10266
bogdanm 82:6473597d706e 10267 /*!
bogdanm 82:6473597d706e 10268 * @addtogroup RTC_Register_Masks RTC Register Masks
bogdanm 82:6473597d706e 10269 * @{
bogdanm 82:6473597d706e 10270 */
bogdanm 82:6473597d706e 10271
bogdanm 82:6473597d706e 10272 /* TSR Bit Fields */
bogdanm 82:6473597d706e 10273 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10274 #define RTC_TSR_TSR_SHIFT 0
bogdanm 82:6473597d706e 10275 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
bogdanm 82:6473597d706e 10276 /* TPR Bit Fields */
bogdanm 82:6473597d706e 10277 #define RTC_TPR_TPR_MASK 0xFFFFu
bogdanm 82:6473597d706e 10278 #define RTC_TPR_TPR_SHIFT 0
bogdanm 82:6473597d706e 10279 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
bogdanm 82:6473597d706e 10280 /* TAR Bit Fields */
bogdanm 82:6473597d706e 10281 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10282 #define RTC_TAR_TAR_SHIFT 0
bogdanm 82:6473597d706e 10283 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
bogdanm 82:6473597d706e 10284 /* TCR Bit Fields */
bogdanm 82:6473597d706e 10285 #define RTC_TCR_TCR_MASK 0xFFu
bogdanm 82:6473597d706e 10286 #define RTC_TCR_TCR_SHIFT 0
bogdanm 82:6473597d706e 10287 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
bogdanm 82:6473597d706e 10288 #define RTC_TCR_CIR_MASK 0xFF00u
bogdanm 82:6473597d706e 10289 #define RTC_TCR_CIR_SHIFT 8
bogdanm 82:6473597d706e 10290 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
bogdanm 82:6473597d706e 10291 #define RTC_TCR_TCV_MASK 0xFF0000u
bogdanm 82:6473597d706e 10292 #define RTC_TCR_TCV_SHIFT 16
bogdanm 82:6473597d706e 10293 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
bogdanm 82:6473597d706e 10294 #define RTC_TCR_CIC_MASK 0xFF000000u
bogdanm 82:6473597d706e 10295 #define RTC_TCR_CIC_SHIFT 24
bogdanm 82:6473597d706e 10296 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
bogdanm 82:6473597d706e 10297 /* CR Bit Fields */
bogdanm 82:6473597d706e 10298 #define RTC_CR_SWR_MASK 0x1u
bogdanm 82:6473597d706e 10299 #define RTC_CR_SWR_SHIFT 0
bogdanm 82:6473597d706e 10300 #define RTC_CR_WPE_MASK 0x2u
bogdanm 82:6473597d706e 10301 #define RTC_CR_WPE_SHIFT 1
bogdanm 82:6473597d706e 10302 #define RTC_CR_SUP_MASK 0x4u
bogdanm 82:6473597d706e 10303 #define RTC_CR_SUP_SHIFT 2
bogdanm 82:6473597d706e 10304 #define RTC_CR_UM_MASK 0x8u
bogdanm 82:6473597d706e 10305 #define RTC_CR_UM_SHIFT 3
bogdanm 82:6473597d706e 10306 #define RTC_CR_WPS_MASK 0x10u
bogdanm 82:6473597d706e 10307 #define RTC_CR_WPS_SHIFT 4
bogdanm 82:6473597d706e 10308 #define RTC_CR_OSCE_MASK 0x100u
bogdanm 82:6473597d706e 10309 #define RTC_CR_OSCE_SHIFT 8
bogdanm 82:6473597d706e 10310 #define RTC_CR_CLKO_MASK 0x200u
bogdanm 82:6473597d706e 10311 #define RTC_CR_CLKO_SHIFT 9
bogdanm 82:6473597d706e 10312 #define RTC_CR_SC16P_MASK 0x400u
bogdanm 82:6473597d706e 10313 #define RTC_CR_SC16P_SHIFT 10
bogdanm 82:6473597d706e 10314 #define RTC_CR_SC8P_MASK 0x800u
bogdanm 82:6473597d706e 10315 #define RTC_CR_SC8P_SHIFT 11
bogdanm 82:6473597d706e 10316 #define RTC_CR_SC4P_MASK 0x1000u
bogdanm 82:6473597d706e 10317 #define RTC_CR_SC4P_SHIFT 12
bogdanm 82:6473597d706e 10318 #define RTC_CR_SC2P_MASK 0x2000u
bogdanm 82:6473597d706e 10319 #define RTC_CR_SC2P_SHIFT 13
bogdanm 82:6473597d706e 10320 /* SR Bit Fields */
bogdanm 82:6473597d706e 10321 #define RTC_SR_TIF_MASK 0x1u
bogdanm 82:6473597d706e 10322 #define RTC_SR_TIF_SHIFT 0
bogdanm 82:6473597d706e 10323 #define RTC_SR_TOF_MASK 0x2u
bogdanm 82:6473597d706e 10324 #define RTC_SR_TOF_SHIFT 1
bogdanm 82:6473597d706e 10325 #define RTC_SR_TAF_MASK 0x4u
bogdanm 82:6473597d706e 10326 #define RTC_SR_TAF_SHIFT 2
bogdanm 82:6473597d706e 10327 #define RTC_SR_TCE_MASK 0x10u
bogdanm 82:6473597d706e 10328 #define RTC_SR_TCE_SHIFT 4
bogdanm 82:6473597d706e 10329 /* LR Bit Fields */
bogdanm 82:6473597d706e 10330 #define RTC_LR_TCL_MASK 0x8u
bogdanm 82:6473597d706e 10331 #define RTC_LR_TCL_SHIFT 3
bogdanm 82:6473597d706e 10332 #define RTC_LR_CRL_MASK 0x10u
bogdanm 82:6473597d706e 10333 #define RTC_LR_CRL_SHIFT 4
bogdanm 82:6473597d706e 10334 #define RTC_LR_SRL_MASK 0x20u
bogdanm 82:6473597d706e 10335 #define RTC_LR_SRL_SHIFT 5
bogdanm 82:6473597d706e 10336 #define RTC_LR_LRL_MASK 0x40u
bogdanm 82:6473597d706e 10337 #define RTC_LR_LRL_SHIFT 6
bogdanm 82:6473597d706e 10338 /* IER Bit Fields */
bogdanm 82:6473597d706e 10339 #define RTC_IER_TIIE_MASK 0x1u
bogdanm 82:6473597d706e 10340 #define RTC_IER_TIIE_SHIFT 0
bogdanm 82:6473597d706e 10341 #define RTC_IER_TOIE_MASK 0x2u
bogdanm 82:6473597d706e 10342 #define RTC_IER_TOIE_SHIFT 1
bogdanm 82:6473597d706e 10343 #define RTC_IER_TAIE_MASK 0x4u
bogdanm 82:6473597d706e 10344 #define RTC_IER_TAIE_SHIFT 2
bogdanm 82:6473597d706e 10345 #define RTC_IER_TSIE_MASK 0x10u
bogdanm 82:6473597d706e 10346 #define RTC_IER_TSIE_SHIFT 4
bogdanm 82:6473597d706e 10347 #define RTC_IER_WPON_MASK 0x80u
bogdanm 82:6473597d706e 10348 #define RTC_IER_WPON_SHIFT 7
bogdanm 82:6473597d706e 10349 /* WAR Bit Fields */
bogdanm 82:6473597d706e 10350 #define RTC_WAR_TSRW_MASK 0x1u
bogdanm 82:6473597d706e 10351 #define RTC_WAR_TSRW_SHIFT 0
bogdanm 82:6473597d706e 10352 #define RTC_WAR_TPRW_MASK 0x2u
bogdanm 82:6473597d706e 10353 #define RTC_WAR_TPRW_SHIFT 1
bogdanm 82:6473597d706e 10354 #define RTC_WAR_TARW_MASK 0x4u
bogdanm 82:6473597d706e 10355 #define RTC_WAR_TARW_SHIFT 2
bogdanm 82:6473597d706e 10356 #define RTC_WAR_TCRW_MASK 0x8u
bogdanm 82:6473597d706e 10357 #define RTC_WAR_TCRW_SHIFT 3
bogdanm 82:6473597d706e 10358 #define RTC_WAR_CRW_MASK 0x10u
bogdanm 82:6473597d706e 10359 #define RTC_WAR_CRW_SHIFT 4
bogdanm 82:6473597d706e 10360 #define RTC_WAR_SRW_MASK 0x20u
bogdanm 82:6473597d706e 10361 #define RTC_WAR_SRW_SHIFT 5
bogdanm 82:6473597d706e 10362 #define RTC_WAR_LRW_MASK 0x40u
bogdanm 82:6473597d706e 10363 #define RTC_WAR_LRW_SHIFT 6
bogdanm 82:6473597d706e 10364 #define RTC_WAR_IERW_MASK 0x80u
bogdanm 82:6473597d706e 10365 #define RTC_WAR_IERW_SHIFT 7
bogdanm 82:6473597d706e 10366 /* RAR Bit Fields */
bogdanm 82:6473597d706e 10367 #define RTC_RAR_TSRR_MASK 0x1u
bogdanm 82:6473597d706e 10368 #define RTC_RAR_TSRR_SHIFT 0
bogdanm 82:6473597d706e 10369 #define RTC_RAR_TPRR_MASK 0x2u
bogdanm 82:6473597d706e 10370 #define RTC_RAR_TPRR_SHIFT 1
bogdanm 82:6473597d706e 10371 #define RTC_RAR_TARR_MASK 0x4u
bogdanm 82:6473597d706e 10372 #define RTC_RAR_TARR_SHIFT 2
bogdanm 82:6473597d706e 10373 #define RTC_RAR_TCRR_MASK 0x8u
bogdanm 82:6473597d706e 10374 #define RTC_RAR_TCRR_SHIFT 3
bogdanm 82:6473597d706e 10375 #define RTC_RAR_CRR_MASK 0x10u
bogdanm 82:6473597d706e 10376 #define RTC_RAR_CRR_SHIFT 4
bogdanm 82:6473597d706e 10377 #define RTC_RAR_SRR_MASK 0x20u
bogdanm 82:6473597d706e 10378 #define RTC_RAR_SRR_SHIFT 5
bogdanm 82:6473597d706e 10379 #define RTC_RAR_LRR_MASK 0x40u
bogdanm 82:6473597d706e 10380 #define RTC_RAR_LRR_SHIFT 6
bogdanm 82:6473597d706e 10381 #define RTC_RAR_IERR_MASK 0x80u
bogdanm 82:6473597d706e 10382 #define RTC_RAR_IERR_SHIFT 7
bogdanm 82:6473597d706e 10383
bogdanm 82:6473597d706e 10384 /*!
bogdanm 82:6473597d706e 10385 * @}
bogdanm 82:6473597d706e 10386 */ /* end of group RTC_Register_Masks */
bogdanm 82:6473597d706e 10387
bogdanm 82:6473597d706e 10388
bogdanm 82:6473597d706e 10389 /* RTC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 10390 /** Peripheral RTC base address */
bogdanm 82:6473597d706e 10391 #define RTC_BASE (0x4003D000u)
bogdanm 82:6473597d706e 10392 /** Peripheral RTC base pointer */
bogdanm 82:6473597d706e 10393 #define RTC ((RTC_Type *)RTC_BASE)
bogdanm 82:6473597d706e 10394 #define RTC_BASE_PTR (RTC)
bogdanm 82:6473597d706e 10395 /** Array initializer of RTC peripheral base pointers */
bogdanm 82:6473597d706e 10396 #define RTC_BASES { RTC }
bogdanm 82:6473597d706e 10397
bogdanm 82:6473597d706e 10398 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10399 -- RTC - Register accessor macros
bogdanm 82:6473597d706e 10400 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10401
bogdanm 82:6473597d706e 10402 /*!
bogdanm 82:6473597d706e 10403 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
bogdanm 82:6473597d706e 10404 * @{
bogdanm 82:6473597d706e 10405 */
bogdanm 82:6473597d706e 10406
bogdanm 82:6473597d706e 10407
bogdanm 82:6473597d706e 10408 /* RTC - Register instance definitions */
bogdanm 82:6473597d706e 10409 /* RTC */
bogdanm 82:6473597d706e 10410 #define RTC_TSR RTC_TSR_REG(RTC)
bogdanm 82:6473597d706e 10411 #define RTC_TPR RTC_TPR_REG(RTC)
bogdanm 82:6473597d706e 10412 #define RTC_TAR RTC_TAR_REG(RTC)
bogdanm 82:6473597d706e 10413 #define RTC_TCR RTC_TCR_REG(RTC)
bogdanm 82:6473597d706e 10414 #define RTC_CR RTC_CR_REG(RTC)
bogdanm 82:6473597d706e 10415 #define RTC_SR RTC_SR_REG(RTC)
bogdanm 82:6473597d706e 10416 #define RTC_LR RTC_LR_REG(RTC)
bogdanm 82:6473597d706e 10417 #define RTC_IER RTC_IER_REG(RTC)
bogdanm 82:6473597d706e 10418 #define RTC_WAR RTC_WAR_REG(RTC)
bogdanm 82:6473597d706e 10419 #define RTC_RAR RTC_RAR_REG(RTC)
bogdanm 82:6473597d706e 10420
bogdanm 82:6473597d706e 10421 /*!
bogdanm 82:6473597d706e 10422 * @}
bogdanm 82:6473597d706e 10423 */ /* end of group RTC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 10424
bogdanm 82:6473597d706e 10425
bogdanm 82:6473597d706e 10426 /*!
bogdanm 82:6473597d706e 10427 * @}
bogdanm 82:6473597d706e 10428 */ /* end of group RTC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 10429
bogdanm 82:6473597d706e 10430
bogdanm 82:6473597d706e 10431 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10432 -- SDHC Peripheral Access Layer
bogdanm 82:6473597d706e 10433 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10434
bogdanm 82:6473597d706e 10435 /*!
bogdanm 82:6473597d706e 10436 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
bogdanm 82:6473597d706e 10437 * @{
bogdanm 82:6473597d706e 10438 */
bogdanm 82:6473597d706e 10439
bogdanm 82:6473597d706e 10440 /** SDHC - Register Layout Typedef */
bogdanm 82:6473597d706e 10441 typedef struct {
bogdanm 82:6473597d706e 10442 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
bogdanm 82:6473597d706e 10443 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
bogdanm 82:6473597d706e 10444 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
bogdanm 82:6473597d706e 10445 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
bogdanm 82:6473597d706e 10446 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
bogdanm 82:6473597d706e 10447 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
bogdanm 82:6473597d706e 10448 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
bogdanm 82:6473597d706e 10449 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
bogdanm 82:6473597d706e 10450 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
bogdanm 82:6473597d706e 10451 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
bogdanm 82:6473597d706e 10452 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
bogdanm 82:6473597d706e 10453 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
bogdanm 82:6473597d706e 10454 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
bogdanm 82:6473597d706e 10455 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
bogdanm 82:6473597d706e 10456 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
bogdanm 82:6473597d706e 10457 uint8_t RESERVED_0[8];
bogdanm 82:6473597d706e 10458 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
bogdanm 82:6473597d706e 10459 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
bogdanm 82:6473597d706e 10460 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
bogdanm 82:6473597d706e 10461 uint8_t RESERVED_1[100];
bogdanm 82:6473597d706e 10462 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
bogdanm 82:6473597d706e 10463 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
bogdanm 82:6473597d706e 10464 uint8_t RESERVED_2[52];
bogdanm 82:6473597d706e 10465 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
bogdanm 82:6473597d706e 10466 } SDHC_Type, *SDHC_MemMapPtr;
bogdanm 82:6473597d706e 10467
bogdanm 82:6473597d706e 10468 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10469 -- SDHC - Register accessor macros
bogdanm 82:6473597d706e 10470 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10471
bogdanm 82:6473597d706e 10472 /*!
bogdanm 82:6473597d706e 10473 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
bogdanm 82:6473597d706e 10474 * @{
bogdanm 82:6473597d706e 10475 */
bogdanm 82:6473597d706e 10476
bogdanm 82:6473597d706e 10477
bogdanm 82:6473597d706e 10478 /* SDHC - Register accessors */
bogdanm 82:6473597d706e 10479 #define SDHC_DSADDR_REG(base) ((base)->DSADDR)
bogdanm 82:6473597d706e 10480 #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
bogdanm 82:6473597d706e 10481 #define SDHC_CMDARG_REG(base) ((base)->CMDARG)
bogdanm 82:6473597d706e 10482 #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
bogdanm 82:6473597d706e 10483 #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
bogdanm 82:6473597d706e 10484 #define SDHC_DATPORT_REG(base) ((base)->DATPORT)
bogdanm 82:6473597d706e 10485 #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
bogdanm 82:6473597d706e 10486 #define SDHC_PROCTL_REG(base) ((base)->PROCTL)
bogdanm 82:6473597d706e 10487 #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
bogdanm 82:6473597d706e 10488 #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
bogdanm 82:6473597d706e 10489 #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
bogdanm 82:6473597d706e 10490 #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
bogdanm 82:6473597d706e 10491 #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
bogdanm 82:6473597d706e 10492 #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
bogdanm 82:6473597d706e 10493 #define SDHC_WML_REG(base) ((base)->WML)
bogdanm 82:6473597d706e 10494 #define SDHC_FEVT_REG(base) ((base)->FEVT)
bogdanm 82:6473597d706e 10495 #define SDHC_ADMAES_REG(base) ((base)->ADMAES)
bogdanm 82:6473597d706e 10496 #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
bogdanm 82:6473597d706e 10497 #define SDHC_VENDOR_REG(base) ((base)->VENDOR)
bogdanm 82:6473597d706e 10498 #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
bogdanm 82:6473597d706e 10499 #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
bogdanm 82:6473597d706e 10500
bogdanm 82:6473597d706e 10501 /*!
bogdanm 82:6473597d706e 10502 * @}
bogdanm 82:6473597d706e 10503 */ /* end of group SDHC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 10504
bogdanm 82:6473597d706e 10505
bogdanm 82:6473597d706e 10506 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10507 -- SDHC Register Masks
bogdanm 82:6473597d706e 10508 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10509
bogdanm 82:6473597d706e 10510 /*!
bogdanm 82:6473597d706e 10511 * @addtogroup SDHC_Register_Masks SDHC Register Masks
bogdanm 82:6473597d706e 10512 * @{
bogdanm 82:6473597d706e 10513 */
bogdanm 82:6473597d706e 10514
bogdanm 82:6473597d706e 10515 /* DSADDR Bit Fields */
bogdanm 82:6473597d706e 10516 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
bogdanm 82:6473597d706e 10517 #define SDHC_DSADDR_DSADDR_SHIFT 2
bogdanm 82:6473597d706e 10518 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
bogdanm 82:6473597d706e 10519 /* BLKATTR Bit Fields */
bogdanm 82:6473597d706e 10520 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
bogdanm 82:6473597d706e 10521 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
bogdanm 82:6473597d706e 10522 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
bogdanm 82:6473597d706e 10523 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 10524 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
bogdanm 82:6473597d706e 10525 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
bogdanm 82:6473597d706e 10526 /* CMDARG Bit Fields */
bogdanm 82:6473597d706e 10527 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10528 #define SDHC_CMDARG_CMDARG_SHIFT 0
bogdanm 82:6473597d706e 10529 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
bogdanm 82:6473597d706e 10530 /* XFERTYP Bit Fields */
bogdanm 82:6473597d706e 10531 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
bogdanm 82:6473597d706e 10532 #define SDHC_XFERTYP_DMAEN_SHIFT 0
bogdanm 82:6473597d706e 10533 #define SDHC_XFERTYP_BCEN_MASK 0x2u
bogdanm 82:6473597d706e 10534 #define SDHC_XFERTYP_BCEN_SHIFT 1
bogdanm 82:6473597d706e 10535 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
bogdanm 82:6473597d706e 10536 #define SDHC_XFERTYP_AC12EN_SHIFT 2
bogdanm 82:6473597d706e 10537 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
bogdanm 82:6473597d706e 10538 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
bogdanm 82:6473597d706e 10539 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
bogdanm 82:6473597d706e 10540 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
bogdanm 82:6473597d706e 10541 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
bogdanm 82:6473597d706e 10542 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
bogdanm 82:6473597d706e 10543 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
bogdanm 82:6473597d706e 10544 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
bogdanm 82:6473597d706e 10545 #define SDHC_XFERTYP_CCCEN_SHIFT 19
bogdanm 82:6473597d706e 10546 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
bogdanm 82:6473597d706e 10547 #define SDHC_XFERTYP_CICEN_SHIFT 20
bogdanm 82:6473597d706e 10548 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
bogdanm 82:6473597d706e 10549 #define SDHC_XFERTYP_DPSEL_SHIFT 21
bogdanm 82:6473597d706e 10550 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
bogdanm 82:6473597d706e 10551 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
bogdanm 82:6473597d706e 10552 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
bogdanm 82:6473597d706e 10553 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
bogdanm 82:6473597d706e 10554 #define SDHC_XFERTYP_CMDINX_SHIFT 24
bogdanm 82:6473597d706e 10555 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
bogdanm 82:6473597d706e 10556 /* CMDRSP Bit Fields */
bogdanm 82:6473597d706e 10557 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10558 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
bogdanm 82:6473597d706e 10559 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
bogdanm 82:6473597d706e 10560 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10561 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
bogdanm 82:6473597d706e 10562 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
bogdanm 82:6473597d706e 10563 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10564 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
bogdanm 82:6473597d706e 10565 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
bogdanm 82:6473597d706e 10566 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10567 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
bogdanm 82:6473597d706e 10568 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
bogdanm 82:6473597d706e 10569 /* DATPORT Bit Fields */
bogdanm 82:6473597d706e 10570 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 10571 #define SDHC_DATPORT_DATCONT_SHIFT 0
bogdanm 82:6473597d706e 10572 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
bogdanm 82:6473597d706e 10573 /* PRSSTAT Bit Fields */
bogdanm 82:6473597d706e 10574 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
bogdanm 82:6473597d706e 10575 #define SDHC_PRSSTAT_CIHB_SHIFT 0
bogdanm 82:6473597d706e 10576 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
bogdanm 82:6473597d706e 10577 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
bogdanm 82:6473597d706e 10578 #define SDHC_PRSSTAT_DLA_MASK 0x4u
bogdanm 82:6473597d706e 10579 #define SDHC_PRSSTAT_DLA_SHIFT 2
bogdanm 82:6473597d706e 10580 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
bogdanm 82:6473597d706e 10581 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
bogdanm 82:6473597d706e 10582 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
bogdanm 82:6473597d706e 10583 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
bogdanm 82:6473597d706e 10584 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
bogdanm 82:6473597d706e 10585 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
bogdanm 82:6473597d706e 10586 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
bogdanm 82:6473597d706e 10587 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
bogdanm 82:6473597d706e 10588 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
bogdanm 82:6473597d706e 10589 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
bogdanm 82:6473597d706e 10590 #define SDHC_PRSSTAT_WTA_MASK 0x100u
bogdanm 82:6473597d706e 10591 #define SDHC_PRSSTAT_WTA_SHIFT 8
bogdanm 82:6473597d706e 10592 #define SDHC_PRSSTAT_RTA_MASK 0x200u
bogdanm 82:6473597d706e 10593 #define SDHC_PRSSTAT_RTA_SHIFT 9
bogdanm 82:6473597d706e 10594 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
bogdanm 82:6473597d706e 10595 #define SDHC_PRSSTAT_BWEN_SHIFT 10
bogdanm 82:6473597d706e 10596 #define SDHC_PRSSTAT_BREN_MASK 0x800u
bogdanm 82:6473597d706e 10597 #define SDHC_PRSSTAT_BREN_SHIFT 11
bogdanm 82:6473597d706e 10598 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
bogdanm 82:6473597d706e 10599 #define SDHC_PRSSTAT_CINS_SHIFT 16
bogdanm 82:6473597d706e 10600 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
bogdanm 82:6473597d706e 10601 #define SDHC_PRSSTAT_CLSL_SHIFT 23
bogdanm 82:6473597d706e 10602 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
bogdanm 82:6473597d706e 10603 #define SDHC_PRSSTAT_DLSL_SHIFT 24
bogdanm 82:6473597d706e 10604 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
bogdanm 82:6473597d706e 10605 /* PROCTL Bit Fields */
bogdanm 82:6473597d706e 10606 #define SDHC_PROCTL_LCTL_MASK 0x1u
bogdanm 82:6473597d706e 10607 #define SDHC_PROCTL_LCTL_SHIFT 0
bogdanm 82:6473597d706e 10608 #define SDHC_PROCTL_DTW_MASK 0x6u
bogdanm 82:6473597d706e 10609 #define SDHC_PROCTL_DTW_SHIFT 1
bogdanm 82:6473597d706e 10610 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
bogdanm 82:6473597d706e 10611 #define SDHC_PROCTL_D3CD_MASK 0x8u
bogdanm 82:6473597d706e 10612 #define SDHC_PROCTL_D3CD_SHIFT 3
bogdanm 82:6473597d706e 10613 #define SDHC_PROCTL_EMODE_MASK 0x30u
bogdanm 82:6473597d706e 10614 #define SDHC_PROCTL_EMODE_SHIFT 4
bogdanm 82:6473597d706e 10615 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
bogdanm 82:6473597d706e 10616 #define SDHC_PROCTL_CDTL_MASK 0x40u
bogdanm 82:6473597d706e 10617 #define SDHC_PROCTL_CDTL_SHIFT 6
bogdanm 82:6473597d706e 10618 #define SDHC_PROCTL_CDSS_MASK 0x80u
bogdanm 82:6473597d706e 10619 #define SDHC_PROCTL_CDSS_SHIFT 7
bogdanm 82:6473597d706e 10620 #define SDHC_PROCTL_DMAS_MASK 0x300u
bogdanm 82:6473597d706e 10621 #define SDHC_PROCTL_DMAS_SHIFT 8
bogdanm 82:6473597d706e 10622 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
bogdanm 82:6473597d706e 10623 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
bogdanm 82:6473597d706e 10624 #define SDHC_PROCTL_SABGREQ_SHIFT 16
bogdanm 82:6473597d706e 10625 #define SDHC_PROCTL_CREQ_MASK 0x20000u
bogdanm 82:6473597d706e 10626 #define SDHC_PROCTL_CREQ_SHIFT 17
bogdanm 82:6473597d706e 10627 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
bogdanm 82:6473597d706e 10628 #define SDHC_PROCTL_RWCTL_SHIFT 18
bogdanm 82:6473597d706e 10629 #define SDHC_PROCTL_IABG_MASK 0x80000u
bogdanm 82:6473597d706e 10630 #define SDHC_PROCTL_IABG_SHIFT 19
bogdanm 82:6473597d706e 10631 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
bogdanm 82:6473597d706e 10632 #define SDHC_PROCTL_WECINT_SHIFT 24
bogdanm 82:6473597d706e 10633 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
bogdanm 82:6473597d706e 10634 #define SDHC_PROCTL_WECINS_SHIFT 25
bogdanm 82:6473597d706e 10635 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
bogdanm 82:6473597d706e 10636 #define SDHC_PROCTL_WECRM_SHIFT 26
bogdanm 82:6473597d706e 10637 /* SYSCTL Bit Fields */
bogdanm 82:6473597d706e 10638 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
bogdanm 82:6473597d706e 10639 #define SDHC_SYSCTL_IPGEN_SHIFT 0
bogdanm 82:6473597d706e 10640 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
bogdanm 82:6473597d706e 10641 #define SDHC_SYSCTL_HCKEN_SHIFT 1
bogdanm 82:6473597d706e 10642 #define SDHC_SYSCTL_PEREN_MASK 0x4u
bogdanm 82:6473597d706e 10643 #define SDHC_SYSCTL_PEREN_SHIFT 2
bogdanm 82:6473597d706e 10644 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
bogdanm 82:6473597d706e 10645 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
bogdanm 82:6473597d706e 10646 #define SDHC_SYSCTL_DVS_MASK 0xF0u
bogdanm 82:6473597d706e 10647 #define SDHC_SYSCTL_DVS_SHIFT 4
bogdanm 82:6473597d706e 10648 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
bogdanm 82:6473597d706e 10649 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
bogdanm 82:6473597d706e 10650 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
bogdanm 82:6473597d706e 10651 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
bogdanm 82:6473597d706e 10652 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
bogdanm 82:6473597d706e 10653 #define SDHC_SYSCTL_DTOCV_SHIFT 16
bogdanm 82:6473597d706e 10654 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
bogdanm 82:6473597d706e 10655 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
bogdanm 82:6473597d706e 10656 #define SDHC_SYSCTL_RSTA_SHIFT 24
bogdanm 82:6473597d706e 10657 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
bogdanm 82:6473597d706e 10658 #define SDHC_SYSCTL_RSTC_SHIFT 25
bogdanm 82:6473597d706e 10659 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
bogdanm 82:6473597d706e 10660 #define SDHC_SYSCTL_RSTD_SHIFT 26
bogdanm 82:6473597d706e 10661 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
bogdanm 82:6473597d706e 10662 #define SDHC_SYSCTL_INITA_SHIFT 27
bogdanm 82:6473597d706e 10663 /* IRQSTAT Bit Fields */
bogdanm 82:6473597d706e 10664 #define SDHC_IRQSTAT_CC_MASK 0x1u
bogdanm 82:6473597d706e 10665 #define SDHC_IRQSTAT_CC_SHIFT 0
bogdanm 82:6473597d706e 10666 #define SDHC_IRQSTAT_TC_MASK 0x2u
bogdanm 82:6473597d706e 10667 #define SDHC_IRQSTAT_TC_SHIFT 1
bogdanm 82:6473597d706e 10668 #define SDHC_IRQSTAT_BGE_MASK 0x4u
bogdanm 82:6473597d706e 10669 #define SDHC_IRQSTAT_BGE_SHIFT 2
bogdanm 82:6473597d706e 10670 #define SDHC_IRQSTAT_DINT_MASK 0x8u
bogdanm 82:6473597d706e 10671 #define SDHC_IRQSTAT_DINT_SHIFT 3
bogdanm 82:6473597d706e 10672 #define SDHC_IRQSTAT_BWR_MASK 0x10u
bogdanm 82:6473597d706e 10673 #define SDHC_IRQSTAT_BWR_SHIFT 4
bogdanm 82:6473597d706e 10674 #define SDHC_IRQSTAT_BRR_MASK 0x20u
bogdanm 82:6473597d706e 10675 #define SDHC_IRQSTAT_BRR_SHIFT 5
bogdanm 82:6473597d706e 10676 #define SDHC_IRQSTAT_CINS_MASK 0x40u
bogdanm 82:6473597d706e 10677 #define SDHC_IRQSTAT_CINS_SHIFT 6
bogdanm 82:6473597d706e 10678 #define SDHC_IRQSTAT_CRM_MASK 0x80u
bogdanm 82:6473597d706e 10679 #define SDHC_IRQSTAT_CRM_SHIFT 7
bogdanm 82:6473597d706e 10680 #define SDHC_IRQSTAT_CINT_MASK 0x100u
bogdanm 82:6473597d706e 10681 #define SDHC_IRQSTAT_CINT_SHIFT 8
bogdanm 82:6473597d706e 10682 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
bogdanm 82:6473597d706e 10683 #define SDHC_IRQSTAT_CTOE_SHIFT 16
bogdanm 82:6473597d706e 10684 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
bogdanm 82:6473597d706e 10685 #define SDHC_IRQSTAT_CCE_SHIFT 17
bogdanm 82:6473597d706e 10686 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
bogdanm 82:6473597d706e 10687 #define SDHC_IRQSTAT_CEBE_SHIFT 18
bogdanm 82:6473597d706e 10688 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
bogdanm 82:6473597d706e 10689 #define SDHC_IRQSTAT_CIE_SHIFT 19
bogdanm 82:6473597d706e 10690 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
bogdanm 82:6473597d706e 10691 #define SDHC_IRQSTAT_DTOE_SHIFT 20
bogdanm 82:6473597d706e 10692 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
bogdanm 82:6473597d706e 10693 #define SDHC_IRQSTAT_DCE_SHIFT 21
bogdanm 82:6473597d706e 10694 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
bogdanm 82:6473597d706e 10695 #define SDHC_IRQSTAT_DEBE_SHIFT 22
bogdanm 82:6473597d706e 10696 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
bogdanm 82:6473597d706e 10697 #define SDHC_IRQSTAT_AC12E_SHIFT 24
bogdanm 82:6473597d706e 10698 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
bogdanm 82:6473597d706e 10699 #define SDHC_IRQSTAT_DMAE_SHIFT 28
bogdanm 82:6473597d706e 10700 /* IRQSTATEN Bit Fields */
bogdanm 82:6473597d706e 10701 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
bogdanm 82:6473597d706e 10702 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
bogdanm 82:6473597d706e 10703 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
bogdanm 82:6473597d706e 10704 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
bogdanm 82:6473597d706e 10705 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
bogdanm 82:6473597d706e 10706 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
bogdanm 82:6473597d706e 10707 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
bogdanm 82:6473597d706e 10708 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
bogdanm 82:6473597d706e 10709 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
bogdanm 82:6473597d706e 10710 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
bogdanm 82:6473597d706e 10711 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
bogdanm 82:6473597d706e 10712 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
bogdanm 82:6473597d706e 10713 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
bogdanm 82:6473597d706e 10714 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
bogdanm 82:6473597d706e 10715 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
bogdanm 82:6473597d706e 10716 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
bogdanm 82:6473597d706e 10717 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
bogdanm 82:6473597d706e 10718 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
bogdanm 82:6473597d706e 10719 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
bogdanm 82:6473597d706e 10720 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
bogdanm 82:6473597d706e 10721 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
bogdanm 82:6473597d706e 10722 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
bogdanm 82:6473597d706e 10723 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
bogdanm 82:6473597d706e 10724 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
bogdanm 82:6473597d706e 10725 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
bogdanm 82:6473597d706e 10726 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
bogdanm 82:6473597d706e 10727 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
bogdanm 82:6473597d706e 10728 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
bogdanm 82:6473597d706e 10729 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
bogdanm 82:6473597d706e 10730 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
bogdanm 82:6473597d706e 10731 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
bogdanm 82:6473597d706e 10732 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
bogdanm 82:6473597d706e 10733 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
bogdanm 82:6473597d706e 10734 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
bogdanm 82:6473597d706e 10735 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
bogdanm 82:6473597d706e 10736 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
bogdanm 82:6473597d706e 10737 /* IRQSIGEN Bit Fields */
bogdanm 82:6473597d706e 10738 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
bogdanm 82:6473597d706e 10739 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
bogdanm 82:6473597d706e 10740 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
bogdanm 82:6473597d706e 10741 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
bogdanm 82:6473597d706e 10742 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
bogdanm 82:6473597d706e 10743 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
bogdanm 82:6473597d706e 10744 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
bogdanm 82:6473597d706e 10745 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
bogdanm 82:6473597d706e 10746 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
bogdanm 82:6473597d706e 10747 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
bogdanm 82:6473597d706e 10748 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
bogdanm 82:6473597d706e 10749 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
bogdanm 82:6473597d706e 10750 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
bogdanm 82:6473597d706e 10751 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
bogdanm 82:6473597d706e 10752 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
bogdanm 82:6473597d706e 10753 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
bogdanm 82:6473597d706e 10754 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
bogdanm 82:6473597d706e 10755 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
bogdanm 82:6473597d706e 10756 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
bogdanm 82:6473597d706e 10757 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
bogdanm 82:6473597d706e 10758 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
bogdanm 82:6473597d706e 10759 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
bogdanm 82:6473597d706e 10760 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
bogdanm 82:6473597d706e 10761 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
bogdanm 82:6473597d706e 10762 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
bogdanm 82:6473597d706e 10763 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
bogdanm 82:6473597d706e 10764 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
bogdanm 82:6473597d706e 10765 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
bogdanm 82:6473597d706e 10766 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
bogdanm 82:6473597d706e 10767 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
bogdanm 82:6473597d706e 10768 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
bogdanm 82:6473597d706e 10769 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
bogdanm 82:6473597d706e 10770 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
bogdanm 82:6473597d706e 10771 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
bogdanm 82:6473597d706e 10772 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
bogdanm 82:6473597d706e 10773 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
bogdanm 82:6473597d706e 10774 /* AC12ERR Bit Fields */
bogdanm 82:6473597d706e 10775 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
bogdanm 82:6473597d706e 10776 #define SDHC_AC12ERR_AC12NE_SHIFT 0
bogdanm 82:6473597d706e 10777 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
bogdanm 82:6473597d706e 10778 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
bogdanm 82:6473597d706e 10779 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
bogdanm 82:6473597d706e 10780 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
bogdanm 82:6473597d706e 10781 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
bogdanm 82:6473597d706e 10782 #define SDHC_AC12ERR_AC12CE_SHIFT 3
bogdanm 82:6473597d706e 10783 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
bogdanm 82:6473597d706e 10784 #define SDHC_AC12ERR_AC12IE_SHIFT 4
bogdanm 82:6473597d706e 10785 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
bogdanm 82:6473597d706e 10786 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
bogdanm 82:6473597d706e 10787 /* HTCAPBLT Bit Fields */
bogdanm 82:6473597d706e 10788 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
bogdanm 82:6473597d706e 10789 #define SDHC_HTCAPBLT_MBL_SHIFT 16
bogdanm 82:6473597d706e 10790 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
bogdanm 82:6473597d706e 10791 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
bogdanm 82:6473597d706e 10792 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
bogdanm 82:6473597d706e 10793 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
bogdanm 82:6473597d706e 10794 #define SDHC_HTCAPBLT_HSS_SHIFT 21
bogdanm 82:6473597d706e 10795 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
bogdanm 82:6473597d706e 10796 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
bogdanm 82:6473597d706e 10797 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
bogdanm 82:6473597d706e 10798 #define SDHC_HTCAPBLT_SRS_SHIFT 23
bogdanm 82:6473597d706e 10799 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
bogdanm 82:6473597d706e 10800 #define SDHC_HTCAPBLT_VS33_SHIFT 24
bogdanm 82:6473597d706e 10801 /* WML Bit Fields */
bogdanm 82:6473597d706e 10802 #define SDHC_WML_RDWML_MASK 0xFFu
bogdanm 82:6473597d706e 10803 #define SDHC_WML_RDWML_SHIFT 0
bogdanm 82:6473597d706e 10804 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
bogdanm 82:6473597d706e 10805 #define SDHC_WML_WRWML_MASK 0xFF0000u
bogdanm 82:6473597d706e 10806 #define SDHC_WML_WRWML_SHIFT 16
bogdanm 82:6473597d706e 10807 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
bogdanm 82:6473597d706e 10808 /* FEVT Bit Fields */
bogdanm 82:6473597d706e 10809 #define SDHC_FEVT_AC12NE_MASK 0x1u
bogdanm 82:6473597d706e 10810 #define SDHC_FEVT_AC12NE_SHIFT 0
bogdanm 82:6473597d706e 10811 #define SDHC_FEVT_AC12TOE_MASK 0x2u
bogdanm 82:6473597d706e 10812 #define SDHC_FEVT_AC12TOE_SHIFT 1
bogdanm 82:6473597d706e 10813 #define SDHC_FEVT_AC12CE_MASK 0x4u
bogdanm 82:6473597d706e 10814 #define SDHC_FEVT_AC12CE_SHIFT 2
bogdanm 82:6473597d706e 10815 #define SDHC_FEVT_AC12EBE_MASK 0x8u
bogdanm 82:6473597d706e 10816 #define SDHC_FEVT_AC12EBE_SHIFT 3
bogdanm 82:6473597d706e 10817 #define SDHC_FEVT_AC12IE_MASK 0x10u
bogdanm 82:6473597d706e 10818 #define SDHC_FEVT_AC12IE_SHIFT 4
bogdanm 82:6473597d706e 10819 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
bogdanm 82:6473597d706e 10820 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
bogdanm 82:6473597d706e 10821 #define SDHC_FEVT_CTOE_MASK 0x10000u
bogdanm 82:6473597d706e 10822 #define SDHC_FEVT_CTOE_SHIFT 16
bogdanm 82:6473597d706e 10823 #define SDHC_FEVT_CCE_MASK 0x20000u
bogdanm 82:6473597d706e 10824 #define SDHC_FEVT_CCE_SHIFT 17
bogdanm 82:6473597d706e 10825 #define SDHC_FEVT_CEBE_MASK 0x40000u
bogdanm 82:6473597d706e 10826 #define SDHC_FEVT_CEBE_SHIFT 18
bogdanm 82:6473597d706e 10827 #define SDHC_FEVT_CIE_MASK 0x80000u
bogdanm 82:6473597d706e 10828 #define SDHC_FEVT_CIE_SHIFT 19
bogdanm 82:6473597d706e 10829 #define SDHC_FEVT_DTOE_MASK 0x100000u
bogdanm 82:6473597d706e 10830 #define SDHC_FEVT_DTOE_SHIFT 20
bogdanm 82:6473597d706e 10831 #define SDHC_FEVT_DCE_MASK 0x200000u
bogdanm 82:6473597d706e 10832 #define SDHC_FEVT_DCE_SHIFT 21
bogdanm 82:6473597d706e 10833 #define SDHC_FEVT_DEBE_MASK 0x400000u
bogdanm 82:6473597d706e 10834 #define SDHC_FEVT_DEBE_SHIFT 22
bogdanm 82:6473597d706e 10835 #define SDHC_FEVT_AC12E_MASK 0x1000000u
bogdanm 82:6473597d706e 10836 #define SDHC_FEVT_AC12E_SHIFT 24
bogdanm 82:6473597d706e 10837 #define SDHC_FEVT_DMAE_MASK 0x10000000u
bogdanm 82:6473597d706e 10838 #define SDHC_FEVT_DMAE_SHIFT 28
bogdanm 82:6473597d706e 10839 #define SDHC_FEVT_CINT_MASK 0x80000000u
bogdanm 82:6473597d706e 10840 #define SDHC_FEVT_CINT_SHIFT 31
bogdanm 82:6473597d706e 10841 /* ADMAES Bit Fields */
bogdanm 82:6473597d706e 10842 #define SDHC_ADMAES_ADMAES_MASK 0x3u
bogdanm 82:6473597d706e 10843 #define SDHC_ADMAES_ADMAES_SHIFT 0
bogdanm 82:6473597d706e 10844 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
bogdanm 82:6473597d706e 10845 #define SDHC_ADMAES_ADMALME_MASK 0x4u
bogdanm 82:6473597d706e 10846 #define SDHC_ADMAES_ADMALME_SHIFT 2
bogdanm 82:6473597d706e 10847 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
bogdanm 82:6473597d706e 10848 #define SDHC_ADMAES_ADMADCE_SHIFT 3
bogdanm 82:6473597d706e 10849 /* ADSADDR Bit Fields */
bogdanm 82:6473597d706e 10850 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
bogdanm 82:6473597d706e 10851 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
bogdanm 82:6473597d706e 10852 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
bogdanm 82:6473597d706e 10853 /* VENDOR Bit Fields */
bogdanm 82:6473597d706e 10854 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
bogdanm 82:6473597d706e 10855 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
bogdanm 82:6473597d706e 10856 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
bogdanm 82:6473597d706e 10857 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
bogdanm 82:6473597d706e 10858 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
bogdanm 82:6473597d706e 10859 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
bogdanm 82:6473597d706e 10860 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
bogdanm 82:6473597d706e 10861 /* MMCBOOT Bit Fields */
bogdanm 82:6473597d706e 10862 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
bogdanm 82:6473597d706e 10863 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
bogdanm 82:6473597d706e 10864 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
bogdanm 82:6473597d706e 10865 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
bogdanm 82:6473597d706e 10866 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
bogdanm 82:6473597d706e 10867 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
bogdanm 82:6473597d706e 10868 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
bogdanm 82:6473597d706e 10869 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
bogdanm 82:6473597d706e 10870 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
bogdanm 82:6473597d706e 10871 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
bogdanm 82:6473597d706e 10872 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
bogdanm 82:6473597d706e 10873 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 10874 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
bogdanm 82:6473597d706e 10875 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
bogdanm 82:6473597d706e 10876 /* HOSTVER Bit Fields */
bogdanm 82:6473597d706e 10877 #define SDHC_HOSTVER_SVN_MASK 0xFFu
bogdanm 82:6473597d706e 10878 #define SDHC_HOSTVER_SVN_SHIFT 0
bogdanm 82:6473597d706e 10879 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
bogdanm 82:6473597d706e 10880 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
bogdanm 82:6473597d706e 10881 #define SDHC_HOSTVER_VVN_SHIFT 8
bogdanm 82:6473597d706e 10882 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
bogdanm 82:6473597d706e 10883
bogdanm 82:6473597d706e 10884 /*!
bogdanm 82:6473597d706e 10885 * @}
bogdanm 82:6473597d706e 10886 */ /* end of group SDHC_Register_Masks */
bogdanm 82:6473597d706e 10887
bogdanm 82:6473597d706e 10888
bogdanm 82:6473597d706e 10889 /* SDHC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 10890 /** Peripheral SDHC base address */
bogdanm 82:6473597d706e 10891 #define SDHC_BASE (0x400B1000u)
bogdanm 82:6473597d706e 10892 /** Peripheral SDHC base pointer */
bogdanm 82:6473597d706e 10893 #define SDHC ((SDHC_Type *)SDHC_BASE)
bogdanm 82:6473597d706e 10894 #define SDHC_BASE_PTR (SDHC)
bogdanm 82:6473597d706e 10895 /** Array initializer of SDHC peripheral base pointers */
bogdanm 82:6473597d706e 10896 #define SDHC_BASES { SDHC }
bogdanm 82:6473597d706e 10897
bogdanm 82:6473597d706e 10898 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10899 -- SDHC - Register accessor macros
bogdanm 82:6473597d706e 10900 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10901
bogdanm 82:6473597d706e 10902 /*!
bogdanm 82:6473597d706e 10903 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
bogdanm 82:6473597d706e 10904 * @{
bogdanm 82:6473597d706e 10905 */
bogdanm 82:6473597d706e 10906
bogdanm 82:6473597d706e 10907
bogdanm 82:6473597d706e 10908 /* SDHC - Register instance definitions */
bogdanm 82:6473597d706e 10909 /* SDHC */
bogdanm 82:6473597d706e 10910 #define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
bogdanm 82:6473597d706e 10911 #define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
bogdanm 82:6473597d706e 10912 #define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
bogdanm 82:6473597d706e 10913 #define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
bogdanm 82:6473597d706e 10914 #define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
bogdanm 82:6473597d706e 10915 #define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
bogdanm 82:6473597d706e 10916 #define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
bogdanm 82:6473597d706e 10917 #define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
bogdanm 82:6473597d706e 10918 #define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
bogdanm 82:6473597d706e 10919 #define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
bogdanm 82:6473597d706e 10920 #define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
bogdanm 82:6473597d706e 10921 #define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
bogdanm 82:6473597d706e 10922 #define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
bogdanm 82:6473597d706e 10923 #define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
bogdanm 82:6473597d706e 10924 #define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
bogdanm 82:6473597d706e 10925 #define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
bogdanm 82:6473597d706e 10926 #define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
bogdanm 82:6473597d706e 10927 #define SDHC_WML SDHC_WML_REG(SDHC)
bogdanm 82:6473597d706e 10928 #define SDHC_FEVT SDHC_FEVT_REG(SDHC)
bogdanm 82:6473597d706e 10929 #define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
bogdanm 82:6473597d706e 10930 #define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
bogdanm 82:6473597d706e 10931 #define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
bogdanm 82:6473597d706e 10932 #define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
bogdanm 82:6473597d706e 10933 #define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
bogdanm 82:6473597d706e 10934
bogdanm 82:6473597d706e 10935 /* SDHC - Register array accessors */
bogdanm 82:6473597d706e 10936 #define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
bogdanm 82:6473597d706e 10937
bogdanm 82:6473597d706e 10938 /*!
bogdanm 82:6473597d706e 10939 * @}
bogdanm 82:6473597d706e 10940 */ /* end of group SDHC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 10941
bogdanm 82:6473597d706e 10942
bogdanm 82:6473597d706e 10943 /*!
bogdanm 82:6473597d706e 10944 * @}
bogdanm 82:6473597d706e 10945 */ /* end of group SDHC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 10946
bogdanm 82:6473597d706e 10947
bogdanm 82:6473597d706e 10948 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10949 -- SIM Peripheral Access Layer
bogdanm 82:6473597d706e 10950 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10951
bogdanm 82:6473597d706e 10952 /*!
bogdanm 82:6473597d706e 10953 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
bogdanm 82:6473597d706e 10954 * @{
bogdanm 82:6473597d706e 10955 */
bogdanm 82:6473597d706e 10956
bogdanm 82:6473597d706e 10957 /** SIM - Register Layout Typedef */
bogdanm 82:6473597d706e 10958 typedef struct {
bogdanm 82:6473597d706e 10959 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
bogdanm 82:6473597d706e 10960 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
bogdanm 82:6473597d706e 10961 uint8_t RESERVED_0[4092];
bogdanm 82:6473597d706e 10962 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
bogdanm 82:6473597d706e 10963 uint8_t RESERVED_1[4];
bogdanm 82:6473597d706e 10964 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
bogdanm 82:6473597d706e 10965 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
bogdanm 82:6473597d706e 10966 uint8_t RESERVED_2[4];
bogdanm 82:6473597d706e 10967 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
bogdanm 82:6473597d706e 10968 uint8_t RESERVED_3[8];
bogdanm 82:6473597d706e 10969 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
bogdanm 82:6473597d706e 10970 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
bogdanm 82:6473597d706e 10971 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
bogdanm 82:6473597d706e 10972 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
bogdanm 82:6473597d706e 10973 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
bogdanm 82:6473597d706e 10974 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
bogdanm 82:6473597d706e 10975 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
bogdanm 82:6473597d706e 10976 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
bogdanm 82:6473597d706e 10977 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
bogdanm 82:6473597d706e 10978 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
bogdanm 82:6473597d706e 10979 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
bogdanm 82:6473597d706e 10980 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
bogdanm 82:6473597d706e 10981 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
bogdanm 82:6473597d706e 10982 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
bogdanm 82:6473597d706e 10983 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
bogdanm 82:6473597d706e 10984 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
bogdanm 82:6473597d706e 10985 } SIM_Type, *SIM_MemMapPtr;
bogdanm 82:6473597d706e 10986
bogdanm 82:6473597d706e 10987 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 10988 -- SIM - Register accessor macros
bogdanm 82:6473597d706e 10989 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 10990
bogdanm 82:6473597d706e 10991 /*!
bogdanm 82:6473597d706e 10992 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
bogdanm 82:6473597d706e 10993 * @{
bogdanm 82:6473597d706e 10994 */
bogdanm 82:6473597d706e 10995
bogdanm 82:6473597d706e 10996
bogdanm 82:6473597d706e 10997 /* SIM - Register accessors */
bogdanm 82:6473597d706e 10998 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
bogdanm 82:6473597d706e 10999 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
bogdanm 82:6473597d706e 11000 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
bogdanm 82:6473597d706e 11001 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
bogdanm 82:6473597d706e 11002 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
bogdanm 82:6473597d706e 11003 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
bogdanm 82:6473597d706e 11004 #define SIM_SDID_REG(base) ((base)->SDID)
bogdanm 82:6473597d706e 11005 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
bogdanm 82:6473597d706e 11006 #define SIM_SCGC2_REG(base) ((base)->SCGC2)
bogdanm 82:6473597d706e 11007 #define SIM_SCGC3_REG(base) ((base)->SCGC3)
bogdanm 82:6473597d706e 11008 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
bogdanm 82:6473597d706e 11009 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
bogdanm 82:6473597d706e 11010 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
bogdanm 82:6473597d706e 11011 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
bogdanm 82:6473597d706e 11012 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
bogdanm 82:6473597d706e 11013 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
bogdanm 82:6473597d706e 11014 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
bogdanm 82:6473597d706e 11015 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
bogdanm 82:6473597d706e 11016 #define SIM_UIDH_REG(base) ((base)->UIDH)
bogdanm 82:6473597d706e 11017 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
bogdanm 82:6473597d706e 11018 #define SIM_UIDML_REG(base) ((base)->UIDML)
bogdanm 82:6473597d706e 11019 #define SIM_UIDL_REG(base) ((base)->UIDL)
bogdanm 82:6473597d706e 11020
bogdanm 82:6473597d706e 11021 /*!
bogdanm 82:6473597d706e 11022 * @}
bogdanm 82:6473597d706e 11023 */ /* end of group SIM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 11024
bogdanm 82:6473597d706e 11025
bogdanm 82:6473597d706e 11026 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11027 -- SIM Register Masks
bogdanm 82:6473597d706e 11028 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11029
bogdanm 82:6473597d706e 11030 /*!
bogdanm 82:6473597d706e 11031 * @addtogroup SIM_Register_Masks SIM Register Masks
bogdanm 82:6473597d706e 11032 * @{
bogdanm 82:6473597d706e 11033 */
bogdanm 82:6473597d706e 11034
bogdanm 82:6473597d706e 11035 /* SOPT1 Bit Fields */
bogdanm 82:6473597d706e 11036 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
bogdanm 82:6473597d706e 11037 #define SIM_SOPT1_RAMSIZE_SHIFT 12
bogdanm 82:6473597d706e 11038 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
bogdanm 82:6473597d706e 11039 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
bogdanm 82:6473597d706e 11040 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
bogdanm 82:6473597d706e 11041 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
bogdanm 82:6473597d706e 11042 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
bogdanm 82:6473597d706e 11043 #define SIM_SOPT1_USBVSTBY_SHIFT 29
bogdanm 82:6473597d706e 11044 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
bogdanm 82:6473597d706e 11045 #define SIM_SOPT1_USBSSTBY_SHIFT 30
bogdanm 82:6473597d706e 11046 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
bogdanm 82:6473597d706e 11047 #define SIM_SOPT1_USBREGEN_SHIFT 31
bogdanm 82:6473597d706e 11048 /* SOPT1CFG Bit Fields */
bogdanm 82:6473597d706e 11049 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
bogdanm 82:6473597d706e 11050 #define SIM_SOPT1CFG_URWE_SHIFT 24
bogdanm 82:6473597d706e 11051 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
bogdanm 82:6473597d706e 11052 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
bogdanm 82:6473597d706e 11053 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
bogdanm 82:6473597d706e 11054 #define SIM_SOPT1CFG_USSWE_SHIFT 26
bogdanm 82:6473597d706e 11055 /* SOPT2 Bit Fields */
bogdanm 82:6473597d706e 11056 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
bogdanm 82:6473597d706e 11057 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
bogdanm 82:6473597d706e 11058 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
bogdanm 82:6473597d706e 11059 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
bogdanm 82:6473597d706e 11060 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
bogdanm 82:6473597d706e 11061 #define SIM_SOPT2_FBSL_MASK 0x300u
bogdanm 82:6473597d706e 11062 #define SIM_SOPT2_FBSL_SHIFT 8
bogdanm 82:6473597d706e 11063 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
bogdanm 82:6473597d706e 11064 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
bogdanm 82:6473597d706e 11065 #define SIM_SOPT2_PTD7PAD_SHIFT 11
bogdanm 82:6473597d706e 11066 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
bogdanm 82:6473597d706e 11067 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
bogdanm 82:6473597d706e 11068 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
bogdanm 82:6473597d706e 11069 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
bogdanm 82:6473597d706e 11070 #define SIM_SOPT2_USBSRC_MASK 0x40000u
bogdanm 82:6473597d706e 11071 #define SIM_SOPT2_USBSRC_SHIFT 18
bogdanm 82:6473597d706e 11072 #define SIM_SOPT2_RMIISRC_MASK 0x80000u
bogdanm 82:6473597d706e 11073 #define SIM_SOPT2_RMIISRC_SHIFT 19
bogdanm 82:6473597d706e 11074 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
bogdanm 82:6473597d706e 11075 #define SIM_SOPT2_TIMESRC_SHIFT 20
bogdanm 82:6473597d706e 11076 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
bogdanm 82:6473597d706e 11077 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
bogdanm 82:6473597d706e 11078 #define SIM_SOPT2_SDHCSRC_SHIFT 28
bogdanm 82:6473597d706e 11079 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
bogdanm 82:6473597d706e 11080 /* SOPT4 Bit Fields */
bogdanm 82:6473597d706e 11081 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
bogdanm 82:6473597d706e 11082 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
bogdanm 82:6473597d706e 11083 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
bogdanm 82:6473597d706e 11084 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
bogdanm 82:6473597d706e 11085 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
bogdanm 82:6473597d706e 11086 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
bogdanm 82:6473597d706e 11087 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
bogdanm 82:6473597d706e 11088 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
bogdanm 82:6473597d706e 11089 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
bogdanm 82:6473597d706e 11090 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
bogdanm 82:6473597d706e 11091 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
bogdanm 82:6473597d706e 11092 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
bogdanm 82:6473597d706e 11093 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
bogdanm 82:6473597d706e 11094 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
bogdanm 82:6473597d706e 11095 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
bogdanm 82:6473597d706e 11096 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
bogdanm 82:6473597d706e 11097 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
bogdanm 82:6473597d706e 11098 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
bogdanm 82:6473597d706e 11099 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
bogdanm 82:6473597d706e 11100 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
bogdanm 82:6473597d706e 11101 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
bogdanm 82:6473597d706e 11102 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
bogdanm 82:6473597d706e 11103 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
bogdanm 82:6473597d706e 11104 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
bogdanm 82:6473597d706e 11105 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
bogdanm 82:6473597d706e 11106 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
bogdanm 82:6473597d706e 11107 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
bogdanm 82:6473597d706e 11108 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
bogdanm 82:6473597d706e 11109 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
bogdanm 82:6473597d706e 11110 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
bogdanm 82:6473597d706e 11111 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
bogdanm 82:6473597d706e 11112 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
bogdanm 82:6473597d706e 11113 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
bogdanm 82:6473597d706e 11114 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
bogdanm 82:6473597d706e 11115 /* SOPT5 Bit Fields */
bogdanm 82:6473597d706e 11116 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
bogdanm 82:6473597d706e 11117 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
bogdanm 82:6473597d706e 11118 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
bogdanm 82:6473597d706e 11119 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
bogdanm 82:6473597d706e 11120 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
bogdanm 82:6473597d706e 11121 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
bogdanm 82:6473597d706e 11122 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
bogdanm 82:6473597d706e 11123 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
bogdanm 82:6473597d706e 11124 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
bogdanm 82:6473597d706e 11125 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
bogdanm 82:6473597d706e 11126 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
bogdanm 82:6473597d706e 11127 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
bogdanm 82:6473597d706e 11128 /* SOPT7 Bit Fields */
bogdanm 82:6473597d706e 11129 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
bogdanm 82:6473597d706e 11130 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
bogdanm 82:6473597d706e 11131 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
bogdanm 82:6473597d706e 11132 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
bogdanm 82:6473597d706e 11133 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
bogdanm 82:6473597d706e 11134 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
bogdanm 82:6473597d706e 11135 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
bogdanm 82:6473597d706e 11136 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
bogdanm 82:6473597d706e 11137 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
bogdanm 82:6473597d706e 11138 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
bogdanm 82:6473597d706e 11139 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
bogdanm 82:6473597d706e 11140 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
bogdanm 82:6473597d706e 11141 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
bogdanm 82:6473597d706e 11142 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
bogdanm 82:6473597d706e 11143 /* SDID Bit Fields */
bogdanm 82:6473597d706e 11144 #define SIM_SDID_PINID_MASK 0xFu
bogdanm 82:6473597d706e 11145 #define SIM_SDID_PINID_SHIFT 0
bogdanm 82:6473597d706e 11146 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
bogdanm 82:6473597d706e 11147 #define SIM_SDID_FAMID_MASK 0x70u
bogdanm 82:6473597d706e 11148 #define SIM_SDID_FAMID_SHIFT 4
bogdanm 82:6473597d706e 11149 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
bogdanm 82:6473597d706e 11150 #define SIM_SDID_DIEID_MASK 0xF80u
bogdanm 82:6473597d706e 11151 #define SIM_SDID_DIEID_SHIFT 7
bogdanm 82:6473597d706e 11152 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
bogdanm 82:6473597d706e 11153 #define SIM_SDID_REVID_MASK 0xF000u
bogdanm 82:6473597d706e 11154 #define SIM_SDID_REVID_SHIFT 12
bogdanm 82:6473597d706e 11155 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
bogdanm 82:6473597d706e 11156 #define SIM_SDID_SERIESID_MASK 0xF00000u
bogdanm 82:6473597d706e 11157 #define SIM_SDID_SERIESID_SHIFT 20
bogdanm 82:6473597d706e 11158 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
bogdanm 82:6473597d706e 11159 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
bogdanm 82:6473597d706e 11160 #define SIM_SDID_SUBFAMID_SHIFT 24
bogdanm 82:6473597d706e 11161 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
bogdanm 82:6473597d706e 11162 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
bogdanm 82:6473597d706e 11163 #define SIM_SDID_FAMILYID_SHIFT 28
bogdanm 82:6473597d706e 11164 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
bogdanm 82:6473597d706e 11165 /* SCGC1 Bit Fields */
bogdanm 82:6473597d706e 11166 #define SIM_SCGC1_I2C2_MASK 0x40u
bogdanm 82:6473597d706e 11167 #define SIM_SCGC1_I2C2_SHIFT 6
bogdanm 82:6473597d706e 11168 #define SIM_SCGC1_UART4_MASK 0x400u
bogdanm 82:6473597d706e 11169 #define SIM_SCGC1_UART4_SHIFT 10
bogdanm 82:6473597d706e 11170 #define SIM_SCGC1_UART5_MASK 0x800u
bogdanm 82:6473597d706e 11171 #define SIM_SCGC1_UART5_SHIFT 11
bogdanm 82:6473597d706e 11172 /* SCGC2 Bit Fields */
bogdanm 82:6473597d706e 11173 #define SIM_SCGC2_ENET_MASK 0x1u
bogdanm 82:6473597d706e 11174 #define SIM_SCGC2_ENET_SHIFT 0
bogdanm 82:6473597d706e 11175 #define SIM_SCGC2_DAC0_MASK 0x1000u
bogdanm 82:6473597d706e 11176 #define SIM_SCGC2_DAC0_SHIFT 12
bogdanm 82:6473597d706e 11177 #define SIM_SCGC2_DAC1_MASK 0x2000u
bogdanm 82:6473597d706e 11178 #define SIM_SCGC2_DAC1_SHIFT 13
bogdanm 82:6473597d706e 11179 /* SCGC3 Bit Fields */
bogdanm 82:6473597d706e 11180 #define SIM_SCGC3_RNGA_MASK 0x1u
bogdanm 82:6473597d706e 11181 #define SIM_SCGC3_RNGA_SHIFT 0
bogdanm 82:6473597d706e 11182 #define SIM_SCGC3_SPI2_MASK 0x1000u
bogdanm 82:6473597d706e 11183 #define SIM_SCGC3_SPI2_SHIFT 12
bogdanm 82:6473597d706e 11184 #define SIM_SCGC3_SDHC_MASK 0x20000u
bogdanm 82:6473597d706e 11185 #define SIM_SCGC3_SDHC_SHIFT 17
bogdanm 82:6473597d706e 11186 #define SIM_SCGC3_FTM2_MASK 0x1000000u
bogdanm 82:6473597d706e 11187 #define SIM_SCGC3_FTM2_SHIFT 24
bogdanm 82:6473597d706e 11188 #define SIM_SCGC3_FTM3_MASK 0x2000000u
bogdanm 82:6473597d706e 11189 #define SIM_SCGC3_FTM3_SHIFT 25
bogdanm 82:6473597d706e 11190 #define SIM_SCGC3_ADC1_MASK 0x8000000u
bogdanm 82:6473597d706e 11191 #define SIM_SCGC3_ADC1_SHIFT 27
bogdanm 82:6473597d706e 11192 /* SCGC4 Bit Fields */
bogdanm 82:6473597d706e 11193 #define SIM_SCGC4_EWM_MASK 0x2u
bogdanm 82:6473597d706e 11194 #define SIM_SCGC4_EWM_SHIFT 1
bogdanm 82:6473597d706e 11195 #define SIM_SCGC4_CMT_MASK 0x4u
bogdanm 82:6473597d706e 11196 #define SIM_SCGC4_CMT_SHIFT 2
bogdanm 82:6473597d706e 11197 #define SIM_SCGC4_I2C0_MASK 0x40u
bogdanm 82:6473597d706e 11198 #define SIM_SCGC4_I2C0_SHIFT 6
bogdanm 82:6473597d706e 11199 #define SIM_SCGC4_I2C1_MASK 0x80u
bogdanm 82:6473597d706e 11200 #define SIM_SCGC4_I2C1_SHIFT 7
bogdanm 82:6473597d706e 11201 #define SIM_SCGC4_UART0_MASK 0x400u
bogdanm 82:6473597d706e 11202 #define SIM_SCGC4_UART0_SHIFT 10
bogdanm 82:6473597d706e 11203 #define SIM_SCGC4_UART1_MASK 0x800u
bogdanm 82:6473597d706e 11204 #define SIM_SCGC4_UART1_SHIFT 11
bogdanm 82:6473597d706e 11205 #define SIM_SCGC4_UART2_MASK 0x1000u
bogdanm 82:6473597d706e 11206 #define SIM_SCGC4_UART2_SHIFT 12
bogdanm 82:6473597d706e 11207 #define SIM_SCGC4_UART3_MASK 0x2000u
bogdanm 82:6473597d706e 11208 #define SIM_SCGC4_UART3_SHIFT 13
bogdanm 82:6473597d706e 11209 #define SIM_SCGC4_USBOTG_MASK 0x40000u
bogdanm 82:6473597d706e 11210 #define SIM_SCGC4_USBOTG_SHIFT 18
bogdanm 82:6473597d706e 11211 #define SIM_SCGC4_CMP_MASK 0x80000u
bogdanm 82:6473597d706e 11212 #define SIM_SCGC4_CMP_SHIFT 19
bogdanm 82:6473597d706e 11213 #define SIM_SCGC4_VREF_MASK 0x100000u
bogdanm 82:6473597d706e 11214 #define SIM_SCGC4_VREF_SHIFT 20
bogdanm 82:6473597d706e 11215 /* SCGC5 Bit Fields */
bogdanm 82:6473597d706e 11216 #define SIM_SCGC5_LPTMR_MASK 0x1u
bogdanm 82:6473597d706e 11217 #define SIM_SCGC5_LPTMR_SHIFT 0
bogdanm 82:6473597d706e 11218 #define SIM_SCGC5_PORTA_MASK 0x200u
bogdanm 82:6473597d706e 11219 #define SIM_SCGC5_PORTA_SHIFT 9
bogdanm 82:6473597d706e 11220 #define SIM_SCGC5_PORTB_MASK 0x400u
bogdanm 82:6473597d706e 11221 #define SIM_SCGC5_PORTB_SHIFT 10
bogdanm 82:6473597d706e 11222 #define SIM_SCGC5_PORTC_MASK 0x800u
bogdanm 82:6473597d706e 11223 #define SIM_SCGC5_PORTC_SHIFT 11
bogdanm 82:6473597d706e 11224 #define SIM_SCGC5_PORTD_MASK 0x1000u
bogdanm 82:6473597d706e 11225 #define SIM_SCGC5_PORTD_SHIFT 12
bogdanm 82:6473597d706e 11226 #define SIM_SCGC5_PORTE_MASK 0x2000u
bogdanm 82:6473597d706e 11227 #define SIM_SCGC5_PORTE_SHIFT 13
bogdanm 82:6473597d706e 11228 /* SCGC6 Bit Fields */
bogdanm 82:6473597d706e 11229 #define SIM_SCGC6_FTF_MASK 0x1u
bogdanm 82:6473597d706e 11230 #define SIM_SCGC6_FTF_SHIFT 0
bogdanm 82:6473597d706e 11231 #define SIM_SCGC6_DMAMUX_MASK 0x2u
bogdanm 82:6473597d706e 11232 #define SIM_SCGC6_DMAMUX_SHIFT 1
bogdanm 82:6473597d706e 11233 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
bogdanm 82:6473597d706e 11234 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
bogdanm 82:6473597d706e 11235 #define SIM_SCGC6_RNGA_MASK 0x200u
bogdanm 82:6473597d706e 11236 #define SIM_SCGC6_RNGA_SHIFT 9
bogdanm 82:6473597d706e 11237 #define SIM_SCGC6_SPI0_MASK 0x1000u
bogdanm 82:6473597d706e 11238 #define SIM_SCGC6_SPI0_SHIFT 12
bogdanm 82:6473597d706e 11239 #define SIM_SCGC6_SPI1_MASK 0x2000u
bogdanm 82:6473597d706e 11240 #define SIM_SCGC6_SPI1_SHIFT 13
bogdanm 82:6473597d706e 11241 #define SIM_SCGC6_I2S_MASK 0x8000u
bogdanm 82:6473597d706e 11242 #define SIM_SCGC6_I2S_SHIFT 15
bogdanm 82:6473597d706e 11243 #define SIM_SCGC6_CRC_MASK 0x40000u
bogdanm 82:6473597d706e 11244 #define SIM_SCGC6_CRC_SHIFT 18
bogdanm 82:6473597d706e 11245 #define SIM_SCGC6_USBDCD_MASK 0x200000u
bogdanm 82:6473597d706e 11246 #define SIM_SCGC6_USBDCD_SHIFT 21
bogdanm 82:6473597d706e 11247 #define SIM_SCGC6_PDB_MASK 0x400000u
bogdanm 82:6473597d706e 11248 #define SIM_SCGC6_PDB_SHIFT 22
bogdanm 82:6473597d706e 11249 #define SIM_SCGC6_PIT_MASK 0x800000u
bogdanm 82:6473597d706e 11250 #define SIM_SCGC6_PIT_SHIFT 23
bogdanm 82:6473597d706e 11251 #define SIM_SCGC6_FTM0_MASK 0x1000000u
bogdanm 82:6473597d706e 11252 #define SIM_SCGC6_FTM0_SHIFT 24
bogdanm 82:6473597d706e 11253 #define SIM_SCGC6_FTM1_MASK 0x2000000u
bogdanm 82:6473597d706e 11254 #define SIM_SCGC6_FTM1_SHIFT 25
bogdanm 82:6473597d706e 11255 #define SIM_SCGC6_FTM2_MASK 0x4000000u
bogdanm 82:6473597d706e 11256 #define SIM_SCGC6_FTM2_SHIFT 26
bogdanm 82:6473597d706e 11257 #define SIM_SCGC6_ADC0_MASK 0x8000000u
bogdanm 82:6473597d706e 11258 #define SIM_SCGC6_ADC0_SHIFT 27
bogdanm 82:6473597d706e 11259 #define SIM_SCGC6_RTC_MASK 0x20000000u
bogdanm 82:6473597d706e 11260 #define SIM_SCGC6_RTC_SHIFT 29
bogdanm 82:6473597d706e 11261 #define SIM_SCGC6_DAC0_MASK 0x80000000u
bogdanm 82:6473597d706e 11262 #define SIM_SCGC6_DAC0_SHIFT 31
bogdanm 82:6473597d706e 11263 /* SCGC7 Bit Fields */
bogdanm 82:6473597d706e 11264 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
bogdanm 82:6473597d706e 11265 #define SIM_SCGC7_FLEXBUS_SHIFT 0
bogdanm 82:6473597d706e 11266 #define SIM_SCGC7_DMA_MASK 0x2u
bogdanm 82:6473597d706e 11267 #define SIM_SCGC7_DMA_SHIFT 1
bogdanm 82:6473597d706e 11268 #define SIM_SCGC7_MPU_MASK 0x4u
bogdanm 82:6473597d706e 11269 #define SIM_SCGC7_MPU_SHIFT 2
bogdanm 82:6473597d706e 11270 /* CLKDIV1 Bit Fields */
bogdanm 82:6473597d706e 11271 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
bogdanm 82:6473597d706e 11272 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
bogdanm 82:6473597d706e 11273 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
bogdanm 82:6473597d706e 11274 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
bogdanm 82:6473597d706e 11275 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
bogdanm 82:6473597d706e 11276 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
bogdanm 82:6473597d706e 11277 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
bogdanm 82:6473597d706e 11278 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
bogdanm 82:6473597d706e 11279 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
bogdanm 82:6473597d706e 11280 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
bogdanm 82:6473597d706e 11281 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
bogdanm 82:6473597d706e 11282 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
bogdanm 82:6473597d706e 11283 /* CLKDIV2 Bit Fields */
bogdanm 82:6473597d706e 11284 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
bogdanm 82:6473597d706e 11285 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
bogdanm 82:6473597d706e 11286 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
bogdanm 82:6473597d706e 11287 #define SIM_CLKDIV2_USBDIV_SHIFT 1
bogdanm 82:6473597d706e 11288 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
bogdanm 82:6473597d706e 11289 /* FCFG1 Bit Fields */
bogdanm 82:6473597d706e 11290 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
bogdanm 82:6473597d706e 11291 #define SIM_FCFG1_FLASHDIS_SHIFT 0
bogdanm 82:6473597d706e 11292 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
bogdanm 82:6473597d706e 11293 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
bogdanm 82:6473597d706e 11294 #define SIM_FCFG1_DEPART_MASK 0xF00u
bogdanm 82:6473597d706e 11295 #define SIM_FCFG1_DEPART_SHIFT 8
bogdanm 82:6473597d706e 11296 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
bogdanm 82:6473597d706e 11297 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
bogdanm 82:6473597d706e 11298 #define SIM_FCFG1_EESIZE_SHIFT 16
bogdanm 82:6473597d706e 11299 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
bogdanm 82:6473597d706e 11300 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
bogdanm 82:6473597d706e 11301 #define SIM_FCFG1_PFSIZE_SHIFT 24
bogdanm 82:6473597d706e 11302 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
bogdanm 82:6473597d706e 11303 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
bogdanm 82:6473597d706e 11304 #define SIM_FCFG1_NVMSIZE_SHIFT 28
bogdanm 82:6473597d706e 11305 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
bogdanm 82:6473597d706e 11306 /* FCFG2 Bit Fields */
bogdanm 82:6473597d706e 11307 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
bogdanm 82:6473597d706e 11308 #define SIM_FCFG2_MAXADDR1_SHIFT 16
bogdanm 82:6473597d706e 11309 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
bogdanm 82:6473597d706e 11310 #define SIM_FCFG2_PFLSH_MASK 0x800000u
bogdanm 82:6473597d706e 11311 #define SIM_FCFG2_PFLSH_SHIFT 23
bogdanm 82:6473597d706e 11312 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
bogdanm 82:6473597d706e 11313 #define SIM_FCFG2_MAXADDR0_SHIFT 24
bogdanm 82:6473597d706e 11314 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
bogdanm 82:6473597d706e 11315 /* UIDH Bit Fields */
bogdanm 82:6473597d706e 11316 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11317 #define SIM_UIDH_UID_SHIFT 0
bogdanm 82:6473597d706e 11318 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
bogdanm 82:6473597d706e 11319 /* UIDMH Bit Fields */
bogdanm 82:6473597d706e 11320 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11321 #define SIM_UIDMH_UID_SHIFT 0
bogdanm 82:6473597d706e 11322 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
bogdanm 82:6473597d706e 11323 /* UIDML Bit Fields */
bogdanm 82:6473597d706e 11324 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11325 #define SIM_UIDML_UID_SHIFT 0
bogdanm 82:6473597d706e 11326 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
bogdanm 82:6473597d706e 11327 /* UIDL Bit Fields */
bogdanm 82:6473597d706e 11328 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11329 #define SIM_UIDL_UID_SHIFT 0
bogdanm 82:6473597d706e 11330 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
bogdanm 82:6473597d706e 11331
bogdanm 82:6473597d706e 11332 /*!
bogdanm 82:6473597d706e 11333 * @}
bogdanm 82:6473597d706e 11334 */ /* end of group SIM_Register_Masks */
bogdanm 82:6473597d706e 11335
bogdanm 82:6473597d706e 11336
bogdanm 82:6473597d706e 11337 /* SIM - Peripheral instance base addresses */
bogdanm 82:6473597d706e 11338 /** Peripheral SIM base address */
bogdanm 82:6473597d706e 11339 #define SIM_BASE (0x40047000u)
bogdanm 82:6473597d706e 11340 /** Peripheral SIM base pointer */
bogdanm 82:6473597d706e 11341 #define SIM ((SIM_Type *)SIM_BASE)
bogdanm 82:6473597d706e 11342 #define SIM_BASE_PTR (SIM)
bogdanm 82:6473597d706e 11343 /** Array initializer of SIM peripheral base pointers */
bogdanm 82:6473597d706e 11344 #define SIM_BASES { SIM }
bogdanm 82:6473597d706e 11345
bogdanm 82:6473597d706e 11346 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11347 -- SIM - Register accessor macros
bogdanm 82:6473597d706e 11348 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11349
bogdanm 82:6473597d706e 11350 /*!
bogdanm 82:6473597d706e 11351 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
bogdanm 82:6473597d706e 11352 * @{
bogdanm 82:6473597d706e 11353 */
bogdanm 82:6473597d706e 11354
bogdanm 82:6473597d706e 11355
bogdanm 82:6473597d706e 11356 /* SIM - Register instance definitions */
bogdanm 82:6473597d706e 11357 /* SIM */
bogdanm 82:6473597d706e 11358 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
bogdanm 82:6473597d706e 11359 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
bogdanm 82:6473597d706e 11360 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
bogdanm 82:6473597d706e 11361 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
bogdanm 82:6473597d706e 11362 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
bogdanm 82:6473597d706e 11363 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
bogdanm 82:6473597d706e 11364 #define SIM_SDID SIM_SDID_REG(SIM)
bogdanm 82:6473597d706e 11365 #define SIM_SCGC1 SIM_SCGC1_REG(SIM)
bogdanm 82:6473597d706e 11366 #define SIM_SCGC2 SIM_SCGC2_REG(SIM)
bogdanm 82:6473597d706e 11367 #define SIM_SCGC3 SIM_SCGC3_REG(SIM)
bogdanm 82:6473597d706e 11368 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
bogdanm 82:6473597d706e 11369 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
bogdanm 82:6473597d706e 11370 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
bogdanm 82:6473597d706e 11371 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
bogdanm 82:6473597d706e 11372 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
bogdanm 82:6473597d706e 11373 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
bogdanm 82:6473597d706e 11374 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
bogdanm 82:6473597d706e 11375 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
bogdanm 82:6473597d706e 11376 #define SIM_UIDH SIM_UIDH_REG(SIM)
bogdanm 82:6473597d706e 11377 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
bogdanm 82:6473597d706e 11378 #define SIM_UIDML SIM_UIDML_REG(SIM)
bogdanm 82:6473597d706e 11379 #define SIM_UIDL SIM_UIDL_REG(SIM)
bogdanm 82:6473597d706e 11380
bogdanm 82:6473597d706e 11381 /*!
bogdanm 82:6473597d706e 11382 * @}
bogdanm 82:6473597d706e 11383 */ /* end of group SIM_Register_Accessor_Macros */
bogdanm 82:6473597d706e 11384
bogdanm 82:6473597d706e 11385
bogdanm 82:6473597d706e 11386 /*!
bogdanm 82:6473597d706e 11387 * @}
bogdanm 82:6473597d706e 11388 */ /* end of group SIM_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 11389
bogdanm 82:6473597d706e 11390
bogdanm 82:6473597d706e 11391 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11392 -- SMC Peripheral Access Layer
bogdanm 82:6473597d706e 11393 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11394
bogdanm 82:6473597d706e 11395 /*!
bogdanm 82:6473597d706e 11396 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
bogdanm 82:6473597d706e 11397 * @{
bogdanm 82:6473597d706e 11398 */
bogdanm 82:6473597d706e 11399
bogdanm 82:6473597d706e 11400 /** SMC - Register Layout Typedef */
bogdanm 82:6473597d706e 11401 typedef struct {
bogdanm 82:6473597d706e 11402 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
bogdanm 82:6473597d706e 11403 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
bogdanm 82:6473597d706e 11404 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
bogdanm 82:6473597d706e 11405 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
bogdanm 82:6473597d706e 11406 } SMC_Type, *SMC_MemMapPtr;
bogdanm 82:6473597d706e 11407
bogdanm 82:6473597d706e 11408 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11409 -- SMC - Register accessor macros
bogdanm 82:6473597d706e 11410 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11411
bogdanm 82:6473597d706e 11412 /*!
bogdanm 82:6473597d706e 11413 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
bogdanm 82:6473597d706e 11414 * @{
bogdanm 82:6473597d706e 11415 */
bogdanm 82:6473597d706e 11416
bogdanm 82:6473597d706e 11417
bogdanm 82:6473597d706e 11418 /* SMC - Register accessors */
bogdanm 82:6473597d706e 11419 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
bogdanm 82:6473597d706e 11420 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
bogdanm 82:6473597d706e 11421 #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
bogdanm 82:6473597d706e 11422 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
bogdanm 82:6473597d706e 11423
bogdanm 82:6473597d706e 11424 /*!
bogdanm 82:6473597d706e 11425 * @}
bogdanm 82:6473597d706e 11426 */ /* end of group SMC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 11427
bogdanm 82:6473597d706e 11428
bogdanm 82:6473597d706e 11429 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11430 -- SMC Register Masks
bogdanm 82:6473597d706e 11431 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11432
bogdanm 82:6473597d706e 11433 /*!
bogdanm 82:6473597d706e 11434 * @addtogroup SMC_Register_Masks SMC Register Masks
bogdanm 82:6473597d706e 11435 * @{
bogdanm 82:6473597d706e 11436 */
bogdanm 82:6473597d706e 11437
bogdanm 82:6473597d706e 11438 /* PMPROT Bit Fields */
bogdanm 82:6473597d706e 11439 #define SMC_PMPROT_AVLLS_MASK 0x2u
bogdanm 82:6473597d706e 11440 #define SMC_PMPROT_AVLLS_SHIFT 1
bogdanm 82:6473597d706e 11441 #define SMC_PMPROT_ALLS_MASK 0x8u
bogdanm 82:6473597d706e 11442 #define SMC_PMPROT_ALLS_SHIFT 3
bogdanm 82:6473597d706e 11443 #define SMC_PMPROT_AVLP_MASK 0x20u
bogdanm 82:6473597d706e 11444 #define SMC_PMPROT_AVLP_SHIFT 5
bogdanm 82:6473597d706e 11445 /* PMCTRL Bit Fields */
bogdanm 82:6473597d706e 11446 #define SMC_PMCTRL_STOPM_MASK 0x7u
bogdanm 82:6473597d706e 11447 #define SMC_PMCTRL_STOPM_SHIFT 0
bogdanm 82:6473597d706e 11448 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
bogdanm 82:6473597d706e 11449 #define SMC_PMCTRL_STOPA_MASK 0x8u
bogdanm 82:6473597d706e 11450 #define SMC_PMCTRL_STOPA_SHIFT 3
bogdanm 82:6473597d706e 11451 #define SMC_PMCTRL_RUNM_MASK 0x60u
bogdanm 82:6473597d706e 11452 #define SMC_PMCTRL_RUNM_SHIFT 5
bogdanm 82:6473597d706e 11453 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
bogdanm 82:6473597d706e 11454 #define SMC_PMCTRL_LPWUI_MASK 0x80u
bogdanm 82:6473597d706e 11455 #define SMC_PMCTRL_LPWUI_SHIFT 7
bogdanm 82:6473597d706e 11456 /* VLLSCTRL Bit Fields */
bogdanm 82:6473597d706e 11457 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
bogdanm 82:6473597d706e 11458 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
bogdanm 82:6473597d706e 11459 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
bogdanm 82:6473597d706e 11460 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
bogdanm 82:6473597d706e 11461 #define SMC_VLLSCTRL_PORPO_SHIFT 5
bogdanm 82:6473597d706e 11462 /* PMSTAT Bit Fields */
bogdanm 82:6473597d706e 11463 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
bogdanm 82:6473597d706e 11464 #define SMC_PMSTAT_PMSTAT_SHIFT 0
bogdanm 82:6473597d706e 11465 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
bogdanm 82:6473597d706e 11466
bogdanm 82:6473597d706e 11467 /*!
bogdanm 82:6473597d706e 11468 * @}
bogdanm 82:6473597d706e 11469 */ /* end of group SMC_Register_Masks */
bogdanm 82:6473597d706e 11470
bogdanm 82:6473597d706e 11471
bogdanm 82:6473597d706e 11472 /* SMC - Peripheral instance base addresses */
bogdanm 82:6473597d706e 11473 /** Peripheral SMC base address */
bogdanm 82:6473597d706e 11474 #define SMC_BASE (0x4007E000u)
bogdanm 82:6473597d706e 11475 /** Peripheral SMC base pointer */
bogdanm 82:6473597d706e 11476 #define SMC ((SMC_Type *)SMC_BASE)
bogdanm 82:6473597d706e 11477 #define SMC_BASE_PTR (SMC)
bogdanm 82:6473597d706e 11478 /** Array initializer of SMC peripheral base pointers */
bogdanm 82:6473597d706e 11479 #define SMC_BASES { SMC }
bogdanm 82:6473597d706e 11480
bogdanm 82:6473597d706e 11481 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11482 -- SMC - Register accessor macros
bogdanm 82:6473597d706e 11483 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11484
bogdanm 82:6473597d706e 11485 /*!
bogdanm 82:6473597d706e 11486 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
bogdanm 82:6473597d706e 11487 * @{
bogdanm 82:6473597d706e 11488 */
bogdanm 82:6473597d706e 11489
bogdanm 82:6473597d706e 11490
bogdanm 82:6473597d706e 11491 /* SMC - Register instance definitions */
bogdanm 82:6473597d706e 11492 /* SMC */
bogdanm 82:6473597d706e 11493 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
bogdanm 82:6473597d706e 11494 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
bogdanm 82:6473597d706e 11495 #define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
bogdanm 82:6473597d706e 11496 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
bogdanm 82:6473597d706e 11497
bogdanm 82:6473597d706e 11498 /*!
bogdanm 82:6473597d706e 11499 * @}
bogdanm 82:6473597d706e 11500 */ /* end of group SMC_Register_Accessor_Macros */
bogdanm 82:6473597d706e 11501
bogdanm 82:6473597d706e 11502
bogdanm 82:6473597d706e 11503 /*!
bogdanm 82:6473597d706e 11504 * @}
bogdanm 82:6473597d706e 11505 */ /* end of group SMC_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 11506
bogdanm 82:6473597d706e 11507
bogdanm 82:6473597d706e 11508 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11509 -- SPI Peripheral Access Layer
bogdanm 82:6473597d706e 11510 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11511
bogdanm 82:6473597d706e 11512 /*!
bogdanm 82:6473597d706e 11513 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
bogdanm 82:6473597d706e 11514 * @{
bogdanm 82:6473597d706e 11515 */
bogdanm 82:6473597d706e 11516
bogdanm 82:6473597d706e 11517 /** SPI - Register Layout Typedef */
bogdanm 82:6473597d706e 11518 typedef struct {
bogdanm 82:6473597d706e 11519 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
bogdanm 82:6473597d706e 11520 uint8_t RESERVED_0[4];
bogdanm 82:6473597d706e 11521 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
bogdanm 82:6473597d706e 11522 union { /* offset: 0xC */
bogdanm 82:6473597d706e 11523 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
bogdanm 82:6473597d706e 11524 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
bogdanm 82:6473597d706e 11525 };
bogdanm 82:6473597d706e 11526 uint8_t RESERVED_1[24];
bogdanm 82:6473597d706e 11527 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
bogdanm 82:6473597d706e 11528 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
bogdanm 82:6473597d706e 11529 union { /* offset: 0x34 */
bogdanm 82:6473597d706e 11530 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
bogdanm 82:6473597d706e 11531 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
bogdanm 82:6473597d706e 11532 };
bogdanm 82:6473597d706e 11533 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
bogdanm 82:6473597d706e 11534 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
bogdanm 82:6473597d706e 11535 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
bogdanm 82:6473597d706e 11536 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
bogdanm 82:6473597d706e 11537 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
bogdanm 82:6473597d706e 11538 uint8_t RESERVED_2[48];
bogdanm 82:6473597d706e 11539 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
bogdanm 82:6473597d706e 11540 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
bogdanm 82:6473597d706e 11541 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
bogdanm 82:6473597d706e 11542 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
bogdanm 82:6473597d706e 11543 } SPI_Type, *SPI_MemMapPtr;
bogdanm 82:6473597d706e 11544
bogdanm 82:6473597d706e 11545 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11546 -- SPI - Register accessor macros
bogdanm 82:6473597d706e 11547 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11548
bogdanm 82:6473597d706e 11549 /*!
bogdanm 82:6473597d706e 11550 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
bogdanm 82:6473597d706e 11551 * @{
bogdanm 82:6473597d706e 11552 */
bogdanm 82:6473597d706e 11553
bogdanm 82:6473597d706e 11554
bogdanm 82:6473597d706e 11555 /* SPI - Register accessors */
bogdanm 82:6473597d706e 11556 #define SPI_MCR_REG(base) ((base)->MCR)
bogdanm 82:6473597d706e 11557 #define SPI_TCR_REG(base) ((base)->TCR)
bogdanm 82:6473597d706e 11558 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
bogdanm 82:6473597d706e 11559 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
bogdanm 82:6473597d706e 11560 #define SPI_SR_REG(base) ((base)->SR)
bogdanm 82:6473597d706e 11561 #define SPI_RSER_REG(base) ((base)->RSER)
bogdanm 82:6473597d706e 11562 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
bogdanm 82:6473597d706e 11563 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
bogdanm 82:6473597d706e 11564 #define SPI_POPR_REG(base) ((base)->POPR)
bogdanm 82:6473597d706e 11565 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
bogdanm 82:6473597d706e 11566 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
bogdanm 82:6473597d706e 11567 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
bogdanm 82:6473597d706e 11568 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
bogdanm 82:6473597d706e 11569 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
bogdanm 82:6473597d706e 11570 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
bogdanm 82:6473597d706e 11571 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
bogdanm 82:6473597d706e 11572 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
bogdanm 82:6473597d706e 11573
bogdanm 82:6473597d706e 11574 /*!
bogdanm 82:6473597d706e 11575 * @}
bogdanm 82:6473597d706e 11576 */ /* end of group SPI_Register_Accessor_Macros */
bogdanm 82:6473597d706e 11577
bogdanm 82:6473597d706e 11578
bogdanm 82:6473597d706e 11579 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11580 -- SPI Register Masks
bogdanm 82:6473597d706e 11581 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11582
bogdanm 82:6473597d706e 11583 /*!
bogdanm 82:6473597d706e 11584 * @addtogroup SPI_Register_Masks SPI Register Masks
bogdanm 82:6473597d706e 11585 * @{
bogdanm 82:6473597d706e 11586 */
bogdanm 82:6473597d706e 11587
bogdanm 82:6473597d706e 11588 /* MCR Bit Fields */
bogdanm 82:6473597d706e 11589 #define SPI_MCR_HALT_MASK 0x1u
bogdanm 82:6473597d706e 11590 #define SPI_MCR_HALT_SHIFT 0
bogdanm 82:6473597d706e 11591 #define SPI_MCR_SMPL_PT_MASK 0x300u
bogdanm 82:6473597d706e 11592 #define SPI_MCR_SMPL_PT_SHIFT 8
bogdanm 82:6473597d706e 11593 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
bogdanm 82:6473597d706e 11594 #define SPI_MCR_CLR_RXF_MASK 0x400u
bogdanm 82:6473597d706e 11595 #define SPI_MCR_CLR_RXF_SHIFT 10
bogdanm 82:6473597d706e 11596 #define SPI_MCR_CLR_TXF_MASK 0x800u
bogdanm 82:6473597d706e 11597 #define SPI_MCR_CLR_TXF_SHIFT 11
bogdanm 82:6473597d706e 11598 #define SPI_MCR_DIS_RXF_MASK 0x1000u
bogdanm 82:6473597d706e 11599 #define SPI_MCR_DIS_RXF_SHIFT 12
bogdanm 82:6473597d706e 11600 #define SPI_MCR_DIS_TXF_MASK 0x2000u
bogdanm 82:6473597d706e 11601 #define SPI_MCR_DIS_TXF_SHIFT 13
bogdanm 82:6473597d706e 11602 #define SPI_MCR_MDIS_MASK 0x4000u
bogdanm 82:6473597d706e 11603 #define SPI_MCR_MDIS_SHIFT 14
bogdanm 82:6473597d706e 11604 #define SPI_MCR_DOZE_MASK 0x8000u
bogdanm 82:6473597d706e 11605 #define SPI_MCR_DOZE_SHIFT 15
bogdanm 82:6473597d706e 11606 #define SPI_MCR_PCSIS_MASK 0x3F0000u
bogdanm 82:6473597d706e 11607 #define SPI_MCR_PCSIS_SHIFT 16
bogdanm 82:6473597d706e 11608 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
bogdanm 82:6473597d706e 11609 #define SPI_MCR_ROOE_MASK 0x1000000u
bogdanm 82:6473597d706e 11610 #define SPI_MCR_ROOE_SHIFT 24
bogdanm 82:6473597d706e 11611 #define SPI_MCR_PCSSE_MASK 0x2000000u
bogdanm 82:6473597d706e 11612 #define SPI_MCR_PCSSE_SHIFT 25
bogdanm 82:6473597d706e 11613 #define SPI_MCR_MTFE_MASK 0x4000000u
bogdanm 82:6473597d706e 11614 #define SPI_MCR_MTFE_SHIFT 26
bogdanm 82:6473597d706e 11615 #define SPI_MCR_FRZ_MASK 0x8000000u
bogdanm 82:6473597d706e 11616 #define SPI_MCR_FRZ_SHIFT 27
bogdanm 82:6473597d706e 11617 #define SPI_MCR_DCONF_MASK 0x30000000u
bogdanm 82:6473597d706e 11618 #define SPI_MCR_DCONF_SHIFT 28
bogdanm 82:6473597d706e 11619 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
bogdanm 82:6473597d706e 11620 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
bogdanm 82:6473597d706e 11621 #define SPI_MCR_CONT_SCKE_SHIFT 30
bogdanm 82:6473597d706e 11622 #define SPI_MCR_MSTR_MASK 0x80000000u
bogdanm 82:6473597d706e 11623 #define SPI_MCR_MSTR_SHIFT 31
bogdanm 82:6473597d706e 11624 /* TCR Bit Fields */
bogdanm 82:6473597d706e 11625 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 11626 #define SPI_TCR_SPI_TCNT_SHIFT 16
bogdanm 82:6473597d706e 11627 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
bogdanm 82:6473597d706e 11628 /* CTAR Bit Fields */
bogdanm 82:6473597d706e 11629 #define SPI_CTAR_BR_MASK 0xFu
bogdanm 82:6473597d706e 11630 #define SPI_CTAR_BR_SHIFT 0
bogdanm 82:6473597d706e 11631 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
bogdanm 82:6473597d706e 11632 #define SPI_CTAR_DT_MASK 0xF0u
bogdanm 82:6473597d706e 11633 #define SPI_CTAR_DT_SHIFT 4
bogdanm 82:6473597d706e 11634 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
bogdanm 82:6473597d706e 11635 #define SPI_CTAR_ASC_MASK 0xF00u
bogdanm 82:6473597d706e 11636 #define SPI_CTAR_ASC_SHIFT 8
bogdanm 82:6473597d706e 11637 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
bogdanm 82:6473597d706e 11638 #define SPI_CTAR_CSSCK_MASK 0xF000u
bogdanm 82:6473597d706e 11639 #define SPI_CTAR_CSSCK_SHIFT 12
bogdanm 82:6473597d706e 11640 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
bogdanm 82:6473597d706e 11641 #define SPI_CTAR_PBR_MASK 0x30000u
bogdanm 82:6473597d706e 11642 #define SPI_CTAR_PBR_SHIFT 16
bogdanm 82:6473597d706e 11643 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
bogdanm 82:6473597d706e 11644 #define SPI_CTAR_PDT_MASK 0xC0000u
bogdanm 82:6473597d706e 11645 #define SPI_CTAR_PDT_SHIFT 18
bogdanm 82:6473597d706e 11646 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
bogdanm 82:6473597d706e 11647 #define SPI_CTAR_PASC_MASK 0x300000u
bogdanm 82:6473597d706e 11648 #define SPI_CTAR_PASC_SHIFT 20
bogdanm 82:6473597d706e 11649 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
bogdanm 82:6473597d706e 11650 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
bogdanm 82:6473597d706e 11651 #define SPI_CTAR_PCSSCK_SHIFT 22
bogdanm 82:6473597d706e 11652 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
bogdanm 82:6473597d706e 11653 #define SPI_CTAR_LSBFE_MASK 0x1000000u
bogdanm 82:6473597d706e 11654 #define SPI_CTAR_LSBFE_SHIFT 24
bogdanm 82:6473597d706e 11655 #define SPI_CTAR_CPHA_MASK 0x2000000u
bogdanm 82:6473597d706e 11656 #define SPI_CTAR_CPHA_SHIFT 25
bogdanm 82:6473597d706e 11657 #define SPI_CTAR_CPOL_MASK 0x4000000u
bogdanm 82:6473597d706e 11658 #define SPI_CTAR_CPOL_SHIFT 26
bogdanm 82:6473597d706e 11659 #define SPI_CTAR_FMSZ_MASK 0x78000000u
bogdanm 82:6473597d706e 11660 #define SPI_CTAR_FMSZ_SHIFT 27
bogdanm 82:6473597d706e 11661 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
bogdanm 82:6473597d706e 11662 #define SPI_CTAR_DBR_MASK 0x80000000u
bogdanm 82:6473597d706e 11663 #define SPI_CTAR_DBR_SHIFT 31
bogdanm 82:6473597d706e 11664 /* CTAR_SLAVE Bit Fields */
bogdanm 82:6473597d706e 11665 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
bogdanm 82:6473597d706e 11666 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
bogdanm 82:6473597d706e 11667 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
bogdanm 82:6473597d706e 11668 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
bogdanm 82:6473597d706e 11669 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
bogdanm 82:6473597d706e 11670 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
bogdanm 82:6473597d706e 11671 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
bogdanm 82:6473597d706e 11672 /* SR Bit Fields */
bogdanm 82:6473597d706e 11673 #define SPI_SR_POPNXTPTR_MASK 0xFu
bogdanm 82:6473597d706e 11674 #define SPI_SR_POPNXTPTR_SHIFT 0
bogdanm 82:6473597d706e 11675 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
bogdanm 82:6473597d706e 11676 #define SPI_SR_RXCTR_MASK 0xF0u
bogdanm 82:6473597d706e 11677 #define SPI_SR_RXCTR_SHIFT 4
bogdanm 82:6473597d706e 11678 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
bogdanm 82:6473597d706e 11679 #define SPI_SR_TXNXTPTR_MASK 0xF00u
bogdanm 82:6473597d706e 11680 #define SPI_SR_TXNXTPTR_SHIFT 8
bogdanm 82:6473597d706e 11681 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
bogdanm 82:6473597d706e 11682 #define SPI_SR_TXCTR_MASK 0xF000u
bogdanm 82:6473597d706e 11683 #define SPI_SR_TXCTR_SHIFT 12
bogdanm 82:6473597d706e 11684 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
bogdanm 82:6473597d706e 11685 #define SPI_SR_RFDF_MASK 0x20000u
bogdanm 82:6473597d706e 11686 #define SPI_SR_RFDF_SHIFT 17
bogdanm 82:6473597d706e 11687 #define SPI_SR_RFOF_MASK 0x80000u
bogdanm 82:6473597d706e 11688 #define SPI_SR_RFOF_SHIFT 19
bogdanm 82:6473597d706e 11689 #define SPI_SR_TFFF_MASK 0x2000000u
bogdanm 82:6473597d706e 11690 #define SPI_SR_TFFF_SHIFT 25
bogdanm 82:6473597d706e 11691 #define SPI_SR_TFUF_MASK 0x8000000u
bogdanm 82:6473597d706e 11692 #define SPI_SR_TFUF_SHIFT 27
bogdanm 82:6473597d706e 11693 #define SPI_SR_EOQF_MASK 0x10000000u
bogdanm 82:6473597d706e 11694 #define SPI_SR_EOQF_SHIFT 28
bogdanm 82:6473597d706e 11695 #define SPI_SR_TXRXS_MASK 0x40000000u
bogdanm 82:6473597d706e 11696 #define SPI_SR_TXRXS_SHIFT 30
bogdanm 82:6473597d706e 11697 #define SPI_SR_TCF_MASK 0x80000000u
bogdanm 82:6473597d706e 11698 #define SPI_SR_TCF_SHIFT 31
bogdanm 82:6473597d706e 11699 /* RSER Bit Fields */
bogdanm 82:6473597d706e 11700 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
bogdanm 82:6473597d706e 11701 #define SPI_RSER_RFDF_DIRS_SHIFT 16
bogdanm 82:6473597d706e 11702 #define SPI_RSER_RFDF_RE_MASK 0x20000u
bogdanm 82:6473597d706e 11703 #define SPI_RSER_RFDF_RE_SHIFT 17
bogdanm 82:6473597d706e 11704 #define SPI_RSER_RFOF_RE_MASK 0x80000u
bogdanm 82:6473597d706e 11705 #define SPI_RSER_RFOF_RE_SHIFT 19
bogdanm 82:6473597d706e 11706 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
bogdanm 82:6473597d706e 11707 #define SPI_RSER_TFFF_DIRS_SHIFT 24
bogdanm 82:6473597d706e 11708 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
bogdanm 82:6473597d706e 11709 #define SPI_RSER_TFFF_RE_SHIFT 25
bogdanm 82:6473597d706e 11710 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
bogdanm 82:6473597d706e 11711 #define SPI_RSER_TFUF_RE_SHIFT 27
bogdanm 82:6473597d706e 11712 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
bogdanm 82:6473597d706e 11713 #define SPI_RSER_EOQF_RE_SHIFT 28
bogdanm 82:6473597d706e 11714 #define SPI_RSER_TCF_RE_MASK 0x80000000u
bogdanm 82:6473597d706e 11715 #define SPI_RSER_TCF_RE_SHIFT 31
bogdanm 82:6473597d706e 11716 /* PUSHR Bit Fields */
bogdanm 82:6473597d706e 11717 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
bogdanm 82:6473597d706e 11718 #define SPI_PUSHR_TXDATA_SHIFT 0
bogdanm 82:6473597d706e 11719 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
bogdanm 82:6473597d706e 11720 #define SPI_PUSHR_PCS_MASK 0x3F0000u
bogdanm 82:6473597d706e 11721 #define SPI_PUSHR_PCS_SHIFT 16
bogdanm 82:6473597d706e 11722 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
bogdanm 82:6473597d706e 11723 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
bogdanm 82:6473597d706e 11724 #define SPI_PUSHR_CTCNT_SHIFT 26
bogdanm 82:6473597d706e 11725 #define SPI_PUSHR_EOQ_MASK 0x8000000u
bogdanm 82:6473597d706e 11726 #define SPI_PUSHR_EOQ_SHIFT 27
bogdanm 82:6473597d706e 11727 #define SPI_PUSHR_CTAS_MASK 0x70000000u
bogdanm 82:6473597d706e 11728 #define SPI_PUSHR_CTAS_SHIFT 28
bogdanm 82:6473597d706e 11729 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
bogdanm 82:6473597d706e 11730 #define SPI_PUSHR_CONT_MASK 0x80000000u
bogdanm 82:6473597d706e 11731 #define SPI_PUSHR_CONT_SHIFT 31
bogdanm 82:6473597d706e 11732 /* PUSHR_SLAVE Bit Fields */
bogdanm 82:6473597d706e 11733 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11734 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
bogdanm 82:6473597d706e 11735 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
bogdanm 82:6473597d706e 11736 /* POPR Bit Fields */
bogdanm 82:6473597d706e 11737 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11738 #define SPI_POPR_RXDATA_SHIFT 0
bogdanm 82:6473597d706e 11739 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
bogdanm 82:6473597d706e 11740 /* TXFR0 Bit Fields */
bogdanm 82:6473597d706e 11741 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
bogdanm 82:6473597d706e 11742 #define SPI_TXFR0_TXDATA_SHIFT 0
bogdanm 82:6473597d706e 11743 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
bogdanm 82:6473597d706e 11744 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 11745 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
bogdanm 82:6473597d706e 11746 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
bogdanm 82:6473597d706e 11747 /* TXFR1 Bit Fields */
bogdanm 82:6473597d706e 11748 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
bogdanm 82:6473597d706e 11749 #define SPI_TXFR1_TXDATA_SHIFT 0
bogdanm 82:6473597d706e 11750 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
bogdanm 82:6473597d706e 11751 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 11752 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
bogdanm 82:6473597d706e 11753 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
bogdanm 82:6473597d706e 11754 /* TXFR2 Bit Fields */
bogdanm 82:6473597d706e 11755 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
bogdanm 82:6473597d706e 11756 #define SPI_TXFR2_TXDATA_SHIFT 0
bogdanm 82:6473597d706e 11757 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
bogdanm 82:6473597d706e 11758 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 11759 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
bogdanm 82:6473597d706e 11760 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
bogdanm 82:6473597d706e 11761 /* TXFR3 Bit Fields */
bogdanm 82:6473597d706e 11762 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
bogdanm 82:6473597d706e 11763 #define SPI_TXFR3_TXDATA_SHIFT 0
bogdanm 82:6473597d706e 11764 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
bogdanm 82:6473597d706e 11765 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
bogdanm 82:6473597d706e 11766 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
bogdanm 82:6473597d706e 11767 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
bogdanm 82:6473597d706e 11768 /* RXFR0 Bit Fields */
bogdanm 82:6473597d706e 11769 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11770 #define SPI_RXFR0_RXDATA_SHIFT 0
bogdanm 82:6473597d706e 11771 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
bogdanm 82:6473597d706e 11772 /* RXFR1 Bit Fields */
bogdanm 82:6473597d706e 11773 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11774 #define SPI_RXFR1_RXDATA_SHIFT 0
bogdanm 82:6473597d706e 11775 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
bogdanm 82:6473597d706e 11776 /* RXFR2 Bit Fields */
bogdanm 82:6473597d706e 11777 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11778 #define SPI_RXFR2_RXDATA_SHIFT 0
bogdanm 82:6473597d706e 11779 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
bogdanm 82:6473597d706e 11780 /* RXFR3 Bit Fields */
bogdanm 82:6473597d706e 11781 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
bogdanm 82:6473597d706e 11782 #define SPI_RXFR3_RXDATA_SHIFT 0
bogdanm 82:6473597d706e 11783 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
bogdanm 82:6473597d706e 11784
bogdanm 82:6473597d706e 11785 /*!
bogdanm 82:6473597d706e 11786 * @}
bogdanm 82:6473597d706e 11787 */ /* end of group SPI_Register_Masks */
bogdanm 82:6473597d706e 11788
bogdanm 82:6473597d706e 11789
bogdanm 82:6473597d706e 11790 /* SPI - Peripheral instance base addresses */
bogdanm 82:6473597d706e 11791 /** Peripheral SPI0 base address */
bogdanm 82:6473597d706e 11792 #define SPI0_BASE (0x4002C000u)
bogdanm 82:6473597d706e 11793 /** Peripheral SPI0 base pointer */
bogdanm 82:6473597d706e 11794 #define SPI0 ((SPI_Type *)SPI0_BASE)
bogdanm 82:6473597d706e 11795 #define SPI0_BASE_PTR (SPI0)
bogdanm 82:6473597d706e 11796 /** Peripheral SPI1 base address */
bogdanm 82:6473597d706e 11797 #define SPI1_BASE (0x4002D000u)
bogdanm 82:6473597d706e 11798 /** Peripheral SPI1 base pointer */
bogdanm 82:6473597d706e 11799 #define SPI1 ((SPI_Type *)SPI1_BASE)
bogdanm 82:6473597d706e 11800 #define SPI1_BASE_PTR (SPI1)
bogdanm 82:6473597d706e 11801 /** Peripheral SPI2 base address */
bogdanm 82:6473597d706e 11802 #define SPI2_BASE (0x400AC000u)
bogdanm 82:6473597d706e 11803 /** Peripheral SPI2 base pointer */
bogdanm 82:6473597d706e 11804 #define SPI2 ((SPI_Type *)SPI2_BASE)
bogdanm 82:6473597d706e 11805 #define SPI2_BASE_PTR (SPI2)
bogdanm 82:6473597d706e 11806 /** Array initializer of SPI peripheral base pointers */
bogdanm 82:6473597d706e 11807 #define SPI_BASES { SPI0, SPI1, SPI2 }
bogdanm 82:6473597d706e 11808
bogdanm 82:6473597d706e 11809 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11810 -- SPI - Register accessor macros
bogdanm 82:6473597d706e 11811 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11812
bogdanm 82:6473597d706e 11813 /*!
bogdanm 82:6473597d706e 11814 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
bogdanm 82:6473597d706e 11815 * @{
bogdanm 82:6473597d706e 11816 */
bogdanm 82:6473597d706e 11817
bogdanm 82:6473597d706e 11818
bogdanm 82:6473597d706e 11819 /* SPI - Register instance definitions */
bogdanm 82:6473597d706e 11820 /* SPI0 */
bogdanm 82:6473597d706e 11821 #define SPI0_MCR SPI_MCR_REG(SPI0)
bogdanm 82:6473597d706e 11822 #define SPI0_TCR SPI_TCR_REG(SPI0)
bogdanm 82:6473597d706e 11823 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
bogdanm 82:6473597d706e 11824 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
bogdanm 82:6473597d706e 11825 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
bogdanm 82:6473597d706e 11826 #define SPI0_SR SPI_SR_REG(SPI0)
bogdanm 82:6473597d706e 11827 #define SPI0_RSER SPI_RSER_REG(SPI0)
bogdanm 82:6473597d706e 11828 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
bogdanm 82:6473597d706e 11829 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
bogdanm 82:6473597d706e 11830 #define SPI0_POPR SPI_POPR_REG(SPI0)
bogdanm 82:6473597d706e 11831 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
bogdanm 82:6473597d706e 11832 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
bogdanm 82:6473597d706e 11833 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
bogdanm 82:6473597d706e 11834 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
bogdanm 82:6473597d706e 11835 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
bogdanm 82:6473597d706e 11836 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
bogdanm 82:6473597d706e 11837 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
bogdanm 82:6473597d706e 11838 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
bogdanm 82:6473597d706e 11839 /* SPI1 */
bogdanm 82:6473597d706e 11840 #define SPI1_MCR SPI_MCR_REG(SPI1)
bogdanm 82:6473597d706e 11841 #define SPI1_TCR SPI_TCR_REG(SPI1)
bogdanm 82:6473597d706e 11842 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
bogdanm 82:6473597d706e 11843 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
bogdanm 82:6473597d706e 11844 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
bogdanm 82:6473597d706e 11845 #define SPI1_SR SPI_SR_REG(SPI1)
bogdanm 82:6473597d706e 11846 #define SPI1_RSER SPI_RSER_REG(SPI1)
bogdanm 82:6473597d706e 11847 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
bogdanm 82:6473597d706e 11848 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
bogdanm 82:6473597d706e 11849 #define SPI1_POPR SPI_POPR_REG(SPI1)
bogdanm 82:6473597d706e 11850 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
bogdanm 82:6473597d706e 11851 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
bogdanm 82:6473597d706e 11852 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
bogdanm 82:6473597d706e 11853 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
bogdanm 82:6473597d706e 11854 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
bogdanm 82:6473597d706e 11855 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
bogdanm 82:6473597d706e 11856 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
bogdanm 82:6473597d706e 11857 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
bogdanm 82:6473597d706e 11858 /* SPI2 */
bogdanm 82:6473597d706e 11859 #define SPI2_MCR SPI_MCR_REG(SPI2)
bogdanm 82:6473597d706e 11860 #define SPI2_TCR SPI_TCR_REG(SPI2)
bogdanm 82:6473597d706e 11861 #define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
bogdanm 82:6473597d706e 11862 #define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
bogdanm 82:6473597d706e 11863 #define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
bogdanm 82:6473597d706e 11864 #define SPI2_SR SPI_SR_REG(SPI2)
bogdanm 82:6473597d706e 11865 #define SPI2_RSER SPI_RSER_REG(SPI2)
bogdanm 82:6473597d706e 11866 #define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
bogdanm 82:6473597d706e 11867 #define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
bogdanm 82:6473597d706e 11868 #define SPI2_POPR SPI_POPR_REG(SPI2)
bogdanm 82:6473597d706e 11869 #define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
bogdanm 82:6473597d706e 11870 #define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
bogdanm 82:6473597d706e 11871 #define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
bogdanm 82:6473597d706e 11872 #define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
bogdanm 82:6473597d706e 11873 #define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
bogdanm 82:6473597d706e 11874 #define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
bogdanm 82:6473597d706e 11875 #define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
bogdanm 82:6473597d706e 11876 #define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
bogdanm 82:6473597d706e 11877
bogdanm 82:6473597d706e 11878 /* SPI - Register array accessors */
bogdanm 82:6473597d706e 11879 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
bogdanm 82:6473597d706e 11880 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
bogdanm 82:6473597d706e 11881 #define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
bogdanm 82:6473597d706e 11882 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
bogdanm 82:6473597d706e 11883 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
bogdanm 82:6473597d706e 11884 #define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
bogdanm 82:6473597d706e 11885
bogdanm 82:6473597d706e 11886 /*!
bogdanm 82:6473597d706e 11887 * @}
bogdanm 82:6473597d706e 11888 */ /* end of group SPI_Register_Accessor_Macros */
bogdanm 82:6473597d706e 11889
bogdanm 82:6473597d706e 11890
bogdanm 82:6473597d706e 11891 /*!
bogdanm 82:6473597d706e 11892 * @}
bogdanm 82:6473597d706e 11893 */ /* end of group SPI_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 11894
bogdanm 82:6473597d706e 11895
bogdanm 82:6473597d706e 11896 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11897 -- UART Peripheral Access Layer
bogdanm 82:6473597d706e 11898 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11899
bogdanm 82:6473597d706e 11900 /*!
bogdanm 82:6473597d706e 11901 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
bogdanm 82:6473597d706e 11902 * @{
bogdanm 82:6473597d706e 11903 */
bogdanm 82:6473597d706e 11904
bogdanm 82:6473597d706e 11905 /** UART - Register Layout Typedef */
bogdanm 82:6473597d706e 11906 typedef struct {
bogdanm 82:6473597d706e 11907 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
bogdanm 82:6473597d706e 11908 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
bogdanm 82:6473597d706e 11909 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 82:6473597d706e 11910 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 82:6473597d706e 11911 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 82:6473597d706e 11912 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 82:6473597d706e 11913 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 82:6473597d706e 11914 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 82:6473597d706e 11915 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
bogdanm 82:6473597d706e 11916 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
bogdanm 82:6473597d706e 11917 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
bogdanm 82:6473597d706e 11918 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
bogdanm 82:6473597d706e 11919 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
bogdanm 82:6473597d706e 11920 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
bogdanm 82:6473597d706e 11921 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
bogdanm 82:6473597d706e 11922 uint8_t RESERVED_0[1];
bogdanm 82:6473597d706e 11923 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
bogdanm 82:6473597d706e 11924 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
bogdanm 82:6473597d706e 11925 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
bogdanm 82:6473597d706e 11926 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
bogdanm 82:6473597d706e 11927 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
bogdanm 82:6473597d706e 11928 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
bogdanm 82:6473597d706e 11929 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
bogdanm 82:6473597d706e 11930 uint8_t RESERVED_1[1];
bogdanm 82:6473597d706e 11931 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
bogdanm 82:6473597d706e 11932 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
bogdanm 82:6473597d706e 11933 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
bogdanm 82:6473597d706e 11934 union { /* offset: 0x1B */
bogdanm 82:6473597d706e 11935 __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
bogdanm 82:6473597d706e 11936 __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
bogdanm 82:6473597d706e 11937 };
bogdanm 82:6473597d706e 11938 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
bogdanm 82:6473597d706e 11939 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
bogdanm 82:6473597d706e 11940 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
bogdanm 82:6473597d706e 11941 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
bogdanm 82:6473597d706e 11942 } UART_Type, *UART_MemMapPtr;
bogdanm 82:6473597d706e 11943
bogdanm 82:6473597d706e 11944 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11945 -- UART - Register accessor macros
bogdanm 82:6473597d706e 11946 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11947
bogdanm 82:6473597d706e 11948 /*!
bogdanm 82:6473597d706e 11949 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
bogdanm 82:6473597d706e 11950 * @{
bogdanm 82:6473597d706e 11951 */
bogdanm 82:6473597d706e 11952
bogdanm 82:6473597d706e 11953
bogdanm 82:6473597d706e 11954 /* UART - Register accessors */
bogdanm 82:6473597d706e 11955 #define UART_BDH_REG(base) ((base)->BDH)
bogdanm 82:6473597d706e 11956 #define UART_BDL_REG(base) ((base)->BDL)
bogdanm 82:6473597d706e 11957 #define UART_C1_REG(base) ((base)->C1)
bogdanm 82:6473597d706e 11958 #define UART_C2_REG(base) ((base)->C2)
bogdanm 82:6473597d706e 11959 #define UART_S1_REG(base) ((base)->S1)
bogdanm 82:6473597d706e 11960 #define UART_S2_REG(base) ((base)->S2)
bogdanm 82:6473597d706e 11961 #define UART_C3_REG(base) ((base)->C3)
bogdanm 82:6473597d706e 11962 #define UART_D_REG(base) ((base)->D)
bogdanm 82:6473597d706e 11963 #define UART_MA1_REG(base) ((base)->MA1)
bogdanm 82:6473597d706e 11964 #define UART_MA2_REG(base) ((base)->MA2)
bogdanm 82:6473597d706e 11965 #define UART_C4_REG(base) ((base)->C4)
bogdanm 82:6473597d706e 11966 #define UART_C5_REG(base) ((base)->C5)
bogdanm 82:6473597d706e 11967 #define UART_ED_REG(base) ((base)->ED)
bogdanm 82:6473597d706e 11968 #define UART_MODEM_REG(base) ((base)->MODEM)
bogdanm 82:6473597d706e 11969 #define UART_IR_REG(base) ((base)->IR)
bogdanm 82:6473597d706e 11970 #define UART_PFIFO_REG(base) ((base)->PFIFO)
bogdanm 82:6473597d706e 11971 #define UART_CFIFO_REG(base) ((base)->CFIFO)
bogdanm 82:6473597d706e 11972 #define UART_SFIFO_REG(base) ((base)->SFIFO)
bogdanm 82:6473597d706e 11973 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
bogdanm 82:6473597d706e 11974 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
bogdanm 82:6473597d706e 11975 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
bogdanm 82:6473597d706e 11976 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
bogdanm 82:6473597d706e 11977 #define UART_C7816_REG(base) ((base)->C7816)
bogdanm 82:6473597d706e 11978 #define UART_IE7816_REG(base) ((base)->IE7816)
bogdanm 82:6473597d706e 11979 #define UART_IS7816_REG(base) ((base)->IS7816)
bogdanm 82:6473597d706e 11980 #define UART_WP7816_T_TYPE0_REG(base) ((base)->WP7816_T_TYPE0)
bogdanm 82:6473597d706e 11981 #define UART_WP7816_T_TYPE1_REG(base) ((base)->WP7816_T_TYPE1)
bogdanm 82:6473597d706e 11982 #define UART_WN7816_REG(base) ((base)->WN7816)
bogdanm 82:6473597d706e 11983 #define UART_WF7816_REG(base) ((base)->WF7816)
bogdanm 82:6473597d706e 11984 #define UART_ET7816_REG(base) ((base)->ET7816)
bogdanm 82:6473597d706e 11985 #define UART_TL7816_REG(base) ((base)->TL7816)
bogdanm 82:6473597d706e 11986
bogdanm 82:6473597d706e 11987 /*!
bogdanm 82:6473597d706e 11988 * @}
bogdanm 82:6473597d706e 11989 */ /* end of group UART_Register_Accessor_Macros */
bogdanm 82:6473597d706e 11990
bogdanm 82:6473597d706e 11991
bogdanm 82:6473597d706e 11992 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 11993 -- UART Register Masks
bogdanm 82:6473597d706e 11994 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 11995
bogdanm 82:6473597d706e 11996 /*!
bogdanm 82:6473597d706e 11997 * @addtogroup UART_Register_Masks UART Register Masks
bogdanm 82:6473597d706e 11998 * @{
bogdanm 82:6473597d706e 11999 */
bogdanm 82:6473597d706e 12000
bogdanm 82:6473597d706e 12001 /* BDH Bit Fields */
bogdanm 82:6473597d706e 12002 #define UART_BDH_SBR_MASK 0x1Fu
bogdanm 82:6473597d706e 12003 #define UART_BDH_SBR_SHIFT 0
bogdanm 82:6473597d706e 12004 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
bogdanm 82:6473597d706e 12005 #define UART_BDH_SBNS_MASK 0x20u
bogdanm 82:6473597d706e 12006 #define UART_BDH_SBNS_SHIFT 5
bogdanm 82:6473597d706e 12007 #define UART_BDH_RXEDGIE_MASK 0x40u
bogdanm 82:6473597d706e 12008 #define UART_BDH_RXEDGIE_SHIFT 6
bogdanm 82:6473597d706e 12009 #define UART_BDH_LBKDIE_MASK 0x80u
bogdanm 82:6473597d706e 12010 #define UART_BDH_LBKDIE_SHIFT 7
bogdanm 82:6473597d706e 12011 /* BDL Bit Fields */
bogdanm 82:6473597d706e 12012 #define UART_BDL_SBR_MASK 0xFFu
bogdanm 82:6473597d706e 12013 #define UART_BDL_SBR_SHIFT 0
bogdanm 82:6473597d706e 12014 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
bogdanm 82:6473597d706e 12015 /* C1 Bit Fields */
bogdanm 82:6473597d706e 12016 #define UART_C1_PT_MASK 0x1u
bogdanm 82:6473597d706e 12017 #define UART_C1_PT_SHIFT 0
bogdanm 82:6473597d706e 12018 #define UART_C1_PE_MASK 0x2u
bogdanm 82:6473597d706e 12019 #define UART_C1_PE_SHIFT 1
bogdanm 82:6473597d706e 12020 #define UART_C1_ILT_MASK 0x4u
bogdanm 82:6473597d706e 12021 #define UART_C1_ILT_SHIFT 2
bogdanm 82:6473597d706e 12022 #define UART_C1_WAKE_MASK 0x8u
bogdanm 82:6473597d706e 12023 #define UART_C1_WAKE_SHIFT 3
bogdanm 82:6473597d706e 12024 #define UART_C1_M_MASK 0x10u
bogdanm 82:6473597d706e 12025 #define UART_C1_M_SHIFT 4
bogdanm 82:6473597d706e 12026 #define UART_C1_RSRC_MASK 0x20u
bogdanm 82:6473597d706e 12027 #define UART_C1_RSRC_SHIFT 5
bogdanm 82:6473597d706e 12028 #define UART_C1_UARTSWAI_MASK 0x40u
bogdanm 82:6473597d706e 12029 #define UART_C1_UARTSWAI_SHIFT 6
bogdanm 82:6473597d706e 12030 #define UART_C1_LOOPS_MASK 0x80u
bogdanm 82:6473597d706e 12031 #define UART_C1_LOOPS_SHIFT 7
bogdanm 82:6473597d706e 12032 /* C2 Bit Fields */
bogdanm 82:6473597d706e 12033 #define UART_C2_SBK_MASK 0x1u
bogdanm 82:6473597d706e 12034 #define UART_C2_SBK_SHIFT 0
bogdanm 82:6473597d706e 12035 #define UART_C2_RWU_MASK 0x2u
bogdanm 82:6473597d706e 12036 #define UART_C2_RWU_SHIFT 1
bogdanm 82:6473597d706e 12037 #define UART_C2_RE_MASK 0x4u
bogdanm 82:6473597d706e 12038 #define UART_C2_RE_SHIFT 2
bogdanm 82:6473597d706e 12039 #define UART_C2_TE_MASK 0x8u
bogdanm 82:6473597d706e 12040 #define UART_C2_TE_SHIFT 3
bogdanm 82:6473597d706e 12041 #define UART_C2_ILIE_MASK 0x10u
bogdanm 82:6473597d706e 12042 #define UART_C2_ILIE_SHIFT 4
bogdanm 82:6473597d706e 12043 #define UART_C2_RIE_MASK 0x20u
bogdanm 82:6473597d706e 12044 #define UART_C2_RIE_SHIFT 5
bogdanm 82:6473597d706e 12045 #define UART_C2_TCIE_MASK 0x40u
bogdanm 82:6473597d706e 12046 #define UART_C2_TCIE_SHIFT 6
bogdanm 82:6473597d706e 12047 #define UART_C2_TIE_MASK 0x80u
bogdanm 82:6473597d706e 12048 #define UART_C2_TIE_SHIFT 7
bogdanm 82:6473597d706e 12049 /* S1 Bit Fields */
bogdanm 82:6473597d706e 12050 #define UART_S1_PF_MASK 0x1u
bogdanm 82:6473597d706e 12051 #define UART_S1_PF_SHIFT 0
bogdanm 82:6473597d706e 12052 #define UART_S1_FE_MASK 0x2u
bogdanm 82:6473597d706e 12053 #define UART_S1_FE_SHIFT 1
bogdanm 82:6473597d706e 12054 #define UART_S1_NF_MASK 0x4u
bogdanm 82:6473597d706e 12055 #define UART_S1_NF_SHIFT 2
bogdanm 82:6473597d706e 12056 #define UART_S1_OR_MASK 0x8u
bogdanm 82:6473597d706e 12057 #define UART_S1_OR_SHIFT 3
bogdanm 82:6473597d706e 12058 #define UART_S1_IDLE_MASK 0x10u
bogdanm 82:6473597d706e 12059 #define UART_S1_IDLE_SHIFT 4
bogdanm 82:6473597d706e 12060 #define UART_S1_RDRF_MASK 0x20u
bogdanm 82:6473597d706e 12061 #define UART_S1_RDRF_SHIFT 5
bogdanm 82:6473597d706e 12062 #define UART_S1_TC_MASK 0x40u
bogdanm 82:6473597d706e 12063 #define UART_S1_TC_SHIFT 6
bogdanm 82:6473597d706e 12064 #define UART_S1_TDRE_MASK 0x80u
bogdanm 82:6473597d706e 12065 #define UART_S1_TDRE_SHIFT 7
bogdanm 82:6473597d706e 12066 /* S2 Bit Fields */
bogdanm 82:6473597d706e 12067 #define UART_S2_RAF_MASK 0x1u
bogdanm 82:6473597d706e 12068 #define UART_S2_RAF_SHIFT 0
bogdanm 82:6473597d706e 12069 #define UART_S2_LBKDE_MASK 0x2u
bogdanm 82:6473597d706e 12070 #define UART_S2_LBKDE_SHIFT 1
bogdanm 82:6473597d706e 12071 #define UART_S2_BRK13_MASK 0x4u
bogdanm 82:6473597d706e 12072 #define UART_S2_BRK13_SHIFT 2
bogdanm 82:6473597d706e 12073 #define UART_S2_RWUID_MASK 0x8u
bogdanm 82:6473597d706e 12074 #define UART_S2_RWUID_SHIFT 3
bogdanm 82:6473597d706e 12075 #define UART_S2_RXINV_MASK 0x10u
bogdanm 82:6473597d706e 12076 #define UART_S2_RXINV_SHIFT 4
bogdanm 82:6473597d706e 12077 #define UART_S2_MSBF_MASK 0x20u
bogdanm 82:6473597d706e 12078 #define UART_S2_MSBF_SHIFT 5
bogdanm 82:6473597d706e 12079 #define UART_S2_RXEDGIF_MASK 0x40u
bogdanm 82:6473597d706e 12080 #define UART_S2_RXEDGIF_SHIFT 6
bogdanm 82:6473597d706e 12081 #define UART_S2_LBKDIF_MASK 0x80u
bogdanm 82:6473597d706e 12082 #define UART_S2_LBKDIF_SHIFT 7
bogdanm 82:6473597d706e 12083 /* C3 Bit Fields */
bogdanm 82:6473597d706e 12084 #define UART_C3_PEIE_MASK 0x1u
bogdanm 82:6473597d706e 12085 #define UART_C3_PEIE_SHIFT 0
bogdanm 82:6473597d706e 12086 #define UART_C3_FEIE_MASK 0x2u
bogdanm 82:6473597d706e 12087 #define UART_C3_FEIE_SHIFT 1
bogdanm 82:6473597d706e 12088 #define UART_C3_NEIE_MASK 0x4u
bogdanm 82:6473597d706e 12089 #define UART_C3_NEIE_SHIFT 2
bogdanm 82:6473597d706e 12090 #define UART_C3_ORIE_MASK 0x8u
bogdanm 82:6473597d706e 12091 #define UART_C3_ORIE_SHIFT 3
bogdanm 82:6473597d706e 12092 #define UART_C3_TXINV_MASK 0x10u
bogdanm 82:6473597d706e 12093 #define UART_C3_TXINV_SHIFT 4
bogdanm 82:6473597d706e 12094 #define UART_C3_TXDIR_MASK 0x20u
bogdanm 82:6473597d706e 12095 #define UART_C3_TXDIR_SHIFT 5
bogdanm 82:6473597d706e 12096 #define UART_C3_T8_MASK 0x40u
bogdanm 82:6473597d706e 12097 #define UART_C3_T8_SHIFT 6
bogdanm 82:6473597d706e 12098 #define UART_C3_R8_MASK 0x80u
bogdanm 82:6473597d706e 12099 #define UART_C3_R8_SHIFT 7
bogdanm 82:6473597d706e 12100 /* D Bit Fields */
bogdanm 82:6473597d706e 12101 #define UART_D_RT_MASK 0xFFu
bogdanm 82:6473597d706e 12102 #define UART_D_RT_SHIFT 0
bogdanm 82:6473597d706e 12103 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
bogdanm 82:6473597d706e 12104 /* MA1 Bit Fields */
bogdanm 82:6473597d706e 12105 #define UART_MA1_MA_MASK 0xFFu
bogdanm 82:6473597d706e 12106 #define UART_MA1_MA_SHIFT 0
bogdanm 82:6473597d706e 12107 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
bogdanm 82:6473597d706e 12108 /* MA2 Bit Fields */
bogdanm 82:6473597d706e 12109 #define UART_MA2_MA_MASK 0xFFu
bogdanm 82:6473597d706e 12110 #define UART_MA2_MA_SHIFT 0
bogdanm 82:6473597d706e 12111 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
bogdanm 82:6473597d706e 12112 /* C4 Bit Fields */
bogdanm 82:6473597d706e 12113 #define UART_C4_BRFA_MASK 0x1Fu
bogdanm 82:6473597d706e 12114 #define UART_C4_BRFA_SHIFT 0
bogdanm 82:6473597d706e 12115 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
bogdanm 82:6473597d706e 12116 #define UART_C4_M10_MASK 0x20u
bogdanm 82:6473597d706e 12117 #define UART_C4_M10_SHIFT 5
bogdanm 82:6473597d706e 12118 #define UART_C4_MAEN2_MASK 0x40u
bogdanm 82:6473597d706e 12119 #define UART_C4_MAEN2_SHIFT 6
bogdanm 82:6473597d706e 12120 #define UART_C4_MAEN1_MASK 0x80u
bogdanm 82:6473597d706e 12121 #define UART_C4_MAEN1_SHIFT 7
bogdanm 82:6473597d706e 12122 /* C5 Bit Fields */
bogdanm 82:6473597d706e 12123 #define UART_C5_LBKDDMAS_MASK 0x8u
bogdanm 82:6473597d706e 12124 #define UART_C5_LBKDDMAS_SHIFT 3
bogdanm 82:6473597d706e 12125 #define UART_C5_ILDMAS_MASK 0x10u
bogdanm 82:6473597d706e 12126 #define UART_C5_ILDMAS_SHIFT 4
bogdanm 82:6473597d706e 12127 #define UART_C5_RDMAS_MASK 0x20u
bogdanm 82:6473597d706e 12128 #define UART_C5_RDMAS_SHIFT 5
bogdanm 82:6473597d706e 12129 #define UART_C5_TCDMAS_MASK 0x40u
bogdanm 82:6473597d706e 12130 #define UART_C5_TCDMAS_SHIFT 6
bogdanm 82:6473597d706e 12131 #define UART_C5_TDMAS_MASK 0x80u
bogdanm 82:6473597d706e 12132 #define UART_C5_TDMAS_SHIFT 7
bogdanm 82:6473597d706e 12133 /* ED Bit Fields */
bogdanm 82:6473597d706e 12134 #define UART_ED_PARITYE_MASK 0x40u
bogdanm 82:6473597d706e 12135 #define UART_ED_PARITYE_SHIFT 6
bogdanm 82:6473597d706e 12136 #define UART_ED_NOISY_MASK 0x80u
bogdanm 82:6473597d706e 12137 #define UART_ED_NOISY_SHIFT 7
bogdanm 82:6473597d706e 12138 /* MODEM Bit Fields */
bogdanm 82:6473597d706e 12139 #define UART_MODEM_TXCTSE_MASK 0x1u
bogdanm 82:6473597d706e 12140 #define UART_MODEM_TXCTSE_SHIFT 0
bogdanm 82:6473597d706e 12141 #define UART_MODEM_TXRTSE_MASK 0x2u
bogdanm 82:6473597d706e 12142 #define UART_MODEM_TXRTSE_SHIFT 1
bogdanm 82:6473597d706e 12143 #define UART_MODEM_TXRTSPOL_MASK 0x4u
bogdanm 82:6473597d706e 12144 #define UART_MODEM_TXRTSPOL_SHIFT 2
bogdanm 82:6473597d706e 12145 #define UART_MODEM_RXRTSE_MASK 0x8u
bogdanm 82:6473597d706e 12146 #define UART_MODEM_RXRTSE_SHIFT 3
bogdanm 82:6473597d706e 12147 /* IR Bit Fields */
bogdanm 82:6473597d706e 12148 #define UART_IR_TNP_MASK 0x3u
bogdanm 82:6473597d706e 12149 #define UART_IR_TNP_SHIFT 0
bogdanm 82:6473597d706e 12150 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
bogdanm 82:6473597d706e 12151 #define UART_IR_IREN_MASK 0x4u
bogdanm 82:6473597d706e 12152 #define UART_IR_IREN_SHIFT 2
bogdanm 82:6473597d706e 12153 /* PFIFO Bit Fields */
bogdanm 82:6473597d706e 12154 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
bogdanm 82:6473597d706e 12155 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
bogdanm 82:6473597d706e 12156 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
bogdanm 82:6473597d706e 12157 #define UART_PFIFO_RXFE_MASK 0x8u
bogdanm 82:6473597d706e 12158 #define UART_PFIFO_RXFE_SHIFT 3
bogdanm 82:6473597d706e 12159 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
bogdanm 82:6473597d706e 12160 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
bogdanm 82:6473597d706e 12161 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
bogdanm 82:6473597d706e 12162 #define UART_PFIFO_TXFE_MASK 0x80u
bogdanm 82:6473597d706e 12163 #define UART_PFIFO_TXFE_SHIFT 7
bogdanm 82:6473597d706e 12164 /* CFIFO Bit Fields */
bogdanm 82:6473597d706e 12165 #define UART_CFIFO_RXUFE_MASK 0x1u
bogdanm 82:6473597d706e 12166 #define UART_CFIFO_RXUFE_SHIFT 0
bogdanm 82:6473597d706e 12167 #define UART_CFIFO_TXOFE_MASK 0x2u
bogdanm 82:6473597d706e 12168 #define UART_CFIFO_TXOFE_SHIFT 1
bogdanm 82:6473597d706e 12169 #define UART_CFIFO_RXOFE_MASK 0x4u
bogdanm 82:6473597d706e 12170 #define UART_CFIFO_RXOFE_SHIFT 2
bogdanm 82:6473597d706e 12171 #define UART_CFIFO_RXFLUSH_MASK 0x40u
bogdanm 82:6473597d706e 12172 #define UART_CFIFO_RXFLUSH_SHIFT 6
bogdanm 82:6473597d706e 12173 #define UART_CFIFO_TXFLUSH_MASK 0x80u
bogdanm 82:6473597d706e 12174 #define UART_CFIFO_TXFLUSH_SHIFT 7
bogdanm 82:6473597d706e 12175 /* SFIFO Bit Fields */
bogdanm 82:6473597d706e 12176 #define UART_SFIFO_RXUF_MASK 0x1u
bogdanm 82:6473597d706e 12177 #define UART_SFIFO_RXUF_SHIFT 0
bogdanm 82:6473597d706e 12178 #define UART_SFIFO_TXOF_MASK 0x2u
bogdanm 82:6473597d706e 12179 #define UART_SFIFO_TXOF_SHIFT 1
bogdanm 82:6473597d706e 12180 #define UART_SFIFO_RXOF_MASK 0x4u
bogdanm 82:6473597d706e 12181 #define UART_SFIFO_RXOF_SHIFT 2
bogdanm 82:6473597d706e 12182 #define UART_SFIFO_RXEMPT_MASK 0x40u
bogdanm 82:6473597d706e 12183 #define UART_SFIFO_RXEMPT_SHIFT 6
bogdanm 82:6473597d706e 12184 #define UART_SFIFO_TXEMPT_MASK 0x80u
bogdanm 82:6473597d706e 12185 #define UART_SFIFO_TXEMPT_SHIFT 7
bogdanm 82:6473597d706e 12186 /* TWFIFO Bit Fields */
bogdanm 82:6473597d706e 12187 #define UART_TWFIFO_TXWATER_MASK 0xFFu
bogdanm 82:6473597d706e 12188 #define UART_TWFIFO_TXWATER_SHIFT 0
bogdanm 82:6473597d706e 12189 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
bogdanm 82:6473597d706e 12190 /* TCFIFO Bit Fields */
bogdanm 82:6473597d706e 12191 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
bogdanm 82:6473597d706e 12192 #define UART_TCFIFO_TXCOUNT_SHIFT 0
bogdanm 82:6473597d706e 12193 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
bogdanm 82:6473597d706e 12194 /* RWFIFO Bit Fields */
bogdanm 82:6473597d706e 12195 #define UART_RWFIFO_RXWATER_MASK 0xFFu
bogdanm 82:6473597d706e 12196 #define UART_RWFIFO_RXWATER_SHIFT 0
bogdanm 82:6473597d706e 12197 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
bogdanm 82:6473597d706e 12198 /* RCFIFO Bit Fields */
bogdanm 82:6473597d706e 12199 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
bogdanm 82:6473597d706e 12200 #define UART_RCFIFO_RXCOUNT_SHIFT 0
bogdanm 82:6473597d706e 12201 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
bogdanm 82:6473597d706e 12202 /* C7816 Bit Fields */
bogdanm 82:6473597d706e 12203 #define UART_C7816_ISO_7816E_MASK 0x1u
bogdanm 82:6473597d706e 12204 #define UART_C7816_ISO_7816E_SHIFT 0
bogdanm 82:6473597d706e 12205 #define UART_C7816_TTYPE_MASK 0x2u
bogdanm 82:6473597d706e 12206 #define UART_C7816_TTYPE_SHIFT 1
bogdanm 82:6473597d706e 12207 #define UART_C7816_INIT_MASK 0x4u
bogdanm 82:6473597d706e 12208 #define UART_C7816_INIT_SHIFT 2
bogdanm 82:6473597d706e 12209 #define UART_C7816_ANACK_MASK 0x8u
bogdanm 82:6473597d706e 12210 #define UART_C7816_ANACK_SHIFT 3
bogdanm 82:6473597d706e 12211 #define UART_C7816_ONACK_MASK 0x10u
bogdanm 82:6473597d706e 12212 #define UART_C7816_ONACK_SHIFT 4
bogdanm 82:6473597d706e 12213 /* IE7816 Bit Fields */
bogdanm 82:6473597d706e 12214 #define UART_IE7816_RXTE_MASK 0x1u
bogdanm 82:6473597d706e 12215 #define UART_IE7816_RXTE_SHIFT 0
bogdanm 82:6473597d706e 12216 #define UART_IE7816_TXTE_MASK 0x2u
bogdanm 82:6473597d706e 12217 #define UART_IE7816_TXTE_SHIFT 1
bogdanm 82:6473597d706e 12218 #define UART_IE7816_GTVE_MASK 0x4u
bogdanm 82:6473597d706e 12219 #define UART_IE7816_GTVE_SHIFT 2
bogdanm 82:6473597d706e 12220 #define UART_IE7816_INITDE_MASK 0x10u
bogdanm 82:6473597d706e 12221 #define UART_IE7816_INITDE_SHIFT 4
bogdanm 82:6473597d706e 12222 #define UART_IE7816_BWTE_MASK 0x20u
bogdanm 82:6473597d706e 12223 #define UART_IE7816_BWTE_SHIFT 5
bogdanm 82:6473597d706e 12224 #define UART_IE7816_CWTE_MASK 0x40u
bogdanm 82:6473597d706e 12225 #define UART_IE7816_CWTE_SHIFT 6
bogdanm 82:6473597d706e 12226 #define UART_IE7816_WTE_MASK 0x80u
bogdanm 82:6473597d706e 12227 #define UART_IE7816_WTE_SHIFT 7
bogdanm 82:6473597d706e 12228 /* IS7816 Bit Fields */
bogdanm 82:6473597d706e 12229 #define UART_IS7816_RXT_MASK 0x1u
bogdanm 82:6473597d706e 12230 #define UART_IS7816_RXT_SHIFT 0
bogdanm 82:6473597d706e 12231 #define UART_IS7816_TXT_MASK 0x2u
bogdanm 82:6473597d706e 12232 #define UART_IS7816_TXT_SHIFT 1
bogdanm 82:6473597d706e 12233 #define UART_IS7816_GTV_MASK 0x4u
bogdanm 82:6473597d706e 12234 #define UART_IS7816_GTV_SHIFT 2
bogdanm 82:6473597d706e 12235 #define UART_IS7816_INITD_MASK 0x10u
bogdanm 82:6473597d706e 12236 #define UART_IS7816_INITD_SHIFT 4
bogdanm 82:6473597d706e 12237 #define UART_IS7816_BWT_MASK 0x20u
bogdanm 82:6473597d706e 12238 #define UART_IS7816_BWT_SHIFT 5
bogdanm 82:6473597d706e 12239 #define UART_IS7816_CWT_MASK 0x40u
bogdanm 82:6473597d706e 12240 #define UART_IS7816_CWT_SHIFT 6
bogdanm 82:6473597d706e 12241 #define UART_IS7816_WT_MASK 0x80u
bogdanm 82:6473597d706e 12242 #define UART_IS7816_WT_SHIFT 7
bogdanm 82:6473597d706e 12243 /* WP7816_T_TYPE0 Bit Fields */
bogdanm 82:6473597d706e 12244 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
bogdanm 82:6473597d706e 12245 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
bogdanm 82:6473597d706e 12246 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
bogdanm 82:6473597d706e 12247 /* WP7816_T_TYPE1 Bit Fields */
bogdanm 82:6473597d706e 12248 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
bogdanm 82:6473597d706e 12249 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
bogdanm 82:6473597d706e 12250 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
bogdanm 82:6473597d706e 12251 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
bogdanm 82:6473597d706e 12252 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
bogdanm 82:6473597d706e 12253 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
bogdanm 82:6473597d706e 12254 /* WN7816 Bit Fields */
bogdanm 82:6473597d706e 12255 #define UART_WN7816_GTN_MASK 0xFFu
bogdanm 82:6473597d706e 12256 #define UART_WN7816_GTN_SHIFT 0
bogdanm 82:6473597d706e 12257 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
bogdanm 82:6473597d706e 12258 /* WF7816 Bit Fields */
bogdanm 82:6473597d706e 12259 #define UART_WF7816_GTFD_MASK 0xFFu
bogdanm 82:6473597d706e 12260 #define UART_WF7816_GTFD_SHIFT 0
bogdanm 82:6473597d706e 12261 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
bogdanm 82:6473597d706e 12262 /* ET7816 Bit Fields */
bogdanm 82:6473597d706e 12263 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
bogdanm 82:6473597d706e 12264 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
bogdanm 82:6473597d706e 12265 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
bogdanm 82:6473597d706e 12266 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
bogdanm 82:6473597d706e 12267 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
bogdanm 82:6473597d706e 12268 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
bogdanm 82:6473597d706e 12269 /* TL7816 Bit Fields */
bogdanm 82:6473597d706e 12270 #define UART_TL7816_TLEN_MASK 0xFFu
bogdanm 82:6473597d706e 12271 #define UART_TL7816_TLEN_SHIFT 0
bogdanm 82:6473597d706e 12272 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
bogdanm 82:6473597d706e 12273
bogdanm 82:6473597d706e 12274 /*!
bogdanm 82:6473597d706e 12275 * @}
bogdanm 82:6473597d706e 12276 */ /* end of group UART_Register_Masks */
bogdanm 82:6473597d706e 12277
bogdanm 82:6473597d706e 12278
bogdanm 82:6473597d706e 12279 /* UART - Peripheral instance base addresses */
bogdanm 82:6473597d706e 12280 /** Peripheral UART0 base address */
bogdanm 82:6473597d706e 12281 #define UART0_BASE (0x4006A000u)
bogdanm 82:6473597d706e 12282 /** Peripheral UART0 base pointer */
bogdanm 82:6473597d706e 12283 #define UART0 ((UART_Type *)UART0_BASE)
bogdanm 82:6473597d706e 12284 #define UART0_BASE_PTR (UART0)
bogdanm 82:6473597d706e 12285 /** Peripheral UART1 base address */
bogdanm 82:6473597d706e 12286 #define UART1_BASE (0x4006B000u)
bogdanm 82:6473597d706e 12287 /** Peripheral UART1 base pointer */
bogdanm 82:6473597d706e 12288 #define UART1 ((UART_Type *)UART1_BASE)
bogdanm 82:6473597d706e 12289 #define UART1_BASE_PTR (UART1)
bogdanm 82:6473597d706e 12290 /** Peripheral UART2 base address */
bogdanm 82:6473597d706e 12291 #define UART2_BASE (0x4006C000u)
bogdanm 82:6473597d706e 12292 /** Peripheral UART2 base pointer */
bogdanm 82:6473597d706e 12293 #define UART2 ((UART_Type *)UART2_BASE)
bogdanm 82:6473597d706e 12294 #define UART2_BASE_PTR (UART2)
bogdanm 82:6473597d706e 12295 /** Peripheral UART3 base address */
bogdanm 82:6473597d706e 12296 #define UART3_BASE (0x4006D000u)
bogdanm 82:6473597d706e 12297 /** Peripheral UART3 base pointer */
bogdanm 82:6473597d706e 12298 #define UART3 ((UART_Type *)UART3_BASE)
bogdanm 82:6473597d706e 12299 #define UART3_BASE_PTR (UART3)
bogdanm 82:6473597d706e 12300 /** Peripheral UART4 base address */
bogdanm 82:6473597d706e 12301 #define UART4_BASE (0x400EA000u)
bogdanm 82:6473597d706e 12302 /** Peripheral UART4 base pointer */
bogdanm 82:6473597d706e 12303 #define UART4 ((UART_Type *)UART4_BASE)
bogdanm 82:6473597d706e 12304 #define UART4_BASE_PTR (UART4)
bogdanm 82:6473597d706e 12305 /** Peripheral UART5 base address */
bogdanm 82:6473597d706e 12306 #define UART5_BASE (0x400EB000u)
bogdanm 82:6473597d706e 12307 /** Peripheral UART5 base pointer */
bogdanm 82:6473597d706e 12308 #define UART5 ((UART_Type *)UART5_BASE)
bogdanm 82:6473597d706e 12309 #define UART5_BASE_PTR (UART5)
bogdanm 82:6473597d706e 12310 /** Array initializer of UART peripheral base pointers */
bogdanm 82:6473597d706e 12311 #define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
bogdanm 82:6473597d706e 12312
bogdanm 82:6473597d706e 12313 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 12314 -- UART - Register accessor macros
bogdanm 82:6473597d706e 12315 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 12316
bogdanm 82:6473597d706e 12317 /*!
bogdanm 82:6473597d706e 12318 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
bogdanm 82:6473597d706e 12319 * @{
bogdanm 82:6473597d706e 12320 */
bogdanm 82:6473597d706e 12321
bogdanm 82:6473597d706e 12322
bogdanm 82:6473597d706e 12323 /* UART - Register instance definitions */
bogdanm 82:6473597d706e 12324 /* UART0 */
bogdanm 82:6473597d706e 12325 #define UART0_BDH UART_BDH_REG(UART0)
bogdanm 82:6473597d706e 12326 #define UART0_BDL UART_BDL_REG(UART0)
bogdanm 82:6473597d706e 12327 #define UART0_C1 UART_C1_REG(UART0)
bogdanm 82:6473597d706e 12328 #define UART0_C2 UART_C2_REG(UART0)
bogdanm 82:6473597d706e 12329 #define UART0_S1 UART_S1_REG(UART0)
bogdanm 82:6473597d706e 12330 #define UART0_S2 UART_S2_REG(UART0)
bogdanm 82:6473597d706e 12331 #define UART0_C3 UART_C3_REG(UART0)
bogdanm 82:6473597d706e 12332 #define UART0_D UART_D_REG(UART0)
bogdanm 82:6473597d706e 12333 #define UART0_MA1 UART_MA1_REG(UART0)
bogdanm 82:6473597d706e 12334 #define UART0_MA2 UART_MA2_REG(UART0)
bogdanm 82:6473597d706e 12335 #define UART0_C4 UART_C4_REG(UART0)
bogdanm 82:6473597d706e 12336 #define UART0_C5 UART_C5_REG(UART0)
bogdanm 82:6473597d706e 12337 #define UART0_ED UART_ED_REG(UART0)
bogdanm 82:6473597d706e 12338 #define UART0_MODEM UART_MODEM_REG(UART0)
bogdanm 82:6473597d706e 12339 #define UART0_IR UART_IR_REG(UART0)
bogdanm 82:6473597d706e 12340 #define UART0_PFIFO UART_PFIFO_REG(UART0)
bogdanm 82:6473597d706e 12341 #define UART0_CFIFO UART_CFIFO_REG(UART0)
bogdanm 82:6473597d706e 12342 #define UART0_SFIFO UART_SFIFO_REG(UART0)
bogdanm 82:6473597d706e 12343 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
bogdanm 82:6473597d706e 12344 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
bogdanm 82:6473597d706e 12345 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
bogdanm 82:6473597d706e 12346 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
bogdanm 82:6473597d706e 12347 #define UART0_C7816 UART_C7816_REG(UART0)
bogdanm 82:6473597d706e 12348 #define UART0_IE7816 UART_IE7816_REG(UART0)
bogdanm 82:6473597d706e 12349 #define UART0_IS7816 UART_IS7816_REG(UART0)
bogdanm 82:6473597d706e 12350 #define UART0_WP7816T0 UART_WP7816_T_TYPE0_REG(UART0)
bogdanm 82:6473597d706e 12351 #define UART0_WP7816T1 UART_WP7816_T_TYPE1_REG(UART0)
bogdanm 82:6473597d706e 12352 #define UART0_WN7816 UART_WN7816_REG(UART0)
bogdanm 82:6473597d706e 12353 #define UART0_WF7816 UART_WF7816_REG(UART0)
bogdanm 82:6473597d706e 12354 #define UART0_ET7816 UART_ET7816_REG(UART0)
bogdanm 82:6473597d706e 12355 #define UART0_TL7816 UART_TL7816_REG(UART0)
bogdanm 82:6473597d706e 12356 /* UART1 */
bogdanm 82:6473597d706e 12357 #define UART1_BDH UART_BDH_REG(UART1)
bogdanm 82:6473597d706e 12358 #define UART1_BDL UART_BDL_REG(UART1)
bogdanm 82:6473597d706e 12359 #define UART1_C1 UART_C1_REG(UART1)
bogdanm 82:6473597d706e 12360 #define UART1_C2 UART_C2_REG(UART1)
bogdanm 82:6473597d706e 12361 #define UART1_S1 UART_S1_REG(UART1)
bogdanm 82:6473597d706e 12362 #define UART1_S2 UART_S2_REG(UART1)
bogdanm 82:6473597d706e 12363 #define UART1_C3 UART_C3_REG(UART1)
bogdanm 82:6473597d706e 12364 #define UART1_D UART_D_REG(UART1)
bogdanm 82:6473597d706e 12365 #define UART1_MA1 UART_MA1_REG(UART1)
bogdanm 82:6473597d706e 12366 #define UART1_MA2 UART_MA2_REG(UART1)
bogdanm 82:6473597d706e 12367 #define UART1_C4 UART_C4_REG(UART1)
bogdanm 82:6473597d706e 12368 #define UART1_C5 UART_C5_REG(UART1)
bogdanm 82:6473597d706e 12369 #define UART1_ED UART_ED_REG(UART1)
bogdanm 82:6473597d706e 12370 #define UART1_MODEM UART_MODEM_REG(UART1)
bogdanm 82:6473597d706e 12371 #define UART1_IR UART_IR_REG(UART1)
bogdanm 82:6473597d706e 12372 #define UART1_PFIFO UART_PFIFO_REG(UART1)
bogdanm 82:6473597d706e 12373 #define UART1_CFIFO UART_CFIFO_REG(UART1)
bogdanm 82:6473597d706e 12374 #define UART1_SFIFO UART_SFIFO_REG(UART1)
bogdanm 82:6473597d706e 12375 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
bogdanm 82:6473597d706e 12376 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
bogdanm 82:6473597d706e 12377 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
bogdanm 82:6473597d706e 12378 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
bogdanm 82:6473597d706e 12379 /* UART2 */
bogdanm 82:6473597d706e 12380 #define UART2_BDH UART_BDH_REG(UART2)
bogdanm 82:6473597d706e 12381 #define UART2_BDL UART_BDL_REG(UART2)
bogdanm 82:6473597d706e 12382 #define UART2_C1 UART_C1_REG(UART2)
bogdanm 82:6473597d706e 12383 #define UART2_C2 UART_C2_REG(UART2)
bogdanm 82:6473597d706e 12384 #define UART2_S1 UART_S1_REG(UART2)
bogdanm 82:6473597d706e 12385 #define UART2_S2 UART_S2_REG(UART2)
bogdanm 82:6473597d706e 12386 #define UART2_C3 UART_C3_REG(UART2)
bogdanm 82:6473597d706e 12387 #define UART2_D UART_D_REG(UART2)
bogdanm 82:6473597d706e 12388 #define UART2_MA1 UART_MA1_REG(UART2)
bogdanm 82:6473597d706e 12389 #define UART2_MA2 UART_MA2_REG(UART2)
bogdanm 82:6473597d706e 12390 #define UART2_C4 UART_C4_REG(UART2)
bogdanm 82:6473597d706e 12391 #define UART2_C5 UART_C5_REG(UART2)
bogdanm 82:6473597d706e 12392 #define UART2_ED UART_ED_REG(UART2)
bogdanm 82:6473597d706e 12393 #define UART2_MODEM UART_MODEM_REG(UART2)
bogdanm 82:6473597d706e 12394 #define UART2_IR UART_IR_REG(UART2)
bogdanm 82:6473597d706e 12395 #define UART2_PFIFO UART_PFIFO_REG(UART2)
bogdanm 82:6473597d706e 12396 #define UART2_CFIFO UART_CFIFO_REG(UART2)
bogdanm 82:6473597d706e 12397 #define UART2_SFIFO UART_SFIFO_REG(UART2)
bogdanm 82:6473597d706e 12398 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
bogdanm 82:6473597d706e 12399 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
bogdanm 82:6473597d706e 12400 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
bogdanm 82:6473597d706e 12401 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
bogdanm 82:6473597d706e 12402 /* UART3 */
bogdanm 82:6473597d706e 12403 #define UART3_BDH UART_BDH_REG(UART3)
bogdanm 82:6473597d706e 12404 #define UART3_BDL UART_BDL_REG(UART3)
bogdanm 82:6473597d706e 12405 #define UART3_C1 UART_C1_REG(UART3)
bogdanm 82:6473597d706e 12406 #define UART3_C2 UART_C2_REG(UART3)
bogdanm 82:6473597d706e 12407 #define UART3_S1 UART_S1_REG(UART3)
bogdanm 82:6473597d706e 12408 #define UART3_S2 UART_S2_REG(UART3)
bogdanm 82:6473597d706e 12409 #define UART3_C3 UART_C3_REG(UART3)
bogdanm 82:6473597d706e 12410 #define UART3_D UART_D_REG(UART3)
bogdanm 82:6473597d706e 12411 #define UART3_MA1 UART_MA1_REG(UART3)
bogdanm 82:6473597d706e 12412 #define UART3_MA2 UART_MA2_REG(UART3)
bogdanm 82:6473597d706e 12413 #define UART3_C4 UART_C4_REG(UART3)
bogdanm 82:6473597d706e 12414 #define UART3_C5 UART_C5_REG(UART3)
bogdanm 82:6473597d706e 12415 #define UART3_ED UART_ED_REG(UART3)
bogdanm 82:6473597d706e 12416 #define UART3_MODEM UART_MODEM_REG(UART3)
bogdanm 82:6473597d706e 12417 #define UART3_IR UART_IR_REG(UART3)
bogdanm 82:6473597d706e 12418 #define UART3_PFIFO UART_PFIFO_REG(UART3)
bogdanm 82:6473597d706e 12419 #define UART3_CFIFO UART_CFIFO_REG(UART3)
bogdanm 82:6473597d706e 12420 #define UART3_SFIFO UART_SFIFO_REG(UART3)
bogdanm 82:6473597d706e 12421 #define UART3_TWFIFO UART_TWFIFO_REG(UART3)
bogdanm 82:6473597d706e 12422 #define UART3_TCFIFO UART_TCFIFO_REG(UART3)
bogdanm 82:6473597d706e 12423 #define UART3_RWFIFO UART_RWFIFO_REG(UART3)
bogdanm 82:6473597d706e 12424 #define UART3_RCFIFO UART_RCFIFO_REG(UART3)
bogdanm 82:6473597d706e 12425 /* UART4 */
bogdanm 82:6473597d706e 12426 #define UART4_BDH UART_BDH_REG(UART4)
bogdanm 82:6473597d706e 12427 #define UART4_BDL UART_BDL_REG(UART4)
bogdanm 82:6473597d706e 12428 #define UART4_C1 UART_C1_REG(UART4)
bogdanm 82:6473597d706e 12429 #define UART4_C2 UART_C2_REG(UART4)
bogdanm 82:6473597d706e 12430 #define UART4_S1 UART_S1_REG(UART4)
bogdanm 82:6473597d706e 12431 #define UART4_S2 UART_S2_REG(UART4)
bogdanm 82:6473597d706e 12432 #define UART4_C3 UART_C3_REG(UART4)
bogdanm 82:6473597d706e 12433 #define UART4_D UART_D_REG(UART4)
bogdanm 82:6473597d706e 12434 #define UART4_MA1 UART_MA1_REG(UART4)
bogdanm 82:6473597d706e 12435 #define UART4_MA2 UART_MA2_REG(UART4)
bogdanm 82:6473597d706e 12436 #define UART4_C4 UART_C4_REG(UART4)
bogdanm 82:6473597d706e 12437 #define UART4_C5 UART_C5_REG(UART4)
bogdanm 82:6473597d706e 12438 #define UART4_ED UART_ED_REG(UART4)
bogdanm 82:6473597d706e 12439 #define UART4_MODEM UART_MODEM_REG(UART4)
bogdanm 82:6473597d706e 12440 #define UART4_IR UART_IR_REG(UART4)
bogdanm 82:6473597d706e 12441 #define UART4_PFIFO UART_PFIFO_REG(UART4)
bogdanm 82:6473597d706e 12442 #define UART4_CFIFO UART_CFIFO_REG(UART4)
bogdanm 82:6473597d706e 12443 #define UART4_SFIFO UART_SFIFO_REG(UART4)
bogdanm 82:6473597d706e 12444 #define UART4_TWFIFO UART_TWFIFO_REG(UART4)
bogdanm 82:6473597d706e 12445 #define UART4_TCFIFO UART_TCFIFO_REG(UART4)
bogdanm 82:6473597d706e 12446 #define UART4_RWFIFO UART_RWFIFO_REG(UART4)
bogdanm 82:6473597d706e 12447 #define UART4_RCFIFO UART_RCFIFO_REG(UART4)
bogdanm 82:6473597d706e 12448 /* UART5 */
bogdanm 82:6473597d706e 12449 #define UART5_BDH UART_BDH_REG(UART5)
bogdanm 82:6473597d706e 12450 #define UART5_BDL UART_BDL_REG(UART5)
bogdanm 82:6473597d706e 12451 #define UART5_C1 UART_C1_REG(UART5)
bogdanm 82:6473597d706e 12452 #define UART5_C2 UART_C2_REG(UART5)
bogdanm 82:6473597d706e 12453 #define UART5_S1 UART_S1_REG(UART5)
bogdanm 82:6473597d706e 12454 #define UART5_S2 UART_S2_REG(UART5)
bogdanm 82:6473597d706e 12455 #define UART5_C3 UART_C3_REG(UART5)
bogdanm 82:6473597d706e 12456 #define UART5_D UART_D_REG(UART5)
bogdanm 82:6473597d706e 12457 #define UART5_MA1 UART_MA1_REG(UART5)
bogdanm 82:6473597d706e 12458 #define UART5_MA2 UART_MA2_REG(UART5)
bogdanm 82:6473597d706e 12459 #define UART5_C4 UART_C4_REG(UART5)
bogdanm 82:6473597d706e 12460 #define UART5_C5 UART_C5_REG(UART5)
bogdanm 82:6473597d706e 12461 #define UART5_ED UART_ED_REG(UART5)
bogdanm 82:6473597d706e 12462 #define UART5_MODEM UART_MODEM_REG(UART5)
bogdanm 82:6473597d706e 12463 #define UART5_IR UART_IR_REG(UART5)
bogdanm 82:6473597d706e 12464 #define UART5_PFIFO UART_PFIFO_REG(UART5)
bogdanm 82:6473597d706e 12465 #define UART5_CFIFO UART_CFIFO_REG(UART5)
bogdanm 82:6473597d706e 12466 #define UART5_SFIFO UART_SFIFO_REG(UART5)
bogdanm 82:6473597d706e 12467 #define UART5_TWFIFO UART_TWFIFO_REG(UART5)
bogdanm 82:6473597d706e 12468 #define UART5_TCFIFO UART_TCFIFO_REG(UART5)
bogdanm 82:6473597d706e 12469 #define UART5_RWFIFO UART_RWFIFO_REG(UART5)
bogdanm 82:6473597d706e 12470 #define UART5_RCFIFO UART_RCFIFO_REG(UART5)
bogdanm 82:6473597d706e 12471
bogdanm 82:6473597d706e 12472 /*!
bogdanm 82:6473597d706e 12473 * @}
bogdanm 82:6473597d706e 12474 */ /* end of group UART_Register_Accessor_Macros */
bogdanm 82:6473597d706e 12475
bogdanm 82:6473597d706e 12476
bogdanm 82:6473597d706e 12477 /*!
bogdanm 82:6473597d706e 12478 * @}
bogdanm 82:6473597d706e 12479 */ /* end of group UART_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 12480
bogdanm 82:6473597d706e 12481
bogdanm 82:6473597d706e 12482 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 12483 -- USB Peripheral Access Layer
bogdanm 82:6473597d706e 12484 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 12485
bogdanm 82:6473597d706e 12486 /*!
bogdanm 82:6473597d706e 12487 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
bogdanm 82:6473597d706e 12488 * @{
bogdanm 82:6473597d706e 12489 */
bogdanm 82:6473597d706e 12490
bogdanm 82:6473597d706e 12491 /** USB - Register Layout Typedef */
bogdanm 82:6473597d706e 12492 typedef struct {
bogdanm 82:6473597d706e 12493 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
bogdanm 82:6473597d706e 12494 uint8_t RESERVED_0[3];
bogdanm 82:6473597d706e 12495 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
bogdanm 82:6473597d706e 12496 uint8_t RESERVED_1[3];
bogdanm 82:6473597d706e 12497 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
bogdanm 82:6473597d706e 12498 uint8_t RESERVED_2[3];
bogdanm 82:6473597d706e 12499 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
bogdanm 82:6473597d706e 12500 uint8_t RESERVED_3[3];
bogdanm 82:6473597d706e 12501 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
bogdanm 82:6473597d706e 12502 uint8_t RESERVED_4[3];
bogdanm 82:6473597d706e 12503 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
bogdanm 82:6473597d706e 12504 uint8_t RESERVED_5[3];
bogdanm 82:6473597d706e 12505 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
bogdanm 82:6473597d706e 12506 uint8_t RESERVED_6[3];
bogdanm 82:6473597d706e 12507 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
bogdanm 82:6473597d706e 12508 uint8_t RESERVED_7[99];
bogdanm 82:6473597d706e 12509 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
bogdanm 82:6473597d706e 12510 uint8_t RESERVED_8[3];
bogdanm 82:6473597d706e 12511 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
bogdanm 82:6473597d706e 12512 uint8_t RESERVED_9[3];
bogdanm 82:6473597d706e 12513 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
bogdanm 82:6473597d706e 12514 uint8_t RESERVED_10[3];
bogdanm 82:6473597d706e 12515 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
bogdanm 82:6473597d706e 12516 uint8_t RESERVED_11[3];
bogdanm 82:6473597d706e 12517 __I uint8_t STAT; /**< Status register, offset: 0x90 */
bogdanm 82:6473597d706e 12518 uint8_t RESERVED_12[3];
bogdanm 82:6473597d706e 12519 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
bogdanm 82:6473597d706e 12520 uint8_t RESERVED_13[3];
bogdanm 82:6473597d706e 12521 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
bogdanm 82:6473597d706e 12522 uint8_t RESERVED_14[3];
bogdanm 82:6473597d706e 12523 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
bogdanm 82:6473597d706e 12524 uint8_t RESERVED_15[3];
bogdanm 82:6473597d706e 12525 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
bogdanm 82:6473597d706e 12526 uint8_t RESERVED_16[3];
bogdanm 82:6473597d706e 12527 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
bogdanm 82:6473597d706e 12528 uint8_t RESERVED_17[3];
bogdanm 82:6473597d706e 12529 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
bogdanm 82:6473597d706e 12530 uint8_t RESERVED_18[3];
bogdanm 82:6473597d706e 12531 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
bogdanm 82:6473597d706e 12532 uint8_t RESERVED_19[3];
bogdanm 82:6473597d706e 12533 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
bogdanm 82:6473597d706e 12534 uint8_t RESERVED_20[3];
bogdanm 82:6473597d706e 12535 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
bogdanm 82:6473597d706e 12536 uint8_t RESERVED_21[11];
bogdanm 82:6473597d706e 12537 struct { /* offset: 0xC0, array step: 0x4 */
bogdanm 82:6473597d706e 12538 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
bogdanm 82:6473597d706e 12539 uint8_t RESERVED_0[3];
bogdanm 82:6473597d706e 12540 } ENDPOINT[16];
bogdanm 82:6473597d706e 12541 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
bogdanm 82:6473597d706e 12542 uint8_t RESERVED_22[3];
bogdanm 82:6473597d706e 12543 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
bogdanm 82:6473597d706e 12544 uint8_t RESERVED_23[3];
bogdanm 82:6473597d706e 12545 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
bogdanm 82:6473597d706e 12546 uint8_t RESERVED_24[3];
bogdanm 82:6473597d706e 12547 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
bogdanm 82:6473597d706e 12548 uint8_t RESERVED_25[7];
bogdanm 82:6473597d706e 12549 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
bogdanm 82:6473597d706e 12550 } USB_Type, *USB_MemMapPtr;
bogdanm 82:6473597d706e 12551
bogdanm 82:6473597d706e 12552 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 12553 -- USB - Register accessor macros
bogdanm 82:6473597d706e 12554 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 12555
bogdanm 82:6473597d706e 12556 /*!
bogdanm 82:6473597d706e 12557 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
bogdanm 82:6473597d706e 12558 * @{
bogdanm 82:6473597d706e 12559 */
bogdanm 82:6473597d706e 12560
bogdanm 82:6473597d706e 12561
bogdanm 82:6473597d706e 12562 /* USB - Register accessors */
bogdanm 82:6473597d706e 12563 #define USB_PERID_REG(base) ((base)->PERID)
bogdanm 82:6473597d706e 12564 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
bogdanm 82:6473597d706e 12565 #define USB_REV_REG(base) ((base)->REV)
bogdanm 82:6473597d706e 12566 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
bogdanm 82:6473597d706e 12567 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
bogdanm 82:6473597d706e 12568 #define USB_OTGICR_REG(base) ((base)->OTGICR)
bogdanm 82:6473597d706e 12569 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
bogdanm 82:6473597d706e 12570 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
bogdanm 82:6473597d706e 12571 #define USB_ISTAT_REG(base) ((base)->ISTAT)
bogdanm 82:6473597d706e 12572 #define USB_INTEN_REG(base) ((base)->INTEN)
bogdanm 82:6473597d706e 12573 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
bogdanm 82:6473597d706e 12574 #define USB_ERREN_REG(base) ((base)->ERREN)
bogdanm 82:6473597d706e 12575 #define USB_STAT_REG(base) ((base)->STAT)
bogdanm 82:6473597d706e 12576 #define USB_CTL_REG(base) ((base)->CTL)
bogdanm 82:6473597d706e 12577 #define USB_ADDR_REG(base) ((base)->ADDR)
bogdanm 82:6473597d706e 12578 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
bogdanm 82:6473597d706e 12579 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
bogdanm 82:6473597d706e 12580 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
bogdanm 82:6473597d706e 12581 #define USB_TOKEN_REG(base) ((base)->TOKEN)
bogdanm 82:6473597d706e 12582 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
bogdanm 82:6473597d706e 12583 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
bogdanm 82:6473597d706e 12584 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
bogdanm 82:6473597d706e 12585 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
bogdanm 82:6473597d706e 12586 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
bogdanm 82:6473597d706e 12587 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
bogdanm 82:6473597d706e 12588 #define USB_CONTROL_REG(base) ((base)->CONTROL)
bogdanm 82:6473597d706e 12589 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
bogdanm 82:6473597d706e 12590 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
bogdanm 82:6473597d706e 12591
bogdanm 82:6473597d706e 12592 /*!
bogdanm 82:6473597d706e 12593 * @}
bogdanm 82:6473597d706e 12594 */ /* end of group USB_Register_Accessor_Macros */
bogdanm 82:6473597d706e 12595
bogdanm 82:6473597d706e 12596
bogdanm 82:6473597d706e 12597 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 12598 -- USB Register Masks
bogdanm 82:6473597d706e 12599 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 12600
bogdanm 82:6473597d706e 12601 /*!
bogdanm 82:6473597d706e 12602 * @addtogroup USB_Register_Masks USB Register Masks
bogdanm 82:6473597d706e 12603 * @{
bogdanm 82:6473597d706e 12604 */
bogdanm 82:6473597d706e 12605
bogdanm 82:6473597d706e 12606 /* PERID Bit Fields */
bogdanm 82:6473597d706e 12607 #define USB_PERID_ID_MASK 0x3Fu
bogdanm 82:6473597d706e 12608 #define USB_PERID_ID_SHIFT 0
bogdanm 82:6473597d706e 12609 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
bogdanm 82:6473597d706e 12610 /* IDCOMP Bit Fields */
bogdanm 82:6473597d706e 12611 #define USB_IDCOMP_NID_MASK 0x3Fu
bogdanm 82:6473597d706e 12612 #define USB_IDCOMP_NID_SHIFT 0
bogdanm 82:6473597d706e 12613 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
bogdanm 82:6473597d706e 12614 /* REV Bit Fields */
bogdanm 82:6473597d706e 12615 #define USB_REV_REV_MASK 0xFFu
bogdanm 82:6473597d706e 12616 #define USB_REV_REV_SHIFT 0
bogdanm 82:6473597d706e 12617 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
bogdanm 82:6473597d706e 12618 /* ADDINFO Bit Fields */
bogdanm 82:6473597d706e 12619 #define USB_ADDINFO_IEHOST_MASK 0x1u
bogdanm 82:6473597d706e 12620 #define USB_ADDINFO_IEHOST_SHIFT 0
bogdanm 82:6473597d706e 12621 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
bogdanm 82:6473597d706e 12622 #define USB_ADDINFO_IRQNUM_SHIFT 3
bogdanm 82:6473597d706e 12623 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
bogdanm 82:6473597d706e 12624 /* OTGISTAT Bit Fields */
bogdanm 82:6473597d706e 12625 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
bogdanm 82:6473597d706e 12626 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
bogdanm 82:6473597d706e 12627 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
bogdanm 82:6473597d706e 12628 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
bogdanm 82:6473597d706e 12629 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
bogdanm 82:6473597d706e 12630 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
bogdanm 82:6473597d706e 12631 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
bogdanm 82:6473597d706e 12632 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
bogdanm 82:6473597d706e 12633 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
bogdanm 82:6473597d706e 12634 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
bogdanm 82:6473597d706e 12635 #define USB_OTGISTAT_IDCHG_MASK 0x80u
bogdanm 82:6473597d706e 12636 #define USB_OTGISTAT_IDCHG_SHIFT 7
bogdanm 82:6473597d706e 12637 /* OTGICR Bit Fields */
bogdanm 82:6473597d706e 12638 #define USB_OTGICR_AVBUSEN_MASK 0x1u
bogdanm 82:6473597d706e 12639 #define USB_OTGICR_AVBUSEN_SHIFT 0
bogdanm 82:6473597d706e 12640 #define USB_OTGICR_BSESSEN_MASK 0x4u
bogdanm 82:6473597d706e 12641 #define USB_OTGICR_BSESSEN_SHIFT 2
bogdanm 82:6473597d706e 12642 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
bogdanm 82:6473597d706e 12643 #define USB_OTGICR_SESSVLDEN_SHIFT 3
bogdanm 82:6473597d706e 12644 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
bogdanm 82:6473597d706e 12645 #define USB_OTGICR_LINESTATEEN_SHIFT 5
bogdanm 82:6473597d706e 12646 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
bogdanm 82:6473597d706e 12647 #define USB_OTGICR_ONEMSECEN_SHIFT 6
bogdanm 82:6473597d706e 12648 #define USB_OTGICR_IDEN_MASK 0x80u
bogdanm 82:6473597d706e 12649 #define USB_OTGICR_IDEN_SHIFT 7
bogdanm 82:6473597d706e 12650 /* OTGSTAT Bit Fields */
bogdanm 82:6473597d706e 12651 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
bogdanm 82:6473597d706e 12652 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
bogdanm 82:6473597d706e 12653 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
bogdanm 82:6473597d706e 12654 #define USB_OTGSTAT_BSESSEND_SHIFT 2
bogdanm 82:6473597d706e 12655 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
bogdanm 82:6473597d706e 12656 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
bogdanm 82:6473597d706e 12657 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
bogdanm 82:6473597d706e 12658 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
bogdanm 82:6473597d706e 12659 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
bogdanm 82:6473597d706e 12660 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
bogdanm 82:6473597d706e 12661 #define USB_OTGSTAT_ID_MASK 0x80u
bogdanm 82:6473597d706e 12662 #define USB_OTGSTAT_ID_SHIFT 7
bogdanm 82:6473597d706e 12663 /* OTGCTL Bit Fields */
bogdanm 82:6473597d706e 12664 #define USB_OTGCTL_OTGEN_MASK 0x4u
bogdanm 82:6473597d706e 12665 #define USB_OTGCTL_OTGEN_SHIFT 2
bogdanm 82:6473597d706e 12666 #define USB_OTGCTL_DMLOW_MASK 0x10u
bogdanm 82:6473597d706e 12667 #define USB_OTGCTL_DMLOW_SHIFT 4
bogdanm 82:6473597d706e 12668 #define USB_OTGCTL_DPLOW_MASK 0x20u
bogdanm 82:6473597d706e 12669 #define USB_OTGCTL_DPLOW_SHIFT 5
bogdanm 82:6473597d706e 12670 #define USB_OTGCTL_DPHIGH_MASK 0x80u
bogdanm 82:6473597d706e 12671 #define USB_OTGCTL_DPHIGH_SHIFT 7
bogdanm 82:6473597d706e 12672 /* ISTAT Bit Fields */
bogdanm 82:6473597d706e 12673 #define USB_ISTAT_USBRST_MASK 0x1u
bogdanm 82:6473597d706e 12674 #define USB_ISTAT_USBRST_SHIFT 0
bogdanm 82:6473597d706e 12675 #define USB_ISTAT_ERROR_MASK 0x2u
bogdanm 82:6473597d706e 12676 #define USB_ISTAT_ERROR_SHIFT 1
bogdanm 82:6473597d706e 12677 #define USB_ISTAT_SOFTOK_MASK 0x4u
bogdanm 82:6473597d706e 12678 #define USB_ISTAT_SOFTOK_SHIFT 2
bogdanm 82:6473597d706e 12679 #define USB_ISTAT_TOKDNE_MASK 0x8u
bogdanm 82:6473597d706e 12680 #define USB_ISTAT_TOKDNE_SHIFT 3
bogdanm 82:6473597d706e 12681 #define USB_ISTAT_SLEEP_MASK 0x10u
bogdanm 82:6473597d706e 12682 #define USB_ISTAT_SLEEP_SHIFT 4
bogdanm 82:6473597d706e 12683 #define USB_ISTAT_RESUME_MASK 0x20u
bogdanm 82:6473597d706e 12684 #define USB_ISTAT_RESUME_SHIFT 5
bogdanm 82:6473597d706e 12685 #define USB_ISTAT_ATTACH_MASK 0x40u
bogdanm 82:6473597d706e 12686 #define USB_ISTAT_ATTACH_SHIFT 6
bogdanm 82:6473597d706e 12687 #define USB_ISTAT_STALL_MASK 0x80u
bogdanm 82:6473597d706e 12688 #define USB_ISTAT_STALL_SHIFT 7
bogdanm 82:6473597d706e 12689 /* INTEN Bit Fields */
bogdanm 82:6473597d706e 12690 #define USB_INTEN_USBRSTEN_MASK 0x1u
bogdanm 82:6473597d706e 12691 #define USB_INTEN_USBRSTEN_SHIFT 0
bogdanm 82:6473597d706e 12692 #define USB_INTEN_ERROREN_MASK 0x2u
bogdanm 82:6473597d706e 12693 #define USB_INTEN_ERROREN_SHIFT 1
bogdanm 82:6473597d706e 12694 #define USB_INTEN_SOFTOKEN_MASK 0x4u
bogdanm 82:6473597d706e 12695 #define USB_INTEN_SOFTOKEN_SHIFT 2
bogdanm 82:6473597d706e 12696 #define USB_INTEN_TOKDNEEN_MASK 0x8u
bogdanm 82:6473597d706e 12697 #define USB_INTEN_TOKDNEEN_SHIFT 3
bogdanm 82:6473597d706e 12698 #define USB_INTEN_SLEEPEN_MASK 0x10u
bogdanm 82:6473597d706e 12699 #define USB_INTEN_SLEEPEN_SHIFT 4
bogdanm 82:6473597d706e 12700 #define USB_INTEN_RESUMEEN_MASK 0x20u
bogdanm 82:6473597d706e 12701 #define USB_INTEN_RESUMEEN_SHIFT 5
bogdanm 82:6473597d706e 12702 #define USB_INTEN_ATTACHEN_MASK 0x40u
bogdanm 82:6473597d706e 12703 #define USB_INTEN_ATTACHEN_SHIFT 6
bogdanm 82:6473597d706e 12704 #define USB_INTEN_STALLEN_MASK 0x80u
bogdanm 82:6473597d706e 12705 #define USB_INTEN_STALLEN_SHIFT 7
bogdanm 82:6473597d706e 12706 /* ERRSTAT Bit Fields */
bogdanm 82:6473597d706e 12707 #define USB_ERRSTAT_PIDERR_MASK 0x1u
bogdanm 82:6473597d706e 12708 #define USB_ERRSTAT_PIDERR_SHIFT 0
bogdanm 82:6473597d706e 12709 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
bogdanm 82:6473597d706e 12710 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
bogdanm 82:6473597d706e 12711 #define USB_ERRSTAT_CRC16_MASK 0x4u
bogdanm 82:6473597d706e 12712 #define USB_ERRSTAT_CRC16_SHIFT 2
bogdanm 82:6473597d706e 12713 #define USB_ERRSTAT_DFN8_MASK 0x8u
bogdanm 82:6473597d706e 12714 #define USB_ERRSTAT_DFN8_SHIFT 3
bogdanm 82:6473597d706e 12715 #define USB_ERRSTAT_BTOERR_MASK 0x10u
bogdanm 82:6473597d706e 12716 #define USB_ERRSTAT_BTOERR_SHIFT 4
bogdanm 82:6473597d706e 12717 #define USB_ERRSTAT_DMAERR_MASK 0x20u
bogdanm 82:6473597d706e 12718 #define USB_ERRSTAT_DMAERR_SHIFT 5
bogdanm 82:6473597d706e 12719 #define USB_ERRSTAT_BTSERR_MASK 0x80u
bogdanm 82:6473597d706e 12720 #define USB_ERRSTAT_BTSERR_SHIFT 7
bogdanm 82:6473597d706e 12721 /* ERREN Bit Fields */
bogdanm 82:6473597d706e 12722 #define USB_ERREN_PIDERREN_MASK 0x1u
bogdanm 82:6473597d706e 12723 #define USB_ERREN_PIDERREN_SHIFT 0
bogdanm 82:6473597d706e 12724 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
bogdanm 82:6473597d706e 12725 #define USB_ERREN_CRC5EOFEN_SHIFT 1
bogdanm 82:6473597d706e 12726 #define USB_ERREN_CRC16EN_MASK 0x4u
bogdanm 82:6473597d706e 12727 #define USB_ERREN_CRC16EN_SHIFT 2
bogdanm 82:6473597d706e 12728 #define USB_ERREN_DFN8EN_MASK 0x8u
bogdanm 82:6473597d706e 12729 #define USB_ERREN_DFN8EN_SHIFT 3
bogdanm 82:6473597d706e 12730 #define USB_ERREN_BTOERREN_MASK 0x10u
bogdanm 82:6473597d706e 12731 #define USB_ERREN_BTOERREN_SHIFT 4
bogdanm 82:6473597d706e 12732 #define USB_ERREN_DMAERREN_MASK 0x20u
bogdanm 82:6473597d706e 12733 #define USB_ERREN_DMAERREN_SHIFT 5
bogdanm 82:6473597d706e 12734 #define USB_ERREN_BTSERREN_MASK 0x80u
bogdanm 82:6473597d706e 12735 #define USB_ERREN_BTSERREN_SHIFT 7
bogdanm 82:6473597d706e 12736 /* STAT Bit Fields */
bogdanm 82:6473597d706e 12737 #define USB_STAT_ODD_MASK 0x4u
bogdanm 82:6473597d706e 12738 #define USB_STAT_ODD_SHIFT 2
bogdanm 82:6473597d706e 12739 #define USB_STAT_TX_MASK 0x8u
bogdanm 82:6473597d706e 12740 #define USB_STAT_TX_SHIFT 3
bogdanm 82:6473597d706e 12741 #define USB_STAT_ENDP_MASK 0xF0u
bogdanm 82:6473597d706e 12742 #define USB_STAT_ENDP_SHIFT 4
bogdanm 82:6473597d706e 12743 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
bogdanm 82:6473597d706e 12744 /* CTL Bit Fields */
bogdanm 82:6473597d706e 12745 #define USB_CTL_USBENSOFEN_MASK 0x1u
bogdanm 82:6473597d706e 12746 #define USB_CTL_USBENSOFEN_SHIFT 0
bogdanm 82:6473597d706e 12747 #define USB_CTL_ODDRST_MASK 0x2u
bogdanm 82:6473597d706e 12748 #define USB_CTL_ODDRST_SHIFT 1
bogdanm 82:6473597d706e 12749 #define USB_CTL_RESUME_MASK 0x4u
bogdanm 82:6473597d706e 12750 #define USB_CTL_RESUME_SHIFT 2
bogdanm 82:6473597d706e 12751 #define USB_CTL_HOSTMODEEN_MASK 0x8u
bogdanm 82:6473597d706e 12752 #define USB_CTL_HOSTMODEEN_SHIFT 3
bogdanm 82:6473597d706e 12753 #define USB_CTL_RESET_MASK 0x10u
bogdanm 82:6473597d706e 12754 #define USB_CTL_RESET_SHIFT 4
bogdanm 82:6473597d706e 12755 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
bogdanm 82:6473597d706e 12756 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
bogdanm 82:6473597d706e 12757 #define USB_CTL_SE0_MASK 0x40u
bogdanm 82:6473597d706e 12758 #define USB_CTL_SE0_SHIFT 6
bogdanm 82:6473597d706e 12759 #define USB_CTL_JSTATE_MASK 0x80u
bogdanm 82:6473597d706e 12760 #define USB_CTL_JSTATE_SHIFT 7
bogdanm 82:6473597d706e 12761 /* ADDR Bit Fields */
bogdanm 82:6473597d706e 12762 #define USB_ADDR_ADDR_MASK 0x7Fu
bogdanm 82:6473597d706e 12763 #define USB_ADDR_ADDR_SHIFT 0
bogdanm 82:6473597d706e 12764 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
bogdanm 82:6473597d706e 12765 #define USB_ADDR_LSEN_MASK 0x80u
bogdanm 82:6473597d706e 12766 #define USB_ADDR_LSEN_SHIFT 7
bogdanm 82:6473597d706e 12767 /* BDTPAGE1 Bit Fields */
bogdanm 82:6473597d706e 12768 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
bogdanm 82:6473597d706e 12769 #define USB_BDTPAGE1_BDTBA_SHIFT 1
bogdanm 82:6473597d706e 12770 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
bogdanm 82:6473597d706e 12771 /* FRMNUML Bit Fields */
bogdanm 82:6473597d706e 12772 #define USB_FRMNUML_FRM_MASK 0xFFu
bogdanm 82:6473597d706e 12773 #define USB_FRMNUML_FRM_SHIFT 0
bogdanm 82:6473597d706e 12774 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
bogdanm 82:6473597d706e 12775 /* FRMNUMH Bit Fields */
bogdanm 82:6473597d706e 12776 #define USB_FRMNUMH_FRM_MASK 0x7u
bogdanm 82:6473597d706e 12777 #define USB_FRMNUMH_FRM_SHIFT 0
bogdanm 82:6473597d706e 12778 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
bogdanm 82:6473597d706e 12779 /* TOKEN Bit Fields */
bogdanm 82:6473597d706e 12780 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
bogdanm 82:6473597d706e 12781 #define USB_TOKEN_TOKENENDPT_SHIFT 0
bogdanm 82:6473597d706e 12782 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
bogdanm 82:6473597d706e 12783 #define USB_TOKEN_TOKENPID_MASK 0xF0u
bogdanm 82:6473597d706e 12784 #define USB_TOKEN_TOKENPID_SHIFT 4
bogdanm 82:6473597d706e 12785 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
bogdanm 82:6473597d706e 12786 /* SOFTHLD Bit Fields */
bogdanm 82:6473597d706e 12787 #define USB_SOFTHLD_CNT_MASK 0xFFu
bogdanm 82:6473597d706e 12788 #define USB_SOFTHLD_CNT_SHIFT 0
bogdanm 82:6473597d706e 12789 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
bogdanm 82:6473597d706e 12790 /* BDTPAGE2 Bit Fields */
bogdanm 82:6473597d706e 12791 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
bogdanm 82:6473597d706e 12792 #define USB_BDTPAGE2_BDTBA_SHIFT 0
bogdanm 82:6473597d706e 12793 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
bogdanm 82:6473597d706e 12794 /* BDTPAGE3 Bit Fields */
bogdanm 82:6473597d706e 12795 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
bogdanm 82:6473597d706e 12796 #define USB_BDTPAGE3_BDTBA_SHIFT 0
bogdanm 82:6473597d706e 12797 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
bogdanm 82:6473597d706e 12798 /* ENDPT Bit Fields */
bogdanm 82:6473597d706e 12799 #define USB_ENDPT_EPHSHK_MASK 0x1u
bogdanm 82:6473597d706e 12800 #define USB_ENDPT_EPHSHK_SHIFT 0
bogdanm 82:6473597d706e 12801 #define USB_ENDPT_EPSTALL_MASK 0x2u
bogdanm 82:6473597d706e 12802 #define USB_ENDPT_EPSTALL_SHIFT 1
bogdanm 82:6473597d706e 12803 #define USB_ENDPT_EPTXEN_MASK 0x4u
bogdanm 82:6473597d706e 12804 #define USB_ENDPT_EPTXEN_SHIFT 2
bogdanm 82:6473597d706e 12805 #define USB_ENDPT_EPRXEN_MASK 0x8u
bogdanm 82:6473597d706e 12806 #define USB_ENDPT_EPRXEN_SHIFT 3
bogdanm 82:6473597d706e 12807 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
bogdanm 82:6473597d706e 12808 #define USB_ENDPT_EPCTLDIS_SHIFT 4
bogdanm 82:6473597d706e 12809 #define USB_ENDPT_RETRYDIS_MASK 0x40u
bogdanm 82:6473597d706e 12810 #define USB_ENDPT_RETRYDIS_SHIFT 6
bogdanm 82:6473597d706e 12811 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
bogdanm 82:6473597d706e 12812 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
bogdanm 82:6473597d706e 12813 /* USBCTRL Bit Fields */
bogdanm 82:6473597d706e 12814 #define USB_USBCTRL_PDE_MASK 0x40u
bogdanm 82:6473597d706e 12815 #define USB_USBCTRL_PDE_SHIFT 6
bogdanm 82:6473597d706e 12816 #define USB_USBCTRL_SUSP_MASK 0x80u
bogdanm 82:6473597d706e 12817 #define USB_USBCTRL_SUSP_SHIFT 7
bogdanm 82:6473597d706e 12818 /* OBSERVE Bit Fields */
bogdanm 82:6473597d706e 12819 #define USB_OBSERVE_DMPD_MASK 0x10u
bogdanm 82:6473597d706e 12820 #define USB_OBSERVE_DMPD_SHIFT 4
bogdanm 82:6473597d706e 12821 #define USB_OBSERVE_DPPD_MASK 0x40u
bogdanm 82:6473597d706e 12822 #define USB_OBSERVE_DPPD_SHIFT 6
bogdanm 82:6473597d706e 12823 #define USB_OBSERVE_DPPU_MASK 0x80u
bogdanm 82:6473597d706e 12824 #define USB_OBSERVE_DPPU_SHIFT 7
bogdanm 82:6473597d706e 12825 /* CONTROL Bit Fields */
bogdanm 82:6473597d706e 12826 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
bogdanm 82:6473597d706e 12827 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
bogdanm 82:6473597d706e 12828 /* USBTRC0 Bit Fields */
bogdanm 82:6473597d706e 12829 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
bogdanm 82:6473597d706e 12830 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
bogdanm 82:6473597d706e 12831 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
bogdanm 82:6473597d706e 12832 #define USB_USBTRC0_SYNC_DET_SHIFT 1
bogdanm 82:6473597d706e 12833 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
bogdanm 82:6473597d706e 12834 #define USB_USBTRC0_USBRESMEN_SHIFT 5
bogdanm 82:6473597d706e 12835 #define USB_USBTRC0_USBRESET_MASK 0x80u
bogdanm 82:6473597d706e 12836 #define USB_USBTRC0_USBRESET_SHIFT 7
bogdanm 82:6473597d706e 12837 /* USBFRMADJUST Bit Fields */
bogdanm 82:6473597d706e 12838 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
bogdanm 82:6473597d706e 12839 #define USB_USBFRMADJUST_ADJ_SHIFT 0
bogdanm 82:6473597d706e 12840 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
bogdanm 82:6473597d706e 12841
bogdanm 82:6473597d706e 12842 /*!
bogdanm 82:6473597d706e 12843 * @}
bogdanm 82:6473597d706e 12844 */ /* end of group USB_Register_Masks */
bogdanm 82:6473597d706e 12845
bogdanm 82:6473597d706e 12846
bogdanm 82:6473597d706e 12847 /* USB - Peripheral instance base addresses */
bogdanm 82:6473597d706e 12848 /** Peripheral USB0 base address */
bogdanm 82:6473597d706e 12849 #define USB0_BASE (0x40072000u)
bogdanm 82:6473597d706e 12850 /** Peripheral USB0 base pointer */
bogdanm 82:6473597d706e 12851 #define USB0 ((USB_Type *)USB0_BASE)
bogdanm 82:6473597d706e 12852 #define USB0_BASE_PTR (USB0)
bogdanm 82:6473597d706e 12853 /** Array initializer of USB peripheral base pointers */
bogdanm 82:6473597d706e 12854 #define USB_BASES { USB0 }
bogdanm 82:6473597d706e 12855
bogdanm 82:6473597d706e 12856 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 12857 -- USB - Register accessor macros
bogdanm 82:6473597d706e 12858 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 12859
bogdanm 82:6473597d706e 12860 /*!
bogdanm 82:6473597d706e 12861 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
bogdanm 82:6473597d706e 12862 * @{
bogdanm 82:6473597d706e 12863 */
bogdanm 82:6473597d706e 12864
bogdanm 82:6473597d706e 12865
bogdanm 82:6473597d706e 12866 /* USB - Register instance definitions */
bogdanm 82:6473597d706e 12867 /* USB0 */
bogdanm 82:6473597d706e 12868 #define USB0_PERID USB_PERID_REG(USB0)
bogdanm 82:6473597d706e 12869 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
bogdanm 82:6473597d706e 12870 #define USB0_REV USB_REV_REG(USB0)
bogdanm 82:6473597d706e 12871 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
bogdanm 82:6473597d706e 12872 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
bogdanm 82:6473597d706e 12873 #define USB0_OTGICR USB_OTGICR_REG(USB0)
bogdanm 82:6473597d706e 12874 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
bogdanm 82:6473597d706e 12875 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
bogdanm 82:6473597d706e 12876 #define USB0_ISTAT USB_ISTAT_REG(USB0)
bogdanm 82:6473597d706e 12877 #define USB0_INTEN USB_INTEN_REG(USB0)
bogdanm 82:6473597d706e 12878 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
bogdanm 82:6473597d706e 12879 #define USB0_ERREN USB_ERREN_REG(USB0)
bogdanm 82:6473597d706e 12880 #define USB0_STAT USB_STAT_REG(USB0)
bogdanm 82:6473597d706e 12881 #define USB0_CTL USB_CTL_REG(USB0)
bogdanm 82:6473597d706e 12882 #define USB0_ADDR USB_ADDR_REG(USB0)
bogdanm 82:6473597d706e 12883 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
bogdanm 82:6473597d706e 12884 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
bogdanm 82:6473597d706e 12885 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
bogdanm 82:6473597d706e 12886 #define USB0_TOKEN USB_TOKEN_REG(USB0)
bogdanm 82:6473597d706e 12887 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
bogdanm 82:6473597d706e 12888 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
bogdanm 82:6473597d706e 12889 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
bogdanm 82:6473597d706e 12890 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
bogdanm 82:6473597d706e 12891 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
bogdanm 82:6473597d706e 12892 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
bogdanm 82:6473597d706e 12893 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
bogdanm 82:6473597d706e 12894 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
bogdanm 82:6473597d706e 12895 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
bogdanm 82:6473597d706e 12896 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
bogdanm 82:6473597d706e 12897 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
bogdanm 82:6473597d706e 12898 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
bogdanm 82:6473597d706e 12899 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
bogdanm 82:6473597d706e 12900 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
bogdanm 82:6473597d706e 12901 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
bogdanm 82:6473597d706e 12902 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
bogdanm 82:6473597d706e 12903 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
bogdanm 82:6473597d706e 12904 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
bogdanm 82:6473597d706e 12905 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
bogdanm 82:6473597d706e 12906 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
bogdanm 82:6473597d706e 12907 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
bogdanm 82:6473597d706e 12908 #define USB0_CONTROL USB_CONTROL_REG(USB0)
bogdanm 82:6473597d706e 12909 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
bogdanm 82:6473597d706e 12910 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
bogdanm 82:6473597d706e 12911
bogdanm 82:6473597d706e 12912 /* USB - Register array accessors */
bogdanm 82:6473597d706e 12913 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
bogdanm 82:6473597d706e 12914
bogdanm 82:6473597d706e 12915 /*!
bogdanm 82:6473597d706e 12916 * @}
bogdanm 82:6473597d706e 12917 */ /* end of group USB_Register_Accessor_Macros */
bogdanm 82:6473597d706e 12918
bogdanm 82:6473597d706e 12919
bogdanm 82:6473597d706e 12920 /*!
bogdanm 82:6473597d706e 12921 * @}
bogdanm 82:6473597d706e 12922 */ /* end of group USB_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 12923
bogdanm 82:6473597d706e 12924
bogdanm 82:6473597d706e 12925 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 12926 -- USBDCD Peripheral Access Layer
bogdanm 82:6473597d706e 12927 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 12928
bogdanm 82:6473597d706e 12929 /*!
bogdanm 82:6473597d706e 12930 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
bogdanm 82:6473597d706e 12931 * @{
bogdanm 82:6473597d706e 12932 */
bogdanm 82:6473597d706e 12933
bogdanm 82:6473597d706e 12934 /** USBDCD - Register Layout Typedef */
bogdanm 82:6473597d706e 12935 typedef struct {
bogdanm 82:6473597d706e 12936 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
bogdanm 82:6473597d706e 12937 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
bogdanm 82:6473597d706e 12938 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
bogdanm 82:6473597d706e 12939 uint8_t RESERVED_0[4];
bogdanm 82:6473597d706e 12940 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
bogdanm 82:6473597d706e 12941 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
bogdanm 82:6473597d706e 12942 union { /* offset: 0x18 */
bogdanm 82:6473597d706e 12943 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
bogdanm 82:6473597d706e 12944 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
bogdanm 82:6473597d706e 12945 };
bogdanm 82:6473597d706e 12946 } USBDCD_Type, *USBDCD_MemMapPtr;
bogdanm 82:6473597d706e 12947
bogdanm 82:6473597d706e 12948 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 12949 -- USBDCD - Register accessor macros
bogdanm 82:6473597d706e 12950 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 12951
bogdanm 82:6473597d706e 12952 /*!
bogdanm 82:6473597d706e 12953 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
bogdanm 82:6473597d706e 12954 * @{
bogdanm 82:6473597d706e 12955 */
bogdanm 82:6473597d706e 12956
bogdanm 82:6473597d706e 12957
bogdanm 82:6473597d706e 12958 /* USBDCD - Register accessors */
bogdanm 82:6473597d706e 12959 #define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
bogdanm 82:6473597d706e 12960 #define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
bogdanm 82:6473597d706e 12961 #define USBDCD_STATUS_REG(base) ((base)->STATUS)
bogdanm 82:6473597d706e 12962 #define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
bogdanm 82:6473597d706e 12963 #define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
bogdanm 82:6473597d706e 12964 #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
bogdanm 82:6473597d706e 12965 #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
bogdanm 82:6473597d706e 12966
bogdanm 82:6473597d706e 12967 /*!
bogdanm 82:6473597d706e 12968 * @}
bogdanm 82:6473597d706e 12969 */ /* end of group USBDCD_Register_Accessor_Macros */
bogdanm 82:6473597d706e 12970
bogdanm 82:6473597d706e 12971
bogdanm 82:6473597d706e 12972 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 12973 -- USBDCD Register Masks
bogdanm 82:6473597d706e 12974 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 12975
bogdanm 82:6473597d706e 12976 /*!
bogdanm 82:6473597d706e 12977 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
bogdanm 82:6473597d706e 12978 * @{
bogdanm 82:6473597d706e 12979 */
bogdanm 82:6473597d706e 12980
bogdanm 82:6473597d706e 12981 /* CONTROL Bit Fields */
bogdanm 82:6473597d706e 12982 #define USBDCD_CONTROL_IACK_MASK 0x1u
bogdanm 82:6473597d706e 12983 #define USBDCD_CONTROL_IACK_SHIFT 0
bogdanm 82:6473597d706e 12984 #define USBDCD_CONTROL_IF_MASK 0x100u
bogdanm 82:6473597d706e 12985 #define USBDCD_CONTROL_IF_SHIFT 8
bogdanm 82:6473597d706e 12986 #define USBDCD_CONTROL_IE_MASK 0x10000u
bogdanm 82:6473597d706e 12987 #define USBDCD_CONTROL_IE_SHIFT 16
bogdanm 82:6473597d706e 12988 #define USBDCD_CONTROL_BC12_MASK 0x20000u
bogdanm 82:6473597d706e 12989 #define USBDCD_CONTROL_BC12_SHIFT 17
bogdanm 82:6473597d706e 12990 #define USBDCD_CONTROL_START_MASK 0x1000000u
bogdanm 82:6473597d706e 12991 #define USBDCD_CONTROL_START_SHIFT 24
bogdanm 82:6473597d706e 12992 #define USBDCD_CONTROL_SR_MASK 0x2000000u
bogdanm 82:6473597d706e 12993 #define USBDCD_CONTROL_SR_SHIFT 25
bogdanm 82:6473597d706e 12994 /* CLOCK Bit Fields */
bogdanm 82:6473597d706e 12995 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
bogdanm 82:6473597d706e 12996 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
bogdanm 82:6473597d706e 12997 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
bogdanm 82:6473597d706e 12998 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
bogdanm 82:6473597d706e 12999 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
bogdanm 82:6473597d706e 13000 /* STATUS Bit Fields */
bogdanm 82:6473597d706e 13001 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
bogdanm 82:6473597d706e 13002 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
bogdanm 82:6473597d706e 13003 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
bogdanm 82:6473597d706e 13004 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
bogdanm 82:6473597d706e 13005 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
bogdanm 82:6473597d706e 13006 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
bogdanm 82:6473597d706e 13007 #define USBDCD_STATUS_ERR_MASK 0x100000u
bogdanm 82:6473597d706e 13008 #define USBDCD_STATUS_ERR_SHIFT 20
bogdanm 82:6473597d706e 13009 #define USBDCD_STATUS_TO_MASK 0x200000u
bogdanm 82:6473597d706e 13010 #define USBDCD_STATUS_TO_SHIFT 21
bogdanm 82:6473597d706e 13011 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
bogdanm 82:6473597d706e 13012 #define USBDCD_STATUS_ACTIVE_SHIFT 22
bogdanm 82:6473597d706e 13013 /* TIMER0 Bit Fields */
bogdanm 82:6473597d706e 13014 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
bogdanm 82:6473597d706e 13015 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
bogdanm 82:6473597d706e 13016 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
bogdanm 82:6473597d706e 13017 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
bogdanm 82:6473597d706e 13018 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
bogdanm 82:6473597d706e 13019 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
bogdanm 82:6473597d706e 13020 /* TIMER1 Bit Fields */
bogdanm 82:6473597d706e 13021 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
bogdanm 82:6473597d706e 13022 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
bogdanm 82:6473597d706e 13023 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
bogdanm 82:6473597d706e 13024 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
bogdanm 82:6473597d706e 13025 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
bogdanm 82:6473597d706e 13026 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
bogdanm 82:6473597d706e 13027 /* TIMER2_BC11 Bit Fields */
bogdanm 82:6473597d706e 13028 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
bogdanm 82:6473597d706e 13029 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
bogdanm 82:6473597d706e 13030 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
bogdanm 82:6473597d706e 13031 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
bogdanm 82:6473597d706e 13032 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
bogdanm 82:6473597d706e 13033 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
bogdanm 82:6473597d706e 13034 /* TIMER2_BC12 Bit Fields */
bogdanm 82:6473597d706e 13035 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
bogdanm 82:6473597d706e 13036 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
bogdanm 82:6473597d706e 13037 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
bogdanm 82:6473597d706e 13038 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
bogdanm 82:6473597d706e 13039 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
bogdanm 82:6473597d706e 13040 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
bogdanm 82:6473597d706e 13041
bogdanm 82:6473597d706e 13042 /*!
bogdanm 82:6473597d706e 13043 * @}
bogdanm 82:6473597d706e 13044 */ /* end of group USBDCD_Register_Masks */
bogdanm 82:6473597d706e 13045
bogdanm 82:6473597d706e 13046
bogdanm 82:6473597d706e 13047 /* USBDCD - Peripheral instance base addresses */
bogdanm 82:6473597d706e 13048 /** Peripheral USBDCD base address */
bogdanm 82:6473597d706e 13049 #define USBDCD_BASE (0x40035000u)
bogdanm 82:6473597d706e 13050 /** Peripheral USBDCD base pointer */
bogdanm 82:6473597d706e 13051 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
bogdanm 82:6473597d706e 13052 #define USBDCD_BASE_PTR (USBDCD)
bogdanm 82:6473597d706e 13053 /** Array initializer of USBDCD peripheral base pointers */
bogdanm 82:6473597d706e 13054 #define USBDCD_BASES { USBDCD }
bogdanm 82:6473597d706e 13055
bogdanm 82:6473597d706e 13056 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13057 -- USBDCD - Register accessor macros
bogdanm 82:6473597d706e 13058 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13059
bogdanm 82:6473597d706e 13060 /*!
bogdanm 82:6473597d706e 13061 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
bogdanm 82:6473597d706e 13062 * @{
bogdanm 82:6473597d706e 13063 */
bogdanm 82:6473597d706e 13064
bogdanm 82:6473597d706e 13065
bogdanm 82:6473597d706e 13066 /* USBDCD - Register instance definitions */
bogdanm 82:6473597d706e 13067 /* USBDCD */
bogdanm 82:6473597d706e 13068 #define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
bogdanm 82:6473597d706e 13069 #define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
bogdanm 82:6473597d706e 13070 #define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
bogdanm 82:6473597d706e 13071 #define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
bogdanm 82:6473597d706e 13072 #define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
bogdanm 82:6473597d706e 13073 #define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
bogdanm 82:6473597d706e 13074 #define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
bogdanm 82:6473597d706e 13075
bogdanm 82:6473597d706e 13076 /*!
bogdanm 82:6473597d706e 13077 * @}
bogdanm 82:6473597d706e 13078 */ /* end of group USBDCD_Register_Accessor_Macros */
bogdanm 82:6473597d706e 13079
bogdanm 82:6473597d706e 13080
bogdanm 82:6473597d706e 13081 /*!
bogdanm 82:6473597d706e 13082 * @}
bogdanm 82:6473597d706e 13083 */ /* end of group USBDCD_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 13084
bogdanm 82:6473597d706e 13085
bogdanm 82:6473597d706e 13086 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13087 -- VREF Peripheral Access Layer
bogdanm 82:6473597d706e 13088 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13089
bogdanm 82:6473597d706e 13090 /*!
bogdanm 82:6473597d706e 13091 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
bogdanm 82:6473597d706e 13092 * @{
bogdanm 82:6473597d706e 13093 */
bogdanm 82:6473597d706e 13094
bogdanm 82:6473597d706e 13095 /** VREF - Register Layout Typedef */
bogdanm 82:6473597d706e 13096 typedef struct {
bogdanm 82:6473597d706e 13097 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
bogdanm 82:6473597d706e 13098 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
bogdanm 82:6473597d706e 13099 } VREF_Type, *VREF_MemMapPtr;
bogdanm 82:6473597d706e 13100
bogdanm 82:6473597d706e 13101 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13102 -- VREF - Register accessor macros
bogdanm 82:6473597d706e 13103 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13104
bogdanm 82:6473597d706e 13105 /*!
bogdanm 82:6473597d706e 13106 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
bogdanm 82:6473597d706e 13107 * @{
bogdanm 82:6473597d706e 13108 */
bogdanm 82:6473597d706e 13109
bogdanm 82:6473597d706e 13110
bogdanm 82:6473597d706e 13111 /* VREF - Register accessors */
bogdanm 82:6473597d706e 13112 #define VREF_TRM_REG(base) ((base)->TRM)
bogdanm 82:6473597d706e 13113 #define VREF_SC_REG(base) ((base)->SC)
bogdanm 82:6473597d706e 13114
bogdanm 82:6473597d706e 13115 /*!
bogdanm 82:6473597d706e 13116 * @}
bogdanm 82:6473597d706e 13117 */ /* end of group VREF_Register_Accessor_Macros */
bogdanm 82:6473597d706e 13118
bogdanm 82:6473597d706e 13119
bogdanm 82:6473597d706e 13120 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13121 -- VREF Register Masks
bogdanm 82:6473597d706e 13122 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13123
bogdanm 82:6473597d706e 13124 /*!
bogdanm 82:6473597d706e 13125 * @addtogroup VREF_Register_Masks VREF Register Masks
bogdanm 82:6473597d706e 13126 * @{
bogdanm 82:6473597d706e 13127 */
bogdanm 82:6473597d706e 13128
bogdanm 82:6473597d706e 13129 /* TRM Bit Fields */
bogdanm 82:6473597d706e 13130 #define VREF_TRM_TRIM_MASK 0x3Fu
bogdanm 82:6473597d706e 13131 #define VREF_TRM_TRIM_SHIFT 0
bogdanm 82:6473597d706e 13132 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
bogdanm 82:6473597d706e 13133 #define VREF_TRM_CHOPEN_MASK 0x40u
bogdanm 82:6473597d706e 13134 #define VREF_TRM_CHOPEN_SHIFT 6
bogdanm 82:6473597d706e 13135 /* SC Bit Fields */
bogdanm 82:6473597d706e 13136 #define VREF_SC_MODE_LV_MASK 0x3u
bogdanm 82:6473597d706e 13137 #define VREF_SC_MODE_LV_SHIFT 0
bogdanm 82:6473597d706e 13138 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
bogdanm 82:6473597d706e 13139 #define VREF_SC_VREFST_MASK 0x4u
bogdanm 82:6473597d706e 13140 #define VREF_SC_VREFST_SHIFT 2
bogdanm 82:6473597d706e 13141 #define VREF_SC_ICOMPEN_MASK 0x20u
bogdanm 82:6473597d706e 13142 #define VREF_SC_ICOMPEN_SHIFT 5
bogdanm 82:6473597d706e 13143 #define VREF_SC_REGEN_MASK 0x40u
bogdanm 82:6473597d706e 13144 #define VREF_SC_REGEN_SHIFT 6
bogdanm 82:6473597d706e 13145 #define VREF_SC_VREFEN_MASK 0x80u
bogdanm 82:6473597d706e 13146 #define VREF_SC_VREFEN_SHIFT 7
bogdanm 82:6473597d706e 13147
bogdanm 82:6473597d706e 13148 /*!
bogdanm 82:6473597d706e 13149 * @}
bogdanm 82:6473597d706e 13150 */ /* end of group VREF_Register_Masks */
bogdanm 82:6473597d706e 13151
bogdanm 82:6473597d706e 13152
bogdanm 82:6473597d706e 13153 /* VREF - Peripheral instance base addresses */
bogdanm 82:6473597d706e 13154 /** Peripheral VREF base address */
bogdanm 82:6473597d706e 13155 #define VREF_BASE (0x40074000u)
bogdanm 82:6473597d706e 13156 /** Peripheral VREF base pointer */
bogdanm 82:6473597d706e 13157 #define VREF ((VREF_Type *)VREF_BASE)
bogdanm 82:6473597d706e 13158 #define VREF_BASE_PTR (VREF)
bogdanm 82:6473597d706e 13159 /** Array initializer of VREF peripheral base pointers */
bogdanm 82:6473597d706e 13160 #define VREF_BASES { VREF }
bogdanm 82:6473597d706e 13161
bogdanm 82:6473597d706e 13162 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13163 -- VREF - Register accessor macros
bogdanm 82:6473597d706e 13164 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13165
bogdanm 82:6473597d706e 13166 /*!
bogdanm 82:6473597d706e 13167 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
bogdanm 82:6473597d706e 13168 * @{
bogdanm 82:6473597d706e 13169 */
bogdanm 82:6473597d706e 13170
bogdanm 82:6473597d706e 13171
bogdanm 82:6473597d706e 13172 /* VREF - Register instance definitions */
bogdanm 82:6473597d706e 13173 /* VREF */
bogdanm 82:6473597d706e 13174 #define VREF_TRM VREF_TRM_REG(VREF)
bogdanm 82:6473597d706e 13175 #define VREF_SC VREF_SC_REG(VREF)
bogdanm 82:6473597d706e 13176
bogdanm 82:6473597d706e 13177 /*!
bogdanm 82:6473597d706e 13178 * @}
bogdanm 82:6473597d706e 13179 */ /* end of group VREF_Register_Accessor_Macros */
bogdanm 82:6473597d706e 13180
bogdanm 82:6473597d706e 13181
bogdanm 82:6473597d706e 13182 /*!
bogdanm 82:6473597d706e 13183 * @}
bogdanm 82:6473597d706e 13184 */ /* end of group VREF_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 13185
bogdanm 82:6473597d706e 13186
bogdanm 82:6473597d706e 13187 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13188 -- WDOG Peripheral Access Layer
bogdanm 82:6473597d706e 13189 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13190
bogdanm 82:6473597d706e 13191 /*!
bogdanm 82:6473597d706e 13192 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
bogdanm 82:6473597d706e 13193 * @{
bogdanm 82:6473597d706e 13194 */
bogdanm 82:6473597d706e 13195
bogdanm 82:6473597d706e 13196 /** WDOG - Register Layout Typedef */
bogdanm 82:6473597d706e 13197 typedef struct {
bogdanm 82:6473597d706e 13198 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
bogdanm 82:6473597d706e 13199 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
bogdanm 82:6473597d706e 13200 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
bogdanm 82:6473597d706e 13201 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
bogdanm 82:6473597d706e 13202 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
bogdanm 82:6473597d706e 13203 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
bogdanm 82:6473597d706e 13204 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
bogdanm 82:6473597d706e 13205 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
bogdanm 82:6473597d706e 13206 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
bogdanm 82:6473597d706e 13207 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
bogdanm 82:6473597d706e 13208 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
bogdanm 82:6473597d706e 13209 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
bogdanm 82:6473597d706e 13210 } WDOG_Type, *WDOG_MemMapPtr;
bogdanm 82:6473597d706e 13211
bogdanm 82:6473597d706e 13212 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13213 -- WDOG - Register accessor macros
bogdanm 82:6473597d706e 13214 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13215
bogdanm 82:6473597d706e 13216 /*!
bogdanm 82:6473597d706e 13217 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
bogdanm 82:6473597d706e 13218 * @{
bogdanm 82:6473597d706e 13219 */
bogdanm 82:6473597d706e 13220
bogdanm 82:6473597d706e 13221
bogdanm 82:6473597d706e 13222 /* WDOG - Register accessors */
bogdanm 82:6473597d706e 13223 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
bogdanm 82:6473597d706e 13224 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
bogdanm 82:6473597d706e 13225 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
bogdanm 82:6473597d706e 13226 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
bogdanm 82:6473597d706e 13227 #define WDOG_WINH_REG(base) ((base)->WINH)
bogdanm 82:6473597d706e 13228 #define WDOG_WINL_REG(base) ((base)->WINL)
bogdanm 82:6473597d706e 13229 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
bogdanm 82:6473597d706e 13230 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
bogdanm 82:6473597d706e 13231 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
bogdanm 82:6473597d706e 13232 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
bogdanm 82:6473597d706e 13233 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
bogdanm 82:6473597d706e 13234 #define WDOG_PRESC_REG(base) ((base)->PRESC)
bogdanm 82:6473597d706e 13235
bogdanm 82:6473597d706e 13236 /*!
bogdanm 82:6473597d706e 13237 * @}
bogdanm 82:6473597d706e 13238 */ /* end of group WDOG_Register_Accessor_Macros */
bogdanm 82:6473597d706e 13239
bogdanm 82:6473597d706e 13240
bogdanm 82:6473597d706e 13241 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13242 -- WDOG Register Masks
bogdanm 82:6473597d706e 13243 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13244
bogdanm 82:6473597d706e 13245 /*!
bogdanm 82:6473597d706e 13246 * @addtogroup WDOG_Register_Masks WDOG Register Masks
bogdanm 82:6473597d706e 13247 * @{
bogdanm 82:6473597d706e 13248 */
bogdanm 82:6473597d706e 13249
bogdanm 82:6473597d706e 13250 /* STCTRLH Bit Fields */
bogdanm 82:6473597d706e 13251 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
bogdanm 82:6473597d706e 13252 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
bogdanm 82:6473597d706e 13253 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
bogdanm 82:6473597d706e 13254 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
bogdanm 82:6473597d706e 13255 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
bogdanm 82:6473597d706e 13256 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
bogdanm 82:6473597d706e 13257 #define WDOG_STCTRLH_WINEN_MASK 0x8u
bogdanm 82:6473597d706e 13258 #define WDOG_STCTRLH_WINEN_SHIFT 3
bogdanm 82:6473597d706e 13259 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
bogdanm 82:6473597d706e 13260 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
bogdanm 82:6473597d706e 13261 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
bogdanm 82:6473597d706e 13262 #define WDOG_STCTRLH_DBGEN_SHIFT 5
bogdanm 82:6473597d706e 13263 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
bogdanm 82:6473597d706e 13264 #define WDOG_STCTRLH_STOPEN_SHIFT 6
bogdanm 82:6473597d706e 13265 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
bogdanm 82:6473597d706e 13266 #define WDOG_STCTRLH_WAITEN_SHIFT 7
bogdanm 82:6473597d706e 13267 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
bogdanm 82:6473597d706e 13268 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
bogdanm 82:6473597d706e 13269 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
bogdanm 82:6473597d706e 13270 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
bogdanm 82:6473597d706e 13271 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
bogdanm 82:6473597d706e 13272 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
bogdanm 82:6473597d706e 13273 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
bogdanm 82:6473597d706e 13274 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
bogdanm 82:6473597d706e 13275 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
bogdanm 82:6473597d706e 13276 /* STCTRLL Bit Fields */
bogdanm 82:6473597d706e 13277 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
bogdanm 82:6473597d706e 13278 #define WDOG_STCTRLL_INTFLG_SHIFT 15
bogdanm 82:6473597d706e 13279 /* TOVALH Bit Fields */
bogdanm 82:6473597d706e 13280 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
bogdanm 82:6473597d706e 13281 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
bogdanm 82:6473597d706e 13282 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
bogdanm 82:6473597d706e 13283 /* TOVALL Bit Fields */
bogdanm 82:6473597d706e 13284 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
bogdanm 82:6473597d706e 13285 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
bogdanm 82:6473597d706e 13286 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
bogdanm 82:6473597d706e 13287 /* WINH Bit Fields */
bogdanm 82:6473597d706e 13288 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
bogdanm 82:6473597d706e 13289 #define WDOG_WINH_WINHIGH_SHIFT 0
bogdanm 82:6473597d706e 13290 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
bogdanm 82:6473597d706e 13291 /* WINL Bit Fields */
bogdanm 82:6473597d706e 13292 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
bogdanm 82:6473597d706e 13293 #define WDOG_WINL_WINLOW_SHIFT 0
bogdanm 82:6473597d706e 13294 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
bogdanm 82:6473597d706e 13295 /* REFRESH Bit Fields */
bogdanm 82:6473597d706e 13296 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
bogdanm 82:6473597d706e 13297 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
bogdanm 82:6473597d706e 13298 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
bogdanm 82:6473597d706e 13299 /* UNLOCK Bit Fields */
bogdanm 82:6473597d706e 13300 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
bogdanm 82:6473597d706e 13301 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
bogdanm 82:6473597d706e 13302 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
bogdanm 82:6473597d706e 13303 /* TMROUTH Bit Fields */
bogdanm 82:6473597d706e 13304 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
bogdanm 82:6473597d706e 13305 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
bogdanm 82:6473597d706e 13306 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
bogdanm 82:6473597d706e 13307 /* TMROUTL Bit Fields */
bogdanm 82:6473597d706e 13308 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
bogdanm 82:6473597d706e 13309 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
bogdanm 82:6473597d706e 13310 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
bogdanm 82:6473597d706e 13311 /* RSTCNT Bit Fields */
bogdanm 82:6473597d706e 13312 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
bogdanm 82:6473597d706e 13313 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
bogdanm 82:6473597d706e 13314 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
bogdanm 82:6473597d706e 13315 /* PRESC Bit Fields */
bogdanm 82:6473597d706e 13316 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
bogdanm 82:6473597d706e 13317 #define WDOG_PRESC_PRESCVAL_SHIFT 8
bogdanm 82:6473597d706e 13318 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
bogdanm 82:6473597d706e 13319
bogdanm 82:6473597d706e 13320 /*!
bogdanm 82:6473597d706e 13321 * @}
bogdanm 82:6473597d706e 13322 */ /* end of group WDOG_Register_Masks */
bogdanm 82:6473597d706e 13323
bogdanm 82:6473597d706e 13324
bogdanm 82:6473597d706e 13325 /* WDOG - Peripheral instance base addresses */
bogdanm 82:6473597d706e 13326 /** Peripheral WDOG base address */
bogdanm 82:6473597d706e 13327 #define WDOG_BASE (0x40052000u)
bogdanm 82:6473597d706e 13328 /** Peripheral WDOG base pointer */
bogdanm 82:6473597d706e 13329 #define WDOG ((WDOG_Type *)WDOG_BASE)
bogdanm 82:6473597d706e 13330 #define WDOG_BASE_PTR (WDOG)
bogdanm 82:6473597d706e 13331 /** Array initializer of WDOG peripheral base pointers */
bogdanm 82:6473597d706e 13332 #define WDOG_BASES { WDOG }
bogdanm 82:6473597d706e 13333
bogdanm 82:6473597d706e 13334 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13335 -- WDOG - Register accessor macros
bogdanm 82:6473597d706e 13336 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13337
bogdanm 82:6473597d706e 13338 /*!
bogdanm 82:6473597d706e 13339 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
bogdanm 82:6473597d706e 13340 * @{
bogdanm 82:6473597d706e 13341 */
bogdanm 82:6473597d706e 13342
bogdanm 82:6473597d706e 13343
bogdanm 82:6473597d706e 13344 /* WDOG - Register instance definitions */
bogdanm 82:6473597d706e 13345 /* WDOG */
bogdanm 82:6473597d706e 13346 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
bogdanm 82:6473597d706e 13347 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
bogdanm 82:6473597d706e 13348 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
bogdanm 82:6473597d706e 13349 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
bogdanm 82:6473597d706e 13350 #define WDOG_WINH WDOG_WINH_REG(WDOG)
bogdanm 82:6473597d706e 13351 #define WDOG_WINL WDOG_WINL_REG(WDOG)
bogdanm 82:6473597d706e 13352 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
bogdanm 82:6473597d706e 13353 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
bogdanm 82:6473597d706e 13354 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
bogdanm 82:6473597d706e 13355 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
bogdanm 82:6473597d706e 13356 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
bogdanm 82:6473597d706e 13357 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
bogdanm 82:6473597d706e 13358
bogdanm 82:6473597d706e 13359 /*!
bogdanm 82:6473597d706e 13360 * @}
bogdanm 82:6473597d706e 13361 */ /* end of group WDOG_Register_Accessor_Macros */
bogdanm 82:6473597d706e 13362
bogdanm 82:6473597d706e 13363
bogdanm 82:6473597d706e 13364 /*!
bogdanm 82:6473597d706e 13365 * @}
bogdanm 82:6473597d706e 13366 */ /* end of group WDOG_Peripheral_Access_Layer */
bogdanm 82:6473597d706e 13367
bogdanm 82:6473597d706e 13368
bogdanm 82:6473597d706e 13369 /*
bogdanm 82:6473597d706e 13370 ** End of section using anonymous unions
bogdanm 82:6473597d706e 13371 */
bogdanm 82:6473597d706e 13372
bogdanm 82:6473597d706e 13373 #if defined(__ARMCC_VERSION)
bogdanm 82:6473597d706e 13374 #pragma pop
bogdanm 82:6473597d706e 13375 #elif defined(__CWCC__)
bogdanm 82:6473597d706e 13376 #pragma pop
bogdanm 82:6473597d706e 13377 #elif defined(__GNUC__)
bogdanm 82:6473597d706e 13378 /* leave anonymous unions enabled */
bogdanm 82:6473597d706e 13379 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 82:6473597d706e 13380 #pragma language=default
bogdanm 82:6473597d706e 13381 #else
bogdanm 82:6473597d706e 13382 #error Not supported compiler type
bogdanm 82:6473597d706e 13383 #endif
bogdanm 82:6473597d706e 13384
bogdanm 82:6473597d706e 13385 /*!
bogdanm 82:6473597d706e 13386 * @}
bogdanm 82:6473597d706e 13387 */ /* end of group Peripheral_access_layer */
bogdanm 82:6473597d706e 13388
bogdanm 82:6473597d706e 13389
bogdanm 82:6473597d706e 13390 /* ----------------------------------------------------------------------------
bogdanm 82:6473597d706e 13391 -- Backward Compatibility
bogdanm 82:6473597d706e 13392 ---------------------------------------------------------------------------- */
bogdanm 82:6473597d706e 13393
bogdanm 82:6473597d706e 13394 /*!
bogdanm 82:6473597d706e 13395 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
bogdanm 82:6473597d706e 13396 * @{
bogdanm 82:6473597d706e 13397 */
bogdanm 82:6473597d706e 13398
bogdanm 82:6473597d706e 13399 /* No backward compatibility issues. */
bogdanm 82:6473597d706e 13400
bogdanm 82:6473597d706e 13401 /*!
bogdanm 82:6473597d706e 13402 * @}
bogdanm 82:6473597d706e 13403 */ /* end of group Backward_Compatibility_Symbols */
bogdanm 82:6473597d706e 13404
bogdanm 82:6473597d706e 13405
bogdanm 82:6473597d706e 13406 #else /* #if !defined(MCU_MK64F12) */
bogdanm 82:6473597d706e 13407 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
bogdanm 82:6473597d706e 13408 #if (MCU_MEM_MAP_VERSION != 0x0200u)
bogdanm 82:6473597d706e 13409 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
bogdanm 82:6473597d706e 13410 #warning There are included two not compatible versions of memory maps. Please check possible differences.
bogdanm 82:6473597d706e 13411 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
bogdanm 82:6473597d706e 13412 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
bogdanm 82:6473597d706e 13413 #endif /* #if !defined(MCU_MK64F12) */
bogdanm 82:6473597d706e 13414
bogdanm 82:6473597d706e 13415 #endif /* #if !defined(MK64F12_H_) */
bogdanm 82:6473597d706e 13416 /* MK64F12.h, eof. */