frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_RBLAB_NRF51822/nrf51.h@87:6213f644d804, 2014-07-25 (annotated)

Committer:
bogdanm
Date:
Fri Jul 25 09:46:51 2014 +0100
Revision:
87:6213f644d804
Release 87 of the mbed library



Main changes:



- error.h renamed to mbed_error.h to avoid name clashes

- upgraded to V7 of the nRF51822 soft-device 110

- New targets: HRM107

- Improved test infrastructure

- Bug fixes on various targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 87:6213f644d804 1 /* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
bogdanm 87:6213f644d804 2 *
bogdanm 87:6213f644d804 3 * The information contained herein is property of Nordic Semiconductor ASA.
bogdanm 87:6213f644d804 4 * Terms and conditions of usage are described in detail in NORDIC
bogdanm 87:6213f644d804 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
bogdanm 87:6213f644d804 6 *
bogdanm 87:6213f644d804 7 * Licensees are granted free, non-transferable use of the information. NO
bogdanm 87:6213f644d804 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
bogdanm 87:6213f644d804 9 * the file.
bogdanm 87:6213f644d804 10 *
bogdanm 87:6213f644d804 11 */
bogdanm 87:6213f644d804 12
bogdanm 87:6213f644d804 13
bogdanm 87:6213f644d804 14
bogdanm 87:6213f644d804 15 /** @addtogroup Nordic Semiconductor
bogdanm 87:6213f644d804 16 * @{
bogdanm 87:6213f644d804 17 */
bogdanm 87:6213f644d804 18
bogdanm 87:6213f644d804 19 /** @addtogroup nRF51
bogdanm 87:6213f644d804 20 * @{
bogdanm 87:6213f644d804 21 */
bogdanm 87:6213f644d804 22
bogdanm 87:6213f644d804 23 #ifndef NRF51_H
bogdanm 87:6213f644d804 24 #define NRF51_H
bogdanm 87:6213f644d804 25
bogdanm 87:6213f644d804 26 #ifdef __cplusplus
bogdanm 87:6213f644d804 27 extern "C" {
bogdanm 87:6213f644d804 28 #endif
bogdanm 87:6213f644d804 29
bogdanm 87:6213f644d804 30
bogdanm 87:6213f644d804 31 /* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm 87:6213f644d804 32
bogdanm 87:6213f644d804 33 typedef enum {
bogdanm 87:6213f644d804 34 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
bogdanm 87:6213f644d804 35 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 87:6213f644d804 36 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 87:6213f644d804 37 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 87:6213f644d804 38 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
bogdanm 87:6213f644d804 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
bogdanm 87:6213f644d804 40 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
bogdanm 87:6213f644d804 41 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
bogdanm 87:6213f644d804 42 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
bogdanm 87:6213f644d804 43 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
bogdanm 87:6213f644d804 44 RADIO_IRQn = 1, /*!< 1 RADIO */
bogdanm 87:6213f644d804 45 UART0_IRQn = 2, /*!< 2 UART0 */
bogdanm 87:6213f644d804 46 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
bogdanm 87:6213f644d804 47 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
bogdanm 87:6213f644d804 48 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
bogdanm 87:6213f644d804 49 ADC_IRQn = 7, /*!< 7 ADC */
bogdanm 87:6213f644d804 50 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
bogdanm 87:6213f644d804 51 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
bogdanm 87:6213f644d804 52 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
bogdanm 87:6213f644d804 53 RTC0_IRQn = 11, /*!< 11 RTC0 */
bogdanm 87:6213f644d804 54 TEMP_IRQn = 12, /*!< 12 TEMP */
bogdanm 87:6213f644d804 55 RNG_IRQn = 13, /*!< 13 RNG */
bogdanm 87:6213f644d804 56 ECB_IRQn = 14, /*!< 14 ECB */
bogdanm 87:6213f644d804 57 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
bogdanm 87:6213f644d804 58 WDT_IRQn = 16, /*!< 16 WDT */
bogdanm 87:6213f644d804 59 RTC1_IRQn = 17, /*!< 17 RTC1 */
bogdanm 87:6213f644d804 60 QDEC_IRQn = 18, /*!< 18 QDEC */
bogdanm 87:6213f644d804 61 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
bogdanm 87:6213f644d804 62 SWI0_IRQn = 20, /*!< 20 SWI0 */
bogdanm 87:6213f644d804 63 SWI1_IRQn = 21, /*!< 21 SWI1 */
bogdanm 87:6213f644d804 64 SWI2_IRQn = 22, /*!< 22 SWI2 */
bogdanm 87:6213f644d804 65 SWI3_IRQn = 23, /*!< 23 SWI3 */
bogdanm 87:6213f644d804 66 SWI4_IRQn = 24, /*!< 24 SWI4 */
bogdanm 87:6213f644d804 67 SWI5_IRQn = 25 /*!< 25 SWI5 */
bogdanm 87:6213f644d804 68 } IRQn_Type;
bogdanm 87:6213f644d804 69
bogdanm 87:6213f644d804 70
bogdanm 87:6213f644d804 71 /** @addtogroup Configuration_of_CMSIS
bogdanm 87:6213f644d804 72 * @{
bogdanm 87:6213f644d804 73 */
bogdanm 87:6213f644d804 74
bogdanm 87:6213f644d804 75
bogdanm 87:6213f644d804 76 /* ================================================================================ */
bogdanm 87:6213f644d804 77 /* ================ Processor and Core Peripheral Section ================ */
bogdanm 87:6213f644d804 78 /* ================================================================================ */
bogdanm 87:6213f644d804 79
bogdanm 87:6213f644d804 80 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
bogdanm 87:6213f644d804 81 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
bogdanm 87:6213f644d804 82 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 87:6213f644d804 83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 87:6213f644d804 84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 87:6213f644d804 85 /** @} */ /* End of group Configuration_of_CMSIS */
bogdanm 87:6213f644d804 86
bogdanm 87:6213f644d804 87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
bogdanm 87:6213f644d804 88 #include "system_nrf51822.h" /*!< nRF51 System */
bogdanm 87:6213f644d804 89
bogdanm 87:6213f644d804 90
bogdanm 87:6213f644d804 91 /* ================================================================================ */
bogdanm 87:6213f644d804 92 /* ================ Device Specific Peripheral Section ================ */
bogdanm 87:6213f644d804 93 /* ================================================================================ */
bogdanm 87:6213f644d804 94
bogdanm 87:6213f644d804 95
bogdanm 87:6213f644d804 96 /** @addtogroup Device_Peripheral_Registers
bogdanm 87:6213f644d804 97 * @{
bogdanm 87:6213f644d804 98 */
bogdanm 87:6213f644d804 99
bogdanm 87:6213f644d804 100
bogdanm 87:6213f644d804 101 /* ------------------- Start of section using anonymous unions ------------------ */
bogdanm 87:6213f644d804 102 #if defined(__CC_ARM)
bogdanm 87:6213f644d804 103 #pragma push
bogdanm 87:6213f644d804 104 #pragma anon_unions
bogdanm 87:6213f644d804 105 #elif defined(__ICCARM__)
bogdanm 87:6213f644d804 106 #pragma language=extended
bogdanm 87:6213f644d804 107 #elif defined(__GNUC__)
bogdanm 87:6213f644d804 108 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 109 #elif defined(__TMS470__)
bogdanm 87:6213f644d804 110 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 111 #elif defined(__TASKING__)
bogdanm 87:6213f644d804 112 #pragma warning 586
bogdanm 87:6213f644d804 113 #else
bogdanm 87:6213f644d804 114 #warning Not supported compiler type
bogdanm 87:6213f644d804 115 #endif
bogdanm 87:6213f644d804 116
bogdanm 87:6213f644d804 117
bogdanm 87:6213f644d804 118 typedef struct {
bogdanm 87:6213f644d804 119 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
bogdanm 87:6213f644d804 120 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
bogdanm 87:6213f644d804 121 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
bogdanm 87:6213f644d804 122 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
bogdanm 87:6213f644d804 123 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
bogdanm 87:6213f644d804 124 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
bogdanm 87:6213f644d804 125 } AMLI_RAMPRI_Type;
bogdanm 87:6213f644d804 126
bogdanm 87:6213f644d804 127 typedef struct {
bogdanm 87:6213f644d804 128 __O uint32_t EN; /*!< Enable channel group. */
bogdanm 87:6213f644d804 129 __O uint32_t DIS; /*!< Disable channel group. */
bogdanm 87:6213f644d804 130 } PPI_TASKS_CHG_Type;
bogdanm 87:6213f644d804 131
bogdanm 87:6213f644d804 132 typedef struct {
bogdanm 87:6213f644d804 133 __IO uint32_t EEP; /*!< Channel event end-point. */
bogdanm 87:6213f644d804 134 __IO uint32_t TEP; /*!< Channel task end-point. */
bogdanm 87:6213f644d804 135 } PPI_CH_Type;
bogdanm 87:6213f644d804 136
bogdanm 87:6213f644d804 137
bogdanm 87:6213f644d804 138 /* ================================================================================ */
bogdanm 87:6213f644d804 139 /* ================ POWER ================ */
bogdanm 87:6213f644d804 140 /* ================================================================================ */
bogdanm 87:6213f644d804 141
bogdanm 87:6213f644d804 142
bogdanm 87:6213f644d804 143 /**
bogdanm 87:6213f644d804 144 * @brief Power Control. (POWER)
bogdanm 87:6213f644d804 145 */
bogdanm 87:6213f644d804 146
bogdanm 87:6213f644d804 147 typedef struct { /*!< POWER Structure */
bogdanm 87:6213f644d804 148 __I uint32_t RESERVED0[30];
bogdanm 87:6213f644d804 149 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
bogdanm 87:6213f644d804 150 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
bogdanm 87:6213f644d804 151 __I uint32_t RESERVED1[34];
bogdanm 87:6213f644d804 152 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
bogdanm 87:6213f644d804 153 __I uint32_t RESERVED2[126];
bogdanm 87:6213f644d804 154 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 155 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 156 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 157 __IO uint32_t RESETREAS; /*!< Reset reason. */
bogdanm 87:6213f644d804 158 __I uint32_t RESERVED4[63];
bogdanm 87:6213f644d804 159 __O uint32_t SYSTEMOFF; /*!< System off register. */
bogdanm 87:6213f644d804 160 __I uint32_t RESERVED5[3];
bogdanm 87:6213f644d804 161 __IO uint32_t POFCON; /*!< Power failure configuration. */
bogdanm 87:6213f644d804 162 __I uint32_t RESERVED6[2];
bogdanm 87:6213f644d804 163 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
bogdanm 87:6213f644d804 164 register. */
bogdanm 87:6213f644d804 165 __I uint32_t RESERVED7;
bogdanm 87:6213f644d804 166 __IO uint32_t RAMON; /*!< Ram on/off. */
bogdanm 87:6213f644d804 167 __I uint32_t RESERVED8[7];
bogdanm 87:6213f644d804 168 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
bogdanm 87:6213f644d804 169 is a retained register. */
bogdanm 87:6213f644d804 170 __I uint32_t RESERVED9[12];
bogdanm 87:6213f644d804 171 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
bogdanm 87:6213f644d804 172 } NRF_POWER_Type;
bogdanm 87:6213f644d804 173
bogdanm 87:6213f644d804 174
bogdanm 87:6213f644d804 175 /* ================================================================================ */
bogdanm 87:6213f644d804 176 /* ================ CLOCK ================ */
bogdanm 87:6213f644d804 177 /* ================================================================================ */
bogdanm 87:6213f644d804 178
bogdanm 87:6213f644d804 179
bogdanm 87:6213f644d804 180 /**
bogdanm 87:6213f644d804 181 * @brief Clock control. (CLOCK)
bogdanm 87:6213f644d804 182 */
bogdanm 87:6213f644d804 183
bogdanm 87:6213f644d804 184 typedef struct { /*!< CLOCK Structure */
bogdanm 87:6213f644d804 185 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
bogdanm 87:6213f644d804 186 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
bogdanm 87:6213f644d804 187 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
bogdanm 87:6213f644d804 188 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
bogdanm 87:6213f644d804 189 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
bogdanm 87:6213f644d804 190 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
bogdanm 87:6213f644d804 191 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
bogdanm 87:6213f644d804 192 __I uint32_t RESERVED0[57];
bogdanm 87:6213f644d804 193 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
bogdanm 87:6213f644d804 194 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
bogdanm 87:6213f644d804 195 __I uint32_t RESERVED1;
bogdanm 87:6213f644d804 196 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
bogdanm 87:6213f644d804 197 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
bogdanm 87:6213f644d804 198 __I uint32_t RESERVED2[124];
bogdanm 87:6213f644d804 199 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 200 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 201 __I uint32_t RESERVED3[64];
bogdanm 87:6213f644d804 202 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
bogdanm 87:6213f644d804 203 __I uint32_t RESERVED4[2];
bogdanm 87:6213f644d804 204 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
bogdanm 87:6213f644d804 205 __I uint32_t RESERVED5[63];
bogdanm 87:6213f644d804 206 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
bogdanm 87:6213f644d804 207 __I uint32_t RESERVED6[7];
bogdanm 87:6213f644d804 208 __IO uint32_t CTIV; /*!< Calibration timer interval. */
bogdanm 87:6213f644d804 209 __I uint32_t RESERVED7[5];
bogdanm 87:6213f644d804 210 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
bogdanm 87:6213f644d804 211 } NRF_CLOCK_Type;
bogdanm 87:6213f644d804 212
bogdanm 87:6213f644d804 213
bogdanm 87:6213f644d804 214 /* ================================================================================ */
bogdanm 87:6213f644d804 215 /* ================ MPU ================ */
bogdanm 87:6213f644d804 216 /* ================================================================================ */
bogdanm 87:6213f644d804 217
bogdanm 87:6213f644d804 218
bogdanm 87:6213f644d804 219 /**
bogdanm 87:6213f644d804 220 * @brief Memory Protection Unit. (MPU)
bogdanm 87:6213f644d804 221 */
bogdanm 87:6213f644d804 222
bogdanm 87:6213f644d804 223 typedef struct { /*!< MPU Structure */
bogdanm 87:6213f644d804 224 __I uint32_t RESERVED0[330];
bogdanm 87:6213f644d804 225 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
bogdanm 87:6213f644d804 226 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
bogdanm 87:6213f644d804 227 __I uint32_t RESERVED1[52];
bogdanm 87:6213f644d804 228 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
bogdanm 87:6213f644d804 229 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
bogdanm 87:6213f644d804 230 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
bogdanm 87:6213f644d804 231 } NRF_MPU_Type;
bogdanm 87:6213f644d804 232
bogdanm 87:6213f644d804 233
bogdanm 87:6213f644d804 234 /* ================================================================================ */
bogdanm 87:6213f644d804 235 /* ================ PU ================ */
bogdanm 87:6213f644d804 236 /* ================================================================================ */
bogdanm 87:6213f644d804 237
bogdanm 87:6213f644d804 238
bogdanm 87:6213f644d804 239 /**
bogdanm 87:6213f644d804 240 * @brief Patch unit. (PU)
bogdanm 87:6213f644d804 241 */
bogdanm 87:6213f644d804 242
bogdanm 87:6213f644d804 243 typedef struct { /*!< PU Structure */
bogdanm 87:6213f644d804 244 __I uint32_t RESERVED0[448];
bogdanm 87:6213f644d804 245 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
bogdanm 87:6213f644d804 246 __I uint32_t RESERVED1[24];
bogdanm 87:6213f644d804 247 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
bogdanm 87:6213f644d804 248 __I uint32_t RESERVED2[24];
bogdanm 87:6213f644d804 249 __IO uint32_t PATCHEN; /*!< Patch enable register. */
bogdanm 87:6213f644d804 250 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
bogdanm 87:6213f644d804 251 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
bogdanm 87:6213f644d804 252 } NRF_PU_Type;
bogdanm 87:6213f644d804 253
bogdanm 87:6213f644d804 254
bogdanm 87:6213f644d804 255 /* ================================================================================ */
bogdanm 87:6213f644d804 256 /* ================ AMLI ================ */
bogdanm 87:6213f644d804 257 /* ================================================================================ */
bogdanm 87:6213f644d804 258
bogdanm 87:6213f644d804 259
bogdanm 87:6213f644d804 260 /**
bogdanm 87:6213f644d804 261 * @brief AHB Multi-Layer Interface. (AMLI)
bogdanm 87:6213f644d804 262 */
bogdanm 87:6213f644d804 263
bogdanm 87:6213f644d804 264 typedef struct { /*!< AMLI Structure */
bogdanm 87:6213f644d804 265 __I uint32_t RESERVED0[896];
bogdanm 87:6213f644d804 266 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
bogdanm 87:6213f644d804 267 } NRF_AMLI_Type;
bogdanm 87:6213f644d804 268
bogdanm 87:6213f644d804 269
bogdanm 87:6213f644d804 270 /* ================================================================================ */
bogdanm 87:6213f644d804 271 /* ================ RADIO ================ */
bogdanm 87:6213f644d804 272 /* ================================================================================ */
bogdanm 87:6213f644d804 273
bogdanm 87:6213f644d804 274
bogdanm 87:6213f644d804 275 /**
bogdanm 87:6213f644d804 276 * @brief The radio. (RADIO)
bogdanm 87:6213f644d804 277 */
bogdanm 87:6213f644d804 278
bogdanm 87:6213f644d804 279 typedef struct { /*!< RADIO Structure */
bogdanm 87:6213f644d804 280 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
bogdanm 87:6213f644d804 281 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
bogdanm 87:6213f644d804 282 __O uint32_t TASKS_START; /*!< Start radio. */
bogdanm 87:6213f644d804 283 __O uint32_t TASKS_STOP; /*!< Stop radio. */
bogdanm 87:6213f644d804 284 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
bogdanm 87:6213f644d804 285 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
bogdanm 87:6213f644d804 286 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
bogdanm 87:6213f644d804 287 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
bogdanm 87:6213f644d804 288 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
bogdanm 87:6213f644d804 289 __I uint32_t RESERVED0[55];
bogdanm 87:6213f644d804 290 __IO uint32_t EVENTS_READY; /*!< Ready event. */
bogdanm 87:6213f644d804 291 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
bogdanm 87:6213f644d804 292 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
bogdanm 87:6213f644d804 293 __IO uint32_t EVENTS_END; /*!< End event. */
bogdanm 87:6213f644d804 294 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
bogdanm 87:6213f644d804 295 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
bogdanm 87:6213f644d804 296 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
bogdanm 87:6213f644d804 297 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
bogdanm 87:6213f644d804 298 sample is ready for readout at the RSSISAMPLE register. */
bogdanm 87:6213f644d804 299 __I uint32_t RESERVED1[2];
bogdanm 87:6213f644d804 300 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
bogdanm 87:6213f644d804 301 __I uint32_t RESERVED2[53];
bogdanm 87:6213f644d804 302 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
bogdanm 87:6213f644d804 303 __I uint32_t RESERVED3[64];
bogdanm 87:6213f644d804 304 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 305 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 306 __I uint32_t RESERVED4[61];
bogdanm 87:6213f644d804 307 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
bogdanm 87:6213f644d804 308 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 309 __I uint32_t RXMATCH; /*!< Received address. */
bogdanm 87:6213f644d804 310 __I uint32_t RXCRC; /*!< Received CRC. */
bogdanm 87:6213f644d804 311 __IO uint32_t DAI; /*!< Device address match index. */
bogdanm 87:6213f644d804 312 __I uint32_t RESERVED6[60];
bogdanm 87:6213f644d804 313 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
bogdanm 87:6213f644d804 314 __IO uint32_t FREQUENCY; /*!< Frequency. */
bogdanm 87:6213f644d804 315 __IO uint32_t TXPOWER; /*!< Output power. */
bogdanm 87:6213f644d804 316 __IO uint32_t MODE; /*!< Data rate and modulation. */
bogdanm 87:6213f644d804 317 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
bogdanm 87:6213f644d804 318 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
bogdanm 87:6213f644d804 319 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
bogdanm 87:6213f644d804 320 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
bogdanm 87:6213f644d804 321 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
bogdanm 87:6213f644d804 322 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
bogdanm 87:6213f644d804 323 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
bogdanm 87:6213f644d804 324 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
bogdanm 87:6213f644d804 325 __IO uint32_t CRCCNF; /*!< CRC configuration. */
bogdanm 87:6213f644d804 326 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
bogdanm 87:6213f644d804 327 __IO uint32_t CRCINIT; /*!< CRC initial value. */
bogdanm 87:6213f644d804 328 __IO uint32_t TEST; /*!< Test features enable register. */
bogdanm 87:6213f644d804 329 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
bogdanm 87:6213f644d804 330 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
bogdanm 87:6213f644d804 331 __I uint32_t RESERVED7;
bogdanm 87:6213f644d804 332 __I uint32_t STATE; /*!< Current radio state. */
bogdanm 87:6213f644d804 333 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
bogdanm 87:6213f644d804 334 __I uint32_t RESERVED8[2];
bogdanm 87:6213f644d804 335 __IO uint32_t BCC; /*!< Bit counter compare. */
bogdanm 87:6213f644d804 336 __I uint32_t RESERVED9[39];
bogdanm 87:6213f644d804 337 __IO uint32_t DAB[8]; /*!< Device address base segment. */
bogdanm 87:6213f644d804 338 __IO uint32_t DAP[8]; /*!< Device address prefix. */
bogdanm 87:6213f644d804 339 __IO uint32_t DACNF; /*!< Device address match configuration. */
bogdanm 87:6213f644d804 340 __I uint32_t RESERVED10[56];
bogdanm 87:6213f644d804 341 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
bogdanm 87:6213f644d804 342 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
bogdanm 87:6213f644d804 343 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
bogdanm 87:6213f644d804 344 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
bogdanm 87:6213f644d804 345 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
bogdanm 87:6213f644d804 346 __I uint32_t RESERVED11[561];
bogdanm 87:6213f644d804 347 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 348 } NRF_RADIO_Type;
bogdanm 87:6213f644d804 349
bogdanm 87:6213f644d804 350
bogdanm 87:6213f644d804 351 /* ================================================================================ */
bogdanm 87:6213f644d804 352 /* ================ UART ================ */
bogdanm 87:6213f644d804 353 /* ================================================================================ */
bogdanm 87:6213f644d804 354
bogdanm 87:6213f644d804 355
bogdanm 87:6213f644d804 356 /**
bogdanm 87:6213f644d804 357 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
bogdanm 87:6213f644d804 358 */
bogdanm 87:6213f644d804 359
bogdanm 87:6213f644d804 360 typedef struct { /*!< UART Structure */
bogdanm 87:6213f644d804 361 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
bogdanm 87:6213f644d804 362 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
bogdanm 87:6213f644d804 363 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
bogdanm 87:6213f644d804 364 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
bogdanm 87:6213f644d804 365 __I uint32_t RESERVED0[3];
bogdanm 87:6213f644d804 366 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
bogdanm 87:6213f644d804 367 __I uint32_t RESERVED1[56];
bogdanm 87:6213f644d804 368 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
bogdanm 87:6213f644d804 369 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
bogdanm 87:6213f644d804 370 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
bogdanm 87:6213f644d804 371 __I uint32_t RESERVED2[4];
bogdanm 87:6213f644d804 372 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
bogdanm 87:6213f644d804 373 __I uint32_t RESERVED3;
bogdanm 87:6213f644d804 374 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
bogdanm 87:6213f644d804 375 __I uint32_t RESERVED4[7];
bogdanm 87:6213f644d804 376 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
bogdanm 87:6213f644d804 377 __I uint32_t RESERVED5[46];
bogdanm 87:6213f644d804 378 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
bogdanm 87:6213f644d804 379 __I uint32_t RESERVED6[64];
bogdanm 87:6213f644d804 380 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 381 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 382 __I uint32_t RESERVED7[93];
bogdanm 87:6213f644d804 383 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
bogdanm 87:6213f644d804 384 __I uint32_t RESERVED8[31];
bogdanm 87:6213f644d804 385 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
bogdanm 87:6213f644d804 386 __I uint32_t RESERVED9;
bogdanm 87:6213f644d804 387 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
bogdanm 87:6213f644d804 388 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
bogdanm 87:6213f644d804 389 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
bogdanm 87:6213f644d804 390 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
bogdanm 87:6213f644d804 391 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
bogdanm 87:6213f644d804 392 Once read the character is consummed. If read when no character
bogdanm 87:6213f644d804 393 available, the UART will stop working. */
bogdanm 87:6213f644d804 394 __O uint32_t TXD; /*!< TXD register. */
bogdanm 87:6213f644d804 395 __I uint32_t RESERVED10;
bogdanm 87:6213f644d804 396 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
bogdanm 87:6213f644d804 397 __I uint32_t RESERVED11[17];
bogdanm 87:6213f644d804 398 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
bogdanm 87:6213f644d804 399 __I uint32_t RESERVED12[675];
bogdanm 87:6213f644d804 400 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 401 } NRF_UART_Type;
bogdanm 87:6213f644d804 402
bogdanm 87:6213f644d804 403
bogdanm 87:6213f644d804 404 /* ================================================================================ */
bogdanm 87:6213f644d804 405 /* ================ SPI ================ */
bogdanm 87:6213f644d804 406 /* ================================================================================ */
bogdanm 87:6213f644d804 407
bogdanm 87:6213f644d804 408
bogdanm 87:6213f644d804 409 /**
bogdanm 87:6213f644d804 410 * @brief SPI master 0. (SPI)
bogdanm 87:6213f644d804 411 */
bogdanm 87:6213f644d804 412
bogdanm 87:6213f644d804 413 typedef struct { /*!< SPI Structure */
bogdanm 87:6213f644d804 414 __I uint32_t RESERVED0[66];
bogdanm 87:6213f644d804 415 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
bogdanm 87:6213f644d804 416 __I uint32_t RESERVED1[126];
bogdanm 87:6213f644d804 417 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 418 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 419 __I uint32_t RESERVED2[125];
bogdanm 87:6213f644d804 420 __IO uint32_t ENABLE; /*!< Enable SPI. */
bogdanm 87:6213f644d804 421 __I uint32_t RESERVED3;
bogdanm 87:6213f644d804 422 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
bogdanm 87:6213f644d804 423 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
bogdanm 87:6213f644d804 424 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
bogdanm 87:6213f644d804 425 __I uint32_t RESERVED4;
bogdanm 87:6213f644d804 426 __IO uint32_t RXD; /*!< RX data. */
bogdanm 87:6213f644d804 427 __IO uint32_t TXD; /*!< TX data. */
bogdanm 87:6213f644d804 428 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 429 __IO uint32_t FREQUENCY; /*!< SPI frequency */
bogdanm 87:6213f644d804 430 __I uint32_t RESERVED6[11];
bogdanm 87:6213f644d804 431 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 432 __I uint32_t RESERVED7[681];
bogdanm 87:6213f644d804 433 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 434 } NRF_SPI_Type;
bogdanm 87:6213f644d804 435
bogdanm 87:6213f644d804 436
bogdanm 87:6213f644d804 437 /* ================================================================================ */
bogdanm 87:6213f644d804 438 /* ================ TWI ================ */
bogdanm 87:6213f644d804 439 /* ================================================================================ */
bogdanm 87:6213f644d804 440
bogdanm 87:6213f644d804 441
bogdanm 87:6213f644d804 442 /**
bogdanm 87:6213f644d804 443 * @brief Two-wire interface master 0. (TWI)
bogdanm 87:6213f644d804 444 */
bogdanm 87:6213f644d804 445
bogdanm 87:6213f644d804 446 typedef struct { /*!< TWI Structure */
bogdanm 87:6213f644d804 447 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
bogdanm 87:6213f644d804 448 __I uint32_t RESERVED0;
bogdanm 87:6213f644d804 449 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
bogdanm 87:6213f644d804 450 __I uint32_t RESERVED1[2];
bogdanm 87:6213f644d804 451 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
bogdanm 87:6213f644d804 452 __I uint32_t RESERVED2;
bogdanm 87:6213f644d804 453 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
bogdanm 87:6213f644d804 454 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
bogdanm 87:6213f644d804 455 __I uint32_t RESERVED3[56];
bogdanm 87:6213f644d804 456 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
bogdanm 87:6213f644d804 457 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
bogdanm 87:6213f644d804 458 __I uint32_t RESERVED4[4];
bogdanm 87:6213f644d804 459 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
bogdanm 87:6213f644d804 460 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 461 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
bogdanm 87:6213f644d804 462 __I uint32_t RESERVED6[4];
bogdanm 87:6213f644d804 463 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
bogdanm 87:6213f644d804 464 __I uint32_t RESERVED7[49];
bogdanm 87:6213f644d804 465 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
bogdanm 87:6213f644d804 466 __I uint32_t RESERVED8[64];
bogdanm 87:6213f644d804 467 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 468 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 469 __I uint32_t RESERVED9[110];
bogdanm 87:6213f644d804 470 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
bogdanm 87:6213f644d804 471 __I uint32_t RESERVED10[14];
bogdanm 87:6213f644d804 472 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
bogdanm 87:6213f644d804 473 __I uint32_t RESERVED11;
bogdanm 87:6213f644d804 474 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
bogdanm 87:6213f644d804 475 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
bogdanm 87:6213f644d804 476 __I uint32_t RESERVED12[2];
bogdanm 87:6213f644d804 477 __IO uint32_t RXD; /*!< RX data register. */
bogdanm 87:6213f644d804 478 __IO uint32_t TXD; /*!< TX data register. */
bogdanm 87:6213f644d804 479 __I uint32_t RESERVED13;
bogdanm 87:6213f644d804 480 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
bogdanm 87:6213f644d804 481 __I uint32_t RESERVED14[24];
bogdanm 87:6213f644d804 482 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
bogdanm 87:6213f644d804 483 __I uint32_t RESERVED15[668];
bogdanm 87:6213f644d804 484 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 485 } NRF_TWI_Type;
bogdanm 87:6213f644d804 486
bogdanm 87:6213f644d804 487
bogdanm 87:6213f644d804 488 /* ================================================================================ */
bogdanm 87:6213f644d804 489 /* ================ SPIS ================ */
bogdanm 87:6213f644d804 490 /* ================================================================================ */
bogdanm 87:6213f644d804 491
bogdanm 87:6213f644d804 492
bogdanm 87:6213f644d804 493 /**
bogdanm 87:6213f644d804 494 * @brief SPI slave 1. (SPIS)
bogdanm 87:6213f644d804 495 */
bogdanm 87:6213f644d804 496
bogdanm 87:6213f644d804 497 typedef struct { /*!< SPIS Structure */
bogdanm 87:6213f644d804 498 __I uint32_t RESERVED0[9];
bogdanm 87:6213f644d804 499 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
bogdanm 87:6213f644d804 500 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
bogdanm 87:6213f644d804 501 __I uint32_t RESERVED1[54];
bogdanm 87:6213f644d804 502 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
bogdanm 87:6213f644d804 503 __I uint32_t RESERVED2[8];
bogdanm 87:6213f644d804 504 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
bogdanm 87:6213f644d804 505 __I uint32_t RESERVED3[53];
bogdanm 87:6213f644d804 506 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
bogdanm 87:6213f644d804 507 __I uint32_t RESERVED4[64];
bogdanm 87:6213f644d804 508 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 509 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 510 __I uint32_t RESERVED5[61];
bogdanm 87:6213f644d804 511 __I uint32_t SEMSTAT; /*!< Semaphore status. */
bogdanm 87:6213f644d804 512 __I uint32_t RESERVED6[15];
bogdanm 87:6213f644d804 513 __IO uint32_t STATUS; /*!< Status from last transaction. */
bogdanm 87:6213f644d804 514 __I uint32_t RESERVED7[47];
bogdanm 87:6213f644d804 515 __IO uint32_t ENABLE; /*!< Enable SPIS. */
bogdanm 87:6213f644d804 516 __I uint32_t RESERVED8;
bogdanm 87:6213f644d804 517 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
bogdanm 87:6213f644d804 518 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
bogdanm 87:6213f644d804 519 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
bogdanm 87:6213f644d804 520 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
bogdanm 87:6213f644d804 521 __I uint32_t RESERVED9[7];
bogdanm 87:6213f644d804 522 __IO uint32_t RXDPTR; /*!< RX data pointer. */
bogdanm 87:6213f644d804 523 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
bogdanm 87:6213f644d804 524 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
bogdanm 87:6213f644d804 525 __I uint32_t RESERVED10;
bogdanm 87:6213f644d804 526 __IO uint32_t TXDPTR; /*!< TX data pointer. */
bogdanm 87:6213f644d804 527 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
bogdanm 87:6213f644d804 528 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
bogdanm 87:6213f644d804 529 __I uint32_t RESERVED11;
bogdanm 87:6213f644d804 530 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 531 __I uint32_t RESERVED12;
bogdanm 87:6213f644d804 532 __IO uint32_t DEF; /*!< Default character. */
bogdanm 87:6213f644d804 533 __I uint32_t RESERVED13[24];
bogdanm 87:6213f644d804 534 __IO uint32_t ORC; /*!< Over-read character. */
bogdanm 87:6213f644d804 535 __I uint32_t RESERVED14[654];
bogdanm 87:6213f644d804 536 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 537 } NRF_SPIS_Type;
bogdanm 87:6213f644d804 538
bogdanm 87:6213f644d804 539
bogdanm 87:6213f644d804 540 /* ================================================================================ */
bogdanm 87:6213f644d804 541 /* ================ GPIOTE ================ */
bogdanm 87:6213f644d804 542 /* ================================================================================ */
bogdanm 87:6213f644d804 543
bogdanm 87:6213f644d804 544
bogdanm 87:6213f644d804 545 /**
bogdanm 87:6213f644d804 546 * @brief GPIO tasks and events. (GPIOTE)
bogdanm 87:6213f644d804 547 */
bogdanm 87:6213f644d804 548
bogdanm 87:6213f644d804 549 typedef struct { /*!< GPIOTE Structure */
bogdanm 87:6213f644d804 550 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
bogdanm 87:6213f644d804 551 __I uint32_t RESERVED0[60];
bogdanm 87:6213f644d804 552 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
bogdanm 87:6213f644d804 553 __I uint32_t RESERVED1[27];
bogdanm 87:6213f644d804 554 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
bogdanm 87:6213f644d804 555 __I uint32_t RESERVED2[97];
bogdanm 87:6213f644d804 556 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 557 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 558 __I uint32_t RESERVED3[129];
bogdanm 87:6213f644d804 559 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
bogdanm 87:6213f644d804 560 __I uint32_t RESERVED4[695];
bogdanm 87:6213f644d804 561 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 562 } NRF_GPIOTE_Type;
bogdanm 87:6213f644d804 563
bogdanm 87:6213f644d804 564
bogdanm 87:6213f644d804 565 /* ================================================================================ */
bogdanm 87:6213f644d804 566 /* ================ ADC ================ */
bogdanm 87:6213f644d804 567 /* ================================================================================ */
bogdanm 87:6213f644d804 568
bogdanm 87:6213f644d804 569
bogdanm 87:6213f644d804 570 /**
bogdanm 87:6213f644d804 571 * @brief Analog to digital converter. (ADC)
bogdanm 87:6213f644d804 572 */
bogdanm 87:6213f644d804 573
bogdanm 87:6213f644d804 574 typedef struct { /*!< ADC Structure */
bogdanm 87:6213f644d804 575 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
bogdanm 87:6213f644d804 576 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
bogdanm 87:6213f644d804 577 __I uint32_t RESERVED0[62];
bogdanm 87:6213f644d804 578 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
bogdanm 87:6213f644d804 579 __I uint32_t RESERVED1[128];
bogdanm 87:6213f644d804 580 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 581 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 582 __I uint32_t RESERVED2[61];
bogdanm 87:6213f644d804 583 __I uint32_t BUSY; /*!< ADC busy register. */
bogdanm 87:6213f644d804 584 __I uint32_t RESERVED3[63];
bogdanm 87:6213f644d804 585 __IO uint32_t ENABLE; /*!< ADC enable. */
bogdanm 87:6213f644d804 586 __IO uint32_t CONFIG; /*!< ADC configuration register. */
bogdanm 87:6213f644d804 587 __I uint32_t RESULT; /*!< Result of ADC conversion. */
bogdanm 87:6213f644d804 588 __I uint32_t RESERVED4[700];
bogdanm 87:6213f644d804 589 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 590 } NRF_ADC_Type;
bogdanm 87:6213f644d804 591
bogdanm 87:6213f644d804 592
bogdanm 87:6213f644d804 593 /* ================================================================================ */
bogdanm 87:6213f644d804 594 /* ================ TIMER ================ */
bogdanm 87:6213f644d804 595 /* ================================================================================ */
bogdanm 87:6213f644d804 596
bogdanm 87:6213f644d804 597
bogdanm 87:6213f644d804 598 /**
bogdanm 87:6213f644d804 599 * @brief Timer 0. (TIMER)
bogdanm 87:6213f644d804 600 */
bogdanm 87:6213f644d804 601
bogdanm 87:6213f644d804 602 typedef struct { /*!< TIMER Structure */
bogdanm 87:6213f644d804 603 __O uint32_t TASKS_START; /*!< Start Timer. */
bogdanm 87:6213f644d804 604 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
bogdanm 87:6213f644d804 605 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
bogdanm 87:6213f644d804 606 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
bogdanm 87:6213f644d804 607 __I uint32_t RESERVED0[12];
bogdanm 87:6213f644d804 608 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
bogdanm 87:6213f644d804 609 __I uint32_t RESERVED1[60];
bogdanm 87:6213f644d804 610 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
bogdanm 87:6213f644d804 611 __I uint32_t RESERVED2[44];
bogdanm 87:6213f644d804 612 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
bogdanm 87:6213f644d804 613 __I uint32_t RESERVED3[64];
bogdanm 87:6213f644d804 614 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 615 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 616 __I uint32_t RESERVED4[126];
bogdanm 87:6213f644d804 617 __IO uint32_t MODE; /*!< Timer Mode selection. */
bogdanm 87:6213f644d804 618 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
bogdanm 87:6213f644d804 619 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 620 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
bogdanm 87:6213f644d804 621 clock frequency is divided by 2^SCALE. */
bogdanm 87:6213f644d804 622 __I uint32_t RESERVED6[11];
bogdanm 87:6213f644d804 623 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
bogdanm 87:6213f644d804 624 __I uint32_t RESERVED7[683];
bogdanm 87:6213f644d804 625 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 626 } NRF_TIMER_Type;
bogdanm 87:6213f644d804 627
bogdanm 87:6213f644d804 628
bogdanm 87:6213f644d804 629 /* ================================================================================ */
bogdanm 87:6213f644d804 630 /* ================ RTC ================ */
bogdanm 87:6213f644d804 631 /* ================================================================================ */
bogdanm 87:6213f644d804 632
bogdanm 87:6213f644d804 633
bogdanm 87:6213f644d804 634 /**
bogdanm 87:6213f644d804 635 * @brief Real time counter 0. (RTC)
bogdanm 87:6213f644d804 636 */
bogdanm 87:6213f644d804 637
bogdanm 87:6213f644d804 638 typedef struct { /*!< RTC Structure */
bogdanm 87:6213f644d804 639 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
bogdanm 87:6213f644d804 640 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
bogdanm 87:6213f644d804 641 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
bogdanm 87:6213f644d804 642 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
bogdanm 87:6213f644d804 643 __I uint32_t RESERVED0[60];
bogdanm 87:6213f644d804 644 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
bogdanm 87:6213f644d804 645 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
bogdanm 87:6213f644d804 646 __I uint32_t RESERVED1[14];
bogdanm 87:6213f644d804 647 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
bogdanm 87:6213f644d804 648 __I uint32_t RESERVED2[109];
bogdanm 87:6213f644d804 649 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 650 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 651 __I uint32_t RESERVED3[13];
bogdanm 87:6213f644d804 652 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
bogdanm 87:6213f644d804 653 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
bogdanm 87:6213f644d804 654 the value of EVTEN. */
bogdanm 87:6213f644d804 655 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
bogdanm 87:6213f644d804 656 gives the value of EVTEN. */
bogdanm 87:6213f644d804 657 __I uint32_t RESERVED4[110];
bogdanm 87:6213f644d804 658 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
bogdanm 87:6213f644d804 659 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
bogdanm 87:6213f644d804 660 Must be written when RTC is STOPed. */
bogdanm 87:6213f644d804 661 __I uint32_t RESERVED5[13];
bogdanm 87:6213f644d804 662 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
bogdanm 87:6213f644d804 663 __I uint32_t RESERVED6[683];
bogdanm 87:6213f644d804 664 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 665 } NRF_RTC_Type;
bogdanm 87:6213f644d804 666
bogdanm 87:6213f644d804 667
bogdanm 87:6213f644d804 668 /* ================================================================================ */
bogdanm 87:6213f644d804 669 /* ================ TEMP ================ */
bogdanm 87:6213f644d804 670 /* ================================================================================ */
bogdanm 87:6213f644d804 671
bogdanm 87:6213f644d804 672
bogdanm 87:6213f644d804 673 /**
bogdanm 87:6213f644d804 674 * @brief Temperature Sensor. (TEMP)
bogdanm 87:6213f644d804 675 */
bogdanm 87:6213f644d804 676
bogdanm 87:6213f644d804 677 typedef struct { /*!< TEMP Structure */
bogdanm 87:6213f644d804 678 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
bogdanm 87:6213f644d804 679 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
bogdanm 87:6213f644d804 680 __I uint32_t RESERVED0[62];
bogdanm 87:6213f644d804 681 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
bogdanm 87:6213f644d804 682 __I uint32_t RESERVED1[128];
bogdanm 87:6213f644d804 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 685 __I uint32_t RESERVED2[127];
bogdanm 87:6213f644d804 686 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
bogdanm 87:6213f644d804 687 __I uint32_t RESERVED3[700];
bogdanm 87:6213f644d804 688 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 689 } NRF_TEMP_Type;
bogdanm 87:6213f644d804 690
bogdanm 87:6213f644d804 691
bogdanm 87:6213f644d804 692 /* ================================================================================ */
bogdanm 87:6213f644d804 693 /* ================ RNG ================ */
bogdanm 87:6213f644d804 694 /* ================================================================================ */
bogdanm 87:6213f644d804 695
bogdanm 87:6213f644d804 696
bogdanm 87:6213f644d804 697 /**
bogdanm 87:6213f644d804 698 * @brief Random Number Generator. (RNG)
bogdanm 87:6213f644d804 699 */
bogdanm 87:6213f644d804 700
bogdanm 87:6213f644d804 701 typedef struct { /*!< RNG Structure */
bogdanm 87:6213f644d804 702 __O uint32_t TASKS_START; /*!< Start the random number generator. */
bogdanm 87:6213f644d804 703 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
bogdanm 87:6213f644d804 704 __I uint32_t RESERVED0[62];
bogdanm 87:6213f644d804 705 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
bogdanm 87:6213f644d804 706 __I uint32_t RESERVED1[63];
bogdanm 87:6213f644d804 707 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
bogdanm 87:6213f644d804 708 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 709 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
bogdanm 87:6213f644d804 710 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
bogdanm 87:6213f644d804 711 __I uint32_t RESERVED3[126];
bogdanm 87:6213f644d804 712 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 713 __I uint32_t VALUE; /*!< RNG random number. */
bogdanm 87:6213f644d804 714 __I uint32_t RESERVED4[700];
bogdanm 87:6213f644d804 715 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 716 } NRF_RNG_Type;
bogdanm 87:6213f644d804 717
bogdanm 87:6213f644d804 718
bogdanm 87:6213f644d804 719 /* ================================================================================ */
bogdanm 87:6213f644d804 720 /* ================ ECB ================ */
bogdanm 87:6213f644d804 721 /* ================================================================================ */
bogdanm 87:6213f644d804 722
bogdanm 87:6213f644d804 723
bogdanm 87:6213f644d804 724 /**
bogdanm 87:6213f644d804 725 * @brief AES ECB Mode Encryption. (ECB)
bogdanm 87:6213f644d804 726 */
bogdanm 87:6213f644d804 727
bogdanm 87:6213f644d804 728 typedef struct { /*!< ECB Structure */
bogdanm 87:6213f644d804 729 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
bogdanm 87:6213f644d804 730 will not initiate a new encryption and the ERRORECB event will
bogdanm 87:6213f644d804 731 be triggered. */
bogdanm 87:6213f644d804 732 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
bogdanm 87:6213f644d804 733 this will will trigger the ERRORECB event. */
bogdanm 87:6213f644d804 734 __I uint32_t RESERVED0[62];
bogdanm 87:6213f644d804 735 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
bogdanm 87:6213f644d804 736 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
bogdanm 87:6213f644d804 737 error. */
bogdanm 87:6213f644d804 738 __I uint32_t RESERVED1[127];
bogdanm 87:6213f644d804 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 741 __I uint32_t RESERVED2[126];
bogdanm 87:6213f644d804 742 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
bogdanm 87:6213f644d804 743 __I uint32_t RESERVED3[701];
bogdanm 87:6213f644d804 744 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 745 } NRF_ECB_Type;
bogdanm 87:6213f644d804 746
bogdanm 87:6213f644d804 747
bogdanm 87:6213f644d804 748 /* ================================================================================ */
bogdanm 87:6213f644d804 749 /* ================ AAR ================ */
bogdanm 87:6213f644d804 750 /* ================================================================================ */
bogdanm 87:6213f644d804 751
bogdanm 87:6213f644d804 752
bogdanm 87:6213f644d804 753 /**
bogdanm 87:6213f644d804 754 * @brief Accelerated Address Resolver. (AAR)
bogdanm 87:6213f644d804 755 */
bogdanm 87:6213f644d804 756
bogdanm 87:6213f644d804 757 typedef struct { /*!< AAR Structure */
bogdanm 87:6213f644d804 758 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
bogdanm 87:6213f644d804 759 data structure. */
bogdanm 87:6213f644d804 760 __I uint32_t RESERVED0;
bogdanm 87:6213f644d804 761 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
bogdanm 87:6213f644d804 762 __I uint32_t RESERVED1[61];
bogdanm 87:6213f644d804 763 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
bogdanm 87:6213f644d804 764 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
bogdanm 87:6213f644d804 765 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
bogdanm 87:6213f644d804 766 __I uint32_t RESERVED2[126];
bogdanm 87:6213f644d804 767 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 768 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 769 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 770 __I uint32_t STATUS; /*!< Resolution status. */
bogdanm 87:6213f644d804 771 __I uint32_t RESERVED4[63];
bogdanm 87:6213f644d804 772 __IO uint32_t ENABLE; /*!< Enable AAR. */
bogdanm 87:6213f644d804 773 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
bogdanm 87:6213f644d804 774 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
bogdanm 87:6213f644d804 775 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 776 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
bogdanm 87:6213f644d804 777 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
bogdanm 87:6213f644d804 778 resolution. A minimum of 3 bytes must be reserved. */
bogdanm 87:6213f644d804 779 __I uint32_t RESERVED6[697];
bogdanm 87:6213f644d804 780 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 781 } NRF_AAR_Type;
bogdanm 87:6213f644d804 782
bogdanm 87:6213f644d804 783
bogdanm 87:6213f644d804 784 /* ================================================================================ */
bogdanm 87:6213f644d804 785 /* ================ CCM ================ */
bogdanm 87:6213f644d804 786 /* ================================================================================ */
bogdanm 87:6213f644d804 787
bogdanm 87:6213f644d804 788
bogdanm 87:6213f644d804 789 /**
bogdanm 87:6213f644d804 790 * @brief AES CCM Mode Encryption. (CCM)
bogdanm 87:6213f644d804 791 */
bogdanm 87:6213f644d804 792
bogdanm 87:6213f644d804 793 typedef struct { /*!< CCM Structure */
bogdanm 87:6213f644d804 794 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
bogdanm 87:6213f644d804 795 itself when completed. */
bogdanm 87:6213f644d804 796 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
bogdanm 87:6213f644d804 797 completed. */
bogdanm 87:6213f644d804 798 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
bogdanm 87:6213f644d804 799 __I uint32_t RESERVED0[61];
bogdanm 87:6213f644d804 800 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
bogdanm 87:6213f644d804 801 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
bogdanm 87:6213f644d804 802 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
bogdanm 87:6213f644d804 803 __I uint32_t RESERVED1[61];
bogdanm 87:6213f644d804 804 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
bogdanm 87:6213f644d804 805 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 806 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 807 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 808 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 809 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
bogdanm 87:6213f644d804 810 __I uint32_t RESERVED4[63];
bogdanm 87:6213f644d804 811 __IO uint32_t ENABLE; /*!< CCM enable. */
bogdanm 87:6213f644d804 812 __IO uint32_t MODE; /*!< Operation mode. */
bogdanm 87:6213f644d804 813 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
bogdanm 87:6213f644d804 814 __IO uint32_t INPTR; /*!< Pointer to input packet. */
bogdanm 87:6213f644d804 815 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
bogdanm 87:6213f644d804 816 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
bogdanm 87:6213f644d804 817 resolution. A minimum of 43 bytes must be reserved. */
bogdanm 87:6213f644d804 818 __I uint32_t RESERVED5[697];
bogdanm 87:6213f644d804 819 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 820 } NRF_CCM_Type;
bogdanm 87:6213f644d804 821
bogdanm 87:6213f644d804 822
bogdanm 87:6213f644d804 823 /* ================================================================================ */
bogdanm 87:6213f644d804 824 /* ================ WDT ================ */
bogdanm 87:6213f644d804 825 /* ================================================================================ */
bogdanm 87:6213f644d804 826
bogdanm 87:6213f644d804 827
bogdanm 87:6213f644d804 828 /**
bogdanm 87:6213f644d804 829 * @brief Watchdog Timer. (WDT)
bogdanm 87:6213f644d804 830 */
bogdanm 87:6213f644d804 831
bogdanm 87:6213f644d804 832 typedef struct { /*!< WDT Structure */
bogdanm 87:6213f644d804 833 __O uint32_t TASKS_START; /*!< Start the watchdog. */
bogdanm 87:6213f644d804 834 __I uint32_t RESERVED0[63];
bogdanm 87:6213f644d804 835 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
bogdanm 87:6213f644d804 836 __I uint32_t RESERVED1[128];
bogdanm 87:6213f644d804 837 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 838 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 839 __I uint32_t RESERVED2[61];
bogdanm 87:6213f644d804 840 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
bogdanm 87:6213f644d804 841 __I uint32_t REQSTATUS; /*!< Request status. */
bogdanm 87:6213f644d804 842 __I uint32_t RESERVED3[63];
bogdanm 87:6213f644d804 843 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
bogdanm 87:6213f644d804 844 __IO uint32_t RREN; /*!< Reload request enable. */
bogdanm 87:6213f644d804 845 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 846 __I uint32_t RESERVED4[60];
bogdanm 87:6213f644d804 847 __O uint32_t RR[8]; /*!< Reload requests registers. */
bogdanm 87:6213f644d804 848 __I uint32_t RESERVED5[631];
bogdanm 87:6213f644d804 849 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 850 } NRF_WDT_Type;
bogdanm 87:6213f644d804 851
bogdanm 87:6213f644d804 852
bogdanm 87:6213f644d804 853 /* ================================================================================ */
bogdanm 87:6213f644d804 854 /* ================ QDEC ================ */
bogdanm 87:6213f644d804 855 /* ================================================================================ */
bogdanm 87:6213f644d804 856
bogdanm 87:6213f644d804 857
bogdanm 87:6213f644d804 858 /**
bogdanm 87:6213f644d804 859 * @brief Rotary decoder. (QDEC)
bogdanm 87:6213f644d804 860 */
bogdanm 87:6213f644d804 861
bogdanm 87:6213f644d804 862 typedef struct { /*!< QDEC Structure */
bogdanm 87:6213f644d804 863 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
bogdanm 87:6213f644d804 864 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
bogdanm 87:6213f644d804 865 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
bogdanm 87:6213f644d804 866 and clears the ACC registers. */
bogdanm 87:6213f644d804 867 __I uint32_t RESERVED0[61];
bogdanm 87:6213f644d804 868 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
bogdanm 87:6213f644d804 869 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
bogdanm 87:6213f644d804 870 ACC register different than zero. */
bogdanm 87:6213f644d804 871 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
bogdanm 87:6213f644d804 872 __I uint32_t RESERVED1[61];
bogdanm 87:6213f644d804 873 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
bogdanm 87:6213f644d804 874 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 877 __I uint32_t RESERVED3[125];
bogdanm 87:6213f644d804 878 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
bogdanm 87:6213f644d804 879 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
bogdanm 87:6213f644d804 880 __IO uint32_t SAMPLEPER; /*!< Sample period. */
bogdanm 87:6213f644d804 881 __I int32_t SAMPLE; /*!< Motion sample value. */
bogdanm 87:6213f644d804 882 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
bogdanm 87:6213f644d804 883 __I int32_t ACC; /*!< Accumulated valid transitions register. */
bogdanm 87:6213f644d804 884 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
bogdanm 87:6213f644d804 885 task. */
bogdanm 87:6213f644d804 886 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
bogdanm 87:6213f644d804 887 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
bogdanm 87:6213f644d804 888 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
bogdanm 87:6213f644d804 889 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
bogdanm 87:6213f644d804 890 __I uint32_t RESERVED4[5];
bogdanm 87:6213f644d804 891 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
bogdanm 87:6213f644d804 892 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
bogdanm 87:6213f644d804 893 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
bogdanm 87:6213f644d804 894 task. */
bogdanm 87:6213f644d804 895 __I uint32_t RESERVED5[684];
bogdanm 87:6213f644d804 896 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 897 } NRF_QDEC_Type;
bogdanm 87:6213f644d804 898
bogdanm 87:6213f644d804 899
bogdanm 87:6213f644d804 900 /* ================================================================================ */
bogdanm 87:6213f644d804 901 /* ================ LPCOMP ================ */
bogdanm 87:6213f644d804 902 /* ================================================================================ */
bogdanm 87:6213f644d804 903
bogdanm 87:6213f644d804 904
bogdanm 87:6213f644d804 905 /**
bogdanm 87:6213f644d804 906 * @brief Wakeup Comparator. (LPCOMP)
bogdanm 87:6213f644d804 907 */
bogdanm 87:6213f644d804 908
bogdanm 87:6213f644d804 909 typedef struct { /*!< LPCOMP Structure */
bogdanm 87:6213f644d804 910 __O uint32_t TASKS_START; /*!< Start the comparator. */
bogdanm 87:6213f644d804 911 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
bogdanm 87:6213f644d804 912 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
bogdanm 87:6213f644d804 913 __I uint32_t RESERVED0[61];
bogdanm 87:6213f644d804 914 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
bogdanm 87:6213f644d804 915 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
bogdanm 87:6213f644d804 916 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
bogdanm 87:6213f644d804 917 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
bogdanm 87:6213f644d804 918 __I uint32_t RESERVED1[60];
bogdanm 87:6213f644d804 919 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
bogdanm 87:6213f644d804 920 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 921 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 922 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 923 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 924 __I uint32_t RESULT; /*!< Result of last compare. */
bogdanm 87:6213f644d804 925 __I uint32_t RESERVED4[63];
bogdanm 87:6213f644d804 926 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
bogdanm 87:6213f644d804 927 __IO uint32_t PSEL; /*!< Input pin select. */
bogdanm 87:6213f644d804 928 __IO uint32_t REFSEL; /*!< Reference select. */
bogdanm 87:6213f644d804 929 __IO uint32_t EXTREFSEL; /*!< External reference select. */
bogdanm 87:6213f644d804 930 __I uint32_t RESERVED5[4];
bogdanm 87:6213f644d804 931 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
bogdanm 87:6213f644d804 932 __I uint32_t RESERVED6[694];
bogdanm 87:6213f644d804 933 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 934 } NRF_LPCOMP_Type;
bogdanm 87:6213f644d804 935
bogdanm 87:6213f644d804 936
bogdanm 87:6213f644d804 937 /* ================================================================================ */
bogdanm 87:6213f644d804 938 /* ================ COMP ================ */
bogdanm 87:6213f644d804 939 /* ================================================================================ */
bogdanm 87:6213f644d804 940
bogdanm 87:6213f644d804 941
bogdanm 87:6213f644d804 942 /**
bogdanm 87:6213f644d804 943 * @brief Comparator. (COMP)
bogdanm 87:6213f644d804 944 */
bogdanm 87:6213f644d804 945
bogdanm 87:6213f644d804 946 typedef struct { /*!< COMP Structure */
bogdanm 87:6213f644d804 947 __O uint32_t TASKS_START; /*!< Start the comparator. */
bogdanm 87:6213f644d804 948 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
bogdanm 87:6213f644d804 949 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
bogdanm 87:6213f644d804 950 __I uint32_t RESERVED0[61];
bogdanm 87:6213f644d804 951 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
bogdanm 87:6213f644d804 952 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
bogdanm 87:6213f644d804 953 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
bogdanm 87:6213f644d804 954 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
bogdanm 87:6213f644d804 955 __I uint32_t RESERVED1[60];
bogdanm 87:6213f644d804 956 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
bogdanm 87:6213f644d804 957 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 958 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 959 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 960 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 961 __I uint32_t RESULT; /*!< Compare result. */
bogdanm 87:6213f644d804 962 __I uint32_t RESERVED4[63];
bogdanm 87:6213f644d804 963 __IO uint32_t ENABLE; /*!< Enable the COMP. */
bogdanm 87:6213f644d804 964 __IO uint32_t PSEL; /*!< Input pin select. */
bogdanm 87:6213f644d804 965 __IO uint32_t REFSEL; /*!< Reference select. */
bogdanm 87:6213f644d804 966 __IO uint32_t EXTREFSEL; /*!< External reference select. */
bogdanm 87:6213f644d804 967 __I uint32_t RESERVED5[8];
bogdanm 87:6213f644d804 968 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
bogdanm 87:6213f644d804 969 __IO uint32_t MODE; /*!< Mode configuration. */
bogdanm 87:6213f644d804 970 __I uint32_t RESERVED6[689];
bogdanm 87:6213f644d804 971 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 972 } NRF_COMP_Type;
bogdanm 87:6213f644d804 973
bogdanm 87:6213f644d804 974
bogdanm 87:6213f644d804 975 /* ================================================================================ */
bogdanm 87:6213f644d804 976 /* ================ SWI ================ */
bogdanm 87:6213f644d804 977 /* ================================================================================ */
bogdanm 87:6213f644d804 978
bogdanm 87:6213f644d804 979
bogdanm 87:6213f644d804 980 /**
bogdanm 87:6213f644d804 981 * @brief SW Interrupts. (SWI)
bogdanm 87:6213f644d804 982 */
bogdanm 87:6213f644d804 983
bogdanm 87:6213f644d804 984 typedef struct { /*!< SWI Structure */
bogdanm 87:6213f644d804 985 __I uint32_t UNUSED; /*!< Unused. */
bogdanm 87:6213f644d804 986 } NRF_SWI_Type;
bogdanm 87:6213f644d804 987
bogdanm 87:6213f644d804 988
bogdanm 87:6213f644d804 989 /* ================================================================================ */
bogdanm 87:6213f644d804 990 /* ================ NVMC ================ */
bogdanm 87:6213f644d804 991 /* ================================================================================ */
bogdanm 87:6213f644d804 992
bogdanm 87:6213f644d804 993
bogdanm 87:6213f644d804 994 /**
bogdanm 87:6213f644d804 995 * @brief Non Volatile Memory Controller. (NVMC)
bogdanm 87:6213f644d804 996 */
bogdanm 87:6213f644d804 997
bogdanm 87:6213f644d804 998 typedef struct { /*!< NVMC Structure */
bogdanm 87:6213f644d804 999 __I uint32_t RESERVED0[256];
bogdanm 87:6213f644d804 1000 __I uint32_t READY; /*!< Ready flag. */
bogdanm 87:6213f644d804 1001 __I uint32_t RESERVED1[64];
bogdanm 87:6213f644d804 1002 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 1003 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
bogdanm 87:6213f644d804 1004 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
bogdanm 87:6213f644d804 1005 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
bogdanm 87:6213f644d804 1006 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
bogdanm 87:6213f644d804 1007 } NRF_NVMC_Type;
bogdanm 87:6213f644d804 1008
bogdanm 87:6213f644d804 1009
bogdanm 87:6213f644d804 1010 /* ================================================================================ */
bogdanm 87:6213f644d804 1011 /* ================ PPI ================ */
bogdanm 87:6213f644d804 1012 /* ================================================================================ */
bogdanm 87:6213f644d804 1013
bogdanm 87:6213f644d804 1014
bogdanm 87:6213f644d804 1015 /**
bogdanm 87:6213f644d804 1016 * @brief PPI controller. (PPI)
bogdanm 87:6213f644d804 1017 */
bogdanm 87:6213f644d804 1018
bogdanm 87:6213f644d804 1019 typedef struct { /*!< PPI Structure */
bogdanm 87:6213f644d804 1020 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
bogdanm 87:6213f644d804 1021 __I uint32_t RESERVED0[312];
bogdanm 87:6213f644d804 1022 __IO uint32_t CHEN; /*!< Channel enable. */
bogdanm 87:6213f644d804 1023 __IO uint32_t CHENSET; /*!< Channel enable set. */
bogdanm 87:6213f644d804 1024 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
bogdanm 87:6213f644d804 1025 __I uint32_t RESERVED1;
bogdanm 87:6213f644d804 1026 PPI_CH_Type CH[16]; /*!< PPI Channel. */
bogdanm 87:6213f644d804 1027 __I uint32_t RESERVED2[156];
bogdanm 87:6213f644d804 1028 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
bogdanm 87:6213f644d804 1029 } NRF_PPI_Type;
bogdanm 87:6213f644d804 1030
bogdanm 87:6213f644d804 1031
bogdanm 87:6213f644d804 1032 /* ================================================================================ */
bogdanm 87:6213f644d804 1033 /* ================ FICR ================ */
bogdanm 87:6213f644d804 1034 /* ================================================================================ */
bogdanm 87:6213f644d804 1035
bogdanm 87:6213f644d804 1036
bogdanm 87:6213f644d804 1037 /**
bogdanm 87:6213f644d804 1038 * @brief Factory Information Configuration. (FICR)
bogdanm 87:6213f644d804 1039 */
bogdanm 87:6213f644d804 1040
bogdanm 87:6213f644d804 1041 typedef struct { /*!< FICR Structure */
bogdanm 87:6213f644d804 1042 __I uint32_t RESERVED0[4];
bogdanm 87:6213f644d804 1043 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
bogdanm 87:6213f644d804 1044 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
bogdanm 87:6213f644d804 1045 __I uint32_t RESERVED1[4];
bogdanm 87:6213f644d804 1046 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
bogdanm 87:6213f644d804 1047 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
bogdanm 87:6213f644d804 1048 __I uint32_t RESERVED2;
bogdanm 87:6213f644d804 1049 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
bogdanm 87:6213f644d804 1050 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
bogdanm 87:6213f644d804 1051 __I uint32_t RESERVED3[5];
bogdanm 87:6213f644d804 1052 __I uint32_t CONFIGID; /*!< Configuration identifier. */
bogdanm 87:6213f644d804 1053 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
bogdanm 87:6213f644d804 1054 __I uint32_t RESERVED4[6];
bogdanm 87:6213f644d804 1055 __I uint32_t ER[4]; /*!< Encryption root. */
bogdanm 87:6213f644d804 1056 __I uint32_t IR[4]; /*!< Identity root. */
bogdanm 87:6213f644d804 1057 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
bogdanm 87:6213f644d804 1058 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
bogdanm 87:6213f644d804 1059 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
bogdanm 87:6213f644d804 1060 __I uint32_t RESERVED5[15];
bogdanm 87:6213f644d804 1061 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
bogdanm 87:6213f644d804 1062 mode. */
bogdanm 87:6213f644d804 1063 } NRF_FICR_Type;
bogdanm 87:6213f644d804 1064
bogdanm 87:6213f644d804 1065
bogdanm 87:6213f644d804 1066 /* ================================================================================ */
bogdanm 87:6213f644d804 1067 /* ================ UICR ================ */
bogdanm 87:6213f644d804 1068 /* ================================================================================ */
bogdanm 87:6213f644d804 1069
bogdanm 87:6213f644d804 1070
bogdanm 87:6213f644d804 1071 /**
bogdanm 87:6213f644d804 1072 * @brief User Information Configuration. (UICR)
bogdanm 87:6213f644d804 1073 */
bogdanm 87:6213f644d804 1074
bogdanm 87:6213f644d804 1075 typedef struct { /*!< UICR Structure */
bogdanm 87:6213f644d804 1076 __IO uint32_t CLENR0; /*!< Length of code region 0. */
bogdanm 87:6213f644d804 1077 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
bogdanm 87:6213f644d804 1078 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
bogdanm 87:6213f644d804 1079 __I uint32_t RESERVED0;
bogdanm 87:6213f644d804 1080 __I uint32_t FWID; /*!< Firmware ID. */
bogdanm 87:6213f644d804 1081 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
bogdanm 87:6213f644d804 1082 } NRF_UICR_Type;
bogdanm 87:6213f644d804 1083
bogdanm 87:6213f644d804 1084
bogdanm 87:6213f644d804 1085 /* ================================================================================ */
bogdanm 87:6213f644d804 1086 /* ================ GPIO ================ */
bogdanm 87:6213f644d804 1087 /* ================================================================================ */
bogdanm 87:6213f644d804 1088
bogdanm 87:6213f644d804 1089
bogdanm 87:6213f644d804 1090 /**
bogdanm 87:6213f644d804 1091 * @brief General purpose input and output. (GPIO)
bogdanm 87:6213f644d804 1092 */
bogdanm 87:6213f644d804 1093
bogdanm 87:6213f644d804 1094 typedef struct { /*!< GPIO Structure */
bogdanm 87:6213f644d804 1095 __I uint32_t RESERVED0[321];
bogdanm 87:6213f644d804 1096 __IO uint32_t OUT; /*!< Write GPIO port. */
bogdanm 87:6213f644d804 1097 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
bogdanm 87:6213f644d804 1098 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
bogdanm 87:6213f644d804 1099 __I uint32_t IN; /*!< Read GPIO port. */
bogdanm 87:6213f644d804 1100 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
bogdanm 87:6213f644d804 1101 __IO uint32_t DIRSET; /*!< DIR set register. */
bogdanm 87:6213f644d804 1102 __IO uint32_t DIRCLR; /*!< DIR clear register. */
bogdanm 87:6213f644d804 1103 __I uint32_t RESERVED1[120];
bogdanm 87:6213f644d804 1104 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
bogdanm 87:6213f644d804 1105 } NRF_GPIO_Type;
bogdanm 87:6213f644d804 1106
bogdanm 87:6213f644d804 1107
bogdanm 87:6213f644d804 1108 /* -------------------- End of section using anonymous unions ------------------- */
bogdanm 87:6213f644d804 1109 #if defined(__CC_ARM)
bogdanm 87:6213f644d804 1110 #pragma pop
bogdanm 87:6213f644d804 1111 #elif defined(__ICCARM__)
bogdanm 87:6213f644d804 1112 /* leave anonymous unions enabled */
bogdanm 87:6213f644d804 1113 #elif defined(__GNUC__)
bogdanm 87:6213f644d804 1114 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 1115 #elif defined(__TMS470__)
bogdanm 87:6213f644d804 1116 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 1117 #elif defined(__TASKING__)
bogdanm 87:6213f644d804 1118 #pragma warning restore
bogdanm 87:6213f644d804 1119 #else
bogdanm 87:6213f644d804 1120 #warning Not supported compiler type
bogdanm 87:6213f644d804 1121 #endif
bogdanm 87:6213f644d804 1122
bogdanm 87:6213f644d804 1123
bogdanm 87:6213f644d804 1124
bogdanm 87:6213f644d804 1125
bogdanm 87:6213f644d804 1126 /* ================================================================================ */
bogdanm 87:6213f644d804 1127 /* ================ Peripheral memory map ================ */
bogdanm 87:6213f644d804 1128 /* ================================================================================ */
bogdanm 87:6213f644d804 1129
bogdanm 87:6213f644d804 1130 #define NRF_POWER_BASE 0x40000000UL
bogdanm 87:6213f644d804 1131 #define NRF_CLOCK_BASE 0x40000000UL
bogdanm 87:6213f644d804 1132 #define NRF_MPU_BASE 0x40000000UL
bogdanm 87:6213f644d804 1133 #define NRF_PU_BASE 0x40000000UL
bogdanm 87:6213f644d804 1134 #define NRF_AMLI_BASE 0x40000000UL
bogdanm 87:6213f644d804 1135 #define NRF_RADIO_BASE 0x40001000UL
bogdanm 87:6213f644d804 1136 #define NRF_UART0_BASE 0x40002000UL
bogdanm 87:6213f644d804 1137 #define NRF_SPI0_BASE 0x40003000UL
bogdanm 87:6213f644d804 1138 #define NRF_TWI0_BASE 0x40003000UL
bogdanm 87:6213f644d804 1139 #define NRF_SPI1_BASE 0x40004000UL
bogdanm 87:6213f644d804 1140 #define NRF_TWI1_BASE 0x40004000UL
bogdanm 87:6213f644d804 1141 #define NRF_SPIS1_BASE 0x40004000UL
bogdanm 87:6213f644d804 1142 #define NRF_GPIOTE_BASE 0x40006000UL
bogdanm 87:6213f644d804 1143 #define NRF_ADC_BASE 0x40007000UL
bogdanm 87:6213f644d804 1144 #define NRF_TIMER0_BASE 0x40008000UL
bogdanm 87:6213f644d804 1145 #define NRF_TIMER1_BASE 0x40009000UL
bogdanm 87:6213f644d804 1146 #define NRF_TIMER2_BASE 0x4000A000UL
bogdanm 87:6213f644d804 1147 #define NRF_RTC0_BASE 0x4000B000UL
bogdanm 87:6213f644d804 1148 #define NRF_TEMP_BASE 0x4000C000UL
bogdanm 87:6213f644d804 1149 #define NRF_RNG_BASE 0x4000D000UL
bogdanm 87:6213f644d804 1150 #define NRF_ECB_BASE 0x4000E000UL
bogdanm 87:6213f644d804 1151 #define NRF_AAR_BASE 0x4000F000UL
bogdanm 87:6213f644d804 1152 #define NRF_CCM_BASE 0x4000F000UL
bogdanm 87:6213f644d804 1153 #define NRF_WDT_BASE 0x40010000UL
bogdanm 87:6213f644d804 1154 #define NRF_RTC1_BASE 0x40011000UL
bogdanm 87:6213f644d804 1155 #define NRF_QDEC_BASE 0x40012000UL
bogdanm 87:6213f644d804 1156 #define NRF_LPCOMP_BASE 0x40013000UL
bogdanm 87:6213f644d804 1157 #define NRF_COMP_BASE 0x40013000UL
bogdanm 87:6213f644d804 1158 #define NRF_SWI_BASE 0x40014000UL
bogdanm 87:6213f644d804 1159 #define NRF_NVMC_BASE 0x4001E000UL
bogdanm 87:6213f644d804 1160 #define NRF_PPI_BASE 0x4001F000UL
bogdanm 87:6213f644d804 1161 #define NRF_FICR_BASE 0x10000000UL
bogdanm 87:6213f644d804 1162 #define NRF_UICR_BASE 0x10001000UL
bogdanm 87:6213f644d804 1163 #define NRF_GPIO_BASE 0x50000000UL
bogdanm 87:6213f644d804 1164
bogdanm 87:6213f644d804 1165
bogdanm 87:6213f644d804 1166 /* ================================================================================ */
bogdanm 87:6213f644d804 1167 /* ================ Peripheral declaration ================ */
bogdanm 87:6213f644d804 1168 /* ================================================================================ */
bogdanm 87:6213f644d804 1169
bogdanm 87:6213f644d804 1170 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
bogdanm 87:6213f644d804 1171 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
bogdanm 87:6213f644d804 1172 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
bogdanm 87:6213f644d804 1173 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
bogdanm 87:6213f644d804 1174 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
bogdanm 87:6213f644d804 1175 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
bogdanm 87:6213f644d804 1176 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
bogdanm 87:6213f644d804 1177 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
bogdanm 87:6213f644d804 1178 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
bogdanm 87:6213f644d804 1179 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
bogdanm 87:6213f644d804 1180 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
bogdanm 87:6213f644d804 1181 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
bogdanm 87:6213f644d804 1182 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
bogdanm 87:6213f644d804 1183 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
bogdanm 87:6213f644d804 1184 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
bogdanm 87:6213f644d804 1185 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
bogdanm 87:6213f644d804 1186 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
bogdanm 87:6213f644d804 1187 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
bogdanm 87:6213f644d804 1188 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
bogdanm 87:6213f644d804 1189 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
bogdanm 87:6213f644d804 1190 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
bogdanm 87:6213f644d804 1191 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
bogdanm 87:6213f644d804 1192 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
bogdanm 87:6213f644d804 1193 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
bogdanm 87:6213f644d804 1194 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
bogdanm 87:6213f644d804 1195 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
bogdanm 87:6213f644d804 1196 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
bogdanm 87:6213f644d804 1197 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
bogdanm 87:6213f644d804 1198 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
bogdanm 87:6213f644d804 1199 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
bogdanm 87:6213f644d804 1200 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
bogdanm 87:6213f644d804 1201 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
bogdanm 87:6213f644d804 1202 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
bogdanm 87:6213f644d804 1203 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
bogdanm 87:6213f644d804 1204
bogdanm 87:6213f644d804 1205
bogdanm 87:6213f644d804 1206 /** @} */ /* End of group Device_Peripheral_Registers */
bogdanm 87:6213f644d804 1207 /** @} */ /* End of group nRF51 */
bogdanm 87:6213f644d804 1208 /** @} */ /* End of group Nordic Semiconductor */
bogdanm 87:6213f644d804 1209
bogdanm 87:6213f644d804 1210 #ifdef __cplusplus
bogdanm 87:6213f644d804 1211 }
bogdanm 87:6213f644d804 1212 #endif
bogdanm 87:6213f644d804 1213
bogdanm 87:6213f644d804 1214
bogdanm 87:6213f644d804 1215 #endif /* nRF51_H */
bogdanm 87:6213f644d804 1216