frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_RZ_A1H/vdc5_iodefine.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer*
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : vdc5_iodefine.h
bogdanm 92:4fc01daae5a5 25 * $Rev: $
bogdanm 92:4fc01daae5a5 26 * $Date:: $
bogdanm 92:4fc01daae5a5 27 * Description : Definition of I/O Register (V1.00a)
bogdanm 92:4fc01daae5a5 28 ******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef VDC5_IODEFINE_H
bogdanm 92:4fc01daae5a5 30 #define VDC5_IODEFINE_H
bogdanm 92:4fc01daae5a5 31 /* ->QAC 0639 : Over 127 members (C90) */
bogdanm 92:4fc01daae5a5 32 /* ->SEC M1.10.1 : Not magic number */
bogdanm 92:4fc01daae5a5 33
bogdanm 92:4fc01daae5a5 34 struct st_vdc5
bogdanm 92:4fc01daae5a5 35 { /* VDC5 */
bogdanm 92:4fc01daae5a5 36 volatile uint32_t INP_UPDATE; /* INP_UPDATE */
bogdanm 92:4fc01daae5a5 37 volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */
bogdanm 92:4fc01daae5a5 38 volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */
bogdanm 92:4fc01daae5a5 39 volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */
bogdanm 92:4fc01daae5a5 40 volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */
bogdanm 92:4fc01daae5a5 41 volatile uint8_t dummy1[108]; /* */
bogdanm 92:4fc01daae5a5 42 volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */
bogdanm 92:4fc01daae5a5 43 #define VDC5_IMGCNT_NR_CNT0_COUNT 2
bogdanm 92:4fc01daae5a5 44 volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */
bogdanm 92:4fc01daae5a5 45 volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */
bogdanm 92:4fc01daae5a5 46 volatile uint8_t dummy2[20]; /* */
bogdanm 92:4fc01daae5a5 47 volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */
bogdanm 92:4fc01daae5a5 48 volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */
bogdanm 92:4fc01daae5a5 49 volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */
bogdanm 92:4fc01daae5a5 50 volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */
bogdanm 92:4fc01daae5a5 51 volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */
bogdanm 92:4fc01daae5a5 52 volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */
bogdanm 92:4fc01daae5a5 53 volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */
bogdanm 92:4fc01daae5a5 54 volatile uint8_t dummy3[4]; /* */
bogdanm 92:4fc01daae5a5 55 volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */
bogdanm 92:4fc01daae5a5 56 volatile uint8_t dummy4[60]; /* */
bogdanm 92:4fc01daae5a5 57 /* start of struct st_vdc5_from_sc0_scl0_update */
bogdanm 92:4fc01daae5a5 58 volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
bogdanm 92:4fc01daae5a5 59 #define VDC5_SC0_SCL0_FRC1_COUNT 7
bogdanm 92:4fc01daae5a5 60 volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
bogdanm 92:4fc01daae5a5 61 volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
bogdanm 92:4fc01daae5a5 62 volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
bogdanm 92:4fc01daae5a5 63 volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
bogdanm 92:4fc01daae5a5 64 volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
bogdanm 92:4fc01daae5a5 65 volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
bogdanm 92:4fc01daae5a5 66 volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
bogdanm 92:4fc01daae5a5 67 volatile uint8_t dummy5[4]; /* */
bogdanm 92:4fc01daae5a5 68 volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
bogdanm 92:4fc01daae5a5 69 volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
bogdanm 92:4fc01daae5a5 70 volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
bogdanm 92:4fc01daae5a5 71 #define VDC5_SC0_SCL0_DS1_COUNT 7
bogdanm 92:4fc01daae5a5 72 volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
bogdanm 92:4fc01daae5a5 73 volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
bogdanm 92:4fc01daae5a5 74 volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
bogdanm 92:4fc01daae5a5 75 volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
bogdanm 92:4fc01daae5a5 76 volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
bogdanm 92:4fc01daae5a5 77 volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
bogdanm 92:4fc01daae5a5 78 volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
bogdanm 92:4fc01daae5a5 79 #define VDC5_SC0_SCL0_US1_COUNT 8
bogdanm 92:4fc01daae5a5 80 volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
bogdanm 92:4fc01daae5a5 81 volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
bogdanm 92:4fc01daae5a5 82 volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
bogdanm 92:4fc01daae5a5 83 volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
bogdanm 92:4fc01daae5a5 84 volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
bogdanm 92:4fc01daae5a5 85 volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
bogdanm 92:4fc01daae5a5 86 volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
bogdanm 92:4fc01daae5a5 87 volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
bogdanm 92:4fc01daae5a5 88 volatile uint8_t dummy6[4]; /* */
bogdanm 92:4fc01daae5a5 89 volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
bogdanm 92:4fc01daae5a5 90 volatile uint8_t dummy7[16]; /* */
bogdanm 92:4fc01daae5a5 91 volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
bogdanm 92:4fc01daae5a5 92 volatile uint8_t dummy8[4]; /* */
bogdanm 92:4fc01daae5a5 93 #define VDC5_SC0_SCL1_WR1_COUNT 4
bogdanm 92:4fc01daae5a5 94 volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
bogdanm 92:4fc01daae5a5 95 volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
bogdanm 92:4fc01daae5a5 96 volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
bogdanm 92:4fc01daae5a5 97 volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
bogdanm 92:4fc01daae5a5 98 volatile uint8_t dummy9[4]; /* */
bogdanm 92:4fc01daae5a5 99 volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
bogdanm 92:4fc01daae5a5 100 volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
bogdanm 92:4fc01daae5a5 101 volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
bogdanm 92:4fc01daae5a5 102 volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
bogdanm 92:4fc01daae5a5 103 volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
bogdanm 92:4fc01daae5a5 104 volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
bogdanm 92:4fc01daae5a5 105 /* end of struct st_vdc5_from_sc0_scl0_update */
bogdanm 92:4fc01daae5a5 106 volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */
bogdanm 92:4fc01daae5a5 107 volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */
bogdanm 92:4fc01daae5a5 108 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
bogdanm 92:4fc01daae5a5 109 #define VDC5_SC0_SCL1_PBUF0_COUNT 4
bogdanm 92:4fc01daae5a5 110 volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
bogdanm 92:4fc01daae5a5 111 volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
bogdanm 92:4fc01daae5a5 112 volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
bogdanm 92:4fc01daae5a5 113 volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
bogdanm 92:4fc01daae5a5 114 volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
bogdanm 92:4fc01daae5a5 115 volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
bogdanm 92:4fc01daae5a5 116 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
bogdanm 92:4fc01daae5a5 117 volatile uint8_t dummy10[44]; /* */
bogdanm 92:4fc01daae5a5 118 /* start of struct st_vdc5_from_gr0_update */
bogdanm 92:4fc01daae5a5 119 volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
bogdanm 92:4fc01daae5a5 120 volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
bogdanm 92:4fc01daae5a5 121 #define VDC5_GR0_FLM1_COUNT 6
bogdanm 92:4fc01daae5a5 122 volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
bogdanm 92:4fc01daae5a5 123 volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
bogdanm 92:4fc01daae5a5 124 volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
bogdanm 92:4fc01daae5a5 125 volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
bogdanm 92:4fc01daae5a5 126 volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
bogdanm 92:4fc01daae5a5 127 volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
bogdanm 92:4fc01daae5a5 128 #define VDC5_GR0_AB1_COUNT 3
bogdanm 92:4fc01daae5a5 129 volatile uint32_t GR0_AB1; /* GR0_AB1 */
bogdanm 92:4fc01daae5a5 130 volatile uint32_t GR0_AB2; /* GR0_AB2 */
bogdanm 92:4fc01daae5a5 131 volatile uint32_t GR0_AB3; /* GR0_AB3 */
bogdanm 92:4fc01daae5a5 132 /* end of struct st_vdc5_from_gr0_update */
bogdanm 92:4fc01daae5a5 133 volatile uint8_t dummy11[12]; /* */
bogdanm 92:4fc01daae5a5 134 /* start of struct st_vdc5_from_gr0_ab7 */
bogdanm 92:4fc01daae5a5 135 volatile uint32_t GR0_AB7; /* GR0_AB7 */
bogdanm 92:4fc01daae5a5 136 volatile uint32_t GR0_AB8; /* GR0_AB8 */
bogdanm 92:4fc01daae5a5 137 volatile uint32_t GR0_AB9; /* GR0_AB9 */
bogdanm 92:4fc01daae5a5 138 volatile uint32_t GR0_AB10; /* GR0_AB10 */
bogdanm 92:4fc01daae5a5 139 volatile uint32_t GR0_AB11; /* GR0_AB11 */
bogdanm 92:4fc01daae5a5 140 volatile uint32_t GR0_BASE; /* GR0_BASE */
bogdanm 92:4fc01daae5a5 141 /* end of struct st_vdc5_from_gr0_ab7 */
bogdanm 92:4fc01daae5a5 142 volatile uint32_t GR0_CLUT; /* GR0_CLUT */
bogdanm 92:4fc01daae5a5 143 volatile uint8_t dummy12[44]; /* */
bogdanm 92:4fc01daae5a5 144 /* start of struct st_vdc5_from_adj0_update */
bogdanm 92:4fc01daae5a5 145 volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
bogdanm 92:4fc01daae5a5 146 volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
bogdanm 92:4fc01daae5a5 147 #define VDC5_ADJ0_ENH_TIM1_COUNT 3
bogdanm 92:4fc01daae5a5 148 volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
bogdanm 92:4fc01daae5a5 149 volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
bogdanm 92:4fc01daae5a5 150 volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
bogdanm 92:4fc01daae5a5 151 #define VDC5_ADJ0_ENH_SHP1_COUNT 6
bogdanm 92:4fc01daae5a5 152 volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
bogdanm 92:4fc01daae5a5 153 volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
bogdanm 92:4fc01daae5a5 154 volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
bogdanm 92:4fc01daae5a5 155 volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
bogdanm 92:4fc01daae5a5 156 volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
bogdanm 92:4fc01daae5a5 157 volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
bogdanm 92:4fc01daae5a5 158 #define VDC5_ADJ0_ENH_LTI1_COUNT 2
bogdanm 92:4fc01daae5a5 159 volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
bogdanm 92:4fc01daae5a5 160 volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
bogdanm 92:4fc01daae5a5 161 volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
bogdanm 92:4fc01daae5a5 162 volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
bogdanm 92:4fc01daae5a5 163 volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
bogdanm 92:4fc01daae5a5 164 volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
bogdanm 92:4fc01daae5a5 165 volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
bogdanm 92:4fc01daae5a5 166 volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
bogdanm 92:4fc01daae5a5 167 volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
bogdanm 92:4fc01daae5a5 168 /* end of struct st_vdc5_from_adj0_update */
bogdanm 92:4fc01daae5a5 169 volatile uint8_t dummy13[48]; /* */
bogdanm 92:4fc01daae5a5 170 /* start of struct st_vdc5_from_gr0_update */
bogdanm 92:4fc01daae5a5 171 volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */
bogdanm 92:4fc01daae5a5 172 volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */
bogdanm 92:4fc01daae5a5 173 #define VDC5_GR2_FLM1_COUNT 6
bogdanm 92:4fc01daae5a5 174 volatile uint32_t GR2_FLM1; /* GR2_FLM1 */
bogdanm 92:4fc01daae5a5 175 volatile uint32_t GR2_FLM2; /* GR2_FLM2 */
bogdanm 92:4fc01daae5a5 176 volatile uint32_t GR2_FLM3; /* GR2_FLM3 */
bogdanm 92:4fc01daae5a5 177 volatile uint32_t GR2_FLM4; /* GR2_FLM4 */
bogdanm 92:4fc01daae5a5 178 volatile uint32_t GR2_FLM5; /* GR2_FLM5 */
bogdanm 92:4fc01daae5a5 179 volatile uint32_t GR2_FLM6; /* GR2_FLM6 */
bogdanm 92:4fc01daae5a5 180 #define VDC5_GR2_AB1_COUNT 3
bogdanm 92:4fc01daae5a5 181 volatile uint32_t GR2_AB1; /* GR2_AB1 */
bogdanm 92:4fc01daae5a5 182 volatile uint32_t GR2_AB2; /* GR2_AB2 */
bogdanm 92:4fc01daae5a5 183 volatile uint32_t GR2_AB3; /* GR2_AB3 */
bogdanm 92:4fc01daae5a5 184 /* end of struct st_vdc5_from_gr0_update */
bogdanm 92:4fc01daae5a5 185 volatile uint32_t GR2_AB4; /* GR2_AB4 */
bogdanm 92:4fc01daae5a5 186 volatile uint32_t GR2_AB5; /* GR2_AB5 */
bogdanm 92:4fc01daae5a5 187 volatile uint32_t GR2_AB6; /* GR2_AB6 */
bogdanm 92:4fc01daae5a5 188 /* start of struct st_vdc5_from_gr0_ab7 */
bogdanm 92:4fc01daae5a5 189 volatile uint32_t GR2_AB7; /* GR2_AB7 */
bogdanm 92:4fc01daae5a5 190 volatile uint32_t GR2_AB8; /* GR2_AB8 */
bogdanm 92:4fc01daae5a5 191 volatile uint32_t GR2_AB9; /* GR2_AB9 */
bogdanm 92:4fc01daae5a5 192 volatile uint32_t GR2_AB10; /* GR2_AB10 */
bogdanm 92:4fc01daae5a5 193 volatile uint32_t GR2_AB11; /* GR2_AB11 */
bogdanm 92:4fc01daae5a5 194 volatile uint32_t GR2_BASE; /* GR2_BASE */
bogdanm 92:4fc01daae5a5 195 /* end of struct st_vdc5_from_gr0_ab7 */
bogdanm 92:4fc01daae5a5 196 volatile uint32_t GR2_CLUT; /* GR2_CLUT */
bogdanm 92:4fc01daae5a5 197 volatile uint32_t GR2_MON; /* GR2_MON */
bogdanm 92:4fc01daae5a5 198 volatile uint8_t dummy14[40]; /* */
bogdanm 92:4fc01daae5a5 199 /* start of struct st_vdc5_from_gr0_update */
bogdanm 92:4fc01daae5a5 200 volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */
bogdanm 92:4fc01daae5a5 201 volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */
bogdanm 92:4fc01daae5a5 202 #define VDC5_GR3_FLM1_COUNT 6
bogdanm 92:4fc01daae5a5 203 volatile uint32_t GR3_FLM1; /* GR3_FLM1 */
bogdanm 92:4fc01daae5a5 204 volatile uint32_t GR3_FLM2; /* GR3_FLM2 */
bogdanm 92:4fc01daae5a5 205 volatile uint32_t GR3_FLM3; /* GR3_FLM3 */
bogdanm 92:4fc01daae5a5 206 volatile uint32_t GR3_FLM4; /* GR3_FLM4 */
bogdanm 92:4fc01daae5a5 207 volatile uint32_t GR3_FLM5; /* GR3_FLM5 */
bogdanm 92:4fc01daae5a5 208 volatile uint32_t GR3_FLM6; /* GR3_FLM6 */
bogdanm 92:4fc01daae5a5 209 #define VDC5_GR3_AB1_COUNT 3
bogdanm 92:4fc01daae5a5 210 volatile uint32_t GR3_AB1; /* GR3_AB1 */
bogdanm 92:4fc01daae5a5 211 volatile uint32_t GR3_AB2; /* GR3_AB2 */
bogdanm 92:4fc01daae5a5 212 volatile uint32_t GR3_AB3; /* GR3_AB3 */
bogdanm 92:4fc01daae5a5 213 /* end of struct st_vdc5_from_gr0_update */
bogdanm 92:4fc01daae5a5 214 volatile uint32_t GR3_AB4; /* GR3_AB4 */
bogdanm 92:4fc01daae5a5 215 volatile uint32_t GR3_AB5; /* GR3_AB5 */
bogdanm 92:4fc01daae5a5 216 volatile uint32_t GR3_AB6; /* GR3_AB6 */
bogdanm 92:4fc01daae5a5 217 /* start of struct st_vdc5_from_gr0_ab7 */
bogdanm 92:4fc01daae5a5 218 volatile uint32_t GR3_AB7; /* GR3_AB7 */
bogdanm 92:4fc01daae5a5 219 volatile uint32_t GR3_AB8; /* GR3_AB8 */
bogdanm 92:4fc01daae5a5 220 volatile uint32_t GR3_AB9; /* GR3_AB9 */
bogdanm 92:4fc01daae5a5 221 volatile uint32_t GR3_AB10; /* GR3_AB10 */
bogdanm 92:4fc01daae5a5 222 volatile uint32_t GR3_AB11; /* GR3_AB11 */
bogdanm 92:4fc01daae5a5 223 volatile uint32_t GR3_BASE; /* GR3_BASE */
bogdanm 92:4fc01daae5a5 224 /* end of struct st_vdc5_from_gr0_ab7 */
bogdanm 92:4fc01daae5a5 225 volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */
bogdanm 92:4fc01daae5a5 226 volatile uint32_t GR3_MON; /* GR3_MON */
bogdanm 92:4fc01daae5a5 227 volatile uint8_t dummy15[40]; /* */
bogdanm 92:4fc01daae5a5 228 volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */
bogdanm 92:4fc01daae5a5 229 volatile uint32_t GAM_SW; /* GAM_SW */
bogdanm 92:4fc01daae5a5 230 #define VDC5_GAM_G_LUT1_COUNT 16
bogdanm 92:4fc01daae5a5 231 volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */
bogdanm 92:4fc01daae5a5 232 volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */
bogdanm 92:4fc01daae5a5 233 volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */
bogdanm 92:4fc01daae5a5 234 volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */
bogdanm 92:4fc01daae5a5 235 volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */
bogdanm 92:4fc01daae5a5 236 volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */
bogdanm 92:4fc01daae5a5 237 volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */
bogdanm 92:4fc01daae5a5 238 volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */
bogdanm 92:4fc01daae5a5 239 volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */
bogdanm 92:4fc01daae5a5 240 volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */
bogdanm 92:4fc01daae5a5 241 volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */
bogdanm 92:4fc01daae5a5 242 volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */
bogdanm 92:4fc01daae5a5 243 volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */
bogdanm 92:4fc01daae5a5 244 volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */
bogdanm 92:4fc01daae5a5 245 volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */
bogdanm 92:4fc01daae5a5 246 volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */
bogdanm 92:4fc01daae5a5 247 #define VDC5_GAM_G_AREA1_COUNT 8
bogdanm 92:4fc01daae5a5 248 volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */
bogdanm 92:4fc01daae5a5 249 volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */
bogdanm 92:4fc01daae5a5 250 volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */
bogdanm 92:4fc01daae5a5 251 volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */
bogdanm 92:4fc01daae5a5 252 volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */
bogdanm 92:4fc01daae5a5 253 volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */
bogdanm 92:4fc01daae5a5 254 volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */
bogdanm 92:4fc01daae5a5 255 volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */
bogdanm 92:4fc01daae5a5 256 volatile uint8_t dummy16[24]; /* */
bogdanm 92:4fc01daae5a5 257 volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */
bogdanm 92:4fc01daae5a5 258 volatile uint8_t dummy17[4]; /* */
bogdanm 92:4fc01daae5a5 259 #define VDC5_GAM_B_LUT1_COUNT 16
bogdanm 92:4fc01daae5a5 260 volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */
bogdanm 92:4fc01daae5a5 261 volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */
bogdanm 92:4fc01daae5a5 262 volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */
bogdanm 92:4fc01daae5a5 263 volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */
bogdanm 92:4fc01daae5a5 264 volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */
bogdanm 92:4fc01daae5a5 265 volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */
bogdanm 92:4fc01daae5a5 266 volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */
bogdanm 92:4fc01daae5a5 267 volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */
bogdanm 92:4fc01daae5a5 268 volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */
bogdanm 92:4fc01daae5a5 269 volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */
bogdanm 92:4fc01daae5a5 270 volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */
bogdanm 92:4fc01daae5a5 271 volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */
bogdanm 92:4fc01daae5a5 272 volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */
bogdanm 92:4fc01daae5a5 273 volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */
bogdanm 92:4fc01daae5a5 274 volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */
bogdanm 92:4fc01daae5a5 275 volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */
bogdanm 92:4fc01daae5a5 276 #define VDC5_GAM_B_AREA1_COUNT 8
bogdanm 92:4fc01daae5a5 277 volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */
bogdanm 92:4fc01daae5a5 278 volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */
bogdanm 92:4fc01daae5a5 279 volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */
bogdanm 92:4fc01daae5a5 280 volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */
bogdanm 92:4fc01daae5a5 281 volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */
bogdanm 92:4fc01daae5a5 282 volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */
bogdanm 92:4fc01daae5a5 283 volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */
bogdanm 92:4fc01daae5a5 284 volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */
bogdanm 92:4fc01daae5a5 285 volatile uint8_t dummy18[24]; /* */
bogdanm 92:4fc01daae5a5 286 volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */
bogdanm 92:4fc01daae5a5 287 volatile uint8_t dummy19[4]; /* */
bogdanm 92:4fc01daae5a5 288 #define VDC5_GAM_R_LUT1_COUNT 16
bogdanm 92:4fc01daae5a5 289 volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */
bogdanm 92:4fc01daae5a5 290 volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */
bogdanm 92:4fc01daae5a5 291 volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */
bogdanm 92:4fc01daae5a5 292 volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */
bogdanm 92:4fc01daae5a5 293 volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */
bogdanm 92:4fc01daae5a5 294 volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */
bogdanm 92:4fc01daae5a5 295 volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */
bogdanm 92:4fc01daae5a5 296 volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */
bogdanm 92:4fc01daae5a5 297 volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */
bogdanm 92:4fc01daae5a5 298 volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */
bogdanm 92:4fc01daae5a5 299 volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */
bogdanm 92:4fc01daae5a5 300 volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */
bogdanm 92:4fc01daae5a5 301 volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */
bogdanm 92:4fc01daae5a5 302 volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */
bogdanm 92:4fc01daae5a5 303 volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */
bogdanm 92:4fc01daae5a5 304 volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */
bogdanm 92:4fc01daae5a5 305 #define VDC5_GAM_R_AREA1_COUNT 8
bogdanm 92:4fc01daae5a5 306 volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */
bogdanm 92:4fc01daae5a5 307 volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */
bogdanm 92:4fc01daae5a5 308 volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */
bogdanm 92:4fc01daae5a5 309 volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */
bogdanm 92:4fc01daae5a5 310 volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */
bogdanm 92:4fc01daae5a5 311 volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */
bogdanm 92:4fc01daae5a5 312 volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */
bogdanm 92:4fc01daae5a5 313 volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */
bogdanm 92:4fc01daae5a5 314 volatile uint8_t dummy20[24]; /* */
bogdanm 92:4fc01daae5a5 315 volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */
bogdanm 92:4fc01daae5a5 316 volatile uint32_t TCON_TIM; /* TCON_TIM */
bogdanm 92:4fc01daae5a5 317 #define VDC5_TCON_TIM_STVA1_COUNT 2
bogdanm 92:4fc01daae5a5 318 volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */
bogdanm 92:4fc01daae5a5 319 volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */
bogdanm 92:4fc01daae5a5 320 #define VDC5_TCON_TIM_STVB1_COUNT 2
bogdanm 92:4fc01daae5a5 321 volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */
bogdanm 92:4fc01daae5a5 322 volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */
bogdanm 92:4fc01daae5a5 323 #define VDC5_TCON_TIM_STH1_COUNT 2
bogdanm 92:4fc01daae5a5 324 volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */
bogdanm 92:4fc01daae5a5 325 volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */
bogdanm 92:4fc01daae5a5 326 #define VDC5_TCON_TIM_STB1_COUNT 2
bogdanm 92:4fc01daae5a5 327 volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */
bogdanm 92:4fc01daae5a5 328 volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */
bogdanm 92:4fc01daae5a5 329 #define VDC5_TCON_TIM_CPV1_COUNT 2
bogdanm 92:4fc01daae5a5 330 volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */
bogdanm 92:4fc01daae5a5 331 volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */
bogdanm 92:4fc01daae5a5 332 #define VDC5_TCON_TIM_POLA1_COUNT 2
bogdanm 92:4fc01daae5a5 333 volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */
bogdanm 92:4fc01daae5a5 334 volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */
bogdanm 92:4fc01daae5a5 335 #define VDC5_TCON_TIM_POLB1_COUNT 2
bogdanm 92:4fc01daae5a5 336 volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */
bogdanm 92:4fc01daae5a5 337 volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */
bogdanm 92:4fc01daae5a5 338 volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */
bogdanm 92:4fc01daae5a5 339 volatile uint8_t dummy21[60]; /* */
bogdanm 92:4fc01daae5a5 340 volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */
bogdanm 92:4fc01daae5a5 341 volatile uint32_t OUT_SET; /* OUT_SET */
bogdanm 92:4fc01daae5a5 342 #define VDC5_OUT_BRIGHT1_COUNT 2
bogdanm 92:4fc01daae5a5 343 volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */
bogdanm 92:4fc01daae5a5 344 volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */
bogdanm 92:4fc01daae5a5 345 volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */
bogdanm 92:4fc01daae5a5 346 volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */
bogdanm 92:4fc01daae5a5 347 volatile uint8_t dummy22[12]; /* */
bogdanm 92:4fc01daae5a5 348 volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */
bogdanm 92:4fc01daae5a5 349 volatile uint8_t dummy23[88]; /* */
bogdanm 92:4fc01daae5a5 350 #define VDC5_SYSCNT_INT1_COUNT 6
bogdanm 92:4fc01daae5a5 351 volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */
bogdanm 92:4fc01daae5a5 352 volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */
bogdanm 92:4fc01daae5a5 353 volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */
bogdanm 92:4fc01daae5a5 354 volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */
bogdanm 92:4fc01daae5a5 355 volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */
bogdanm 92:4fc01daae5a5 356 volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */
bogdanm 92:4fc01daae5a5 357 volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */
bogdanm 92:4fc01daae5a5 358 volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */
bogdanm 92:4fc01daae5a5 359 volatile uint8_t dummy24[356]; /* */
bogdanm 92:4fc01daae5a5 360 /* start of struct st_vdc5_from_sc0_scl0_update */
bogdanm 92:4fc01daae5a5 361 volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */
bogdanm 92:4fc01daae5a5 362 #define VDC5_SC1_SCL0_FRC1_COUNT 7
bogdanm 92:4fc01daae5a5 363 volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */
bogdanm 92:4fc01daae5a5 364 volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */
bogdanm 92:4fc01daae5a5 365 volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */
bogdanm 92:4fc01daae5a5 366 volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */
bogdanm 92:4fc01daae5a5 367 volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */
bogdanm 92:4fc01daae5a5 368 volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */
bogdanm 92:4fc01daae5a5 369 volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */
bogdanm 92:4fc01daae5a5 370 volatile uint8_t dummy25[4]; /* */
bogdanm 92:4fc01daae5a5 371 volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */
bogdanm 92:4fc01daae5a5 372 volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */
bogdanm 92:4fc01daae5a5 373 volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */
bogdanm 92:4fc01daae5a5 374 #define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
bogdanm 92:4fc01daae5a5 375 volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */
bogdanm 92:4fc01daae5a5 376 volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */
bogdanm 92:4fc01daae5a5 377 volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */
bogdanm 92:4fc01daae5a5 378 volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */
bogdanm 92:4fc01daae5a5 379 volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */
bogdanm 92:4fc01daae5a5 380 volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */
bogdanm 92:4fc01daae5a5 381 volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */
bogdanm 92:4fc01daae5a5 382 #define VDC5_SC1_SC1_SCL0_US1_COUNT 8
bogdanm 92:4fc01daae5a5 383 volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */
bogdanm 92:4fc01daae5a5 384 volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */
bogdanm 92:4fc01daae5a5 385 volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */
bogdanm 92:4fc01daae5a5 386 volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */
bogdanm 92:4fc01daae5a5 387 volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */
bogdanm 92:4fc01daae5a5 388 volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */
bogdanm 92:4fc01daae5a5 389 volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */
bogdanm 92:4fc01daae5a5 390 volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */
bogdanm 92:4fc01daae5a5 391 volatile uint8_t dummy26[4]; /* */
bogdanm 92:4fc01daae5a5 392 volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */
bogdanm 92:4fc01daae5a5 393 volatile uint8_t dummy27[16]; /* */
bogdanm 92:4fc01daae5a5 394 volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */
bogdanm 92:4fc01daae5a5 395 volatile uint8_t dummy28[4]; /* */
bogdanm 92:4fc01daae5a5 396 #define VDC5_SC1_SCL1_WR1_COUNT 4
bogdanm 92:4fc01daae5a5 397 volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */
bogdanm 92:4fc01daae5a5 398 volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */
bogdanm 92:4fc01daae5a5 399 volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */
bogdanm 92:4fc01daae5a5 400 volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */
bogdanm 92:4fc01daae5a5 401 volatile uint8_t dummy29[4]; /* */
bogdanm 92:4fc01daae5a5 402 volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */
bogdanm 92:4fc01daae5a5 403 volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */
bogdanm 92:4fc01daae5a5 404 volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */
bogdanm 92:4fc01daae5a5 405 volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */
bogdanm 92:4fc01daae5a5 406 volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */
bogdanm 92:4fc01daae5a5 407 volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */
bogdanm 92:4fc01daae5a5 408 /* end of struct st_vdc5_from_sc0_scl0_update */
bogdanm 92:4fc01daae5a5 409 volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */
bogdanm 92:4fc01daae5a5 410 volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */
bogdanm 92:4fc01daae5a5 411 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
bogdanm 92:4fc01daae5a5 412 #define VDC5_SC1_SCL1_PBUF0_COUNT 4
bogdanm 92:4fc01daae5a5 413 volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */
bogdanm 92:4fc01daae5a5 414 volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */
bogdanm 92:4fc01daae5a5 415 volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */
bogdanm 92:4fc01daae5a5 416 volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */
bogdanm 92:4fc01daae5a5 417 volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */
bogdanm 92:4fc01daae5a5 418 volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */
bogdanm 92:4fc01daae5a5 419 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
bogdanm 92:4fc01daae5a5 420 volatile uint8_t dummy30[44]; /* */
bogdanm 92:4fc01daae5a5 421 /* start of struct st_vdc5_from_gr0_update */
bogdanm 92:4fc01daae5a5 422 volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */
bogdanm 92:4fc01daae5a5 423 volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */
bogdanm 92:4fc01daae5a5 424 #define VDC5_GR1_FLM1_COUNT 6
bogdanm 92:4fc01daae5a5 425 volatile uint32_t GR1_FLM1; /* GR1_FLM1 */
bogdanm 92:4fc01daae5a5 426 volatile uint32_t GR1_FLM2; /* GR1_FLM2 */
bogdanm 92:4fc01daae5a5 427 volatile uint32_t GR1_FLM3; /* GR1_FLM3 */
bogdanm 92:4fc01daae5a5 428 volatile uint32_t GR1_FLM4; /* GR1_FLM4 */
bogdanm 92:4fc01daae5a5 429 volatile uint32_t GR1_FLM5; /* GR1_FLM5 */
bogdanm 92:4fc01daae5a5 430 volatile uint32_t GR1_FLM6; /* GR1_FLM6 */
bogdanm 92:4fc01daae5a5 431 #define VDC5_GR1_AB1_COUNT 3
bogdanm 92:4fc01daae5a5 432 volatile uint32_t GR1_AB1; /* GR1_AB1 */
bogdanm 92:4fc01daae5a5 433 volatile uint32_t GR1_AB2; /* GR1_AB2 */
bogdanm 92:4fc01daae5a5 434 volatile uint32_t GR1_AB3; /* GR1_AB3 */
bogdanm 92:4fc01daae5a5 435 /* end of struct st_vdc5_from_gr0_update */
bogdanm 92:4fc01daae5a5 436 volatile uint32_t GR1_AB4; /* GR1_AB4 */
bogdanm 92:4fc01daae5a5 437 volatile uint32_t GR1_AB5; /* GR1_AB5 */
bogdanm 92:4fc01daae5a5 438 volatile uint32_t GR1_AB6; /* GR1_AB6 */
bogdanm 92:4fc01daae5a5 439 /* start of struct st_vdc5_from_gr0_ab7 */
bogdanm 92:4fc01daae5a5 440 volatile uint32_t GR1_AB7; /* GR1_AB7 */
bogdanm 92:4fc01daae5a5 441 volatile uint32_t GR1_AB8; /* GR1_AB8 */
bogdanm 92:4fc01daae5a5 442 volatile uint32_t GR1_AB9; /* GR1_AB9 */
bogdanm 92:4fc01daae5a5 443 volatile uint32_t GR1_AB10; /* GR1_AB10 */
bogdanm 92:4fc01daae5a5 444 volatile uint32_t GR1_AB11; /* GR1_AB11 */
bogdanm 92:4fc01daae5a5 445 volatile uint32_t GR1_BASE; /* GR1_BASE */
bogdanm 92:4fc01daae5a5 446 /* end of struct st_vdc5_from_gr0_ab7 */
bogdanm 92:4fc01daae5a5 447 volatile uint32_t GR1_CLUT; /* GR1_CLUT */
bogdanm 92:4fc01daae5a5 448 volatile uint32_t GR1_MON; /* GR1_MON */
bogdanm 92:4fc01daae5a5 449 volatile uint8_t dummy31[40]; /* */
bogdanm 92:4fc01daae5a5 450 /* start of struct st_vdc5_from_adj0_update */
bogdanm 92:4fc01daae5a5 451 volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */
bogdanm 92:4fc01daae5a5 452 volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */
bogdanm 92:4fc01daae5a5 453 #define VDC5_ADJ1_ENH_TIM1_COUNT 3
bogdanm 92:4fc01daae5a5 454 volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */
bogdanm 92:4fc01daae5a5 455 volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */
bogdanm 92:4fc01daae5a5 456 volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */
bogdanm 92:4fc01daae5a5 457 #define VDC5_ADJ1_ENH_SHP1_COUNT 6
bogdanm 92:4fc01daae5a5 458 volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */
bogdanm 92:4fc01daae5a5 459 volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */
bogdanm 92:4fc01daae5a5 460 volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */
bogdanm 92:4fc01daae5a5 461 volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */
bogdanm 92:4fc01daae5a5 462 volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */
bogdanm 92:4fc01daae5a5 463 volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */
bogdanm 92:4fc01daae5a5 464 #define VDC5_ADJ1_ENH_LTI1_COUNT 2
bogdanm 92:4fc01daae5a5 465 volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */
bogdanm 92:4fc01daae5a5 466 volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */
bogdanm 92:4fc01daae5a5 467 volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */
bogdanm 92:4fc01daae5a5 468 volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */
bogdanm 92:4fc01daae5a5 469 volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */
bogdanm 92:4fc01daae5a5 470 volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */
bogdanm 92:4fc01daae5a5 471 volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */
bogdanm 92:4fc01daae5a5 472 volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */
bogdanm 92:4fc01daae5a5 473 volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */
bogdanm 92:4fc01daae5a5 474 /* end of struct st_vdc5_from_adj0_update */
bogdanm 92:4fc01daae5a5 475 volatile uint8_t dummy32[48]; /* */
bogdanm 92:4fc01daae5a5 476 volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */
bogdanm 92:4fc01daae5a5 477 volatile uint8_t dummy33[28]; /* */
bogdanm 92:4fc01daae5a5 478 #define VDC5_GR_VIN_AB1_COUNT 7
bogdanm 92:4fc01daae5a5 479 volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */
bogdanm 92:4fc01daae5a5 480 volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */
bogdanm 92:4fc01daae5a5 481 volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */
bogdanm 92:4fc01daae5a5 482 volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */
bogdanm 92:4fc01daae5a5 483 volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */
bogdanm 92:4fc01daae5a5 484 volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */
bogdanm 92:4fc01daae5a5 485 volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */
bogdanm 92:4fc01daae5a5 486 volatile uint8_t dummy34[16]; /* */
bogdanm 92:4fc01daae5a5 487 volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */
bogdanm 92:4fc01daae5a5 488 volatile uint8_t dummy35[4]; /* */
bogdanm 92:4fc01daae5a5 489 volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */
bogdanm 92:4fc01daae5a5 490 volatile uint8_t dummy36[40]; /* */
bogdanm 92:4fc01daae5a5 491 volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */
bogdanm 92:4fc01daae5a5 492 #define VDC5_OIR_SCL0_FRC1_COUNT 7
bogdanm 92:4fc01daae5a5 493 volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */
bogdanm 92:4fc01daae5a5 494 volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */
bogdanm 92:4fc01daae5a5 495 volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */
bogdanm 92:4fc01daae5a5 496 volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */
bogdanm 92:4fc01daae5a5 497 volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */
bogdanm 92:4fc01daae5a5 498 volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */
bogdanm 92:4fc01daae5a5 499 volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */
bogdanm 92:4fc01daae5a5 500 volatile uint8_t dummy37[12]; /* */
bogdanm 92:4fc01daae5a5 501 #define VDC5_OIR_SCL0_DS1_COUNT 3
bogdanm 92:4fc01daae5a5 502 volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */
bogdanm 92:4fc01daae5a5 503 volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */
bogdanm 92:4fc01daae5a5 504 volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */
bogdanm 92:4fc01daae5a5 505 volatile uint8_t dummy38[12]; /* */
bogdanm 92:4fc01daae5a5 506 volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */
bogdanm 92:4fc01daae5a5 507 volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */
bogdanm 92:4fc01daae5a5 508 volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */
bogdanm 92:4fc01daae5a5 509 volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */
bogdanm 92:4fc01daae5a5 510 volatile uint8_t dummy39[16]; /* */
bogdanm 92:4fc01daae5a5 511 volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */
bogdanm 92:4fc01daae5a5 512 volatile uint8_t dummy40[4]; /* */
bogdanm 92:4fc01daae5a5 513 volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */
bogdanm 92:4fc01daae5a5 514 volatile uint8_t dummy41[16]; /* */
bogdanm 92:4fc01daae5a5 515 volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */
bogdanm 92:4fc01daae5a5 516 volatile uint8_t dummy42[4]; /* */
bogdanm 92:4fc01daae5a5 517 #define VDC5_OIR_SCL1_WR1_COUNT 4
bogdanm 92:4fc01daae5a5 518 volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */
bogdanm 92:4fc01daae5a5 519 volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */
bogdanm 92:4fc01daae5a5 520 volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */
bogdanm 92:4fc01daae5a5 521 volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */
bogdanm 92:4fc01daae5a5 522 volatile uint8_t dummy43[4]; /* */
bogdanm 92:4fc01daae5a5 523 volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */
bogdanm 92:4fc01daae5a5 524 volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */
bogdanm 92:4fc01daae5a5 525 volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */
bogdanm 92:4fc01daae5a5 526 volatile uint8_t dummy44[88]; /* */
bogdanm 92:4fc01daae5a5 527 volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */
bogdanm 92:4fc01daae5a5 528 volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */
bogdanm 92:4fc01daae5a5 529 #define VDC5_GR_OIR_FLM1_COUNT 6
bogdanm 92:4fc01daae5a5 530 volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */
bogdanm 92:4fc01daae5a5 531 volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */
bogdanm 92:4fc01daae5a5 532 volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */
bogdanm 92:4fc01daae5a5 533 volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */
bogdanm 92:4fc01daae5a5 534 volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */
bogdanm 92:4fc01daae5a5 535 volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */
bogdanm 92:4fc01daae5a5 536 #define VDC5_GR_OIR_AB1_COUNT 3
bogdanm 92:4fc01daae5a5 537 volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */
bogdanm 92:4fc01daae5a5 538 volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */
bogdanm 92:4fc01daae5a5 539 volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */
bogdanm 92:4fc01daae5a5 540 volatile uint8_t dummy45[12]; /* */
bogdanm 92:4fc01daae5a5 541 volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */
bogdanm 92:4fc01daae5a5 542 volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */
bogdanm 92:4fc01daae5a5 543 volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */
bogdanm 92:4fc01daae5a5 544 volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */
bogdanm 92:4fc01daae5a5 545 volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */
bogdanm 92:4fc01daae5a5 546 volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */
bogdanm 92:4fc01daae5a5 547 volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */
bogdanm 92:4fc01daae5a5 548 volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */
bogdanm 92:4fc01daae5a5 549 };
bogdanm 92:4fc01daae5a5 550
bogdanm 92:4fc01daae5a5 551
bogdanm 92:4fc01daae5a5 552 struct st_vdc5_from_gr0_update
bogdanm 92:4fc01daae5a5 553 {
bogdanm 92:4fc01daae5a5 554 volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
bogdanm 92:4fc01daae5a5 555 volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
bogdanm 92:4fc01daae5a5 556 volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
bogdanm 92:4fc01daae5a5 557 volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
bogdanm 92:4fc01daae5a5 558 volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
bogdanm 92:4fc01daae5a5 559 volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
bogdanm 92:4fc01daae5a5 560 volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
bogdanm 92:4fc01daae5a5 561 volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
bogdanm 92:4fc01daae5a5 562 volatile uint32_t GR0_AB1; /* GR0_AB1 */
bogdanm 92:4fc01daae5a5 563 volatile uint32_t GR0_AB2; /* GR0_AB2 */
bogdanm 92:4fc01daae5a5 564 volatile uint32_t GR0_AB3; /* GR0_AB3 */
bogdanm 92:4fc01daae5a5 565 };
bogdanm 92:4fc01daae5a5 566
bogdanm 92:4fc01daae5a5 567
bogdanm 92:4fc01daae5a5 568 struct st_vdc5_from_gr0_ab7
bogdanm 92:4fc01daae5a5 569 {
bogdanm 92:4fc01daae5a5 570 volatile uint32_t GR0_AB7; /* GR0_AB7 */
bogdanm 92:4fc01daae5a5 571 volatile uint32_t GR0_AB8; /* GR0_AB8 */
bogdanm 92:4fc01daae5a5 572 volatile uint32_t GR0_AB9; /* GR0_AB9 */
bogdanm 92:4fc01daae5a5 573 volatile uint32_t GR0_AB10; /* GR0_AB10 */
bogdanm 92:4fc01daae5a5 574 volatile uint32_t GR0_AB11; /* GR0_AB11 */
bogdanm 92:4fc01daae5a5 575 volatile uint32_t GR0_BASE; /* GR0_BASE */
bogdanm 92:4fc01daae5a5 576 };
bogdanm 92:4fc01daae5a5 577
bogdanm 92:4fc01daae5a5 578
bogdanm 92:4fc01daae5a5 579 struct st_vdc5_from_adj0_update
bogdanm 92:4fc01daae5a5 580 {
bogdanm 92:4fc01daae5a5 581 volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
bogdanm 92:4fc01daae5a5 582 volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
bogdanm 92:4fc01daae5a5 583 volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
bogdanm 92:4fc01daae5a5 584 volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
bogdanm 92:4fc01daae5a5 585 volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
bogdanm 92:4fc01daae5a5 586 volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
bogdanm 92:4fc01daae5a5 587 volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
bogdanm 92:4fc01daae5a5 588 volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
bogdanm 92:4fc01daae5a5 589 volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
bogdanm 92:4fc01daae5a5 590 volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
bogdanm 92:4fc01daae5a5 591 volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
bogdanm 92:4fc01daae5a5 592 volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
bogdanm 92:4fc01daae5a5 593 volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
bogdanm 92:4fc01daae5a5 594 volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
bogdanm 92:4fc01daae5a5 595 volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
bogdanm 92:4fc01daae5a5 596 volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
bogdanm 92:4fc01daae5a5 597 volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
bogdanm 92:4fc01daae5a5 598 volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
bogdanm 92:4fc01daae5a5 599 volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
bogdanm 92:4fc01daae5a5 600 volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
bogdanm 92:4fc01daae5a5 601 };
bogdanm 92:4fc01daae5a5 602
bogdanm 92:4fc01daae5a5 603
bogdanm 92:4fc01daae5a5 604 struct st_vdc5_from_sc0_scl0_update
bogdanm 92:4fc01daae5a5 605 {
bogdanm 92:4fc01daae5a5 606 volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
bogdanm 92:4fc01daae5a5 607 volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
bogdanm 92:4fc01daae5a5 608 volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
bogdanm 92:4fc01daae5a5 609 volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
bogdanm 92:4fc01daae5a5 610 volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
bogdanm 92:4fc01daae5a5 611 volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
bogdanm 92:4fc01daae5a5 612 volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
bogdanm 92:4fc01daae5a5 613 volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
bogdanm 92:4fc01daae5a5 614 volatile uint8_t dummy5[4]; /* */
bogdanm 92:4fc01daae5a5 615 volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
bogdanm 92:4fc01daae5a5 616 volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
bogdanm 92:4fc01daae5a5 617 volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
bogdanm 92:4fc01daae5a5 618 volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
bogdanm 92:4fc01daae5a5 619 volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
bogdanm 92:4fc01daae5a5 620 volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
bogdanm 92:4fc01daae5a5 621 volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
bogdanm 92:4fc01daae5a5 622 volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
bogdanm 92:4fc01daae5a5 623 volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
bogdanm 92:4fc01daae5a5 624 volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
bogdanm 92:4fc01daae5a5 625 volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
bogdanm 92:4fc01daae5a5 626 volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
bogdanm 92:4fc01daae5a5 627 volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
bogdanm 92:4fc01daae5a5 628 volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
bogdanm 92:4fc01daae5a5 629 volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
bogdanm 92:4fc01daae5a5 630 volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
bogdanm 92:4fc01daae5a5 631 volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
bogdanm 92:4fc01daae5a5 632 volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
bogdanm 92:4fc01daae5a5 633 volatile uint8_t dummy6[4]; /* */
bogdanm 92:4fc01daae5a5 634 volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
bogdanm 92:4fc01daae5a5 635 volatile uint8_t dummy7[16]; /* */
bogdanm 92:4fc01daae5a5 636 volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
bogdanm 92:4fc01daae5a5 637 volatile uint8_t dummy8[4]; /* */
bogdanm 92:4fc01daae5a5 638 volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
bogdanm 92:4fc01daae5a5 639 volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
bogdanm 92:4fc01daae5a5 640 volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
bogdanm 92:4fc01daae5a5 641 volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
bogdanm 92:4fc01daae5a5 642 volatile uint8_t dummy9[4]; /* */
bogdanm 92:4fc01daae5a5 643 volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
bogdanm 92:4fc01daae5a5 644 volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
bogdanm 92:4fc01daae5a5 645 volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
bogdanm 92:4fc01daae5a5 646 volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
bogdanm 92:4fc01daae5a5 647 volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
bogdanm 92:4fc01daae5a5 648 volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
bogdanm 92:4fc01daae5a5 649 };
bogdanm 92:4fc01daae5a5 650
bogdanm 92:4fc01daae5a5 651
bogdanm 92:4fc01daae5a5 652 struct st_vdc5_from_sc0_scl1_pbuf0
bogdanm 92:4fc01daae5a5 653 {
bogdanm 92:4fc01daae5a5 654 volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
bogdanm 92:4fc01daae5a5 655 volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
bogdanm 92:4fc01daae5a5 656 volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
bogdanm 92:4fc01daae5a5 657 volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
bogdanm 92:4fc01daae5a5 658 volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
bogdanm 92:4fc01daae5a5 659 volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
bogdanm 92:4fc01daae5a5 660 };
bogdanm 92:4fc01daae5a5 661
bogdanm 92:4fc01daae5a5 662
bogdanm 92:4fc01daae5a5 663 #define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */
bogdanm 92:4fc01daae5a5 664 #define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */
bogdanm 92:4fc01daae5a5 665
bogdanm 92:4fc01daae5a5 666
bogdanm 92:4fc01daae5a5 667 /* Start of channnel array defines of VDC5 */
bogdanm 92:4fc01daae5a5 668
bogdanm 92:4fc01daae5a5 669 /* Channnel array defines of VDC5 */
bogdanm 92:4fc01daae5a5 670 /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
bogdanm 92:4fc01daae5a5 671 #define VDC5_COUNT 2
bogdanm 92:4fc01daae5a5 672 #define VDC5_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 673 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 674 &VDC50, &VDC51 \
bogdanm 92:4fc01daae5a5 675 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 676
bogdanm 92:4fc01daae5a5 677
bogdanm 92:4fc01daae5a5 678
bogdanm 92:4fc01daae5a5 679 /* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
bogdanm 92:4fc01daae5a5 680 /*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
bogdanm 92:4fc01daae5a5 681 #define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2
bogdanm 92:4fc01daae5a5 682 #define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 683 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 684 { \
bogdanm 92:4fc01daae5a5 685 &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
bogdanm 92:4fc01daae5a5 686 &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
bogdanm 92:4fc01daae5a5 687 } \
bogdanm 92:4fc01daae5a5 688 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 689 #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
bogdanm 92:4fc01daae5a5 690 #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
bogdanm 92:4fc01daae5a5 691 #define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
bogdanm 92:4fc01daae5a5 692 #define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
bogdanm 92:4fc01daae5a5 693
bogdanm 92:4fc01daae5a5 694
bogdanm 92:4fc01daae5a5 695
bogdanm 92:4fc01daae5a5 696
bogdanm 92:4fc01daae5a5 697 /* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
bogdanm 92:4fc01daae5a5 698 /*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
bogdanm 92:4fc01daae5a5 699 #define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2
bogdanm 92:4fc01daae5a5 700 #define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 701 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 702 { \
bogdanm 92:4fc01daae5a5 703 &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
bogdanm 92:4fc01daae5a5 704 &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
bogdanm 92:4fc01daae5a5 705 } \
bogdanm 92:4fc01daae5a5 706 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 707 #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
bogdanm 92:4fc01daae5a5 708 #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
bogdanm 92:4fc01daae5a5 709 #define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
bogdanm 92:4fc01daae5a5 710 #define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
bogdanm 92:4fc01daae5a5 711
bogdanm 92:4fc01daae5a5 712
bogdanm 92:4fc01daae5a5 713
bogdanm 92:4fc01daae5a5 714
bogdanm 92:4fc01daae5a5 715 /* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
bogdanm 92:4fc01daae5a5 716 /*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
bogdanm 92:4fc01daae5a5 717 #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2
bogdanm 92:4fc01daae5a5 718 #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 719 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 720 { \
bogdanm 92:4fc01daae5a5 721 &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
bogdanm 92:4fc01daae5a5 722 &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
bogdanm 92:4fc01daae5a5 723 } \
bogdanm 92:4fc01daae5a5 724 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 725 #define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
bogdanm 92:4fc01daae5a5 726 #define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
bogdanm 92:4fc01daae5a5 727 #define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
bogdanm 92:4fc01daae5a5 728 #define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
bogdanm 92:4fc01daae5a5 729
bogdanm 92:4fc01daae5a5 730
bogdanm 92:4fc01daae5a5 731
bogdanm 92:4fc01daae5a5 732
bogdanm 92:4fc01daae5a5 733 /* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
bogdanm 92:4fc01daae5a5 734 /*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
bogdanm 92:4fc01daae5a5 735 #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2
bogdanm 92:4fc01daae5a5 736 #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 737 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 738 { \
bogdanm 92:4fc01daae5a5 739 &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
bogdanm 92:4fc01daae5a5 740 &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
bogdanm 92:4fc01daae5a5 741 } \
bogdanm 92:4fc01daae5a5 742 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 743 #define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
bogdanm 92:4fc01daae5a5 744 #define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
bogdanm 92:4fc01daae5a5 745 #define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
bogdanm 92:4fc01daae5a5 746 #define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
bogdanm 92:4fc01daae5a5 747
bogdanm 92:4fc01daae5a5 748
bogdanm 92:4fc01daae5a5 749
bogdanm 92:4fc01daae5a5 750
bogdanm 92:4fc01daae5a5 751 /* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
bogdanm 92:4fc01daae5a5 752 /*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
bogdanm 92:4fc01daae5a5 753 #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2
bogdanm 92:4fc01daae5a5 754 #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 755 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 756 { \
bogdanm 92:4fc01daae5a5 757 &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
bogdanm 92:4fc01daae5a5 758 &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
bogdanm 92:4fc01daae5a5 759 } \
bogdanm 92:4fc01daae5a5 760 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 761 #define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
bogdanm 92:4fc01daae5a5 762 #define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
bogdanm 92:4fc01daae5a5 763 #define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
bogdanm 92:4fc01daae5a5 764 #define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
bogdanm 92:4fc01daae5a5 765
bogdanm 92:4fc01daae5a5 766
bogdanm 92:4fc01daae5a5 767
bogdanm 92:4fc01daae5a5 768
bogdanm 92:4fc01daae5a5 769 /* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
bogdanm 92:4fc01daae5a5 770 /*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
bogdanm 92:4fc01daae5a5 771 #define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2
bogdanm 92:4fc01daae5a5 772 #define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 773 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 774 { \
bogdanm 92:4fc01daae5a5 775 &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
bogdanm 92:4fc01daae5a5 776 &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
bogdanm 92:4fc01daae5a5 777 } \
bogdanm 92:4fc01daae5a5 778 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 779 #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
bogdanm 92:4fc01daae5a5 780 #define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
bogdanm 92:4fc01daae5a5 781 #define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
bogdanm 92:4fc01daae5a5 782 #define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
bogdanm 92:4fc01daae5a5 783
bogdanm 92:4fc01daae5a5 784
bogdanm 92:4fc01daae5a5 785
bogdanm 92:4fc01daae5a5 786
bogdanm 92:4fc01daae5a5 787 /* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
bogdanm 92:4fc01daae5a5 788 /*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
bogdanm 92:4fc01daae5a5 789 #define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2
bogdanm 92:4fc01daae5a5 790 #define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 791 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 792 { \
bogdanm 92:4fc01daae5a5 793 &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
bogdanm 92:4fc01daae5a5 794 &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
bogdanm 92:4fc01daae5a5 795 } \
bogdanm 92:4fc01daae5a5 796 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 797 #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
bogdanm 92:4fc01daae5a5 798 #define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
bogdanm 92:4fc01daae5a5 799 #define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
bogdanm 92:4fc01daae5a5 800 #define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
bogdanm 92:4fc01daae5a5 801
bogdanm 92:4fc01daae5a5 802
bogdanm 92:4fc01daae5a5 803 /* End of channnel array defines of VDC5 */
bogdanm 92:4fc01daae5a5 804
bogdanm 92:4fc01daae5a5 805
bogdanm 92:4fc01daae5a5 806 #define VDC50INP_UPDATE VDC50.INP_UPDATE
bogdanm 92:4fc01daae5a5 807 #define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
bogdanm 92:4fc01daae5a5 808 #define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
bogdanm 92:4fc01daae5a5 809 #define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
bogdanm 92:4fc01daae5a5 810 #define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
bogdanm 92:4fc01daae5a5 811 #define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
bogdanm 92:4fc01daae5a5 812 #define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
bogdanm 92:4fc01daae5a5 813 #define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
bogdanm 92:4fc01daae5a5 814 #define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
bogdanm 92:4fc01daae5a5 815 #define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
bogdanm 92:4fc01daae5a5 816 #define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
bogdanm 92:4fc01daae5a5 817 #define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
bogdanm 92:4fc01daae5a5 818 #define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
bogdanm 92:4fc01daae5a5 819 #define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
bogdanm 92:4fc01daae5a5 820 #define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
bogdanm 92:4fc01daae5a5 821 #define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
bogdanm 92:4fc01daae5a5 822 #define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
bogdanm 92:4fc01daae5a5 823 #define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
bogdanm 92:4fc01daae5a5 824 #define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
bogdanm 92:4fc01daae5a5 825 #define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
bogdanm 92:4fc01daae5a5 826 #define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
bogdanm 92:4fc01daae5a5 827 #define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
bogdanm 92:4fc01daae5a5 828 #define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
bogdanm 92:4fc01daae5a5 829 #define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
bogdanm 92:4fc01daae5a5 830 #define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
bogdanm 92:4fc01daae5a5 831 #define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
bogdanm 92:4fc01daae5a5 832 #define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
bogdanm 92:4fc01daae5a5 833 #define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
bogdanm 92:4fc01daae5a5 834 #define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
bogdanm 92:4fc01daae5a5 835 #define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
bogdanm 92:4fc01daae5a5 836 #define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
bogdanm 92:4fc01daae5a5 837 #define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
bogdanm 92:4fc01daae5a5 838 #define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
bogdanm 92:4fc01daae5a5 839 #define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
bogdanm 92:4fc01daae5a5 840 #define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
bogdanm 92:4fc01daae5a5 841 #define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
bogdanm 92:4fc01daae5a5 842 #define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
bogdanm 92:4fc01daae5a5 843 #define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
bogdanm 92:4fc01daae5a5 844 #define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
bogdanm 92:4fc01daae5a5 845 #define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
bogdanm 92:4fc01daae5a5 846 #define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
bogdanm 92:4fc01daae5a5 847 #define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
bogdanm 92:4fc01daae5a5 848 #define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
bogdanm 92:4fc01daae5a5 849 #define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
bogdanm 92:4fc01daae5a5 850 #define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
bogdanm 92:4fc01daae5a5 851 #define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
bogdanm 92:4fc01daae5a5 852 #define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
bogdanm 92:4fc01daae5a5 853 #define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
bogdanm 92:4fc01daae5a5 854 #define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
bogdanm 92:4fc01daae5a5 855 #define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
bogdanm 92:4fc01daae5a5 856 #define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
bogdanm 92:4fc01daae5a5 857 #define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
bogdanm 92:4fc01daae5a5 858 #define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
bogdanm 92:4fc01daae5a5 859 #define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
bogdanm 92:4fc01daae5a5 860 #define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
bogdanm 92:4fc01daae5a5 861 #define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
bogdanm 92:4fc01daae5a5 862 #define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
bogdanm 92:4fc01daae5a5 863 #define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
bogdanm 92:4fc01daae5a5 864 #define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
bogdanm 92:4fc01daae5a5 865 #define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
bogdanm 92:4fc01daae5a5 866 #define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
bogdanm 92:4fc01daae5a5 867 #define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
bogdanm 92:4fc01daae5a5 868 #define VDC50GR0_UPDATE VDC50.GR0_UPDATE
bogdanm 92:4fc01daae5a5 869 #define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
bogdanm 92:4fc01daae5a5 870 #define VDC50GR0_FLM1 VDC50.GR0_FLM1
bogdanm 92:4fc01daae5a5 871 #define VDC50GR0_FLM2 VDC50.GR0_FLM2
bogdanm 92:4fc01daae5a5 872 #define VDC50GR0_FLM3 VDC50.GR0_FLM3
bogdanm 92:4fc01daae5a5 873 #define VDC50GR0_FLM4 VDC50.GR0_FLM4
bogdanm 92:4fc01daae5a5 874 #define VDC50GR0_FLM5 VDC50.GR0_FLM5
bogdanm 92:4fc01daae5a5 875 #define VDC50GR0_FLM6 VDC50.GR0_FLM6
bogdanm 92:4fc01daae5a5 876 #define VDC50GR0_AB1 VDC50.GR0_AB1
bogdanm 92:4fc01daae5a5 877 #define VDC50GR0_AB2 VDC50.GR0_AB2
bogdanm 92:4fc01daae5a5 878 #define VDC50GR0_AB3 VDC50.GR0_AB3
bogdanm 92:4fc01daae5a5 879 #define VDC50GR0_AB7 VDC50.GR0_AB7
bogdanm 92:4fc01daae5a5 880 #define VDC50GR0_AB8 VDC50.GR0_AB8
bogdanm 92:4fc01daae5a5 881 #define VDC50GR0_AB9 VDC50.GR0_AB9
bogdanm 92:4fc01daae5a5 882 #define VDC50GR0_AB10 VDC50.GR0_AB10
bogdanm 92:4fc01daae5a5 883 #define VDC50GR0_AB11 VDC50.GR0_AB11
bogdanm 92:4fc01daae5a5 884 #define VDC50GR0_BASE VDC50.GR0_BASE
bogdanm 92:4fc01daae5a5 885 #define VDC50GR0_CLUT VDC50.GR0_CLUT
bogdanm 92:4fc01daae5a5 886 #define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
bogdanm 92:4fc01daae5a5 887 #define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
bogdanm 92:4fc01daae5a5 888 #define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
bogdanm 92:4fc01daae5a5 889 #define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
bogdanm 92:4fc01daae5a5 890 #define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
bogdanm 92:4fc01daae5a5 891 #define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
bogdanm 92:4fc01daae5a5 892 #define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
bogdanm 92:4fc01daae5a5 893 #define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
bogdanm 92:4fc01daae5a5 894 #define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
bogdanm 92:4fc01daae5a5 895 #define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
bogdanm 92:4fc01daae5a5 896 #define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
bogdanm 92:4fc01daae5a5 897 #define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
bogdanm 92:4fc01daae5a5 898 #define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
bogdanm 92:4fc01daae5a5 899 #define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
bogdanm 92:4fc01daae5a5 900 #define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
bogdanm 92:4fc01daae5a5 901 #define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
bogdanm 92:4fc01daae5a5 902 #define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
bogdanm 92:4fc01daae5a5 903 #define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
bogdanm 92:4fc01daae5a5 904 #define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
bogdanm 92:4fc01daae5a5 905 #define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
bogdanm 92:4fc01daae5a5 906 #define VDC50GR2_UPDATE VDC50.GR2_UPDATE
bogdanm 92:4fc01daae5a5 907 #define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
bogdanm 92:4fc01daae5a5 908 #define VDC50GR2_FLM1 VDC50.GR2_FLM1
bogdanm 92:4fc01daae5a5 909 #define VDC50GR2_FLM2 VDC50.GR2_FLM2
bogdanm 92:4fc01daae5a5 910 #define VDC50GR2_FLM3 VDC50.GR2_FLM3
bogdanm 92:4fc01daae5a5 911 #define VDC50GR2_FLM4 VDC50.GR2_FLM4
bogdanm 92:4fc01daae5a5 912 #define VDC50GR2_FLM5 VDC50.GR2_FLM5
bogdanm 92:4fc01daae5a5 913 #define VDC50GR2_FLM6 VDC50.GR2_FLM6
bogdanm 92:4fc01daae5a5 914 #define VDC50GR2_AB1 VDC50.GR2_AB1
bogdanm 92:4fc01daae5a5 915 #define VDC50GR2_AB2 VDC50.GR2_AB2
bogdanm 92:4fc01daae5a5 916 #define VDC50GR2_AB3 VDC50.GR2_AB3
bogdanm 92:4fc01daae5a5 917 #define VDC50GR2_AB4 VDC50.GR2_AB4
bogdanm 92:4fc01daae5a5 918 #define VDC50GR2_AB5 VDC50.GR2_AB5
bogdanm 92:4fc01daae5a5 919 #define VDC50GR2_AB6 VDC50.GR2_AB6
bogdanm 92:4fc01daae5a5 920 #define VDC50GR2_AB7 VDC50.GR2_AB7
bogdanm 92:4fc01daae5a5 921 #define VDC50GR2_AB8 VDC50.GR2_AB8
bogdanm 92:4fc01daae5a5 922 #define VDC50GR2_AB9 VDC50.GR2_AB9
bogdanm 92:4fc01daae5a5 923 #define VDC50GR2_AB10 VDC50.GR2_AB10
bogdanm 92:4fc01daae5a5 924 #define VDC50GR2_AB11 VDC50.GR2_AB11
bogdanm 92:4fc01daae5a5 925 #define VDC50GR2_BASE VDC50.GR2_BASE
bogdanm 92:4fc01daae5a5 926 #define VDC50GR2_CLUT VDC50.GR2_CLUT
bogdanm 92:4fc01daae5a5 927 #define VDC50GR2_MON VDC50.GR2_MON
bogdanm 92:4fc01daae5a5 928 #define VDC50GR3_UPDATE VDC50.GR3_UPDATE
bogdanm 92:4fc01daae5a5 929 #define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
bogdanm 92:4fc01daae5a5 930 #define VDC50GR3_FLM1 VDC50.GR3_FLM1
bogdanm 92:4fc01daae5a5 931 #define VDC50GR3_FLM2 VDC50.GR3_FLM2
bogdanm 92:4fc01daae5a5 932 #define VDC50GR3_FLM3 VDC50.GR3_FLM3
bogdanm 92:4fc01daae5a5 933 #define VDC50GR3_FLM4 VDC50.GR3_FLM4
bogdanm 92:4fc01daae5a5 934 #define VDC50GR3_FLM5 VDC50.GR3_FLM5
bogdanm 92:4fc01daae5a5 935 #define VDC50GR3_FLM6 VDC50.GR3_FLM6
bogdanm 92:4fc01daae5a5 936 #define VDC50GR3_AB1 VDC50.GR3_AB1
bogdanm 92:4fc01daae5a5 937 #define VDC50GR3_AB2 VDC50.GR3_AB2
bogdanm 92:4fc01daae5a5 938 #define VDC50GR3_AB3 VDC50.GR3_AB3
bogdanm 92:4fc01daae5a5 939 #define VDC50GR3_AB4 VDC50.GR3_AB4
bogdanm 92:4fc01daae5a5 940 #define VDC50GR3_AB5 VDC50.GR3_AB5
bogdanm 92:4fc01daae5a5 941 #define VDC50GR3_AB6 VDC50.GR3_AB6
bogdanm 92:4fc01daae5a5 942 #define VDC50GR3_AB7 VDC50.GR3_AB7
bogdanm 92:4fc01daae5a5 943 #define VDC50GR3_AB8 VDC50.GR3_AB8
bogdanm 92:4fc01daae5a5 944 #define VDC50GR3_AB9 VDC50.GR3_AB9
bogdanm 92:4fc01daae5a5 945 #define VDC50GR3_AB10 VDC50.GR3_AB10
bogdanm 92:4fc01daae5a5 946 #define VDC50GR3_AB11 VDC50.GR3_AB11
bogdanm 92:4fc01daae5a5 947 #define VDC50GR3_BASE VDC50.GR3_BASE
bogdanm 92:4fc01daae5a5 948 #define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
bogdanm 92:4fc01daae5a5 949 #define VDC50GR3_MON VDC50.GR3_MON
bogdanm 92:4fc01daae5a5 950 #define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
bogdanm 92:4fc01daae5a5 951 #define VDC50GAM_SW VDC50.GAM_SW
bogdanm 92:4fc01daae5a5 952 #define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
bogdanm 92:4fc01daae5a5 953 #define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
bogdanm 92:4fc01daae5a5 954 #define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
bogdanm 92:4fc01daae5a5 955 #define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
bogdanm 92:4fc01daae5a5 956 #define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
bogdanm 92:4fc01daae5a5 957 #define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
bogdanm 92:4fc01daae5a5 958 #define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
bogdanm 92:4fc01daae5a5 959 #define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
bogdanm 92:4fc01daae5a5 960 #define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
bogdanm 92:4fc01daae5a5 961 #define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
bogdanm 92:4fc01daae5a5 962 #define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
bogdanm 92:4fc01daae5a5 963 #define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
bogdanm 92:4fc01daae5a5 964 #define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
bogdanm 92:4fc01daae5a5 965 #define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
bogdanm 92:4fc01daae5a5 966 #define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
bogdanm 92:4fc01daae5a5 967 #define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
bogdanm 92:4fc01daae5a5 968 #define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
bogdanm 92:4fc01daae5a5 969 #define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
bogdanm 92:4fc01daae5a5 970 #define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
bogdanm 92:4fc01daae5a5 971 #define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
bogdanm 92:4fc01daae5a5 972 #define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
bogdanm 92:4fc01daae5a5 973 #define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
bogdanm 92:4fc01daae5a5 974 #define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
bogdanm 92:4fc01daae5a5 975 #define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
bogdanm 92:4fc01daae5a5 976 #define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
bogdanm 92:4fc01daae5a5 977 #define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
bogdanm 92:4fc01daae5a5 978 #define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
bogdanm 92:4fc01daae5a5 979 #define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
bogdanm 92:4fc01daae5a5 980 #define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
bogdanm 92:4fc01daae5a5 981 #define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
bogdanm 92:4fc01daae5a5 982 #define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
bogdanm 92:4fc01daae5a5 983 #define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
bogdanm 92:4fc01daae5a5 984 #define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
bogdanm 92:4fc01daae5a5 985 #define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
bogdanm 92:4fc01daae5a5 986 #define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
bogdanm 92:4fc01daae5a5 987 #define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
bogdanm 92:4fc01daae5a5 988 #define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
bogdanm 92:4fc01daae5a5 989 #define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
bogdanm 92:4fc01daae5a5 990 #define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
bogdanm 92:4fc01daae5a5 991 #define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
bogdanm 92:4fc01daae5a5 992 #define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
bogdanm 92:4fc01daae5a5 993 #define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
bogdanm 92:4fc01daae5a5 994 #define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
bogdanm 92:4fc01daae5a5 995 #define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
bogdanm 92:4fc01daae5a5 996 #define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
bogdanm 92:4fc01daae5a5 997 #define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
bogdanm 92:4fc01daae5a5 998 #define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
bogdanm 92:4fc01daae5a5 999 #define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
bogdanm 92:4fc01daae5a5 1000 #define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
bogdanm 92:4fc01daae5a5 1001 #define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
bogdanm 92:4fc01daae5a5 1002 #define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
bogdanm 92:4fc01daae5a5 1003 #define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
bogdanm 92:4fc01daae5a5 1004 #define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
bogdanm 92:4fc01daae5a5 1005 #define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
bogdanm 92:4fc01daae5a5 1006 #define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
bogdanm 92:4fc01daae5a5 1007 #define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
bogdanm 92:4fc01daae5a5 1008 #define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
bogdanm 92:4fc01daae5a5 1009 #define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
bogdanm 92:4fc01daae5a5 1010 #define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
bogdanm 92:4fc01daae5a5 1011 #define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
bogdanm 92:4fc01daae5a5 1012 #define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
bogdanm 92:4fc01daae5a5 1013 #define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
bogdanm 92:4fc01daae5a5 1014 #define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
bogdanm 92:4fc01daae5a5 1015 #define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
bogdanm 92:4fc01daae5a5 1016 #define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
bogdanm 92:4fc01daae5a5 1017 #define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
bogdanm 92:4fc01daae5a5 1018 #define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
bogdanm 92:4fc01daae5a5 1019 #define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
bogdanm 92:4fc01daae5a5 1020 #define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
bogdanm 92:4fc01daae5a5 1021 #define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
bogdanm 92:4fc01daae5a5 1022 #define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
bogdanm 92:4fc01daae5a5 1023 #define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
bogdanm 92:4fc01daae5a5 1024 #define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
bogdanm 92:4fc01daae5a5 1025 #define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
bogdanm 92:4fc01daae5a5 1026 #define VDC50TCON_UPDATE VDC50.TCON_UPDATE
bogdanm 92:4fc01daae5a5 1027 #define VDC50TCON_TIM VDC50.TCON_TIM
bogdanm 92:4fc01daae5a5 1028 #define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
bogdanm 92:4fc01daae5a5 1029 #define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
bogdanm 92:4fc01daae5a5 1030 #define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
bogdanm 92:4fc01daae5a5 1031 #define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
bogdanm 92:4fc01daae5a5 1032 #define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
bogdanm 92:4fc01daae5a5 1033 #define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
bogdanm 92:4fc01daae5a5 1034 #define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
bogdanm 92:4fc01daae5a5 1035 #define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
bogdanm 92:4fc01daae5a5 1036 #define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
bogdanm 92:4fc01daae5a5 1037 #define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
bogdanm 92:4fc01daae5a5 1038 #define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
bogdanm 92:4fc01daae5a5 1039 #define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
bogdanm 92:4fc01daae5a5 1040 #define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
bogdanm 92:4fc01daae5a5 1041 #define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
bogdanm 92:4fc01daae5a5 1042 #define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
bogdanm 92:4fc01daae5a5 1043 #define VDC50OUT_UPDATE VDC50.OUT_UPDATE
bogdanm 92:4fc01daae5a5 1044 #define VDC50OUT_SET VDC50.OUT_SET
bogdanm 92:4fc01daae5a5 1045 #define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
bogdanm 92:4fc01daae5a5 1046 #define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
bogdanm 92:4fc01daae5a5 1047 #define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
bogdanm 92:4fc01daae5a5 1048 #define VDC50OUT_PDTHA VDC50.OUT_PDTHA
bogdanm 92:4fc01daae5a5 1049 #define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
bogdanm 92:4fc01daae5a5 1050 #define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
bogdanm 92:4fc01daae5a5 1051 #define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
bogdanm 92:4fc01daae5a5 1052 #define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
bogdanm 92:4fc01daae5a5 1053 #define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
bogdanm 92:4fc01daae5a5 1054 #define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
bogdanm 92:4fc01daae5a5 1055 #define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
bogdanm 92:4fc01daae5a5 1056 #define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
bogdanm 92:4fc01daae5a5 1057 #define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
bogdanm 92:4fc01daae5a5 1058 #define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
bogdanm 92:4fc01daae5a5 1059 #define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
bogdanm 92:4fc01daae5a5 1060 #define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
bogdanm 92:4fc01daae5a5 1061 #define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
bogdanm 92:4fc01daae5a5 1062 #define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
bogdanm 92:4fc01daae5a5 1063 #define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
bogdanm 92:4fc01daae5a5 1064 #define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
bogdanm 92:4fc01daae5a5 1065 #define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
bogdanm 92:4fc01daae5a5 1066 #define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
bogdanm 92:4fc01daae5a5 1067 #define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
bogdanm 92:4fc01daae5a5 1068 #define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
bogdanm 92:4fc01daae5a5 1069 #define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
bogdanm 92:4fc01daae5a5 1070 #define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
bogdanm 92:4fc01daae5a5 1071 #define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
bogdanm 92:4fc01daae5a5 1072 #define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
bogdanm 92:4fc01daae5a5 1073 #define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
bogdanm 92:4fc01daae5a5 1074 #define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
bogdanm 92:4fc01daae5a5 1075 #define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
bogdanm 92:4fc01daae5a5 1076 #define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
bogdanm 92:4fc01daae5a5 1077 #define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
bogdanm 92:4fc01daae5a5 1078 #define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
bogdanm 92:4fc01daae5a5 1079 #define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
bogdanm 92:4fc01daae5a5 1080 #define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
bogdanm 92:4fc01daae5a5 1081 #define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
bogdanm 92:4fc01daae5a5 1082 #define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
bogdanm 92:4fc01daae5a5 1083 #define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
bogdanm 92:4fc01daae5a5 1084 #define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
bogdanm 92:4fc01daae5a5 1085 #define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
bogdanm 92:4fc01daae5a5 1086 #define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
bogdanm 92:4fc01daae5a5 1087 #define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
bogdanm 92:4fc01daae5a5 1088 #define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
bogdanm 92:4fc01daae5a5 1089 #define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
bogdanm 92:4fc01daae5a5 1090 #define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
bogdanm 92:4fc01daae5a5 1091 #define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
bogdanm 92:4fc01daae5a5 1092 #define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
bogdanm 92:4fc01daae5a5 1093 #define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
bogdanm 92:4fc01daae5a5 1094 #define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
bogdanm 92:4fc01daae5a5 1095 #define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
bogdanm 92:4fc01daae5a5 1096 #define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
bogdanm 92:4fc01daae5a5 1097 #define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
bogdanm 92:4fc01daae5a5 1098 #define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
bogdanm 92:4fc01daae5a5 1099 #define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
bogdanm 92:4fc01daae5a5 1100 #define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
bogdanm 92:4fc01daae5a5 1101 #define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
bogdanm 92:4fc01daae5a5 1102 #define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
bogdanm 92:4fc01daae5a5 1103 #define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
bogdanm 92:4fc01daae5a5 1104 #define VDC50GR1_UPDATE VDC50.GR1_UPDATE
bogdanm 92:4fc01daae5a5 1105 #define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
bogdanm 92:4fc01daae5a5 1106 #define VDC50GR1_FLM1 VDC50.GR1_FLM1
bogdanm 92:4fc01daae5a5 1107 #define VDC50GR1_FLM2 VDC50.GR1_FLM2
bogdanm 92:4fc01daae5a5 1108 #define VDC50GR1_FLM3 VDC50.GR1_FLM3
bogdanm 92:4fc01daae5a5 1109 #define VDC50GR1_FLM4 VDC50.GR1_FLM4
bogdanm 92:4fc01daae5a5 1110 #define VDC50GR1_FLM5 VDC50.GR1_FLM5
bogdanm 92:4fc01daae5a5 1111 #define VDC50GR1_FLM6 VDC50.GR1_FLM6
bogdanm 92:4fc01daae5a5 1112 #define VDC50GR1_AB1 VDC50.GR1_AB1
bogdanm 92:4fc01daae5a5 1113 #define VDC50GR1_AB2 VDC50.GR1_AB2
bogdanm 92:4fc01daae5a5 1114 #define VDC50GR1_AB3 VDC50.GR1_AB3
bogdanm 92:4fc01daae5a5 1115 #define VDC50GR1_AB4 VDC50.GR1_AB4
bogdanm 92:4fc01daae5a5 1116 #define VDC50GR1_AB5 VDC50.GR1_AB5
bogdanm 92:4fc01daae5a5 1117 #define VDC50GR1_AB6 VDC50.GR1_AB6
bogdanm 92:4fc01daae5a5 1118 #define VDC50GR1_AB7 VDC50.GR1_AB7
bogdanm 92:4fc01daae5a5 1119 #define VDC50GR1_AB8 VDC50.GR1_AB8
bogdanm 92:4fc01daae5a5 1120 #define VDC50GR1_AB9 VDC50.GR1_AB9
bogdanm 92:4fc01daae5a5 1121 #define VDC50GR1_AB10 VDC50.GR1_AB10
bogdanm 92:4fc01daae5a5 1122 #define VDC50GR1_AB11 VDC50.GR1_AB11
bogdanm 92:4fc01daae5a5 1123 #define VDC50GR1_BASE VDC50.GR1_BASE
bogdanm 92:4fc01daae5a5 1124 #define VDC50GR1_CLUT VDC50.GR1_CLUT
bogdanm 92:4fc01daae5a5 1125 #define VDC50GR1_MON VDC50.GR1_MON
bogdanm 92:4fc01daae5a5 1126 #define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
bogdanm 92:4fc01daae5a5 1127 #define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
bogdanm 92:4fc01daae5a5 1128 #define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
bogdanm 92:4fc01daae5a5 1129 #define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
bogdanm 92:4fc01daae5a5 1130 #define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
bogdanm 92:4fc01daae5a5 1131 #define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
bogdanm 92:4fc01daae5a5 1132 #define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
bogdanm 92:4fc01daae5a5 1133 #define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
bogdanm 92:4fc01daae5a5 1134 #define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
bogdanm 92:4fc01daae5a5 1135 #define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
bogdanm 92:4fc01daae5a5 1136 #define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
bogdanm 92:4fc01daae5a5 1137 #define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
bogdanm 92:4fc01daae5a5 1138 #define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
bogdanm 92:4fc01daae5a5 1139 #define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
bogdanm 92:4fc01daae5a5 1140 #define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
bogdanm 92:4fc01daae5a5 1141 #define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
bogdanm 92:4fc01daae5a5 1142 #define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
bogdanm 92:4fc01daae5a5 1143 #define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
bogdanm 92:4fc01daae5a5 1144 #define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
bogdanm 92:4fc01daae5a5 1145 #define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
bogdanm 92:4fc01daae5a5 1146 #define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
bogdanm 92:4fc01daae5a5 1147 #define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
bogdanm 92:4fc01daae5a5 1148 #define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
bogdanm 92:4fc01daae5a5 1149 #define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
bogdanm 92:4fc01daae5a5 1150 #define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
bogdanm 92:4fc01daae5a5 1151 #define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
bogdanm 92:4fc01daae5a5 1152 #define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
bogdanm 92:4fc01daae5a5 1153 #define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
bogdanm 92:4fc01daae5a5 1154 #define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
bogdanm 92:4fc01daae5a5 1155 #define VDC50GR_VIN_MON VDC50.GR_VIN_MON
bogdanm 92:4fc01daae5a5 1156 #define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
bogdanm 92:4fc01daae5a5 1157 #define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
bogdanm 92:4fc01daae5a5 1158 #define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
bogdanm 92:4fc01daae5a5 1159 #define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
bogdanm 92:4fc01daae5a5 1160 #define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
bogdanm 92:4fc01daae5a5 1161 #define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
bogdanm 92:4fc01daae5a5 1162 #define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
bogdanm 92:4fc01daae5a5 1163 #define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
bogdanm 92:4fc01daae5a5 1164 #define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
bogdanm 92:4fc01daae5a5 1165 #define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
bogdanm 92:4fc01daae5a5 1166 #define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
bogdanm 92:4fc01daae5a5 1167 #define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
bogdanm 92:4fc01daae5a5 1168 #define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
bogdanm 92:4fc01daae5a5 1169 #define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
bogdanm 92:4fc01daae5a5 1170 #define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
bogdanm 92:4fc01daae5a5 1171 #define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
bogdanm 92:4fc01daae5a5 1172 #define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
bogdanm 92:4fc01daae5a5 1173 #define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
bogdanm 92:4fc01daae5a5 1174 #define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
bogdanm 92:4fc01daae5a5 1175 #define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
bogdanm 92:4fc01daae5a5 1176 #define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
bogdanm 92:4fc01daae5a5 1177 #define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
bogdanm 92:4fc01daae5a5 1178 #define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
bogdanm 92:4fc01daae5a5 1179 #define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
bogdanm 92:4fc01daae5a5 1180 #define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
bogdanm 92:4fc01daae5a5 1181 #define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
bogdanm 92:4fc01daae5a5 1182 #define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
bogdanm 92:4fc01daae5a5 1183 #define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
bogdanm 92:4fc01daae5a5 1184 #define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
bogdanm 92:4fc01daae5a5 1185 #define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
bogdanm 92:4fc01daae5a5 1186 #define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
bogdanm 92:4fc01daae5a5 1187 #define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
bogdanm 92:4fc01daae5a5 1188 #define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
bogdanm 92:4fc01daae5a5 1189 #define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
bogdanm 92:4fc01daae5a5 1190 #define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
bogdanm 92:4fc01daae5a5 1191 #define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
bogdanm 92:4fc01daae5a5 1192 #define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
bogdanm 92:4fc01daae5a5 1193 #define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
bogdanm 92:4fc01daae5a5 1194 #define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
bogdanm 92:4fc01daae5a5 1195 #define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
bogdanm 92:4fc01daae5a5 1196 #define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
bogdanm 92:4fc01daae5a5 1197 #define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
bogdanm 92:4fc01daae5a5 1198 #define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
bogdanm 92:4fc01daae5a5 1199 #define VDC50GR_OIR_MON VDC50.GR_OIR_MON
bogdanm 92:4fc01daae5a5 1200 #define VDC51INP_UPDATE VDC51.INP_UPDATE
bogdanm 92:4fc01daae5a5 1201 #define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
bogdanm 92:4fc01daae5a5 1202 #define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
bogdanm 92:4fc01daae5a5 1203 #define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
bogdanm 92:4fc01daae5a5 1204 #define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
bogdanm 92:4fc01daae5a5 1205 #define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
bogdanm 92:4fc01daae5a5 1206 #define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
bogdanm 92:4fc01daae5a5 1207 #define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
bogdanm 92:4fc01daae5a5 1208 #define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
bogdanm 92:4fc01daae5a5 1209 #define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
bogdanm 92:4fc01daae5a5 1210 #define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
bogdanm 92:4fc01daae5a5 1211 #define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
bogdanm 92:4fc01daae5a5 1212 #define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
bogdanm 92:4fc01daae5a5 1213 #define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
bogdanm 92:4fc01daae5a5 1214 #define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
bogdanm 92:4fc01daae5a5 1215 #define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
bogdanm 92:4fc01daae5a5 1216 #define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
bogdanm 92:4fc01daae5a5 1217 #define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
bogdanm 92:4fc01daae5a5 1218 #define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
bogdanm 92:4fc01daae5a5 1219 #define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
bogdanm 92:4fc01daae5a5 1220 #define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
bogdanm 92:4fc01daae5a5 1221 #define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
bogdanm 92:4fc01daae5a5 1222 #define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
bogdanm 92:4fc01daae5a5 1223 #define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
bogdanm 92:4fc01daae5a5 1224 #define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
bogdanm 92:4fc01daae5a5 1225 #define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
bogdanm 92:4fc01daae5a5 1226 #define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
bogdanm 92:4fc01daae5a5 1227 #define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
bogdanm 92:4fc01daae5a5 1228 #define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
bogdanm 92:4fc01daae5a5 1229 #define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
bogdanm 92:4fc01daae5a5 1230 #define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
bogdanm 92:4fc01daae5a5 1231 #define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
bogdanm 92:4fc01daae5a5 1232 #define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
bogdanm 92:4fc01daae5a5 1233 #define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
bogdanm 92:4fc01daae5a5 1234 #define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
bogdanm 92:4fc01daae5a5 1235 #define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
bogdanm 92:4fc01daae5a5 1236 #define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
bogdanm 92:4fc01daae5a5 1237 #define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
bogdanm 92:4fc01daae5a5 1238 #define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
bogdanm 92:4fc01daae5a5 1239 #define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
bogdanm 92:4fc01daae5a5 1240 #define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
bogdanm 92:4fc01daae5a5 1241 #define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
bogdanm 92:4fc01daae5a5 1242 #define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
bogdanm 92:4fc01daae5a5 1243 #define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
bogdanm 92:4fc01daae5a5 1244 #define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
bogdanm 92:4fc01daae5a5 1245 #define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
bogdanm 92:4fc01daae5a5 1246 #define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
bogdanm 92:4fc01daae5a5 1247 #define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
bogdanm 92:4fc01daae5a5 1248 #define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
bogdanm 92:4fc01daae5a5 1249 #define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
bogdanm 92:4fc01daae5a5 1250 #define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
bogdanm 92:4fc01daae5a5 1251 #define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
bogdanm 92:4fc01daae5a5 1252 #define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
bogdanm 92:4fc01daae5a5 1253 #define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
bogdanm 92:4fc01daae5a5 1254 #define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
bogdanm 92:4fc01daae5a5 1255 #define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
bogdanm 92:4fc01daae5a5 1256 #define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
bogdanm 92:4fc01daae5a5 1257 #define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
bogdanm 92:4fc01daae5a5 1258 #define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
bogdanm 92:4fc01daae5a5 1259 #define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
bogdanm 92:4fc01daae5a5 1260 #define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
bogdanm 92:4fc01daae5a5 1261 #define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
bogdanm 92:4fc01daae5a5 1262 #define VDC51GR0_UPDATE VDC51.GR0_UPDATE
bogdanm 92:4fc01daae5a5 1263 #define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
bogdanm 92:4fc01daae5a5 1264 #define VDC51GR0_FLM1 VDC51.GR0_FLM1
bogdanm 92:4fc01daae5a5 1265 #define VDC51GR0_FLM2 VDC51.GR0_FLM2
bogdanm 92:4fc01daae5a5 1266 #define VDC51GR0_FLM3 VDC51.GR0_FLM3
bogdanm 92:4fc01daae5a5 1267 #define VDC51GR0_FLM4 VDC51.GR0_FLM4
bogdanm 92:4fc01daae5a5 1268 #define VDC51GR0_FLM5 VDC51.GR0_FLM5
bogdanm 92:4fc01daae5a5 1269 #define VDC51GR0_FLM6 VDC51.GR0_FLM6
bogdanm 92:4fc01daae5a5 1270 #define VDC51GR0_AB1 VDC51.GR0_AB1
bogdanm 92:4fc01daae5a5 1271 #define VDC51GR0_AB2 VDC51.GR0_AB2
bogdanm 92:4fc01daae5a5 1272 #define VDC51GR0_AB3 VDC51.GR0_AB3
bogdanm 92:4fc01daae5a5 1273 #define VDC51GR0_AB7 VDC51.GR0_AB7
bogdanm 92:4fc01daae5a5 1274 #define VDC51GR0_AB8 VDC51.GR0_AB8
bogdanm 92:4fc01daae5a5 1275 #define VDC51GR0_AB9 VDC51.GR0_AB9
bogdanm 92:4fc01daae5a5 1276 #define VDC51GR0_AB10 VDC51.GR0_AB10
bogdanm 92:4fc01daae5a5 1277 #define VDC51GR0_AB11 VDC51.GR0_AB11
bogdanm 92:4fc01daae5a5 1278 #define VDC51GR0_BASE VDC51.GR0_BASE
bogdanm 92:4fc01daae5a5 1279 #define VDC51GR0_CLUT VDC51.GR0_CLUT
bogdanm 92:4fc01daae5a5 1280 #define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
bogdanm 92:4fc01daae5a5 1281 #define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
bogdanm 92:4fc01daae5a5 1282 #define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
bogdanm 92:4fc01daae5a5 1283 #define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
bogdanm 92:4fc01daae5a5 1284 #define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
bogdanm 92:4fc01daae5a5 1285 #define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
bogdanm 92:4fc01daae5a5 1286 #define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
bogdanm 92:4fc01daae5a5 1287 #define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
bogdanm 92:4fc01daae5a5 1288 #define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
bogdanm 92:4fc01daae5a5 1289 #define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
bogdanm 92:4fc01daae5a5 1290 #define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
bogdanm 92:4fc01daae5a5 1291 #define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
bogdanm 92:4fc01daae5a5 1292 #define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
bogdanm 92:4fc01daae5a5 1293 #define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
bogdanm 92:4fc01daae5a5 1294 #define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
bogdanm 92:4fc01daae5a5 1295 #define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
bogdanm 92:4fc01daae5a5 1296 #define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
bogdanm 92:4fc01daae5a5 1297 #define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
bogdanm 92:4fc01daae5a5 1298 #define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
bogdanm 92:4fc01daae5a5 1299 #define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
bogdanm 92:4fc01daae5a5 1300 #define VDC51GR2_UPDATE VDC51.GR2_UPDATE
bogdanm 92:4fc01daae5a5 1301 #define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
bogdanm 92:4fc01daae5a5 1302 #define VDC51GR2_FLM1 VDC51.GR2_FLM1
bogdanm 92:4fc01daae5a5 1303 #define VDC51GR2_FLM2 VDC51.GR2_FLM2
bogdanm 92:4fc01daae5a5 1304 #define VDC51GR2_FLM3 VDC51.GR2_FLM3
bogdanm 92:4fc01daae5a5 1305 #define VDC51GR2_FLM4 VDC51.GR2_FLM4
bogdanm 92:4fc01daae5a5 1306 #define VDC51GR2_FLM5 VDC51.GR2_FLM5
bogdanm 92:4fc01daae5a5 1307 #define VDC51GR2_FLM6 VDC51.GR2_FLM6
bogdanm 92:4fc01daae5a5 1308 #define VDC51GR2_AB1 VDC51.GR2_AB1
bogdanm 92:4fc01daae5a5 1309 #define VDC51GR2_AB2 VDC51.GR2_AB2
bogdanm 92:4fc01daae5a5 1310 #define VDC51GR2_AB3 VDC51.GR2_AB3
bogdanm 92:4fc01daae5a5 1311 #define VDC51GR2_AB4 VDC51.GR2_AB4
bogdanm 92:4fc01daae5a5 1312 #define VDC51GR2_AB5 VDC51.GR2_AB5
bogdanm 92:4fc01daae5a5 1313 #define VDC51GR2_AB6 VDC51.GR2_AB6
bogdanm 92:4fc01daae5a5 1314 #define VDC51GR2_AB7 VDC51.GR2_AB7
bogdanm 92:4fc01daae5a5 1315 #define VDC51GR2_AB8 VDC51.GR2_AB8
bogdanm 92:4fc01daae5a5 1316 #define VDC51GR2_AB9 VDC51.GR2_AB9
bogdanm 92:4fc01daae5a5 1317 #define VDC51GR2_AB10 VDC51.GR2_AB10
bogdanm 92:4fc01daae5a5 1318 #define VDC51GR2_AB11 VDC51.GR2_AB11
bogdanm 92:4fc01daae5a5 1319 #define VDC51GR2_BASE VDC51.GR2_BASE
bogdanm 92:4fc01daae5a5 1320 #define VDC51GR2_CLUT VDC51.GR2_CLUT
bogdanm 92:4fc01daae5a5 1321 #define VDC51GR2_MON VDC51.GR2_MON
bogdanm 92:4fc01daae5a5 1322 #define VDC51GR3_UPDATE VDC51.GR3_UPDATE
bogdanm 92:4fc01daae5a5 1323 #define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
bogdanm 92:4fc01daae5a5 1324 #define VDC51GR3_FLM1 VDC51.GR3_FLM1
bogdanm 92:4fc01daae5a5 1325 #define VDC51GR3_FLM2 VDC51.GR3_FLM2
bogdanm 92:4fc01daae5a5 1326 #define VDC51GR3_FLM3 VDC51.GR3_FLM3
bogdanm 92:4fc01daae5a5 1327 #define VDC51GR3_FLM4 VDC51.GR3_FLM4
bogdanm 92:4fc01daae5a5 1328 #define VDC51GR3_FLM5 VDC51.GR3_FLM5
bogdanm 92:4fc01daae5a5 1329 #define VDC51GR3_FLM6 VDC51.GR3_FLM6
bogdanm 92:4fc01daae5a5 1330 #define VDC51GR3_AB1 VDC51.GR3_AB1
bogdanm 92:4fc01daae5a5 1331 #define VDC51GR3_AB2 VDC51.GR3_AB2
bogdanm 92:4fc01daae5a5 1332 #define VDC51GR3_AB3 VDC51.GR3_AB3
bogdanm 92:4fc01daae5a5 1333 #define VDC51GR3_AB4 VDC51.GR3_AB4
bogdanm 92:4fc01daae5a5 1334 #define VDC51GR3_AB5 VDC51.GR3_AB5
bogdanm 92:4fc01daae5a5 1335 #define VDC51GR3_AB6 VDC51.GR3_AB6
bogdanm 92:4fc01daae5a5 1336 #define VDC51GR3_AB7 VDC51.GR3_AB7
bogdanm 92:4fc01daae5a5 1337 #define VDC51GR3_AB8 VDC51.GR3_AB8
bogdanm 92:4fc01daae5a5 1338 #define VDC51GR3_AB9 VDC51.GR3_AB9
bogdanm 92:4fc01daae5a5 1339 #define VDC51GR3_AB10 VDC51.GR3_AB10
bogdanm 92:4fc01daae5a5 1340 #define VDC51GR3_AB11 VDC51.GR3_AB11
bogdanm 92:4fc01daae5a5 1341 #define VDC51GR3_BASE VDC51.GR3_BASE
bogdanm 92:4fc01daae5a5 1342 #define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
bogdanm 92:4fc01daae5a5 1343 #define VDC51GR3_MON VDC51.GR3_MON
bogdanm 92:4fc01daae5a5 1344 #define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
bogdanm 92:4fc01daae5a5 1345 #define VDC51GAM_SW VDC51.GAM_SW
bogdanm 92:4fc01daae5a5 1346 #define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
bogdanm 92:4fc01daae5a5 1347 #define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
bogdanm 92:4fc01daae5a5 1348 #define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
bogdanm 92:4fc01daae5a5 1349 #define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
bogdanm 92:4fc01daae5a5 1350 #define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
bogdanm 92:4fc01daae5a5 1351 #define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
bogdanm 92:4fc01daae5a5 1352 #define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
bogdanm 92:4fc01daae5a5 1353 #define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
bogdanm 92:4fc01daae5a5 1354 #define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
bogdanm 92:4fc01daae5a5 1355 #define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
bogdanm 92:4fc01daae5a5 1356 #define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
bogdanm 92:4fc01daae5a5 1357 #define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
bogdanm 92:4fc01daae5a5 1358 #define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
bogdanm 92:4fc01daae5a5 1359 #define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
bogdanm 92:4fc01daae5a5 1360 #define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
bogdanm 92:4fc01daae5a5 1361 #define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
bogdanm 92:4fc01daae5a5 1362 #define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
bogdanm 92:4fc01daae5a5 1363 #define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
bogdanm 92:4fc01daae5a5 1364 #define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
bogdanm 92:4fc01daae5a5 1365 #define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
bogdanm 92:4fc01daae5a5 1366 #define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
bogdanm 92:4fc01daae5a5 1367 #define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
bogdanm 92:4fc01daae5a5 1368 #define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
bogdanm 92:4fc01daae5a5 1369 #define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
bogdanm 92:4fc01daae5a5 1370 #define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
bogdanm 92:4fc01daae5a5 1371 #define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
bogdanm 92:4fc01daae5a5 1372 #define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
bogdanm 92:4fc01daae5a5 1373 #define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
bogdanm 92:4fc01daae5a5 1374 #define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
bogdanm 92:4fc01daae5a5 1375 #define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
bogdanm 92:4fc01daae5a5 1376 #define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
bogdanm 92:4fc01daae5a5 1377 #define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
bogdanm 92:4fc01daae5a5 1378 #define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
bogdanm 92:4fc01daae5a5 1379 #define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
bogdanm 92:4fc01daae5a5 1380 #define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
bogdanm 92:4fc01daae5a5 1381 #define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
bogdanm 92:4fc01daae5a5 1382 #define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
bogdanm 92:4fc01daae5a5 1383 #define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
bogdanm 92:4fc01daae5a5 1384 #define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
bogdanm 92:4fc01daae5a5 1385 #define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
bogdanm 92:4fc01daae5a5 1386 #define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
bogdanm 92:4fc01daae5a5 1387 #define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
bogdanm 92:4fc01daae5a5 1388 #define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
bogdanm 92:4fc01daae5a5 1389 #define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
bogdanm 92:4fc01daae5a5 1390 #define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
bogdanm 92:4fc01daae5a5 1391 #define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
bogdanm 92:4fc01daae5a5 1392 #define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
bogdanm 92:4fc01daae5a5 1393 #define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
bogdanm 92:4fc01daae5a5 1394 #define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
bogdanm 92:4fc01daae5a5 1395 #define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
bogdanm 92:4fc01daae5a5 1396 #define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
bogdanm 92:4fc01daae5a5 1397 #define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
bogdanm 92:4fc01daae5a5 1398 #define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
bogdanm 92:4fc01daae5a5 1399 #define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
bogdanm 92:4fc01daae5a5 1400 #define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
bogdanm 92:4fc01daae5a5 1401 #define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
bogdanm 92:4fc01daae5a5 1402 #define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
bogdanm 92:4fc01daae5a5 1403 #define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
bogdanm 92:4fc01daae5a5 1404 #define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
bogdanm 92:4fc01daae5a5 1405 #define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
bogdanm 92:4fc01daae5a5 1406 #define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
bogdanm 92:4fc01daae5a5 1407 #define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
bogdanm 92:4fc01daae5a5 1408 #define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
bogdanm 92:4fc01daae5a5 1409 #define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
bogdanm 92:4fc01daae5a5 1410 #define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
bogdanm 92:4fc01daae5a5 1411 #define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
bogdanm 92:4fc01daae5a5 1412 #define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
bogdanm 92:4fc01daae5a5 1413 #define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
bogdanm 92:4fc01daae5a5 1414 #define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
bogdanm 92:4fc01daae5a5 1415 #define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
bogdanm 92:4fc01daae5a5 1416 #define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
bogdanm 92:4fc01daae5a5 1417 #define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
bogdanm 92:4fc01daae5a5 1418 #define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
bogdanm 92:4fc01daae5a5 1419 #define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
bogdanm 92:4fc01daae5a5 1420 #define VDC51TCON_UPDATE VDC51.TCON_UPDATE
bogdanm 92:4fc01daae5a5 1421 #define VDC51TCON_TIM VDC51.TCON_TIM
bogdanm 92:4fc01daae5a5 1422 #define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
bogdanm 92:4fc01daae5a5 1423 #define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
bogdanm 92:4fc01daae5a5 1424 #define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
bogdanm 92:4fc01daae5a5 1425 #define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
bogdanm 92:4fc01daae5a5 1426 #define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
bogdanm 92:4fc01daae5a5 1427 #define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
bogdanm 92:4fc01daae5a5 1428 #define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
bogdanm 92:4fc01daae5a5 1429 #define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
bogdanm 92:4fc01daae5a5 1430 #define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
bogdanm 92:4fc01daae5a5 1431 #define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
bogdanm 92:4fc01daae5a5 1432 #define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
bogdanm 92:4fc01daae5a5 1433 #define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
bogdanm 92:4fc01daae5a5 1434 #define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
bogdanm 92:4fc01daae5a5 1435 #define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
bogdanm 92:4fc01daae5a5 1436 #define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
bogdanm 92:4fc01daae5a5 1437 #define VDC51OUT_UPDATE VDC51.OUT_UPDATE
bogdanm 92:4fc01daae5a5 1438 #define VDC51OUT_SET VDC51.OUT_SET
bogdanm 92:4fc01daae5a5 1439 #define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
bogdanm 92:4fc01daae5a5 1440 #define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
bogdanm 92:4fc01daae5a5 1441 #define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
bogdanm 92:4fc01daae5a5 1442 #define VDC51OUT_PDTHA VDC51.OUT_PDTHA
bogdanm 92:4fc01daae5a5 1443 #define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
bogdanm 92:4fc01daae5a5 1444 #define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
bogdanm 92:4fc01daae5a5 1445 #define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
bogdanm 92:4fc01daae5a5 1446 #define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
bogdanm 92:4fc01daae5a5 1447 #define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
bogdanm 92:4fc01daae5a5 1448 #define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
bogdanm 92:4fc01daae5a5 1449 #define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
bogdanm 92:4fc01daae5a5 1450 #define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
bogdanm 92:4fc01daae5a5 1451 #define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
bogdanm 92:4fc01daae5a5 1452 #define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
bogdanm 92:4fc01daae5a5 1453 #define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
bogdanm 92:4fc01daae5a5 1454 #define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
bogdanm 92:4fc01daae5a5 1455 #define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
bogdanm 92:4fc01daae5a5 1456 #define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
bogdanm 92:4fc01daae5a5 1457 #define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
bogdanm 92:4fc01daae5a5 1458 #define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
bogdanm 92:4fc01daae5a5 1459 #define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
bogdanm 92:4fc01daae5a5 1460 #define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
bogdanm 92:4fc01daae5a5 1461 #define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
bogdanm 92:4fc01daae5a5 1462 #define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
bogdanm 92:4fc01daae5a5 1463 #define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
bogdanm 92:4fc01daae5a5 1464 #define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
bogdanm 92:4fc01daae5a5 1465 #define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
bogdanm 92:4fc01daae5a5 1466 #define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
bogdanm 92:4fc01daae5a5 1467 #define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
bogdanm 92:4fc01daae5a5 1468 #define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
bogdanm 92:4fc01daae5a5 1469 #define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
bogdanm 92:4fc01daae5a5 1470 #define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
bogdanm 92:4fc01daae5a5 1471 #define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
bogdanm 92:4fc01daae5a5 1472 #define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
bogdanm 92:4fc01daae5a5 1473 #define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
bogdanm 92:4fc01daae5a5 1474 #define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
bogdanm 92:4fc01daae5a5 1475 #define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
bogdanm 92:4fc01daae5a5 1476 #define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
bogdanm 92:4fc01daae5a5 1477 #define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
bogdanm 92:4fc01daae5a5 1478 #define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
bogdanm 92:4fc01daae5a5 1479 #define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
bogdanm 92:4fc01daae5a5 1480 #define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
bogdanm 92:4fc01daae5a5 1481 #define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
bogdanm 92:4fc01daae5a5 1482 #define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
bogdanm 92:4fc01daae5a5 1483 #define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
bogdanm 92:4fc01daae5a5 1484 #define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
bogdanm 92:4fc01daae5a5 1485 #define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
bogdanm 92:4fc01daae5a5 1486 #define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
bogdanm 92:4fc01daae5a5 1487 #define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
bogdanm 92:4fc01daae5a5 1488 #define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
bogdanm 92:4fc01daae5a5 1489 #define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
bogdanm 92:4fc01daae5a5 1490 #define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
bogdanm 92:4fc01daae5a5 1491 #define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
bogdanm 92:4fc01daae5a5 1492 #define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
bogdanm 92:4fc01daae5a5 1493 #define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
bogdanm 92:4fc01daae5a5 1494 #define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
bogdanm 92:4fc01daae5a5 1495 #define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
bogdanm 92:4fc01daae5a5 1496 #define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
bogdanm 92:4fc01daae5a5 1497 #define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
bogdanm 92:4fc01daae5a5 1498 #define VDC51GR1_UPDATE VDC51.GR1_UPDATE
bogdanm 92:4fc01daae5a5 1499 #define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
bogdanm 92:4fc01daae5a5 1500 #define VDC51GR1_FLM1 VDC51.GR1_FLM1
bogdanm 92:4fc01daae5a5 1501 #define VDC51GR1_FLM2 VDC51.GR1_FLM2
bogdanm 92:4fc01daae5a5 1502 #define VDC51GR1_FLM3 VDC51.GR1_FLM3
bogdanm 92:4fc01daae5a5 1503 #define VDC51GR1_FLM4 VDC51.GR1_FLM4
bogdanm 92:4fc01daae5a5 1504 #define VDC51GR1_FLM5 VDC51.GR1_FLM5
bogdanm 92:4fc01daae5a5 1505 #define VDC51GR1_FLM6 VDC51.GR1_FLM6
bogdanm 92:4fc01daae5a5 1506 #define VDC51GR1_AB1 VDC51.GR1_AB1
bogdanm 92:4fc01daae5a5 1507 #define VDC51GR1_AB2 VDC51.GR1_AB2
bogdanm 92:4fc01daae5a5 1508 #define VDC51GR1_AB3 VDC51.GR1_AB3
bogdanm 92:4fc01daae5a5 1509 #define VDC51GR1_AB4 VDC51.GR1_AB4
bogdanm 92:4fc01daae5a5 1510 #define VDC51GR1_AB5 VDC51.GR1_AB5
bogdanm 92:4fc01daae5a5 1511 #define VDC51GR1_AB6 VDC51.GR1_AB6
bogdanm 92:4fc01daae5a5 1512 #define VDC51GR1_AB7 VDC51.GR1_AB7
bogdanm 92:4fc01daae5a5 1513 #define VDC51GR1_AB8 VDC51.GR1_AB8
bogdanm 92:4fc01daae5a5 1514 #define VDC51GR1_AB9 VDC51.GR1_AB9
bogdanm 92:4fc01daae5a5 1515 #define VDC51GR1_AB10 VDC51.GR1_AB10
bogdanm 92:4fc01daae5a5 1516 #define VDC51GR1_AB11 VDC51.GR1_AB11
bogdanm 92:4fc01daae5a5 1517 #define VDC51GR1_BASE VDC51.GR1_BASE
bogdanm 92:4fc01daae5a5 1518 #define VDC51GR1_CLUT VDC51.GR1_CLUT
bogdanm 92:4fc01daae5a5 1519 #define VDC51GR1_MON VDC51.GR1_MON
bogdanm 92:4fc01daae5a5 1520 #define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
bogdanm 92:4fc01daae5a5 1521 #define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
bogdanm 92:4fc01daae5a5 1522 #define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
bogdanm 92:4fc01daae5a5 1523 #define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
bogdanm 92:4fc01daae5a5 1524 #define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
bogdanm 92:4fc01daae5a5 1525 #define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
bogdanm 92:4fc01daae5a5 1526 #define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
bogdanm 92:4fc01daae5a5 1527 #define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
bogdanm 92:4fc01daae5a5 1528 #define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
bogdanm 92:4fc01daae5a5 1529 #define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
bogdanm 92:4fc01daae5a5 1530 #define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
bogdanm 92:4fc01daae5a5 1531 #define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
bogdanm 92:4fc01daae5a5 1532 #define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
bogdanm 92:4fc01daae5a5 1533 #define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
bogdanm 92:4fc01daae5a5 1534 #define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
bogdanm 92:4fc01daae5a5 1535 #define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
bogdanm 92:4fc01daae5a5 1536 #define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
bogdanm 92:4fc01daae5a5 1537 #define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
bogdanm 92:4fc01daae5a5 1538 #define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
bogdanm 92:4fc01daae5a5 1539 #define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
bogdanm 92:4fc01daae5a5 1540 #define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
bogdanm 92:4fc01daae5a5 1541 #define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
bogdanm 92:4fc01daae5a5 1542 #define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
bogdanm 92:4fc01daae5a5 1543 #define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
bogdanm 92:4fc01daae5a5 1544 #define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
bogdanm 92:4fc01daae5a5 1545 #define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
bogdanm 92:4fc01daae5a5 1546 #define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
bogdanm 92:4fc01daae5a5 1547 #define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
bogdanm 92:4fc01daae5a5 1548 #define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
bogdanm 92:4fc01daae5a5 1549 #define VDC51GR_VIN_MON VDC51.GR_VIN_MON
bogdanm 92:4fc01daae5a5 1550 #define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
bogdanm 92:4fc01daae5a5 1551 #define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
bogdanm 92:4fc01daae5a5 1552 #define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
bogdanm 92:4fc01daae5a5 1553 #define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
bogdanm 92:4fc01daae5a5 1554 #define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
bogdanm 92:4fc01daae5a5 1555 #define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
bogdanm 92:4fc01daae5a5 1556 #define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
bogdanm 92:4fc01daae5a5 1557 #define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
bogdanm 92:4fc01daae5a5 1558 #define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
bogdanm 92:4fc01daae5a5 1559 #define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
bogdanm 92:4fc01daae5a5 1560 #define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
bogdanm 92:4fc01daae5a5 1561 #define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
bogdanm 92:4fc01daae5a5 1562 #define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
bogdanm 92:4fc01daae5a5 1563 #define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
bogdanm 92:4fc01daae5a5 1564 #define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
bogdanm 92:4fc01daae5a5 1565 #define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
bogdanm 92:4fc01daae5a5 1566 #define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
bogdanm 92:4fc01daae5a5 1567 #define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
bogdanm 92:4fc01daae5a5 1568 #define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
bogdanm 92:4fc01daae5a5 1569 #define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
bogdanm 92:4fc01daae5a5 1570 #define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
bogdanm 92:4fc01daae5a5 1571 #define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
bogdanm 92:4fc01daae5a5 1572 #define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
bogdanm 92:4fc01daae5a5 1573 #define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
bogdanm 92:4fc01daae5a5 1574 #define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
bogdanm 92:4fc01daae5a5 1575 #define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
bogdanm 92:4fc01daae5a5 1576 #define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
bogdanm 92:4fc01daae5a5 1577 #define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
bogdanm 92:4fc01daae5a5 1578 #define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
bogdanm 92:4fc01daae5a5 1579 #define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
bogdanm 92:4fc01daae5a5 1580 #define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
bogdanm 92:4fc01daae5a5 1581 #define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
bogdanm 92:4fc01daae5a5 1582 #define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
bogdanm 92:4fc01daae5a5 1583 #define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
bogdanm 92:4fc01daae5a5 1584 #define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
bogdanm 92:4fc01daae5a5 1585 #define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
bogdanm 92:4fc01daae5a5 1586 #define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
bogdanm 92:4fc01daae5a5 1587 #define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
bogdanm 92:4fc01daae5a5 1588 #define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
bogdanm 92:4fc01daae5a5 1589 #define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
bogdanm 92:4fc01daae5a5 1590 #define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
bogdanm 92:4fc01daae5a5 1591 #define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
bogdanm 92:4fc01daae5a5 1592 #define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
bogdanm 92:4fc01daae5a5 1593 #define VDC51GR_OIR_MON VDC51.GR_OIR_MON
bogdanm 92:4fc01daae5a5 1594 /* <-SEC M1.10.1 */
bogdanm 92:4fc01daae5a5 1595 /* <-QAC 0639 */
bogdanm 92:4fc01daae5a5 1596 #endif