frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_RZ_A1H/riic_iobitmask.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : riic_iobitmask.h
bogdanm 92:4fc01daae5a5 25 * $Rev: 1114 $
bogdanm 92:4fc01daae5a5 26 * $Date:: 2014-07-09 14:56:39 +0900#$
bogdanm 92:4fc01daae5a5 27 * Description : RIIC register define header
bogdanm 92:4fc01daae5a5 28 *******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef RIIC_IOBITMASK_H
bogdanm 92:4fc01daae5a5 30 #define RIIC_IOBITMASK_H
bogdanm 92:4fc01daae5a5 31
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 /* ==== Mask values for IO registers ==== */
bogdanm 92:4fc01daae5a5 34 #define RIICn_RIICnCR1_SDAI (0x01u)
bogdanm 92:4fc01daae5a5 35 #define RIICn_RIICnCR1_SCLI (0x02u)
bogdanm 92:4fc01daae5a5 36 #define RIICn_RIICnCR1_SDAO (0x04u)
bogdanm 92:4fc01daae5a5 37 #define RIICn_RIICnCR1_SCLO (0x08u)
bogdanm 92:4fc01daae5a5 38 #define RIICn_RIICnCR1_SOWP (0x10u)
bogdanm 92:4fc01daae5a5 39 #define RIICn_RIICnCR1_CLO (0x20u)
bogdanm 92:4fc01daae5a5 40 #define RIICn_RIICnCR1_IICRST (0x40u)
bogdanm 92:4fc01daae5a5 41 #define RIICn_RIICnCR1_ICE (0x80u)
bogdanm 92:4fc01daae5a5 42
bogdanm 92:4fc01daae5a5 43 #define RIICn_RIICnCR2_ST (0x02u)
bogdanm 92:4fc01daae5a5 44 #define RIICn_RIICnCR2_RS (0x04u)
bogdanm 92:4fc01daae5a5 45 #define RIICn_RIICnCR2_SP (0x08u)
bogdanm 92:4fc01daae5a5 46 #define RIICn_RIICnCR2_TRS (0x20u)
bogdanm 92:4fc01daae5a5 47 #define RIICn_RIICnCR2_MST (0x40u)
bogdanm 92:4fc01daae5a5 48 #define RIICn_RIICnCR2_BBSY (0x80u)
bogdanm 92:4fc01daae5a5 49
bogdanm 92:4fc01daae5a5 50 #define RIICn_RIICnMR1_BC (0x07u)
bogdanm 92:4fc01daae5a5 51 #define RIICn_RIICnMR1_BCWP (0x08u)
bogdanm 92:4fc01daae5a5 52 #define RIICn_RIICnMR1_CKS (0x70u)
bogdanm 92:4fc01daae5a5 53 #define RIICn_RIICnMR1_MTWP (0x80u)
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 #define RIICn_RIICnMR2_TMOS (0x01u)
bogdanm 92:4fc01daae5a5 56 #define RIICn_RIICnMR2_TMOL (0x02u)
bogdanm 92:4fc01daae5a5 57 #define RIICn_RIICnMR2_TMOH (0x04u)
bogdanm 92:4fc01daae5a5 58 #define RIICn_RIICnMR2_SDDL (0x70u)
bogdanm 92:4fc01daae5a5 59 #define RIICn_RIICnMR2_DLCS (0x80u)
bogdanm 92:4fc01daae5a5 60
bogdanm 92:4fc01daae5a5 61 #define RIICn_RIICnMR3_NF (0x03u)
bogdanm 92:4fc01daae5a5 62 #define RIICn_RIICnMR3_ACKBR (0x04u)
bogdanm 92:4fc01daae5a5 63 #define RIICn_RIICnMR3_ACKBT (0x08u)
bogdanm 92:4fc01daae5a5 64 #define RIICn_RIICnMR3_ACKWP (0x10u)
bogdanm 92:4fc01daae5a5 65 #define RIICn_RIICnMR3_RDRFS (0x20u)
bogdanm 92:4fc01daae5a5 66 #define RIICn_RIICnMR3_WAIT (0x40u)
bogdanm 92:4fc01daae5a5 67 #define RIICn_RIICnMR3_SMBS (0x80u)
bogdanm 92:4fc01daae5a5 68
bogdanm 92:4fc01daae5a5 69 #define RIICn_RIICnFER_TMOE (0x01u)
bogdanm 92:4fc01daae5a5 70 #define RIICn_RIICnFER_MALE (0x02u)
bogdanm 92:4fc01daae5a5 71 #define RIICn_RIICnFER_NALE (0x04u)
bogdanm 92:4fc01daae5a5 72 #define RIICn_RIICnFER_SALE (0x08u)
bogdanm 92:4fc01daae5a5 73 #define RIICn_RIICnFER_NACKE (0x10u)
bogdanm 92:4fc01daae5a5 74 #define RIICn_RIICnFER_NFE (0x20u)
bogdanm 92:4fc01daae5a5 75 #define RIICn_RIICnFER_SCLE (0x40u)
bogdanm 92:4fc01daae5a5 76 #define RIICn_RIICnFER_FMPE (0x80u)
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 #define RIICn_RIICnSER_SAR0E (0x01u)
bogdanm 92:4fc01daae5a5 79 #define RIICn_RIICnSER_SAR1E (0x02u)
bogdanm 92:4fc01daae5a5 80 #define RIICn_RIICnSER_SAR2E (0x04u)
bogdanm 92:4fc01daae5a5 81 #define RIICn_RIICnSER_GCAE (0x08u)
bogdanm 92:4fc01daae5a5 82 #define RIICn_RIICnSER_DIDE (0x20u)
bogdanm 92:4fc01daae5a5 83 #define RIICn_RIICnSER_HOAE (0x80u)
bogdanm 92:4fc01daae5a5 84
bogdanm 92:4fc01daae5a5 85 #define RIICn_RIICnIER_TMOIE (0x01u)
bogdanm 92:4fc01daae5a5 86 #define RIICn_RIICnIER_ALIE (0x02u)
bogdanm 92:4fc01daae5a5 87 #define RIICn_RIICnIER_STIE (0x04u)
bogdanm 92:4fc01daae5a5 88 #define RIICn_RIICnIER_SPIE (0x08u)
bogdanm 92:4fc01daae5a5 89 #define RIICn_RIICnIER_NAKIE (0x10u)
bogdanm 92:4fc01daae5a5 90 #define RIICn_RIICnIER_RIE (0x20u)
bogdanm 92:4fc01daae5a5 91 #define RIICn_RIICnIER_TEIE (0x40u)
bogdanm 92:4fc01daae5a5 92 #define RIICn_RIICnIER_TIE (0x80u)
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 #define RIICn_RIICnSR1_AAS0 (0x01u)
bogdanm 92:4fc01daae5a5 95 #define RIICn_RIICnSR1_AAS1 (0x02u)
bogdanm 92:4fc01daae5a5 96 #define RIICn_RIICnSR1_AAS2 (0x04u)
bogdanm 92:4fc01daae5a5 97 #define RIICn_RIICnSR1_GCA (0x08u)
bogdanm 92:4fc01daae5a5 98 #define RIICn_RIICnSR1_DID (0x20u)
bogdanm 92:4fc01daae5a5 99 #define RIICn_RIICnSR1_HOA (0x80u)
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 #define RIICn_RIICnSR2_TMOF (0x01u)
bogdanm 92:4fc01daae5a5 102 #define RIICn_RIICnSR2_AL (0x02u)
bogdanm 92:4fc01daae5a5 103 #define RIICn_RIICnSR2_START (0x04u)
bogdanm 92:4fc01daae5a5 104 #define RIICn_RIICnSR2_STOP (0x08u)
bogdanm 92:4fc01daae5a5 105 #define RIICn_RIICnSR2_NACKF (0x10u)
bogdanm 92:4fc01daae5a5 106 #define RIICn_RIICnSR2_RDRF (0x20u)
bogdanm 92:4fc01daae5a5 107 #define RIICn_RIICnSR2_TEND (0x40u)
bogdanm 92:4fc01daae5a5 108 #define RIICn_RIICnSR2_TDRE (0x80u)
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110 #define RIICn_RIICnSAR0_SVA0 (0x0001u)
bogdanm 92:4fc01daae5a5 111 #define RIICn_RIICnSAR0_SVA (0x03FEu)
bogdanm 92:4fc01daae5a5 112 #define RIICn_RIICnSAR0_FSy (0x8000u)
bogdanm 92:4fc01daae5a5 113
bogdanm 92:4fc01daae5a5 114 #define RIICn_RIICnSAR1_SVA0 (0x0001u)
bogdanm 92:4fc01daae5a5 115 #define RIICn_RIICnSAR1_SVA (0x03FEu)
bogdanm 92:4fc01daae5a5 116 #define RIICn_RIICnSAR1_FSy (0x8000u)
bogdanm 92:4fc01daae5a5 117
bogdanm 92:4fc01daae5a5 118 #define RIICn_RIICnSAR2_SVA0 (0x0001u)
bogdanm 92:4fc01daae5a5 119 #define RIICn_RIICnSAR2_SVA (0x03FEu)
bogdanm 92:4fc01daae5a5 120 #define RIICn_RIICnSAR2_FSy (0x8000u)
bogdanm 92:4fc01daae5a5 121
bogdanm 92:4fc01daae5a5 122 #define RIICn_RIICnBRL_BRL (0x1Fu)
bogdanm 92:4fc01daae5a5 123
bogdanm 92:4fc01daae5a5 124 #define RIICn_RIICnBRH_BRH (0x1Fu)
bogdanm 92:4fc01daae5a5 125
bogdanm 92:4fc01daae5a5 126 #define RIICn_RIICnDRT_DRT (0xFFu)
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 #define RIICn_RIICnDRR_DRR (0xFFu)
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 /* ==== Shift values for IO registers ==== */
bogdanm 92:4fc01daae5a5 132 #define RIICn_RIICnCR1_SDAI_SHIFT (0u)
bogdanm 92:4fc01daae5a5 133 #define RIICn_RIICnCR1_SCLI_SHIFT (1u)
bogdanm 92:4fc01daae5a5 134 #define RIICn_RIICnCR1_SDAO_SHIFT (2u)
bogdanm 92:4fc01daae5a5 135 #define RIICn_RIICnCR1_SCLO_SHIFT (3u)
bogdanm 92:4fc01daae5a5 136 #define RIICn_RIICnCR1_SOWP_SHIFT (4u)
bogdanm 92:4fc01daae5a5 137 #define RIICn_RIICnCR1_CLO_SHIFT (5u)
bogdanm 92:4fc01daae5a5 138 #define RIICn_RIICnCR1_IICRST_SHIFT (6u)
bogdanm 92:4fc01daae5a5 139 #define RIICn_RIICnCR1_ICE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 140
bogdanm 92:4fc01daae5a5 141 #define RIICn_RIICnCR2_ST_SHIFT (1u)
bogdanm 92:4fc01daae5a5 142 #define RIICn_RIICnCR2_RS_SHIFT (2u)
bogdanm 92:4fc01daae5a5 143 #define RIICn_RIICnCR2_SP_SHIFT (3u)
bogdanm 92:4fc01daae5a5 144 #define RIICn_RIICnCR2_TRS_SHIFT (5u)
bogdanm 92:4fc01daae5a5 145 #define RIICn_RIICnCR2_MST_SHIFT (6u)
bogdanm 92:4fc01daae5a5 146 #define RIICn_RIICnCR2_BBSY_SHIFT (7u)
bogdanm 92:4fc01daae5a5 147
bogdanm 92:4fc01daae5a5 148 #define RIICn_RIICnMR1_BC_SHIFT (0u)
bogdanm 92:4fc01daae5a5 149 #define RIICn_RIICnMR1_BCWP_SHIFT (3u)
bogdanm 92:4fc01daae5a5 150 #define RIICn_RIICnMR1_CKS_SHIFT (4u)
bogdanm 92:4fc01daae5a5 151 #define RIICn_RIICnMR1_MTWP_SHIFT (7u)
bogdanm 92:4fc01daae5a5 152
bogdanm 92:4fc01daae5a5 153 #define RIICn_RIICnMR2_TMOS_SHIFT (0u)
bogdanm 92:4fc01daae5a5 154 #define RIICn_RIICnMR2_TMOL_SHIFT (1u)
bogdanm 92:4fc01daae5a5 155 #define RIICn_RIICnMR2_TMOH_SHIFT (2u)
bogdanm 92:4fc01daae5a5 156 #define RIICn_RIICnMR2_SDDL_SHIFT (4u)
bogdanm 92:4fc01daae5a5 157 #define RIICn_RIICnMR2_DLCS_SHIFT (7u)
bogdanm 92:4fc01daae5a5 158
bogdanm 92:4fc01daae5a5 159 #define RIICn_RIICnMR3_NF_SHIFT (0u)
bogdanm 92:4fc01daae5a5 160 #define RIICn_RIICnMR3_ACKBR_SHIFT (2u)
bogdanm 92:4fc01daae5a5 161 #define RIICn_RIICnMR3_ACKBT_SHIFT (3u)
bogdanm 92:4fc01daae5a5 162 #define RIICn_RIICnMR3_ACKWP_SHIFT (4u)
bogdanm 92:4fc01daae5a5 163 #define RIICn_RIICnMR3_RDRFS_SHIFT (5u)
bogdanm 92:4fc01daae5a5 164 #define RIICn_RIICnMR3_WAIT_SHIFT (6u)
bogdanm 92:4fc01daae5a5 165 #define RIICn_RIICnMR3_SMBS_SHIFT (7u)
bogdanm 92:4fc01daae5a5 166
bogdanm 92:4fc01daae5a5 167 #define RIICn_RIICnFER_TMOE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 168 #define RIICn_RIICnFER_MALE_SHIFT (1u)
bogdanm 92:4fc01daae5a5 169 #define RIICn_RIICnFER_NALE_SHIFT (2u)
bogdanm 92:4fc01daae5a5 170 #define RIICn_RIICnFER_SALE_SHIFT (3u)
bogdanm 92:4fc01daae5a5 171 #define RIICn_RIICnFER_NACKE_SHIFT (4u)
bogdanm 92:4fc01daae5a5 172 #define RIICn_RIICnFER_NFE_SHIFT (5u)
bogdanm 92:4fc01daae5a5 173 #define RIICn_RIICnFER_SCLE_SHIFT (6u)
bogdanm 92:4fc01daae5a5 174 #define RIICn_RIICnFER_FMPE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 175
bogdanm 92:4fc01daae5a5 176 #define RIICn_RIICnSER_SAR0E_SHIFT (0u)
bogdanm 92:4fc01daae5a5 177 #define RIICn_RIICnSER_SAR1E_SHIFT (1u)
bogdanm 92:4fc01daae5a5 178 #define RIICn_RIICnSER_SAR2E_SHIFT (2u)
bogdanm 92:4fc01daae5a5 179 #define RIICn_RIICnSER_GCAE_SHIFT (3u)
bogdanm 92:4fc01daae5a5 180 #define RIICn_RIICnSER_DIDE_SHIFT (5u)
bogdanm 92:4fc01daae5a5 181 #define RIICn_RIICnSER_HOAE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183 #define RIICn_RIICnIER_TMOIE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 184 #define RIICn_RIICnIER_ALIE_SHIFT (1u)
bogdanm 92:4fc01daae5a5 185 #define RIICn_RIICnIER_STIE_SHIFT (2u)
bogdanm 92:4fc01daae5a5 186 #define RIICn_RIICnIER_SPIE_SHIFT (3u)
bogdanm 92:4fc01daae5a5 187 #define RIICn_RIICnIER_NAKIE_SHIFT (4u)
bogdanm 92:4fc01daae5a5 188 #define RIICn_RIICnIER_RIE_SHIFT (5u)
bogdanm 92:4fc01daae5a5 189 #define RIICn_RIICnIER_TEIE_SHIFT (6u)
bogdanm 92:4fc01daae5a5 190 #define RIICn_RIICnIER_TIE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 191
bogdanm 92:4fc01daae5a5 192 #define RIICn_RIICnSR1_AAS0_SHIFT (0u)
bogdanm 92:4fc01daae5a5 193 #define RIICn_RIICnSR1_AAS1_SHIFT (1u)
bogdanm 92:4fc01daae5a5 194 #define RIICn_RIICnSR1_AAS2_SHIFT (2u)
bogdanm 92:4fc01daae5a5 195 #define RIICn_RIICnSR1_GCA_SHIFT (3u)
bogdanm 92:4fc01daae5a5 196 #define RIICn_RIICnSR1_DID_SHIFT (5u)
bogdanm 92:4fc01daae5a5 197 #define RIICn_RIICnSR1_HOA_SHIFT (7u)
bogdanm 92:4fc01daae5a5 198
bogdanm 92:4fc01daae5a5 199 #define RIICn_RIICnSR2_TMOF_SHIFT (0u)
bogdanm 92:4fc01daae5a5 200 #define RIICn_RIICnSR2_AL_SHIFT (1u)
bogdanm 92:4fc01daae5a5 201 #define RIICn_RIICnSR2_START_SHIFT (2u)
bogdanm 92:4fc01daae5a5 202 #define RIICn_RIICnSR2_STOP_SHIFT (3u)
bogdanm 92:4fc01daae5a5 203 #define RIICn_RIICnSR2_NACKF_SHIFT (4u)
bogdanm 92:4fc01daae5a5 204 #define RIICn_RIICnSR2_RDRF_SHIFT (5u)
bogdanm 92:4fc01daae5a5 205 #define RIICn_RIICnSR2_TEND_SHIFT (6u)
bogdanm 92:4fc01daae5a5 206 #define RIICn_RIICnSR2_TDRE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 207
bogdanm 92:4fc01daae5a5 208 #define RIICn_RIICnSAR0_SVA0_SHIFT (0u)
bogdanm 92:4fc01daae5a5 209 #define RIICn_RIICnSAR0_SVA_SHIFT (1u)
bogdanm 92:4fc01daae5a5 210 #define RIICn_RIICnSAR0_FSy_SHIFT (15u)
bogdanm 92:4fc01daae5a5 211
bogdanm 92:4fc01daae5a5 212 #define RIICn_RIICnSAR1_SVA0_SHIFT (0u)
bogdanm 92:4fc01daae5a5 213 #define RIICn_RIICnSAR1_SVA_SHIFT (1u)
bogdanm 92:4fc01daae5a5 214 #define RIICn_RIICnSAR1_FSy_SHIFT (15u)
bogdanm 92:4fc01daae5a5 215
bogdanm 92:4fc01daae5a5 216 #define RIICn_RIICnSAR2_SVA0_SHIFT (0u)
bogdanm 92:4fc01daae5a5 217 #define RIICn_RIICnSAR2_SVA_SHIFT (1u)
bogdanm 92:4fc01daae5a5 218 #define RIICn_RIICnSAR2_FSy_SHIFT (15u)
bogdanm 92:4fc01daae5a5 219
bogdanm 92:4fc01daae5a5 220 #define RIICn_RIICnBRL_BRL_SHIFT (0u)
bogdanm 92:4fc01daae5a5 221
bogdanm 92:4fc01daae5a5 222 #define RIICn_RIICnBRH_BRH_SHIFT (0u)
bogdanm 92:4fc01daae5a5 223
bogdanm 92:4fc01daae5a5 224 #define RIICn_RIICnDRT_DRT_SHIFT (0u)
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226 #define RIICn_RIICnDRR_DRR_SHIFT (0u)
bogdanm 92:4fc01daae5a5 227
bogdanm 92:4fc01daae5a5 228
bogdanm 92:4fc01daae5a5 229 #endif /* RIIC_IOBITMASK_H */
bogdanm 92:4fc01daae5a5 230
bogdanm 92:4fc01daae5a5 231 /* End of File */