frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_RZ_A1H/iodefine.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer*
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : iodefine.h
bogdanm 92:4fc01daae5a5 25 * $Rev: $
bogdanm 92:4fc01daae5a5 26 * $Date:: $
bogdanm 92:4fc01daae5a5 27 * Description : Definition of I/O Register (V1.00a)
bogdanm 92:4fc01daae5a5 28 ******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef R7S72100_IODEFINE_H
bogdanm 92:4fc01daae5a5 30 #define R7S72100_IODEFINE_H
bogdanm 92:4fc01daae5a5 31 #define IODEFINE_H_VERSION 100
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 enum iodefine_byte_select_t
bogdanm 92:4fc01daae5a5 34 {
bogdanm 92:4fc01daae5a5 35 L = 0, H = 1,
bogdanm 92:4fc01daae5a5 36 LL= 0, LH = 1, HL = 2, HH = 3
bogdanm 92:4fc01daae5a5 37 };
bogdanm 92:4fc01daae5a5 38
bogdanm 92:4fc01daae5a5 39 /***********************************************************************
bogdanm 92:4fc01daae5a5 40 <<< [iodefine_reg32_t] >>>
bogdanm 92:4fc01daae5a5 41 - Padding : sizeof(iodefine_reg32_t) == 4
bogdanm 92:4fc01daae5a5 42 - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
bogdanm 92:4fc01daae5a5 43 - &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
bogdanm 92:4fc01daae5a5 44 - Endian : Independent (Same as CPU endian as register endian)
bogdanm 92:4fc01daae5a5 45 - Bit-Order : Independent
bogdanm 92:4fc01daae5a5 46 ************************************************************************/
bogdanm 92:4fc01daae5a5 47 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
bogdanm 92:4fc01daae5a5 48 /* ->SEC M1.10.1 : Not magic number */
bogdanm 92:4fc01daae5a5 49 union iodefine_reg32_t
bogdanm 92:4fc01daae5a5 50 {
bogdanm 92:4fc01daae5a5 51 volatile uint32_t UINT32; /* 32-bit Access */
bogdanm 92:4fc01daae5a5 52 volatile uint16_t UINT16[2]; /* 16-bit Access */
bogdanm 92:4fc01daae5a5 53 volatile uint8_t UINT8[4]; /* 8-bit Access */
bogdanm 92:4fc01daae5a5 54 };
bogdanm 92:4fc01daae5a5 55 /* <-SEC M1.10.1 */
bogdanm 92:4fc01daae5a5 56 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
bogdanm 92:4fc01daae5a5 57
bogdanm 92:4fc01daae5a5 58 /***********************************************************************
bogdanm 92:4fc01daae5a5 59 <<< [iodefine_reg32_16_t] >>>
bogdanm 92:4fc01daae5a5 60 - Padding : sizeof(iodefine_reg32_16_t) == 4
bogdanm 92:4fc01daae5a5 61 - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
bogdanm 92:4fc01daae5a5 62 - Endian : Independent (Same as CPU endian as register endian)
bogdanm 92:4fc01daae5a5 63 - Bit-Order : Independent
bogdanm 92:4fc01daae5a5 64 ************************************************************************/
bogdanm 92:4fc01daae5a5 65 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
bogdanm 92:4fc01daae5a5 66 /* ->SEC M1.10.1 : Not magic number */
bogdanm 92:4fc01daae5a5 67 union iodefine_reg32_16_t
bogdanm 92:4fc01daae5a5 68 {
bogdanm 92:4fc01daae5a5 69 volatile uint32_t UINT32; /* 32-bit Access */
bogdanm 92:4fc01daae5a5 70 volatile uint16_t UINT16[2]; /* 16-bit Access */
bogdanm 92:4fc01daae5a5 71 };
bogdanm 92:4fc01daae5a5 72 /* <-SEC M1.10.1 */
bogdanm 92:4fc01daae5a5 73 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
bogdanm 92:4fc01daae5a5 74
bogdanm 92:4fc01daae5a5 75 /***********************************************************************
bogdanm 92:4fc01daae5a5 76 <<< [iodefine_reg16_8_t] >>>
bogdanm 92:4fc01daae5a5 77 - Padding : sizeof(iodefine_reg16_8_t) == 2
bogdanm 92:4fc01daae5a5 78 - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
bogdanm 92:4fc01daae5a5 79 - Endian : Independent (Same as CPU endian as register endian)
bogdanm 92:4fc01daae5a5 80 - Bit-Order : Independent
bogdanm 92:4fc01daae5a5 81 ************************************************************************/
bogdanm 92:4fc01daae5a5 82 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
bogdanm 92:4fc01daae5a5 83 /* ->SEC M1.10.1 : Not magic number */
bogdanm 92:4fc01daae5a5 84 union iodefine_reg16_8_t
bogdanm 92:4fc01daae5a5 85 {
bogdanm 92:4fc01daae5a5 86 volatile uint16_t UINT16; /* 16-bit Access */
bogdanm 92:4fc01daae5a5 87 volatile uint8_t UINT8[2]; /* 8-bit Access */
bogdanm 92:4fc01daae5a5 88 };
bogdanm 92:4fc01daae5a5 89 /* <-SEC M1.10.1 */
bogdanm 92:4fc01daae5a5 90 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95
bogdanm 92:4fc01daae5a5 96
bogdanm 92:4fc01daae5a5 97 #include "adc_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 98 #include "bsc_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 99 #include "ceu_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 100 #include "cpg_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 101 #include "disc_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 102 #include "dmac_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 103 #include "dvdec_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 104 #include "ether_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 105 #include "flctl_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 106 #include "gpio_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 107 #include "ieb_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 108 #include "inb_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 109 #include "intc_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 110 #include "irda_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 111 #include "jcu_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 112 #include "l2c_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 113 #include "lin_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 114 #include "lvds_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 115 #include "mlb_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 116 #include "mmc_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 117 #include "mtu2_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 118 #include "ostm_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 119 #include "pfv_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 120 #include "pwm_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 121 #include "riic_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 122 #include "romdec_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 123 #include "rscan0_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 124 #include "rspi_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 125 #include "rtc_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 126 #include "scif_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 127 #include "scim_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 128 #include "scux_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 129 #include "sdg_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 130 #include "spdif_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 131 #include "spibsc_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 132 #include "ssif_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 133 #include "usb20_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 134 #include "vdc5_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 135 #include "wdt_iodefine.h" /* (V1.00a) */
bogdanm 92:4fc01daae5a5 136 #endif