frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_RZ_A1H/gic.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file gic.h
bogdanm 92:4fc01daae5a5 3 * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
bogdanm 92:4fc01daae5a5 4 * @version
bogdanm 92:4fc01daae5a5 5 * @date 29 August 2013
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
bogdanm 92:4fc01daae5a5 10 /* Copyright (c) 2011 - 2013 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37 #ifndef GIC_H_
bogdanm 92:4fc01daae5a5 38 #define GIC_H_
bogdanm 92:4fc01daae5a5 39
bogdanm 92:4fc01daae5a5 40 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 92:4fc01daae5a5 41 /**
bogdanm 92:4fc01daae5a5 42 */
bogdanm 92:4fc01daae5a5 43 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 44 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 45 #else
bogdanm 92:4fc01daae5a5 46 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 47 #endif
bogdanm 92:4fc01daae5a5 48 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 92:4fc01daae5a5 49 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
bogdanm 92:4fc01daae5a5 52 */
bogdanm 92:4fc01daae5a5 53 typedef struct
bogdanm 92:4fc01daae5a5 54 {
bogdanm 92:4fc01daae5a5 55 __IO uint32_t ICDDCR;
bogdanm 92:4fc01daae5a5 56 __I uint32_t ICDICTR;
bogdanm 92:4fc01daae5a5 57 __I uint32_t ICDIIDR;
bogdanm 92:4fc01daae5a5 58 uint32_t RESERVED0[29];
bogdanm 92:4fc01daae5a5 59 __IO uint32_t ICDISR[32];
bogdanm 92:4fc01daae5a5 60 __IO uint32_t ICDISER[32];
bogdanm 92:4fc01daae5a5 61 __IO uint32_t ICDICER[32];
bogdanm 92:4fc01daae5a5 62 __IO uint32_t ICDISPR[32];
bogdanm 92:4fc01daae5a5 63 __IO uint32_t ICDICPR[32];
bogdanm 92:4fc01daae5a5 64 __I uint32_t ICDABR[32];
bogdanm 92:4fc01daae5a5 65 uint32_t RESERVED1[32];
bogdanm 92:4fc01daae5a5 66 __IO uint32_t ICDIPR[256];
bogdanm 92:4fc01daae5a5 67 __IO uint32_t ICDIPTR[256];
bogdanm 92:4fc01daae5a5 68 __IO uint32_t ICDICFR[64];
bogdanm 92:4fc01daae5a5 69 uint32_t RESERVED2[128];
bogdanm 92:4fc01daae5a5 70 __IO uint32_t ICDSGIR;
bogdanm 92:4fc01daae5a5 71 } GICDistributor_Type;
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 /** \brief Structure type to access the Controller Interface (GICC)
bogdanm 92:4fc01daae5a5 74 */
bogdanm 92:4fc01daae5a5 75 typedef struct
bogdanm 92:4fc01daae5a5 76 {
bogdanm 92:4fc01daae5a5 77 __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
bogdanm 92:4fc01daae5a5 78 __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
bogdanm 92:4fc01daae5a5 79 __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
bogdanm 92:4fc01daae5a5 80 __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
bogdanm 92:4fc01daae5a5 81 __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
bogdanm 92:4fc01daae5a5 82 __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
bogdanm 92:4fc01daae5a5 83 __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
bogdanm 92:4fc01daae5a5 84 __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 uint32_t RESERVED[55];
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
bogdanm 92:4fc01daae5a5 89 } GICInterface_Type;
bogdanm 92:4fc01daae5a5 90
bogdanm 92:4fc01daae5a5 91 /*@} end of GICD */
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93 /* ########################## GIC functions #################################### */
bogdanm 92:4fc01daae5a5 94 /** \brief Functions that manage interrupts via the GIC.
bogdanm 92:4fc01daae5a5 95 @{
bogdanm 92:4fc01daae5a5 96 */
bogdanm 92:4fc01daae5a5 97
bogdanm 92:4fc01daae5a5 98 /** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
bogdanm 92:4fc01daae5a5 99
bogdanm 92:4fc01daae5a5 100 Enables the forwarding of pending interrupts to the CPU interfaces.
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102 */
bogdanm 92:4fc01daae5a5 103 void GIC_EnableDistributor(void);
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 /** \brief Disable Distributor
bogdanm 92:4fc01daae5a5 106
bogdanm 92:4fc01daae5a5 107 Disables the forwarding of pending interrupts to the CPU interfaces.
bogdanm 92:4fc01daae5a5 108
bogdanm 92:4fc01daae5a5 109 */
bogdanm 92:4fc01daae5a5 110 void GIC_DisableDistributor(void);
bogdanm 92:4fc01daae5a5 111
bogdanm 92:4fc01daae5a5 112 /** \brief Provides information about the configuration of the GIC.
bogdanm 92:4fc01daae5a5 113 Provides information about the configuration of the GIC.
bogdanm 92:4fc01daae5a5 114 - whether the GIC implements the Security Extensions
bogdanm 92:4fc01daae5a5 115 - the maximum number of interrupt IDs that the GIC supports
bogdanm 92:4fc01daae5a5 116 - the number of CPU interfaces implemented
bogdanm 92:4fc01daae5a5 117 - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
bogdanm 92:4fc01daae5a5 118
bogdanm 92:4fc01daae5a5 119 \return Distributor Information.
bogdanm 92:4fc01daae5a5 120 */
bogdanm 92:4fc01daae5a5 121 uint32_t GIC_DistributorInfo(void);
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 /** \brief Distributor Implementer Identification Register.
bogdanm 92:4fc01daae5a5 124
bogdanm 92:4fc01daae5a5 125 Distributor Implementer Identification Register
bogdanm 92:4fc01daae5a5 126
bogdanm 92:4fc01daae5a5 127 \return Implementer Information.
bogdanm 92:4fc01daae5a5 128 */
bogdanm 92:4fc01daae5a5 129 uint32_t GIC_DistributorImplementer(void);
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 /** \brief Set list of processors that the interrupt is sent to if it is asserted.
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
bogdanm 92:4fc01daae5a5 134 This field stores the list of processors that the interrupt is sent to if it is asserted.
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 137 \param [in] target CPU target
bogdanm 92:4fc01daae5a5 138 */
bogdanm 92:4fc01daae5a5 139 void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
bogdanm 92:4fc01daae5a5 140
bogdanm 92:4fc01daae5a5 141 /** \brief Get list of processors that the interrupt is sent to if it is asserted.
bogdanm 92:4fc01daae5a5 142
bogdanm 92:4fc01daae5a5 143 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
bogdanm 92:4fc01daae5a5 144 This field stores the list of processors that the interrupt is sent to if it is asserted.
bogdanm 92:4fc01daae5a5 145
bogdanm 92:4fc01daae5a5 146 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 147 \param [in] target CPU target
bogdanm 92:4fc01daae5a5 148 */
bogdanm 92:4fc01daae5a5 149 uint32_t GIC_GetTarget(IRQn_Type IRQn);
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 /** \brief Enable Interface
bogdanm 92:4fc01daae5a5 152
bogdanm 92:4fc01daae5a5 153 Enables the signalling of interrupts to the target processors.
bogdanm 92:4fc01daae5a5 154
bogdanm 92:4fc01daae5a5 155 */
bogdanm 92:4fc01daae5a5 156 void GIC_EnableInterface(void);
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 /** \brief Disable Interface
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 Disables the signalling of interrupts to the target processors.
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 */
bogdanm 92:4fc01daae5a5 163 void GIC_DisableInterface(void);
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 /** \brief Acknowledge Interrupt
bogdanm 92:4fc01daae5a5 166
bogdanm 92:4fc01daae5a5 167 The function acknowledges the highest priority pending interrupt and returns its IRQ number.
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 \return Interrupt number
bogdanm 92:4fc01daae5a5 170 */
bogdanm 92:4fc01daae5a5 171 IRQn_Type GIC_AcknowledgePending(void);
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173 /** \brief End Interrupt
bogdanm 92:4fc01daae5a5 174
bogdanm 92:4fc01daae5a5 175 The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
bogdanm 92:4fc01daae5a5 176
bogdanm 92:4fc01daae5a5 177 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 178 */
bogdanm 92:4fc01daae5a5 179 void GIC_EndInterrupt(IRQn_Type IRQn);
bogdanm 92:4fc01daae5a5 180
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 /** \brief Enable Interrupt
bogdanm 92:4fc01daae5a5 183
bogdanm 92:4fc01daae5a5 184 Set-enable bit for each interrupt supported by the GIC.
bogdanm 92:4fc01daae5a5 185
bogdanm 92:4fc01daae5a5 186 \param [in] IRQn External interrupt number.
bogdanm 92:4fc01daae5a5 187 */
bogdanm 92:4fc01daae5a5 188 void GIC_EnableIRQ(IRQn_Type IRQn);
bogdanm 92:4fc01daae5a5 189
bogdanm 92:4fc01daae5a5 190 /** \brief Disable Interrupt
bogdanm 92:4fc01daae5a5 191
bogdanm 92:4fc01daae5a5 192 Clear-enable bit for each interrupt supported by the GIC.
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194 \param [in] IRQn Number of the external interrupt to disable
bogdanm 92:4fc01daae5a5 195 */
bogdanm 92:4fc01daae5a5 196 void GIC_DisableIRQ(IRQn_Type IRQn);
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 /** \brief Set Pending Interrupt
bogdanm 92:4fc01daae5a5 199
bogdanm 92:4fc01daae5a5 200 Set-pending bit for each interrupt supported by the GIC.
bogdanm 92:4fc01daae5a5 201
bogdanm 92:4fc01daae5a5 202 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 203 */
bogdanm 92:4fc01daae5a5 204 void GIC_SetPendingIRQ(IRQn_Type IRQn);
bogdanm 92:4fc01daae5a5 205
bogdanm 92:4fc01daae5a5 206 /** \brief Clear Pending Interrupt
bogdanm 92:4fc01daae5a5 207
bogdanm 92:4fc01daae5a5 208 Clear-pending bit for each interrupt supported by the GIC
bogdanm 92:4fc01daae5a5 209
bogdanm 92:4fc01daae5a5 210 \param [in] IRQn Number of the interrupt for clear pending
bogdanm 92:4fc01daae5a5 211 */
bogdanm 92:4fc01daae5a5 212 void GIC_ClearPendingIRQ(IRQn_Type IRQn);
bogdanm 92:4fc01daae5a5 213
bogdanm 92:4fc01daae5a5 214 /** \brief Int_config field for each interrupt supported by the GIC.
bogdanm 92:4fc01daae5a5 215
bogdanm 92:4fc01daae5a5 216 This field identifies whether the corresponding interrupt is:
bogdanm 92:4fc01daae5a5 217 (1) edge-triggered or (0) level-sensitive
bogdanm 92:4fc01daae5a5 218 (1) 1-N model or (0) N-N model
bogdanm 92:4fc01daae5a5 219
bogdanm 92:4fc01daae5a5 220 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 221 \param [in] edge_level (1) edge-triggered or (0) level-sensitive
bogdanm 92:4fc01daae5a5 222 \param [in] model (1) 1-N model or (0) N-N model
bogdanm 92:4fc01daae5a5 223 */
bogdanm 92:4fc01daae5a5 224 void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226
bogdanm 92:4fc01daae5a5 227 /** \brief Set Interrupt Priority
bogdanm 92:4fc01daae5a5 228
bogdanm 92:4fc01daae5a5 229 The function sets the priority of an interrupt.
bogdanm 92:4fc01daae5a5 230
bogdanm 92:4fc01daae5a5 231 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 232 \param [in] priority Priority to set.
bogdanm 92:4fc01daae5a5 233 */
bogdanm 92:4fc01daae5a5 234 void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
bogdanm 92:4fc01daae5a5 235
bogdanm 92:4fc01daae5a5 236 /** \brief Get Interrupt Priority
bogdanm 92:4fc01daae5a5 237
bogdanm 92:4fc01daae5a5 238 The function reads the priority of an interrupt.
bogdanm 92:4fc01daae5a5 239
bogdanm 92:4fc01daae5a5 240 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 241 \return Interrupt Priority.
bogdanm 92:4fc01daae5a5 242 */
bogdanm 92:4fc01daae5a5 243 uint32_t GIC_GetPriority(IRQn_Type IRQn);
bogdanm 92:4fc01daae5a5 244
bogdanm 92:4fc01daae5a5 245 /** \brief CPU Interface Priority Mask Register
bogdanm 92:4fc01daae5a5 246
bogdanm 92:4fc01daae5a5 247 The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
bogdanm 92:4fc01daae5a5 248 value indicated by this field, the interface signals the interrupt to the processor.
bogdanm 92:4fc01daae5a5 249
bogdanm 92:4fc01daae5a5 250 \param [in] Mask.
bogdanm 92:4fc01daae5a5 251 */
bogdanm 92:4fc01daae5a5 252 void GIC_InterfacePriorityMask(uint32_t priority);
bogdanm 92:4fc01daae5a5 253
bogdanm 92:4fc01daae5a5 254 /** \brief Set the binary point.
bogdanm 92:4fc01daae5a5 255
bogdanm 92:4fc01daae5a5 256 Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
bogdanm 92:4fc01daae5a5 257
bogdanm 92:4fc01daae5a5 258 \param [in] Mask.
bogdanm 92:4fc01daae5a5 259 */
bogdanm 92:4fc01daae5a5 260 void GIC_SetBinaryPoint(uint32_t binary_point);
bogdanm 92:4fc01daae5a5 261
bogdanm 92:4fc01daae5a5 262 /** \brief Get the binary point.
bogdanm 92:4fc01daae5a5 263
bogdanm 92:4fc01daae5a5 264 Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
bogdanm 92:4fc01daae5a5 265
bogdanm 92:4fc01daae5a5 266 \return Binary point.
bogdanm 92:4fc01daae5a5 267 */
bogdanm 92:4fc01daae5a5 268 uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270 /** \brief Get Interrupt state.
bogdanm 92:4fc01daae5a5 271
bogdanm 92:4fc01daae5a5 272 Get the interrupt state, whether pending and/or active
bogdanm 92:4fc01daae5a5 273
bogdanm 92:4fc01daae5a5 274 \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
bogdanm 92:4fc01daae5a5 275 */
bogdanm 92:4fc01daae5a5 276 uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
bogdanm 92:4fc01daae5a5 277
bogdanm 92:4fc01daae5a5 278 /** \brief Send Software Generated interrupt
bogdanm 92:4fc01daae5a5 279
bogdanm 92:4fc01daae5a5 280 Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
bogdanm 92:4fc01daae5a5 281 GIC_InterfacePriorityMask
bogdanm 92:4fc01daae5a5 282 \param [in] IRQn The Interrupt ID of the SGI.
bogdanm 92:4fc01daae5a5 283 \param [in] target_list CPUTargetList
bogdanm 92:4fc01daae5a5 284 \param [in] filter_list TargetListFilter
bogdanm 92:4fc01daae5a5 285 */
bogdanm 92:4fc01daae5a5 286 void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
bogdanm 92:4fc01daae5a5 287
bogdanm 92:4fc01daae5a5 288 /** \brief API call to initialise the interrupt distributor
bogdanm 92:4fc01daae5a5 289
bogdanm 92:4fc01daae5a5 290 API call to initialise the interrupt distributor
bogdanm 92:4fc01daae5a5 291
bogdanm 92:4fc01daae5a5 292 */
bogdanm 92:4fc01daae5a5 293 void GIC_DistInit(void);
bogdanm 92:4fc01daae5a5 294
bogdanm 92:4fc01daae5a5 295 /** \brief API call to initialise the CPU interface
bogdanm 92:4fc01daae5a5 296
bogdanm 92:4fc01daae5a5 297 API call to initialise the CPU interface
bogdanm 92:4fc01daae5a5 298
bogdanm 92:4fc01daae5a5 299 */
bogdanm 92:4fc01daae5a5 300 void GIC_CPUInterfaceInit(void);
bogdanm 92:4fc01daae5a5 301
bogdanm 92:4fc01daae5a5 302 /** \brief API call to set the Interrupt Configuration Registers
bogdanm 92:4fc01daae5a5 303
bogdanm 92:4fc01daae5a5 304 API call to initialise the Interrupt Configuration Registers
bogdanm 92:4fc01daae5a5 305
bogdanm 92:4fc01daae5a5 306 */
bogdanm 92:4fc01daae5a5 307 void GIC_SetICDICFR (const uint32_t *ICDICFRn);
bogdanm 92:4fc01daae5a5 308
bogdanm 92:4fc01daae5a5 309 /** \brief API call to Enable the GIC
bogdanm 92:4fc01daae5a5 310
bogdanm 92:4fc01daae5a5 311 API call to Enable the GIC
bogdanm 92:4fc01daae5a5 312
bogdanm 92:4fc01daae5a5 313 */
bogdanm 92:4fc01daae5a5 314 void GIC_Enable(void);
bogdanm 92:4fc01daae5a5 315
bogdanm 92:4fc01daae5a5 316 #endif /* GIC_H_ */