frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_RZ_A1H/bsc_iobitmask.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : bsc_iobitmask.h
bogdanm 92:4fc01daae5a5 25 * $Rev: 1115 $
bogdanm 92:4fc01daae5a5 26 * $Date:: 2014-07-09 15:35:02 +0900#$
bogdanm 92:4fc01daae5a5 27 * Description : BSC register define header
bogdanm 92:4fc01daae5a5 28 *******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef BSC_IOBITMASK_H
bogdanm 92:4fc01daae5a5 30 #define BSC_IOBITMASK_H
bogdanm 92:4fc01daae5a5 31
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 /* ==== Mask values for IO registers ==== */
bogdanm 92:4fc01daae5a5 34 #define BSC_CMNCR_HIZCNT (0x00000001uL)
bogdanm 92:4fc01daae5a5 35 #define BSC_CMNCR_HIZMEM (0x00000002uL)
bogdanm 92:4fc01daae5a5 36 #define BSC_CMNCR_DPRTY (0x00000600uL)
bogdanm 92:4fc01daae5a5 37 #define BSC_CMNCR_AL0 (0x01000000uL)
bogdanm 92:4fc01daae5a5 38 #define BSC_CMNCR_TL0 (0x10000000uL)
bogdanm 92:4fc01daae5a5 39
bogdanm 92:4fc01daae5a5 40 #define BSC_CS0BCR_BSZ (0x00000600uL)
bogdanm 92:4fc01daae5a5 41 #define BSC_CS0BCR_TYPE (0x00007000uL)
bogdanm 92:4fc01daae5a5 42 #define BSC_CS0BCR_IWRRS (0x00070000uL)
bogdanm 92:4fc01daae5a5 43 #define BSC_CS0BCR_IWRRD (0x00380000uL)
bogdanm 92:4fc01daae5a5 44 #define BSC_CS0BCR_IWRWS (0x01C00000uL)
bogdanm 92:4fc01daae5a5 45 #define BSC_CS0BCR_IWRWD (0x0E000000uL)
bogdanm 92:4fc01daae5a5 46 #define BSC_CS0BCR_IWW (0x70000000uL)
bogdanm 92:4fc01daae5a5 47
bogdanm 92:4fc01daae5a5 48 #define BSC_CS1BCR_BSZ (0x00000600uL)
bogdanm 92:4fc01daae5a5 49 #define BSC_CS1BCR_TYPE (0x00007000uL)
bogdanm 92:4fc01daae5a5 50 #define BSC_CS1BCR_IWRRS (0x00070000uL)
bogdanm 92:4fc01daae5a5 51 #define BSC_CS1BCR_IWRRD (0x00380000uL)
bogdanm 92:4fc01daae5a5 52 #define BSC_CS1BCR_IWRWS (0x01C00000uL)
bogdanm 92:4fc01daae5a5 53 #define BSC_CS1BCR_IWRWD (0x0E000000uL)
bogdanm 92:4fc01daae5a5 54 #define BSC_CS1BCR_IWW (0x70000000uL)
bogdanm 92:4fc01daae5a5 55
bogdanm 92:4fc01daae5a5 56 #define BSC_CS2BCR_BSZ (0x00000600uL)
bogdanm 92:4fc01daae5a5 57 #define BSC_CS2BCR_TYPE (0x00007000uL)
bogdanm 92:4fc01daae5a5 58 #define BSC_CS2BCR_IWRRS (0x00070000uL)
bogdanm 92:4fc01daae5a5 59 #define BSC_CS2BCR_IWRRD (0x00380000uL)
bogdanm 92:4fc01daae5a5 60 #define BSC_CS2BCR_IWRWS (0x01C00000uL)
bogdanm 92:4fc01daae5a5 61 #define BSC_CS2BCR_IWRWD (0x0E000000uL)
bogdanm 92:4fc01daae5a5 62 #define BSC_CS2BCR_IWW (0x70000000uL)
bogdanm 92:4fc01daae5a5 63
bogdanm 92:4fc01daae5a5 64 #define BSC_CS3BCR_BSZ (0x00000600uL)
bogdanm 92:4fc01daae5a5 65 #define BSC_CS3BCR_TYPE (0x00007000uL)
bogdanm 92:4fc01daae5a5 66 #define BSC_CS3BCR_IWRRS (0x00070000uL)
bogdanm 92:4fc01daae5a5 67 #define BSC_CS3BCR_IWRRD (0x00380000uL)
bogdanm 92:4fc01daae5a5 68 #define BSC_CS3BCR_IWRWS (0x01C00000uL)
bogdanm 92:4fc01daae5a5 69 #define BSC_CS3BCR_IWRWD (0x0E000000uL)
bogdanm 92:4fc01daae5a5 70 #define BSC_CS3BCR_IWW (0x70000000uL)
bogdanm 92:4fc01daae5a5 71
bogdanm 92:4fc01daae5a5 72 #define BSC_CS4BCR_BSZ (0x00000600uL)
bogdanm 92:4fc01daae5a5 73 #define BSC_CS4BCR_TYPE (0x00007000uL)
bogdanm 92:4fc01daae5a5 74 #define BSC_CS4BCR_IWRRS (0x00070000uL)
bogdanm 92:4fc01daae5a5 75 #define BSC_CS4BCR_IWRRD (0x00380000uL)
bogdanm 92:4fc01daae5a5 76 #define BSC_CS4BCR_IWRWS (0x01C00000uL)
bogdanm 92:4fc01daae5a5 77 #define BSC_CS4BCR_IWRWD (0x0E000000uL)
bogdanm 92:4fc01daae5a5 78 #define BSC_CS4BCR_IWW (0x70000000uL)
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 #define BSC_CS5BCR_BSZ (0x00000600uL)
bogdanm 92:4fc01daae5a5 81 #define BSC_CS5BCR_TYPE (0x00007000uL)
bogdanm 92:4fc01daae5a5 82 #define BSC_CS5BCR_IWRRS (0x00070000uL)
bogdanm 92:4fc01daae5a5 83 #define BSC_CS5BCR_IWRRD (0x00380000uL)
bogdanm 92:4fc01daae5a5 84 #define BSC_CS5BCR_IWRWS (0x01C00000uL)
bogdanm 92:4fc01daae5a5 85 #define BSC_CS5BCR_IWRWD (0x0E000000uL)
bogdanm 92:4fc01daae5a5 86 #define BSC_CS5BCR_IWW (0x70000000uL)
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 #define BSC_CS0WCR_NORMAL_HW (0x00000003uL)
bogdanm 92:4fc01daae5a5 89 #define BSC_CS0WCR_NORMAL_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 90 #define BSC_CS0WCR_NORMAL_WR (0x00000780uL)
bogdanm 92:4fc01daae5a5 91 #define BSC_CS0WCR_NORMAL_SW (0x00001800uL)
bogdanm 92:4fc01daae5a5 92 #define BSC_CS0WCR_NORMAL_BAS (0x00100000uL)
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 #define BSC_CS1WCR_NORMAL_HW (0x00000003uL)
bogdanm 92:4fc01daae5a5 95 #define BSC_CS1WCR_NORMAL_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 96 #define BSC_CS1WCR_NORMAL_WR (0x00000780uL)
bogdanm 92:4fc01daae5a5 97 #define BSC_CS1WCR_NORMAL_SW (0x00001800uL)
bogdanm 92:4fc01daae5a5 98 #define BSC_CS1WCR_NORMAL_WW (0x00070000uL)
bogdanm 92:4fc01daae5a5 99 #define BSC_CS1WCR_NORMAL_BAS (0x00100000uL)
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 #define BSC_CS2WCR_NORMAL_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 102 #define BSC_CS2WCR_NORMAL_WR (0x00000780uL)
bogdanm 92:4fc01daae5a5 103 #define BSC_CS2WCR_NORMAL_BAS (0x00100000uL)
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 #define BSC_CS3WCR_NORMAL_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 106 #define BSC_CS3WCR_NORMAL_WR (0x00000780uL)
bogdanm 92:4fc01daae5a5 107 #define BSC_CS3WCR_NORMAL_BAS (0x00100000uL)
bogdanm 92:4fc01daae5a5 108
bogdanm 92:4fc01daae5a5 109 #define BSC_CS4WCR_NORMAL_HW (0x00000003uL)
bogdanm 92:4fc01daae5a5 110 #define BSC_CS4WCR_NORMAL_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 111 #define BSC_CS4WCR_NORMAL_WR (0x00000780uL)
bogdanm 92:4fc01daae5a5 112 #define BSC_CS4WCR_NORMAL_SW (0x00001800uL)
bogdanm 92:4fc01daae5a5 113 #define BSC_CS4WCR_NORMAL_WW (0x00070000uL)
bogdanm 92:4fc01daae5a5 114 #define BSC_CS4WCR_NORMAL_BAS (0x00100000uL)
bogdanm 92:4fc01daae5a5 115
bogdanm 92:4fc01daae5a5 116 #define BSC_CS5WCR_NORMAL_HW (0x00000003uL)
bogdanm 92:4fc01daae5a5 117 #define BSC_CS5WCR_NORMAL_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 118 #define BSC_CS5WCR_NORMAL_WR (0x00000780uL)
bogdanm 92:4fc01daae5a5 119 #define BSC_CS5WCR_NORMAL_SW (0x00001800uL)
bogdanm 92:4fc01daae5a5 120 #define BSC_CS5WCR_NORMAL_WW (0x00070000uL)
bogdanm 92:4fc01daae5a5 121 #define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL)
bogdanm 92:4fc01daae5a5 122 #define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL)
bogdanm 92:4fc01daae5a5 123
bogdanm 92:4fc01daae5a5 124 #define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 125 #define BSC_CS0WCR_BROM_ASY_W (0x00000780uL)
bogdanm 92:4fc01daae5a5 126 #define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL)
bogdanm 92:4fc01daae5a5 127 #define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL)
bogdanm 92:4fc01daae5a5 128
bogdanm 92:4fc01daae5a5 129 #define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL)
bogdanm 92:4fc01daae5a5 130 #define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 131 #define BSC_CS4WCR_BROM_ASY_W (0x00000780uL)
bogdanm 92:4fc01daae5a5 132 #define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL)
bogdanm 92:4fc01daae5a5 133 #define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL)
bogdanm 92:4fc01daae5a5 134 #define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL)
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 #define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL)
bogdanm 92:4fc01daae5a5 137
bogdanm 92:4fc01daae5a5 138 #define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL)
bogdanm 92:4fc01daae5a5 139 #define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL)
bogdanm 92:4fc01daae5a5 140 #define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL)
bogdanm 92:4fc01daae5a5 141 #define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL)
bogdanm 92:4fc01daae5a5 142 #define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL)
bogdanm 92:4fc01daae5a5 143
bogdanm 92:4fc01daae5a5 144 #define BSC_CS0WCR_BROM_SY_WM (0x00000040uL)
bogdanm 92:4fc01daae5a5 145 #define BSC_CS0WCR_BROM_SY_W (0x00000780uL)
bogdanm 92:4fc01daae5a5 146 #define BSC_CS0WCR_BROM_SY_BW (0x00030000uL)
bogdanm 92:4fc01daae5a5 147
bogdanm 92:4fc01daae5a5 148 #define BSC_SDCR_A3COL (0x00000003uL)
bogdanm 92:4fc01daae5a5 149 #define BSC_SDCR_A3ROW (0x00000018uL)
bogdanm 92:4fc01daae5a5 150 #define BSC_SDCR_BACTV (0x00000100uL)
bogdanm 92:4fc01daae5a5 151 #define BSC_SDCR_PDOWN (0x00000200uL)
bogdanm 92:4fc01daae5a5 152 #define BSC_SDCR_RMODE (0x00000400uL)
bogdanm 92:4fc01daae5a5 153 #define BSC_SDCR_RFSH (0x00000800uL)
bogdanm 92:4fc01daae5a5 154 #define BSC_SDCR_DEEP (0x00002000uL)
bogdanm 92:4fc01daae5a5 155 #define BSC_SDCR_A2COL (0x00030000uL)
bogdanm 92:4fc01daae5a5 156 #define BSC_SDCR_A2ROW (0x00180000uL)
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 #define BSC_RTCSR_RRC (0x00000007uL)
bogdanm 92:4fc01daae5a5 159 #define BSC_RTCSR_CKS (0x00000038uL)
bogdanm 92:4fc01daae5a5 160 #define BSC_RTCSR_CMIE (0x00000040uL)
bogdanm 92:4fc01daae5a5 161 #define BSC_RTCSR_CMF (0x00000080uL)
bogdanm 92:4fc01daae5a5 162
bogdanm 92:4fc01daae5a5 163 #define BSC_RTCNT_D (0xFFFFFFFFuL)
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 #define BSC_RTCOR_D (0xFFFFFFFFuL)
bogdanm 92:4fc01daae5a5 166
bogdanm 92:4fc01daae5a5 167 #define BSC_TOSCOR0_D (0x0000FFFFuL)
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 #define BSC_TOSCOR1_D (0x0000FFFFuL)
bogdanm 92:4fc01daae5a5 170
bogdanm 92:4fc01daae5a5 171 #define BSC_TOSCOR2_D (0x0000FFFFuL)
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173 #define BSC_TOSCOR3_D (0x0000FFFFuL)
bogdanm 92:4fc01daae5a5 174
bogdanm 92:4fc01daae5a5 175 #define BSC_TOSCOR4_D (0x0000FFFFuL)
bogdanm 92:4fc01daae5a5 176
bogdanm 92:4fc01daae5a5 177 #define BSC_TOSCOR5_D (0x0000FFFFuL)
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179 #define BSC_TOSTR_CS0TOSTF (0x00000001uL)
bogdanm 92:4fc01daae5a5 180 #define BSC_TOSTR_CS1TOSTF (0x00000002uL)
bogdanm 92:4fc01daae5a5 181 #define BSC_TOSTR_CS2TOSTF (0x00000004uL)
bogdanm 92:4fc01daae5a5 182 #define BSC_TOSTR_CS3TOSTF (0x00000008uL)
bogdanm 92:4fc01daae5a5 183 #define BSC_TOSTR_CS4TOSTF (0x00000010uL)
bogdanm 92:4fc01daae5a5 184 #define BSC_TOSTR_CS5TOSTF (0x00000020uL)
bogdanm 92:4fc01daae5a5 185
bogdanm 92:4fc01daae5a5 186 #define BSC_TOENR_CS0TOEN (0x00000001uL)
bogdanm 92:4fc01daae5a5 187 #define BSC_TOENR_CS1TOEN (0x00000002uL)
bogdanm 92:4fc01daae5a5 188 #define BSC_TOENR_CS2TOEN (0x00000004uL)
bogdanm 92:4fc01daae5a5 189 #define BSC_TOENR_CS3TOEN (0x00000008uL)
bogdanm 92:4fc01daae5a5 190 #define BSC_TOENR_CS4TOEN (0x00000010uL)
bogdanm 92:4fc01daae5a5 191 #define BSC_TOENR_CS5TOEN (0x00000020uL)
bogdanm 92:4fc01daae5a5 192
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194 /* ==== Shift values for IO registers ==== */
bogdanm 92:4fc01daae5a5 195 #define BSC_CMNCR_HIZCNT_SHIFT (0u)
bogdanm 92:4fc01daae5a5 196 #define BSC_CMNCR_HIZMEM_SHIFT (1u)
bogdanm 92:4fc01daae5a5 197 #define BSC_CMNCR_DPRTY_SHIFT (9u)
bogdanm 92:4fc01daae5a5 198 #define BSC_CMNCR_AL0_SHIFT (24u)
bogdanm 92:4fc01daae5a5 199 #define BSC_CMNCR_TL0_SHIFT (28u)
bogdanm 92:4fc01daae5a5 200
bogdanm 92:4fc01daae5a5 201 #define BSC_CS0BCR_BSZ_SHIFT (9u)
bogdanm 92:4fc01daae5a5 202 #define BSC_CS0BCR_TYPE_SHIFT (12u)
bogdanm 92:4fc01daae5a5 203 #define BSC_CS0BCR_IWRRS_SHIFT (16u)
bogdanm 92:4fc01daae5a5 204 #define BSC_CS0BCR_IWRRD_SHIFT (19u)
bogdanm 92:4fc01daae5a5 205 #define BSC_CS0BCR_IWRWS_SHIFT (22u)
bogdanm 92:4fc01daae5a5 206 #define BSC_CS0BCR_IWRWD_SHIFT (25u)
bogdanm 92:4fc01daae5a5 207 #define BSC_CS0BCR_IWW_SHIFT (28u)
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 #define BSC_CS1BCR_BSZ_SHIFT (9u)
bogdanm 92:4fc01daae5a5 210 #define BSC_CS1BCR_TYPE_SHIFT (12u)
bogdanm 92:4fc01daae5a5 211 #define BSC_CS1BCR_IWRRS_SHIFT (16u)
bogdanm 92:4fc01daae5a5 212 #define BSC_CS1BCR_IWRRD_SHIFT (19u)
bogdanm 92:4fc01daae5a5 213 #define BSC_CS1BCR_IWRWS_SHIFT (22u)
bogdanm 92:4fc01daae5a5 214 #define BSC_CS1BCR_IWRWD_SHIFT (25u)
bogdanm 92:4fc01daae5a5 215 #define BSC_CS1BCR_IWW_SHIFT (28u)
bogdanm 92:4fc01daae5a5 216
bogdanm 92:4fc01daae5a5 217 #define BSC_CS2BCR_BSZ_SHIFT (9u)
bogdanm 92:4fc01daae5a5 218 #define BSC_CS2BCR_TYPE_SHIFT (12u)
bogdanm 92:4fc01daae5a5 219 #define BSC_CS2BCR_IWRRS_SHIFT (16u)
bogdanm 92:4fc01daae5a5 220 #define BSC_CS2BCR_IWRRD_SHIFT (19u)
bogdanm 92:4fc01daae5a5 221 #define BSC_CS2BCR_IWRWS_SHIFT (22u)
bogdanm 92:4fc01daae5a5 222 #define BSC_CS2BCR_IWRWD_SHIFT (25u)
bogdanm 92:4fc01daae5a5 223 #define BSC_CS2BCR_IWW_SHIFT (28u)
bogdanm 92:4fc01daae5a5 224
bogdanm 92:4fc01daae5a5 225 #define BSC_CS3BCR_BSZ_SHIFT (9u)
bogdanm 92:4fc01daae5a5 226 #define BSC_CS3BCR_TYPE_SHIFT (12u)
bogdanm 92:4fc01daae5a5 227 #define BSC_CS3BCR_IWRRS_SHIFT (16u)
bogdanm 92:4fc01daae5a5 228 #define BSC_CS3BCR_IWRRD_SHIFT (19u)
bogdanm 92:4fc01daae5a5 229 #define BSC_CS3BCR_IWRWS_SHIFT (22u)
bogdanm 92:4fc01daae5a5 230 #define BSC_CS3BCR_IWRWD_SHIFT (25u)
bogdanm 92:4fc01daae5a5 231 #define BSC_CS3BCR_IWW_SHIFT (28u)
bogdanm 92:4fc01daae5a5 232
bogdanm 92:4fc01daae5a5 233 #define BSC_CS4BCR_BSZ_SHIFT (9u)
bogdanm 92:4fc01daae5a5 234 #define BSC_CS4BCR_TYPE_SHIFT (12u)
bogdanm 92:4fc01daae5a5 235 #define BSC_CS4BCR_IWRRS_SHIFT (16u)
bogdanm 92:4fc01daae5a5 236 #define BSC_CS4BCR_IWRRD_SHIFT (19u)
bogdanm 92:4fc01daae5a5 237 #define BSC_CS4BCR_IWRWS_SHIFT (22u)
bogdanm 92:4fc01daae5a5 238 #define BSC_CS4BCR_IWRWD_SHIFT (25u)
bogdanm 92:4fc01daae5a5 239 #define BSC_CS4BCR_IWW_SHIFT (28u)
bogdanm 92:4fc01daae5a5 240
bogdanm 92:4fc01daae5a5 241 #define BSC_CS5BCR_BSZ_SHIFT (9u)
bogdanm 92:4fc01daae5a5 242 #define BSC_CS5BCR_TYPE_SHIFT (12u)
bogdanm 92:4fc01daae5a5 243 #define BSC_CS5BCR_IWRRS_SHIFT (16u)
bogdanm 92:4fc01daae5a5 244 #define BSC_CS5BCR_IWRRD_SHIFT (19u)
bogdanm 92:4fc01daae5a5 245 #define BSC_CS5BCR_IWRWS_SHIFT (22u)
bogdanm 92:4fc01daae5a5 246 #define BSC_CS5BCR_IWRWD_SHIFT (25u)
bogdanm 92:4fc01daae5a5 247 #define BSC_CS5BCR_IWW_SHIFT (28u)
bogdanm 92:4fc01daae5a5 248
bogdanm 92:4fc01daae5a5 249 #define BSC_CS0WCR_NORMAL_HW_SHIFT (0u)
bogdanm 92:4fc01daae5a5 250 #define BSC_CS0WCR_NORMAL_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 251 #define BSC_CS0WCR_NORMAL_WR_SHIFT (7u)
bogdanm 92:4fc01daae5a5 252 #define BSC_CS0WCR_NORMAL_SW_SHIFT (11u)
bogdanm 92:4fc01daae5a5 253 #define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u)
bogdanm 92:4fc01daae5a5 254
bogdanm 92:4fc01daae5a5 255 #define BSC_CS1WCR_NORMAL_HW_SHIFT (0u)
bogdanm 92:4fc01daae5a5 256 #define BSC_CS1WCR_NORMAL_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 257 #define BSC_CS1WCR_NORMAL_WR_SHIFT (7u)
bogdanm 92:4fc01daae5a5 258 #define BSC_CS1WCR_NORMAL_SW_SHIFT (11u)
bogdanm 92:4fc01daae5a5 259 #define BSC_CS1WCR_NORMAL_WW_SHIFT (16u)
bogdanm 92:4fc01daae5a5 260 #define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u)
bogdanm 92:4fc01daae5a5 261
bogdanm 92:4fc01daae5a5 262 #define BSC_CS2WCR_NORMAL_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 263 #define BSC_CS2WCR_NORMAL_WR_SHIFT (7u)
bogdanm 92:4fc01daae5a5 264 #define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u)
bogdanm 92:4fc01daae5a5 265
bogdanm 92:4fc01daae5a5 266 #define BSC_CS3WCR_NORMAL_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 267 #define BSC_CS3WCR_NORMAL_WR_SHIFT (7u)
bogdanm 92:4fc01daae5a5 268 #define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u)
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270 #define BSC_CS4WCR_NORMAL_HW_SHIFT (0u)
bogdanm 92:4fc01daae5a5 271 #define BSC_CS4WCR_NORMAL_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 272 #define BSC_CS4WCR_NORMAL_WR_SHIFT (7u)
bogdanm 92:4fc01daae5a5 273 #define BSC_CS4WCR_NORMAL_SW_SHIFT (11u)
bogdanm 92:4fc01daae5a5 274 #define BSC_CS4WCR_NORMAL_WW_SHIFT (16u)
bogdanm 92:4fc01daae5a5 275 #define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u)
bogdanm 92:4fc01daae5a5 276
bogdanm 92:4fc01daae5a5 277 #define BSC_CS5WCR_NORMAL_HW_SHIFT (0u)
bogdanm 92:4fc01daae5a5 278 #define BSC_CS5WCR_NORMAL_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 279 #define BSC_CS5WCR_NORMAL_WR_SHIFT (7u)
bogdanm 92:4fc01daae5a5 280 #define BSC_CS5WCR_NORMAL_SW_SHIFT (11u)
bogdanm 92:4fc01daae5a5 281 #define BSC_CS5WCR_NORMAL_WW_SHIFT (16u)
bogdanm 92:4fc01daae5a5 282 #define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u)
bogdanm 92:4fc01daae5a5 283 #define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u)
bogdanm 92:4fc01daae5a5 284
bogdanm 92:4fc01daae5a5 285 #define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 286 #define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u)
bogdanm 92:4fc01daae5a5 287 #define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u)
bogdanm 92:4fc01daae5a5 288 #define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u)
bogdanm 92:4fc01daae5a5 289
bogdanm 92:4fc01daae5a5 290 #define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u)
bogdanm 92:4fc01daae5a5 291 #define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 292 #define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u)
bogdanm 92:4fc01daae5a5 293 #define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u)
bogdanm 92:4fc01daae5a5 294 #define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u)
bogdanm 92:4fc01daae5a5 295 #define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u)
bogdanm 92:4fc01daae5a5 296
bogdanm 92:4fc01daae5a5 297 #define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u)
bogdanm 92:4fc01daae5a5 298
bogdanm 92:4fc01daae5a5 299 #define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u)
bogdanm 92:4fc01daae5a5 300 #define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u)
bogdanm 92:4fc01daae5a5 301 #define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u)
bogdanm 92:4fc01daae5a5 302 #define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u)
bogdanm 92:4fc01daae5a5 303 #define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u)
bogdanm 92:4fc01daae5a5 304
bogdanm 92:4fc01daae5a5 305 #define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u)
bogdanm 92:4fc01daae5a5 306 #define BSC_CS0WCR_BROM_SY_W_SHIFT (7u)
bogdanm 92:4fc01daae5a5 307 #define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u)
bogdanm 92:4fc01daae5a5 308
bogdanm 92:4fc01daae5a5 309 #define BSC_SDCR_A3COL_SHIFT (0u)
bogdanm 92:4fc01daae5a5 310 #define BSC_SDCR_A3ROW_SHIFT (3u)
bogdanm 92:4fc01daae5a5 311 #define BSC_SDCR_BACTV_SHIFT (8u)
bogdanm 92:4fc01daae5a5 312 #define BSC_SDCR_PDOWN_SHIFT (9u)
bogdanm 92:4fc01daae5a5 313 #define BSC_SDCR_RMODE_SHIFT (10u)
bogdanm 92:4fc01daae5a5 314 #define BSC_SDCR_RFSH_SHIFT (11u)
bogdanm 92:4fc01daae5a5 315 #define BSC_SDCR_DEEP_SHIFT (13u)
bogdanm 92:4fc01daae5a5 316 #define BSC_SDCR_A2COL_SHIFT (16u)
bogdanm 92:4fc01daae5a5 317 #define BSC_SDCR_A2ROW_SHIFT (19u)
bogdanm 92:4fc01daae5a5 318
bogdanm 92:4fc01daae5a5 319 #define BSC_RTCSR_RRC_SHIFT (0u)
bogdanm 92:4fc01daae5a5 320 #define BSC_RTCSR_CKS_SHIFT (3u)
bogdanm 92:4fc01daae5a5 321 #define BSC_RTCSR_CMIE_SHIFT (6u)
bogdanm 92:4fc01daae5a5 322 #define BSC_RTCSR_CMF_SHIFT (7u)
bogdanm 92:4fc01daae5a5 323
bogdanm 92:4fc01daae5a5 324 #define BSC_RTCNT_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 325
bogdanm 92:4fc01daae5a5 326 #define BSC_RTCOR_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 327
bogdanm 92:4fc01daae5a5 328 #define BSC_TOSCOR0_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 329
bogdanm 92:4fc01daae5a5 330 #define BSC_TOSCOR1_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 331
bogdanm 92:4fc01daae5a5 332 #define BSC_TOSCOR2_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 333
bogdanm 92:4fc01daae5a5 334 #define BSC_TOSCOR3_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 335
bogdanm 92:4fc01daae5a5 336 #define BSC_TOSCOR4_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 337
bogdanm 92:4fc01daae5a5 338 #define BSC_TOSCOR5_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 339
bogdanm 92:4fc01daae5a5 340 #define BSC_TOSTR_CS0TOSTF_SHIFT (0u)
bogdanm 92:4fc01daae5a5 341 #define BSC_TOSTR_CS1TOSTF_SHIFT (1u)
bogdanm 92:4fc01daae5a5 342 #define BSC_TOSTR_CS2TOSTF_SHIFT (2u)
bogdanm 92:4fc01daae5a5 343 #define BSC_TOSTR_CS3TOSTF_SHIFT (3u)
bogdanm 92:4fc01daae5a5 344 #define BSC_TOSTR_CS4TOSTF_SHIFT (4u)
bogdanm 92:4fc01daae5a5 345 #define BSC_TOSTR_CS5TOSTF_SHIFT (5u)
bogdanm 92:4fc01daae5a5 346
bogdanm 92:4fc01daae5a5 347 #define BSC_TOENR_CS0TOEN_SHIFT (0u)
bogdanm 92:4fc01daae5a5 348 #define BSC_TOENR_CS1TOEN_SHIFT (1u)
bogdanm 92:4fc01daae5a5 349 #define BSC_TOENR_CS2TOEN_SHIFT (2u)
bogdanm 92:4fc01daae5a5 350 #define BSC_TOENR_CS3TOEN_SHIFT (3u)
bogdanm 92:4fc01daae5a5 351 #define BSC_TOENR_CS4TOEN_SHIFT (4u)
bogdanm 92:4fc01daae5a5 352 #define BSC_TOENR_CS5TOEN_SHIFT (5u)
bogdanm 92:4fc01daae5a5 353
bogdanm 92:4fc01daae5a5 354
bogdanm 92:4fc01daae5a5 355 #endif /* BSC_IOBITMASK_H */
bogdanm 92:4fc01daae5a5 356
bogdanm 92:4fc01daae5a5 357 /* End of File */