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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_pwr.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_pwr.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of PWR HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_PWR_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_PWR_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup PWR
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /**
bogdanm 92:4fc01daae5a5 59 * @brief PWR PVD configuration structure definition
bogdanm 92:4fc01daae5a5 60 */
bogdanm 92:4fc01daae5a5 61 typedef struct
bogdanm 92:4fc01daae5a5 62 {
bogdanm 92:4fc01daae5a5 63 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
bogdanm 92:4fc01daae5a5 64 This parameter can be a value of @ref PWR_PVD_detection_level */
bogdanm 92:4fc01daae5a5 65
bogdanm 92:4fc01daae5a5 66 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
bogdanm 92:4fc01daae5a5 67 This parameter can be a value of @ref PWR_PVD_Mode */
bogdanm 92:4fc01daae5a5 68 }PWR_PVDTypeDef;
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 71 /* ------------- PWR registers bit address in the alias region ---------------*/
bogdanm 92:4fc01daae5a5 72 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
bogdanm 92:4fc01daae5a5 73
bogdanm 92:4fc01daae5a5 74 /* --- CR Register ---*/
bogdanm 92:4fc01daae5a5 75 /* Alias word address of DBP bit */
bogdanm 92:4fc01daae5a5 76 #define CR_OFFSET (PWR_OFFSET + 0x00)
bogdanm 92:4fc01daae5a5 77 #define DBP_BitNumber 0x08
bogdanm 92:4fc01daae5a5 78 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 /* Alias word address of PVDE bit */
bogdanm 92:4fc01daae5a5 81 #define PVDE_BitNumber 0x04
bogdanm 92:4fc01daae5a5 82 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
bogdanm 92:4fc01daae5a5 83
bogdanm 92:4fc01daae5a5 84 /* Alias word address of PMODE bit */
bogdanm 92:4fc01daae5a5 85 #define PMODE_BitNumber 0x0E
bogdanm 92:4fc01daae5a5 86 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 /* --- CSR Register ---*/
bogdanm 92:4fc01daae5a5 89 /* Alias word address of EWUP bit */
bogdanm 92:4fc01daae5a5 90 #define CSR_OFFSET (PWR_OFFSET + 0x04)
bogdanm 92:4fc01daae5a5 91 #define EWUP_BitNumber 0x08
bogdanm 92:4fc01daae5a5 92 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 /** @defgroup PWR_Exported_Constants
bogdanm 92:4fc01daae5a5 95 * @{
bogdanm 92:4fc01daae5a5 96 */
bogdanm 92:4fc01daae5a5 97
bogdanm 92:4fc01daae5a5 98 /** @defgroup PWR_WakeUp_Pins
bogdanm 92:4fc01daae5a5 99 * @{
bogdanm 92:4fc01daae5a5 100 */
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
bogdanm 92:4fc01daae5a5 103 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
bogdanm 92:4fc01daae5a5 104 /**
bogdanm 92:4fc01daae5a5 105 * @}
bogdanm 92:4fc01daae5a5 106 */
bogdanm 92:4fc01daae5a5 107
bogdanm 92:4fc01daae5a5 108 /** @defgroup PWR_PVD_detection_level
bogdanm 92:4fc01daae5a5 109 * @{
bogdanm 92:4fc01daae5a5 110 */
bogdanm 92:4fc01daae5a5 111 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
bogdanm 92:4fc01daae5a5 112 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
bogdanm 92:4fc01daae5a5 113 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
bogdanm 92:4fc01daae5a5 114 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
bogdanm 92:4fc01daae5a5 115 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
bogdanm 92:4fc01daae5a5 116 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
bogdanm 92:4fc01daae5a5 117 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
bogdanm 92:4fc01daae5a5 118 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
bogdanm 92:4fc01daae5a5 119 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
bogdanm 92:4fc01daae5a5 120 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
bogdanm 92:4fc01daae5a5 121 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
bogdanm 92:4fc01daae5a5 122 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
bogdanm 92:4fc01daae5a5 123 /**
bogdanm 92:4fc01daae5a5 124 * @}
bogdanm 92:4fc01daae5a5 125 */
bogdanm 92:4fc01daae5a5 126
bogdanm 92:4fc01daae5a5 127 /** @defgroup PWR_PVD_Mode
bogdanm 92:4fc01daae5a5 128 * @{
bogdanm 92:4fc01daae5a5 129 */
bogdanm 92:4fc01daae5a5 130 #define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
bogdanm 92:4fc01daae5a5 131 #define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
bogdanm 92:4fc01daae5a5 132 #define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
bogdanm 92:4fc01daae5a5 133 #define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
bogdanm 92:4fc01daae5a5 134 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
bogdanm 92:4fc01daae5a5 135 ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
bogdanm 92:4fc01daae5a5 136 /**
bogdanm 92:4fc01daae5a5 137 * @}
bogdanm 92:4fc01daae5a5 138 */
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 /** @defgroup PWR_Regulator_state_in_STOP_mode
bogdanm 92:4fc01daae5a5 141 * @{
bogdanm 92:4fc01daae5a5 142 */
bogdanm 92:4fc01daae5a5 143 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 144 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
bogdanm 92:4fc01daae5a5 145
bogdanm 92:4fc01daae5a5 146 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
bogdanm 92:4fc01daae5a5 147 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
bogdanm 92:4fc01daae5a5 148 /**
bogdanm 92:4fc01daae5a5 149 * @}
bogdanm 92:4fc01daae5a5 150 */
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 /** @defgroup PWR_SLEEP_mode_entry
bogdanm 92:4fc01daae5a5 153 * @{
bogdanm 92:4fc01daae5a5 154 */
bogdanm 92:4fc01daae5a5 155 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
bogdanm 92:4fc01daae5a5 156 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
bogdanm 92:4fc01daae5a5 157 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
bogdanm 92:4fc01daae5a5 158 /**
bogdanm 92:4fc01daae5a5 159 * @}
bogdanm 92:4fc01daae5a5 160 */
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 /** @defgroup PWR_STOP_mode_entry
bogdanm 92:4fc01daae5a5 163 * @{
bogdanm 92:4fc01daae5a5 164 */
bogdanm 92:4fc01daae5a5 165 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
bogdanm 92:4fc01daae5a5 166 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
bogdanm 92:4fc01daae5a5 167 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
bogdanm 92:4fc01daae5a5 168 /**
bogdanm 92:4fc01daae5a5 169 * @}
bogdanm 92:4fc01daae5a5 170 */
bogdanm 92:4fc01daae5a5 171
bogdanm 92:4fc01daae5a5 172 /** @defgroup PWR_Regulator_Voltage_Scale
bogdanm 92:4fc01daae5a5 173 * @{
bogdanm 92:4fc01daae5a5 174 */
bogdanm 92:4fc01daae5a5 175 #define PWR_REGULATOR_VOLTAGE_SCALE1 ((uint32_t)0x0000C000)
bogdanm 92:4fc01daae5a5 176 #define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 177 #define PWR_REGULATOR_VOLTAGE_SCALE3 ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 178 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
bogdanm 92:4fc01daae5a5 179 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
bogdanm 92:4fc01daae5a5 180 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
bogdanm 92:4fc01daae5a5 181 /**
bogdanm 92:4fc01daae5a5 182 * @}
bogdanm 92:4fc01daae5a5 183 */
bogdanm 92:4fc01daae5a5 184
bogdanm 92:4fc01daae5a5 185 /** @defgroup PWR_Flag
bogdanm 92:4fc01daae5a5 186 * @{
bogdanm 92:4fc01daae5a5 187 */
bogdanm 92:4fc01daae5a5 188 #define PWR_FLAG_WU PWR_CSR_WUF
bogdanm 92:4fc01daae5a5 189 #define PWR_FLAG_SB PWR_CSR_SBF
bogdanm 92:4fc01daae5a5 190 #define PWR_FLAG_PVDO PWR_CSR_PVDO
bogdanm 92:4fc01daae5a5 191 #define PWR_FLAG_BRR PWR_CSR_BRR
bogdanm 92:4fc01daae5a5 192 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194 /**
bogdanm 92:4fc01daae5a5 195 * @}
bogdanm 92:4fc01daae5a5 196 */
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 /**
bogdanm 92:4fc01daae5a5 199 * @}
bogdanm 92:4fc01daae5a5 200 */
bogdanm 92:4fc01daae5a5 201
bogdanm 92:4fc01daae5a5 202 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 203
bogdanm 92:4fc01daae5a5 204 /** @brief macros configure the main internal regulator output voltage.
bogdanm 92:4fc01daae5a5 205 * @param __REGULATOR__: specifies the regulator output voltage to achieve
bogdanm 92:4fc01daae5a5 206 * a tradeoff between performance and power consumption when the device does
bogdanm 92:4fc01daae5a5 207 * not operate at the maximum frequency (refer to the datasheets for more details).
bogdanm 92:4fc01daae5a5 208 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 209 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
bogdanm 92:4fc01daae5a5 210 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
bogdanm 92:4fc01daae5a5 211 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
bogdanm 92:4fc01daae5a5 212 * @retval None
bogdanm 92:4fc01daae5a5 213 */
bogdanm 92:4fc01daae5a5 214 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
bogdanm 92:4fc01daae5a5 215
bogdanm 92:4fc01daae5a5 216 /** @brief Check PWR flag is set or not.
bogdanm 92:4fc01daae5a5 217 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 218 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 219 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
bogdanm 92:4fc01daae5a5 220 * was received from the WKUP pin or from the RTC alarm (Alarm A
bogdanm 92:4fc01daae5a5 221 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
bogdanm 92:4fc01daae5a5 222 * An additional wakeup event is detected if the WKUP pin is enabled
bogdanm 92:4fc01daae5a5 223 * (by setting the EWUP bit) when the WKUP pin level is already high.
bogdanm 92:4fc01daae5a5 224 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
bogdanm 92:4fc01daae5a5 225 * resumed from StandBy mode.
bogdanm 92:4fc01daae5a5 226 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
bogdanm 92:4fc01daae5a5 227 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
bogdanm 92:4fc01daae5a5 228 * For this reason, this bit is equal to 0 after Standby or reset
bogdanm 92:4fc01daae5a5 229 * until the PVDE bit is set.
bogdanm 92:4fc01daae5a5 230 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
bogdanm 92:4fc01daae5a5 231 * when the device wakes up from Standby mode or by a system reset
bogdanm 92:4fc01daae5a5 232 * or power reset.
bogdanm 92:4fc01daae5a5 233 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
bogdanm 92:4fc01daae5a5 234 * scaling output selection is ready.
bogdanm 92:4fc01daae5a5 235 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 236 */
bogdanm 92:4fc01daae5a5 237 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 238
bogdanm 92:4fc01daae5a5 239 /** @brief Clear the PWR's pending flags.
bogdanm 92:4fc01daae5a5 240 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 241 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 242 * @arg PWR_FLAG_WU: Wake Up flag
bogdanm 92:4fc01daae5a5 243 * @arg PWR_FLAG_SB: StandBy flag
bogdanm 92:4fc01daae5a5 244 */
bogdanm 92:4fc01daae5a5 245 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
bogdanm 92:4fc01daae5a5 246
bogdanm 92:4fc01daae5a5 247 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
bogdanm 92:4fc01daae5a5 248 /**
bogdanm 92:4fc01daae5a5 249 * @brief Enable the PVD Exti Line.
bogdanm 92:4fc01daae5a5 250 * @param __EXTILINE__: specifies the PVD Exti sources to be enabled.
bogdanm 92:4fc01daae5a5 251 * This parameter can be:
bogdanm 92:4fc01daae5a5 252 * @arg PWR_EXTI_LINE_PVD
bogdanm 92:4fc01daae5a5 253 * @retval None.
bogdanm 92:4fc01daae5a5 254 */
bogdanm 92:4fc01daae5a5 255 #define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
bogdanm 92:4fc01daae5a5 256
bogdanm 92:4fc01daae5a5 257 /**
bogdanm 92:4fc01daae5a5 258 * @brief Disable the PVD EXTI Line.
bogdanm 92:4fc01daae5a5 259 * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
bogdanm 92:4fc01daae5a5 260 * This parameter can be:
bogdanm 92:4fc01daae5a5 261 * @arg PWR_EXTI_LINE_PVD
bogdanm 92:4fc01daae5a5 262 * @retval None.
bogdanm 92:4fc01daae5a5 263 */
bogdanm 92:4fc01daae5a5 264 #define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
bogdanm 92:4fc01daae5a5 265
bogdanm 92:4fc01daae5a5 266 /**
bogdanm 92:4fc01daae5a5 267 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
bogdanm 92:4fc01daae5a5 268 * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
bogdanm 92:4fc01daae5a5 269 * This parameter can be:
bogdanm 92:4fc01daae5a5 270 * @arg PWR_EXTI_LINE_PVD
bogdanm 92:4fc01daae5a5 271 * @retval EXTI PVD Line Status.
bogdanm 92:4fc01daae5a5 272 */
bogdanm 92:4fc01daae5a5 273 #define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
bogdanm 92:4fc01daae5a5 274
bogdanm 92:4fc01daae5a5 275 /**
bogdanm 92:4fc01daae5a5 276 * @brief Clear the PVD Exti flag.
bogdanm 92:4fc01daae5a5 277 * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
bogdanm 92:4fc01daae5a5 278 * This parameter can be:
bogdanm 92:4fc01daae5a5 279 * @arg PWR_EXTI_LINE_PVD
bogdanm 92:4fc01daae5a5 280 * @retval None.
bogdanm 92:4fc01daae5a5 281 */
bogdanm 92:4fc01daae5a5 282 #define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
bogdanm 92:4fc01daae5a5 283
bogdanm 92:4fc01daae5a5 284 /**
bogdanm 92:4fc01daae5a5 285 * @brief Generates a Software interrupt on selected EXTI line.
bogdanm 92:4fc01daae5a5 286 * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
bogdanm 92:4fc01daae5a5 287 * This parameter can be:
bogdanm 92:4fc01daae5a5 288 * @arg PWR_EXTI_LINE_PVD
bogdanm 92:4fc01daae5a5 289 * @retval None
bogdanm 92:4fc01daae5a5 290 */
bogdanm 92:4fc01daae5a5 291 #define __HAL_PVD_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
bogdanm 92:4fc01daae5a5 292
bogdanm 92:4fc01daae5a5 293 /* Include PWR HAL Extension module */
bogdanm 92:4fc01daae5a5 294 #include "stm32f4xx_hal_pwr_ex.h"
bogdanm 92:4fc01daae5a5 295
bogdanm 92:4fc01daae5a5 296 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 297
bogdanm 92:4fc01daae5a5 298 /* Initialization and de-initialization functions *****************************/
bogdanm 92:4fc01daae5a5 299 void HAL_PWR_DeInit(void);
bogdanm 92:4fc01daae5a5 300 void HAL_PWR_EnableBkUpAccess(void);
bogdanm 92:4fc01daae5a5 301 void HAL_PWR_DisableBkUpAccess(void);
bogdanm 92:4fc01daae5a5 302
bogdanm 92:4fc01daae5a5 303 /* Peripheral Control functions **********************************************/
bogdanm 92:4fc01daae5a5 304 /* PVD configuration */
bogdanm 92:4fc01daae5a5 305 void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
bogdanm 92:4fc01daae5a5 306 void HAL_PWR_EnablePVD(void);
bogdanm 92:4fc01daae5a5 307 void HAL_PWR_DisablePVD(void);
bogdanm 92:4fc01daae5a5 308
bogdanm 92:4fc01daae5a5 309 /* WakeUp pins configuration */
bogdanm 92:4fc01daae5a5 310 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 92:4fc01daae5a5 311 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 92:4fc01daae5a5 312
bogdanm 92:4fc01daae5a5 313 /* Low Power modes entry */
bogdanm 92:4fc01daae5a5 314 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
bogdanm 92:4fc01daae5a5 315 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
bogdanm 92:4fc01daae5a5 316 void HAL_PWR_EnterSTANDBYMode(void);
bogdanm 92:4fc01daae5a5 317
bogdanm 92:4fc01daae5a5 318 void HAL_PWR_PVD_IRQHandler(void);
bogdanm 92:4fc01daae5a5 319 void HAL_PWR_PVDCallback(void);
bogdanm 92:4fc01daae5a5 320
bogdanm 92:4fc01daae5a5 321
bogdanm 92:4fc01daae5a5 322 /**
bogdanm 92:4fc01daae5a5 323 * @}
bogdanm 92:4fc01daae5a5 324 */
bogdanm 92:4fc01daae5a5 325
bogdanm 92:4fc01daae5a5 326 /**
bogdanm 92:4fc01daae5a5 327 * @}
bogdanm 92:4fc01daae5a5 328 */
bogdanm 92:4fc01daae5a5 329
bogdanm 92:4fc01daae5a5 330 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 331 }
bogdanm 92:4fc01daae5a5 332 #endif
bogdanm 92:4fc01daae5a5 333
bogdanm 92:4fc01daae5a5 334
bogdanm 92:4fc01daae5a5 335 #endif /* __STM32F4xx_HAL_PWR_H */
bogdanm 92:4fc01daae5a5 336
bogdanm 92:4fc01daae5a5 337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/