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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_nand.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_nand.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of NAND HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_NAND_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_NAND_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 92:4fc01daae5a5 48 #include "stm32f4xx_ll_fsmc.h"
bogdanm 92:4fc01daae5a5 49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 92:4fc01daae5a5 52 #include "stm32f4xx_ll_fmc.h"
bogdanm 92:4fc01daae5a5 53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 56 * @{
bogdanm 92:4fc01daae5a5 57 */
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /** @addtogroup NAND
bogdanm 92:4fc01daae5a5 60 * @{
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 92:4fc01daae5a5 64
bogdanm 92:4fc01daae5a5 65 /* Exported typedef ----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 66 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 67
bogdanm 92:4fc01daae5a5 68 /**
bogdanm 92:4fc01daae5a5 69 * @brief HAL NAND State structures definition
bogdanm 92:4fc01daae5a5 70 */
bogdanm 92:4fc01daae5a5 71 typedef enum
bogdanm 92:4fc01daae5a5 72 {
bogdanm 92:4fc01daae5a5 73 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 74 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
bogdanm 92:4fc01daae5a5 75 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
bogdanm 92:4fc01daae5a5 76 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
bogdanm 92:4fc01daae5a5 77 }HAL_NAND_StateTypeDef;
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 /**
bogdanm 92:4fc01daae5a5 80 * @brief NAND Memory electronic signature Structure definition
bogdanm 92:4fc01daae5a5 81 */
bogdanm 92:4fc01daae5a5 82 typedef struct
bogdanm 92:4fc01daae5a5 83 {
bogdanm 92:4fc01daae5a5 84 /*<! NAND memory electronic signature maker and device IDs */
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 uint8_t Maker_Id;
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 uint8_t Device_Id;
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 uint8_t Third_Id;
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92 uint8_t Fourth_Id;
bogdanm 92:4fc01daae5a5 93 }NAND_IDTypeDef;
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95 /**
bogdanm 92:4fc01daae5a5 96 * @brief NAND Memory address Structure definition
bogdanm 92:4fc01daae5a5 97 */
bogdanm 92:4fc01daae5a5 98 typedef struct
bogdanm 92:4fc01daae5a5 99 {
bogdanm 92:4fc01daae5a5 100 uint16_t Page; /*!< NAND memory Page address */
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102 uint16_t Zone; /*!< NAND memory Zone address */
bogdanm 92:4fc01daae5a5 103
bogdanm 92:4fc01daae5a5 104 uint16_t Block; /*!< NAND memory Block address */
bogdanm 92:4fc01daae5a5 105
bogdanm 92:4fc01daae5a5 106 }NAND_AddressTypedef;
bogdanm 92:4fc01daae5a5 107
bogdanm 92:4fc01daae5a5 108 /**
bogdanm 92:4fc01daae5a5 109 * @brief NAND Memory info Structure definition
bogdanm 92:4fc01daae5a5 110 */
bogdanm 92:4fc01daae5a5 111 typedef struct
bogdanm 92:4fc01daae5a5 112 {
bogdanm 92:4fc01daae5a5 113 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 uint32_t BlockSize; /*!< NAND memory block size number of pages */
bogdanm 92:4fc01daae5a5 118
bogdanm 92:4fc01daae5a5 119 uint32_t BlockNbr; /*!< NAND memory number of blocks */
bogdanm 92:4fc01daae5a5 120
bogdanm 92:4fc01daae5a5 121 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
bogdanm 92:4fc01daae5a5 122 }NAND_InfoTypeDef;
bogdanm 92:4fc01daae5a5 123
bogdanm 92:4fc01daae5a5 124 /**
bogdanm 92:4fc01daae5a5 125 * @brief NAND handle Structure definition
bogdanm 92:4fc01daae5a5 126 */
bogdanm 92:4fc01daae5a5 127 typedef struct
bogdanm 92:4fc01daae5a5 128 {
bogdanm 92:4fc01daae5a5 129 FMC_NAND_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133 HAL_LockTypeDef Lock; /*!< NAND locking object */
bogdanm 92:4fc01daae5a5 134
bogdanm 92:4fc01daae5a5 135 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
bogdanm 92:4fc01daae5a5 138 }NAND_HandleTypeDef;
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140
bogdanm 92:4fc01daae5a5 141 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 142 /** @defgroup NAND_Exported_Constants
bogdanm 92:4fc01daae5a5 143 * @{
bogdanm 92:4fc01daae5a5 144 */
bogdanm 92:4fc01daae5a5 145 #define NAND_DEVICE1 ((uint32_t)0x70000000)
bogdanm 92:4fc01daae5a5 146 #define NAND_DEVICE2 ((uint32_t)0x80000000)
bogdanm 92:4fc01daae5a5 147 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
bogdanm 92:4fc01daae5a5 150 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 #define NAND_CMD_AREA_A ((uint8_t)0x00)
bogdanm 92:4fc01daae5a5 153 #define NAND_CMD_AREA_B ((uint8_t)0x01)
bogdanm 92:4fc01daae5a5 154 #define NAND_CMD_AREA_C ((uint8_t)0x50)
bogdanm 92:4fc01daae5a5 155 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
bogdanm 92:4fc01daae5a5 156
bogdanm 92:4fc01daae5a5 157 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
bogdanm 92:4fc01daae5a5 158 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
bogdanm 92:4fc01daae5a5 159 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
bogdanm 92:4fc01daae5a5 160 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
bogdanm 92:4fc01daae5a5 161 #define NAND_CMD_READID ((uint8_t)0x90)
bogdanm 92:4fc01daae5a5 162 #define NAND_CMD_STATUS ((uint8_t)0x70)
bogdanm 92:4fc01daae5a5 163 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
bogdanm 92:4fc01daae5a5 164 #define NAND_CMD_RESET ((uint8_t)0xFF)
bogdanm 92:4fc01daae5a5 165
bogdanm 92:4fc01daae5a5 166 /* NAND memory status */
bogdanm 92:4fc01daae5a5 167 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 168 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 169 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 170 #define NAND_BUSY ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 171 #define NAND_ERROR ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 172 #define NAND_READY ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174 /**
bogdanm 92:4fc01daae5a5 175 * @}
bogdanm 92:4fc01daae5a5 176 */
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 179
bogdanm 92:4fc01daae5a5 180 /** @brief Reset NAND handle state
bogdanm 92:4fc01daae5a5 181 * @param __HANDLE__: specifies the NAND handle.
bogdanm 92:4fc01daae5a5 182 * @retval None
bogdanm 92:4fc01daae5a5 183 */
bogdanm 92:4fc01daae5a5 184 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
bogdanm 92:4fc01daae5a5 185
bogdanm 92:4fc01daae5a5 186 /**
bogdanm 92:4fc01daae5a5 187 * @brief NAND memory address computation.
bogdanm 92:4fc01daae5a5 188 * @param __ADDRESS__: NAND memory address.
bogdanm 92:4fc01daae5a5 189 * @param __HANDLE__ : NAND handle.
bogdanm 92:4fc01daae5a5 190 * @retval NAND Raw address value
bogdanm 92:4fc01daae5a5 191 */
bogdanm 92:4fc01daae5a5 192 #define __ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
bogdanm 92:4fc01daae5a5 193 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
bogdanm 92:4fc01daae5a5 194
bogdanm 92:4fc01daae5a5 195 /**
bogdanm 92:4fc01daae5a5 196 * @brief NAND memory address cycling.
bogdanm 92:4fc01daae5a5 197 * @param __ADDRESS__: NAND memory address.
bogdanm 92:4fc01daae5a5 198 * @retval NAND address cycling value.
bogdanm 92:4fc01daae5a5 199 */
bogdanm 92:4fc01daae5a5 200 #define __ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
bogdanm 92:4fc01daae5a5 201 #define __ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
bogdanm 92:4fc01daae5a5 202 #define __ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
bogdanm 92:4fc01daae5a5 203 #define __ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
bogdanm 92:4fc01daae5a5 204
bogdanm 92:4fc01daae5a5 205 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 206
bogdanm 92:4fc01daae5a5 207 /* Initialization/de-initialization functions ********************************/
bogdanm 92:4fc01daae5a5 208 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
bogdanm 92:4fc01daae5a5 209 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 210 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 211 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 212 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 213 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 214
bogdanm 92:4fc01daae5a5 215 /* IO operation functions ****************************************************/
bogdanm 92:4fc01daae5a5 216 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
bogdanm 92:4fc01daae5a5 217 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 218 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
bogdanm 92:4fc01daae5a5 219 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
bogdanm 92:4fc01daae5a5 220 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
bogdanm 92:4fc01daae5a5 221 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
bogdanm 92:4fc01daae5a5 222 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
bogdanm 92:4fc01daae5a5 223 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 224 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226 /* NAND Control functions ****************************************************/
bogdanm 92:4fc01daae5a5 227 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 228 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 229 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 230
bogdanm 92:4fc01daae5a5 231 /* NAND State functions *******************************************************/
bogdanm 92:4fc01daae5a5 232 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 233 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
bogdanm 92:4fc01daae5a5 234
bogdanm 92:4fc01daae5a5 235 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 92:4fc01daae5a5 236 /**
bogdanm 92:4fc01daae5a5 237 * @}
bogdanm 92:4fc01daae5a5 238 */
bogdanm 92:4fc01daae5a5 239
bogdanm 92:4fc01daae5a5 240 /**
bogdanm 92:4fc01daae5a5 241 * @}
bogdanm 92:4fc01daae5a5 242 */
bogdanm 92:4fc01daae5a5 243
bogdanm 92:4fc01daae5a5 244 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 245 }
bogdanm 92:4fc01daae5a5 246 #endif
bogdanm 92:4fc01daae5a5 247
bogdanm 92:4fc01daae5a5 248 #endif /* __STM32F4xx_HAL_NAND_H */
bogdanm 92:4fc01daae5a5 249
bogdanm 92:4fc01daae5a5 250 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/