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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_dma.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_dma.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of DMA HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_DMA_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_DMA_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup DMA
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /**
bogdanm 92:4fc01daae5a5 60 * @brief DMA Configuration Structure definition
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62 typedef struct
bogdanm 92:4fc01daae5a5 63 {
bogdanm 92:4fc01daae5a5 64 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
bogdanm 92:4fc01daae5a5 65 This parameter can be a value of @ref DMA_Channel_selection */
bogdanm 92:4fc01daae5a5 66
bogdanm 92:4fc01daae5a5 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 92:4fc01daae5a5 68 from memory to memory or from peripheral to memory.
bogdanm 92:4fc01daae5a5 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 92:4fc01daae5a5 70
bogdanm 92:4fc01daae5a5 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 92:4fc01daae5a5 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 92:4fc01daae5a5 73
bogdanm 92:4fc01daae5a5 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 92:4fc01daae5a5 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 92:4fc01daae5a5 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 92:4fc01daae5a5 81 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 92:4fc01daae5a5 82
bogdanm 92:4fc01daae5a5 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
bogdanm 92:4fc01daae5a5 84 This parameter can be a value of @ref DMA_mode
bogdanm 92:4fc01daae5a5 85 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 92:4fc01daae5a5 86 data transfer is configured on the selected Stream */
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
bogdanm 92:4fc01daae5a5 89 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 92:4fc01daae5a5 90
bogdanm 92:4fc01daae5a5 91 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
bogdanm 92:4fc01daae5a5 92 This parameter can be a value of @ref DMA_FIFO_direct_mode
bogdanm 92:4fc01daae5a5 93 @note The Direct mode (FIFO mode disabled) cannot be used if the
bogdanm 92:4fc01daae5a5 94 memory-to-memory data transfer is configured on the selected stream */
bogdanm 92:4fc01daae5a5 95
bogdanm 92:4fc01daae5a5 96 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
bogdanm 92:4fc01daae5a5 97 This parameter can be a value of @ref DMA_FIFO_threshold_level */
bogdanm 92:4fc01daae5a5 98
bogdanm 92:4fc01daae5a5 99 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
bogdanm 92:4fc01daae5a5 100 It specifies the amount of data to be transferred in a single non interruptable
bogdanm 92:4fc01daae5a5 101 transaction.
bogdanm 92:4fc01daae5a5 102 This parameter can be a value of @ref DMA_Memory_burst
bogdanm 92:4fc01daae5a5 103 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
bogdanm 92:4fc01daae5a5 106 It specifies the amount of data to be transferred in a single non interruptable
bogdanm 92:4fc01daae5a5 107 transaction.
bogdanm 92:4fc01daae5a5 108 This parameter can be a value of @ref DMA_Peripheral_burst
bogdanm 92:4fc01daae5a5 109 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 92:4fc01daae5a5 110 }DMA_InitTypeDef;
bogdanm 92:4fc01daae5a5 111
bogdanm 92:4fc01daae5a5 112 /**
bogdanm 92:4fc01daae5a5 113 * @brief HAL DMA State structures definition
bogdanm 92:4fc01daae5a5 114 */
bogdanm 92:4fc01daae5a5 115 typedef enum
bogdanm 92:4fc01daae5a5 116 {
bogdanm 92:4fc01daae5a5 117 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 118 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
bogdanm 92:4fc01daae5a5 119 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
bogdanm 92:4fc01daae5a5 120 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
bogdanm 92:4fc01daae5a5 121 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
bogdanm 92:4fc01daae5a5 122 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
bogdanm 92:4fc01daae5a5 123 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 92:4fc01daae5a5 124 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
bogdanm 92:4fc01daae5a5 125 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
bogdanm 92:4fc01daae5a5 126 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 92:4fc01daae5a5 127 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 92:4fc01daae5a5 128 }HAL_DMA_StateTypeDef;
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 /**
bogdanm 92:4fc01daae5a5 131 * @brief HAL DMA Error Code structure definition
bogdanm 92:4fc01daae5a5 132 */
bogdanm 92:4fc01daae5a5 133 typedef enum
bogdanm 92:4fc01daae5a5 134 {
bogdanm 92:4fc01daae5a5 135 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 92:4fc01daae5a5 136 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 92:4fc01daae5a5 137 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 92:4fc01daae5a5 138
bogdanm 92:4fc01daae5a5 139 /**
bogdanm 92:4fc01daae5a5 140 * @brief DMA handle Structure definition
bogdanm 92:4fc01daae5a5 141 */
bogdanm 92:4fc01daae5a5 142 typedef struct __DMA_HandleTypeDef
bogdanm 92:4fc01daae5a5 143 {
bogdanm 92:4fc01daae5a5 144 DMA_Stream_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 145
bogdanm 92:4fc01daae5a5 146 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 92:4fc01daae5a5 147
bogdanm 92:4fc01daae5a5 148 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 92:4fc01daae5a5 149
bogdanm 92:4fc01daae5a5 150 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 void *Parent; /*!< Parent object state */
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 92:4fc01daae5a5 155
bogdanm 92:4fc01daae5a5 156 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 92:4fc01daae5a5 163 }DMA_HandleTypeDef;
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 166
bogdanm 92:4fc01daae5a5 167 /** @defgroup DMA_Exported_Constants
bogdanm 92:4fc01daae5a5 168 * @{
bogdanm 92:4fc01daae5a5 169 */
bogdanm 92:4fc01daae5a5 170
bogdanm 92:4fc01daae5a5 171 /** @defgroup DMA_Error_Code
bogdanm 92:4fc01daae5a5 172 * @{
bogdanm 92:4fc01daae5a5 173 */
bogdanm 92:4fc01daae5a5 174 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 92:4fc01daae5a5 175 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 92:4fc01daae5a5 176 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
bogdanm 92:4fc01daae5a5 177 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
bogdanm 92:4fc01daae5a5 178 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 92:4fc01daae5a5 179 /**
bogdanm 92:4fc01daae5a5 180 * @}
bogdanm 92:4fc01daae5a5 181 */
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183 /** @defgroup DMA_Channel_selection
bogdanm 92:4fc01daae5a5 184 * @{
bogdanm 92:4fc01daae5a5 185 */
bogdanm 92:4fc01daae5a5 186 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
bogdanm 92:4fc01daae5a5 187 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
bogdanm 92:4fc01daae5a5 188 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
bogdanm 92:4fc01daae5a5 189 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
bogdanm 92:4fc01daae5a5 190 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
bogdanm 92:4fc01daae5a5 191 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
bogdanm 92:4fc01daae5a5 192 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
bogdanm 92:4fc01daae5a5 193 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
bogdanm 92:4fc01daae5a5 194
bogdanm 92:4fc01daae5a5 195 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
bogdanm 92:4fc01daae5a5 196 ((CHANNEL) == DMA_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 197 ((CHANNEL) == DMA_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 198 ((CHANNEL) == DMA_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 199 ((CHANNEL) == DMA_CHANNEL_4) || \
bogdanm 92:4fc01daae5a5 200 ((CHANNEL) == DMA_CHANNEL_5) || \
bogdanm 92:4fc01daae5a5 201 ((CHANNEL) == DMA_CHANNEL_6) || \
bogdanm 92:4fc01daae5a5 202 ((CHANNEL) == DMA_CHANNEL_7))
bogdanm 92:4fc01daae5a5 203 /**
bogdanm 92:4fc01daae5a5 204 * @}
bogdanm 92:4fc01daae5a5 205 */
bogdanm 92:4fc01daae5a5 206
bogdanm 92:4fc01daae5a5 207 /** @defgroup DMA_Data_transfer_direction
bogdanm 92:4fc01daae5a5 208 * @{
bogdanm 92:4fc01daae5a5 209 */
bogdanm 92:4fc01daae5a5 210 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 92:4fc01daae5a5 211 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
bogdanm 92:4fc01daae5a5 212 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
bogdanm 92:4fc01daae5a5 213
bogdanm 92:4fc01daae5a5 214 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 92:4fc01daae5a5 215 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 92:4fc01daae5a5 216 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 92:4fc01daae5a5 217 /**
bogdanm 92:4fc01daae5a5 218 * @}
bogdanm 92:4fc01daae5a5 219 */
bogdanm 92:4fc01daae5a5 220
bogdanm 92:4fc01daae5a5 221 /** @defgroup DMA_Data_buffer_size
bogdanm 92:4fc01daae5a5 222 * @{
bogdanm 92:4fc01daae5a5 223 */
bogdanm 92:4fc01daae5a5 224 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 92:4fc01daae5a5 225 /**
bogdanm 92:4fc01daae5a5 226 * @}
bogdanm 92:4fc01daae5a5 227 */
bogdanm 92:4fc01daae5a5 228
bogdanm 92:4fc01daae5a5 229 /** @defgroup DMA_Peripheral_incremented_mode
bogdanm 92:4fc01daae5a5 230 * @{
bogdanm 92:4fc01daae5a5 231 */
bogdanm 92:4fc01daae5a5 232 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
bogdanm 92:4fc01daae5a5 233 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
bogdanm 92:4fc01daae5a5 234
bogdanm 92:4fc01daae5a5 235 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 92:4fc01daae5a5 236 ((STATE) == DMA_PINC_DISABLE))
bogdanm 92:4fc01daae5a5 237 /**
bogdanm 92:4fc01daae5a5 238 * @}
bogdanm 92:4fc01daae5a5 239 */
bogdanm 92:4fc01daae5a5 240
bogdanm 92:4fc01daae5a5 241 /** @defgroup DMA_Memory_incremented_mode
bogdanm 92:4fc01daae5a5 242 * @{
bogdanm 92:4fc01daae5a5 243 */
bogdanm 92:4fc01daae5a5 244 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
bogdanm 92:4fc01daae5a5 245 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
bogdanm 92:4fc01daae5a5 246
bogdanm 92:4fc01daae5a5 247 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 92:4fc01daae5a5 248 ((STATE) == DMA_MINC_DISABLE))
bogdanm 92:4fc01daae5a5 249 /**
bogdanm 92:4fc01daae5a5 250 * @}
bogdanm 92:4fc01daae5a5 251 */
bogdanm 92:4fc01daae5a5 252
bogdanm 92:4fc01daae5a5 253 /** @defgroup DMA_Peripheral_data_size
bogdanm 92:4fc01daae5a5 254 * @{
bogdanm 92:4fc01daae5a5 255 */
bogdanm 92:4fc01daae5a5 256 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
bogdanm 92:4fc01daae5a5 257 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
bogdanm 92:4fc01daae5a5 258 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
bogdanm 92:4fc01daae5a5 259
bogdanm 92:4fc01daae5a5 260 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 92:4fc01daae5a5 261 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 92:4fc01daae5a5 262 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 92:4fc01daae5a5 263 /**
bogdanm 92:4fc01daae5a5 264 * @}
bogdanm 92:4fc01daae5a5 265 */
bogdanm 92:4fc01daae5a5 266
bogdanm 92:4fc01daae5a5 267
bogdanm 92:4fc01daae5a5 268 /** @defgroup DMA_Memory_data_size
bogdanm 92:4fc01daae5a5 269 * @{
bogdanm 92:4fc01daae5a5 270 */
bogdanm 92:4fc01daae5a5 271 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
bogdanm 92:4fc01daae5a5 272 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
bogdanm 92:4fc01daae5a5 273 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
bogdanm 92:4fc01daae5a5 274
bogdanm 92:4fc01daae5a5 275 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 92:4fc01daae5a5 276 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 92:4fc01daae5a5 277 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 92:4fc01daae5a5 278 /**
bogdanm 92:4fc01daae5a5 279 * @}
bogdanm 92:4fc01daae5a5 280 */
bogdanm 92:4fc01daae5a5 281
bogdanm 92:4fc01daae5a5 282 /** @defgroup DMA_mode
bogdanm 92:4fc01daae5a5 283 * @{
bogdanm 92:4fc01daae5a5 284 */
bogdanm 92:4fc01daae5a5 285 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
bogdanm 92:4fc01daae5a5 286 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
bogdanm 92:4fc01daae5a5 287 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
bogdanm 92:4fc01daae5a5 288
bogdanm 92:4fc01daae5a5 289 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 92:4fc01daae5a5 290 ((MODE) == DMA_CIRCULAR) || \
bogdanm 92:4fc01daae5a5 291 ((MODE) == DMA_PFCTRL))
bogdanm 92:4fc01daae5a5 292 /**
bogdanm 92:4fc01daae5a5 293 * @}
bogdanm 92:4fc01daae5a5 294 */
bogdanm 92:4fc01daae5a5 295
bogdanm 92:4fc01daae5a5 296 /** @defgroup DMA_Priority_level
bogdanm 92:4fc01daae5a5 297 * @{
bogdanm 92:4fc01daae5a5 298 */
bogdanm 92:4fc01daae5a5 299 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
bogdanm 92:4fc01daae5a5 300 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
bogdanm 92:4fc01daae5a5 301 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
bogdanm 92:4fc01daae5a5 302 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
bogdanm 92:4fc01daae5a5 303
bogdanm 92:4fc01daae5a5 304 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 92:4fc01daae5a5 305 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 92:4fc01daae5a5 306 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 92:4fc01daae5a5 307 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 92:4fc01daae5a5 308 /**
bogdanm 92:4fc01daae5a5 309 * @}
bogdanm 92:4fc01daae5a5 310 */
bogdanm 92:4fc01daae5a5 311
bogdanm 92:4fc01daae5a5 312 /** @defgroup DMA_FIFO_direct_mode
bogdanm 92:4fc01daae5a5 313 * @{
bogdanm 92:4fc01daae5a5 314 */
bogdanm 92:4fc01daae5a5 315 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
bogdanm 92:4fc01daae5a5 316 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
bogdanm 92:4fc01daae5a5 317
bogdanm 92:4fc01daae5a5 318 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
bogdanm 92:4fc01daae5a5 319 ((STATE) == DMA_FIFOMODE_ENABLE))
bogdanm 92:4fc01daae5a5 320 /**
bogdanm 92:4fc01daae5a5 321 * @}
bogdanm 92:4fc01daae5a5 322 */
bogdanm 92:4fc01daae5a5 323
bogdanm 92:4fc01daae5a5 324 /** @defgroup DMA_FIFO_threshold_level
bogdanm 92:4fc01daae5a5 325 * @{
bogdanm 92:4fc01daae5a5 326 */
bogdanm 92:4fc01daae5a5 327 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
bogdanm 92:4fc01daae5a5 328 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
bogdanm 92:4fc01daae5a5 329 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
bogdanm 92:4fc01daae5a5 330 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
bogdanm 92:4fc01daae5a5 331
bogdanm 92:4fc01daae5a5 332 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
bogdanm 92:4fc01daae5a5 333 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
bogdanm 92:4fc01daae5a5 334 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
bogdanm 92:4fc01daae5a5 335 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
bogdanm 92:4fc01daae5a5 336 /**
bogdanm 92:4fc01daae5a5 337 * @}
bogdanm 92:4fc01daae5a5 338 */
bogdanm 92:4fc01daae5a5 339
bogdanm 92:4fc01daae5a5 340 /** @defgroup DMA_Memory_burst
bogdanm 92:4fc01daae5a5 341 * @{
bogdanm 92:4fc01daae5a5 342 */
bogdanm 92:4fc01daae5a5 343 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 344 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
bogdanm 92:4fc01daae5a5 345 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
bogdanm 92:4fc01daae5a5 346 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
bogdanm 92:4fc01daae5a5 347
bogdanm 92:4fc01daae5a5 348 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
bogdanm 92:4fc01daae5a5 349 ((BURST) == DMA_MBURST_INC4) || \
bogdanm 92:4fc01daae5a5 350 ((BURST) == DMA_MBURST_INC8) || \
bogdanm 92:4fc01daae5a5 351 ((BURST) == DMA_MBURST_INC16))
bogdanm 92:4fc01daae5a5 352 /**
bogdanm 92:4fc01daae5a5 353 * @}
bogdanm 92:4fc01daae5a5 354 */
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 /** @defgroup DMA_Peripheral_burst
bogdanm 92:4fc01daae5a5 357 * @{
bogdanm 92:4fc01daae5a5 358 */
bogdanm 92:4fc01daae5a5 359 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 360 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
bogdanm 92:4fc01daae5a5 361 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
bogdanm 92:4fc01daae5a5 362 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
bogdanm 92:4fc01daae5a5 363
bogdanm 92:4fc01daae5a5 364 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
bogdanm 92:4fc01daae5a5 365 ((BURST) == DMA_PBURST_INC4) || \
bogdanm 92:4fc01daae5a5 366 ((BURST) == DMA_PBURST_INC8) || \
bogdanm 92:4fc01daae5a5 367 ((BURST) == DMA_PBURST_INC16))
bogdanm 92:4fc01daae5a5 368 /**
bogdanm 92:4fc01daae5a5 369 * @}
bogdanm 92:4fc01daae5a5 370 */
bogdanm 92:4fc01daae5a5 371
bogdanm 92:4fc01daae5a5 372 /** @defgroup DMA_interrupt_enable_definitions
bogdanm 92:4fc01daae5a5 373 * @{
bogdanm 92:4fc01daae5a5 374 */
bogdanm 92:4fc01daae5a5 375 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
bogdanm 92:4fc01daae5a5 376 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
bogdanm 92:4fc01daae5a5 377 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
bogdanm 92:4fc01daae5a5 378 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
bogdanm 92:4fc01daae5a5 379 #define DMA_IT_FE ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 380 /**
bogdanm 92:4fc01daae5a5 381 * @}
bogdanm 92:4fc01daae5a5 382 */
bogdanm 92:4fc01daae5a5 383
bogdanm 92:4fc01daae5a5 384 /** @defgroup DMA_flag_definitions
bogdanm 92:4fc01daae5a5 385 * @{
bogdanm 92:4fc01daae5a5 386 */
bogdanm 92:4fc01daae5a5 387 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
bogdanm 92:4fc01daae5a5 388 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
bogdanm 92:4fc01daae5a5 389 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 390 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 391 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 392 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 393 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 394 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 395 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 396 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 397 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 398 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 399 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 400 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 401 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 402 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 403 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 404 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 405 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 406 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 407 /**
bogdanm 92:4fc01daae5a5 408 * @}
bogdanm 92:4fc01daae5a5 409 */
bogdanm 92:4fc01daae5a5 410
bogdanm 92:4fc01daae5a5 411 /**
bogdanm 92:4fc01daae5a5 412 * @}
bogdanm 92:4fc01daae5a5 413 */
bogdanm 92:4fc01daae5a5 414
bogdanm 92:4fc01daae5a5 415 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 416
bogdanm 92:4fc01daae5a5 417 /** @brief Reset DMA handle state
bogdanm 92:4fc01daae5a5 418 * @param __HANDLE__: specifies the DMA handle.
bogdanm 92:4fc01daae5a5 419 * @retval None
bogdanm 92:4fc01daae5a5 420 */
bogdanm 92:4fc01daae5a5 421 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 /**
bogdanm 92:4fc01daae5a5 424 * @brief Return the current DMA Stream FIFO filled level.
bogdanm 92:4fc01daae5a5 425 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 426 * @retval The FIFO filling state.
bogdanm 92:4fc01daae5a5 427 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
bogdanm 92:4fc01daae5a5 428 * and not empty.
bogdanm 92:4fc01daae5a5 429 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
bogdanm 92:4fc01daae5a5 430 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
bogdanm 92:4fc01daae5a5 431 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
bogdanm 92:4fc01daae5a5 432 * - DMA_FIFOStatus_Empty: when FIFO is empty
bogdanm 92:4fc01daae5a5 433 * - DMA_FIFOStatus_Full: when FIFO is full
bogdanm 92:4fc01daae5a5 434 */
bogdanm 92:4fc01daae5a5 435 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
bogdanm 92:4fc01daae5a5 436
bogdanm 92:4fc01daae5a5 437 /**
bogdanm 92:4fc01daae5a5 438 * @brief Enable the specified DMA Stream.
bogdanm 92:4fc01daae5a5 439 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 440 * @retval None
bogdanm 92:4fc01daae5a5 441 */
bogdanm 92:4fc01daae5a5 442 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
bogdanm 92:4fc01daae5a5 443
bogdanm 92:4fc01daae5a5 444 /**
bogdanm 92:4fc01daae5a5 445 * @brief Disable the specified DMA Stream.
bogdanm 92:4fc01daae5a5 446 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 447 * @retval None
bogdanm 92:4fc01daae5a5 448 */
bogdanm 92:4fc01daae5a5 449 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
bogdanm 92:4fc01daae5a5 450
bogdanm 92:4fc01daae5a5 451 /* Interrupt & Flag management */
bogdanm 92:4fc01daae5a5 452
bogdanm 92:4fc01daae5a5 453 /**
bogdanm 92:4fc01daae5a5 454 * @brief Return the current DMA Stream transfer complete flag.
bogdanm 92:4fc01daae5a5 455 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 456 * @retval The specified transfer complete flag index.
bogdanm 92:4fc01daae5a5 457 */
bogdanm 92:4fc01daae5a5 458 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 92:4fc01daae5a5 459 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 471 DMA_FLAG_TCIF3_7)
bogdanm 92:4fc01daae5a5 472
bogdanm 92:4fc01daae5a5 473 /**
bogdanm 92:4fc01daae5a5 474 * @brief Return the current DMA Stream half transfer complete flag.
bogdanm 92:4fc01daae5a5 475 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 476 * @retval The specified half transfer complete flag index.
bogdanm 92:4fc01daae5a5 477 */
bogdanm 92:4fc01daae5a5 478 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 479 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 491 DMA_FLAG_HTIF3_7)
bogdanm 92:4fc01daae5a5 492
bogdanm 92:4fc01daae5a5 493 /**
bogdanm 92:4fc01daae5a5 494 * @brief Return the current DMA Stream transfer error flag.
bogdanm 92:4fc01daae5a5 495 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 496 * @retval The specified transfer error flag index.
bogdanm 92:4fc01daae5a5 497 */
bogdanm 92:4fc01daae5a5 498 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 499 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 511 DMA_FLAG_TEIF3_7)
bogdanm 92:4fc01daae5a5 512
bogdanm 92:4fc01daae5a5 513 /**
bogdanm 92:4fc01daae5a5 514 * @brief Return the current DMA Stream FIFO error flag.
bogdanm 92:4fc01daae5a5 515 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 516 * @retval The specified FIFO error flag index.
bogdanm 92:4fc01daae5a5 517 */
bogdanm 92:4fc01daae5a5 518 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 519 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 531 DMA_FLAG_FEIF3_7)
bogdanm 92:4fc01daae5a5 532
bogdanm 92:4fc01daae5a5 533 /**
bogdanm 92:4fc01daae5a5 534 * @brief Return the current DMA Stream direct mode error flag.
bogdanm 92:4fc01daae5a5 535 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 536 * @retval The specified direct mode error flag index.
bogdanm 92:4fc01daae5a5 537 */
bogdanm 92:4fc01daae5a5 538 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 539 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 549 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 550 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 551 DMA_FLAG_DMEIF3_7)
bogdanm 92:4fc01daae5a5 552
bogdanm 92:4fc01daae5a5 553 /**
bogdanm 92:4fc01daae5a5 554 * @brief Get the DMA Stream pending flags.
bogdanm 92:4fc01daae5a5 555 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 556 * @param __FLAG__: Get the specified flag.
bogdanm 92:4fc01daae5a5 557 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 558 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 92:4fc01daae5a5 559 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 92:4fc01daae5a5 560 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 92:4fc01daae5a5 561 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 92:4fc01daae5a5 562 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 92:4fc01daae5a5 563 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 92:4fc01daae5a5 564 * @retval The state of FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 565 */
bogdanm 92:4fc01daae5a5 566 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
bogdanm 92:4fc01daae5a5 567 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 568 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 569 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
bogdanm 92:4fc01daae5a5 570
bogdanm 92:4fc01daae5a5 571 /**
bogdanm 92:4fc01daae5a5 572 * @brief Clear the DMA Stream pending flags.
bogdanm 92:4fc01daae5a5 573 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 574 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 575 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 576 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 92:4fc01daae5a5 577 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 92:4fc01daae5a5 578 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 92:4fc01daae5a5 579 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 92:4fc01daae5a5 580 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 92:4fc01daae5a5 581 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 92:4fc01daae5a5 582 * @retval None
bogdanm 92:4fc01daae5a5 583 */
bogdanm 92:4fc01daae5a5 584 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
bogdanm 92:4fc01daae5a5 585 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 586 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 587 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
bogdanm 92:4fc01daae5a5 588
bogdanm 92:4fc01daae5a5 589 /**
bogdanm 92:4fc01daae5a5 590 * @brief Enable the specified DMA Stream interrupts.
bogdanm 92:4fc01daae5a5 591 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 592 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 593 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 594 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 595 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 596 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 597 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 598 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 599 * @retval None
bogdanm 92:4fc01daae5a5 600 */
bogdanm 92:4fc01daae5a5 601 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 602 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 603
bogdanm 92:4fc01daae5a5 604 /**
bogdanm 92:4fc01daae5a5 605 * @brief Disable the specified DMA Stream interrupts.
bogdanm 92:4fc01daae5a5 606 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 607 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 608 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 609 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 610 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 611 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 612 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 613 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 614 * @retval None
bogdanm 92:4fc01daae5a5 615 */
bogdanm 92:4fc01daae5a5 616 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 617 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 618
bogdanm 92:4fc01daae5a5 619 /**
bogdanm 92:4fc01daae5a5 620 * @brief Check whether the specified DMA Stream interrupt has occurred or not.
bogdanm 92:4fc01daae5a5 621 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 622 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 92:4fc01daae5a5 623 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 624 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 625 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 626 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 627 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 628 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 629 * @retval The state of DMA_IT.
bogdanm 92:4fc01daae5a5 630 */
bogdanm 92:4fc01daae5a5 631 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 632 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
bogdanm 92:4fc01daae5a5 633 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 634
bogdanm 92:4fc01daae5a5 635 /**
bogdanm 92:4fc01daae5a5 636 * @brief Writes the number of data units to be transferred on the DMA Stream.
bogdanm 92:4fc01daae5a5 637 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 638 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
bogdanm 92:4fc01daae5a5 639 * Number of data items depends only on the Peripheral data format.
bogdanm 92:4fc01daae5a5 640 *
bogdanm 92:4fc01daae5a5 641 * @note If Peripheral data format is Bytes: number of data units is equal
bogdanm 92:4fc01daae5a5 642 * to total number of bytes to be transferred.
bogdanm 92:4fc01daae5a5 643 *
bogdanm 92:4fc01daae5a5 644 * @note If Peripheral data format is Half-Word: number of data units is
bogdanm 92:4fc01daae5a5 645 * equal to total number of bytes to be transferred / 2.
bogdanm 92:4fc01daae5a5 646 *
bogdanm 92:4fc01daae5a5 647 * @note If Peripheral data format is Word: number of data units is equal
bogdanm 92:4fc01daae5a5 648 * to total number of bytes to be transferred / 4.
bogdanm 92:4fc01daae5a5 649 *
bogdanm 92:4fc01daae5a5 650 * @retval The number of remaining data units in the current DMAy Streamx transfer.
bogdanm 92:4fc01daae5a5 651 */
bogdanm 92:4fc01daae5a5 652 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
bogdanm 92:4fc01daae5a5 653
bogdanm 92:4fc01daae5a5 654 /**
bogdanm 92:4fc01daae5a5 655 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
bogdanm 92:4fc01daae5a5 656 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 657 *
bogdanm 92:4fc01daae5a5 658 * @retval The number of remaining data units in the current DMA Stream transfer.
bogdanm 92:4fc01daae5a5 659 */
bogdanm 92:4fc01daae5a5 660 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
bogdanm 92:4fc01daae5a5 661
bogdanm 92:4fc01daae5a5 662
bogdanm 92:4fc01daae5a5 663 /* Include DMA HAL Extension module */
bogdanm 92:4fc01daae5a5 664 #include "stm32f4xx_hal_dma_ex.h"
bogdanm 92:4fc01daae5a5 665
bogdanm 92:4fc01daae5a5 666 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 667
bogdanm 92:4fc01daae5a5 668 /* Initialization and de-initialization functions *****************************/
bogdanm 92:4fc01daae5a5 669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 671
bogdanm 92:4fc01daae5a5 672 /* IO operation functions *****************************************************/
bogdanm 92:4fc01daae5a5 673 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 92:4fc01daae5a5 674 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 92:4fc01daae5a5 675 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 676 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 677 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 678
bogdanm 92:4fc01daae5a5 679 /* Peripheral State and Error functions ***************************************/
bogdanm 92:4fc01daae5a5 680 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 681 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 682
bogdanm 92:4fc01daae5a5 683 /**
bogdanm 92:4fc01daae5a5 684 * @}
bogdanm 92:4fc01daae5a5 685 */
bogdanm 92:4fc01daae5a5 686
bogdanm 92:4fc01daae5a5 687 /**
bogdanm 92:4fc01daae5a5 688 * @}
bogdanm 92:4fc01daae5a5 689 */
bogdanm 92:4fc01daae5a5 690
bogdanm 92:4fc01daae5a5 691 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 692 }
bogdanm 92:4fc01daae5a5 693 #endif
bogdanm 92:4fc01daae5a5 694
bogdanm 92:4fc01daae5a5 695 #endif /* __STM32F4xx_HAL_DMA_H */
bogdanm 92:4fc01daae5a5 696
bogdanm 92:4fc01daae5a5 697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/