frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_NUCLEO_F103RB/stm32f10x_dma.h@73:1efda918f0ba, 2013-12-09 (annotated)

Committer:
bogdanm
Date:
Mon Dec 09 18:43:03 2013 +0200
Revision:
73:1efda918f0ba
Child:
76:824293ae5e43
Release 73 of the mbed library



Main changes:



- added support for KL46Z and NUCLEO_F103RB

- STM32 USB device support

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 73:1efda918f0ba 1 /**
bogdanm 73:1efda918f0ba 2 ******************************************************************************
bogdanm 73:1efda918f0ba 3 * @file stm32f10x_dma.h
bogdanm 73:1efda918f0ba 4 * @author MCD Application Team
bogdanm 73:1efda918f0ba 5 * @version V3.5.0
bogdanm 73:1efda918f0ba 6 * @date 11-March-2011
bogdanm 73:1efda918f0ba 7 * @brief This file contains all the functions prototypes for the DMA firmware
bogdanm 73:1efda918f0ba 8 * library.
bogdanm 73:1efda918f0ba 9 ******************************************************************************
bogdanm 73:1efda918f0ba 10 * @attention
bogdanm 73:1efda918f0ba 11 *
bogdanm 73:1efda918f0ba 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
bogdanm 73:1efda918f0ba 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
bogdanm 73:1efda918f0ba 14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
bogdanm 73:1efda918f0ba 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
bogdanm 73:1efda918f0ba 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
bogdanm 73:1efda918f0ba 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
bogdanm 73:1efda918f0ba 18 *
bogdanm 73:1efda918f0ba 19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
bogdanm 73:1efda918f0ba 20 ******************************************************************************
bogdanm 73:1efda918f0ba 21 */
bogdanm 73:1efda918f0ba 22
bogdanm 73:1efda918f0ba 23 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 73:1efda918f0ba 24 #ifndef __STM32F10x_DMA_H
bogdanm 73:1efda918f0ba 25 #define __STM32F10x_DMA_H
bogdanm 73:1efda918f0ba 26
bogdanm 73:1efda918f0ba 27 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 28 extern "C" {
bogdanm 73:1efda918f0ba 29 #endif
bogdanm 73:1efda918f0ba 30
bogdanm 73:1efda918f0ba 31 /* Includes ------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 32 #include "stm32f10x.h"
bogdanm 73:1efda918f0ba 33
bogdanm 73:1efda918f0ba 34 /** @addtogroup STM32F10x_StdPeriph_Driver
bogdanm 73:1efda918f0ba 35 * @{
bogdanm 73:1efda918f0ba 36 */
bogdanm 73:1efda918f0ba 37
bogdanm 73:1efda918f0ba 38 /** @addtogroup DMA
bogdanm 73:1efda918f0ba 39 * @{
bogdanm 73:1efda918f0ba 40 */
bogdanm 73:1efda918f0ba 41
bogdanm 73:1efda918f0ba 42 /** @defgroup DMA_Exported_Types
bogdanm 73:1efda918f0ba 43 * @{
bogdanm 73:1efda918f0ba 44 */
bogdanm 73:1efda918f0ba 45
bogdanm 73:1efda918f0ba 46 /**
bogdanm 73:1efda918f0ba 47 * @brief DMA Init structure definition
bogdanm 73:1efda918f0ba 48 */
bogdanm 73:1efda918f0ba 49
bogdanm 73:1efda918f0ba 50 typedef struct
bogdanm 73:1efda918f0ba 51 {
bogdanm 73:1efda918f0ba 52 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
bogdanm 73:1efda918f0ba 53
bogdanm 73:1efda918f0ba 54 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
bogdanm 73:1efda918f0ba 55
bogdanm 73:1efda918f0ba 56 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
bogdanm 73:1efda918f0ba 57 This parameter can be a value of @ref DMA_data_transfer_direction */
bogdanm 73:1efda918f0ba 58
bogdanm 73:1efda918f0ba 59 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
bogdanm 73:1efda918f0ba 60 The data unit is equal to the configuration set in DMA_PeripheralDataSize
bogdanm 73:1efda918f0ba 61 or DMA_MemoryDataSize members depending in the transfer direction. */
bogdanm 73:1efda918f0ba 62
bogdanm 73:1efda918f0ba 63 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
bogdanm 73:1efda918f0ba 64 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
bogdanm 73:1efda918f0ba 65
bogdanm 73:1efda918f0ba 66 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
bogdanm 73:1efda918f0ba 67 This parameter can be a value of @ref DMA_memory_incremented_mode */
bogdanm 73:1efda918f0ba 68
bogdanm 73:1efda918f0ba 69 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
bogdanm 73:1efda918f0ba 70 This parameter can be a value of @ref DMA_peripheral_data_size */
bogdanm 73:1efda918f0ba 71
bogdanm 73:1efda918f0ba 72 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
bogdanm 73:1efda918f0ba 73 This parameter can be a value of @ref DMA_memory_data_size */
bogdanm 73:1efda918f0ba 74
bogdanm 73:1efda918f0ba 75 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 73:1efda918f0ba 76 This parameter can be a value of @ref DMA_circular_normal_mode.
bogdanm 73:1efda918f0ba 77 @note: The circular buffer mode cannot be used if the memory-to-memory
bogdanm 73:1efda918f0ba 78 data transfer is configured on the selected Channel */
bogdanm 73:1efda918f0ba 79
bogdanm 73:1efda918f0ba 80 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 73:1efda918f0ba 81 This parameter can be a value of @ref DMA_priority_level */
bogdanm 73:1efda918f0ba 82
bogdanm 73:1efda918f0ba 83 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
bogdanm 73:1efda918f0ba 84 This parameter can be a value of @ref DMA_memory_to_memory */
bogdanm 73:1efda918f0ba 85 }DMA_InitTypeDef;
bogdanm 73:1efda918f0ba 86
bogdanm 73:1efda918f0ba 87 /**
bogdanm 73:1efda918f0ba 88 * @}
bogdanm 73:1efda918f0ba 89 */
bogdanm 73:1efda918f0ba 90
bogdanm 73:1efda918f0ba 91 /** @defgroup DMA_Exported_Constants
bogdanm 73:1efda918f0ba 92 * @{
bogdanm 73:1efda918f0ba 93 */
bogdanm 73:1efda918f0ba 94
bogdanm 73:1efda918f0ba 95 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
bogdanm 73:1efda918f0ba 96 ((PERIPH) == DMA1_Channel2) || \
bogdanm 73:1efda918f0ba 97 ((PERIPH) == DMA1_Channel3) || \
bogdanm 73:1efda918f0ba 98 ((PERIPH) == DMA1_Channel4) || \
bogdanm 73:1efda918f0ba 99 ((PERIPH) == DMA1_Channel5) || \
bogdanm 73:1efda918f0ba 100 ((PERIPH) == DMA1_Channel6) || \
bogdanm 73:1efda918f0ba 101 ((PERIPH) == DMA1_Channel7) || \
bogdanm 73:1efda918f0ba 102 ((PERIPH) == DMA2_Channel1) || \
bogdanm 73:1efda918f0ba 103 ((PERIPH) == DMA2_Channel2) || \
bogdanm 73:1efda918f0ba 104 ((PERIPH) == DMA2_Channel3) || \
bogdanm 73:1efda918f0ba 105 ((PERIPH) == DMA2_Channel4) || \
bogdanm 73:1efda918f0ba 106 ((PERIPH) == DMA2_Channel5))
bogdanm 73:1efda918f0ba 107
bogdanm 73:1efda918f0ba 108 /** @defgroup DMA_data_transfer_direction
bogdanm 73:1efda918f0ba 109 * @{
bogdanm 73:1efda918f0ba 110 */
bogdanm 73:1efda918f0ba 111
bogdanm 73:1efda918f0ba 112 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 113 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 114 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
bogdanm 73:1efda918f0ba 115 ((DIR) == DMA_DIR_PeripheralSRC))
bogdanm 73:1efda918f0ba 116 /**
bogdanm 73:1efda918f0ba 117 * @}
bogdanm 73:1efda918f0ba 118 */
bogdanm 73:1efda918f0ba 119
bogdanm 73:1efda918f0ba 120 /** @defgroup DMA_peripheral_incremented_mode
bogdanm 73:1efda918f0ba 121 * @{
bogdanm 73:1efda918f0ba 122 */
bogdanm 73:1efda918f0ba 123
bogdanm 73:1efda918f0ba 124 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
bogdanm 73:1efda918f0ba 125 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 126 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
bogdanm 73:1efda918f0ba 127 ((STATE) == DMA_PeripheralInc_Disable))
bogdanm 73:1efda918f0ba 128 /**
bogdanm 73:1efda918f0ba 129 * @}
bogdanm 73:1efda918f0ba 130 */
bogdanm 73:1efda918f0ba 131
bogdanm 73:1efda918f0ba 132 /** @defgroup DMA_memory_incremented_mode
bogdanm 73:1efda918f0ba 133 * @{
bogdanm 73:1efda918f0ba 134 */
bogdanm 73:1efda918f0ba 135
bogdanm 73:1efda918f0ba 136 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
bogdanm 73:1efda918f0ba 137 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 138 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
bogdanm 73:1efda918f0ba 139 ((STATE) == DMA_MemoryInc_Disable))
bogdanm 73:1efda918f0ba 140 /**
bogdanm 73:1efda918f0ba 141 * @}
bogdanm 73:1efda918f0ba 142 */
bogdanm 73:1efda918f0ba 143
bogdanm 73:1efda918f0ba 144 /** @defgroup DMA_peripheral_data_size
bogdanm 73:1efda918f0ba 145 * @{
bogdanm 73:1efda918f0ba 146 */
bogdanm 73:1efda918f0ba 147
bogdanm 73:1efda918f0ba 148 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 149 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
bogdanm 73:1efda918f0ba 150 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
bogdanm 73:1efda918f0ba 151 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
bogdanm 73:1efda918f0ba 152 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
bogdanm 73:1efda918f0ba 153 ((SIZE) == DMA_PeripheralDataSize_Word))
bogdanm 73:1efda918f0ba 154 /**
bogdanm 73:1efda918f0ba 155 * @}
bogdanm 73:1efda918f0ba 156 */
bogdanm 73:1efda918f0ba 157
bogdanm 73:1efda918f0ba 158 /** @defgroup DMA_memory_data_size
bogdanm 73:1efda918f0ba 159 * @{
bogdanm 73:1efda918f0ba 160 */
bogdanm 73:1efda918f0ba 161
bogdanm 73:1efda918f0ba 162 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 163 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
bogdanm 73:1efda918f0ba 164 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
bogdanm 73:1efda918f0ba 165 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
bogdanm 73:1efda918f0ba 166 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
bogdanm 73:1efda918f0ba 167 ((SIZE) == DMA_MemoryDataSize_Word))
bogdanm 73:1efda918f0ba 168 /**
bogdanm 73:1efda918f0ba 169 * @}
bogdanm 73:1efda918f0ba 170 */
bogdanm 73:1efda918f0ba 171
bogdanm 73:1efda918f0ba 172 /** @defgroup DMA_circular_normal_mode
bogdanm 73:1efda918f0ba 173 * @{
bogdanm 73:1efda918f0ba 174 */
bogdanm 73:1efda918f0ba 175
bogdanm 73:1efda918f0ba 176 #define DMA_Mode_Circular ((uint32_t)0x00000020)
bogdanm 73:1efda918f0ba 177 #define DMA_Mode_Normal ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 178 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
bogdanm 73:1efda918f0ba 179 /**
bogdanm 73:1efda918f0ba 180 * @}
bogdanm 73:1efda918f0ba 181 */
bogdanm 73:1efda918f0ba 182
bogdanm 73:1efda918f0ba 183 /** @defgroup DMA_priority_level
bogdanm 73:1efda918f0ba 184 * @{
bogdanm 73:1efda918f0ba 185 */
bogdanm 73:1efda918f0ba 186
bogdanm 73:1efda918f0ba 187 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
bogdanm 73:1efda918f0ba 188 #define DMA_Priority_High ((uint32_t)0x00002000)
bogdanm 73:1efda918f0ba 189 #define DMA_Priority_Medium ((uint32_t)0x00001000)
bogdanm 73:1efda918f0ba 190 #define DMA_Priority_Low ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 191 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
bogdanm 73:1efda918f0ba 192 ((PRIORITY) == DMA_Priority_High) || \
bogdanm 73:1efda918f0ba 193 ((PRIORITY) == DMA_Priority_Medium) || \
bogdanm 73:1efda918f0ba 194 ((PRIORITY) == DMA_Priority_Low))
bogdanm 73:1efda918f0ba 195 /**
bogdanm 73:1efda918f0ba 196 * @}
bogdanm 73:1efda918f0ba 197 */
bogdanm 73:1efda918f0ba 198
bogdanm 73:1efda918f0ba 199 /** @defgroup DMA_memory_to_memory
bogdanm 73:1efda918f0ba 200 * @{
bogdanm 73:1efda918f0ba 201 */
bogdanm 73:1efda918f0ba 202
bogdanm 73:1efda918f0ba 203 #define DMA_M2M_Enable ((uint32_t)0x00004000)
bogdanm 73:1efda918f0ba 204 #define DMA_M2M_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 205 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
bogdanm 73:1efda918f0ba 206
bogdanm 73:1efda918f0ba 207 /**
bogdanm 73:1efda918f0ba 208 * @}
bogdanm 73:1efda918f0ba 209 */
bogdanm 73:1efda918f0ba 210
bogdanm 73:1efda918f0ba 211 /** @defgroup DMA_interrupts_definition
bogdanm 73:1efda918f0ba 212 * @{
bogdanm 73:1efda918f0ba 213 */
bogdanm 73:1efda918f0ba 214
bogdanm 73:1efda918f0ba 215 #define DMA_IT_TC ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 216 #define DMA_IT_HT ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 217 #define DMA_IT_TE ((uint32_t)0x00000008)
bogdanm 73:1efda918f0ba 218 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
bogdanm 73:1efda918f0ba 219
bogdanm 73:1efda918f0ba 220 #define DMA1_IT_GL1 ((uint32_t)0x00000001)
bogdanm 73:1efda918f0ba 221 #define DMA1_IT_TC1 ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 222 #define DMA1_IT_HT1 ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 223 #define DMA1_IT_TE1 ((uint32_t)0x00000008)
bogdanm 73:1efda918f0ba 224 #define DMA1_IT_GL2 ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 225 #define DMA1_IT_TC2 ((uint32_t)0x00000020)
bogdanm 73:1efda918f0ba 226 #define DMA1_IT_HT2 ((uint32_t)0x00000040)
bogdanm 73:1efda918f0ba 227 #define DMA1_IT_TE2 ((uint32_t)0x00000080)
bogdanm 73:1efda918f0ba 228 #define DMA1_IT_GL3 ((uint32_t)0x00000100)
bogdanm 73:1efda918f0ba 229 #define DMA1_IT_TC3 ((uint32_t)0x00000200)
bogdanm 73:1efda918f0ba 230 #define DMA1_IT_HT3 ((uint32_t)0x00000400)
bogdanm 73:1efda918f0ba 231 #define DMA1_IT_TE3 ((uint32_t)0x00000800)
bogdanm 73:1efda918f0ba 232 #define DMA1_IT_GL4 ((uint32_t)0x00001000)
bogdanm 73:1efda918f0ba 233 #define DMA1_IT_TC4 ((uint32_t)0x00002000)
bogdanm 73:1efda918f0ba 234 #define DMA1_IT_HT4 ((uint32_t)0x00004000)
bogdanm 73:1efda918f0ba 235 #define DMA1_IT_TE4 ((uint32_t)0x00008000)
bogdanm 73:1efda918f0ba 236 #define DMA1_IT_GL5 ((uint32_t)0x00010000)
bogdanm 73:1efda918f0ba 237 #define DMA1_IT_TC5 ((uint32_t)0x00020000)
bogdanm 73:1efda918f0ba 238 #define DMA1_IT_HT5 ((uint32_t)0x00040000)
bogdanm 73:1efda918f0ba 239 #define DMA1_IT_TE5 ((uint32_t)0x00080000)
bogdanm 73:1efda918f0ba 240 #define DMA1_IT_GL6 ((uint32_t)0x00100000)
bogdanm 73:1efda918f0ba 241 #define DMA1_IT_TC6 ((uint32_t)0x00200000)
bogdanm 73:1efda918f0ba 242 #define DMA1_IT_HT6 ((uint32_t)0x00400000)
bogdanm 73:1efda918f0ba 243 #define DMA1_IT_TE6 ((uint32_t)0x00800000)
bogdanm 73:1efda918f0ba 244 #define DMA1_IT_GL7 ((uint32_t)0x01000000)
bogdanm 73:1efda918f0ba 245 #define DMA1_IT_TC7 ((uint32_t)0x02000000)
bogdanm 73:1efda918f0ba 246 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
bogdanm 73:1efda918f0ba 247 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
bogdanm 73:1efda918f0ba 248
bogdanm 73:1efda918f0ba 249 #define DMA2_IT_GL1 ((uint32_t)0x10000001)
bogdanm 73:1efda918f0ba 250 #define DMA2_IT_TC1 ((uint32_t)0x10000002)
bogdanm 73:1efda918f0ba 251 #define DMA2_IT_HT1 ((uint32_t)0x10000004)
bogdanm 73:1efda918f0ba 252 #define DMA2_IT_TE1 ((uint32_t)0x10000008)
bogdanm 73:1efda918f0ba 253 #define DMA2_IT_GL2 ((uint32_t)0x10000010)
bogdanm 73:1efda918f0ba 254 #define DMA2_IT_TC2 ((uint32_t)0x10000020)
bogdanm 73:1efda918f0ba 255 #define DMA2_IT_HT2 ((uint32_t)0x10000040)
bogdanm 73:1efda918f0ba 256 #define DMA2_IT_TE2 ((uint32_t)0x10000080)
bogdanm 73:1efda918f0ba 257 #define DMA2_IT_GL3 ((uint32_t)0x10000100)
bogdanm 73:1efda918f0ba 258 #define DMA2_IT_TC3 ((uint32_t)0x10000200)
bogdanm 73:1efda918f0ba 259 #define DMA2_IT_HT3 ((uint32_t)0x10000400)
bogdanm 73:1efda918f0ba 260 #define DMA2_IT_TE3 ((uint32_t)0x10000800)
bogdanm 73:1efda918f0ba 261 #define DMA2_IT_GL4 ((uint32_t)0x10001000)
bogdanm 73:1efda918f0ba 262 #define DMA2_IT_TC4 ((uint32_t)0x10002000)
bogdanm 73:1efda918f0ba 263 #define DMA2_IT_HT4 ((uint32_t)0x10004000)
bogdanm 73:1efda918f0ba 264 #define DMA2_IT_TE4 ((uint32_t)0x10008000)
bogdanm 73:1efda918f0ba 265 #define DMA2_IT_GL5 ((uint32_t)0x10010000)
bogdanm 73:1efda918f0ba 266 #define DMA2_IT_TC5 ((uint32_t)0x10020000)
bogdanm 73:1efda918f0ba 267 #define DMA2_IT_HT5 ((uint32_t)0x10040000)
bogdanm 73:1efda918f0ba 268 #define DMA2_IT_TE5 ((uint32_t)0x10080000)
bogdanm 73:1efda918f0ba 269
bogdanm 73:1efda918f0ba 270 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
bogdanm 73:1efda918f0ba 271
bogdanm 73:1efda918f0ba 272 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
bogdanm 73:1efda918f0ba 273 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
bogdanm 73:1efda918f0ba 274 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
bogdanm 73:1efda918f0ba 275 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
bogdanm 73:1efda918f0ba 276 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
bogdanm 73:1efda918f0ba 277 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
bogdanm 73:1efda918f0ba 278 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
bogdanm 73:1efda918f0ba 279 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
bogdanm 73:1efda918f0ba 280 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
bogdanm 73:1efda918f0ba 281 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
bogdanm 73:1efda918f0ba 282 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
bogdanm 73:1efda918f0ba 283 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
bogdanm 73:1efda918f0ba 284 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
bogdanm 73:1efda918f0ba 285 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
bogdanm 73:1efda918f0ba 286 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
bogdanm 73:1efda918f0ba 287 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
bogdanm 73:1efda918f0ba 288 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
bogdanm 73:1efda918f0ba 289 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
bogdanm 73:1efda918f0ba 290 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
bogdanm 73:1efda918f0ba 291 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
bogdanm 73:1efda918f0ba 292 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
bogdanm 73:1efda918f0ba 293 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
bogdanm 73:1efda918f0ba 294 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
bogdanm 73:1efda918f0ba 295 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
bogdanm 73:1efda918f0ba 296
bogdanm 73:1efda918f0ba 297 /**
bogdanm 73:1efda918f0ba 298 * @}
bogdanm 73:1efda918f0ba 299 */
bogdanm 73:1efda918f0ba 300
bogdanm 73:1efda918f0ba 301 /** @defgroup DMA_flags_definition
bogdanm 73:1efda918f0ba 302 * @{
bogdanm 73:1efda918f0ba 303 */
bogdanm 73:1efda918f0ba 304 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 73:1efda918f0ba 305 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 306 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 307 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 73:1efda918f0ba 308 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 309 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 73:1efda918f0ba 310 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 73:1efda918f0ba 311 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 73:1efda918f0ba 312 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 73:1efda918f0ba 313 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 73:1efda918f0ba 314 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 73:1efda918f0ba 315 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 73:1efda918f0ba 316 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 73:1efda918f0ba 317 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 73:1efda918f0ba 318 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 73:1efda918f0ba 319 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 73:1efda918f0ba 320 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 73:1efda918f0ba 321 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 73:1efda918f0ba 322 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 73:1efda918f0ba 323 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 73:1efda918f0ba 324 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 73:1efda918f0ba 325 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 73:1efda918f0ba 326 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 73:1efda918f0ba 327 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 73:1efda918f0ba 328 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 73:1efda918f0ba 329 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 73:1efda918f0ba 330 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 73:1efda918f0ba 331 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 73:1efda918f0ba 332
bogdanm 73:1efda918f0ba 333 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
bogdanm 73:1efda918f0ba 334 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
bogdanm 73:1efda918f0ba 335 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
bogdanm 73:1efda918f0ba 336 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
bogdanm 73:1efda918f0ba 337 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
bogdanm 73:1efda918f0ba 338 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
bogdanm 73:1efda918f0ba 339 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
bogdanm 73:1efda918f0ba 340 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
bogdanm 73:1efda918f0ba 341 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
bogdanm 73:1efda918f0ba 342 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
bogdanm 73:1efda918f0ba 343 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
bogdanm 73:1efda918f0ba 344 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
bogdanm 73:1efda918f0ba 345 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
bogdanm 73:1efda918f0ba 346 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
bogdanm 73:1efda918f0ba 347 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
bogdanm 73:1efda918f0ba 348 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
bogdanm 73:1efda918f0ba 349 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
bogdanm 73:1efda918f0ba 350 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
bogdanm 73:1efda918f0ba 351 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
bogdanm 73:1efda918f0ba 352 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
bogdanm 73:1efda918f0ba 353
bogdanm 73:1efda918f0ba 354 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
bogdanm 73:1efda918f0ba 355
bogdanm 73:1efda918f0ba 356 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
bogdanm 73:1efda918f0ba 357 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
bogdanm 73:1efda918f0ba 358 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
bogdanm 73:1efda918f0ba 359 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
bogdanm 73:1efda918f0ba 360 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
bogdanm 73:1efda918f0ba 361 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
bogdanm 73:1efda918f0ba 362 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
bogdanm 73:1efda918f0ba 363 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
bogdanm 73:1efda918f0ba 364 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
bogdanm 73:1efda918f0ba 365 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
bogdanm 73:1efda918f0ba 366 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
bogdanm 73:1efda918f0ba 367 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
bogdanm 73:1efda918f0ba 368 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
bogdanm 73:1efda918f0ba 369 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
bogdanm 73:1efda918f0ba 370 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
bogdanm 73:1efda918f0ba 371 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
bogdanm 73:1efda918f0ba 372 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
bogdanm 73:1efda918f0ba 373 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
bogdanm 73:1efda918f0ba 374 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
bogdanm 73:1efda918f0ba 375 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
bogdanm 73:1efda918f0ba 376 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
bogdanm 73:1efda918f0ba 377 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
bogdanm 73:1efda918f0ba 378 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
bogdanm 73:1efda918f0ba 379 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
bogdanm 73:1efda918f0ba 380 /**
bogdanm 73:1efda918f0ba 381 * @}
bogdanm 73:1efda918f0ba 382 */
bogdanm 73:1efda918f0ba 383
bogdanm 73:1efda918f0ba 384 /** @defgroup DMA_Buffer_Size
bogdanm 73:1efda918f0ba 385 * @{
bogdanm 73:1efda918f0ba 386 */
bogdanm 73:1efda918f0ba 387
bogdanm 73:1efda918f0ba 388 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 73:1efda918f0ba 389
bogdanm 73:1efda918f0ba 390 /**
bogdanm 73:1efda918f0ba 391 * @}
bogdanm 73:1efda918f0ba 392 */
bogdanm 73:1efda918f0ba 393
bogdanm 73:1efda918f0ba 394 /**
bogdanm 73:1efda918f0ba 395 * @}
bogdanm 73:1efda918f0ba 396 */
bogdanm 73:1efda918f0ba 397
bogdanm 73:1efda918f0ba 398 /** @defgroup DMA_Exported_Macros
bogdanm 73:1efda918f0ba 399 * @{
bogdanm 73:1efda918f0ba 400 */
bogdanm 73:1efda918f0ba 401
bogdanm 73:1efda918f0ba 402 /**
bogdanm 73:1efda918f0ba 403 * @}
bogdanm 73:1efda918f0ba 404 */
bogdanm 73:1efda918f0ba 405
bogdanm 73:1efda918f0ba 406 /** @defgroup DMA_Exported_Functions
bogdanm 73:1efda918f0ba 407 * @{
bogdanm 73:1efda918f0ba 408 */
bogdanm 73:1efda918f0ba 409
bogdanm 73:1efda918f0ba 410 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
bogdanm 73:1efda918f0ba 411 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
bogdanm 73:1efda918f0ba 412 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
bogdanm 73:1efda918f0ba 413 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
bogdanm 73:1efda918f0ba 414 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
bogdanm 73:1efda918f0ba 415 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
bogdanm 73:1efda918f0ba 416 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
bogdanm 73:1efda918f0ba 417 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
bogdanm 73:1efda918f0ba 418 void DMA_ClearFlag(uint32_t DMAy_FLAG);
bogdanm 73:1efda918f0ba 419 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
bogdanm 73:1efda918f0ba 420 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
bogdanm 73:1efda918f0ba 421
bogdanm 73:1efda918f0ba 422 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 423 }
bogdanm 73:1efda918f0ba 424 #endif
bogdanm 73:1efda918f0ba 425
bogdanm 73:1efda918f0ba 426 #endif /*__STM32F10x_DMA_H */
bogdanm 73:1efda918f0ba 427 /**
bogdanm 73:1efda918f0ba 428 * @}
bogdanm 73:1efda918f0ba 429 */
bogdanm 73:1efda918f0ba 430
bogdanm 73:1efda918f0ba 431 /**
bogdanm 73:1efda918f0ba 432 * @}
bogdanm 73:1efda918f0ba 433 */
bogdanm 73:1efda918f0ba 434
bogdanm 73:1efda918f0ba 435 /**
bogdanm 73:1efda918f0ba 436 * @}
bogdanm 73:1efda918f0ba 437 */
bogdanm 73:1efda918f0ba 438
bogdanm 73:1efda918f0ba 439 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/