frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc_ex.h@86:04dd9b1680ae, 2014-07-02 (annotated)

Committer:
bogdanm
Date:
Wed Jul 02 13:22:23 2014 +0100
Revision:
86:04dd9b1680ae
Release 86 of the mbed library



Main changes:





- bug fixes in various backends

- mbed "error" replaced by assert logic (mbed_assert)

- new ST Nucleo targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f4xx_hal_rcc_ex.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.1.0
bogdanm 86:04dd9b1680ae 6 * @date 19-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of RCC HAL Extension module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F4xx_HAL_RCC_EX_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F4xx_HAL_RCC_EX_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f4xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup RCCEx
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 58 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 59 /**
bogdanm 86:04dd9b1680ae 60 * @brief PLLI2S Clock structure definition
bogdanm 86:04dd9b1680ae 61 */
bogdanm 86:04dd9b1680ae 62 typedef struct
bogdanm 86:04dd9b1680ae 63 {
bogdanm 86:04dd9b1680ae 64 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 86:04dd9b1680ae 65 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 86:04dd9b1680ae 66 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 86:04dd9b1680ae 67
bogdanm 86:04dd9b1680ae 68 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm 86:04dd9b1680ae 69 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 86:04dd9b1680ae 70 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 86:04dd9b1680ae 71
bogdanm 86:04dd9b1680ae 72 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm 86:04dd9b1680ae 73 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 86:04dd9b1680ae 74 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm 86:04dd9b1680ae 75 }RCC_PLLI2SInitTypeDef;
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 /**
bogdanm 86:04dd9b1680ae 78 * @brief PLLSAI Clock structure definition
bogdanm 86:04dd9b1680ae 79 */
bogdanm 86:04dd9b1680ae 80 typedef struct
bogdanm 86:04dd9b1680ae 81 {
bogdanm 86:04dd9b1680ae 82 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 86:04dd9b1680ae 83 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 86:04dd9b1680ae 84 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm 86:04dd9b1680ae 85
bogdanm 86:04dd9b1680ae 86 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm 86:04dd9b1680ae 87 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 86:04dd9b1680ae 88 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm 86:04dd9b1680ae 89
bogdanm 86:04dd9b1680ae 90 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm 86:04dd9b1680ae 91 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 86:04dd9b1680ae 92 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
bogdanm 86:04dd9b1680ae 93
bogdanm 86:04dd9b1680ae 94 }RCC_PLLSAIInitTypeDef;
bogdanm 86:04dd9b1680ae 95 /**
bogdanm 86:04dd9b1680ae 96 * @brief RCC extended clocks structure definition
bogdanm 86:04dd9b1680ae 97 */
bogdanm 86:04dd9b1680ae 98 typedef struct
bogdanm 86:04dd9b1680ae 99 {
bogdanm 86:04dd9b1680ae 100 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 101 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 102
bogdanm 86:04dd9b1680ae 103 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm 86:04dd9b1680ae 104 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 86:04dd9b1680ae 105
bogdanm 86:04dd9b1680ae 106 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
bogdanm 86:04dd9b1680ae 107 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
bogdanm 86:04dd9b1680ae 108
bogdanm 86:04dd9b1680ae 109 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm 86:04dd9b1680ae 110 This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm 86:04dd9b1680ae 111 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm 86:04dd9b1680ae 112
bogdanm 86:04dd9b1680ae 113 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm 86:04dd9b1680ae 114 This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm 86:04dd9b1680ae 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm 86:04dd9b1680ae 116
bogdanm 86:04dd9b1680ae 117 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
bogdanm 86:04dd9b1680ae 118 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
bogdanm 86:04dd9b1680ae 119
bogdanm 86:04dd9b1680ae 120 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm 86:04dd9b1680ae 121 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 122
bogdanm 86:04dd9b1680ae 123 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
bogdanm 86:04dd9b1680ae 124 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
bogdanm 86:04dd9b1680ae 125
bogdanm 86:04dd9b1680ae 126 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 127 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 128
bogdanm 86:04dd9b1680ae 129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
bogdanm 86:04dd9b1680ae 130 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
bogdanm 86:04dd9b1680ae 131 /**
bogdanm 86:04dd9b1680ae 132 * @brief PLLI2S Clock structure definition
bogdanm 86:04dd9b1680ae 133 */
bogdanm 86:04dd9b1680ae 134 typedef struct
bogdanm 86:04dd9b1680ae 135 {
bogdanm 86:04dd9b1680ae 136 #if defined(STM32F411xE)
bogdanm 86:04dd9b1680ae 137 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
bogdanm 86:04dd9b1680ae 138 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
bogdanm 86:04dd9b1680ae 139 #endif /* STM32F411xE */
bogdanm 86:04dd9b1680ae 140
bogdanm 86:04dd9b1680ae 141 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 86:04dd9b1680ae 142 This parameter must be a number between Min_Data = 192 and Max_Data = 432
bogdanm 86:04dd9b1680ae 143 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 86:04dd9b1680ae 144
bogdanm 86:04dd9b1680ae 145 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm 86:04dd9b1680ae 146 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 86:04dd9b1680ae 147 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 86:04dd9b1680ae 148
bogdanm 86:04dd9b1680ae 149 }RCC_PLLI2SInitTypeDef;
bogdanm 86:04dd9b1680ae 150
bogdanm 86:04dd9b1680ae 151
bogdanm 86:04dd9b1680ae 152 /**
bogdanm 86:04dd9b1680ae 153 * @brief RCC extended clocks structure definition
bogdanm 86:04dd9b1680ae 154 */
bogdanm 86:04dd9b1680ae 155 typedef struct
bogdanm 86:04dd9b1680ae 156 {
bogdanm 86:04dd9b1680ae 157 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 158 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 159
bogdanm 86:04dd9b1680ae 160 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm 86:04dd9b1680ae 161 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 86:04dd9b1680ae 162
bogdanm 86:04dd9b1680ae 163 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm 86:04dd9b1680ae 164 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 165
bogdanm 86:04dd9b1680ae 166 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 167 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
bogdanm 86:04dd9b1680ae 168 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 169 /** @defgroup RCCEx_Exported_Constants
bogdanm 86:04dd9b1680ae 170 * @{
bogdanm 86:04dd9b1680ae 171 */
bogdanm 86:04dd9b1680ae 172
bogdanm 86:04dd9b1680ae 173 /** @defgroup RCCEx_Periph_Clock_Selection
bogdanm 86:04dd9b1680ae 174 * @{
bogdanm 86:04dd9b1680ae 175 */
bogdanm 86:04dd9b1680ae 176 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 177 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 178 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 179 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 180 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 181 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 182 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 183 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
bogdanm 86:04dd9b1680ae 184 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 185
bogdanm 86:04dd9b1680ae 186 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
bogdanm 86:04dd9b1680ae 187 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
bogdanm 86:04dd9b1680ae 188 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 189 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 190 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
bogdanm 86:04dd9b1680ae 191 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
bogdanm 86:04dd9b1680ae 192
bogdanm 86:04dd9b1680ae 193 /**
bogdanm 86:04dd9b1680ae 194 * @}
bogdanm 86:04dd9b1680ae 195 */
bogdanm 86:04dd9b1680ae 196
bogdanm 86:04dd9b1680ae 197 /** @defgroup RCCEx_BitAddress_AliasRegion
bogdanm 86:04dd9b1680ae 198 * @brief RCC registers bit address in the alias region
bogdanm 86:04dd9b1680ae 199 * @{
bogdanm 86:04dd9b1680ae 200 */
bogdanm 86:04dd9b1680ae 201 /* --- CR Register ---*/
bogdanm 86:04dd9b1680ae 202 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 203 /* Alias word address of PLLSAION bit */
bogdanm 86:04dd9b1680ae 204 #define PLLSAION_BitNumber 0x1C
bogdanm 86:04dd9b1680ae 205 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
bogdanm 86:04dd9b1680ae 206
bogdanm 86:04dd9b1680ae 207 /* --- DCKCFGR Register ---*/
bogdanm 86:04dd9b1680ae 208 /* Alias word address of TIMPRE bit */
bogdanm 86:04dd9b1680ae 209 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
bogdanm 86:04dd9b1680ae 210 #define TIMPRE_BitNumber 0x18
bogdanm 86:04dd9b1680ae 211 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
bogdanm 86:04dd9b1680ae 212 /**
bogdanm 86:04dd9b1680ae 213 * @}
bogdanm 86:04dd9b1680ae 214 */
bogdanm 86:04dd9b1680ae 215
bogdanm 86:04dd9b1680ae 216 /** @defgroup RCCEx_PLLI2S_Clock_Source
bogdanm 86:04dd9b1680ae 217 * @{
bogdanm 86:04dd9b1680ae 218 */
bogdanm 86:04dd9b1680ae 219 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm 86:04dd9b1680ae 220 /**
bogdanm 86:04dd9b1680ae 221 * @}
bogdanm 86:04dd9b1680ae 222 */
bogdanm 86:04dd9b1680ae 223
bogdanm 86:04dd9b1680ae 224 /** @defgroup RCCEx_PLLSAI_Clock_Source
bogdanm 86:04dd9b1680ae 225 * @{
bogdanm 86:04dd9b1680ae 226 */
bogdanm 86:04dd9b1680ae 227 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm 86:04dd9b1680ae 228 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm 86:04dd9b1680ae 229 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm 86:04dd9b1680ae 230 /**
bogdanm 86:04dd9b1680ae 231 * @}
bogdanm 86:04dd9b1680ae 232 */
bogdanm 86:04dd9b1680ae 233
bogdanm 86:04dd9b1680ae 234 /** @defgroup RCCEx_PLLSAI_DIVQ
bogdanm 86:04dd9b1680ae 235 * @{
bogdanm 86:04dd9b1680ae 236 */
bogdanm 86:04dd9b1680ae 237 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm 86:04dd9b1680ae 238 /**
bogdanm 86:04dd9b1680ae 239 * @}
bogdanm 86:04dd9b1680ae 240 */
bogdanm 86:04dd9b1680ae 241
bogdanm 86:04dd9b1680ae 242 /** @defgroup RCCEx_PLLI2S_DIVQ
bogdanm 86:04dd9b1680ae 243 * @{
bogdanm 86:04dd9b1680ae 244 */
bogdanm 86:04dd9b1680ae 245 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm 86:04dd9b1680ae 246
bogdanm 86:04dd9b1680ae 247 /**
bogdanm 86:04dd9b1680ae 248 * @}
bogdanm 86:04dd9b1680ae 249 */
bogdanm 86:04dd9b1680ae 250
bogdanm 86:04dd9b1680ae 251 /** @defgroup RCCEx_PLLSAI_DIVR
bogdanm 86:04dd9b1680ae 252 * @{
bogdanm 86:04dd9b1680ae 253 */
bogdanm 86:04dd9b1680ae 254 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 255 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 256 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 257 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
bogdanm 86:04dd9b1680ae 258 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
bogdanm 86:04dd9b1680ae 259 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
bogdanm 86:04dd9b1680ae 260 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
bogdanm 86:04dd9b1680ae 261 ((VALUE) == RCC_PLLSAIDIVR_16))
bogdanm 86:04dd9b1680ae 262
bogdanm 86:04dd9b1680ae 263 /**
bogdanm 86:04dd9b1680ae 264 * @}
bogdanm 86:04dd9b1680ae 265 */
bogdanm 86:04dd9b1680ae 266
bogdanm 86:04dd9b1680ae 267 /** @defgroup RCCEx_SAI_BlockA_Clock_Source
bogdanm 86:04dd9b1680ae 268 * @{
bogdanm 86:04dd9b1680ae 269 */
bogdanm 86:04dd9b1680ae 270 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 271 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 272 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 273 /**
bogdanm 86:04dd9b1680ae 274 * @}
bogdanm 86:04dd9b1680ae 275 */
bogdanm 86:04dd9b1680ae 276
bogdanm 86:04dd9b1680ae 277 /** @defgroup RCCEx_SAI_BlockB_Clock_Source
bogdanm 86:04dd9b1680ae 278 * @{
bogdanm 86:04dd9b1680ae 279 */
bogdanm 86:04dd9b1680ae 280 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 281 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 282 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 283 /**
bogdanm 86:04dd9b1680ae 284 * @}
bogdanm 86:04dd9b1680ae 285 */
bogdanm 86:04dd9b1680ae 286
bogdanm 86:04dd9b1680ae 287 /** @defgroup RCCEx_TIM_PRescaler_Selection
bogdanm 86:04dd9b1680ae 288 * @{
bogdanm 86:04dd9b1680ae 289 */
bogdanm 86:04dd9b1680ae 290 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
bogdanm 86:04dd9b1680ae 291 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
bogdanm 86:04dd9b1680ae 292 /**
bogdanm 86:04dd9b1680ae 293 * @}
bogdanm 86:04dd9b1680ae 294 */
bogdanm 86:04dd9b1680ae 295 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 296
bogdanm 86:04dd9b1680ae 297 #if defined(STM32F411xE)
bogdanm 86:04dd9b1680ae 298 /** @defgroup RCCEx_PLLI2S_PLLI2SM
bogdanm 86:04dd9b1680ae 299 * @{
bogdanm 86:04dd9b1680ae 300 */
bogdanm 86:04dd9b1680ae 301 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
bogdanm 86:04dd9b1680ae 302 /**
bogdanm 86:04dd9b1680ae 303 * @}
bogdanm 86:04dd9b1680ae 304 */
bogdanm 86:04dd9b1680ae 305
bogdanm 86:04dd9b1680ae 306 /** @defgroup RCCEx_LSE_Dual_Mode_Selection
bogdanm 86:04dd9b1680ae 307 * @{
bogdanm 86:04dd9b1680ae 308 */
bogdanm 86:04dd9b1680ae 309 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
bogdanm 86:04dd9b1680ae 310 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
bogdanm 86:04dd9b1680ae 311 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
bogdanm 86:04dd9b1680ae 312 ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
bogdanm 86:04dd9b1680ae 313 /**
bogdanm 86:04dd9b1680ae 314 * @}
bogdanm 86:04dd9b1680ae 315 */
bogdanm 86:04dd9b1680ae 316
bogdanm 86:04dd9b1680ae 317 #endif /* STM32F411xE */
bogdanm 86:04dd9b1680ae 318 /**
bogdanm 86:04dd9b1680ae 319 * @}
bogdanm 86:04dd9b1680ae 320 */
bogdanm 86:04dd9b1680ae 321
bogdanm 86:04dd9b1680ae 322 /* Exported macro ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 323
bogdanm 86:04dd9b1680ae 324 /*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/
bogdanm 86:04dd9b1680ae 325 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 326 /** @brief Enables or disables the AHB1 peripheral clock.
bogdanm 86:04dd9b1680ae 327 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 328 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 329 * using it.
bogdanm 86:04dd9b1680ae 330 */
bogdanm 86:04dd9b1680ae 331 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
bogdanm 86:04dd9b1680ae 332 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
bogdanm 86:04dd9b1680ae 333 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
bogdanm 86:04dd9b1680ae 334 #define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
bogdanm 86:04dd9b1680ae 335 #define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
bogdanm 86:04dd9b1680ae 336 #define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
bogdanm 86:04dd9b1680ae 337 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
bogdanm 86:04dd9b1680ae 338 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
bogdanm 86:04dd9b1680ae 339 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
bogdanm 86:04dd9b1680ae 340 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
bogdanm 86:04dd9b1680ae 341 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
bogdanm 86:04dd9b1680ae 342 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
bogdanm 86:04dd9b1680ae 343
bogdanm 86:04dd9b1680ae 344 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm 86:04dd9b1680ae 345 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm 86:04dd9b1680ae 346 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
bogdanm 86:04dd9b1680ae 347 #define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
bogdanm 86:04dd9b1680ae 348 #define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
bogdanm 86:04dd9b1680ae 349 #define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
bogdanm 86:04dd9b1680ae 350 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
bogdanm 86:04dd9b1680ae 351 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
bogdanm 86:04dd9b1680ae 352 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
bogdanm 86:04dd9b1680ae 353 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
bogdanm 86:04dd9b1680ae 354 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm 86:04dd9b1680ae 355 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm 86:04dd9b1680ae 356
bogdanm 86:04dd9b1680ae 357 /**
bogdanm 86:04dd9b1680ae 358 * @brief Enable ETHERNET clock.
bogdanm 86:04dd9b1680ae 359 */
bogdanm 86:04dd9b1680ae 360 #define __ETH_CLK_ENABLE() do { \
bogdanm 86:04dd9b1680ae 361 __ETHMAC_CLK_ENABLE(); \
bogdanm 86:04dd9b1680ae 362 __ETHMACTX_CLK_ENABLE(); \
bogdanm 86:04dd9b1680ae 363 __ETHMACRX_CLK_ENABLE(); \
bogdanm 86:04dd9b1680ae 364 } while(0)
bogdanm 86:04dd9b1680ae 365 /**
bogdanm 86:04dd9b1680ae 366 * @brief Disable ETHERNET clock.
bogdanm 86:04dd9b1680ae 367 */
bogdanm 86:04dd9b1680ae 368 #define __ETH_CLK_DISABLE() do { \
bogdanm 86:04dd9b1680ae 369 __ETHMACTX_CLK_DISABLE(); \
bogdanm 86:04dd9b1680ae 370 __ETHMACRX_CLK_DISABLE(); \
bogdanm 86:04dd9b1680ae 371 __ETHMAC_CLK_DISABLE(); \
bogdanm 86:04dd9b1680ae 372 } while(0)
bogdanm 86:04dd9b1680ae 373
bogdanm 86:04dd9b1680ae 374 /** @brief Enable or disable the AHB2 peripheral clock.
bogdanm 86:04dd9b1680ae 375 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 376 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 377 * using it.
bogdanm 86:04dd9b1680ae 378 */
bogdanm 86:04dd9b1680ae 379
bogdanm 86:04dd9b1680ae 380 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
bogdanm 86:04dd9b1680ae 381 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm 86:04dd9b1680ae 382
bogdanm 86:04dd9b1680ae 383 #if defined(STM32F437xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 384 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
bogdanm 86:04dd9b1680ae 385 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
bogdanm 86:04dd9b1680ae 386
bogdanm 86:04dd9b1680ae 387 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
bogdanm 86:04dd9b1680ae 388 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm 86:04dd9b1680ae 389 #endif /* STM32F437xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 390
bogdanm 86:04dd9b1680ae 391 /** @brief Enables or disables the AHB3 peripheral clock.
bogdanm 86:04dd9b1680ae 392 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 393 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 394 * using it.
bogdanm 86:04dd9b1680ae 395 */
bogdanm 86:04dd9b1680ae 396 #define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
bogdanm 86:04dd9b1680ae 397 #define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
bogdanm 86:04dd9b1680ae 398
bogdanm 86:04dd9b1680ae 399 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 86:04dd9b1680ae 400 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 401 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 402 * using it.
bogdanm 86:04dd9b1680ae 403 */
bogdanm 86:04dd9b1680ae 404 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
bogdanm 86:04dd9b1680ae 405 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
bogdanm 86:04dd9b1680ae 406 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
bogdanm 86:04dd9b1680ae 407 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
bogdanm 86:04dd9b1680ae 408 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
bogdanm 86:04dd9b1680ae 409 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
bogdanm 86:04dd9b1680ae 410 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
bogdanm 86:04dd9b1680ae 411 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
bogdanm 86:04dd9b1680ae 412 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
bogdanm 86:04dd9b1680ae 413 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
bogdanm 86:04dd9b1680ae 414 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
bogdanm 86:04dd9b1680ae 415 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
bogdanm 86:04dd9b1680ae 416 #define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
bogdanm 86:04dd9b1680ae 417 #define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
bogdanm 86:04dd9b1680ae 418
bogdanm 86:04dd9b1680ae 419 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm 86:04dd9b1680ae 420 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm 86:04dd9b1680ae 421 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm 86:04dd9b1680ae 422 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm 86:04dd9b1680ae 423 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm 86:04dd9b1680ae 424 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm 86:04dd9b1680ae 425 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm 86:04dd9b1680ae 426 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm 86:04dd9b1680ae 427 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm 86:04dd9b1680ae 428 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm 86:04dd9b1680ae 429 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm 86:04dd9b1680ae 430 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm 86:04dd9b1680ae 431 #define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
bogdanm 86:04dd9b1680ae 432 #define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
bogdanm 86:04dd9b1680ae 433
bogdanm 86:04dd9b1680ae 434 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 86:04dd9b1680ae 435 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 436 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 437 * using it.
bogdanm 86:04dd9b1680ae 438 */
bogdanm 86:04dd9b1680ae 439 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
bogdanm 86:04dd9b1680ae 440 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
bogdanm 86:04dd9b1680ae 441 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
bogdanm 86:04dd9b1680ae 442 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
bogdanm 86:04dd9b1680ae 443 #define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
bogdanm 86:04dd9b1680ae 444 #define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
bogdanm 86:04dd9b1680ae 445
bogdanm 86:04dd9b1680ae 446 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm 86:04dd9b1680ae 447 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm 86:04dd9b1680ae 448 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
bogdanm 86:04dd9b1680ae 449 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
bogdanm 86:04dd9b1680ae 450 #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
bogdanm 86:04dd9b1680ae 451 #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
bogdanm 86:04dd9b1680ae 452
bogdanm 86:04dd9b1680ae 453 #if defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 454 #define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
bogdanm 86:04dd9b1680ae 455
bogdanm 86:04dd9b1680ae 456 #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
bogdanm 86:04dd9b1680ae 457 #endif /* STM32F429xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 458
bogdanm 86:04dd9b1680ae 459 /** @brief Force or release AHB1 peripheral reset.
bogdanm 86:04dd9b1680ae 460 */
bogdanm 86:04dd9b1680ae 461 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
bogdanm 86:04dd9b1680ae 462 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
bogdanm 86:04dd9b1680ae 463 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
bogdanm 86:04dd9b1680ae 464 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
bogdanm 86:04dd9b1680ae 465 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
bogdanm 86:04dd9b1680ae 466 #define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
bogdanm 86:04dd9b1680ae 467 #define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
bogdanm 86:04dd9b1680ae 468 #define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
bogdanm 86:04dd9b1680ae 469
bogdanm 86:04dd9b1680ae 470 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm 86:04dd9b1680ae 471 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm 86:04dd9b1680ae 472 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm 86:04dd9b1680ae 473 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
bogdanm 86:04dd9b1680ae 474 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm 86:04dd9b1680ae 475 #define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
bogdanm 86:04dd9b1680ae 476 #define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
bogdanm 86:04dd9b1680ae 477 #define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
bogdanm 86:04dd9b1680ae 478
bogdanm 86:04dd9b1680ae 479 /** @brief Force or release AHB2 peripheral reset.
bogdanm 86:04dd9b1680ae 480 */
bogdanm 86:04dd9b1680ae 481 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
bogdanm 86:04dd9b1680ae 482 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm 86:04dd9b1680ae 483
bogdanm 86:04dd9b1680ae 484 #if defined(STM32F437xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 485 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
bogdanm 86:04dd9b1680ae 486 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
bogdanm 86:04dd9b1680ae 487
bogdanm 86:04dd9b1680ae 488 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
bogdanm 86:04dd9b1680ae 489 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm 86:04dd9b1680ae 490 #endif /* STM32F437xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 491
bogdanm 86:04dd9b1680ae 492 /** @brief Force or release AHB3 peripheral reset
bogdanm 86:04dd9b1680ae 493 */
bogdanm 86:04dd9b1680ae 494 #define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
bogdanm 86:04dd9b1680ae 495 #define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
bogdanm 86:04dd9b1680ae 496
bogdanm 86:04dd9b1680ae 497 /** @brief Force or release APB1 peripheral reset.
bogdanm 86:04dd9b1680ae 498 */
bogdanm 86:04dd9b1680ae 499 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
bogdanm 86:04dd9b1680ae 500 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
bogdanm 86:04dd9b1680ae 501 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
bogdanm 86:04dd9b1680ae 502 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
bogdanm 86:04dd9b1680ae 503 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
bogdanm 86:04dd9b1680ae 504 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
bogdanm 86:04dd9b1680ae 505 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
bogdanm 86:04dd9b1680ae 506 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
bogdanm 86:04dd9b1680ae 507 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
bogdanm 86:04dd9b1680ae 508 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
bogdanm 86:04dd9b1680ae 509 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
bogdanm 86:04dd9b1680ae 510 #define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
bogdanm 86:04dd9b1680ae 511 #define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
bogdanm 86:04dd9b1680ae 512
bogdanm 86:04dd9b1680ae 513 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm 86:04dd9b1680ae 514 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm 86:04dd9b1680ae 515 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm 86:04dd9b1680ae 516 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm 86:04dd9b1680ae 517 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm 86:04dd9b1680ae 518 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm 86:04dd9b1680ae 519 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm 86:04dd9b1680ae 520 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm 86:04dd9b1680ae 521 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm 86:04dd9b1680ae 522 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm 86:04dd9b1680ae 523 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm 86:04dd9b1680ae 524 #define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
bogdanm 86:04dd9b1680ae 525 #define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
bogdanm 86:04dd9b1680ae 526
bogdanm 86:04dd9b1680ae 527 /** @brief Force or release APB2 peripheral reset.
bogdanm 86:04dd9b1680ae 528 */
bogdanm 86:04dd9b1680ae 529 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
bogdanm 86:04dd9b1680ae 530 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
bogdanm 86:04dd9b1680ae 531 #define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
bogdanm 86:04dd9b1680ae 532 #define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
bogdanm 86:04dd9b1680ae 533
bogdanm 86:04dd9b1680ae 534 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm 86:04dd9b1680ae 535 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
bogdanm 86:04dd9b1680ae 536 #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
bogdanm 86:04dd9b1680ae 537 #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
bogdanm 86:04dd9b1680ae 538
bogdanm 86:04dd9b1680ae 539 #if defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 540 #define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
bogdanm 86:04dd9b1680ae 541 #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
bogdanm 86:04dd9b1680ae 542 #endif /* STM32F429xx|| STM32F439xx */
bogdanm 86:04dd9b1680ae 543
bogdanm 86:04dd9b1680ae 544 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 545 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 546 * power consumption.
bogdanm 86:04dd9b1680ae 547 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 548 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 549 */
bogdanm 86:04dd9b1680ae 550 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm 86:04dd9b1680ae 551 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm 86:04dd9b1680ae 552 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
bogdanm 86:04dd9b1680ae 553 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm 86:04dd9b1680ae 554 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
bogdanm 86:04dd9b1680ae 555 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm 86:04dd9b1680ae 556 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm 86:04dd9b1680ae 557 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm 86:04dd9b1680ae 558 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm 86:04dd9b1680ae 559 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm 86:04dd9b1680ae 560 #define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
bogdanm 86:04dd9b1680ae 561 #define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
bogdanm 86:04dd9b1680ae 562 #define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
bogdanm 86:04dd9b1680ae 563 #define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
bogdanm 86:04dd9b1680ae 564
bogdanm 86:04dd9b1680ae 565 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm 86:04dd9b1680ae 566 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm 86:04dd9b1680ae 567 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
bogdanm 86:04dd9b1680ae 568 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm 86:04dd9b1680ae 569 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
bogdanm 86:04dd9b1680ae 570 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm 86:04dd9b1680ae 571 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm 86:04dd9b1680ae 572 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm 86:04dd9b1680ae 573 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm 86:04dd9b1680ae 574 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm 86:04dd9b1680ae 575 #define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
bogdanm 86:04dd9b1680ae 576 #define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
bogdanm 86:04dd9b1680ae 577 #define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
bogdanm 86:04dd9b1680ae 578
bogdanm 86:04dd9b1680ae 579 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 580 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 581 * power consumption.
bogdanm 86:04dd9b1680ae 582 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 583 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 584 */
bogdanm 86:04dd9b1680ae 585 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
bogdanm 86:04dd9b1680ae 586 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm 86:04dd9b1680ae 587
bogdanm 86:04dd9b1680ae 588 #if defined(STM32F437xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 589 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
bogdanm 86:04dd9b1680ae 590 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
bogdanm 86:04dd9b1680ae 591
bogdanm 86:04dd9b1680ae 592 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
bogdanm 86:04dd9b1680ae 593 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm 86:04dd9b1680ae 594 #endif /* STM32F437xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 595
bogdanm 86:04dd9b1680ae 596 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 597 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 598 * power consumption.
bogdanm 86:04dd9b1680ae 599 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 600 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 601 */
bogdanm 86:04dd9b1680ae 602 #define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
bogdanm 86:04dd9b1680ae 603 #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
bogdanm 86:04dd9b1680ae 604
bogdanm 86:04dd9b1680ae 605 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 606 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 607 * power consumption.
bogdanm 86:04dd9b1680ae 608 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 609 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 610 */
bogdanm 86:04dd9b1680ae 611 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
bogdanm 86:04dd9b1680ae 612 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
bogdanm 86:04dd9b1680ae 613 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
bogdanm 86:04dd9b1680ae 614 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
bogdanm 86:04dd9b1680ae 615 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
bogdanm 86:04dd9b1680ae 616 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
bogdanm 86:04dd9b1680ae 617 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
bogdanm 86:04dd9b1680ae 618 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
bogdanm 86:04dd9b1680ae 619 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
bogdanm 86:04dd9b1680ae 620 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
bogdanm 86:04dd9b1680ae 621 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
bogdanm 86:04dd9b1680ae 622 #define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
bogdanm 86:04dd9b1680ae 623 #define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
bogdanm 86:04dd9b1680ae 624
bogdanm 86:04dd9b1680ae 625 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm 86:04dd9b1680ae 626 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm 86:04dd9b1680ae 627 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm 86:04dd9b1680ae 628 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm 86:04dd9b1680ae 629 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm 86:04dd9b1680ae 630 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm 86:04dd9b1680ae 631 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm 86:04dd9b1680ae 632 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm 86:04dd9b1680ae 633 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm 86:04dd9b1680ae 634 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm 86:04dd9b1680ae 635 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
bogdanm 86:04dd9b1680ae 636 #define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
bogdanm 86:04dd9b1680ae 637 #define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
bogdanm 86:04dd9b1680ae 638
bogdanm 86:04dd9b1680ae 639 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 640 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 641 * power consumption.
bogdanm 86:04dd9b1680ae 642 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 643 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 644 */
bogdanm 86:04dd9b1680ae 645 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
bogdanm 86:04dd9b1680ae 646 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
bogdanm 86:04dd9b1680ae 647 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
bogdanm 86:04dd9b1680ae 648 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
bogdanm 86:04dd9b1680ae 649 #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
bogdanm 86:04dd9b1680ae 650 #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
bogdanm 86:04dd9b1680ae 651
bogdanm 86:04dd9b1680ae 652 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm 86:04dd9b1680ae 653 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm 86:04dd9b1680ae 654 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm 86:04dd9b1680ae 655 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
bogdanm 86:04dd9b1680ae 656 #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
bogdanm 86:04dd9b1680ae 657 #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
bogdanm 86:04dd9b1680ae 658
bogdanm 86:04dd9b1680ae 659 #if defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 660 #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
bogdanm 86:04dd9b1680ae 661
bogdanm 86:04dd9b1680ae 662 #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
bogdanm 86:04dd9b1680ae 663 #endif /* STM32F429xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 664 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
bogdanm 86:04dd9b1680ae 665 /*---------------------------------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 666
bogdanm 86:04dd9b1680ae 667 /*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/
bogdanm 86:04dd9b1680ae 668 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 86:04dd9b1680ae 669 /** @brief Enables or disables the AHB1 peripheral clock.
bogdanm 86:04dd9b1680ae 670 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 671 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 672 * using it.
bogdanm 86:04dd9b1680ae 673 */
bogdanm 86:04dd9b1680ae 674 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
bogdanm 86:04dd9b1680ae 675 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
bogdanm 86:04dd9b1680ae 676 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
bogdanm 86:04dd9b1680ae 677 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
bogdanm 86:04dd9b1680ae 678 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
bogdanm 86:04dd9b1680ae 679
bogdanm 86:04dd9b1680ae 680 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm 86:04dd9b1680ae 681 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm 86:04dd9b1680ae 682 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
bogdanm 86:04dd9b1680ae 683 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm 86:04dd9b1680ae 684 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm 86:04dd9b1680ae 685
bogdanm 86:04dd9b1680ae 686 #if defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 86:04dd9b1680ae 687 /**
bogdanm 86:04dd9b1680ae 688 * @brief Enable ETHERNET clock.
bogdanm 86:04dd9b1680ae 689 */
bogdanm 86:04dd9b1680ae 690 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
bogdanm 86:04dd9b1680ae 691 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
bogdanm 86:04dd9b1680ae 692 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
bogdanm 86:04dd9b1680ae 693 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
bogdanm 86:04dd9b1680ae 694 #define __ETH_CLK_ENABLE() do { \
bogdanm 86:04dd9b1680ae 695 __ETHMAC_CLK_ENABLE(); \
bogdanm 86:04dd9b1680ae 696 __ETHMACTX_CLK_ENABLE(); \
bogdanm 86:04dd9b1680ae 697 __ETHMACRX_CLK_ENABLE(); \
bogdanm 86:04dd9b1680ae 698 } while(0)
bogdanm 86:04dd9b1680ae 699
bogdanm 86:04dd9b1680ae 700 /**
bogdanm 86:04dd9b1680ae 701 * @brief Disable ETHERNET clock.
bogdanm 86:04dd9b1680ae 702 */
bogdanm 86:04dd9b1680ae 703 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
bogdanm 86:04dd9b1680ae 704 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
bogdanm 86:04dd9b1680ae 705 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
bogdanm 86:04dd9b1680ae 706 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
bogdanm 86:04dd9b1680ae 707 #define __ETH_CLK_DISABLE() do { \
bogdanm 86:04dd9b1680ae 708 __ETHMACTX_CLK_DISABLE(); \
bogdanm 86:04dd9b1680ae 709 __ETHMACRX_CLK_DISABLE(); \
bogdanm 86:04dd9b1680ae 710 __ETHMAC_CLK_DISABLE(); \
bogdanm 86:04dd9b1680ae 711 } while(0)
bogdanm 86:04dd9b1680ae 712 #endif /* STM32F407xx || STM32F417xx */
bogdanm 86:04dd9b1680ae 713
bogdanm 86:04dd9b1680ae 714 /** @brief Enable or disable the AHB2 peripheral clock.
bogdanm 86:04dd9b1680ae 715 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 716 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 717 * using it.
bogdanm 86:04dd9b1680ae 718 */
bogdanm 86:04dd9b1680ae 719 #if defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 86:04dd9b1680ae 720 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
bogdanm 86:04dd9b1680ae 721 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm 86:04dd9b1680ae 722 #endif /* STM32F407xx || STM32F417xx */
bogdanm 86:04dd9b1680ae 723
bogdanm 86:04dd9b1680ae 724 #if defined(STM32F415xx) || defined(STM32F417xx)
bogdanm 86:04dd9b1680ae 725 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
bogdanm 86:04dd9b1680ae 726 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
bogdanm 86:04dd9b1680ae 727
bogdanm 86:04dd9b1680ae 728 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
bogdanm 86:04dd9b1680ae 729 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm 86:04dd9b1680ae 730 #endif /* STM32F415xx || STM32F417xx */
bogdanm 86:04dd9b1680ae 731
bogdanm 86:04dd9b1680ae 732 /** @brief Enables or disables the AHB3 peripheral clock.
bogdanm 86:04dd9b1680ae 733 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 734 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 735 * using it.
bogdanm 86:04dd9b1680ae 736 */
bogdanm 86:04dd9b1680ae 737 #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
bogdanm 86:04dd9b1680ae 738 #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
bogdanm 86:04dd9b1680ae 739
bogdanm 86:04dd9b1680ae 740 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 86:04dd9b1680ae 741 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 742 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 743 * using it.
bogdanm 86:04dd9b1680ae 744 */
bogdanm 86:04dd9b1680ae 745 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
bogdanm 86:04dd9b1680ae 746 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
bogdanm 86:04dd9b1680ae 747 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
bogdanm 86:04dd9b1680ae 748 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
bogdanm 86:04dd9b1680ae 749 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
bogdanm 86:04dd9b1680ae 750 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
bogdanm 86:04dd9b1680ae 751 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
bogdanm 86:04dd9b1680ae 752 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
bogdanm 86:04dd9b1680ae 753 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
bogdanm 86:04dd9b1680ae 754 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
bogdanm 86:04dd9b1680ae 755 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
bogdanm 86:04dd9b1680ae 756 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
bogdanm 86:04dd9b1680ae 757
bogdanm 86:04dd9b1680ae 758 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm 86:04dd9b1680ae 759 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm 86:04dd9b1680ae 760 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm 86:04dd9b1680ae 761 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm 86:04dd9b1680ae 762 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm 86:04dd9b1680ae 763 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm 86:04dd9b1680ae 764 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm 86:04dd9b1680ae 765 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm 86:04dd9b1680ae 766 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm 86:04dd9b1680ae 767 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm 86:04dd9b1680ae 768 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm 86:04dd9b1680ae 769 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm 86:04dd9b1680ae 770
bogdanm 86:04dd9b1680ae 771 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 86:04dd9b1680ae 772 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 773 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 774 * using it.
bogdanm 86:04dd9b1680ae 775 */
bogdanm 86:04dd9b1680ae 776 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
bogdanm 86:04dd9b1680ae 777 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
bogdanm 86:04dd9b1680ae 778 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
bogdanm 86:04dd9b1680ae 779
bogdanm 86:04dd9b1680ae 780 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm 86:04dd9b1680ae 781 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm 86:04dd9b1680ae 782 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
bogdanm 86:04dd9b1680ae 783
bogdanm 86:04dd9b1680ae 784 /** @brief Force or release AHB1 peripheral reset.
bogdanm 86:04dd9b1680ae 785 */
bogdanm 86:04dd9b1680ae 786 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
bogdanm 86:04dd9b1680ae 787 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
bogdanm 86:04dd9b1680ae 788 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
bogdanm 86:04dd9b1680ae 789 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
bogdanm 86:04dd9b1680ae 790 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
bogdanm 86:04dd9b1680ae 791
bogdanm 86:04dd9b1680ae 792 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm 86:04dd9b1680ae 793 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm 86:04dd9b1680ae 794 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm 86:04dd9b1680ae 795 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
bogdanm 86:04dd9b1680ae 796 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm 86:04dd9b1680ae 797
bogdanm 86:04dd9b1680ae 798 /** @brief Force or release AHB2 peripheral reset.
bogdanm 86:04dd9b1680ae 799 */
bogdanm 86:04dd9b1680ae 800 #if defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 86:04dd9b1680ae 801 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
bogdanm 86:04dd9b1680ae 802 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm 86:04dd9b1680ae 803 #endif /* STM32F407xx || STM32F417xx */
bogdanm 86:04dd9b1680ae 804
bogdanm 86:04dd9b1680ae 805 #if defined(STM32F415xx) || defined(STM32F417xx)
bogdanm 86:04dd9b1680ae 806 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
bogdanm 86:04dd9b1680ae 807 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
bogdanm 86:04dd9b1680ae 808
bogdanm 86:04dd9b1680ae 809 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
bogdanm 86:04dd9b1680ae 810 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm 86:04dd9b1680ae 811
bogdanm 86:04dd9b1680ae 812 #endif /* STM32F415xx || STM32F417xx */
bogdanm 86:04dd9b1680ae 813
bogdanm 86:04dd9b1680ae 814 /** @brief Force or release AHB3 peripheral reset
bogdanm 86:04dd9b1680ae 815 */
bogdanm 86:04dd9b1680ae 816 #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
bogdanm 86:04dd9b1680ae 817 #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
bogdanm 86:04dd9b1680ae 818
bogdanm 86:04dd9b1680ae 819 /** @brief Force or release APB1 peripheral reset.
bogdanm 86:04dd9b1680ae 820 */
bogdanm 86:04dd9b1680ae 821 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
bogdanm 86:04dd9b1680ae 822 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
bogdanm 86:04dd9b1680ae 823 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
bogdanm 86:04dd9b1680ae 824 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
bogdanm 86:04dd9b1680ae 825 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
bogdanm 86:04dd9b1680ae 826 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
bogdanm 86:04dd9b1680ae 827 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
bogdanm 86:04dd9b1680ae 828 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
bogdanm 86:04dd9b1680ae 829 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
bogdanm 86:04dd9b1680ae 830 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
bogdanm 86:04dd9b1680ae 831 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
bogdanm 86:04dd9b1680ae 832
bogdanm 86:04dd9b1680ae 833 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm 86:04dd9b1680ae 834 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm 86:04dd9b1680ae 835 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm 86:04dd9b1680ae 836 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm 86:04dd9b1680ae 837 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm 86:04dd9b1680ae 838 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm 86:04dd9b1680ae 839 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm 86:04dd9b1680ae 840 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm 86:04dd9b1680ae 841 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm 86:04dd9b1680ae 842 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm 86:04dd9b1680ae 843 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm 86:04dd9b1680ae 844
bogdanm 86:04dd9b1680ae 845 /** @brief Force or release APB2 peripheral reset.
bogdanm 86:04dd9b1680ae 846 */
bogdanm 86:04dd9b1680ae 847 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
bogdanm 86:04dd9b1680ae 848 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm 86:04dd9b1680ae 849
bogdanm 86:04dd9b1680ae 850 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 851 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 852 * power consumption.
bogdanm 86:04dd9b1680ae 853 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 854 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 855 */
bogdanm 86:04dd9b1680ae 856 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm 86:04dd9b1680ae 857 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm 86:04dd9b1680ae 858 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
bogdanm 86:04dd9b1680ae 859 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm 86:04dd9b1680ae 860 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
bogdanm 86:04dd9b1680ae 861 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm 86:04dd9b1680ae 862 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm 86:04dd9b1680ae 863 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm 86:04dd9b1680ae 864 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm 86:04dd9b1680ae 865 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm 86:04dd9b1680ae 866
bogdanm 86:04dd9b1680ae 867 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm 86:04dd9b1680ae 868 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm 86:04dd9b1680ae 869 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
bogdanm 86:04dd9b1680ae 870 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm 86:04dd9b1680ae 871 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
bogdanm 86:04dd9b1680ae 872 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm 86:04dd9b1680ae 873 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm 86:04dd9b1680ae 874 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm 86:04dd9b1680ae 875 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm 86:04dd9b1680ae 876 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm 86:04dd9b1680ae 877
bogdanm 86:04dd9b1680ae 878 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 879 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 880 * power consumption.
bogdanm 86:04dd9b1680ae 881 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 882 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 883 */
bogdanm 86:04dd9b1680ae 884 #if defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 86:04dd9b1680ae 885 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
bogdanm 86:04dd9b1680ae 886 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm 86:04dd9b1680ae 887 #endif /* STM32F407xx || STM32F417xx */
bogdanm 86:04dd9b1680ae 888
bogdanm 86:04dd9b1680ae 889 #if defined(STM32F415xx) || defined(STM32F417xx)
bogdanm 86:04dd9b1680ae 890 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
bogdanm 86:04dd9b1680ae 891 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
bogdanm 86:04dd9b1680ae 892
bogdanm 86:04dd9b1680ae 893 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
bogdanm 86:04dd9b1680ae 894 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm 86:04dd9b1680ae 895 #endif /* STM32F415xx || STM32F417xx */
bogdanm 86:04dd9b1680ae 896
bogdanm 86:04dd9b1680ae 897 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 898 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 899 * power consumption.
bogdanm 86:04dd9b1680ae 900 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 901 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 902 */
bogdanm 86:04dd9b1680ae 903 #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
bogdanm 86:04dd9b1680ae 904 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
bogdanm 86:04dd9b1680ae 905
bogdanm 86:04dd9b1680ae 906 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 907 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 908 * power consumption.
bogdanm 86:04dd9b1680ae 909 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 910 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 911 */
bogdanm 86:04dd9b1680ae 912 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
bogdanm 86:04dd9b1680ae 913 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
bogdanm 86:04dd9b1680ae 914 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
bogdanm 86:04dd9b1680ae 915 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
bogdanm 86:04dd9b1680ae 916 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
bogdanm 86:04dd9b1680ae 917 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
bogdanm 86:04dd9b1680ae 918 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
bogdanm 86:04dd9b1680ae 919 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
bogdanm 86:04dd9b1680ae 920 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
bogdanm 86:04dd9b1680ae 921 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
bogdanm 86:04dd9b1680ae 922 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
bogdanm 86:04dd9b1680ae 923
bogdanm 86:04dd9b1680ae 924 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm 86:04dd9b1680ae 925 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm 86:04dd9b1680ae 926 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm 86:04dd9b1680ae 927 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm 86:04dd9b1680ae 928 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm 86:04dd9b1680ae 929 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm 86:04dd9b1680ae 930 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm 86:04dd9b1680ae 931 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm 86:04dd9b1680ae 932 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm 86:04dd9b1680ae 933 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm 86:04dd9b1680ae 934 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
bogdanm 86:04dd9b1680ae 935
bogdanm 86:04dd9b1680ae 936 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 937 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 938 * power consumption.
bogdanm 86:04dd9b1680ae 939 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 940 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 86:04dd9b1680ae 941 */
bogdanm 86:04dd9b1680ae 942 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
bogdanm 86:04dd9b1680ae 943 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
bogdanm 86:04dd9b1680ae 944 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
bogdanm 86:04dd9b1680ae 945
bogdanm 86:04dd9b1680ae 946 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm 86:04dd9b1680ae 947 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm 86:04dd9b1680ae 948 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm 86:04dd9b1680ae 949 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 86:04dd9b1680ae 950 /*---------------------------------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 951
bogdanm 86:04dd9b1680ae 952 /*------------------------------------------ STM32F411xx --------------------------------------*/
bogdanm 86:04dd9b1680ae 953 #if defined(STM32F411xE)
bogdanm 86:04dd9b1680ae 954 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 86:04dd9b1680ae 955 */
bogdanm 86:04dd9b1680ae 956 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
bogdanm 86:04dd9b1680ae 957 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
bogdanm 86:04dd9b1680ae 958
bogdanm 86:04dd9b1680ae 959 /** @brief Force or release APB2 peripheral reset.
bogdanm 86:04dd9b1680ae 960 */
bogdanm 86:04dd9b1680ae 961 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
bogdanm 86:04dd9b1680ae 962 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
bogdanm 86:04dd9b1680ae 963
bogdanm 86:04dd9b1680ae 964 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 965 */
bogdanm 86:04dd9b1680ae 966 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
bogdanm 86:04dd9b1680ae 967 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
bogdanm 86:04dd9b1680ae 968
bogdanm 86:04dd9b1680ae 969 #endif /* STM32F411xE */
bogdanm 86:04dd9b1680ae 970 /*---------------------------------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 971
bogdanm 86:04dd9b1680ae 972 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
bogdanm 86:04dd9b1680ae 973 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
bogdanm 86:04dd9b1680ae 974
bogdanm 86:04dd9b1680ae 975 /** @brief Macro to configure the Timers clocks prescalers
bogdanm 86:04dd9b1680ae 976 * @note This feature is only available with STM32F429x/439x Devices.
bogdanm 86:04dd9b1680ae 977 * @param __PRESC__ : specifies the Timers clocks prescalers selection
bogdanm 86:04dd9b1680ae 978 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 979 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
bogdanm 86:04dd9b1680ae 980 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
bogdanm 86:04dd9b1680ae 981 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
bogdanm 86:04dd9b1680ae 982 * division by 4 or more.
bogdanm 86:04dd9b1680ae 983 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
bogdanm 86:04dd9b1680ae 984 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
bogdanm 86:04dd9b1680ae 985 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
bogdanm 86:04dd9b1680ae 986 * to division by 8 or more.
bogdanm 86:04dd9b1680ae 987 */
bogdanm 86:04dd9b1680ae 988 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
bogdanm 86:04dd9b1680ae 989
bogdanm 86:04dd9b1680ae 990 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */
bogdanm 86:04dd9b1680ae 991
bogdanm 86:04dd9b1680ae 992 #if defined(STM32F411xE)
bogdanm 86:04dd9b1680ae 993
bogdanm 86:04dd9b1680ae 994 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
bogdanm 86:04dd9b1680ae 995 * @note This macro must be used only when the PLLI2S is disabled.
bogdanm 86:04dd9b1680ae 996 * @note This macro must be used only when the PLLI2S is disabled.
bogdanm 86:04dd9b1680ae 997 * @note PLLI2S clock source is common with the main PLL (configured in
bogdanm 86:04dd9b1680ae 998 * HAL_RCC_ClockConfig() API).
bogdanm 86:04dd9b1680ae 999 * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
bogdanm 86:04dd9b1680ae 1000 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm 86:04dd9b1680ae 1001 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
bogdanm 86:04dd9b1680ae 1002 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm 86:04dd9b1680ae 1003 * of 2 MHz to limit PLLI2S jitter.
bogdanm 86:04dd9b1680ae 1004 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
bogdanm 86:04dd9b1680ae 1005 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 86:04dd9b1680ae 1006 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm 86:04dd9b1680ae 1007 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm 86:04dd9b1680ae 1008 * @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm 86:04dd9b1680ae 1009 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 86:04dd9b1680ae 1010 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm 86:04dd9b1680ae 1011 * on the I2S clock frequency.
bogdanm 86:04dd9b1680ae 1012 */
bogdanm 86:04dd9b1680ae 1013 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
bogdanm 86:04dd9b1680ae 1014 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__))
bogdanm 86:04dd9b1680ae 1015 #endif /* STM32F411xE */
bogdanm 86:04dd9b1680ae 1016
bogdanm 86:04dd9b1680ae 1017
bogdanm 86:04dd9b1680ae 1018 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 86:04dd9b1680ae 1019
bogdanm 86:04dd9b1680ae 1020 /** @brief Macros to Enable or Disable the PLLISAI.
bogdanm 86:04dd9b1680ae 1021 * @note The PLLSAI is only available with STM32F429x/439x Devices.
bogdanm 86:04dd9b1680ae 1022 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 1023 */
bogdanm 86:04dd9b1680ae 1024 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
bogdanm 86:04dd9b1680ae 1025 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
bogdanm 86:04dd9b1680ae 1026
bogdanm 86:04dd9b1680ae 1027 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
bogdanm 86:04dd9b1680ae 1028 * @note The PLLSAI is only available with STM32F429x/439x Devices.
bogdanm 86:04dd9b1680ae 1029 * @note This function must be used only when the PLLSAI is disabled.
bogdanm 86:04dd9b1680ae 1030 * @note PLLSAI clock source is common with the main PLL (configured in
bogdanm 86:04dd9b1680ae 1031 * RCC_PLLConfig function )
bogdanm 86:04dd9b1680ae 1032 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
bogdanm 86:04dd9b1680ae 1033 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 86:04dd9b1680ae 1034 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
bogdanm 86:04dd9b1680ae 1035 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm 86:04dd9b1680ae 1036 * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
bogdanm 86:04dd9b1680ae 1037 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 86:04dd9b1680ae 1038 * @param __PLLSAIR__: specifies the division factor for LTDC clock
bogdanm 86:04dd9b1680ae 1039 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 86:04dd9b1680ae 1040 */
bogdanm 86:04dd9b1680ae 1041 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
bogdanm 86:04dd9b1680ae 1042
bogdanm 86:04dd9b1680ae 1043 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
bogdanm 86:04dd9b1680ae 1044 * @note This macro must be used only when the PLLI2S is disabled.
bogdanm 86:04dd9b1680ae 1045 * @note PLLI2S clock source is common with the main PLL (configured in
bogdanm 86:04dd9b1680ae 1046 * HAL_RCC_ClockConfig() API)
bogdanm 86:04dd9b1680ae 1047 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 86:04dd9b1680ae 1048 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 86:04dd9b1680ae 1049 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm 86:04dd9b1680ae 1050 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm 86:04dd9b1680ae 1051 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
bogdanm 86:04dd9b1680ae 1052 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 86:04dd9b1680ae 1053 * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
bogdanm 86:04dd9b1680ae 1054 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
bogdanm 86:04dd9b1680ae 1055 * @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm 86:04dd9b1680ae 1056 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 86:04dd9b1680ae 1057 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm 86:04dd9b1680ae 1058 * on the I2S clock frequency.
bogdanm 86:04dd9b1680ae 1059 */
bogdanm 86:04dd9b1680ae 1060 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
bogdanm 86:04dd9b1680ae 1061
bogdanm 86:04dd9b1680ae 1062 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
bogdanm 86:04dd9b1680ae 1063 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm 86:04dd9b1680ae 1064 * @note This function must be called before enabling the PLLI2S.
bogdanm 86:04dd9b1680ae 1065 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
bogdanm 86:04dd9b1680ae 1066 * This parameter must be a number between 1 and 32.
bogdanm 86:04dd9b1680ae 1067 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
bogdanm 86:04dd9b1680ae 1068 */
bogdanm 86:04dd9b1680ae 1069 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
bogdanm 86:04dd9b1680ae 1070
bogdanm 86:04dd9b1680ae 1071 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
bogdanm 86:04dd9b1680ae 1072 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm 86:04dd9b1680ae 1073 * @note This function must be called before enabling the PLLSAI.
bogdanm 86:04dd9b1680ae 1074 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
bogdanm 86:04dd9b1680ae 1075 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
bogdanm 86:04dd9b1680ae 1076 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
bogdanm 86:04dd9b1680ae 1077 */
bogdanm 86:04dd9b1680ae 1078 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
bogdanm 86:04dd9b1680ae 1079
bogdanm 86:04dd9b1680ae 1080 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
bogdanm 86:04dd9b1680ae 1081 *
bogdanm 86:04dd9b1680ae 1082 * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
bogdanm 86:04dd9b1680ae 1083 * @note This function must be called before enabling the PLLSAI.
bogdanm 86:04dd9b1680ae 1084 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
bogdanm 86:04dd9b1680ae 1085 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
bogdanm 86:04dd9b1680ae 1086 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
bogdanm 86:04dd9b1680ae 1087 */
bogdanm 86:04dd9b1680ae 1088 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
bogdanm 86:04dd9b1680ae 1089
bogdanm 86:04dd9b1680ae 1090 /** @brief Macro to configure SAI1BlockA clock source selection.
bogdanm 86:04dd9b1680ae 1091 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm 86:04dd9b1680ae 1092 * @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm 86:04dd9b1680ae 1093 * the SAI clock.
bogdanm 86:04dd9b1680ae 1094 * @param __SOURCE__: specifies the SAI Block A clock source.
bogdanm 86:04dd9b1680ae 1095 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1096 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm 86:04dd9b1680ae 1097 * as SAI1 Block A clock.
bogdanm 86:04dd9b1680ae 1098 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm 86:04dd9b1680ae 1099 * as SAI1 Block A clock.
bogdanm 86:04dd9b1680ae 1100 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 1101 * used as SAI1 Block A clock.
bogdanm 86:04dd9b1680ae 1102 */
bogdanm 86:04dd9b1680ae 1103 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
bogdanm 86:04dd9b1680ae 1104
bogdanm 86:04dd9b1680ae 1105 /** @brief Macro to configure SAI1BlockB clock source selection.
bogdanm 86:04dd9b1680ae 1106 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm 86:04dd9b1680ae 1107 * @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm 86:04dd9b1680ae 1108 * the SAI clock.
bogdanm 86:04dd9b1680ae 1109 * @param __SOURCE__: specifies the SAI Block B clock source.
bogdanm 86:04dd9b1680ae 1110 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1111 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm 86:04dd9b1680ae 1112 * as SAI1 Block B clock.
bogdanm 86:04dd9b1680ae 1113 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm 86:04dd9b1680ae 1114 * as SAI1 Block B clock.
bogdanm 86:04dd9b1680ae 1115 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 1116 * used as SAI1 Block B clock.
bogdanm 86:04dd9b1680ae 1117 */
bogdanm 86:04dd9b1680ae 1118 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
bogdanm 86:04dd9b1680ae 1119
bogdanm 86:04dd9b1680ae 1120 /** @brief Enable PLLSAI_RDY interrupt.
bogdanm 86:04dd9b1680ae 1121 */
bogdanm 86:04dd9b1680ae 1122 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
bogdanm 86:04dd9b1680ae 1123
bogdanm 86:04dd9b1680ae 1124 /** @brief Disable PLLSAI_RDY interrupt.
bogdanm 86:04dd9b1680ae 1125 */
bogdanm 86:04dd9b1680ae 1126 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
bogdanm 86:04dd9b1680ae 1127
bogdanm 86:04dd9b1680ae 1128 /** @brief Clear the PLLSAI RDY interrupt pending bits.
bogdanm 86:04dd9b1680ae 1129 */
bogdanm 86:04dd9b1680ae 1130 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
bogdanm 86:04dd9b1680ae 1131
bogdanm 86:04dd9b1680ae 1132 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
bogdanm 86:04dd9b1680ae 1133 * @retval The new state (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 1134 */
bogdanm 86:04dd9b1680ae 1135 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
bogdanm 86:04dd9b1680ae 1136
bogdanm 86:04dd9b1680ae 1137 /** @brief Check PLLSAI RDY flag is set or not.
bogdanm 86:04dd9b1680ae 1138 * @retval The new state (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 1139 */
bogdanm 86:04dd9b1680ae 1140 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
bogdanm 86:04dd9b1680ae 1141
bogdanm 86:04dd9b1680ae 1142 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 86:04dd9b1680ae 1143
bogdanm 86:04dd9b1680ae 1144 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 1145 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm 86:04dd9b1680ae 1146 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm 86:04dd9b1680ae 1147
bogdanm 86:04dd9b1680ae 1148 #if defined(STM32F411xE)
bogdanm 86:04dd9b1680ae 1149 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
bogdanm 86:04dd9b1680ae 1150 #endif /* STM32F411xE */
bogdanm 86:04dd9b1680ae 1151 /**
bogdanm 86:04dd9b1680ae 1152 * @}
bogdanm 86:04dd9b1680ae 1153 */
bogdanm 86:04dd9b1680ae 1154
bogdanm 86:04dd9b1680ae 1155 /**
bogdanm 86:04dd9b1680ae 1156 * @}
bogdanm 86:04dd9b1680ae 1157 */
bogdanm 86:04dd9b1680ae 1158
bogdanm 86:04dd9b1680ae 1159 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 1160 }
bogdanm 86:04dd9b1680ae 1161 #endif
bogdanm 86:04dd9b1680ae 1162
bogdanm 86:04dd9b1680ae 1163 #endif /* __STM32F4xx_HAL_RCC_EX_H */
bogdanm 86:04dd9b1680ae 1164
bogdanm 86:04dd9b1680ae 1165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/