frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc.h@86:04dd9b1680ae, 2014-07-02 (annotated)

Committer:
bogdanm
Date:
Wed Jul 02 13:22:23 2014 +0100
Revision:
86:04dd9b1680ae
Child:
92:4fc01daae5a5
Release 86 of the mbed library



Main changes:





- bug fixes in various backends

- mbed "error" replaced by assert logic (mbed_assert)

- new ST Nucleo targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_rcc.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.0.1
bogdanm 86:04dd9b1680ae 6 * @date 18-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of RCC HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_RCC_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_RCC_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup RCC
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59 /**
bogdanm 86:04dd9b1680ae 60 * @brief RCC PLL configuration structure definition
bogdanm 86:04dd9b1680ae 61 */
bogdanm 86:04dd9b1680ae 62 typedef struct
bogdanm 86:04dd9b1680ae 63 {
bogdanm 86:04dd9b1680ae 64 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
bogdanm 86:04dd9b1680ae 65 This parameter can be a value of @ref RCC_PLL_Config */
bogdanm 86:04dd9b1680ae 66
bogdanm 86:04dd9b1680ae 67 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
bogdanm 86:04dd9b1680ae 68 This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm 86:04dd9b1680ae 69
bogdanm 86:04dd9b1680ae 70 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
bogdanm 86:04dd9b1680ae 71 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
bogdanm 86:04dd9b1680ae 72
bogdanm 86:04dd9b1680ae 73 }RCC_PLLInitTypeDef;
bogdanm 86:04dd9b1680ae 74
bogdanm 86:04dd9b1680ae 75 /**
bogdanm 86:04dd9b1680ae 76 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 86:04dd9b1680ae 77 */
bogdanm 86:04dd9b1680ae 78 typedef struct
bogdanm 86:04dd9b1680ae 79 {
bogdanm 86:04dd9b1680ae 80 uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm 86:04dd9b1680ae 81 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 86:04dd9b1680ae 82
bogdanm 86:04dd9b1680ae 83 uint32_t HSEState; /*!< The new state of the HSE.
bogdanm 86:04dd9b1680ae 84 This parameter can be a value of @ref RCC_HSE_Config */
bogdanm 86:04dd9b1680ae 85
bogdanm 86:04dd9b1680ae 86 uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
bogdanm 86:04dd9b1680ae 87 This parameter can be a value of @ref RCC_HSE_Predivision_Factor */
bogdanm 86:04dd9b1680ae 88
bogdanm 86:04dd9b1680ae 89 uint32_t LSEState; /*!< The new state of the LSE.
bogdanm 86:04dd9b1680ae 90 This parameter can be a value of @ref RCC_LSE_Config */
bogdanm 86:04dd9b1680ae 91
bogdanm 86:04dd9b1680ae 92 uint32_t HSIState; /*!< The new state of the HSI.
bogdanm 86:04dd9b1680ae 93 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 86:04dd9b1680ae 94
bogdanm 86:04dd9b1680ae 95 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm 86:04dd9b1680ae 96 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm 86:04dd9b1680ae 97
bogdanm 86:04dd9b1680ae 98 uint32_t LSIState; /*!< The new state of the LSI.
bogdanm 86:04dd9b1680ae 99 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 86:04dd9b1680ae 100
bogdanm 86:04dd9b1680ae 101 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 86:04dd9b1680ae 102
bogdanm 86:04dd9b1680ae 103 }RCC_OscInitTypeDef;
bogdanm 86:04dd9b1680ae 104
bogdanm 86:04dd9b1680ae 105 /**
bogdanm 86:04dd9b1680ae 106 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 86:04dd9b1680ae 107 */
bogdanm 86:04dd9b1680ae 108 typedef struct
bogdanm 86:04dd9b1680ae 109 {
bogdanm 86:04dd9b1680ae 110 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 86:04dd9b1680ae 111 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 86:04dd9b1680ae 112
bogdanm 86:04dd9b1680ae 113 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 86:04dd9b1680ae 114 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 86:04dd9b1680ae 115
bogdanm 86:04dd9b1680ae 116 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 86:04dd9b1680ae 117 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 86:04dd9b1680ae 118
bogdanm 86:04dd9b1680ae 119 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 86:04dd9b1680ae 120 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 86:04dd9b1680ae 121
bogdanm 86:04dd9b1680ae 122 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 86:04dd9b1680ae 123 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 86:04dd9b1680ae 124
bogdanm 86:04dd9b1680ae 125 }RCC_ClkInitTypeDef;
bogdanm 86:04dd9b1680ae 126
bogdanm 86:04dd9b1680ae 127 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 128 /** @defgroup RCC_Exported_Constants
bogdanm 86:04dd9b1680ae 129 * @{
bogdanm 86:04dd9b1680ae 130 */
bogdanm 86:04dd9b1680ae 131
bogdanm 86:04dd9b1680ae 132 /** @defgroup RCC_BitAddress_AliasRegion
bogdanm 86:04dd9b1680ae 133 * @brief RCC registers bit address in the alias region
bogdanm 86:04dd9b1680ae 134 * @{
bogdanm 86:04dd9b1680ae 135 */
bogdanm 86:04dd9b1680ae 136 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm 86:04dd9b1680ae 137 /* --- CR Register ---*/
bogdanm 86:04dd9b1680ae 138 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm 86:04dd9b1680ae 139 /* Alias word address of HSION bit */
bogdanm 86:04dd9b1680ae 140 #define HSION_BitNumber 0
bogdanm 86:04dd9b1680ae 141 #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
bogdanm 86:04dd9b1680ae 142 /* Alias word address of HSEON bit */
bogdanm 86:04dd9b1680ae 143 #define HSEON_BitNumber 16
bogdanm 86:04dd9b1680ae 144 #define CR_HSEON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSEON_BitNumber * 4))
bogdanm 86:04dd9b1680ae 145 /* Alias word address of CSSON bit */
bogdanm 86:04dd9b1680ae 146 #define CSSON_BitNumber 19
bogdanm 86:04dd9b1680ae 147 #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
bogdanm 86:04dd9b1680ae 148 /* Alias word address of PLLON bit */
bogdanm 86:04dd9b1680ae 149 #define PLLON_BitNumber 24
bogdanm 86:04dd9b1680ae 150 #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
bogdanm 86:04dd9b1680ae 151
bogdanm 86:04dd9b1680ae 152 /* --- CFGR Register ---*/
bogdanm 86:04dd9b1680ae 153 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
bogdanm 86:04dd9b1680ae 154 /* Alias word address of PLLSRC bit */
bogdanm 86:04dd9b1680ae 155 #define PLLSRC_BitNumber 16
bogdanm 86:04dd9b1680ae 156 #define CFGR_PLLSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (PLLSRC_BitNumber * 4))
bogdanm 86:04dd9b1680ae 157
bogdanm 86:04dd9b1680ae 158 /* --- CIR Register ---*/
bogdanm 86:04dd9b1680ae 159 #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
bogdanm 86:04dd9b1680ae 160
bogdanm 86:04dd9b1680ae 161 /* --- BDCR Register ---*/
bogdanm 86:04dd9b1680ae 162 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
bogdanm 86:04dd9b1680ae 163 /* Alias word address of LSEON bit */
bogdanm 86:04dd9b1680ae 164 #define LSEON_BitNumber 0
bogdanm 86:04dd9b1680ae 165 #define BDCR_LSEON_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (LSEON_BitNumber * 4))
bogdanm 86:04dd9b1680ae 166 /* Alias word address of RTCEN bit */
bogdanm 86:04dd9b1680ae 167 #define RTCEN_BitNumber 15
bogdanm 86:04dd9b1680ae 168 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
bogdanm 86:04dd9b1680ae 169 /* Alias word address of BDRST bit */
bogdanm 86:04dd9b1680ae 170 #define BDRST_BitNumber 16
bogdanm 86:04dd9b1680ae 171 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
bogdanm 86:04dd9b1680ae 172
bogdanm 86:04dd9b1680ae 173 /* --- CSR Register ---*/
bogdanm 86:04dd9b1680ae 174 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
bogdanm 86:04dd9b1680ae 175 /* Alias word address of LSION bit */
bogdanm 86:04dd9b1680ae 176 #define LSION_BitNumber 0
bogdanm 86:04dd9b1680ae 177 #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
bogdanm 86:04dd9b1680ae 178 /* Alias word address of RMVF bit */
bogdanm 86:04dd9b1680ae 179 #define RMVF_BitNumber 24
bogdanm 86:04dd9b1680ae 180 #define CSR_RMVF_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RMVF_BitNumber * 4))
bogdanm 86:04dd9b1680ae 181
bogdanm 86:04dd9b1680ae 182 /* CR register byte 2 (Bits[23:16]) base address */
bogdanm 86:04dd9b1680ae 183 #define CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
bogdanm 86:04dd9b1680ae 184
bogdanm 86:04dd9b1680ae 185 /* CIR register byte 1 (Bits[15:8]) base address */
bogdanm 86:04dd9b1680ae 186 #define CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
bogdanm 86:04dd9b1680ae 187
bogdanm 86:04dd9b1680ae 188 /* CIR register byte 2 (Bits[23:16]) base address */
bogdanm 86:04dd9b1680ae 189 #define CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
bogdanm 86:04dd9b1680ae 190
bogdanm 86:04dd9b1680ae 191 /* CSR register byte 1 (Bits[15:8]) base address */
bogdanm 86:04dd9b1680ae 192 #define CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
bogdanm 86:04dd9b1680ae 193
bogdanm 86:04dd9b1680ae 194 /* BDCR register byte 0 (Bits[7:0] base address */
bogdanm 86:04dd9b1680ae 195 #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm 86:04dd9b1680ae 196
bogdanm 86:04dd9b1680ae 197 /* LSE state change timeout */
bogdanm 86:04dd9b1680ae 198 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm 86:04dd9b1680ae 199
bogdanm 86:04dd9b1680ae 200 /* Disable Backup domain write protection state change timeout */
bogdanm 86:04dd9b1680ae 201 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 86:04dd9b1680ae 202 /**
bogdanm 86:04dd9b1680ae 203 * @}
bogdanm 86:04dd9b1680ae 204 */
bogdanm 86:04dd9b1680ae 205
bogdanm 86:04dd9b1680ae 206 /** @defgroup RCC_Oscillator_Type
bogdanm 86:04dd9b1680ae 207 * @{
bogdanm 86:04dd9b1680ae 208 */
bogdanm 86:04dd9b1680ae 209 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 210 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 211 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 212 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 213 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 214
bogdanm 86:04dd9b1680ae 215 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
bogdanm 86:04dd9b1680ae 216 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
bogdanm 86:04dd9b1680ae 217 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
bogdanm 86:04dd9b1680ae 218 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
bogdanm 86:04dd9b1680ae 219 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
bogdanm 86:04dd9b1680ae 220 /**
bogdanm 86:04dd9b1680ae 221 * @}
bogdanm 86:04dd9b1680ae 222 */
bogdanm 86:04dd9b1680ae 223
bogdanm 86:04dd9b1680ae 224 /** @defgroup RCC_HSE_Config
bogdanm 86:04dd9b1680ae 225 * @{
bogdanm 86:04dd9b1680ae 226 */
bogdanm 86:04dd9b1680ae 227 #define RCC_HSE_OFF ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 228 #define RCC_HSE_ON ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 229 #define RCC_HSE_BYPASS ((uint32_t)0x00000005)
bogdanm 86:04dd9b1680ae 230
bogdanm 86:04dd9b1680ae 231 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
bogdanm 86:04dd9b1680ae 232 ((HSE) == RCC_HSE_BYPASS))
bogdanm 86:04dd9b1680ae 233 /**
bogdanm 86:04dd9b1680ae 234 * @}
bogdanm 86:04dd9b1680ae 235 */
bogdanm 86:04dd9b1680ae 236
bogdanm 86:04dd9b1680ae 237 /** @defgroup RCC_HSE_Predivision_Factor
bogdanm 86:04dd9b1680ae 238 * @{
bogdanm 86:04dd9b1680ae 239 */
bogdanm 86:04dd9b1680ae 240
bogdanm 86:04dd9b1680ae 241 #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
bogdanm 86:04dd9b1680ae 242 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
bogdanm 86:04dd9b1680ae 243 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
bogdanm 86:04dd9b1680ae 244 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
bogdanm 86:04dd9b1680ae 245 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
bogdanm 86:04dd9b1680ae 246 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
bogdanm 86:04dd9b1680ae 247 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
bogdanm 86:04dd9b1680ae 248 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
bogdanm 86:04dd9b1680ae 249 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
bogdanm 86:04dd9b1680ae 250 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
bogdanm 86:04dd9b1680ae 251 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
bogdanm 86:04dd9b1680ae 252 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
bogdanm 86:04dd9b1680ae 253 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
bogdanm 86:04dd9b1680ae 254 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
bogdanm 86:04dd9b1680ae 255 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
bogdanm 86:04dd9b1680ae 256 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
bogdanm 86:04dd9b1680ae 257
bogdanm 86:04dd9b1680ae 258 #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
bogdanm 86:04dd9b1680ae 259 ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
bogdanm 86:04dd9b1680ae 260 ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
bogdanm 86:04dd9b1680ae 261 ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
bogdanm 86:04dd9b1680ae 262 ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
bogdanm 86:04dd9b1680ae 263 ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
bogdanm 86:04dd9b1680ae 264 ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
bogdanm 86:04dd9b1680ae 265 ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
bogdanm 86:04dd9b1680ae 266
bogdanm 86:04dd9b1680ae 267 /**
bogdanm 86:04dd9b1680ae 268 * @}
bogdanm 86:04dd9b1680ae 269 */
bogdanm 86:04dd9b1680ae 270
bogdanm 86:04dd9b1680ae 271 /** @defgroup RCC_LSE_Config
bogdanm 86:04dd9b1680ae 272 * @{
bogdanm 86:04dd9b1680ae 273 */
bogdanm 86:04dd9b1680ae 274 #define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 275 #define RCC_LSE_ON ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 276 #define RCC_LSE_BYPASS ((uint32_t)0x00000005)
bogdanm 86:04dd9b1680ae 277
bogdanm 86:04dd9b1680ae 278 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
bogdanm 86:04dd9b1680ae 279 ((LSE) == RCC_LSE_BYPASS))
bogdanm 86:04dd9b1680ae 280 /**
bogdanm 86:04dd9b1680ae 281 * @}
bogdanm 86:04dd9b1680ae 282 */
bogdanm 86:04dd9b1680ae 283
bogdanm 86:04dd9b1680ae 284 /** @defgroup RCC_HSI_Config
bogdanm 86:04dd9b1680ae 285 * @{
bogdanm 86:04dd9b1680ae 286 */
bogdanm 86:04dd9b1680ae 287 #define RCC_HSI_OFF ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 288 #define RCC_HSI_ON ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 289
bogdanm 86:04dd9b1680ae 290 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
bogdanm 86:04dd9b1680ae 291 /**
bogdanm 86:04dd9b1680ae 292 * @}
bogdanm 86:04dd9b1680ae 293 */
bogdanm 86:04dd9b1680ae 294
bogdanm 86:04dd9b1680ae 295 /** @defgroup RCC_LSI_Config
bogdanm 86:04dd9b1680ae 296 * @{
bogdanm 86:04dd9b1680ae 297 */
bogdanm 86:04dd9b1680ae 298 #define RCC_LSI_OFF ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 299 #define RCC_LSI_ON ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 300
bogdanm 86:04dd9b1680ae 301 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
bogdanm 86:04dd9b1680ae 302 /**
bogdanm 86:04dd9b1680ae 303 * @}
bogdanm 86:04dd9b1680ae 304 */
bogdanm 86:04dd9b1680ae 305
bogdanm 86:04dd9b1680ae 306 /** @defgroup RCC_PLL_Config
bogdanm 86:04dd9b1680ae 307 * @{
bogdanm 86:04dd9b1680ae 308 */
bogdanm 86:04dd9b1680ae 309 #define RCC_PLL_NONE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 310 #define RCC_PLL_OFF ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 311 #define RCC_PLL_ON ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 312
bogdanm 86:04dd9b1680ae 313 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
bogdanm 86:04dd9b1680ae 314 /**
bogdanm 86:04dd9b1680ae 315 * @}
bogdanm 86:04dd9b1680ae 316 */
bogdanm 86:04dd9b1680ae 317
bogdanm 86:04dd9b1680ae 318 /** @defgroup RCC_PLL_Multiplication_Factor
bogdanm 86:04dd9b1680ae 319 * @{
bogdanm 86:04dd9b1680ae 320 */
bogdanm 86:04dd9b1680ae 321 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
bogdanm 86:04dd9b1680ae 322 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
bogdanm 86:04dd9b1680ae 323 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
bogdanm 86:04dd9b1680ae 324 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
bogdanm 86:04dd9b1680ae 325 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
bogdanm 86:04dd9b1680ae 326 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
bogdanm 86:04dd9b1680ae 327 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
bogdanm 86:04dd9b1680ae 328 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
bogdanm 86:04dd9b1680ae 329 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
bogdanm 86:04dd9b1680ae 330 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
bogdanm 86:04dd9b1680ae 331 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
bogdanm 86:04dd9b1680ae 332 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
bogdanm 86:04dd9b1680ae 333 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
bogdanm 86:04dd9b1680ae 334 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
bogdanm 86:04dd9b1680ae 335 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
bogdanm 86:04dd9b1680ae 336
bogdanm 86:04dd9b1680ae 337 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
bogdanm 86:04dd9b1680ae 338 ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
bogdanm 86:04dd9b1680ae 339 ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
bogdanm 86:04dd9b1680ae 340 ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
bogdanm 86:04dd9b1680ae 341 ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
bogdanm 86:04dd9b1680ae 342 ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
bogdanm 86:04dd9b1680ae 343 ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
bogdanm 86:04dd9b1680ae 344 ((MUL) == RCC_PLL_MUL16))
bogdanm 86:04dd9b1680ae 345 /**
bogdanm 86:04dd9b1680ae 346 * @}
bogdanm 86:04dd9b1680ae 347 */
bogdanm 86:04dd9b1680ae 348
bogdanm 86:04dd9b1680ae 349 /** @defgroup RCC_PLL_Clock_Source
bogdanm 86:04dd9b1680ae 350 * @{
bogdanm 86:04dd9b1680ae 351 */
bogdanm 86:04dd9b1680ae 352 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
bogdanm 86:04dd9b1680ae 353 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
bogdanm 86:04dd9b1680ae 354
bogdanm 86:04dd9b1680ae 355 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 356 ((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm 86:04dd9b1680ae 357 /**
bogdanm 86:04dd9b1680ae 358 * @}
bogdanm 86:04dd9b1680ae 359 */
bogdanm 86:04dd9b1680ae 360
bogdanm 86:04dd9b1680ae 361 /** @defgroup RCC_System_Clock_Type
bogdanm 86:04dd9b1680ae 362 * @{
bogdanm 86:04dd9b1680ae 363 */
bogdanm 86:04dd9b1680ae 364 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 365 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 366 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 367 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 368
bogdanm 86:04dd9b1680ae 369 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 370 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
bogdanm 86:04dd9b1680ae 371 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
bogdanm 86:04dd9b1680ae 372 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
bogdanm 86:04dd9b1680ae 373 /**
bogdanm 86:04dd9b1680ae 374 * @}
bogdanm 86:04dd9b1680ae 375 */
bogdanm 86:04dd9b1680ae 376
bogdanm 86:04dd9b1680ae 377 /** @defgroup RCC_System_Clock_Source
bogdanm 86:04dd9b1680ae 378 * @{
bogdanm 86:04dd9b1680ae 379 */
bogdanm 86:04dd9b1680ae 380 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm 86:04dd9b1680ae 381 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm 86:04dd9b1680ae 382 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm 86:04dd9b1680ae 383
bogdanm 86:04dd9b1680ae 384 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 385 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
bogdanm 86:04dd9b1680ae 386 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm 86:04dd9b1680ae 387 /**
bogdanm 86:04dd9b1680ae 388 * @}
bogdanm 86:04dd9b1680ae 389 */
bogdanm 86:04dd9b1680ae 390
bogdanm 86:04dd9b1680ae 391 /** @defgroup RCC_System_Clock_Source_Status
bogdanm 86:04dd9b1680ae 392 * @{
bogdanm 86:04dd9b1680ae 393 */
bogdanm 86:04dd9b1680ae 394 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
bogdanm 86:04dd9b1680ae 395 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
bogdanm 86:04dd9b1680ae 396 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
bogdanm 86:04dd9b1680ae 397
bogdanm 86:04dd9b1680ae 398 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
bogdanm 86:04dd9b1680ae 399 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
bogdanm 86:04dd9b1680ae 400 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)))
bogdanm 86:04dd9b1680ae 401 /**
bogdanm 86:04dd9b1680ae 402 * @}
bogdanm 86:04dd9b1680ae 403 */
bogdanm 86:04dd9b1680ae 404
bogdanm 86:04dd9b1680ae 405 /** @defgroup RCC_AHB_Clock_Source
bogdanm 86:04dd9b1680ae 406 * @{
bogdanm 86:04dd9b1680ae 407 */
bogdanm 86:04dd9b1680ae 408 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm 86:04dd9b1680ae 409 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm 86:04dd9b1680ae 410 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm 86:04dd9b1680ae 411 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm 86:04dd9b1680ae 412 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm 86:04dd9b1680ae 413 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm 86:04dd9b1680ae 414 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm 86:04dd9b1680ae 415 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm 86:04dd9b1680ae 416 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm 86:04dd9b1680ae 417
bogdanm 86:04dd9b1680ae 418 #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
bogdanm 86:04dd9b1680ae 419 ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
bogdanm 86:04dd9b1680ae 420 ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
bogdanm 86:04dd9b1680ae 421 ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
bogdanm 86:04dd9b1680ae 422 ((DIV) == RCC_SYSCLK_DIV512))
bogdanm 86:04dd9b1680ae 423 /**
bogdanm 86:04dd9b1680ae 424 * @}
bogdanm 86:04dd9b1680ae 425 */
bogdanm 86:04dd9b1680ae 426
bogdanm 86:04dd9b1680ae 427 /** @defgroup RCC_APB1_APB2_Clock_Source
bogdanm 86:04dd9b1680ae 428 * @{
bogdanm 86:04dd9b1680ae 429 */
bogdanm 86:04dd9b1680ae 430 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm 86:04dd9b1680ae 431 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm 86:04dd9b1680ae 432 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm 86:04dd9b1680ae 433 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm 86:04dd9b1680ae 434 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm 86:04dd9b1680ae 435
bogdanm 86:04dd9b1680ae 436 #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
bogdanm 86:04dd9b1680ae 437 ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
bogdanm 86:04dd9b1680ae 438 ((DIV) == RCC_HCLK_DIV16))
bogdanm 86:04dd9b1680ae 439 /**
bogdanm 86:04dd9b1680ae 440 * @}
bogdanm 86:04dd9b1680ae 441 */
bogdanm 86:04dd9b1680ae 442
bogdanm 86:04dd9b1680ae 443 /** @defgroup RCC_RTC_Clock_Source
bogdanm 86:04dd9b1680ae 444 * @{
bogdanm 86:04dd9b1680ae 445 */
bogdanm 86:04dd9b1680ae 446 #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
bogdanm 86:04dd9b1680ae 447 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
bogdanm 86:04dd9b1680ae 448 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
bogdanm 86:04dd9b1680ae 449 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
bogdanm 86:04dd9b1680ae 450
bogdanm 86:04dd9b1680ae 451 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
bogdanm 86:04dd9b1680ae 452 ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 453 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
bogdanm 86:04dd9b1680ae 454 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
bogdanm 86:04dd9b1680ae 455 /**
bogdanm 86:04dd9b1680ae 456 * @}
bogdanm 86:04dd9b1680ae 457 */
bogdanm 86:04dd9b1680ae 458
bogdanm 86:04dd9b1680ae 459 /** @defgroup RCC_USART2_Clock_Source
bogdanm 86:04dd9b1680ae 460 * @{
bogdanm 86:04dd9b1680ae 461 */
bogdanm 86:04dd9b1680ae 462 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm 86:04dd9b1680ae 463 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm 86:04dd9b1680ae 464 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm 86:04dd9b1680ae 465 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm 86:04dd9b1680ae 466
bogdanm 86:04dd9b1680ae 467 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
bogdanm 86:04dd9b1680ae 468 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 469 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 470 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 471 /**
bogdanm 86:04dd9b1680ae 472 * @}
bogdanm 86:04dd9b1680ae 473 */
bogdanm 86:04dd9b1680ae 474
bogdanm 86:04dd9b1680ae 475 /** @defgroup RCC_USART3_Clock_Source
bogdanm 86:04dd9b1680ae 476 * @{
bogdanm 86:04dd9b1680ae 477 */
bogdanm 86:04dd9b1680ae 478 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm 86:04dd9b1680ae 479 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm 86:04dd9b1680ae 480 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm 86:04dd9b1680ae 481 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm 86:04dd9b1680ae 482
bogdanm 86:04dd9b1680ae 483 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
bogdanm 86:04dd9b1680ae 484 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 485 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 486 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 487 /**
bogdanm 86:04dd9b1680ae 488 * @}
bogdanm 86:04dd9b1680ae 489 */
bogdanm 86:04dd9b1680ae 490
bogdanm 86:04dd9b1680ae 491 /** @defgroup RCC_I2C1_Clock_Source
bogdanm 86:04dd9b1680ae 492 * @{
bogdanm 86:04dd9b1680ae 493 */
bogdanm 86:04dd9b1680ae 494 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
bogdanm 86:04dd9b1680ae 495 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
bogdanm 86:04dd9b1680ae 496
bogdanm 86:04dd9b1680ae 497 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 498 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
bogdanm 86:04dd9b1680ae 499 /**
bogdanm 86:04dd9b1680ae 500 * @}
bogdanm 86:04dd9b1680ae 501 */
bogdanm 86:04dd9b1680ae 502
bogdanm 86:04dd9b1680ae 503 /** @defgroup RCC_MCOx_Index
bogdanm 86:04dd9b1680ae 504 * @{
bogdanm 86:04dd9b1680ae 505 */
bogdanm 86:04dd9b1680ae 506 #define RCC_MCO ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 507
bogdanm 86:04dd9b1680ae 508 #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
bogdanm 86:04dd9b1680ae 509 /**
bogdanm 86:04dd9b1680ae 510 * @}
bogdanm 86:04dd9b1680ae 511 */
bogdanm 86:04dd9b1680ae 512
bogdanm 86:04dd9b1680ae 513 /** @defgroup RCC_MCO_Clock_Source
bogdanm 86:04dd9b1680ae 514 * @{
bogdanm 86:04dd9b1680ae 515 */
bogdanm 86:04dd9b1680ae 516 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
bogdanm 86:04dd9b1680ae 517 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
bogdanm 86:04dd9b1680ae 518 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
bogdanm 86:04dd9b1680ae 519 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
bogdanm 86:04dd9b1680ae 520 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
bogdanm 86:04dd9b1680ae 521 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
bogdanm 86:04dd9b1680ae 522 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
bogdanm 86:04dd9b1680ae 523
bogdanm 86:04dd9b1680ae 524 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
bogdanm 86:04dd9b1680ae 525 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
bogdanm 86:04dd9b1680ae 526 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 527 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 528 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 529 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
bogdanm 86:04dd9b1680ae 530 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
bogdanm 86:04dd9b1680ae 531 /**
bogdanm 86:04dd9b1680ae 532 * @}
bogdanm 86:04dd9b1680ae 533 */
bogdanm 86:04dd9b1680ae 534
bogdanm 86:04dd9b1680ae 535 /** @defgroup RCC_Interrupt
bogdanm 86:04dd9b1680ae 536 * @{
bogdanm 86:04dd9b1680ae 537 */
bogdanm 86:04dd9b1680ae 538 #define RCC_IT_LSIRDY ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 539 #define RCC_IT_LSERDY ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 540 #define RCC_IT_HSIRDY ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 541 #define RCC_IT_HSERDY ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 542 #define RCC_IT_PLLRDY ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 543 #define RCC_IT_CSS ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 544 /**
bogdanm 86:04dd9b1680ae 545 * @}
bogdanm 86:04dd9b1680ae 546 */
bogdanm 86:04dd9b1680ae 547
bogdanm 86:04dd9b1680ae 548 /** @defgroup RCC_Flag
bogdanm 86:04dd9b1680ae 549 * Elements values convention: 0XXYYYYYb
bogdanm 86:04dd9b1680ae 550 * - YYYYY : Flag position in the register
bogdanm 86:04dd9b1680ae 551 * - XX : Register index
bogdanm 86:04dd9b1680ae 552 * - 01: CR register
bogdanm 86:04dd9b1680ae 553 * - 10: BDCR register
bogdanm 86:04dd9b1680ae 554 * - 11: CSR register
bogdanm 86:04dd9b1680ae 555 * @{
bogdanm 86:04dd9b1680ae 556 */
bogdanm 86:04dd9b1680ae 557 #define CR_REG_INDEX 1U
bogdanm 86:04dd9b1680ae 558 #define BDCR_REG_INDEX 2U
bogdanm 86:04dd9b1680ae 559 #define CSR_REG_INDEX 3U
bogdanm 86:04dd9b1680ae 560
bogdanm 86:04dd9b1680ae 561 /* Flags in the CR register */
bogdanm 86:04dd9b1680ae 562 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSIRDY))))
bogdanm 86:04dd9b1680ae 563 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSERDY))))
bogdanm 86:04dd9b1680ae 564 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_PLLRDY))))
bogdanm 86:04dd9b1680ae 565
bogdanm 86:04dd9b1680ae 566 /* Flags in the BDCR register */
bogdanm 86:04dd9b1680ae 567 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_BDCR_LSERDY))))
bogdanm 86:04dd9b1680ae 568
bogdanm 86:04dd9b1680ae 569 /* Flags in the CSR register */
bogdanm 86:04dd9b1680ae 570 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LSIRDY))))
bogdanm 86:04dd9b1680ae 571 #define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_RMVF))))
bogdanm 86:04dd9b1680ae 572 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_OBLRSTF))))
bogdanm 86:04dd9b1680ae 573 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PINRSTF))))
bogdanm 86:04dd9b1680ae 574 #define RCC_FLAG_PORRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PORRSTF))))
bogdanm 86:04dd9b1680ae 575 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_SFTRSTF))))
bogdanm 86:04dd9b1680ae 576 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_IWDGRSTF))))
bogdanm 86:04dd9b1680ae 577 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_WWDGRSTF))))
bogdanm 86:04dd9b1680ae 578 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LPWRRSTF))))
bogdanm 86:04dd9b1680ae 579 /**
bogdanm 86:04dd9b1680ae 580 * @}
bogdanm 86:04dd9b1680ae 581 */
bogdanm 86:04dd9b1680ae 582
bogdanm 86:04dd9b1680ae 583 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm 86:04dd9b1680ae 584 /**
bogdanm 86:04dd9b1680ae 585 * @}
bogdanm 86:04dd9b1680ae 586 */
bogdanm 86:04dd9b1680ae 587 /* Exported macro ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 588
bogdanm 86:04dd9b1680ae 589 /** @brief Enable or disable the AHB peripheral clock.
bogdanm 86:04dd9b1680ae 590 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 591 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 592 * using it.
bogdanm 86:04dd9b1680ae 593 */
bogdanm 86:04dd9b1680ae 594 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
bogdanm 86:04dd9b1680ae 595 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
bogdanm 86:04dd9b1680ae 596 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
bogdanm 86:04dd9b1680ae 597 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
bogdanm 86:04dd9b1680ae 598 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
bogdanm 86:04dd9b1680ae 599 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
bogdanm 86:04dd9b1680ae 600 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
bogdanm 86:04dd9b1680ae 601 #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
bogdanm 86:04dd9b1680ae 602 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
bogdanm 86:04dd9b1680ae 603 #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
bogdanm 86:04dd9b1680ae 604
bogdanm 86:04dd9b1680ae 605 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
bogdanm 86:04dd9b1680ae 606 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
bogdanm 86:04dd9b1680ae 607 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
bogdanm 86:04dd9b1680ae 608 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm 86:04dd9b1680ae 609 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
bogdanm 86:04dd9b1680ae 610 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
bogdanm 86:04dd9b1680ae 611 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
bogdanm 86:04dd9b1680ae 612 #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
bogdanm 86:04dd9b1680ae 613 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm 86:04dd9b1680ae 614 #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm 86:04dd9b1680ae 615
bogdanm 86:04dd9b1680ae 616 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 86:04dd9b1680ae 617 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 618 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 619 * using it.
bogdanm 86:04dd9b1680ae 620 */
bogdanm 86:04dd9b1680ae 621 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
bogdanm 86:04dd9b1680ae 622 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
bogdanm 86:04dd9b1680ae 623 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
bogdanm 86:04dd9b1680ae 624 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
bogdanm 86:04dd9b1680ae 625 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
bogdanm 86:04dd9b1680ae 626 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
bogdanm 86:04dd9b1680ae 627 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
bogdanm 86:04dd9b1680ae 628 #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC1EN))
bogdanm 86:04dd9b1680ae 629
bogdanm 86:04dd9b1680ae 630 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm 86:04dd9b1680ae 631 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm 86:04dd9b1680ae 632 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm 86:04dd9b1680ae 633 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm 86:04dd9b1680ae 634 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm 86:04dd9b1680ae 635 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm 86:04dd9b1680ae 636 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm 86:04dd9b1680ae 637 #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
bogdanm 86:04dd9b1680ae 638
bogdanm 86:04dd9b1680ae 639 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 86:04dd9b1680ae 640 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 641 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 642 * using it.
bogdanm 86:04dd9b1680ae 643 */
bogdanm 86:04dd9b1680ae 644 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
bogdanm 86:04dd9b1680ae 645 #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
bogdanm 86:04dd9b1680ae 646 #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
bogdanm 86:04dd9b1680ae 647 #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
bogdanm 86:04dd9b1680ae 648 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
bogdanm 86:04dd9b1680ae 649
bogdanm 86:04dd9b1680ae 650 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm 86:04dd9b1680ae 651 #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm 86:04dd9b1680ae 652 #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
bogdanm 86:04dd9b1680ae 653 #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
bogdanm 86:04dd9b1680ae 654 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm 86:04dd9b1680ae 655
bogdanm 86:04dd9b1680ae 656 /** @brief Force or release AHB peripheral reset.
bogdanm 86:04dd9b1680ae 657 */
bogdanm 86:04dd9b1680ae 658 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 659 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
bogdanm 86:04dd9b1680ae 660 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
bogdanm 86:04dd9b1680ae 661 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
bogdanm 86:04dd9b1680ae 662 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
bogdanm 86:04dd9b1680ae 663 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
bogdanm 86:04dd9b1680ae 664 #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
bogdanm 86:04dd9b1680ae 665
bogdanm 86:04dd9b1680ae 666 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
bogdanm 86:04dd9b1680ae 667 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
bogdanm 86:04dd9b1680ae 668 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
bogdanm 86:04dd9b1680ae 669 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
bogdanm 86:04dd9b1680ae 670 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm 86:04dd9b1680ae 671 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
bogdanm 86:04dd9b1680ae 672 #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm 86:04dd9b1680ae 673
bogdanm 86:04dd9b1680ae 674 /** @brief Force or release APB1 peripheral reset.
bogdanm 86:04dd9b1680ae 675 */
bogdanm 86:04dd9b1680ae 676 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 677 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
bogdanm 86:04dd9b1680ae 678 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
bogdanm 86:04dd9b1680ae 679 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
bogdanm 86:04dd9b1680ae 680 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
bogdanm 86:04dd9b1680ae 681 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
bogdanm 86:04dd9b1680ae 682 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
bogdanm 86:04dd9b1680ae 683 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 86:04dd9b1680ae 684 #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
bogdanm 86:04dd9b1680ae 685
bogdanm 86:04dd9b1680ae 686 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm 86:04dd9b1680ae 687 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm 86:04dd9b1680ae 688 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm 86:04dd9b1680ae 689 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm 86:04dd9b1680ae 690 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm 86:04dd9b1680ae 691 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm 86:04dd9b1680ae 692 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm 86:04dd9b1680ae 693 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm 86:04dd9b1680ae 694 #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
bogdanm 86:04dd9b1680ae 695
bogdanm 86:04dd9b1680ae 696 /** @brief Force or release APB2 peripheral reset.
bogdanm 86:04dd9b1680ae 697 */
bogdanm 86:04dd9b1680ae 698 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 699 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
bogdanm 86:04dd9b1680ae 700 #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
bogdanm 86:04dd9b1680ae 701 #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
bogdanm 86:04dd9b1680ae 702 #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
bogdanm 86:04dd9b1680ae 703 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
bogdanm 86:04dd9b1680ae 704
bogdanm 86:04dd9b1680ae 705 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm 86:04dd9b1680ae 706 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm 86:04dd9b1680ae 707 #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm 86:04dd9b1680ae 708 #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
bogdanm 86:04dd9b1680ae 709 #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
bogdanm 86:04dd9b1680ae 710 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm 86:04dd9b1680ae 711
bogdanm 86:04dd9b1680ae 712 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 86:04dd9b1680ae 713 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 714 * It is used (enabled by hardware) as system clock source after startup
bogdanm 86:04dd9b1680ae 715 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm 86:04dd9b1680ae 716 * of the HSE used directly or indirectly as system clock (if the Clock
bogdanm 86:04dd9b1680ae 717 * Security System CSS is enabled).
bogdanm 86:04dd9b1680ae 718 * @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm 86:04dd9b1680ae 719 * you have to select another source of the system clock then stop the HSI.
bogdanm 86:04dd9b1680ae 720 * @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm 86:04dd9b1680ae 721 * flag to be set indicating that HSI clock is stable and can be used as
bogdanm 86:04dd9b1680ae 722 * system clock source.
bogdanm 86:04dd9b1680ae 723 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 86:04dd9b1680ae 724 * clock cycles.
bogdanm 86:04dd9b1680ae 725 */
bogdanm 86:04dd9b1680ae 726 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)CR_HSION_BB = ENABLE)
bogdanm 86:04dd9b1680ae 727 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)CR_HSION_BB = DISABLE)
bogdanm 86:04dd9b1680ae 728
bogdanm 86:04dd9b1680ae 729
bogdanm 86:04dd9b1680ae 730 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm 86:04dd9b1680ae 731 * @note The calibration is used to compensate for the variations in voltage
bogdanm 86:04dd9b1680ae 732 * and temperature that influence the frequency of the internal HSI RC.
bogdanm 86:04dd9b1680ae 733 * @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm 86:04dd9b1680ae 734 * This parameter must be a number between 0 and 0x1F.
bogdanm 86:04dd9b1680ae 735 */
bogdanm 86:04dd9b1680ae 736 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
bogdanm 86:04dd9b1680ae 737 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))
bogdanm 86:04dd9b1680ae 738
bogdanm 86:04dd9b1680ae 739
bogdanm 86:04dd9b1680ae 740 /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 86:04dd9b1680ae 741 * @note After enabling the LSI, the application software should wait on
bogdanm 86:04dd9b1680ae 742 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 86:04dd9b1680ae 743 * be used to clock the IWDG and/or the RTC.
bogdanm 86:04dd9b1680ae 744 * @note LSI can not be disabled if the IWDG is running.
bogdanm 86:04dd9b1680ae 745 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 86:04dd9b1680ae 746 * clock cycles.
bogdanm 86:04dd9b1680ae 747 */
bogdanm 86:04dd9b1680ae 748 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)CSR_LSION_BB = ENABLE)
bogdanm 86:04dd9b1680ae 749 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)CSR_LSION_BB = DISABLE)
bogdanm 86:04dd9b1680ae 750
bogdanm 86:04dd9b1680ae 751 /**
bogdanm 86:04dd9b1680ae 752 * @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm 86:04dd9b1680ae 753 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 86:04dd9b1680ae 754 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 86:04dd9b1680ae 755 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 86:04dd9b1680ae 756 * @note HSE state can not be changed if it is used directly or through the
bogdanm 86:04dd9b1680ae 757 * PLL as system clock. In this case, you have to select another source
bogdanm 86:04dd9b1680ae 758 * of the system clock then change the HSE state (ex. disable it).
bogdanm 86:04dd9b1680ae 759 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 760 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
bogdanm 86:04dd9b1680ae 761 * was previously enabled you have to enable it again after calling this
bogdanm 86:04dd9b1680ae 762 * function.
bogdanm 86:04dd9b1680ae 763 * @param __STATE__: specifies the new state of the HSE.
bogdanm 86:04dd9b1680ae 764 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 765 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 86:04dd9b1680ae 766 * 6 HSE oscillator clock cycles.
bogdanm 86:04dd9b1680ae 767 * @arg RCC_HSE_ON: turn ON the HSE oscillator
bogdanm 86:04dd9b1680ae 768 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
bogdanm 86:04dd9b1680ae 769 */
bogdanm 86:04dd9b1680ae 770 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)CR_BYTE2_ADDRESS = (__STATE__))
bogdanm 86:04dd9b1680ae 771
bogdanm 86:04dd9b1680ae 772 /**
bogdanm 86:04dd9b1680ae 773 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
bogdanm 86:04dd9b1680ae 774 * @note Predivision factor can not be changed if PLL is used as system clock
bogdanm 86:04dd9b1680ae 775 * In this case, you have to select another source of the system clock, disable the PLL and
bogdanm 86:04dd9b1680ae 776 * then change the HSE predivision factor.
bogdanm 86:04dd9b1680ae 777 * @param __HSEPredivValue__: specifies the division value applied to HSE.
bogdanm 86:04dd9b1680ae 778 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
bogdanm 86:04dd9b1680ae 779 */
bogdanm 86:04dd9b1680ae 780 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
bogdanm 86:04dd9b1680ae 781 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
bogdanm 86:04dd9b1680ae 782
bogdanm 86:04dd9b1680ae 783 /**
bogdanm 86:04dd9b1680ae 784 * @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm 86:04dd9b1680ae 785 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 86:04dd9b1680ae 786 * this domain after reset, you have to enable write access using
bogdanm 86:04dd9b1680ae 787 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 86:04dd9b1680ae 788 * (to be done once after reset).
bogdanm 86:04dd9b1680ae 789 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 86:04dd9b1680ae 790 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 86:04dd9b1680ae 791 * is stable and can be used to clock the RTC.
bogdanm 86:04dd9b1680ae 792 * @param __STATE__: specifies the new state of the LSE.
bogdanm 86:04dd9b1680ae 793 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 794 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 86:04dd9b1680ae 795 * 6 LSE oscillator clock cycles.
bogdanm 86:04dd9b1680ae 796 * @arg RCC_LSE_ON: turn ON the LSE oscillator
bogdanm 86:04dd9b1680ae 797 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
bogdanm 86:04dd9b1680ae 798 */
bogdanm 86:04dd9b1680ae 799 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm 86:04dd9b1680ae 800 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
bogdanm 86:04dd9b1680ae 801
bogdanm 86:04dd9b1680ae 802 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
bogdanm 86:04dd9b1680ae 803 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm 86:04dd9b1680ae 804 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 805 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm 86:04dd9b1680ae 806 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm 86:04dd9b1680ae 807 */
bogdanm 86:04dd9b1680ae 808 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm 86:04dd9b1680ae 809 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
bogdanm 86:04dd9b1680ae 810
bogdanm 86:04dd9b1680ae 811 /** @brief Macro to get the I2C1 clock source.
bogdanm 86:04dd9b1680ae 812 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 813 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm 86:04dd9b1680ae 814 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm 86:04dd9b1680ae 815 */
bogdanm 86:04dd9b1680ae 816 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
bogdanm 86:04dd9b1680ae 817
bogdanm 86:04dd9b1680ae 818 /** @brief Macro to configure the USART1 clock (USART1CLK).
bogdanm 86:04dd9b1680ae 819 * @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm 86:04dd9b1680ae 820 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 821 * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
bogdanm 86:04dd9b1680ae 822 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm 86:04dd9b1680ae 823 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm 86:04dd9b1680ae 824 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm 86:04dd9b1680ae 825 */
bogdanm 86:04dd9b1680ae 826 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm 86:04dd9b1680ae 827 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
bogdanm 86:04dd9b1680ae 828
bogdanm 86:04dd9b1680ae 829 /** @brief Macro to get the USART1 clock source.
bogdanm 86:04dd9b1680ae 830 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 831 * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
bogdanm 86:04dd9b1680ae 832 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm 86:04dd9b1680ae 833 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm 86:04dd9b1680ae 834 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm 86:04dd9b1680ae 835 */
bogdanm 86:04dd9b1680ae 836 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
bogdanm 86:04dd9b1680ae 837
bogdanm 86:04dd9b1680ae 838 /** @brief Macro to configure the USART2 clock (USART2CLK).
bogdanm 86:04dd9b1680ae 839 * @param __USART2CLKSource__: specifies the USART2 clock source.
bogdanm 86:04dd9b1680ae 840 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 841 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm 86:04dd9b1680ae 842 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm 86:04dd9b1680ae 843 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm 86:04dd9b1680ae 844 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm 86:04dd9b1680ae 845 */
bogdanm 86:04dd9b1680ae 846 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
bogdanm 86:04dd9b1680ae 847 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
bogdanm 86:04dd9b1680ae 848
bogdanm 86:04dd9b1680ae 849 /** @brief Macro to get the USART2 clock source.
bogdanm 86:04dd9b1680ae 850 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 851 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm 86:04dd9b1680ae 852 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm 86:04dd9b1680ae 853 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm 86:04dd9b1680ae 854 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm 86:04dd9b1680ae 855 */
bogdanm 86:04dd9b1680ae 856 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
bogdanm 86:04dd9b1680ae 857
bogdanm 86:04dd9b1680ae 858 /** @brief Macro to configure the USART3 clock (USART3CLK).
bogdanm 86:04dd9b1680ae 859 * @param __USART3CLKSource__: specifies the USART3 clock source.
bogdanm 86:04dd9b1680ae 860 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 861 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm 86:04dd9b1680ae 862 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm 86:04dd9b1680ae 863 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm 86:04dd9b1680ae 864 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm 86:04dd9b1680ae 865 */
bogdanm 86:04dd9b1680ae 866 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
bogdanm 86:04dd9b1680ae 867 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
bogdanm 86:04dd9b1680ae 868
bogdanm 86:04dd9b1680ae 869 /** @brief Macro to get the USART3 clock source.
bogdanm 86:04dd9b1680ae 870 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 871 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm 86:04dd9b1680ae 872 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm 86:04dd9b1680ae 873 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm 86:04dd9b1680ae 874 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm 86:04dd9b1680ae 875 */
bogdanm 86:04dd9b1680ae 876 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
bogdanm 86:04dd9b1680ae 877
bogdanm 86:04dd9b1680ae 878 /** @brief Macros to enable or disable the the RTC clock.
bogdanm 86:04dd9b1680ae 879 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 86:04dd9b1680ae 880 */
bogdanm 86:04dd9b1680ae 881 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = ENABLE)
bogdanm 86:04dd9b1680ae 882 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = DISABLE)
bogdanm 86:04dd9b1680ae 883
bogdanm 86:04dd9b1680ae 884 /** @brief Macro to configure the RTC clock (RTCCLK).
bogdanm 86:04dd9b1680ae 885 * @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm 86:04dd9b1680ae 886 * access is denied to this domain after reset, you have to enable write
bogdanm 86:04dd9b1680ae 887 * access using the Power Backup Access macro before to configure
bogdanm 86:04dd9b1680ae 888 * the RTC clock source (to be done once after reset).
bogdanm 86:04dd9b1680ae 889 * @note Once the RTC clock is configured it can't be changed unless the
bogdanm 86:04dd9b1680ae 890 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm 86:04dd9b1680ae 891 * a Power On Reset (POR).
bogdanm 86:04dd9b1680ae 892 * @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm 86:04dd9b1680ae 893 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 894 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
bogdanm 86:04dd9b1680ae 895 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm 86:04dd9b1680ae 896 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm 86:04dd9b1680ae 897 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
bogdanm 86:04dd9b1680ae 898 *
bogdanm 86:04dd9b1680ae 899 * @note If the LSE is used as RTC clock source, the RTC continues to
bogdanm 86:04dd9b1680ae 900 * work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm 86:04dd9b1680ae 901 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
bogdanm 86:04dd9b1680ae 902 * the RTC cannot be used in STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 903 * @note The system must always be configured so as to get a PCLK frequency greater than or
bogdanm 86:04dd9b1680ae 904 * equal to the RTCCLK frequency for a proper operation of the RTC.
bogdanm 86:04dd9b1680ae 905 */
bogdanm 86:04dd9b1680ae 906 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
bogdanm 86:04dd9b1680ae 907 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
bogdanm 86:04dd9b1680ae 908
bogdanm 86:04dd9b1680ae 909 /** @brief Macro to get the RTC clock source.
bogdanm 86:04dd9b1680ae 910 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 911 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
bogdanm 86:04dd9b1680ae 912 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm 86:04dd9b1680ae 913 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm 86:04dd9b1680ae 914 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
bogdanm 86:04dd9b1680ae 915 */
bogdanm 86:04dd9b1680ae 916 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
bogdanm 86:04dd9b1680ae 917
bogdanm 86:04dd9b1680ae 918 /** @brief Macro to force or release the Backup domain reset.
bogdanm 86:04dd9b1680ae 919 * @note These macros reset the RTC peripheral (including the backup registers)
bogdanm 86:04dd9b1680ae 920 * and the RTC clock source selection in RCC_CSR register.
bogdanm 86:04dd9b1680ae 921 * @note The BKPSRAM is not affected by this reset.
bogdanm 86:04dd9b1680ae 922 */
bogdanm 86:04dd9b1680ae 923 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)BDCR_BDRST_BB = ENABLE)
bogdanm 86:04dd9b1680ae 924 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)BDCR_BDRST_BB = DISABLE)
bogdanm 86:04dd9b1680ae 925
bogdanm 86:04dd9b1680ae 926 /** @brief Macro to enable or disable the PLL.
bogdanm 86:04dd9b1680ae 927 * @note After enabling the PLL, the application software should wait on
bogdanm 86:04dd9b1680ae 928 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 86:04dd9b1680ae 929 * be used as system clock source.
bogdanm 86:04dd9b1680ae 930 * @note The PLL can not be disabled if it is used as system clock source
bogdanm 86:04dd9b1680ae 931 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 932 */
bogdanm 86:04dd9b1680ae 933 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)CR_PLLON_BB = ENABLE)
bogdanm 86:04dd9b1680ae 934 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)CR_PLLON_BB = DISABLE)
bogdanm 86:04dd9b1680ae 935
bogdanm 86:04dd9b1680ae 936 /** @brief Macro to configure the PLL clock source and multiplication factor.
bogdanm 86:04dd9b1680ae 937 * @note This macro must be used only when the PLL is disabled.
bogdanm 86:04dd9b1680ae 938 *
bogdanm 86:04dd9b1680ae 939 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm 86:04dd9b1680ae 940 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 941 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 86:04dd9b1680ae 942 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm 86:04dd9b1680ae 943 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
bogdanm 86:04dd9b1680ae 944 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
bogdanm 86:04dd9b1680ae 945 *
bogdanm 86:04dd9b1680ae 946 */
bogdanm 86:04dd9b1680ae 947 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
bogdanm 86:04dd9b1680ae 948 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
bogdanm 86:04dd9b1680ae 949
bogdanm 86:04dd9b1680ae 950
bogdanm 86:04dd9b1680ae 951 /** @brief Macro to get the clock source used as system clock.
bogdanm 86:04dd9b1680ae 952 * @retval The clock source used as system clock.
bogdanm 86:04dd9b1680ae 953 * The returned value can be one of the following value:
bogdanm 86:04dd9b1680ae 954 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
bogdanm 86:04dd9b1680ae 955 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
bogdanm 86:04dd9b1680ae 956 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
bogdanm 86:04dd9b1680ae 957 */
bogdanm 86:04dd9b1680ae 958 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
bogdanm 86:04dd9b1680ae 959
bogdanm 86:04dd9b1680ae 960 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 86:04dd9b1680ae 961 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 86:04dd9b1680ae 962 * of the following:
bogdanm 86:04dd9b1680ae 963 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 86:04dd9b1680ae 964 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 86:04dd9b1680ae 965 */
bogdanm 86:04dd9b1680ae 966 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
bogdanm 86:04dd9b1680ae 967
bogdanm 86:04dd9b1680ae 968 /** @defgroup RCC_Flags_Interrupts_Management
bogdanm 86:04dd9b1680ae 969 * @brief macros to manage the specified RCC Flags and interrupts.
bogdanm 86:04dd9b1680ae 970 * @{
bogdanm 86:04dd9b1680ae 971 */
bogdanm 86:04dd9b1680ae 972
bogdanm 86:04dd9b1680ae 973 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
bogdanm 86:04dd9b1680ae 974 * the selected interrupts.).
bogdanm 86:04dd9b1680ae 975 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 86:04dd9b1680ae 976 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 977 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
bogdanm 86:04dd9b1680ae 978 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
bogdanm 86:04dd9b1680ae 979 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
bogdanm 86:04dd9b1680ae 980 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
bogdanm 86:04dd9b1680ae 981 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
bogdanm 86:04dd9b1680ae 982 */
bogdanm 86:04dd9b1680ae 983 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 984
bogdanm 86:04dd9b1680ae 985 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
bogdanm 86:04dd9b1680ae 986 * the selected interrupts.).
bogdanm 86:04dd9b1680ae 987 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 86:04dd9b1680ae 988 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 989 * @arg RCC_IT_LSIRDYIE: LSI ready interrupt enable
bogdanm 86:04dd9b1680ae 990 * @arg RCC_IT_LSERDYIE: LSE ready interrupt enable
bogdanm 86:04dd9b1680ae 991 * @arg RCC_IT_HSIRDYIE: HSI ready interrupt enable
bogdanm 86:04dd9b1680ae 992 * @arg RCC_IT_HSERDYIE: HSE ready interrupt enable
bogdanm 86:04dd9b1680ae 993 * @arg RCC_IT_PLLRDYIE: PLL ready interrupt enable
bogdanm 86:04dd9b1680ae 994 */
bogdanm 86:04dd9b1680ae 995 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 996
bogdanm 86:04dd9b1680ae 997 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
bogdanm 86:04dd9b1680ae 998 * bits to clear the selected interrupt pending bits.
bogdanm 86:04dd9b1680ae 999 * @param __IT__: specifies the interrupt pending bit to clear.
bogdanm 86:04dd9b1680ae 1000 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1001 * @arg RCC_IT_LSIRDYC: LSI ready interrupt clear
bogdanm 86:04dd9b1680ae 1002 * @arg RCC_IT_LSERDYC: LSE ready interrupt clear
bogdanm 86:04dd9b1680ae 1003 * @arg RCC_IT_HSIRDYC: HSI ready interrupt clear
bogdanm 86:04dd9b1680ae 1004 * @arg RCC_IT_HSERDYC: HSE ready interrupt clear
bogdanm 86:04dd9b1680ae 1005 * @arg RCC_IT_PLLRDYC: PLL ready interrupt clear
bogdanm 86:04dd9b1680ae 1006 * @arg RCC_IT_CSSC: Clock Security System interrupt clear
bogdanm 86:04dd9b1680ae 1007 */
bogdanm 86:04dd9b1680ae 1008 #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)CIR_BYTE2_ADDRESS = (__IT__))
bogdanm 86:04dd9b1680ae 1009
bogdanm 86:04dd9b1680ae 1010 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 86:04dd9b1680ae 1011 * @param __IT__: specifies the RCC interrupt source to check.
bogdanm 86:04dd9b1680ae 1012 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1013 * @arg RCC_IT_LSIRDYF: LSI ready interrupt flag
bogdanm 86:04dd9b1680ae 1014 * @arg RCC_IT_LSERDYF: LSE ready interrupt flag
bogdanm 86:04dd9b1680ae 1015 * @arg RCC_IT_HSIRDYF: HSI ready interrupt flag
bogdanm 86:04dd9b1680ae 1016 * @arg RCC_IT_HSERDYF: HSE ready interrupt flag
bogdanm 86:04dd9b1680ae 1017 * @arg RCC_IT_PLLRDYF: PLL ready interrupt flag
bogdanm 86:04dd9b1680ae 1018 * @arg RCC_IT_CSSF: Clock Security System interrupt flag
bogdanm 86:04dd9b1680ae 1019 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 1020 */
bogdanm 86:04dd9b1680ae 1021 #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
bogdanm 86:04dd9b1680ae 1022
bogdanm 86:04dd9b1680ae 1023 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
bogdanm 86:04dd9b1680ae 1024 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm 86:04dd9b1680ae 1025 */
bogdanm 86:04dd9b1680ae 1026 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)CSR_RMVF_BB = ENABLE)
bogdanm 86:04dd9b1680ae 1027
bogdanm 86:04dd9b1680ae 1028 /** @brief Check RCC flag is set or not.
bogdanm 86:04dd9b1680ae 1029 * @param __FLAG__: specifies the flag to check.
bogdanm 86:04dd9b1680ae 1030 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1031 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
bogdanm 86:04dd9b1680ae 1032 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm 86:04dd9b1680ae 1033 * @arg RCC_FLAG_PLLRDY: PLL clock ready
bogdanm 86:04dd9b1680ae 1034 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm 86:04dd9b1680ae 1035 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
bogdanm 86:04dd9b1680ae 1036 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
bogdanm 86:04dd9b1680ae 1037 * @arg RCC_FLAG_PINRST: Pin reset
bogdanm 86:04dd9b1680ae 1038 * @arg RCC_FLAG_PORRST: POR/PDR reset
bogdanm 86:04dd9b1680ae 1039 * @arg RCC_FLAG_SFTRST: Software reset
bogdanm 86:04dd9b1680ae 1040 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm 86:04dd9b1680ae 1041 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm 86:04dd9b1680ae 1042 * @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm 86:04dd9b1680ae 1043 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 1044 */
bogdanm 86:04dd9b1680ae 1045 #define RCC_FLAG_MASK ((uint32_t)0x0000001F)
bogdanm 86:04dd9b1680ae 1046 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
bogdanm 86:04dd9b1680ae 1047 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
bogdanm 86:04dd9b1680ae 1048 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm 86:04dd9b1680ae 1049
bogdanm 86:04dd9b1680ae 1050
bogdanm 86:04dd9b1680ae 1051 /**
bogdanm 86:04dd9b1680ae 1052 * @}
bogdanm 86:04dd9b1680ae 1053 */
bogdanm 86:04dd9b1680ae 1054
bogdanm 86:04dd9b1680ae 1055 /* Include RCC HAL Extension module */
bogdanm 86:04dd9b1680ae 1056 #include "stm32f3xx_hal_rcc_ex.h"
bogdanm 86:04dd9b1680ae 1057
bogdanm 86:04dd9b1680ae 1058 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 1059
bogdanm 86:04dd9b1680ae 1060 /* Initialization and de-initialization functions ***************************/
bogdanm 86:04dd9b1680ae 1061 void HAL_RCC_DeInit(void);
bogdanm 86:04dd9b1680ae 1062 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 86:04dd9b1680ae 1063 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm 86:04dd9b1680ae 1064
bogdanm 86:04dd9b1680ae 1065 /* Peripheral Control functions *********************************************/
bogdanm 86:04dd9b1680ae 1066 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm 86:04dd9b1680ae 1067 void HAL_RCC_EnableCSS(void);
bogdanm 86:04dd9b1680ae 1068 void HAL_RCC_DisableCSS(void);
bogdanm 86:04dd9b1680ae 1069 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 86:04dd9b1680ae 1070 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 86:04dd9b1680ae 1071 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 86:04dd9b1680ae 1072 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 86:04dd9b1680ae 1073 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 86:04dd9b1680ae 1074 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 86:04dd9b1680ae 1075
bogdanm 86:04dd9b1680ae 1076 /* CSS NMI IRQ handler */
bogdanm 86:04dd9b1680ae 1077 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 86:04dd9b1680ae 1078
bogdanm 86:04dd9b1680ae 1079 /* User Callbacks in non blocking mode (IT mode) */
bogdanm 86:04dd9b1680ae 1080 void HAL_RCC_CCSCallback(void);
bogdanm 86:04dd9b1680ae 1081
bogdanm 86:04dd9b1680ae 1082 /**
bogdanm 86:04dd9b1680ae 1083 * @}
bogdanm 86:04dd9b1680ae 1084 */
bogdanm 86:04dd9b1680ae 1085
bogdanm 86:04dd9b1680ae 1086 /**
bogdanm 86:04dd9b1680ae 1087 * @}
bogdanm 86:04dd9b1680ae 1088 */
bogdanm 86:04dd9b1680ae 1089
bogdanm 86:04dd9b1680ae 1090 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 1091 }
bogdanm 86:04dd9b1680ae 1092 #endif
bogdanm 86:04dd9b1680ae 1093
bogdanm 86:04dd9b1680ae 1094 #endif /* __STM32F3xx_HAL_RCC_H */
bogdanm 86:04dd9b1680ae 1095
bogdanm 86:04dd9b1680ae 1096 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/