frederic blanc / QEI_hw_m

control speed motor PID QEIHW MOTOR

qeihw.h@0:37964304d479, 2012-07-18 (annotated)

Committer:
fblanc
Date:
Wed Jul 18 13:06:05 2012 +0000
Revision:
0:37964304d479
[mbed] converted /Aubaine/QEI_hw_m

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fblanc 0:37964304d479 1 /* mbed Library - QEIhw
fblanc 0:37964304d479 2 * Copyright (c) 2010, hball
fblanc 0:37964304d479 3 * released under MIT license http://mbed.org/licence/mit
fblanc 0:37964304d479 4 */
fblanc 0:37964304d479 5
fblanc 0:37964304d479 6 /***********************************************************************//**
fblanc 0:37964304d479 7 * @file qeihw.h
fblanc 0:37964304d479 8 * @brief Header file for the qeihw driver. Adapted from the CMSIS
fblanc 0:37964304d479 9 * header, lpc17xx_qei.h, v 2.0
fblanc 0:37964304d479 10 * @version 0.0
fblanc 0:37964304d479 11 * @date 10 Dec 2010
fblanc 0:37964304d479 12 * @author hb
fblanc 0:37964304d479 13 **************************************************************************/
fblanc 0:37964304d479 14
fblanc 0:37964304d479 15
fblanc 0:37964304d479 16 #ifndef MBED_QEIHW_H
fblanc 0:37964304d479 17 #define MBED_QEIHW_H
fblanc 0:37964304d479 18
fblanc 0:37964304d479 19 /* Includes ------------------------------------------------------------------- */
fblanc 0:37964304d479 20 #include "mbed.h"
fblanc 0:37964304d479 21
fblanc 0:37964304d479 22
fblanc 0:37964304d479 23 /* Public Types --------------------------------------------------------------- */
fblanc 0:37964304d479 24
fblanc 0:37964304d479 25 /* Flag Status type definition */
fblanc 0:37964304d479 26 typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
fblanc 0:37964304d479 27
fblanc 0:37964304d479 28 /* Functional State Definition */
fblanc 0:37964304d479 29 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
fblanc 0:37964304d479 30
fblanc 0:37964304d479 31
fblanc 0:37964304d479 32 /* Other definitions */
fblanc 0:37964304d479 33 #define XTAL_FREQ 12000000
fblanc 0:37964304d479 34
fblanc 0:37964304d479 35 /* Public Functions ----------------------------------------------------------- */
fblanc 0:37964304d479 36 /** @defgroup QEI_Public_Functions QEI Public Functions
fblanc 0:37964304d479 37 */
fblanc 0:37964304d479 38
fblanc 0:37964304d479 39 /** QEI hardware interface class
fblanc 0:37964304d479 40 * Requires mbed hardware modification: connect
fblanc 0:37964304d479 41 * encoder PhA to p1.20, and PhB to p1.23.
fblanc 0:37964304d479 42 *
fblanc 0:37964304d479 43 * Example:
fblanc 0:37964304d479 44 * @code
fblanc 0:37964304d479 45 * // Display changes in encoder position and direction
fblanc 0:37964304d479 46 #include "mbed.h"
fblanc 0:37964304d479 47 * #include "qeihw.h"
fblanc 0:37964304d479 48 *
fblanc 0:37964304d479 49 * DigitalOut led1(LED1);
fblanc 0:37964304d479 50 * DigitalOut led3(LED3);
fblanc 0:37964304d479 51 * QEIHW qei(QEI_DIRINV_NONE, QEI_SIGNALMODE_QUAD, QEI_CAPMODE_2X, QEI_INVINX_NONE );
fblanc 0:37964304d479 52 *
fblanc 0:37964304d479 53 * int main() {
fblanc 0:37964304d479 54 * int32_t temp, position = 0;
fblanc 0:37964304d479 55 * qei.SetDigiFilter(480UL);
fblanc 0:37964304d479 56 * qei.SetMaxPosition(0xFFFFFFFF);
fblanc 0:37964304d479 57 *
fblanc 0:37964304d479 58 * while(1) {
fblanc 0:37964304d479 59 * while(position == (temp = qei.GetPosition()) );
fblanc 0:37964304d479 60 * position = temp;
fblanc 0:37964304d479 61 * printf("New position = %d.\r\n", temp);
fblanc 0:37964304d479 62 * led1 = qei.Direction() == SET ? 1 : 0;
fblanc 0:37964304d479 63 * led3 = !led1;
fblanc 0:37964304d479 64 * wait(0.1);
fblanc 0:37964304d479 65 * }
fblanc 0:37964304d479 66 * }
fblanc 0:37964304d479 67 * @endcode
fblanc 0:37964304d479 68 */
fblanc 0:37964304d479 69
fblanc 0:37964304d479 70 class QEIHW {
fblanc 0:37964304d479 71 public:
fblanc 0:37964304d479 72
fblanc 0:37964304d479 73 /** Create a QEI object and configure it
fblanc 0:37964304d479 74 *
fblanc 0:37964304d479 75 * @param _dirinv Direction invert. When = 1, complements the QEICONF register DIR bit
fblanc 0:37964304d479 76 * @param _sigmode Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock
fblanc 0:37964304d479 77 * @param _capmode Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode).
fblanc 0:37964304d479 78 * @param _invinx Invert index. When = 1, inverts the sense of the index signal
fblanc 0:37964304d479 79 */
fblanc 0:37964304d479 80 QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx);
fblanc 0:37964304d479 81
fblanc 0:37964304d479 82 /** Resets value for each type of QEI value, such as velocity, position, etc.
fblanc 0:37964304d479 83 *
fblanc 0:37964304d479 84 * @param[in] ulResetType QEI Reset Type, should be one of the following:
fblanc 0:37964304d479 85 * - QEI_RESET_POS: Reset Position Counter
fblanc 0:37964304d479 86 * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal
fblanc 0:37964304d479 87 * - QEI_RESET_VEL: Reset Velocity
fblanc 0:37964304d479 88 * - QEI_RESET_IDX: Reset Index Counter
fblanc 0:37964304d479 89 */
fblanc 0:37964304d479 90 void Reset(uint32_t ulResetType);
fblanc 0:37964304d479 91
fblanc 0:37964304d479 92 /** Powers down the QEI block, returns pins to GPIO mode
fblanc 0:37964304d479 93 *
fblanc 0:37964304d479 94 */
fblanc 0:37964304d479 95 void DeInit();
fblanc 0:37964304d479 96
fblanc 0:37964304d479 97 /** Report direction (QEISTAT bit DIR)
fblanc 0:37964304d479 98 *
fblanc 0:37964304d479 99 * @return State of the DIR bit (SET or RESET)
fblanc 0:37964304d479 100 */
fblanc 0:37964304d479 101 FlagStatus Direction();
fblanc 0:37964304d479 102
fblanc 0:37964304d479 103 /**
fblanc 0:37964304d479 104 * @brief Get current position value in QEI peripheral
fblanc 0:37964304d479 105 *
fblanc 0:37964304d479 106 * @return Current position value of QEI peripheral
fblanc 0:37964304d479 107 */
fblanc 0:37964304d479 108 uint32_t GetPosition();
fblanc 0:37964304d479 109
fblanc 0:37964304d479 110 /** Set max position value for QEI peripheral
fblanc 0:37964304d479 111 *
fblanc 0:37964304d479 112 * @param[in] ulMaxPos Max position value to set
fblanc 0:37964304d479 113 * @return None
fblanc 0:37964304d479 114 */
fblanc 0:37964304d479 115 void SetMaxPosition(uint32_t ulMaxPos);
fblanc 0:37964304d479 116
fblanc 0:37964304d479 117 /** Set position compare value for QEI peripheral
fblanc 0:37964304d479 118 * @param[in] bPosCompCh Compare Position channel, should be:
fblanc 0:37964304d479 119 * - QEI_COMPPOS_CH_0: QEI compare position channel 0
fblanc 0:37964304d479 120 * - QEI_COMPPOS_CH_1: QEI compare position channel 1
fblanc 0:37964304d479 121 * - QEI_COMPPOS_CH_2: QEI compare position channel 2
fblanc 0:37964304d479 122 * @param[in] ulPosComp Compare Position value to set
fblanc 0:37964304d479 123 * @return None
fblanc 0:37964304d479 124 */
fblanc 0:37964304d479 125 void SetPositionComp( uint8_t bPosCompCh, uint32_t ulPosComp);
fblanc 0:37964304d479 126
fblanc 0:37964304d479 127 /** Get current index counter of QEI peripheral
fblanc 0:37964304d479 128 *
fblanc 0:37964304d479 129 * @return Current value of QEI index counter
fblanc 0:37964304d479 130 */
fblanc 0:37964304d479 131 uint32_t GetIndex();
fblanc 0:37964304d479 132
fblanc 0:37964304d479 133 /** Set value for index compare in QEI peripheral
fblanc 0:37964304d479 134 * @param[in] ulIndexComp Compare Index Value to set
fblanc 0:37964304d479 135 * @return None
fblanc 0:37964304d479 136 */
fblanc 0:37964304d479 137 void SetIndexComp( uint32_t ulIndexComp);
fblanc 0:37964304d479 138
fblanc 0:37964304d479 139 /** Set Velocity timer reload value
fblanc 0:37964304d479 140 *
fblanc 0:37964304d479 141 * @param[in] ulReloadValue Velocity timer reload count
fblanc 0:37964304d479 142 * @return None
fblanc 0:37964304d479 143 */
fblanc 0:37964304d479 144 void SetVelocityTimerReload( uint32_t ulReloadValue);
fblanc 0:37964304d479 145
fblanc 0:37964304d479 146 /** Set Velocity timer reload value in microseconds
fblanc 0:37964304d479 147 *
fblanc 0:37964304d479 148 * @param[in] ulReloadValue Velocity timer reload count
fblanc 0:37964304d479 149 * @return None
fblanc 0:37964304d479 150 */
fblanc 0:37964304d479 151 void SetVelocityTimerReload_us( uint32_t ulReloadValue);
fblanc 0:37964304d479 152
fblanc 0:37964304d479 153 /** Get current timer counter in QEI peripheral
fblanc 0:37964304d479 154 *
fblanc 0:37964304d479 155 * @return Current timer counter in QEI peripheral
fblanc 0:37964304d479 156 */
fblanc 0:37964304d479 157 uint32_t GetTimer();
fblanc 0:37964304d479 158
fblanc 0:37964304d479 159 /** Get current velocity pulse counter in current time period
fblanc 0:37964304d479 160 *
fblanc 0:37964304d479 161 * @return Current velocity pulse counter value
fblanc 0:37964304d479 162 */
fblanc 0:37964304d479 163 uint32_t GetVelocity();
fblanc 0:37964304d479 164
fblanc 0:37964304d479 165 /** Get the most recently measured velocity of the QEI. When
fblanc 0:37964304d479 166 * the Velocity timer in QEI is over-flow, the current velocity
fblanc 0:37964304d479 167 * value will be loaded into Velocity Capture register.
fblanc 0:37964304d479 168 *
fblanc 0:37964304d479 169 * @return The most recently measured velocity value
fblanc 0:37964304d479 170 */
fblanc 0:37964304d479 171 uint32_t GetVelocityCap();
fblanc 0:37964304d479 172
fblanc 0:37964304d479 173 /** Set Velocity Compare value for QEI peripheral
fblanc 0:37964304d479 174 *
fblanc 0:37964304d479 175 * @param[in] ulVelComp Compare Velocity value to set
fblanc 0:37964304d479 176 * @return None
fblanc 0:37964304d479 177 */
fblanc 0:37964304d479 178 void SetVelocityComp( uint32_t ulVelComp);
fblanc 0:37964304d479 179
fblanc 0:37964304d479 180 /** Set value of sampling count for the digital filter in
fblanc 0:37964304d479 181 * QEI peripheral
fblanc 0:37964304d479 182 *
fblanc 0:37964304d479 183 * @param[in] ulSamplingPulse Value of sampling count to set
fblanc 0:37964304d479 184 * @return None
fblanc 0:37964304d479 185 */
fblanc 0:37964304d479 186 void SetDigiFilter( uint32_t ulSamplingPulse);
fblanc 0:37964304d479 187
fblanc 0:37964304d479 188 /** Check whether if specified interrupt flag status in QEI
fblanc 0:37964304d479 189 * peripheral is set or not
fblanc 0:37964304d479 190 *
fblanc 0:37964304d479 191 * @param[in] ulIntType Interrupt Flag Status type, should be:
fblanc 0:37964304d479 192 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:37964304d479 193 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:37964304d479 194 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:37964304d479 195 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:37964304d479 196 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:37964304d479 197 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:37964304d479 198 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:37964304d479 199 current position interrupt
fblanc 0:37964304d479 200 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:37964304d479 201 current position interrupt
fblanc 0:37964304d479 202 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:37964304d479 203 current position interrupt
fblanc 0:37964304d479 204 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:37964304d479 205 index count interrupt
fblanc 0:37964304d479 206 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:37964304d479 207 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:37964304d479 208 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:37964304d479 209 * @return New State of specified interrupt flag status (SET or RESET)
fblanc 0:37964304d479 210 */
fblanc 0:37964304d479 211 FlagStatus GetIntStatus( uint32_t ulIntType);
fblanc 0:37964304d479 212
fblanc 0:37964304d479 213 /** Enable/Disable specified interrupt in QEI peripheral
fblanc 0:37964304d479 214 *
fblanc 0:37964304d479 215 * @param[in] ulIntType Interrupt Flag Status type, should be:
fblanc 0:37964304d479 216 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:37964304d479 217 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:37964304d479 218 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:37964304d479 219 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:37964304d479 220 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:37964304d479 221 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:37964304d479 222 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:37964304d479 223 * current position interrupt
fblanc 0:37964304d479 224 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:37964304d479 225 * current position interrupt
fblanc 0:37964304d479 226 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:37964304d479 227 * current position interrupt
fblanc 0:37964304d479 228 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:37964304d479 229 * index count interrupt
fblanc 0:37964304d479 230 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:37964304d479 231 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:37964304d479 232 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:37964304d479 233 * @param[in] NewState New function state, should be:
fblanc 0:37964304d479 234 * - DISABLE
fblanc 0:37964304d479 235 * - ENABLE
fblanc 0:37964304d479 236 * @return None
fblanc 0:37964304d479 237 */
fblanc 0:37964304d479 238 void IntCmd( uint32_t ulIntType, FunctionalState NewState);
fblanc 0:37964304d479 239
fblanc 0:37964304d479 240 /** Asserts specified interrupt in QEI peripheral
fblanc 0:37964304d479 241 *
fblanc 0:37964304d479 242 * @param[in] ulIntType Interrupt Flag Status type, should be:
fblanc 0:37964304d479 243 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:37964304d479 244 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:37964304d479 245 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:37964304d479 246 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:37964304d479 247 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:37964304d479 248 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:37964304d479 249 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:37964304d479 250 current position interrupt
fblanc 0:37964304d479 251 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:37964304d479 252 current position interrupt
fblanc 0:37964304d479 253 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:37964304d479 254 current position interrupt
fblanc 0:37964304d479 255 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:37964304d479 256 index count interrupt
fblanc 0:37964304d479 257 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:37964304d479 258 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:37964304d479 259 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:37964304d479 260 * @return None
fblanc 0:37964304d479 261 */
fblanc 0:37964304d479 262 void IntSet( uint32_t ulIntType);
fblanc 0:37964304d479 263
fblanc 0:37964304d479 264 /** De-asserts specified interrupt (pending) in QEI peripheral
fblanc 0:37964304d479 265 *
fblanc 0:37964304d479 266 * @param[in] ulIntType Interrupt Flag Status type, should be:
fblanc 0:37964304d479 267 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:37964304d479 268 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:37964304d479 269 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:37964304d479 270 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:37964304d479 271 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:37964304d479 272 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:37964304d479 273 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:37964304d479 274 current position interrupt
fblanc 0:37964304d479 275 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:37964304d479 276 current position interrupt
fblanc 0:37964304d479 277 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:37964304d479 278 current position interrupt
fblanc 0:37964304d479 279 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:37964304d479 280 index count interrupt
fblanc 0:37964304d479 281 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:37964304d479 282 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:37964304d479 283 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:37964304d479 284 * @return None
fblanc 0:37964304d479 285 */
fblanc 0:37964304d479 286 void IntClear( uint32_t ulIntType);
fblanc 0:37964304d479 287
fblanc 0:37964304d479 288 /** Append interrupt handler for specific QEI interrupt source
fblanc 0:37964304d479 289 *
fblanc 0:37964304d479 290 * @param[in] ulISRType Interrupt Flag Status type, should be:
fblanc 0:37964304d479 291 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:37964304d479 292 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:37964304d479 293 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:37964304d479 294 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:37964304d479 295 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:37964304d479 296 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:37964304d479 297 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:37964304d479 298 * current position interrupt
fblanc 0:37964304d479 299 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:37964304d479 300 * current position interrupt
fblanc 0:37964304d479 301 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:37964304d479 302 * current position interrupt
fblanc 0:37964304d479 303 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:37964304d479 304 * index count interrupt
fblanc 0:37964304d479 305 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:37964304d479 306 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:37964304d479 307 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:37964304d479 308 *
fblanc 0:37964304d479 309 * @return none
fblanc 0:37964304d479 310 */
fblanc 0:37964304d479 311 void AppendISR(uint32_t ulISRType, void(*fptr)(void));
fblanc 0:37964304d479 312
fblanc 0:37964304d479 313 /** Unappend interrupt handler for specific QEI interrupt source
fblanc 0:37964304d479 314 *
fblanc 0:37964304d479 315 * @param[in] ulISRType Interrupt Flag Status type, should be:
fblanc 0:37964304d479 316 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:37964304d479 317 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:37964304d479 318 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:37964304d479 319 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:37964304d479 320 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:37964304d479 321 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:37964304d479 322 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:37964304d479 323 * current position interrupt
fblanc 0:37964304d479 324 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:37964304d479 325 * current position interrupt
fblanc 0:37964304d479 326 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:37964304d479 327 * current position interrupt
fblanc 0:37964304d479 328 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:37964304d479 329 * index count interrupt
fblanc 0:37964304d479 330 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:37964304d479 331 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:37964304d479 332 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:37964304d479 333 *
fblanc 0:37964304d479 334 * @return none
fblanc 0:37964304d479 335 */
fblanc 0:37964304d479 336 void UnAppendISR(uint32_t ulISRType);
fblanc 0:37964304d479 337
fblanc 0:37964304d479 338
fblanc 0:37964304d479 339 /**
fblanc 0:37964304d479 340 * @brief Calculates the actual velocity in RPM passed via velocity
fblanc 0:37964304d479 341 * capture value and Pulse Per Revolution (of the encoder) value
fblanc 0:37964304d479 342 * parameter input.
fblanc 0:37964304d479 343 *
fblanc 0:37964304d479 344 * @param[in] ulVelCapValue Velocity capture input value that can
fblanc 0:37964304d479 345 * be got from QEI_GetVelocityCap() function
fblanc 0:37964304d479 346 * @param[in] ulPPR Pulse per round of encoder
fblanc 0:37964304d479 347 * @return The actual value of velocity in RPM (Revolutions per minute)
fblanc 0:37964304d479 348 */
fblanc 0:37964304d479 349 uint32_t CalculateRPM( uint32_t ulVelCapValue, uint32_t ulPPR);
fblanc 0:37964304d479 350
fblanc 0:37964304d479 351
fblanc 0:37964304d479 352 /* Public Macros -------------------------------------------------------------- */
fblanc 0:37964304d479 353 /* QEI Reset types */
fblanc 0:37964304d479 354 #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
fblanc 0:37964304d479 355 #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
fblanc 0:37964304d479 356 #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
fblanc 0:37964304d479 357 #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
fblanc 0:37964304d479 358
fblanc 0:37964304d479 359 /* QEI Direction Invert Type Option */
fblanc 0:37964304d479 360 #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
fblanc 0:37964304d479 361 #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
fblanc 0:37964304d479 362
fblanc 0:37964304d479 363 /* QEI Signal Mode Option */
fblanc 0:37964304d479 364 #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
fblanc 0:37964304d479 365 #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
fblanc 0:37964304d479 366
fblanc 0:37964304d479 367 /* QEI Capture Mode Option */
fblanc 0:37964304d479 368 #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
fblanc 0:37964304d479 369 #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
fblanc 0:37964304d479 370
fblanc 0:37964304d479 371 /* QEI Invert Index Signal Option */
fblanc 0:37964304d479 372 #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
fblanc 0:37964304d479 373 #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
fblanc 0:37964304d479 374
fblanc 0:37964304d479 375 /* QEI timer reload option */
fblanc 0:37964304d479 376 #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
fblanc 0:37964304d479 377 #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
fblanc 0:37964304d479 378
fblanc 0:37964304d479 379 /* QEI Flag Status type */
fblanc 0:37964304d479 380 #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
fblanc 0:37964304d479 381
fblanc 0:37964304d479 382 /* QEI Compare Position channel option */
fblanc 0:37964304d479 383 #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
fblanc 0:37964304d479 384 #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
fblanc 0:37964304d479 385 #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
fblanc 0:37964304d479 386
fblanc 0:37964304d479 387 /* QEI interrupt flag type */
fblanc 0:37964304d479 388 #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
fblanc 0:37964304d479 389 #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
fblanc 0:37964304d479 390 #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
fblanc 0:37964304d479 391 #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
fblanc 0:37964304d479 392 #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
fblanc 0:37964304d479 393 #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
fblanc 0:37964304d479 394 #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
fblanc 0:37964304d479 395 current position interrupt */
fblanc 0:37964304d479 396 #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
fblanc 0:37964304d479 397 current position interrupt */
fblanc 0:37964304d479 398 #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
fblanc 0:37964304d479 399 current position interrupt */
fblanc 0:37964304d479 400 #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
fblanc 0:37964304d479 401 index count interrupt */
fblanc 0:37964304d479 402 #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
fblanc 0:37964304d479 403 #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
fblanc 0:37964304d479 404 #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
fblanc 0:37964304d479 405
fblanc 0:37964304d479 406 /* QEI Process position reporting options */
fblanc 0:37964304d479 407 #define QEI_PROCESS_OPERATE 0;
fblanc 0:37964304d479 408 #define QEI_PROCESS_RESET 1;
fblanc 0:37964304d479 409 #define QEI_PROCESS_INCREMENTAL 0;
fblanc 0:37964304d479 410 #define QEI_PROCESS_ACCUMULATE 1;
fblanc 0:37964304d479 411 #define QEI_PROCESS_LINEAR 0;
fblanc 0:37964304d479 412 #define QEI_PROCESS_WEIGHTED 1;
fblanc 0:37964304d479 413
fblanc 0:37964304d479 414 private:
fblanc 0:37964304d479 415 static void _Qeiisr(void);
fblanc 0:37964304d479 416 void Qeiisr(void);
fblanc 0:37964304d479 417 static QEIHW *instance;
fblanc 0:37964304d479 418
fblanc 0:37964304d479 419 void(*_qei_isr[13])();
fblanc 0:37964304d479 420
fblanc 0:37964304d479 421
fblanc 0:37964304d479 422 /* Private Macros ------------------------------------------------------------- */
fblanc 0:37964304d479 423 /* --------------------- BIT DEFINITIONS -------------------------------------- */
fblanc 0:37964304d479 424 /* Quadrature Encoder Interface Control Register Definition --------------------- */
fblanc 0:37964304d479 425 /*********************************************************************//**
fblanc 0:37964304d479 426 * Macro defines for QEI Control register
fblanc 0:37964304d479 427 **********************************************************************/
fblanc 0:37964304d479 428 #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
fblanc 0:37964304d479 429 #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
fblanc 0:37964304d479 430 #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
fblanc 0:37964304d479 431 #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
fblanc 0:37964304d479 432 #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
fblanc 0:37964304d479 433
fblanc 0:37964304d479 434 /*********************************************************************//**
fblanc 0:37964304d479 435 * Macro defines for QEI Configuration register
fblanc 0:37964304d479 436 **********************************************************************/
fblanc 0:37964304d479 437 #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
fblanc 0:37964304d479 438 #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
fblanc 0:37964304d479 439 #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
fblanc 0:37964304d479 440 #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
fblanc 0:37964304d479 441 #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
fblanc 0:37964304d479 442
fblanc 0:37964304d479 443 /*********************************************************************//**
fblanc 0:37964304d479 444 * Macro defines for QEI Status register
fblanc 0:37964304d479 445 **********************************************************************/
fblanc 0:37964304d479 446 #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
fblanc 0:37964304d479 447 #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
fblanc 0:37964304d479 448
fblanc 0:37964304d479 449 /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
fblanc 0:37964304d479 450 /*********************************************************************//**
fblanc 0:37964304d479 451 * Macro defines for QEI Interrupt Status register
fblanc 0:37964304d479 452 **********************************************************************/
fblanc 0:37964304d479 453 #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
fblanc 0:37964304d479 454 #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
fblanc 0:37964304d479 455 #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
fblanc 0:37964304d479 456 #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
fblanc 0:37964304d479 457 #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
fblanc 0:37964304d479 458 #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
fblanc 0:37964304d479 459 #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
fblanc 0:37964304d479 460 current position */
fblanc 0:37964304d479 461 #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
fblanc 0:37964304d479 462 current position */
fblanc 0:37964304d479 463 #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
fblanc 0:37964304d479 464 current position */
fblanc 0:37964304d479 465 #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
fblanc 0:37964304d479 466 index count */
fblanc 0:37964304d479 467 #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
fblanc 0:37964304d479 468 both the POS0_Int bit is set and the REV_Int is set */
fblanc 0:37964304d479 469 #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
fblanc 0:37964304d479 470 both the POS1_Int bit is set and the REV_Int is set */
fblanc 0:37964304d479 471 #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
fblanc 0:37964304d479 472 both the POS2_Int bit is set and the REV_Int is set */
fblanc 0:37964304d479 473 #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
fblanc 0:37964304d479 474
fblanc 0:37964304d479 475 /*********************************************************************//**
fblanc 0:37964304d479 476 * Macro defines for QEI Interrupt Set register
fblanc 0:37964304d479 477 **********************************************************************/
fblanc 0:37964304d479 478 #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
fblanc 0:37964304d479 479 #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
fblanc 0:37964304d479 480 #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:37964304d479 481 #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
fblanc 0:37964304d479 482 #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
fblanc 0:37964304d479 483 #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
fblanc 0:37964304d479 484 #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
fblanc 0:37964304d479 485 current position */
fblanc 0:37964304d479 486 #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
fblanc 0:37964304d479 487 current position */
fblanc 0:37964304d479 488 #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
fblanc 0:37964304d479 489 current position */
fblanc 0:37964304d479 490 #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
fblanc 0:37964304d479 491 index count */
fblanc 0:37964304d479 492 #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
fblanc 0:37964304d479 493 #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
fblanc 0:37964304d479 494 #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
fblanc 0:37964304d479 495 #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
fblanc 0:37964304d479 496
fblanc 0:37964304d479 497 /*********************************************************************//**
fblanc 0:37964304d479 498 * Macro defines for QEI Interrupt Clear register
fblanc 0:37964304d479 499 **********************************************************************/
fblanc 0:37964304d479 500 #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
fblanc 0:37964304d479 501 #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
fblanc 0:37964304d479 502 #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:37964304d479 503 #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
fblanc 0:37964304d479 504 #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
fblanc 0:37964304d479 505 #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
fblanc 0:37964304d479 506 #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
fblanc 0:37964304d479 507 current position */
fblanc 0:37964304d479 508 #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
fblanc 0:37964304d479 509 current position */
fblanc 0:37964304d479 510 #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
fblanc 0:37964304d479 511 current position */
fblanc 0:37964304d479 512 #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
fblanc 0:37964304d479 513 index count */
fblanc 0:37964304d479 514 #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
fblanc 0:37964304d479 515 #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
fblanc 0:37964304d479 516 #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
fblanc 0:37964304d479 517 #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */
fblanc 0:37964304d479 518
fblanc 0:37964304d479 519 /*********************************************************************//**
fblanc 0:37964304d479 520 * Macro defines for QEI Interrupt Enable register
fblanc 0:37964304d479 521 **********************************************************************/
fblanc 0:37964304d479 522 #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
fblanc 0:37964304d479 523 #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
fblanc 0:37964304d479 524 #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:37964304d479 525 #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
fblanc 0:37964304d479 526 #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
fblanc 0:37964304d479 527 #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
fblanc 0:37964304d479 528 #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
fblanc 0:37964304d479 529 current position */
fblanc 0:37964304d479 530 #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
fblanc 0:37964304d479 531 current position */
fblanc 0:37964304d479 532 #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
fblanc 0:37964304d479 533 current position */
fblanc 0:37964304d479 534 #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
fblanc 0:37964304d479 535 index count */
fblanc 0:37964304d479 536 #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
fblanc 0:37964304d479 537 #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
fblanc 0:37964304d479 538 #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
fblanc 0:37964304d479 539 #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
fblanc 0:37964304d479 540
fblanc 0:37964304d479 541 /*********************************************************************//**
fblanc 0:37964304d479 542 * Macro defines for QEI Interrupt Enable Set register
fblanc 0:37964304d479 543 **********************************************************************/
fblanc 0:37964304d479 544 #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
fblanc 0:37964304d479 545 #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
fblanc 0:37964304d479 546 #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:37964304d479 547 #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
fblanc 0:37964304d479 548 #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
fblanc 0:37964304d479 549 #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
fblanc 0:37964304d479 550 #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
fblanc 0:37964304d479 551 current position */
fblanc 0:37964304d479 552 #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
fblanc 0:37964304d479 553 current position */
fblanc 0:37964304d479 554 #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
fblanc 0:37964304d479 555 current position */
fblanc 0:37964304d479 556 #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
fblanc 0:37964304d479 557 index count */
fblanc 0:37964304d479 558 #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
fblanc 0:37964304d479 559 #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
fblanc 0:37964304d479 560 #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
fblanc 0:37964304d479 561 #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
fblanc 0:37964304d479 562
fblanc 0:37964304d479 563 /*********************************************************************//**
fblanc 0:37964304d479 564 * Macro defines for QEI Interrupt Enable Clear register
fblanc 0:37964304d479 565 **********************************************************************/
fblanc 0:37964304d479 566 #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
fblanc 0:37964304d479 567 #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
fblanc 0:37964304d479 568 #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:37964304d479 569 #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
fblanc 0:37964304d479 570 #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
fblanc 0:37964304d479 571 #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
fblanc 0:37964304d479 572 #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
fblanc 0:37964304d479 573 current position */
fblanc 0:37964304d479 574 #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
fblanc 0:37964304d479 575 current position */
fblanc 0:37964304d479 576 #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
fblanc 0:37964304d479 577 current position */
fblanc 0:37964304d479 578 #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
fblanc 0:37964304d479 579 index count */
fblanc 0:37964304d479 580 #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
fblanc 0:37964304d479 581 #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
fblanc 0:37964304d479 582 #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
fblanc 0:37964304d479 583 #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */
fblanc 0:37964304d479 584
fblanc 0:37964304d479 585 /*********************************************************************//**
fblanc 0:37964304d479 586 * Macro defines for PCONP register QEI-related bits
fblanc 0:37964304d479 587 **********************************************************************/
fblanc 0:37964304d479 588 #define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */
fblanc 0:37964304d479 589 #define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */
fblanc 0:37964304d479 590
fblanc 0:37964304d479 591 /*********************************************************************//**
fblanc 0:37964304d479 592 * Macro defines for PCLKSELx register QEI-related bits
fblanc 0:37964304d479 593 **********************************************************************/
fblanc 0:37964304d479 594 #define PCLKSEL_CCLK_DIV_1 1UL /**< Set PCLK to CCLK/1 */
fblanc 0:37964304d479 595 #define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */
fblanc 0:37964304d479 596 #define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */
fblanc 0:37964304d479 597 #define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */
fblanc 0:37964304d479 598 #define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */
fblanc 0:37964304d479 599 /*********************************************************************//**
fblanc 0:37964304d479 600 * Macro defines for PINSEL3 register QEI-related bits
fblanc 0:37964304d479 601 **********************************************************************/
fblanc 0:37964304d479 602 #define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */
fblanc 0:37964304d479 603 #define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */
fblanc 0:37964304d479 604 #define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */
fblanc 0:37964304d479 605 #define PINSEL3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI2 (PhB) pin mask */
fblanc 0:37964304d479 606 #define PINSEL3_MCI2 ((uint32_t)(1<<16)) /**< MCI2 (Index) pin select */
fblanc 0:37964304d479 607 #define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */
fblanc 0:37964304d479 608
fblanc 0:37964304d479 609 /*********************************************************************//**
fblanc 0:37964304d479 610 * Macro defines for PINMODE3 register QEI-related bits
fblanc 0:37964304d479 611 **********************************************************************/
fblanc 0:37964304d479 612 #define PIN_PULL_UP 0UL
fblanc 0:37964304d479 613 #define PIN_REPEATER 1UL
fblanc 0:37964304d479 614 #define PIN_NORESISTOR 2UL
fblanc 0:37964304d479 615 #define PIN_PULL_DOWN 3UL
fblanc 0:37964304d479 616
fblanc 0:37964304d479 617 #define PINMODE3_MCI0 ((uint32_t)(PIN_NORESISTOR<<8)) /**< MCIO (PhA) resistor selection */
fblanc 0:37964304d479 618 #define PINMODE3_GPIO1p20 ((uint32_t)(PIN_PULL_DOWN<<8)) /**< GPIO 1.20) resistor selection */
fblanc 0:37964304d479 619 #define PINMODE3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) resistor mask */
fblanc 0:37964304d479 620
fblanc 0:37964304d479 621 #define PINMODE3_MCI1 ((uint32_t)(PIN_NORESISTOR<<14)) /**< MCI1 (PhB) resistor selection */
fblanc 0:37964304d479 622 #define PINMODE3_GPIO1p23 ((uint32_t)(PIN_PULL_DOWN<<14)) /**< GPIO 1.23) resistor selection */
fblanc 0:37964304d479 623 #define PINMODE3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI1 (PhB) resistor mask */
fblanc 0:37964304d479 624
fblanc 0:37964304d479 625 #define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */
fblanc 0:37964304d479 626 #define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */
fblanc 0:37964304d479 627 #define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */
fblanc 0:37964304d479 628
fblanc 0:37964304d479 629 };
fblanc 0:37964304d479 630
fblanc 0:37964304d479 631
fblanc 0:37964304d479 632 #endif /* MBED_QEI_H */
fblanc 0:37964304d479 633 /* --------------------------------- End Of File ------------------------------ */