12-Bit, 8-Channel, ADC System Monitor w/ Temp Sensor, Internal/External Reference, & I2C Interface
Dependents: ADC128D818_HelloWorld
ADC128D818.h@2:f9a0518b352a, 2013-09-05 (annotated)
- Committer:
- fblanc
- Date:
- Thu Sep 05 11:50:58 2013 +0000
- Revision:
- 2:f9a0518b352a
- Parent:
- 1:5f9dbbbc34c5
- Child:
- 3:816284ff2a09
doc .H
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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fblanc | 1:5f9dbbbc34c5 | 1 | /** |
fblanc | 1:5f9dbbbc34c5 | 2 | * @brief ADC128D818 12-Bit, 8-Channel, ADC System Monitor w/ Temp Sensor, Internal/External Reference, & I2C Interfac |
fblanc | 1:5f9dbbbc34c5 | 3 | * http://www.ti.com/product/adc128d818/ |
fblanc | 1:5f9dbbbc34c5 | 4 | * @date 02/09/2013 |
fblanc | 1:5f9dbbbc34c5 | 5 | * @author F.BLANC LAAS-CNRS |
fblanc | 1:5f9dbbbc34c5 | 6 | * http://homepages.laas.fr/fblanc/ |
fblanc | 1:5f9dbbbc34c5 | 7 | */ |
fblanc | 0:9cc68ef524da | 8 | |
fblanc | 0:9cc68ef524da | 9 | #ifndef ADC128D818_H |
fblanc | 0:9cc68ef524da | 10 | |
fblanc | 0:9cc68ef524da | 11 | #define ADC128D818_H |
fblanc | 0:9cc68ef524da | 12 | |
fblanc | 0:9cc68ef524da | 13 | #include "mbed.h" |
fblanc | 0:9cc68ef524da | 14 | |
fblanc | 0:9cc68ef524da | 15 | |
fblanc | 0:9cc68ef524da | 16 | //Library for the ADC128D818 12 BIT ADC. |
fblanc | 0:9cc68ef524da | 17 | enum ADC_MODE { |
fblanc | 2:f9a0518b352a | 18 | ADC_MODE_0 = 0x00, |
fblanc | 2:f9a0518b352a | 19 | ADC_MODE_1 = 0x01, |
fblanc | 2:f9a0518b352a | 20 | ADC_MODE_2 = 0x02, |
fblanc | 2:f9a0518b352a | 21 | ADC_MODE_3 = 0x03 |
fblanc | 2:f9a0518b352a | 22 | }; |
fblanc | 2:f9a0518b352a | 23 | enum ADC_ADDRESS { |
fblanc | 2:f9a0518b352a | 24 | ADC_ADDRESS_LOW_LOW = 0x1D, |
fblanc | 2:f9a0518b352a | 25 | ADC_ADDRESS_LOW_MID = 0x1E, |
fblanc | 2:f9a0518b352a | 26 | ADC_ADDRESS_LOW_HIGH = 0x1F, |
fblanc | 2:f9a0518b352a | 27 | ADC_ADDRESS_MID_LOW = 0x2D, |
fblanc | 2:f9a0518b352a | 28 | ADC_ADDRESS_MID_MID = 0x2E, |
fblanc | 2:f9a0518b352a | 29 | ADC_ADDRESS_MID_HIGH = 0x2F, |
fblanc | 2:f9a0518b352a | 30 | ADC_ADDRESS_HIGH_LOW = 0x35, |
fblanc | 2:f9a0518b352a | 31 | ADC_ADDRESS_HIGH_MID = 0x36, |
fblanc | 2:f9a0518b352a | 32 | ADC_ADDRESS_HIGH_HIGH = 0x37 |
fblanc | 2:f9a0518b352a | 33 | }; |
fblanc | 2:f9a0518b352a | 34 | enum ADC_VREF { |
fblanc | 2:f9a0518b352a | 35 | ADC_VREF_INT = 0x00, |
fblanc | 2:f9a0518b352a | 36 | ADC_VREF_EXT = 0x01 |
fblanc | 2:f9a0518b352a | 37 | }; |
fblanc | 2:f9a0518b352a | 38 | enum ADC_RATE { |
fblanc | 2:f9a0518b352a | 39 | ADC_RATE_LOW_POWER = 0x00, |
fblanc | 2:f9a0518b352a | 40 | ADC_RATE_CONTINUOUS = 0x01 |
fblanc | 2:f9a0518b352a | 41 | }; |
fblanc | 2:f9a0518b352a | 42 | enum ADC_LIMIT { |
fblanc | 2:f9a0518b352a | 43 | ADC_LIMIT_HIGH = 0x00, |
fblanc | 2:f9a0518b352a | 44 | ADC_LIMIT_LOW = 0x01 |
fblanc | 2:f9a0518b352a | 45 | }; |
fblanc | 2:f9a0518b352a | 46 | enum ADC_CHANNEL { |
fblanc | 2:f9a0518b352a | 47 | ADC_CHANNEL_IN0 = 0x00, |
fblanc | 2:f9a0518b352a | 48 | ADC_CHANNEL_IN1 = 0x01, |
fblanc | 2:f9a0518b352a | 49 | ADC_CHANNEL_IN2 = 0x02, |
fblanc | 2:f9a0518b352a | 50 | ADC_CHANNEL_IN3 = 0x03, |
fblanc | 2:f9a0518b352a | 51 | ADC_CHANNEL_IN4 = 0x04, |
fblanc | 2:f9a0518b352a | 52 | ADC_CHANNEL_IN5 = 0x05, |
fblanc | 2:f9a0518b352a | 53 | ADC_CHANNEL_IN6 = 0x06, |
fblanc | 2:f9a0518b352a | 54 | ADC_CHANNEL_IN7 = 0x07, |
fblanc | 2:f9a0518b352a | 55 | ADC_CHANNEL_TEMP = 0x07 |
fblanc | 2:f9a0518b352a | 56 | }; |
fblanc | 2:f9a0518b352a | 57 | enum ADC_INT { |
fblanc | 2:f9a0518b352a | 58 | |
fblanc | 2:f9a0518b352a | 59 | ADC_INT_IN0 = (char)~(0x01 <<0), |
fblanc | 2:f9a0518b352a | 60 | ADC_INT_IN1 = (char)~(0x01 <<1), |
fblanc | 2:f9a0518b352a | 61 | ADC_INT_IN2 = (char)~(0x01 <<2), |
fblanc | 2:f9a0518b352a | 62 | ADC_INT_IN3 = (char)~(0x01 <<3), |
fblanc | 2:f9a0518b352a | 63 | ADC_INT_IN4 = (char)~(0x01 <<4), |
fblanc | 2:f9a0518b352a | 64 | ADC_INT_IN5 = (char)~(0x01 <<5), |
fblanc | 2:f9a0518b352a | 65 | ADC_INT_IN6 = (char)~(0x01 <<6), |
fblanc | 2:f9a0518b352a | 66 | ADC_INT_IN7 = (char)~(0x01 <<7), |
fblanc | 2:f9a0518b352a | 67 | ADC_INT_TEMP = (char)~(0x01 <<7), |
fblanc | 2:f9a0518b352a | 68 | ADC_INT_ALL = 0x00 |
fblanc | 2:f9a0518b352a | 69 | }; |
fblanc | 2:f9a0518b352a | 70 | enum ADC_ENABLE { |
fblanc | 2:f9a0518b352a | 71 | |
fblanc | 2:f9a0518b352a | 72 | ADC_ENABLE_IN0 = (char)~(0x01 <<0), |
fblanc | 2:f9a0518b352a | 73 | ADC_ENABLE_IN1 = (char)~(0x01 <<1), |
fblanc | 2:f9a0518b352a | 74 | ADC_ENABLE_IN2 = (char)~(0x01 <<2), |
fblanc | 2:f9a0518b352a | 75 | ADC_ENABLE_IN3 = (char)~(0x01 <<3), |
fblanc | 2:f9a0518b352a | 76 | ADC_ENABLE_IN4 = (char)~(0x01 <<4), |
fblanc | 2:f9a0518b352a | 77 | ADC_ENABLE_IN5 = (char)~(0x01 <<5), |
fblanc | 2:f9a0518b352a | 78 | ADC_ENABLE_IN6 = (char)~(0x01 <<6), |
fblanc | 2:f9a0518b352a | 79 | ADC_ENABLE_IN7 = (char)~(0x01 <<7), |
fblanc | 2:f9a0518b352a | 80 | ADC_ENABLE_TEMP = ~(0x01 <<7), |
fblanc | 2:f9a0518b352a | 81 | ADC_ENABLE_ALL = 0x00 |
fblanc | 2:f9a0518b352a | 82 | }; |
fblanc | 2:f9a0518b352a | 83 | enum ADC_REG { |
fblanc | 2:f9a0518b352a | 84 | ADC_REG_Configuration_Register = 0x00, |
fblanc | 2:f9a0518b352a | 85 | ADC_REG_Interrupt_Status_Register = 0x01, |
fblanc | 2:f9a0518b352a | 86 | ADC_REG_Interrupt_Mask_Register = 0x03, |
fblanc | 2:f9a0518b352a | 87 | ADC_REG_Conversion_Rate_Register = 0x07, |
fblanc | 2:f9a0518b352a | 88 | ADC_REG_Channel_Disable_Register = 0x08, |
fblanc | 2:f9a0518b352a | 89 | ADC_REG_One_Shot_Register = 0x09, |
fblanc | 2:f9a0518b352a | 90 | ADC_REG_Deep_Shutdown_Register = 0x0A, |
fblanc | 2:f9a0518b352a | 91 | ADC_REG_Advanced_Configuration_Register = 0x0B, |
fblanc | 2:f9a0518b352a | 92 | ADC_REG_Busy_Status_Register = 0x0C, |
fblanc | 2:f9a0518b352a | 93 | ADC_REG_Channel_Readings_Registers = 0x20, |
fblanc | 2:f9a0518b352a | 94 | ADC_REG_Limit_Registers = 0x2A, |
fblanc | 2:f9a0518b352a | 95 | ADC_REG_Manufacturer_ID_Register = 0x3E, |
fblanc | 2:f9a0518b352a | 96 | ADC_REG_Revision_ID_Register = 0x3F |
fblanc | 2:f9a0518b352a | 97 | }; |
fblanc | 0:9cc68ef524da | 98 | class ADC128D818 |
fblanc | 0:9cc68ef524da | 99 | { |
fblanc | 2:f9a0518b352a | 100 | protected: |
fblanc | 2:f9a0518b352a | 101 | |
fblanc | 2:f9a0518b352a | 102 | |
fblanc | 2:f9a0518b352a | 103 | enum Configuration_Register { |
fblanc | 0:9cc68ef524da | 104 | Configuration_Register_Start = 1<<0, |
fblanc | 0:9cc68ef524da | 105 | Configuration_Register_INT_Enable = 1<<1, |
fblanc | 0:9cc68ef524da | 106 | Configuration_Register_INT_Clear = 1<<3, |
fblanc | 0:9cc68ef524da | 107 | Configuration_Register_Initialization = 1<<7 |
fblanc | 0:9cc68ef524da | 108 | }; |
fblanc | 2:f9a0518b352a | 109 | |
fblanc | 0:9cc68ef524da | 110 | enum Busy_Status_Register { |
fblanc | 0:9cc68ef524da | 111 | Busy_Status_Register_Busy = 1<<0, |
fblanc | 0:9cc68ef524da | 112 | Busy_Status_Register_Not_Ready = 1<<1 |
fblanc | 0:9cc68ef524da | 113 | }; |
fblanc | 2:f9a0518b352a | 114 | |
fblanc | 0:9cc68ef524da | 115 | enum Advanced_Configuration_Register { |
fblanc | 0:9cc68ef524da | 116 | Advanced_Configuration_Register_External_Reference_Enable = 1<<0, |
fblanc | 0:9cc68ef524da | 117 | Advanced_Configuration_Register_Mode_Select_0 = 1<<1, |
fblanc | 0:9cc68ef524da | 118 | Advanced_Configuration_Register_Mode_Select_1 = 1<<2 |
fblanc | 0:9cc68ef524da | 119 | }; |
fblanc | 2:f9a0518b352a | 120 | |
fblanc | 0:9cc68ef524da | 121 | enum Conversion_Rate_Register { |
fblanc | 0:9cc68ef524da | 122 | Conversion_Rate_Register_Rate_Register = 1<<0 |
fblanc | 0:9cc68ef524da | 123 | }; |
fblanc | 2:f9a0518b352a | 124 | |
fblanc | 2:f9a0518b352a | 125 | |
fblanc | 0:9cc68ef524da | 126 | private: |
fblanc | 0:9cc68ef524da | 127 | I2C _i2c; |
fblanc | 0:9cc68ef524da | 128 | char _data[2]; |
fblanc | 0:9cc68ef524da | 129 | char _address; |
fblanc | 0:9cc68ef524da | 130 | char _mode; |
fblanc | 2:f9a0518b352a | 131 | |
fblanc | 0:9cc68ef524da | 132 | public: |
fblanc | 2:f9a0518b352a | 133 | /** |
fblanc | 2:f9a0518b352a | 134 | * @brief Constructor. |
fblanc | 2:f9a0518b352a | 135 | * |
fblanc | 2:f9a0518b352a | 136 | * @param sda I2C |
fblanc | 2:f9a0518b352a | 137 | * @param scl I2C |
fblanc | 2:f9a0518b352a | 138 | * @param adc_int |
fblanc | 2:f9a0518b352a | 139 | */ |
fblanc | 0:9cc68ef524da | 140 | ADC128D818(PinName sda, PinName scl, PinName adc_int ); |
fblanc | 2:f9a0518b352a | 141 | /** |
fblanc | 2:f9a0518b352a | 142 | * @brief Destructor. |
fblanc | 2:f9a0518b352a | 143 | */ |
fblanc | 0:9cc68ef524da | 144 | ~ADC128D818(); |
fblanc | 0:9cc68ef524da | 145 | |
fblanc | 0:9cc68ef524da | 146 | InterruptIn _Adc_Int; |
fblanc | 2:f9a0518b352a | 147 | /** |
fblanc | 2:f9a0518b352a | 148 | * @brief read_channel |
fblanc | 2:f9a0518b352a | 149 | * @param channel |
fblanc | 2:f9a0518b352a | 150 | * @return u32_data |
fblanc | 2:f9a0518b352a | 151 | * @date 02/09/2013 |
fblanc | 2:f9a0518b352a | 152 | */ |
fblanc | 0:9cc68ef524da | 153 | int read_channel(char channel); |
fblanc | 2:f9a0518b352a | 154 | /** |
fblanc | 2:f9a0518b352a | 155 | * @brief read_register |
fblanc | 2:f9a0518b352a | 156 | * @param Register |
fblanc | 2:f9a0518b352a | 157 | * @return u8_data |
fblanc | 2:f9a0518b352a | 158 | * @date 02/09/2013 |
fblanc | 2:f9a0518b352a | 159 | */ |
fblanc | 0:9cc68ef524da | 160 | char read_register(char Register); |
fblanc | 2:f9a0518b352a | 161 | /** |
fblanc | 2:f9a0518b352a | 162 | * @brief init |
fblanc | 2:f9a0518b352a | 163 | * |
fblanc | 2:f9a0518b352a | 164 | * @param address I2C (7bits) |
fblanc | 2:f9a0518b352a | 165 | ADC_ADDRESS_LOW_LOW |
fblanc | 2:f9a0518b352a | 166 | ADC_ADDRESS_LOW_MID |
fblanc | 2:f9a0518b352a | 167 | ADC_ADDRESS_LOW_HIGH |
fblanc | 2:f9a0518b352a | 168 | ADC_ADDRESS_MID_LOW |
fblanc | 2:f9a0518b352a | 169 | ADC_ADDRESS_MID_MID |
fblanc | 2:f9a0518b352a | 170 | ADC_ADDRESS_MID_HIGH |
fblanc | 2:f9a0518b352a | 171 | ADC_ADDRESS_HIGH_LOW |
fblanc | 2:f9a0518b352a | 172 | ADC_ADDRESS_HIGH_MID |
fblanc | 2:f9a0518b352a | 173 | ADC_ADDRESS_HIGH_HIGH |
fblanc | 2:f9a0518b352a | 174 | * @param mode : |
fblanc | 2:f9a0518b352a | 175 | ADC_MODE_0 |
fblanc | 2:f9a0518b352a | 176 | ADC_MODE_1 |
fblanc | 2:f9a0518b352a | 177 | ADC_MODE_2 |
fblanc | 2:f9a0518b352a | 178 | ADC_MODE_3 |
fblanc | 2:f9a0518b352a | 179 | * @param vref |
fblanc | 2:f9a0518b352a | 180 | ADC_VREF_INT |
fblanc | 2:f9a0518b352a | 181 | ADC_VREF_EXT |
fblanc | 2:f9a0518b352a | 182 | * @param rate |
fblanc | 2:f9a0518b352a | 183 | ADC_RATE_LOW_POWER |
fblanc | 2:f9a0518b352a | 184 | ADC_RATE_CONTINUOUS |
fblanc | 2:f9a0518b352a | 185 | * @param mask_channel |
fblanc | 2:f9a0518b352a | 186 | * @param mask_int |
fblanc | 2:f9a0518b352a | 187 | * @return error 0 OK, -1 NO DEVICE, -2 ADC is BUSY |
fblanc | 2:f9a0518b352a | 188 | * @date 02/09/2013 |
fblanc | 2:f9a0518b352a | 189 | */ |
fblanc | 0:9cc68ef524da | 190 | int init(char address, char mode, char vref, char rate, char mask_channel, char mask_int); |
fblanc | 2:f9a0518b352a | 191 | /** |
fblanc | 2:f9a0518b352a | 192 | * @brief init_limit |
fblanc | 2:f9a0518b352a | 193 | * |
fblanc | 2:f9a0518b352a | 194 | * @param limit |
fblanc | 2:f9a0518b352a | 195 | * @param high_low |
fblanc | 2:f9a0518b352a | 196 | ADC_LIMIT_HIGH |
fblanc | 2:f9a0518b352a | 197 | ADC_LIMIT_LOW |
fblanc | 2:f9a0518b352a | 198 | * @return error 0 OK |
fblanc | 2:f9a0518b352a | 199 | * @date 02/09/2013 |
fblanc | 2:f9a0518b352a | 200 | */ |
fblanc | 1:5f9dbbbc34c5 | 201 | int init_limit(char channel, char limit, char high_low); |
fblanc | 2:f9a0518b352a | 202 | /** |
fblanc | 2:f9a0518b352a | 203 | * @brief start |
fblanc | 2:f9a0518b352a | 204 | * @date 02/09/2013 |
fblanc | 2:f9a0518b352a | 205 | */ |
fblanc | 0:9cc68ef524da | 206 | void start(); |
fblanc | 2:f9a0518b352a | 207 | /** |
fblanc | 2:f9a0518b352a | 208 | * @brief stop |
fblanc | 2:f9a0518b352a | 209 | * @date 02/09/2013 |
fblanc | 2:f9a0518b352a | 210 | */ |
fblanc | 0:9cc68ef524da | 211 | void stop(); |
fblanc | 0:9cc68ef524da | 212 | }; |
fblanc | 0:9cc68ef524da | 213 | |
fblanc | 0:9cc68ef524da | 214 | #endif |
fblanc | 0:9cc68ef524da | 215 |