Jay M / Mbed 2 deprecated interface_v2

Interface between the mbed lpc1768 and the ads1298

Dependencies:   USBDevice mbed

ADS1x9x.h@1:26b8b0e4d836, 2014-04-14 (annotated)

Committer:
faithcerebral
Date:
Mon Apr 14 16:27:56 2014 +0000
Revision:
1:26b8b0e4d836
Parent:
0:bd3a560e245e 
uncommented the test info

Who changed what in which revision?

UserRevisionLine numberNew contents of line
faithcerebral 0:bd3a560e245e 1 /**************************************************************************************************************************************************
faithcerebral 0:bd3a560e245e 2 * ADS1x9x.h Register File to set up system registers of the ADS1x9x *
faithcerebral 0:bd3a560e245e 3 * *
faithcerebral 0:bd3a560e245e 4 * Author: Mike Claassen *
faithcerebral 0:bd3a560e245e 5 * *
faithcerebral 0:bd3a560e245e 6 * Revision Date: August, 2009 *
faithcerebral 0:bd3a560e245e 7 * *
faithcerebral 0:bd3a560e245e 8 * Revision Level: 1st pass *
faithcerebral 0:bd3a560e245e 9 * *
faithcerebral 0:bd3a560e245e 10 * For Support: https://e2e.ti.com/support/development_tools/mavrk/default.aspx *
faithcerebral 0:bd3a560e245e 11 * *
faithcerebral 0:bd3a560e245e 12 ***************************************************************************************************************************************************
faithcerebral 0:bd3a560e245e 13 * Copyright � 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ *
faithcerebral 0:bd3a560e245e 14 ***************************************************************************************************************************************************
faithcerebral 0:bd3a560e245e 15 * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: *
faithcerebral 0:bd3a560e245e 16 * *
faithcerebral 0:bd3a560e245e 17 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. *
faithcerebral 0:bd3a560e245e 18 * *
faithcerebral 0:bd3a560e245e 19 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the *
faithcerebral 0:bd3a560e245e 20 * documentation and/or other materials provided with the distribution. *
faithcerebral 0:bd3a560e245e 21 * *
faithcerebral 0:bd3a560e245e 22 * Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived *
faithcerebral 0:bd3a560e245e 23 * from this software without specific prior written permission. *
faithcerebral 0:bd3a560e245e 24 * *
faithcerebral 0:bd3a560e245e 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT *
faithcerebral 0:bd3a560e245e 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT *
faithcerebral 0:bd3a560e245e 27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *
faithcerebral 0:bd3a560e245e 28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY *
faithcerebral 0:bd3a560e245e 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *
faithcerebral 0:bd3a560e245e 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
faithcerebral 0:bd3a560e245e 31 ***************************************************************************************************************************************************
faithcerebral 0:bd3a560e245e 32 * MODULE CHANGE LOG *
faithcerebral 0:bd3a560e245e 33 * *
faithcerebral 0:bd3a560e245e 34 * Date Changed: { Date } Developer: { Author } *
faithcerebral 0:bd3a560e245e 35 * Change Description: { Description } *
faithcerebral 0:bd3a560e245e 36 * *
faithcerebral 0:bd3a560e245e 37 **************************************************************************************************************************************************/
faithcerebral 0:bd3a560e245e 38 /**************************************************************************************************************************************************
faithcerebral 0:bd3a560e245e 39 * Prototypes *
faithcerebral 0:bd3a560e245e 40 **************************************************************************************************************************************************/
faithcerebral 0:bd3a560e245e 41 /**************************************************************************************************************************************************
faithcerebral 0:bd3a560e245e 42 * Prototypes *
faithcerebral 0:bd3a560e245e 43 **************************************************************************************************************************************************/
faithcerebral 0:bd3a560e245e 44 unsigned char init_ADS1x9x (unsigned char);
faithcerebral 0:bd3a560e245e 45 unsigned char ADS1x9x_SPI_Burst (unsigned char, unsigned char);
faithcerebral 0:bd3a560e245e 46 void init_ADS1x9x_IO (unsigned char);
faithcerebral 0:bd3a560e245e 47 void POR_Reset_ADS1x9x (unsigned char);
faithcerebral 0:bd3a560e245e 48 void Hard_Start_ReStart_ADS1x9x ();
faithcerebral 0:bd3a560e245e 49 void Soft_Start_ReStart_ADS1x9x (unsigned char);
faithcerebral 0:bd3a560e245e 50 void Power_Up_ADS1x9x (unsigned char);
faithcerebral 0:bd3a560e245e 51 void Stop_Read_Data_Continuous (unsigned char);
faithcerebral 0:bd3a560e245e 52 void Start_Read_Data_Continuous (unsigned char);
faithcerebral 0:bd3a560e245e 53 void enable_ADS1x9x_Conversion (unsigned char);
faithcerebral 0:bd3a560e245e 54 unsigned char Initialize_ADS1x9x_Registers (unsigned char);
faithcerebral 0:bd3a560e245e 55 unsigned char ADS1x9x_Read_Version (unsigned char);
faithcerebral 0:bd3a560e245e 56 void ADS1x9x_SPI_Address_Byte_Count (unsigned char, unsigned char, unsigned char);
faithcerebral 0:bd3a560e245e 57 unsigned char ADS1x9x_SPI_Data (unsigned char, unsigned char);
faithcerebral 0:bd3a560e245e 58 void init_ADS1x9x_Via_Constant_Table (unsigned char, unsigned char*);
faithcerebral 0:bd3a560e245e 59 unsigned char verify_ADS1x9x_Registers (unsigned char, unsigned char*);
faithcerebral 0:bd3a560e245e 60 unsigned char Enable_ADS1x9x_Test_Mode (unsigned char, unsigned char, unsigned char, unsigned char);
faithcerebral 0:bd3a560e245e 61 void Set_ADS1x9x_Chip_Enable (unsigned char);
faithcerebral 0:bd3a560e245e 62 void Clear_ADS1x9x_Chip_Enable (unsigned char);
faithcerebral 0:bd3a560e245e 63
faithcerebral 0:bd3a560e245e 64 unsigned char Initialize_ADS1x9x_Data_Rate (unsigned char, unsigned char);
faithcerebral 0:bd3a560e245e 65 unsigned char Initialize_ADS1x9x_Mode (unsigned char, unsigned char);
faithcerebral 0:bd3a560e245e 66 unsigned char Initialize_ADS1x9x_Channel (unsigned char, unsigned char, unsigned char, unsigned char, unsigned char, unsigned char);
faithcerebral 0:bd3a560e245e 67 /**************************************************************************************************************************************************
faithcerebral 0:bd3a560e245e 68 * Union Structures and Definitions *
faithcerebral 0:bd3a560e245e 69 **************************************************************************************************************************************************/
faithcerebral 0:bd3a560e245e 70 #ifndef SPI_TEST_DATA
faithcerebral 0:bd3a560e245e 71 #define SPI_TEST_DATA 0xAA // Use 1010 1010 to SPI port for debug purposes
faithcerebral 0:bd3a560e245e 72 #endif
faithcerebral 0:bd3a560e245e 73
faithcerebral 0:bd3a560e245e 74 #define ADS1x9x_DEFAULT_GPIO_STATE 0x07
faithcerebral 0:bd3a560e245e 75
faithcerebral 0:bd3a560e245e 76
faithcerebral 0:bd3a560e245e 77 enum Context_Save_Channel_Info_Type
faithcerebral 0:bd3a560e245e 78 {
faithcerebral 0:bd3a560e245e 79 CONTEXT_SAVE_CHANNEL = 1,
faithcerebral 0:bd3a560e245e 80 IGNORE_PREVIOUS_STATE = 0
faithcerebral 0:bd3a560e245e 81 };
faithcerebral 0:bd3a560e245e 82
faithcerebral 0:bd3a560e245e 83 enum ADS_1x9x_Status_Type
faithcerebral 0:bd3a560e245e 84 {
faithcerebral 0:bd3a560e245e 85 ADS_1x9x_VERIFY_ERROR = 3,
faithcerebral 0:bd3a560e245e 86 ADS_1x9x_INIT_SUCCESS = 2,
faithcerebral 0:bd3a560e245e 87 ADS_1x9x_NOT_FOUND = 1
faithcerebral 0:bd3a560e245e 88 };
faithcerebral 0:bd3a560e245e 89
faithcerebral 0:bd3a560e245e 90 #define NEW_ADS1x9x_DATA 5
faithcerebral 0:bd3a560e245e 91
faithcerebral 0:bd3a560e245e 92 #define ADS1x9x_DATA_SIZE NUMBER_ADC_CHANNELS * ADS1x9x_DATA_WIDTH
faithcerebral 0:bd3a560e245e 93
faithcerebral 0:bd3a560e245e 94 typedef struct
faithcerebral 0:bd3a560e245e 95 {
faithcerebral 0:bd3a560e245e 96 unsigned char ADC_Data_Ready: 1;
faithcerebral 0:bd3a560e245e 97 unsigned char ADC_New_Data: 1;
faithcerebral 0:bd3a560e245e 98 unsigned char ADS_1298_Module_Status: 2;
faithcerebral 0:bd3a560e245e 99 unsigned char Reserved: 4;
faithcerebral 0:bd3a560e245e 100 } ADS1x9x_Status_Flags_type;
faithcerebral 0:bd3a560e245e 101
faithcerebral 0:bd3a560e245e 102 #define ADS1x9x_PREAMBLE_GOOD 0x0C
faithcerebral 0:bd3a560e245e 103
faithcerebral 0:bd3a560e245e 104 typedef struct
faithcerebral 0:bd3a560e245e 105 {
faithcerebral 0:bd3a560e245e 106 unsigned char ID_Reserved: 5; // Reserved
faithcerebral 0:bd3a560e245e 107 unsigned char Revision_ID: 3; // Revision ID (REV_ID[3:1])
faithcerebral 0:bd3a560e245e 108 } ADS1x9x_ID_Register_type;
faithcerebral 0:bd3a560e245e 109
faithcerebral 0:bd3a560e245e 110 // REVISION_ID bit field definition
faithcerebral 0:bd3a560e245e 111 #define ADS1x9x_REV 0
faithcerebral 0:bd3a560e245e 112
faithcerebral 0:bd3a560e245e 113 typedef struct
faithcerebral 0:bd3a560e245e 114 {
faithcerebral 0:bd3a560e245e 115 unsigned char Output_Data_Rate: 3; // Output Data Rate (DR[2:0])
faithcerebral 0:bd3a560e245e 116 unsigned char Config_1_Reserved: 2; // Reserved
faithcerebral 0:bd3a560e245e 117 unsigned char Oscillator_Clock_Output: 1; // CLKOUT Connection (CLK_EN)
faithcerebral 0:bd3a560e245e 118 unsigned char Readback_Mode: 1; // Daisy-chain/multiple readback mode (DAISY_EN')
faithcerebral 0:bd3a560e245e 119 unsigned char Power_Resolution_Optimization: 1; // Low-Power/High-Resolution mode (HR)
faithcerebral 0:bd3a560e245e 120 } ADS1x9x_Config_1_Register_type;
faithcerebral 0:bd3a560e245e 121
faithcerebral 0:bd3a560e245e 122
faithcerebral 0:bd3a560e245e 123 // OUTPUT_DATA_RATE bit field definition
faithcerebral 0:bd3a560e245e 124 enum Output_Data_Rate_Type
faithcerebral 0:bd3a560e245e 125 {
faithcerebral 0:bd3a560e245e 126 DEFAULT_MODULATION_FREQUENCY_DIVIDED_BY_16 = 0,
faithcerebral 0:bd3a560e245e 127 MODULATION_FREQUENCY_DIVIDED_BY_32 = 1,
faithcerebral 0:bd3a560e245e 128 MODULATION_FREQUENCY_DIVIDED_BY_64 = 2,
faithcerebral 0:bd3a560e245e 129 MODULATION_FREQUENCY_DIVIDED_BY_128 = 3,
faithcerebral 0:bd3a560e245e 130 MODULATION_FREQUENCY_DIVIDED_BY_256 = 4,
faithcerebral 0:bd3a560e245e 131 MODULATION_FREQUENCY_DIVIDED_BY_512 = 5,
faithcerebral 0:bd3a560e245e 132 MODULATION_FREQUENCY_DIVIDED_BY_1024 = 6
faithcerebral 0:bd3a560e245e 133 };
faithcerebral 0:bd3a560e245e 134
faithcerebral 0:bd3a560e245e 135 enum Readback_Mode_Type
faithcerebral 0:bd3a560e245e 136 {
faithcerebral 0:bd3a560e245e 137 DEFAULT_DAISY_CHAIN_MODE = 0,
faithcerebral 0:bd3a560e245e 138 MULTIPLE_READBACK_MODE = 1
faithcerebral 0:bd3a560e245e 139 };
faithcerebral 0:bd3a560e245e 140
faithcerebral 0:bd3a560e245e 141 enum Power_Resolution_Optimization_Type
faithcerebral 0:bd3a560e245e 142 {
faithcerebral 0:bd3a560e245e 143 DEFAULT_LOW_POWER_MODE = 0,
faithcerebral 0:bd3a560e245e 144 HIGH_RESOLUTION_MODE = 1
faithcerebral 0:bd3a560e245e 145 };
faithcerebral 0:bd3a560e245e 146
faithcerebral 0:bd3a560e245e 147 typedef struct
faithcerebral 0:bd3a560e245e 148 {
faithcerebral 0:bd3a560e245e 149 unsigned char Test_Signal_Frequency: 2; // Test Signal Frequency (TEST_FREQ[1:0])
faithcerebral 0:bd3a560e245e 150 unsigned char Test_Signal_Amplitude: 2; // Test Signal Amplitude (TEST_AMP[1:0])
faithcerebral 0:bd3a560e245e 151 unsigned char Test_Source: 1; // Test Source
faithcerebral 0:bd3a560e245e 152 unsigned char Config_2_Reserved: 3; // Reserved - Needs to be written with 1's
faithcerebral 0:bd3a560e245e 153 } ADS1x9x_Config_2_Register_type;
faithcerebral 0:bd3a560e245e 154
faithcerebral 0:bd3a560e245e 155 // CONFIG_2_RESERVED bit field definition
faithcerebral 0:bd3a560e245e 156 #define CONFIG_2_RESERVED_VALUE 7
faithcerebral 0:bd3a560e245e 157
faithcerebral 0:bd3a560e245e 158 enum Test_Source_Type
faithcerebral 0:bd3a560e245e 159 {
faithcerebral 0:bd3a560e245e 160 DEFAULT_TEST_SIGNALS_ARE_DRIVEN_EXTERNALLY = 0,
faithcerebral 0:bd3a560e245e 161 TEST_SIGNALS_ARE_DRIVEN_INTERNALLY = 1
faithcerebral 0:bd3a560e245e 162 };
faithcerebral 0:bd3a560e245e 163
faithcerebral 0:bd3a560e245e 164 enum Test_Signal_Amplitude_Type
faithcerebral 0:bd3a560e245e 165 {
faithcerebral 0:bd3a560e245e 166 DEFAULT_PLUS_MINUS_1_MV_TIMES_VREF_DIVIDED_BY_2_4 = 0,
faithcerebral 0:bd3a560e245e 167 PLUS_MINUS_2_MV_TIMES_VREF_DIVIDED_BY_2_4 = 1,
faithcerebral 0:bd3a560e245e 168 PLUS_MINUS_10_MV_TIMES_VREF_DIVIDED_BY_2_4 = 2,
faithcerebral 0:bd3a560e245e 169 PLUS_MINUS_1V_TIMES_VREF_DIVIDED_BY_2_4 = 3
faithcerebral 0:bd3a560e245e 170 };
faithcerebral 0:bd3a560e245e 171
faithcerebral 0:bd3a560e245e 172 enum Test_Signal_Frequency_Type
faithcerebral 0:bd3a560e245e 173 {
faithcerebral 0:bd3a560e245e 174 DEFAULT_PULSED_AT_CLOCK_FREQUENCY_DIVIDED_BY_2_TO_THE_21ST = 0,
faithcerebral 0:bd3a560e245e 175 PULSED_AT_CLOCK_FREQUENCY_DIVIDED_BY_2_TO_THE_20TH = 1,
faithcerebral 0:bd3a560e245e 176 AT_DC = 2
faithcerebral 0:bd3a560e245e 177 };
faithcerebral 0:bd3a560e245e 178
faithcerebral 0:bd3a560e245e 179 typedef struct
faithcerebral 0:bd3a560e245e 180 {
faithcerebral 0:bd3a560e245e 181 unsigned char Config_3_Reserved: 2; // Reserved - Needs to be written with 0's
faithcerebral 0:bd3a560e245e 182 unsigned char Disable_Right_Leg_Detect_Buffer: 1; // RLD Buffer Power (PD_RLD)
faithcerebral 0:bd3a560e245e 183 unsigned char Right_Leg_Detect_Reference_Source: 1; // RLD Reference Select (RLDREF)
faithcerebral 0:bd3a560e245e 184 unsigned char Right_Leg_Detect_Signal_Route: 1; // RLD Output Routed to ADC Mux (RLD_MEAS)
faithcerebral 0:bd3a560e245e 185 unsigned char Reference_Voltage: 1; // Reference Voltage (VREF_4V)
faithcerebral 0:bd3a560e245e 186 unsigned char Config_3_Reserved_1: 1; // Reserved - Needs to be written with 1
faithcerebral 0:bd3a560e245e 187 unsigned char Internal_Reference_Buffer: 1; // Reference Voltage (PD_REFBUR')
faithcerebral 0:bd3a560e245e 188 } ADS1x9x_Config_3_Register_type;
faithcerebral 0:bd3a560e245e 189
faithcerebral 0:bd3a560e245e 190 // CONFIG_3_RESERVED_1 bit field definition
faithcerebral 0:bd3a560e245e 191 #define CONFIG_3_RESERVED_1_VALUE 1
faithcerebral 0:bd3a560e245e 192
faithcerebral 0:bd3a560e245e 193 enum Right_Leg_Detect_Reference_Source_Type
faithcerebral 0:bd3a560e245e 194 {
faithcerebral 0:bd3a560e245e 195 DEFAULT_IS_FED_EXTERNALLY = 0,
faithcerebral 0:bd3a560e245e 196 IS_FED_INTERNALLY = 1
faithcerebral 0:bd3a560e245e 197 };
faithcerebral 0:bd3a560e245e 198
faithcerebral 0:bd3a560e245e 199 enum Right_Leg_Detect_Signal_Route_Type
faithcerebral 0:bd3a560e245e 200 {
faithcerebral 0:bd3a560e245e 201 DEFAULT_IS_OPEN = 0,
faithcerebral 0:bd3a560e245e 202 ROUTED_TO_MUX_SETTING_VREF = 1
faithcerebral 0:bd3a560e245e 203 };
faithcerebral 0:bd3a560e245e 204
faithcerebral 0:bd3a560e245e 205 enum Reference_Voltage_Type
faithcerebral 0:bd3a560e245e 206 {
faithcerebral 0:bd3a560e245e 207 DEFAULT_IS_SET_TO_2_4_VOLTS = 0,
faithcerebral 0:bd3a560e245e 208 IS_SET_TO_4_VOLTS = 1
faithcerebral 0:bd3a560e245e 209 };
faithcerebral 0:bd3a560e245e 210
faithcerebral 0:bd3a560e245e 211 typedef struct
faithcerebral 0:bd3a560e245e 212 {
faithcerebral 0:bd3a560e245e 213 unsigned char Lead_Off_Frequency: 2; // Frequency Lead (FLEAD_OFF[1:0])
faithcerebral 0:bd3a560e245e 214 unsigned char Lead_Off_Current: 2; // Lead off Current Magnitude (ILEAD_OFF[1:0])
faithcerebral 0:bd3a560e245e 215 unsigned char Lead_Off_Detection_Mode: 1; // Lead off Detection Mode (VLEAD_OFF_EN)
faithcerebral 0:bd3a560e245e 216 unsigned char Lead_Off_Comparator_Threshold: 3; // Lead off Comparator Threshold (COMP_TH[2:0])
faithcerebral 0:bd3a560e245e 217 } ADS1x9x_Lead_Off_Control_Register_type;
faithcerebral 0:bd3a560e245e 218
faithcerebral 0:bd3a560e245e 219 enum Lead_Off_Frequency_Type
faithcerebral 0:bd3a560e245e 220 {
faithcerebral 0:bd3a560e245e 221 DEFAULT_LEAD_OFF_DETECTION_DISABLED = 0,
faithcerebral 0:bd3a560e245e 222 ONE_HALF_THE_OUTPUT_DATA_RATE = 1,
faithcerebral 0:bd3a560e245e 223 ONE_FOURTH_THE_OUTPUT_DATA_RATE = 2,
faithcerebral 0:bd3a560e245e 224 DC_LEAD_OFF_DETECT = 3
faithcerebral 0:bd3a560e245e 225 };
faithcerebral 0:bd3a560e245e 226
faithcerebral 0:bd3a560e245e 227 enum Lead_Off_Current_Type
faithcerebral 0:bd3a560e245e 228 {
faithcerebral 0:bd3a560e245e 229 DEFAULT_12_5_NA = 0,
faithcerebral 0:bd3a560e245e 230 _25_NA = 1,
faithcerebral 0:bd3a560e245e 231 _35_5NA = 2,
faithcerebral 0:bd3a560e245e 232 _50NA = 3
faithcerebral 0:bd3a560e245e 233 };
faithcerebral 0:bd3a560e245e 234
faithcerebral 0:bd3a560e245e 235 enum Lead_Off_Detection_Mode_Type
faithcerebral 0:bd3a560e245e 236 {
faithcerebral 0:bd3a560e245e 237 DEFAULT_CURRENT_MODE = 0,
faithcerebral 0:bd3a560e245e 238 VOLTAGE_MODE = 1
faithcerebral 0:bd3a560e245e 239 };
faithcerebral 0:bd3a560e245e 240
faithcerebral 0:bd3a560e245e 241 enum Lead_Off_Comparator_Threshold_Type
faithcerebral 0:bd3a560e245e 242 {
faithcerebral 0:bd3a560e245e 243 DEFAULT_55_PERCENT = 0,
faithcerebral 0:bd3a560e245e 244 _60_PERCENT = 1,
faithcerebral 0:bd3a560e245e 245 _65_PERCENT = 2,
faithcerebral 0:bd3a560e245e 246 _70_PERCENT = 3,
faithcerebral 0:bd3a560e245e 247 _75_PERCENT = 4,
faithcerebral 0:bd3a560e245e 248 _80_PERCENT = 5,
faithcerebral 0:bd3a560e245e 249 _85_PERCENT = 6,
faithcerebral 0:bd3a560e245e 250 _90_PERCENT = 7
faithcerebral 0:bd3a560e245e 251 };
faithcerebral 0:bd3a560e245e 252
faithcerebral 0:bd3a560e245e 253 typedef struct
faithcerebral 0:bd3a560e245e 254 {
faithcerebral 0:bd3a560e245e 255 unsigned char Channel_Input_Is: 3; // Channel Input (MUX[2:0])
faithcerebral 0:bd3a560e245e 256 unsigned char Channel_Setting_Reserved: 1; // Reserved (Must Write 0)
faithcerebral 0:bd3a560e245e 257 unsigned char Programmable_Gain_Setting: 3; // PGA Gain (GAIN[2:0])
faithcerebral 0:bd3a560e245e 258 unsigned char Power_Down_Channel: 1; // Power-Down (PD)
faithcerebral 0:bd3a560e245e 259 } ADS1x9x_Channel_Settings_Register_type;
faithcerebral 0:bd3a560e245e 260
faithcerebral 0:bd3a560e245e 261 enum Programmable_Gain_Setting_Type
faithcerebral 0:bd3a560e245e 262 {
faithcerebral 0:bd3a560e245e 263 DEFAULT_GAIN_OF_6 = 0,
faithcerebral 0:bd3a560e245e 264 GAIN_OF_1 = 1,
faithcerebral 0:bd3a560e245e 265 GAIN_OF_2 = 2,
faithcerebral 0:bd3a560e245e 266 GAIN_OF_3 = 3,
faithcerebral 0:bd3a560e245e 267 GAIN_OF_4 = 4,
faithcerebral 0:bd3a560e245e 268 GAIN_OF_8 = 5,
faithcerebral 0:bd3a560e245e 269 GAIN_OF_12 = 6
faithcerebral 0:bd3a560e245e 270 };
faithcerebral 0:bd3a560e245e 271
faithcerebral 0:bd3a560e245e 272 enum Channel_Input_Is_Type
faithcerebral 0:bd3a560e245e 273 {
faithcerebral 0:bd3a560e245e 274 DEFAULT_ADS1x9x_ELECTRODE_INPUT = 0,
faithcerebral 0:bd3a560e245e 275 ADS1x9x_INPUT_SHORTED = 1,
faithcerebral 0:bd3a560e245e 276 ADS1x9x_RIGHT_LEG_DETECT = 2,
faithcerebral 0:bd3a560e245e 277 ADS1x9x_ONE_HALF_DIGITAL_SUPPLY = 3,
faithcerebral 0:bd3a560e245e 278 ADS1x9x_TEMPERATURE_SENSOR = 4,
faithcerebral 0:bd3a560e245e 279 ADS1x9x_TEST_SIGNAL = 5,
faithcerebral 0:bd3a560e245e 280 ADS1x9x_RIGHT_LEG_DETECT_POSITIVE = 6,
faithcerebral 0:bd3a560e245e 281 ADS1x9x_RIGHT_LEG_DETECT_NEGATIVE = 7
faithcerebral 0:bd3a560e245e 282 };
faithcerebral 0:bd3a560e245e 283
faithcerebral 0:bd3a560e245e 284 // Used in Test Routine
faithcerebral 0:bd3a560e245e 285 #define ADS1x9x_CHANNEL_IS_DISABLED 0xFF
faithcerebral 0:bd3a560e245e 286
faithcerebral 0:bd3a560e245e 287 enum Power_Down_Channel_Type
faithcerebral 0:bd3a560e245e 288 {
faithcerebral 0:bd3a560e245e 289 DEFAULT_DISABLE_POWER_DOWN = 0,
faithcerebral 0:bd3a560e245e 290 ENABLE_POWER_DOWN = 1
faithcerebral 0:bd3a560e245e 291 };
faithcerebral 0:bd3a560e245e 292
faithcerebral 0:bd3a560e245e 293 typedef struct
faithcerebral 0:bd3a560e245e 294 {
faithcerebral 0:bd3a560e245e 295 unsigned char GPIO_Direction: 4; // Corresponding GPIOD (GPIOC[3:0])
faithcerebral 0:bd3a560e245e 296 unsigned char GPIO_Data: 4; // GPIO Data (GPIOD[4:7])
faithcerebral 0:bd3a560e245e 297 } ADS1x9x_GPIO_Settings_Register_type;
faithcerebral 0:bd3a560e245e 298
faithcerebral 0:bd3a560e245e 299 typedef struct
faithcerebral 0:bd3a560e245e 300 {
faithcerebral 0:bd3a560e245e 301 unsigned char Pace_Detect_Buffer: 1; // PACE detect buffer (PD_PACE')
faithcerebral 0:bd3a560e245e 302 unsigned char Odd_Pace_Channel_Select: 2; // PACE_OUT1 odd (PACEO[1:0]
faithcerebral 0:bd3a560e245e 303 unsigned char Even_Pace_Channel_Select: 2; // PACE_OUT2 even (PACEE[1:0])
faithcerebral 0:bd3a560e245e 304 unsigned char Bypass_Respiration_DC_Block_Capacitor: 1; // Respiration DC Block (RESP_NO_DCBLK)
faithcerebral 0:bd3a560e245e 305 unsigned char Channel_1_Internal_Demodulation: 1; // Channel 1 internal demodulation (RESP_DEMOD_EN1)
faithcerebral 0:bd3a560e245e 306 unsigned char Channel_2_Internal_Demodulation: 1; // Channel 2 internal demodulation (RESP_DEMOD_EN2)
faithcerebral 0:bd3a560e245e 307 } ADS1x9x_PACE_Detect_Settings_Register_type;
faithcerebral 0:bd3a560e245e 308
faithcerebral 0:bd3a560e245e 309
faithcerebral 0:bd3a560e245e 310 // ODD_PACE_CHANNEL_SELECT & EVEN_PACE_CHANNEL_SELECT bit field definition
faithcerebral 0:bd3a560e245e 311 enum Pace_Channel_Select_Type
faithcerebral 0:bd3a560e245e 312 {
faithcerebral 0:bd3a560e245e 313 DEFAULT_PACE_CHANNEL_IS_1 = 0,
faithcerebral 0:bd3a560e245e 314 DEFAULT_PACE_CHANNEL_IS_2 = 0,
faithcerebral 0:bd3a560e245e 315 PACE_CHANNEL_IS_3 = 1,
faithcerebral 0:bd3a560e245e 316 PACE_CHANNEL_IS_4 = 1,
faithcerebral 0:bd3a560e245e 317 PACE_CHANNEL_IS_5 = 2,
faithcerebral 0:bd3a560e245e 318 PACE_CHANNEL_IS_6 = 2,
faithcerebral 0:bd3a560e245e 319 PACE_CHANNEL_IS_7 = 3,
faithcerebral 0:bd3a560e245e 320 PACE_CHANNEL_IS_8 = 3
faithcerebral 0:bd3a560e245e 321 };
faithcerebral 0:bd3a560e245e 322
faithcerebral 0:bd3a560e245e 323 typedef struct
faithcerebral 0:bd3a560e245e 324 {
faithcerebral 0:bd3a560e245e 325 unsigned char Respiration_Clock_Source: 2; // Respiration Control Mode (RESP_CTRL[1:0])
faithcerebral 0:bd3a560e245e 326 unsigned char Respiration_Signal_Phase: 2; // Respiration Phase (RESP_PH[2:0])
faithcerebral 0:bd3a560e245e 327 unsigned char Respiration_Frequency: 1; // Respiration Frequency (RESP_FREQ)
faithcerebral 0:bd3a560e245e 328 unsigned char Channel_1_Internal_Modulation: 1; // Channel 1 internal modulation (RESP_MOD_EN1)
faithcerebral 0:bd3a560e245e 329 unsigned char Channel_2_Internal_Modulation: 1; // Channel 2 internal modulation (RESP_MOD_EN2)
faithcerebral 0:bd3a560e245e 330 } ADS1x9x_Respiration_Control_Register_type;
faithcerebral 0:bd3a560e245e 331
faithcerebral 0:bd3a560e245e 332 enum Respiration_Signal_Phase_Type
faithcerebral 0:bd3a560e245e 333 {
faithcerebral 0:bd3a560e245e 334 DEFAULT_PHASE_IS_22_5_DEGREES = 0,
faithcerebral 0:bd3a560e245e 335 PHASE_IS_45_DEGREES = 1,
faithcerebral 0:bd3a560e245e 336 PHASE_IS_67_5_DEGREES = 2,
faithcerebral 0:bd3a560e245e 337 PHASE_IS_90_DEGREES = 3,
faithcerebral 0:bd3a560e245e 338 PHASE_IS_112_5_DEGREES = 4,
faithcerebral 0:bd3a560e245e 339 PHASE_IS_135_DEGREES = 5,
faithcerebral 0:bd3a560e245e 340 PHASE_IS_157_5_DEGREES = 6,
faithcerebral 0:bd3a560e245e 341 PHASE_IS_180_DEGREES = 7
faithcerebral 0:bd3a560e245e 342 };
faithcerebral 0:bd3a560e245e 343
faithcerebral 0:bd3a560e245e 344 enum Respiration_Clock_Source_Type
faithcerebral 0:bd3a560e245e 345 {
faithcerebral 0:bd3a560e245e 346 DEFAULT_RESPIRATION_MODE_DISABLED = 0,
faithcerebral 0:bd3a560e245e 347 GPIO_3_IS_RESP_CLK_OUT_AND_GPIO_4_IS_RESP_PHASE_CLK_OUT = 1,
faithcerebral 0:bd3a560e245e 348 INTERNAL_RESPIRATION_USING_INTERNAL_CLOCK = 2,
faithcerebral 0:bd3a560e245e 349 GPIO_3_IS_RESP_CLK_IN_AND_GPIO_4_IS_RESP_PHASE_CLK_IN = 3
faithcerebral 0:bd3a560e245e 350 };
faithcerebral 0:bd3a560e245e 351
faithcerebral 0:bd3a560e245e 352 typedef struct
faithcerebral 0:bd3a560e245e 353 {
faithcerebral 0:bd3a560e245e 354 unsigned char Config_4_Reserved_2: 1; // Reserved (Must be One)
faithcerebral 0:bd3a560e245e 355 unsigned char Disable_Lead_Off_Comparators: 1; // Respiration Frequency (RESP_FREQ)
faithcerebral 0:bd3a560e245e 356 unsigned char Config_4_Reserved_1: 1; // Reserved (Must be Zero)
faithcerebral 0:bd3a560e245e 357 unsigned char Pulse_Mode: 1; // Pulse Mode (PULSE_MODE)
faithcerebral 0:bd3a560e245e 358 unsigned char Config_4_Reserved_0: 4; // Reserved (Must be Zero)
faithcerebral 0:bd3a560e245e 359 } ADS1x9x_Config_4_Register_type;
faithcerebral 0:bd3a560e245e 360
faithcerebral 0:bd3a560e245e 361 // CONFIG_2_RESERVED bit field definition
faithcerebral 0:bd3a560e245e 362 #define CONFIG_4_RESERVED_2_VALUE 1
faithcerebral 0:bd3a560e245e 363
faithcerebral 0:bd3a560e245e 364 //-----------------------------------------------------------------------------------------------------------------
faithcerebral 0:bd3a560e245e 365 enum ADS1x9x_Command_Values
faithcerebral 0:bd3a560e245e 366 {
faithcerebral 0:bd3a560e245e 367 // System Commands // ADS1x9x Command Definitions
faithcerebral 0:bd3a560e245e 368 WAKE_CONVERTER_FROM_SLEEP = 0x02, // WAKEUP
faithcerebral 0:bd3a560e245e 369 PLACE_CONVERTER_IN_SLEEP_MODE = 0x04, // SLEEP
faithcerebral 0:bd3a560e245e 370 RESET_CONVERTER = 0x06, // RESET
faithcerebral 0:bd3a560e245e 371 START_RESTART_CONVERSION = 0x08, // START
faithcerebral 0:bd3a560e245e 372 STOP_CONVERSION = 0x0A, // STOP
faithcerebral 0:bd3a560e245e 373
faithcerebral 0:bd3a560e245e 374 // Cal Commands
faithcerebral 0:bd3a560e245e 375 CALIBRATE_OFFSET_FOR_ALL_CHANNELS = 0x1A, // OFFCAL
faithcerebral 0:bd3a560e245e 376
faithcerebral 0:bd3a560e245e 377 // Data Read Commands
faithcerebral 0:bd3a560e245e 378 SET_READ_DATA_CONTINUOUSLY = 0x10, // RDATAC
faithcerebral 0:bd3a560e245e 379 STOP_READ_DATA_CONTINUOUSLY = 0x11, // SDATAC
faithcerebral 0:bd3a560e245e 380 READ_DATA_MANUALLY = 0x12, // RDATA
faithcerebral 0:bd3a560e245e 381
faithcerebral 0:bd3a560e245e 382 // Register Read Commands
faithcerebral 0:bd3a560e245e 383 DEFAULT_READ_NUMBER_OF_REGISTERS = 0x21,
faithcerebral 0:bd3a560e245e 384 DEFAULT_WRITE_NUMBER_OF_REGISTERS = 0x41
faithcerebral 0:bd3a560e245e 385 };
faithcerebral 0:bd3a560e245e 386
faithcerebral 0:bd3a560e245e 387 // Specific Register Read Commands
faithcerebral 0:bd3a560e245e 388 enum Specific_Register_Read_Command_Type
faithcerebral 0:bd3a560e245e 389 {
faithcerebral 0:bd3a560e245e 390 // Device Settings
faithcerebral 0:bd3a560e245e 391 READ_DEVICE_ID = 0x20,
faithcerebral 0:bd3a560e245e 392 // Glocal Settings Across Channels
faithcerebral 0:bd3a560e245e 393 READ_CONFIG_1_REGISTER = 0x21,
faithcerebral 0:bd3a560e245e 394 WRITE_CONFIG_1_REGISTER = 0x41,
faithcerebral 0:bd3a560e245e 395 READ_CONFIG_2_REGISTER = 0x22,
faithcerebral 0:bd3a560e245e 396 WRITE_CONFIG_2_REGISTER = 0x42,
faithcerebral 0:bd3a560e245e 397 READ_CONFIG_3_REGISTER = 0x23,
faithcerebral 0:bd3a560e245e 398 WRITE_CONFIG_3_REGISTER = 0x43,
faithcerebral 0:bd3a560e245e 399 READ_CONFIG_4_REGISTER = 0x37,
faithcerebral 0:bd3a560e245e 400 WRITE_CONFIG_4_REGISTER = 0x57,
faithcerebral 0:bd3a560e245e 401 READ_LEAD_OFF_CONTROL_REGISTER = 0x24,
faithcerebral 0:bd3a560e245e 402 WRITE_LEAD_OFF_CONTROL_REGISTER = 0x44,
faithcerebral 0:bd3a560e245e 403 // Channel Specific Settings
faithcerebral 0:bd3a560e245e 404 READ_CHANNEL_1_SET_REGISTER = 0x25,
faithcerebral 0:bd3a560e245e 405 WRITE_CHANNEL_1_SET_REGISTER = 0x45,
faithcerebral 0:bd3a560e245e 406 READ_CHANNEL_2_SET_REGISTER = 0x26,
faithcerebral 0:bd3a560e245e 407 WRITE_CHANNEL_2_SET_REGISTER = 0x46,
faithcerebral 0:bd3a560e245e 408 READ_CHANNEL_3_SET_REGISTER = 0x27,
faithcerebral 0:bd3a560e245e 409 WRITE_CHANNEL_3_SET_REGISTER = 0x47,
faithcerebral 0:bd3a560e245e 410 READ_CHANNEL_4_SET_REGISTER = 0x28,
faithcerebral 0:bd3a560e245e 411 WRITE_CHANNEL_4_SET_REGISTER = 0x48,
faithcerebral 0:bd3a560e245e 412 READ_CHANNEL_5_SET_REGISTER = 0x29,
faithcerebral 0:bd3a560e245e 413 WRITE_CHANNEL_5_SET_REGISTER = 0x49,
faithcerebral 0:bd3a560e245e 414 READ_CHANNEL_6_SET_REGISTER = 0x2A,
faithcerebral 0:bd3a560e245e 415 WRITE_CHANNEL_6_SET_REGISTER = 0x4A,
faithcerebral 0:bd3a560e245e 416 READ_CHANNEL_7_SET_REGISTER = 0x2B,
faithcerebral 0:bd3a560e245e 417 WRITE_CHANNEL_7_SET_REGISTER = 0x4B,
faithcerebral 0:bd3a560e245e 418 READ_CHANNEL_8_SET_REGISTER = 0x2C,
faithcerebral 0:bd3a560e245e 419 WRITE_CHANNEL_8_SET_REGISTER = 0x4C,
faithcerebral 0:bd3a560e245e 420
faithcerebral 0:bd3a560e245e 421 READ_RIGHT_LEG_DRIVE_SENSE_POSITIVE_REGISTER = 0x2D,
faithcerebral 0:bd3a560e245e 422 WRITE_RIGHT_LEG_DRIVE_SENSE_POSITIVE_REGISTER = 0x4D,
faithcerebral 0:bd3a560e245e 423 READ_RIGHT_LEG_DRIVE_SENSE_NEGATIVE_REGISTER = 0x2E,
faithcerebral 0:bd3a560e245e 424 WRITE_RIGHT_LEG_DRIVE_SENSE_NEGATIVE_REGISTER = 0x4E,
faithcerebral 0:bd3a560e245e 425
faithcerebral 0:bd3a560e245e 426 READ_LEAD_OFF_SENSE_POSITIVE_REGISTER = 0x2F,
faithcerebral 0:bd3a560e245e 427 WRITE_LEAD_OFF_SENSE_POSITIVE_REGISTER = 0x4F,
faithcerebral 0:bd3a560e245e 428 READ_LEAD_OFF_SENSE_NEGATIVE_REGISTER = 0x30,
faithcerebral 0:bd3a560e245e 429 WRITE_LEAD_OFF_SENSE_NEGATIVE_REGISTER = 0x50,
faithcerebral 0:bd3a560e245e 430
faithcerebral 0:bd3a560e245e 431 READ_LEAD_OFF_FLIP_REGISTER = 0x31,
faithcerebral 0:bd3a560e245e 432 WRITE_LEAD_OFF_FLIP_REGISTER = 0x51,
faithcerebral 0:bd3a560e245e 433 // Lead Off Status Registers
faithcerebral 0:bd3a560e245e 434 READ_LEAD_OFF_STATUS_POSITIVE_REGISTER = 0x32,
faithcerebral 0:bd3a560e245e 435 READ_LEAD_OFF_STATUS_NEGATIVE_REGISTER = 0x33,
faithcerebral 0:bd3a560e245e 436 // GPIO and OTHER Registers
faithcerebral 0:bd3a560e245e 437 READ_GENERAL_PORT_IO = 0x34,
faithcerebral 0:bd3a560e245e 438 WRITE_GENERAL_PORT_IO = 0x54,
faithcerebral 0:bd3a560e245e 439 READ_PACE_DETECT_REGISTER = 0x35,
faithcerebral 0:bd3a560e245e 440 WRITE_PACE_DETECT_REGISTER = 0x55,
faithcerebral 0:bd3a560e245e 441
faithcerebral 0:bd3a560e245e 442 READ_RESPIRATION_CONTROL_REGISTER = 0x36,
faithcerebral 0:bd3a560e245e 443 WRITE_RESPIRATION_CONTROL_REGISTER = 0x56,
faithcerebral 0:bd3a560e245e 444 READ_CONFIGURATION_CONTROL_REGISTER = 0x37,
faithcerebral 0:bd3a560e245e 445 WRITE_CONFIGURATION_CONTROL_REGISTER = 0x57
faithcerebral 0:bd3a560e245e 446 };
faithcerebral 0:bd3a560e245e 447
faithcerebral 0:bd3a560e245e 448 #define SINGLE_BYTE_READ_WRITE 0x00
faithcerebral 0:bd3a560e245e 449
faithcerebral 0:bd3a560e245e 450 #define ADS1x9x_SPI_WRITE_DELAY 0x04
faithcerebral 0:bd3a560e245e 451
faithcerebral 0:bd3a560e245e 452 #define ADS1x9x_TOP_REGISTER_SIZE 0x11
faithcerebral 0:bd3a560e245e 453 #define ADS1x9x_REGISTER_OFFSET 0x14
faithcerebral 0:bd3a560e245e 454 #define ADS1x9x_BOTTOM_REGISTER_SIZE 0x04
faithcerebral 0:bd3a560e245e 455
faithcerebral 0:bd3a560e245e 456 #define FETCH_DATA 0x00
faithcerebral 0:bd3a560e245e 457 #define EIGHT_BYTE_READ_WRITE 0x07
faithcerebral 0:bd3a560e245e 458 #define THIRTY_TWO_KSPS_SAMPLING_FREQ 0xC0
faithcerebral 0:bd3a560e245e 459 #define SIXTEEN_KSPS_SAMPLING_FREQ 0xC1
faithcerebral 0:bd3a560e245e 460 #define EIGHT_KSPS_SAMPLING_FREQ 0xC2
faithcerebral 0:bd3a560e245e 461 #define FOUR_KSPS_SAMPLING_FREQ 0xC3
faithcerebral 0:bd3a560e245e 462 #define TWO_KSPS_SAMPLING_FREQ 0xC4
faithcerebral 0:bd3a560e245e 463 #define ONE_KSPS_SAMPLING_FREQ 0xC5
faithcerebral 0:bd3a560e245e 464 #define FIVE_SPS_SAMPLING_FREQ 0xC6
faithcerebral 0:bd3a560e245e 465 #define INTERNAL_REF 0xC0
faithcerebral 0:bd3a560e245e 466
faithcerebral 0:bd3a560e245e 467 #define GAIN_ONE 0x10
faithcerebral 0:bd3a560e245e 468 #define GAIN_TWO 0x20
faithcerebral 0:bd3a560e245e 469 #define GAIN_THREE 0x30
faithcerebral 0:bd3a560e245e 470 #define GAIN_FOUR 0x40
faithcerebral 0:bd3a560e245e 471 #define GAIN_SIX 0x00
faithcerebral 0:bd3a560e245e 472 #define GAIN_EIGHT 0x50
faithcerebral 0:bd3a560e245e 473 #define GAIN_TWELVE 0x60
faithcerebral 0:bd3a560e245e 474 #define TURN_OFF_CHANNEL 0x80
faithcerebral 0:bd3a560e245e 475 #define INPUT_SHORT 0x01