Diff: targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c

Revision:

522:aee49fe30179

Parent:

496:543871686697

diff -r 149b1eddda04 -r aee49fe30179 targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c
--- a/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c	Thu Apr 23 08:30:10 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c	Thu Apr 23 09:15:08 2015 +0100
@@ -50,12 +50,43 @@
 
 void deepsleep(void)
 {
+#if defined(TARGET_MOTE_L152RC)
+    int8_t STOPEntry = PWR_STOPENTRY_WFI;
+#endif
+
     // Disable HAL tick interrupt
     TimMasterHandle.Instance = TIM5;
     __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
 
+#if defined(TARGET_MOTE_L152RC)
+    /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
+    MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), PWR_LOWPOWERREGULATOR_ON);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+    /* Select Stop mode entry --------------------------------------------------*/
+    if(STOPEntry == PWR_STOPENTRY_WFI)
+    {
+        /* Request Wait For Interrupt */
+        __WFI();
+    }
+    else
+    {
+        /* Request Wait For Event */
+        __SEV();
+        __WFE();
+        __WFE();
+    }
+    __NOP();
+    __NOP();
+    __NOP();
+    /* Reset SLEEPDEEP bit of Cortex System Control Register */
+    CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+#else
     // Request to enter STOP mode with regulator in low power mode
     HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+#endif
 
     // After wake-up from STOP reconfigure the PLL
     SetSysClock();