Thomas Byrne / mbed-src-stm32f030k6

Public fork of mbed-src to add generic stm32f030k6 target

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt@256:76fd9a263045, 2014-07-15 (annotated)

Committer:
mbed_official
Date:
Tue Jul 15 07:45:08 2014 +0100
Revision:
256:76fd9a263045
Parent:
20:4263a77256ae 
Synchronized with git revision 2031512f69c228e1d13ea89c39409db813af949f



Full URL: https://github.com/mbedmicro/mbed/commit/2031512f69c228e1d13ea89c39409db813af949f/



[LPC4330] Updated LPC4330_M4 port

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 mbed port to NXP LPC43xx
bogdanm 20:4263a77256ae 2 ========================
mbed_official 256:76fd9a263045 3 Updated: 07/11/14
bogdanm 20:4263a77256ae 4
mbed_official 256:76fd9a263045 5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
mbed_official 256:76fd9a263045 6 microcontroller package. This port allows mbed developers to take advantage
mbed_official 256:76fd9a263045 7 of the LPC43xx in their application using APIs that they are familiar with.
mbed_official 256:76fd9a263045 8 Some of the key features of the LPC43xx include:
bogdanm 20:4263a77256ae 9
bogdanm 20:4263a77256ae 10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
bogdanm 20:4263a77256ae 11 * Up to 264 KB SRAM, 1 MB internal flash
bogdanm 20:4263a77256ae 12 * Two High-speed USB 2.0 interfaces
bogdanm 20:4263a77256ae 13 * Ethernet MAC
bogdanm 20:4263a77256ae 14 * LCD interface
bogdanm 20:4263a77256ae 15 * Quad-SPI Flash Interface (SPIFI)
bogdanm 20:4263a77256ae 16 * State Configurable Timer (SCT)
bogdanm 20:4263a77256ae 17 * Serial GPIO (SGPIO)
bogdanm 20:4263a77256ae 18 * Up to 164 GPIO
bogdanm 20:4263a77256ae 19
bogdanm 20:4263a77256ae 20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
bogdanm 20:4263a77256ae 21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
bogdanm 20:4263a77256ae 22
bogdanm 20:4263a77256ae 23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
bogdanm 20:4263a77256ae 24
bogdanm 20:4263a77256ae 25 Compatibility
bogdanm 20:4263a77256ae 26 -------------
bogdanm 20:4263a77256ae 27 * This port has been tested with the following boards:
bogdanm 20:4263a77256ae 28 Board MCU RAM/Flash
bogdanm 20:4263a77256ae 29 Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
mbed_official 256:76fd9a263045 30 Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
mbed_official 256:76fd9a263045 31 Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
mbed_official 256:76fd9a263045 32 Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
bogdanm 20:4263a77256ae 33
mbed_official 256:76fd9a263045 34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
mbed_official 256:76fd9a263045 35 To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
mbed_official 256:76fd9a263045 36 for flash programming.
bogdanm 20:4263a77256ae 37
bogdanm 20:4263a77256ae 38 * This port should support NXP LPC43XX and LPC18XX variants with a single
bogdanm 20:4263a77256ae 39 codebase. The core declaration specifies the binaries to be built:
bogdanm 20:4263a77256ae 40 mbed define CMSIS define MCU Target
bogdanm 20:4263a77256ae 41 __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
bogdanm 20:4263a77256ae 42 __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
bogdanm 20:4263a77256ae 43 __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
bogdanm 20:4263a77256ae 44 These MCUs all share the peripheral IP, common driver code is feasible.
bogdanm 20:4263a77256ae 45 Yet each variant can have different memory segments, peripherals, etc.
bogdanm 20:4263a77256ae 46 Plus, each board design can integrate different external peripherals
bogdanm 20:4263a77256ae 47 or interfaces. A future release of the mbed SDK and its build tools will
bogdanm 20:4263a77256ae 48 support specifying the target board when building binaries. At this time
bogdanm 20:4263a77256ae 49 building binaries for different targets requires an external project or
bogdanm 20:4263a77256ae 50 Makefile.
bogdanm 20:4263a77256ae 51
mbed_official 256:76fd9a263045 52 * No testing has been done with LPC18xx hardware.
bogdanm 20:4263a77256ae 53
bogdanm 20:4263a77256ae 54 Notes
bogdanm 20:4263a77256ae 55 -----
bogdanm 20:4263a77256ae 56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
bogdanm 20:4263a77256ae 57 requiring different offsets for the SCU and GPIO registers. To simplify logic
bogdanm 20:4263a77256ae 58 the pin identifier encodes the offsets. Macros are used for decoding.
bogdanm 20:4263a77256ae 59 For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
bogdanm 20:4263a77256ae 60
bogdanm 20:4263a77256ae 61 P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
bogdanm 20:4263a77256ae 62
bogdanm 20:4263a77256ae 63 MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
bogdanm 20:4263a77256ae 64 MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
bogdanm 20:4263a77256ae 65
mbed_official 256:76fd9a263045 66 * Pin names use multiple aliases to support Arduino naming conventions as well
mbed_official 256:76fd9a263045 67 as others. For example, to use pin p21 on the Bambino 210 from mbed applications
mbed_official 256:76fd9a263045 68 the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
mbed_official 256:76fd9a263045 69 See the board pinout graphic and the PinNames.h for available aliases.
mbed_official 256:76fd9a263045 70
bogdanm 20:4263a77256ae 71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
bogdanm 20:4263a77256ae 72 GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
bogdanm 20:4263a77256ae 73 pin can only interrupt on the rising or falling edge, not both as required
bogdanm 20:4263a77256ae 74 by the mbed InterruptIn class. Also, group interrupts can't be cleared
bogdanm 20:4263a77256ae 75 individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
bogdanm 20:4263a77256ae 76 A future implementation may provide group interrupt support.
mbed_official 256:76fd9a263045 77
mbed_official 256:76fd9a263045 78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
mbed_official 256:76fd9a263045 79 build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
mbed_official 256:76fd9a263045 80 and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
mbed_official 256:76fd9a263045 81 when building the library.