Thomas Byrne
/
mbed-src-stm32f030k6
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mbed-src
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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_vcmp.h@525:c320967f86b9, 2015-04-28 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Apr 28 11:45:12 2015 +0100
- Revision:
- 525:c320967f86b9
Synchronized with git revision 299385b8331142b9dc524da7a986536f60b14553
Full URL: https://github.com/mbedmicro/mbed/commit/299385b8331142b9dc524da7a986536f60b14553/
Add in Silicon Labs targets with asynchronous API support
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 525:c320967f86b9 | 1 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 2 | * @file efm32zg_vcmp.h |
| mbed_official | 525:c320967f86b9 | 3 | * @brief EFM32ZG_VCMP register and bit field definitions |
| mbed_official | 525:c320967f86b9 | 4 | * @version 3.20.6 |
| mbed_official | 525:c320967f86b9 | 5 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 6 | * @section License |
| mbed_official | 525:c320967f86b9 | 7 | * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 525:c320967f86b9 | 8 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 9 | * |
| mbed_official | 525:c320967f86b9 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 525:c320967f86b9 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 525:c320967f86b9 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 525:c320967f86b9 | 13 | * |
| mbed_official | 525:c320967f86b9 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 525:c320967f86b9 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 525:c320967f86b9 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 525:c320967f86b9 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 525:c320967f86b9 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 525:c320967f86b9 | 19 | * |
| mbed_official | 525:c320967f86b9 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 525:c320967f86b9 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 525:c320967f86b9 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 525:c320967f86b9 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 525:c320967f86b9 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 525:c320967f86b9 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 525:c320967f86b9 | 26 | * |
| mbed_official | 525:c320967f86b9 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 525:c320967f86b9 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 525:c320967f86b9 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 525:c320967f86b9 | 30 | * |
| mbed_official | 525:c320967f86b9 | 31 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 32 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 33 | * @defgroup EFM32ZG_VCMP |
| mbed_official | 525:c320967f86b9 | 34 | * @{ |
| mbed_official | 525:c320967f86b9 | 35 | * @brief EFM32ZG_VCMP Register Declaration |
| mbed_official | 525:c320967f86b9 | 36 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 37 | typedef struct |
| mbed_official | 525:c320967f86b9 | 38 | { |
| mbed_official | 525:c320967f86b9 | 39 | __IO uint32_t CTRL; /**< Control Register */ |
| mbed_official | 525:c320967f86b9 | 40 | __IO uint32_t INPUTSEL; /**< Input Selection Register */ |
| mbed_official | 525:c320967f86b9 | 41 | __I uint32_t STATUS; /**< Status Register */ |
| mbed_official | 525:c320967f86b9 | 42 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| mbed_official | 525:c320967f86b9 | 43 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| mbed_official | 525:c320967f86b9 | 44 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| mbed_official | 525:c320967f86b9 | 45 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| mbed_official | 525:c320967f86b9 | 46 | } VCMP_TypeDef; /** @} */ |
| mbed_official | 525:c320967f86b9 | 47 | |
| mbed_official | 525:c320967f86b9 | 48 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 49 | * @defgroup EFM32ZG_VCMP_BitFields |
| mbed_official | 525:c320967f86b9 | 50 | * @{ |
| mbed_official | 525:c320967f86b9 | 51 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 52 | |
| mbed_official | 525:c320967f86b9 | 53 | /* Bit fields for VCMP CTRL */ |
| mbed_official | 525:c320967f86b9 | 54 | #define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 55 | #define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 56 | #define VCMP_CTRL_EN (0x1UL << 0) /**< Voltage Supply Comparator Enable */ |
| mbed_official | 525:c320967f86b9 | 57 | #define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */ |
| mbed_official | 525:c320967f86b9 | 58 | #define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */ |
| mbed_official | 525:c320967f86b9 | 59 | #define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 60 | #define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 61 | #define VCMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ |
| mbed_official | 525:c320967f86b9 | 62 | #define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */ |
| mbed_official | 525:c320967f86b9 | 63 | #define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */ |
| mbed_official | 525:c320967f86b9 | 64 | #define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 65 | #define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 66 | #define VCMP_CTRL_HYSTEN (0x1UL << 4) /**< Hysteresis Enable */ |
| mbed_official | 525:c320967f86b9 | 67 | #define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */ |
| mbed_official | 525:c320967f86b9 | 68 | #define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */ |
| mbed_official | 525:c320967f86b9 | 69 | #define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 70 | #define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 71 | #define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */ |
| mbed_official | 525:c320967f86b9 | 72 | #define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */ |
| mbed_official | 525:c320967f86b9 | 73 | #define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 74 | #define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 75 | #define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 76 | #define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 77 | #define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 78 | #define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 79 | #define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 80 | #define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 81 | #define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 82 | #define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 83 | #define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 84 | #define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 85 | #define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 86 | #define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 87 | #define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 88 | #define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 89 | #define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 90 | #define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 91 | #define VCMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */ |
| mbed_official | 525:c320967f86b9 | 92 | #define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */ |
| mbed_official | 525:c320967f86b9 | 93 | #define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */ |
| mbed_official | 525:c320967f86b9 | 94 | #define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 95 | #define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 96 | #define VCMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */ |
| mbed_official | 525:c320967f86b9 | 97 | #define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */ |
| mbed_official | 525:c320967f86b9 | 98 | #define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */ |
| mbed_official | 525:c320967f86b9 | 99 | #define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 100 | #define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 101 | #define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 102 | #define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 103 | #define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 104 | #define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 105 | #define VCMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */ |
| mbed_official | 525:c320967f86b9 | 106 | #define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */ |
| mbed_official | 525:c320967f86b9 | 107 | #define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */ |
| mbed_official | 525:c320967f86b9 | 108 | #define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 109 | #define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 110 | |
| mbed_official | 525:c320967f86b9 | 111 | /* Bit fields for VCMP INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 112 | #define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 113 | #define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 114 | #define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */ |
| mbed_official | 525:c320967f86b9 | 115 | #define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */ |
| mbed_official | 525:c320967f86b9 | 116 | #define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 117 | #define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 118 | #define VCMP_INPUTSEL_LPREF (0x1UL << 8) /**< Low Power Reference */ |
| mbed_official | 525:c320967f86b9 | 119 | #define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */ |
| mbed_official | 525:c320967f86b9 | 120 | #define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */ |
| mbed_official | 525:c320967f86b9 | 121 | #define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 122 | #define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 123 | |
| mbed_official | 525:c320967f86b9 | 124 | /* Bit fields for VCMP STATUS */ |
| mbed_official | 525:c320967f86b9 | 125 | #define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 126 | #define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 127 | #define VCMP_STATUS_VCMPACT (0x1UL << 0) /**< Voltage Supply Comparator Active */ |
| mbed_official | 525:c320967f86b9 | 128 | #define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */ |
| mbed_official | 525:c320967f86b9 | 129 | #define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */ |
| mbed_official | 525:c320967f86b9 | 130 | #define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 131 | #define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 132 | #define VCMP_STATUS_VCMPOUT (0x1UL << 1) /**< Voltage Supply Comparator Output */ |
| mbed_official | 525:c320967f86b9 | 133 | #define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */ |
| mbed_official | 525:c320967f86b9 | 134 | #define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */ |
| mbed_official | 525:c320967f86b9 | 135 | #define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 136 | #define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 137 | |
| mbed_official | 525:c320967f86b9 | 138 | /* Bit fields for VCMP IEN */ |
| mbed_official | 525:c320967f86b9 | 139 | #define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 140 | #define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 141 | #define VCMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 142 | #define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 143 | #define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 144 | #define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 145 | #define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 146 | #define VCMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 147 | #define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 148 | #define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 149 | #define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 150 | #define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 151 | |
| mbed_official | 525:c320967f86b9 | 152 | /* Bit fields for VCMP IF */ |
| mbed_official | 525:c320967f86b9 | 153 | #define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */ |
| mbed_official | 525:c320967f86b9 | 154 | #define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */ |
| mbed_official | 525:c320967f86b9 | 155 | #define VCMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 156 | #define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 157 | #define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 158 | #define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */ |
| mbed_official | 525:c320967f86b9 | 159 | #define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IF */ |
| mbed_official | 525:c320967f86b9 | 160 | #define VCMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 161 | #define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 162 | #define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 163 | #define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */ |
| mbed_official | 525:c320967f86b9 | 164 | #define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IF */ |
| mbed_official | 525:c320967f86b9 | 165 | |
| mbed_official | 525:c320967f86b9 | 166 | /* Bit fields for VCMP IFS */ |
| mbed_official | 525:c320967f86b9 | 167 | #define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 168 | #define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 169 | #define VCMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 170 | #define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 171 | #define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 172 | #define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 173 | #define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 174 | #define VCMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 175 | #define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 176 | #define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 177 | #define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 178 | #define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 179 | |
| mbed_official | 525:c320967f86b9 | 180 | /* Bit fields for VCMP IFC */ |
| mbed_official | 525:c320967f86b9 | 181 | #define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 182 | #define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 183 | #define VCMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 184 | #define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 185 | #define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 186 | #define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 187 | #define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 188 | #define VCMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 189 | #define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 190 | #define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 191 | #define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 192 | #define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 193 | |
| mbed_official | 525:c320967f86b9 | 194 | /** @} End of group EFM32ZG_VCMP */ |
| mbed_official | 525:c320967f86b9 | 195 | |
| mbed_official | 525:c320967f86b9 | 196 |