Thomas Byrne
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mbed-src-stm32f030k6
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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_rmu.h@525:c320967f86b9, 2015-04-28 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Apr 28 11:45:12 2015 +0100
- Revision:
- 525:c320967f86b9
Synchronized with git revision 299385b8331142b9dc524da7a986536f60b14553
Full URL: https://github.com/mbedmicro/mbed/commit/299385b8331142b9dc524da7a986536f60b14553/
Add in Silicon Labs targets with asynchronous API support
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 525:c320967f86b9 | 1 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 2 | * @file efm32lg_rmu.h |
| mbed_official | 525:c320967f86b9 | 3 | * @brief EFM32LG_RMU register and bit field definitions |
| mbed_official | 525:c320967f86b9 | 4 | * @version 3.20.6 |
| mbed_official | 525:c320967f86b9 | 5 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 6 | * @section License |
| mbed_official | 525:c320967f86b9 | 7 | * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 525:c320967f86b9 | 8 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 9 | * |
| mbed_official | 525:c320967f86b9 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 525:c320967f86b9 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 525:c320967f86b9 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 525:c320967f86b9 | 13 | * |
| mbed_official | 525:c320967f86b9 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 525:c320967f86b9 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 525:c320967f86b9 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 525:c320967f86b9 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 525:c320967f86b9 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 525:c320967f86b9 | 19 | * |
| mbed_official | 525:c320967f86b9 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 525:c320967f86b9 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 525:c320967f86b9 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 525:c320967f86b9 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 525:c320967f86b9 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 525:c320967f86b9 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 525:c320967f86b9 | 26 | * |
| mbed_official | 525:c320967f86b9 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 525:c320967f86b9 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 525:c320967f86b9 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 525:c320967f86b9 | 30 | * |
| mbed_official | 525:c320967f86b9 | 31 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 32 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 33 | * @defgroup EFM32LG_RMU |
| mbed_official | 525:c320967f86b9 | 34 | * @{ |
| mbed_official | 525:c320967f86b9 | 35 | * @brief EFM32LG_RMU Register Declaration |
| mbed_official | 525:c320967f86b9 | 36 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 37 | typedef struct |
| mbed_official | 525:c320967f86b9 | 38 | { |
| mbed_official | 525:c320967f86b9 | 39 | __IO uint32_t CTRL; /**< Control Register */ |
| mbed_official | 525:c320967f86b9 | 40 | __I uint32_t RSTCAUSE; /**< Reset Cause Register */ |
| mbed_official | 525:c320967f86b9 | 41 | __O uint32_t CMD; /**< Command Register */ |
| mbed_official | 525:c320967f86b9 | 42 | } RMU_TypeDef; /** @} */ |
| mbed_official | 525:c320967f86b9 | 43 | |
| mbed_official | 525:c320967f86b9 | 44 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 45 | * @defgroup EFM32LG_RMU_BitFields |
| mbed_official | 525:c320967f86b9 | 46 | * @{ |
| mbed_official | 525:c320967f86b9 | 47 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 48 | |
| mbed_official | 525:c320967f86b9 | 49 | /* Bit fields for RMU CTRL */ |
| mbed_official | 525:c320967f86b9 | 50 | #define _RMU_CTRL_RESETVALUE 0x00000002UL /**< Default value for RMU_CTRL */ |
| mbed_official | 525:c320967f86b9 | 51 | #define _RMU_CTRL_MASK 0x00000003UL /**< Mask for RMU_CTRL */ |
| mbed_official | 525:c320967f86b9 | 52 | #define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */ |
| mbed_official | 525:c320967f86b9 | 53 | #define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */ |
| mbed_official | 525:c320967f86b9 | 54 | #define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */ |
| mbed_official | 525:c320967f86b9 | 55 | #define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ |
| mbed_official | 525:c320967f86b9 | 56 | #define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ |
| mbed_official | 525:c320967f86b9 | 57 | #define RMU_CTRL_BURSTEN (0x1UL << 1) /**< Backup domain reset enable */ |
| mbed_official | 525:c320967f86b9 | 58 | #define _RMU_CTRL_BURSTEN_SHIFT 1 /**< Shift value for RMU_BURSTEN */ |
| mbed_official | 525:c320967f86b9 | 59 | #define _RMU_CTRL_BURSTEN_MASK 0x2UL /**< Bit mask for RMU_BURSTEN */ |
| mbed_official | 525:c320967f86b9 | 60 | #define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for RMU_CTRL */ |
| mbed_official | 525:c320967f86b9 | 61 | #define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_CTRL */ |
| mbed_official | 525:c320967f86b9 | 62 | |
| mbed_official | 525:c320967f86b9 | 63 | /* Bit fields for RMU RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 64 | #define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 65 | #define _RMU_RSTCAUSE_MASK 0x0000FFFFUL /**< Mask for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 66 | #define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */ |
| mbed_official | 525:c320967f86b9 | 67 | #define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ |
| mbed_official | 525:c320967f86b9 | 68 | #define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ |
| mbed_official | 525:c320967f86b9 | 69 | #define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 70 | #define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 71 | #define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */ |
| mbed_official | 525:c320967f86b9 | 72 | #define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */ |
| mbed_official | 525:c320967f86b9 | 73 | #define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */ |
| mbed_official | 525:c320967f86b9 | 74 | #define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 75 | #define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 76 | #define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */ |
| mbed_official | 525:c320967f86b9 | 77 | #define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */ |
| mbed_official | 525:c320967f86b9 | 78 | #define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */ |
| mbed_official | 525:c320967f86b9 | 79 | #define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 80 | #define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 81 | #define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */ |
| mbed_official | 525:c320967f86b9 | 82 | #define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */ |
| mbed_official | 525:c320967f86b9 | 83 | #define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */ |
| mbed_official | 525:c320967f86b9 | 84 | #define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 85 | #define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 86 | #define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */ |
| mbed_official | 525:c320967f86b9 | 87 | #define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */ |
| mbed_official | 525:c320967f86b9 | 88 | #define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */ |
| mbed_official | 525:c320967f86b9 | 89 | #define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 90 | #define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 91 | #define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */ |
| mbed_official | 525:c320967f86b9 | 92 | #define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */ |
| mbed_official | 525:c320967f86b9 | 93 | #define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */ |
| mbed_official | 525:c320967f86b9 | 94 | #define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 95 | #define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 96 | #define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */ |
| mbed_official | 525:c320967f86b9 | 97 | #define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */ |
| mbed_official | 525:c320967f86b9 | 98 | #define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */ |
| mbed_official | 525:c320967f86b9 | 99 | #define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 100 | #define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 101 | #define RMU_RSTCAUSE_EM4RST (0x1UL << 7) /**< EM4 Reset */ |
| mbed_official | 525:c320967f86b9 | 102 | #define _RMU_RSTCAUSE_EM4RST_SHIFT 7 /**< Shift value for RMU_EM4RST */ |
| mbed_official | 525:c320967f86b9 | 103 | #define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL /**< Bit mask for RMU_EM4RST */ |
| mbed_official | 525:c320967f86b9 | 104 | #define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 105 | #define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 106 | #define RMU_RSTCAUSE_EM4WURST (0x1UL << 8) /**< EM4 Wake-up Reset */ |
| mbed_official | 525:c320967f86b9 | 107 | #define _RMU_RSTCAUSE_EM4WURST_SHIFT 8 /**< Shift value for RMU_EM4WURST */ |
| mbed_official | 525:c320967f86b9 | 108 | #define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL /**< Bit mask for RMU_EM4WURST */ |
| mbed_official | 525:c320967f86b9 | 109 | #define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 110 | #define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 111 | #define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9) /**< AVDD0 Bod Reset */ |
| mbed_official | 525:c320967f86b9 | 112 | #define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9 /**< Shift value for RMU_BODAVDD0 */ |
| mbed_official | 525:c320967f86b9 | 113 | #define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL /**< Bit mask for RMU_BODAVDD0 */ |
| mbed_official | 525:c320967f86b9 | 114 | #define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 115 | #define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 116 | #define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10) /**< AVDD1 Bod Reset */ |
| mbed_official | 525:c320967f86b9 | 117 | #define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10 /**< Shift value for RMU_BODAVDD1 */ |
| mbed_official | 525:c320967f86b9 | 118 | #define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL /**< Bit mask for RMU_BODAVDD1 */ |
| mbed_official | 525:c320967f86b9 | 119 | #define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 120 | #define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 121 | #define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11) /**< Backup Brown Out Detector, VDD_DREG */ |
| mbed_official | 525:c320967f86b9 | 122 | #define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11 /**< Shift value for RMU_BUBODVDDDREG */ |
| mbed_official | 525:c320967f86b9 | 123 | #define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL /**< Bit mask for RMU_BUBODVDDDREG */ |
| mbed_official | 525:c320967f86b9 | 124 | #define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 125 | #define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT (_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 126 | #define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12) /**< Backup Brown Out Detector, BU_VIN */ |
| mbed_official | 525:c320967f86b9 | 127 | #define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12 /**< Shift value for RMU_BUBODBUVIN */ |
| mbed_official | 525:c320967f86b9 | 128 | #define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL /**< Bit mask for RMU_BUBODBUVIN */ |
| mbed_official | 525:c320967f86b9 | 129 | #define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 130 | #define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT (_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 131 | #define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13) /**< Backup Brown Out Detector Unregulated Domain */ |
| mbed_official | 525:c320967f86b9 | 132 | #define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13 /**< Shift value for RMU_BUBODUNREG */ |
| mbed_official | 525:c320967f86b9 | 133 | #define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL /**< Bit mask for RMU_BUBODUNREG */ |
| mbed_official | 525:c320967f86b9 | 134 | #define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 135 | #define RMU_RSTCAUSE_BUBODUNREG_DEFAULT (_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 136 | #define RMU_RSTCAUSE_BUBODREG (0x1UL << 14) /**< Backup Brown Out Detector Regulated Domain */ |
| mbed_official | 525:c320967f86b9 | 137 | #define _RMU_RSTCAUSE_BUBODREG_SHIFT 14 /**< Shift value for RMU_BUBODREG */ |
| mbed_official | 525:c320967f86b9 | 138 | #define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL /**< Bit mask for RMU_BUBODREG */ |
| mbed_official | 525:c320967f86b9 | 139 | #define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 140 | #define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 141 | #define RMU_RSTCAUSE_BUMODERST (0x1UL << 15) /**< Backup mode reset */ |
| mbed_official | 525:c320967f86b9 | 142 | #define _RMU_RSTCAUSE_BUMODERST_SHIFT 15 /**< Shift value for RMU_BUMODERST */ |
| mbed_official | 525:c320967f86b9 | 143 | #define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL /**< Bit mask for RMU_BUMODERST */ |
| mbed_official | 525:c320967f86b9 | 144 | #define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 145 | #define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 15) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
| mbed_official | 525:c320967f86b9 | 146 | |
| mbed_official | 525:c320967f86b9 | 147 | /* Bit fields for RMU CMD */ |
| mbed_official | 525:c320967f86b9 | 148 | #define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ |
| mbed_official | 525:c320967f86b9 | 149 | #define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ |
| mbed_official | 525:c320967f86b9 | 150 | #define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ |
| mbed_official | 525:c320967f86b9 | 151 | #define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ |
| mbed_official | 525:c320967f86b9 | 152 | #define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ |
| mbed_official | 525:c320967f86b9 | 153 | #define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ |
| mbed_official | 525:c320967f86b9 | 154 | #define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ |
| mbed_official | 525:c320967f86b9 | 155 | |
| mbed_official | 525:c320967f86b9 | 156 | /** @} End of group EFM32LG_RMU */ |
| mbed_official | 525:c320967f86b9 | 157 | |
| mbed_official | 525:c320967f86b9 | 158 |