Éric Bisson / Mbed 2 deprecated S5info_APP4

app4

Dependencies:   mbed-rtos mbed CRC16

Fork of S5info_APP2 by Éric Bisson

main.cpp@14:bd909277eb13, 2017-03-07 (annotated)

Committer:
ericbisson
Date:
Tue Mar 07 04:39:57 2017 +0000
Revision:
14:bd909277eb13
Parent:
11:b27d1a83f688
Child:
15:7c2e70c36b98
temp commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ericbisson 14:bd909277eb13 1 #include "read.h"
ericbisson 1:b3ae0d9f02ad 2
ericbisson 14:bd909277eb13 3 Serial pc(USBTX, USBRX);
ericbisson 14:bd909277eb13 4 DigitalOut out(p8);
ericbisson 2:c6465d4e82d2 5
ericbisson 14:bd909277eb13 6 void initTimers()
ericbisson 14:bd909277eb13 7 {
ericbisson 14:bd909277eb13 8 //Timer 1 (match)
ericbisson 14:bd909277eb13 9 LPC_SC->PCLKSEL0 |= (1 << 4); // pclk = cclk timer1
ericbisson 14:bd909277eb13 10 LPC_SC->PCONP |= (1 << 2); // timer1 power on
ericbisson 14:bd909277eb13 11 LPC_TIM1->MR0 = CLOCKS_TO_SECOND / 100; // 100 ms
ericbisson 14:bd909277eb13 12 LPC_TIM1->MCR = 3; // interrupt and reset control
ericbisson 14:bd909277eb13 13 LPC_TIM1->EMR = (3 << 4); // Interrupt & reset timer on match
ericbisson 14:bd909277eb13 14 NVIC_EnableIRQ(TIMER1_IRQn); // enable timer interrupt
ericbisson 14:bd909277eb13 15 LPC_TIM1->TCR = 1; // enable Timer
ericbisson 14:bd909277eb13 16
ericbisson 14:bd909277eb13 17 //Timer 2 (cap)
ericbisson 14:bd909277eb13 18 LPC_SC->PCLKSEL1 |= (1 << 12); // pclk = cclk timer2
ericbisson 14:bd909277eb13 19 LPC_SC->PCONP |= (1 << 22); // timer2 power on
ericbisson 14:bd909277eb13 20 LPC_TIM2->TC = 0; // clear timer counter
ericbisson 14:bd909277eb13 21 LPC_TIM2->PC = 0; // clear prescale counter
ericbisson 14:bd909277eb13 22 LPC_TIM2->PR = 0; // clear prescale register
ericbisson 14:bd909277eb13 23 LPC_TIM2->TCR |= (1 << 1); // reset timer
ericbisson 14:bd909277eb13 24 LPC_TIM2->TCR &= ~(1 << 1); // release reset
ericbisson 14:bd909277eb13 25 LPC_TIM2->IR = 0xFFFFFFFF; // clear interrupt register
ericbisson 14:bd909277eb13 26 LPC_TIM2->CCR |= 0x0000007; // enable rising-edge and falling-edge capture
ericbisson 14:bd909277eb13 27 NVIC_EnableIRQ(TIMER2_IRQn); // enable timer interrupt
ericbisson 14:bd909277eb13 28 LPC_TIM2->TCR = 1; // start Timer
ericbisson 14:bd909277eb13 29 }
JoeyDionne 11:b27d1a83f688 30
ericbisson 14:bd909277eb13 31 bool bTimer1 = false;
ericbisson 14:bd909277eb13 32 extern "C" void TIMER1_IRQHandler()
ericbisson 14:bd909277eb13 33 {
ericbisson 14:bd909277eb13 34 if ((LPC_TIM1->IR & 0x01) == 0x01)
ericbisson 14:bd909277eb13 35 {
ericbisson 14:bd909277eb13 36 bTimer1 = !bTimer1;
ericbisson 14:bd909277eb13 37
ericbisson 14:bd909277eb13 38 LPC_TIM1->IR |= 1 << 0; // clear
ericbisson 14:bd909277eb13 39 }
ericbisson 1:b3ae0d9f02ad 40 }
ericbisson 1:b3ae0d9f02ad 41
ericbisson 14:bd909277eb13 42 int sumClocks = 0;
ericbisson 14:bd909277eb13 43 int PeriodLength = 0;
ericbisson 14:bd909277eb13 44 bool bReceivedFirstBit = false;
ericbisson 14:bd909277eb13 45 extern "C" void TIMER2_IRQHandler()
ericbisson 7:5501dbea5650 46 {
ericbisson 14:bd909277eb13 47 if (PeriodLength > 0)
ericbisson 7:5501dbea5650 48 {
ericbisson 14:bd909277eb13 49 if (LPC_TIM2->CR0 >= PeriodLength*1.5 || (sumClocks + clocks) >= PeriodLength*1.5)
ericbisson 8:5b87b1f9d91f 50 {
ericbisson 14:bd909277eb13 51 sumClocks = 0;
ericbisson 14:bd909277eb13 52
ericbisson 14:bd909277eb13 53 ThreadLecture.signal_set(1);
ericbisson 14:bd909277eb13 54 }
ericbisson 14:bd909277eb13 55 else
ericbisson 14:bd909277eb13 56 {
ericbisson 14:bd909277eb13 57 sumClocks += LPC_TIM2->CR0;
ericbisson 8:5b87b1f9d91f 58 }
ericbisson 1:b3ae0d9f02ad 59 }
ericbisson 14:bd909277eb13 60 else if (bReceivedFirstBit)
ericbisson 14:bd909277eb13 61 {
ericbisson 14:bd909277eb13 62 PeriodLength = LPC_TIM2->CR0 / 2;
ericbisson 14:bd909277eb13 63 ThreadLecture.signal_set(1);
ericbisson 14:bd909277eb13 64 }
ericbisson 14:bd909277eb13 65 else
ericbisson 14:bd909277eb13 66 {
ericbisson 14:bd909277eb13 67 bReceivedFirstBit = true;
ericbisson 14:bd909277eb13 68 ThreadLecture.signal_set(1);
ericbisson 14:bd909277eb13 69 }
ericbisson 14:bd909277eb13 70
ericbisson 14:bd909277eb13 71 LPC_TIM2->TC = 0;
ericbisson 14:bd909277eb13 72 LPC_TIM2->IR |= 0xFFFFFFFF; // clear
ericbisson 14:bd909277eb13 73 }
ericbisson 4:87e9b434bb4d 74
ericbisson 2:c6465d4e82d2 75 int main() {
ericbisson 14:bd909277eb13 76 LPC_PINCON->PINSEL0 |= (3 << 8); // pin30
ericbisson 14:bd909277eb13 77 initTimers();
ericbisson 14:bd909277eb13 78 ThreadLecture.attach(read);
ericbisson 14:bd909277eb13 79 ThreadLecture.start();
ericbisson 0:c637467eeb8f 80
ericbisson 3:3ecbcc05bc85 81 while(true) {
ericbisson 0:c637467eeb8f 82 }
ericbisson 7:5501dbea5650 83 };