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version_2.0

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TARGET_NRF51822/nrf51_bitfields.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
Parent:
80:8e73be2a2ac1 
version_2.0

Who changed what in which revision?

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emilmont 80:8e73be2a2ac1 1 /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
emilmont 80:8e73be2a2ac1 2 *
emilmont 80:8e73be2a2ac1 3 * The information contained herein is property of Nordic Semiconductor ASA.
emilmont 80:8e73be2a2ac1 4 * Terms and conditions of usage are described in detail in NORDIC
emilmont 80:8e73be2a2ac1 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * Licensees are granted free, non-transferable use of the information. NO
emilmont 80:8e73be2a2ac1 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
emilmont 80:8e73be2a2ac1 9 * the file.
emilmont 80:8e73be2a2ac1 10 *
emilmont 80:8e73be2a2ac1 11 */
emilmont 80:8e73be2a2ac1 12
emilmont 80:8e73be2a2ac1 13
emilmont 80:8e73be2a2ac1 14 #ifndef __NRF51_BITS_H
emilmont 80:8e73be2a2ac1 15 #define __NRF51_BITS_H
emilmont 80:8e73be2a2ac1 16
emilmont 80:8e73be2a2ac1 17 /*lint ++flb "Enter library region */
emilmont 80:8e73be2a2ac1 18
emilmont 80:8e73be2a2ac1 19 //#include <core_cm0.h>
emilmont 80:8e73be2a2ac1 20
emilmont 80:8e73be2a2ac1 21 /* Peripheral: AAR */
emilmont 80:8e73be2a2ac1 22 /* Description: Accelerated Address Resolver. */
emilmont 80:8e73be2a2ac1 23
emilmont 80:8e73be2a2ac1 24 /* Register: AAR_INTENSET */
emilmont 80:8e73be2a2ac1 25 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 26
emilmont 80:8e73be2a2ac1 27 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
emilmont 80:8e73be2a2ac1 28 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
emilmont 80:8e73be2a2ac1 29 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
emilmont 80:8e73be2a2ac1 30 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 31 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 32 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 33
emilmont 80:8e73be2a2ac1 34 /* Bit 1 : Enable interrupt on RESOLVED event. */
emilmont 80:8e73be2a2ac1 35 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
emilmont 80:8e73be2a2ac1 36 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
emilmont 80:8e73be2a2ac1 37 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 38 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 39 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 40
emilmont 80:8e73be2a2ac1 41 /* Bit 0 : Enable interrupt on END event. */
emilmont 80:8e73be2a2ac1 42 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
emilmont 80:8e73be2a2ac1 43 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
emilmont 80:8e73be2a2ac1 44 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 45 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 46 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 47
emilmont 80:8e73be2a2ac1 48 /* Register: AAR_INTENCLR */
emilmont 80:8e73be2a2ac1 49 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 50
emilmont 80:8e73be2a2ac1 51 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
emilmont 80:8e73be2a2ac1 52 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
emilmont 80:8e73be2a2ac1 53 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
emilmont 80:8e73be2a2ac1 54 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 55 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 56 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 57
emilmont 80:8e73be2a2ac1 58 /* Bit 1 : Disable interrupt on RESOLVED event. */
emilmont 80:8e73be2a2ac1 59 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
emilmont 80:8e73be2a2ac1 60 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
emilmont 80:8e73be2a2ac1 61 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 62 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 63 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 64
emilmont 80:8e73be2a2ac1 65 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
emilmont 80:8e73be2a2ac1 66 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
emilmont 80:8e73be2a2ac1 67 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
emilmont 80:8e73be2a2ac1 68 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 69 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 70 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 71
emilmont 80:8e73be2a2ac1 72 /* Register: AAR_STATUS */
emilmont 80:8e73be2a2ac1 73 /* Description: Resolution status. */
emilmont 80:8e73be2a2ac1 74
emilmont 80:8e73be2a2ac1 75 /* Bits 3..0 : The IRK used last time an address was resolved. */
emilmont 80:8e73be2a2ac1 76 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
emilmont 80:8e73be2a2ac1 77 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
emilmont 80:8e73be2a2ac1 78
emilmont 80:8e73be2a2ac1 79 /* Register: AAR_ENABLE */
emilmont 80:8e73be2a2ac1 80 /* Description: Enable AAR. */
emilmont 80:8e73be2a2ac1 81
emilmont 80:8e73be2a2ac1 82 /* Bits 1..0 : Enable AAR. */
emilmont 80:8e73be2a2ac1 83 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 84 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 85 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
emilmont 80:8e73be2a2ac1 86 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
emilmont 80:8e73be2a2ac1 87
emilmont 80:8e73be2a2ac1 88 /* Register: AAR_NIRK */
emilmont 80:8e73be2a2ac1 89 /* Description: Number of Identity root Keys in the IRK data structure. */
emilmont 80:8e73be2a2ac1 90
emilmont 80:8e73be2a2ac1 91 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
emilmont 80:8e73be2a2ac1 92 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
emilmont 80:8e73be2a2ac1 93 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
emilmont 80:8e73be2a2ac1 94
emilmont 80:8e73be2a2ac1 95 /* Register: AAR_POWER */
emilmont 80:8e73be2a2ac1 96 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 97
emilmont 80:8e73be2a2ac1 98 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 99 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 100 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 101 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 102 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 103
emilmont 80:8e73be2a2ac1 104
emilmont 80:8e73be2a2ac1 105 /* Peripheral: ADC */
emilmont 80:8e73be2a2ac1 106 /* Description: Analog to digital converter. */
emilmont 80:8e73be2a2ac1 107
emilmont 80:8e73be2a2ac1 108 /* Register: ADC_INTENSET */
emilmont 80:8e73be2a2ac1 109 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 110
emilmont 80:8e73be2a2ac1 111 /* Bit 0 : Enable interrupt on END event. */
emilmont 80:8e73be2a2ac1 112 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
emilmont 80:8e73be2a2ac1 113 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
emilmont 80:8e73be2a2ac1 114 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 115 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 116 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 117
emilmont 80:8e73be2a2ac1 118 /* Register: ADC_INTENCLR */
emilmont 80:8e73be2a2ac1 119 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 120
emilmont 80:8e73be2a2ac1 121 /* Bit 0 : Disable interrupt on END event. */
emilmont 80:8e73be2a2ac1 122 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
emilmont 80:8e73be2a2ac1 123 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
emilmont 80:8e73be2a2ac1 124 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 125 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 126 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 127
emilmont 80:8e73be2a2ac1 128 /* Register: ADC_BUSY */
emilmont 80:8e73be2a2ac1 129 /* Description: ADC busy register. */
emilmont 80:8e73be2a2ac1 130
emilmont 80:8e73be2a2ac1 131 /* Bit 0 : ADC busy register. */
emilmont 80:8e73be2a2ac1 132 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
emilmont 80:8e73be2a2ac1 133 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
emilmont 80:8e73be2a2ac1 134 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
emilmont 80:8e73be2a2ac1 135 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
emilmont 80:8e73be2a2ac1 136
emilmont 80:8e73be2a2ac1 137 /* Register: ADC_ENABLE */
emilmont 80:8e73be2a2ac1 138 /* Description: ADC enable. */
emilmont 80:8e73be2a2ac1 139
emilmont 80:8e73be2a2ac1 140 /* Bits 1..0 : ADC enable. */
emilmont 80:8e73be2a2ac1 141 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 142 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 143 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
emilmont 80:8e73be2a2ac1 144 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
emilmont 80:8e73be2a2ac1 145
emilmont 80:8e73be2a2ac1 146 /* Register: ADC_CONFIG */
emilmont 80:8e73be2a2ac1 147 /* Description: ADC configuration register. */
emilmont 80:8e73be2a2ac1 148
emilmont 80:8e73be2a2ac1 149 /* Bits 17..16 : ADC external reference pin selection. */
emilmont 80:8e73be2a2ac1 150 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
emilmont 80:8e73be2a2ac1 151 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
emilmont 80:8e73be2a2ac1 152 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
emilmont 80:8e73be2a2ac1 153 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
emilmont 80:8e73be2a2ac1 154 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
emilmont 80:8e73be2a2ac1 155
emilmont 80:8e73be2a2ac1 156 /* Bits 15..8 : ADC analog pin selection. */
emilmont 80:8e73be2a2ac1 157 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
emilmont 80:8e73be2a2ac1 158 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
emilmont 80:8e73be2a2ac1 159 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
emilmont 80:8e73be2a2ac1 160 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
emilmont 80:8e73be2a2ac1 161 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
emilmont 80:8e73be2a2ac1 162 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
emilmont 80:8e73be2a2ac1 163 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
emilmont 80:8e73be2a2ac1 164 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
emilmont 80:8e73be2a2ac1 165 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
emilmont 80:8e73be2a2ac1 166 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
emilmont 80:8e73be2a2ac1 167 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
emilmont 80:8e73be2a2ac1 168
emilmont 80:8e73be2a2ac1 169 /* Bits 6..5 : ADC reference selection. */
emilmont 80:8e73be2a2ac1 170 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
emilmont 80:8e73be2a2ac1 171 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
emilmont 80:8e73be2a2ac1 172 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
emilmont 80:8e73be2a2ac1 173 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
emilmont 80:8e73be2a2ac1 174 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
emilmont 80:8e73be2a2ac1 175 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
emilmont 80:8e73be2a2ac1 176
emilmont 80:8e73be2a2ac1 177 /* Bits 4..2 : ADC input selection. */
emilmont 80:8e73be2a2ac1 178 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
emilmont 80:8e73be2a2ac1 179 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
emilmont 80:8e73be2a2ac1 180 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
emilmont 80:8e73be2a2ac1 181 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
emilmont 80:8e73be2a2ac1 182 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
emilmont 80:8e73be2a2ac1 183 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
emilmont 80:8e73be2a2ac1 184 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
emilmont 80:8e73be2a2ac1 185
emilmont 80:8e73be2a2ac1 186 /* Bits 1..0 : ADC resolution. */
emilmont 80:8e73be2a2ac1 187 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
emilmont 80:8e73be2a2ac1 188 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
emilmont 80:8e73be2a2ac1 189 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
emilmont 80:8e73be2a2ac1 190 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
emilmont 80:8e73be2a2ac1 191 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
emilmont 80:8e73be2a2ac1 192
emilmont 80:8e73be2a2ac1 193 /* Register: ADC_RESULT */
emilmont 80:8e73be2a2ac1 194 /* Description: Result of ADC conversion. */
emilmont 80:8e73be2a2ac1 195
emilmont 80:8e73be2a2ac1 196 /* Bits 9..0 : Result of ADC conversion. */
emilmont 80:8e73be2a2ac1 197 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
emilmont 80:8e73be2a2ac1 198 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
emilmont 80:8e73be2a2ac1 199
emilmont 80:8e73be2a2ac1 200 /* Register: ADC_POWER */
emilmont 80:8e73be2a2ac1 201 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 202
emilmont 80:8e73be2a2ac1 203 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 204 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 205 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 206 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 207 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 208
emilmont 80:8e73be2a2ac1 209
emilmont 80:8e73be2a2ac1 210 /* Peripheral: AMLI */
emilmont 80:8e73be2a2ac1 211 /* Description: AHB Multi-Layer Interface. */
emilmont 80:8e73be2a2ac1 212
emilmont 80:8e73be2a2ac1 213 /* Register: AMLI_RAMPRI_CPU0 */
emilmont 80:8e73be2a2ac1 214 /* Description: Configurable priority configuration register for CPU0. */
emilmont 80:8e73be2a2ac1 215
emilmont 80:8e73be2a2ac1 216 /* Bits 15..12 : Configuration field for RAM block 3. */
emilmont 80:8e73be2a2ac1 217 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
emilmont 80:8e73be2a2ac1 218 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
emilmont 80:8e73be2a2ac1 219
emilmont 80:8e73be2a2ac1 220 /* Bits 11..8 : Configuration field for RAM block 2. */
emilmont 80:8e73be2a2ac1 221 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
emilmont 80:8e73be2a2ac1 222 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
emilmont 80:8e73be2a2ac1 223
emilmont 80:8e73be2a2ac1 224 /* Bits 7..4 : Configuration field for RAM block 1. */
emilmont 80:8e73be2a2ac1 225 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
emilmont 80:8e73be2a2ac1 226 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
emilmont 80:8e73be2a2ac1 227
emilmont 80:8e73be2a2ac1 228 /* Bits 3..0 : Configuration field for RAM block 0. */
emilmont 80:8e73be2a2ac1 229 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
emilmont 80:8e73be2a2ac1 230 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
emilmont 80:8e73be2a2ac1 231
emilmont 80:8e73be2a2ac1 232 /* Register: AMLI_RAMPRI_SPIS1 */
emilmont 80:8e73be2a2ac1 233 /* Description: Configurable priority configuration register for SPIS1. */
emilmont 80:8e73be2a2ac1 234
emilmont 80:8e73be2a2ac1 235 /* Bits 15..12 : Configuration field for RAM block 3. */
emilmont 80:8e73be2a2ac1 236 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
emilmont 80:8e73be2a2ac1 237 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
emilmont 80:8e73be2a2ac1 238
emilmont 80:8e73be2a2ac1 239 /* Bits 11..8 : Configuration field for RAM block 2. */
emilmont 80:8e73be2a2ac1 240 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
emilmont 80:8e73be2a2ac1 241 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
emilmont 80:8e73be2a2ac1 242
emilmont 80:8e73be2a2ac1 243 /* Bits 7..4 : Configuration field for RAM block 1. */
emilmont 80:8e73be2a2ac1 244 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
emilmont 80:8e73be2a2ac1 245 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
emilmont 80:8e73be2a2ac1 246
emilmont 80:8e73be2a2ac1 247 /* Bits 3..0 : Configuration field for RAM block 0. */
emilmont 80:8e73be2a2ac1 248 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
emilmont 80:8e73be2a2ac1 249 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
emilmont 80:8e73be2a2ac1 250
emilmont 80:8e73be2a2ac1 251 /* Register: AMLI_RAMPRI_RADIO */
emilmont 80:8e73be2a2ac1 252 /* Description: Configurable priority configuration register for RADIO. */
emilmont 80:8e73be2a2ac1 253
emilmont 80:8e73be2a2ac1 254 /* Bits 15..12 : Configuration field for RAM block 3. */
emilmont 80:8e73be2a2ac1 255 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
emilmont 80:8e73be2a2ac1 256 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
emilmont 80:8e73be2a2ac1 257
emilmont 80:8e73be2a2ac1 258 /* Bits 11..8 : Configuration field for RAM block 2. */
emilmont 80:8e73be2a2ac1 259 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
emilmont 80:8e73be2a2ac1 260 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
emilmont 80:8e73be2a2ac1 261
emilmont 80:8e73be2a2ac1 262 /* Bits 7..4 : Configuration field for RAM block 1. */
emilmont 80:8e73be2a2ac1 263 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
emilmont 80:8e73be2a2ac1 264 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
emilmont 80:8e73be2a2ac1 265
emilmont 80:8e73be2a2ac1 266 /* Bits 3..0 : Configuration field for RAM block 0. */
emilmont 80:8e73be2a2ac1 267 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
emilmont 80:8e73be2a2ac1 268 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
emilmont 80:8e73be2a2ac1 269
emilmont 80:8e73be2a2ac1 270 /* Register: AMLI_RAMPRI_ECB */
emilmont 80:8e73be2a2ac1 271 /* Description: Configurable priority configuration register for ECB. */
emilmont 80:8e73be2a2ac1 272
emilmont 80:8e73be2a2ac1 273 /* Bits 15..12 : Configuration field for RAM block 3. */
emilmont 80:8e73be2a2ac1 274 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
emilmont 80:8e73be2a2ac1 275 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
emilmont 80:8e73be2a2ac1 276
emilmont 80:8e73be2a2ac1 277 /* Bits 11..8 : Configuration field for RAM block 2. */
emilmont 80:8e73be2a2ac1 278 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
emilmont 80:8e73be2a2ac1 279 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
emilmont 80:8e73be2a2ac1 280
emilmont 80:8e73be2a2ac1 281 /* Bits 7..4 : Configuration field for RAM block 1. */
emilmont 80:8e73be2a2ac1 282 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
emilmont 80:8e73be2a2ac1 283 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
emilmont 80:8e73be2a2ac1 284
emilmont 80:8e73be2a2ac1 285 /* Bits 3..0 : Configuration field for RAM block 0. */
emilmont 80:8e73be2a2ac1 286 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
emilmont 80:8e73be2a2ac1 287 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
emilmont 80:8e73be2a2ac1 288
emilmont 80:8e73be2a2ac1 289 /* Register: AMLI_RAMPRI_CCM */
emilmont 80:8e73be2a2ac1 290 /* Description: Configurable priority configuration register for CCM. */
emilmont 80:8e73be2a2ac1 291
emilmont 80:8e73be2a2ac1 292 /* Bits 15..12 : Configuration field for RAM block 3. */
emilmont 80:8e73be2a2ac1 293 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
emilmont 80:8e73be2a2ac1 294 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
emilmont 80:8e73be2a2ac1 295
emilmont 80:8e73be2a2ac1 296 /* Bits 11..8 : Configuration field for RAM block 2. */
emilmont 80:8e73be2a2ac1 297 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
emilmont 80:8e73be2a2ac1 298 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
emilmont 80:8e73be2a2ac1 299
emilmont 80:8e73be2a2ac1 300 /* Bits 7..4 : Configuration field for RAM block 1. */
emilmont 80:8e73be2a2ac1 301 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
emilmont 80:8e73be2a2ac1 302 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
emilmont 80:8e73be2a2ac1 303
emilmont 80:8e73be2a2ac1 304 /* Bits 3..0 : Configuration field for RAM block 0. */
emilmont 80:8e73be2a2ac1 305 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
emilmont 80:8e73be2a2ac1 306 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
emilmont 80:8e73be2a2ac1 307
emilmont 80:8e73be2a2ac1 308 /* Register: AMLI_RAMPRI_AAR */
emilmont 80:8e73be2a2ac1 309 /* Description: Configurable priority configuration register for AAR. */
emilmont 80:8e73be2a2ac1 310
emilmont 80:8e73be2a2ac1 311 /* Bits 15..12 : Configuration field for RAM block 3. */
emilmont 80:8e73be2a2ac1 312 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
emilmont 80:8e73be2a2ac1 313 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
emilmont 80:8e73be2a2ac1 314
emilmont 80:8e73be2a2ac1 315 /* Bits 11..8 : Configuration field for RAM block 2. */
emilmont 80:8e73be2a2ac1 316 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
emilmont 80:8e73be2a2ac1 317 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
emilmont 80:8e73be2a2ac1 318
emilmont 80:8e73be2a2ac1 319 /* Bits 7..4 : Configuration field for RAM block 1. */
emilmont 80:8e73be2a2ac1 320 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
emilmont 80:8e73be2a2ac1 321 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
emilmont 80:8e73be2a2ac1 322
emilmont 80:8e73be2a2ac1 323 /* Bits 3..0 : Configuration field for RAM block 0. */
emilmont 80:8e73be2a2ac1 324 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
emilmont 80:8e73be2a2ac1 325 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
emilmont 80:8e73be2a2ac1 326
emilmont 80:8e73be2a2ac1 327 /* Peripheral: CCM */
emilmont 80:8e73be2a2ac1 328 /* Description: AES CCM Mode Encryption. */
emilmont 80:8e73be2a2ac1 329
emilmont 80:8e73be2a2ac1 330 /* Register: CCM_SHORTS */
emilmont 80:8e73be2a2ac1 331 /* Description: Shortcut for the CCM. */
emilmont 80:8e73be2a2ac1 332
emilmont 80:8e73be2a2ac1 333 /* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */
emilmont 80:8e73be2a2ac1 334 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
emilmont 80:8e73be2a2ac1 335 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
emilmont 80:8e73be2a2ac1 336 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 337 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 338
emilmont 80:8e73be2a2ac1 339 /* Register: CCM_INTENSET */
emilmont 80:8e73be2a2ac1 340 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 341
emilmont 80:8e73be2a2ac1 342 /* Bit 2 : Enable interrupt on ERROR event. */
emilmont 80:8e73be2a2ac1 343 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
emilmont 80:8e73be2a2ac1 344 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
emilmont 80:8e73be2a2ac1 345 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 346 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 347 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 348
emilmont 80:8e73be2a2ac1 349 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
emilmont 80:8e73be2a2ac1 350 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
emilmont 80:8e73be2a2ac1 351 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
emilmont 80:8e73be2a2ac1 352 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 353 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 354 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 355
emilmont 80:8e73be2a2ac1 356 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
emilmont 80:8e73be2a2ac1 357 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
emilmont 80:8e73be2a2ac1 358 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
emilmont 80:8e73be2a2ac1 359 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 360 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 361 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 362
emilmont 80:8e73be2a2ac1 363 /* Register: CCM_INTENCLR */
emilmont 80:8e73be2a2ac1 364 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 365
emilmont 80:8e73be2a2ac1 366 /* Bit 2 : Disable interrupt on ERROR event. */
emilmont 80:8e73be2a2ac1 367 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
emilmont 80:8e73be2a2ac1 368 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
emilmont 80:8e73be2a2ac1 369 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 370 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 371 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 372
emilmont 80:8e73be2a2ac1 373 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
emilmont 80:8e73be2a2ac1 374 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
emilmont 80:8e73be2a2ac1 375 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
emilmont 80:8e73be2a2ac1 376 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 377 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 378 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 379
emilmont 80:8e73be2a2ac1 380 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
emilmont 80:8e73be2a2ac1 381 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
emilmont 80:8e73be2a2ac1 382 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
emilmont 80:8e73be2a2ac1 383 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 384 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 385 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 386
emilmont 80:8e73be2a2ac1 387 /* Register: CCM_MICSTATUS */
emilmont 80:8e73be2a2ac1 388 /* Description: CCM RX MIC check result. */
emilmont 80:8e73be2a2ac1 389
emilmont 80:8e73be2a2ac1 390 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
emilmont 80:8e73be2a2ac1 391 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
emilmont 80:8e73be2a2ac1 392 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
emilmont 80:8e73be2a2ac1 393 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
emilmont 80:8e73be2a2ac1 394 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
emilmont 80:8e73be2a2ac1 395
emilmont 80:8e73be2a2ac1 396 /* Register: CCM_ENABLE */
emilmont 80:8e73be2a2ac1 397 /* Description: CCM enable. */
emilmont 80:8e73be2a2ac1 398
emilmont 80:8e73be2a2ac1 399 /* Bits 1..0 : CCM enable. */
emilmont 80:8e73be2a2ac1 400 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 401 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 402 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
emilmont 80:8e73be2a2ac1 403 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
emilmont 80:8e73be2a2ac1 404
emilmont 80:8e73be2a2ac1 405 /* Register: CCM_MODE */
emilmont 80:8e73be2a2ac1 406 /* Description: Operation mode. */
emilmont 80:8e73be2a2ac1 407
emilmont 80:8e73be2a2ac1 408 /* Bit 0 : CCM mode operation. */
emilmont 80:8e73be2a2ac1 409 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
emilmont 80:8e73be2a2ac1 410 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
emilmont 80:8e73be2a2ac1 411 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
emilmont 80:8e73be2a2ac1 412 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
emilmont 80:8e73be2a2ac1 413
emilmont 80:8e73be2a2ac1 414 /* Register: CCM_POWER */
emilmont 80:8e73be2a2ac1 415 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 416
emilmont 80:8e73be2a2ac1 417 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 418 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 419 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 420 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 421 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 422
emilmont 80:8e73be2a2ac1 423
emilmont 80:8e73be2a2ac1 424 /* Peripheral: CLOCK */
emilmont 80:8e73be2a2ac1 425 /* Description: Clock control. */
emilmont 80:8e73be2a2ac1 426
emilmont 80:8e73be2a2ac1 427 /* Register: CLOCK_INTENSET */
emilmont 80:8e73be2a2ac1 428 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 429
emilmont 80:8e73be2a2ac1 430 /* Bit 4 : Enable interrupt on CTTO event. */
emilmont 80:8e73be2a2ac1 431 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
emilmont 80:8e73be2a2ac1 432 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
emilmont 80:8e73be2a2ac1 433 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 434 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 435 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 436
emilmont 80:8e73be2a2ac1 437 /* Bit 3 : Enable interrupt on DONE event. */
emilmont 80:8e73be2a2ac1 438 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
emilmont 80:8e73be2a2ac1 439 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
emilmont 80:8e73be2a2ac1 440 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 441 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 442 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 443
emilmont 80:8e73be2a2ac1 444 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
emilmont 80:8e73be2a2ac1 445 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
emilmont 80:8e73be2a2ac1 446 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
emilmont 80:8e73be2a2ac1 447 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 448 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 449 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 450
emilmont 80:8e73be2a2ac1 451 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
emilmont 80:8e73be2a2ac1 452 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
emilmont 80:8e73be2a2ac1 453 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
emilmont 80:8e73be2a2ac1 454 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 455 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 456 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 457
emilmont 80:8e73be2a2ac1 458 /* Register: CLOCK_INTENCLR */
emilmont 80:8e73be2a2ac1 459 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 460
emilmont 80:8e73be2a2ac1 461 /* Bit 4 : Disable interrupt on CTTO event. */
emilmont 80:8e73be2a2ac1 462 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
emilmont 80:8e73be2a2ac1 463 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
emilmont 80:8e73be2a2ac1 464 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 465 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 466 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 467
emilmont 80:8e73be2a2ac1 468 /* Bit 3 : Disable interrupt on DONE event. */
emilmont 80:8e73be2a2ac1 469 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
emilmont 80:8e73be2a2ac1 470 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
emilmont 80:8e73be2a2ac1 471 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 472 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 473 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 474
emilmont 80:8e73be2a2ac1 475 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
emilmont 80:8e73be2a2ac1 476 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
emilmont 80:8e73be2a2ac1 477 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
emilmont 80:8e73be2a2ac1 478 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 479 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 480 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 481
emilmont 80:8e73be2a2ac1 482 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
emilmont 80:8e73be2a2ac1 483 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
emilmont 80:8e73be2a2ac1 484 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
emilmont 80:8e73be2a2ac1 485 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 486 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 487 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 488
emilmont 80:8e73be2a2ac1 489 /* Register: CLOCK_HFCLKSTAT */
emilmont 80:8e73be2a2ac1 490 /* Description: High frequency clock status. */
emilmont 80:8e73be2a2ac1 491
emilmont 80:8e73be2a2ac1 492 /* Bit 16 : State for the HFCLK. */
emilmont 80:8e73be2a2ac1 493 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
emilmont 80:8e73be2a2ac1 494 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
emilmont 80:8e73be2a2ac1 495 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
emilmont 80:8e73be2a2ac1 496 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
emilmont 80:8e73be2a2ac1 497
emilmont 80:8e73be2a2ac1 498 /* Bit 0 : Active clock source for the HF clock. */
emilmont 80:8e73be2a2ac1 499 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
emilmont 80:8e73be2a2ac1 500 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
emilmont 80:8e73be2a2ac1 501 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
emilmont 80:8e73be2a2ac1 502 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
emilmont 80:8e73be2a2ac1 503
emilmont 80:8e73be2a2ac1 504 /* Register: CLOCK_LFCLKSTAT */
emilmont 80:8e73be2a2ac1 505 /* Description: Low frequency clock status. */
emilmont 80:8e73be2a2ac1 506
emilmont 80:8e73be2a2ac1 507 /* Bit 16 : State for the LF clock. */
emilmont 80:8e73be2a2ac1 508 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
emilmont 80:8e73be2a2ac1 509 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
emilmont 80:8e73be2a2ac1 510 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
emilmont 80:8e73be2a2ac1 511 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
emilmont 80:8e73be2a2ac1 512
emilmont 80:8e73be2a2ac1 513 /* Bits 1..0 : Active clock source for the LF clock. */
emilmont 80:8e73be2a2ac1 514 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
emilmont 80:8e73be2a2ac1 515 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
emilmont 80:8e73be2a2ac1 516 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
emilmont 80:8e73be2a2ac1 517 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
emilmont 80:8e73be2a2ac1 518 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
emilmont 80:8e73be2a2ac1 519
emilmont 80:8e73be2a2ac1 520 /* Register: CLOCK_LFCLKSRC */
emilmont 80:8e73be2a2ac1 521 /* Description: Clock source for the LFCLK clock. */
emilmont 80:8e73be2a2ac1 522
emilmont 80:8e73be2a2ac1 523 /* Bits 1..0 : Clock source. */
emilmont 80:8e73be2a2ac1 524 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
emilmont 80:8e73be2a2ac1 525 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
emilmont 80:8e73be2a2ac1 526 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
emilmont 80:8e73be2a2ac1 527 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
emilmont 80:8e73be2a2ac1 528 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
emilmont 80:8e73be2a2ac1 529
emilmont 80:8e73be2a2ac1 530 /* Register: CLOCK_CTIV */
emilmont 80:8e73be2a2ac1 531 /* Description: Calibration timer interval. */
emilmont 80:8e73be2a2ac1 532
emilmont 80:8e73be2a2ac1 533 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
emilmont 80:8e73be2a2ac1 534 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
emilmont 80:8e73be2a2ac1 535 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
emilmont 80:8e73be2a2ac1 536
emilmont 80:8e73be2a2ac1 537 /* Register: CLOCK_XTALFREQ */
emilmont 80:8e73be2a2ac1 538 /* Description: Crystal frequency. */
emilmont 80:8e73be2a2ac1 539
emilmont 80:8e73be2a2ac1 540 /* Bits 7..0 : External Xtal frequency selection. */
emilmont 80:8e73be2a2ac1 541 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
emilmont 80:8e73be2a2ac1 542 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
emilmont 80:8e73be2a2ac1 543 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used. */
emilmont 80:8e73be2a2ac1 544 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used. */
emilmont 80:8e73be2a2ac1 545
emilmont 80:8e73be2a2ac1 546
emilmont 80:8e73be2a2ac1 547 /* Peripheral: COMP */
emilmont 80:8e73be2a2ac1 548 /* Description: Comparator. */
emilmont 80:8e73be2a2ac1 549
emilmont 80:8e73be2a2ac1 550 /* Register: COMP_SHORTS */
emilmont 80:8e73be2a2ac1 551 /* Description: Shortcut for the COMP. */
emilmont 80:8e73be2a2ac1 552
emilmont 80:8e73be2a2ac1 553 /* Bit 4 : Short-cut between CROSS event and STOP task. */
emilmont 80:8e73be2a2ac1 554 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
emilmont 80:8e73be2a2ac1 555 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
emilmont 80:8e73be2a2ac1 556 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 557 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 558
emilmont 80:8e73be2a2ac1 559 /* Bit 3 : Short-cut between UP event and STOP task. */
emilmont 80:8e73be2a2ac1 560 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
emilmont 80:8e73be2a2ac1 561 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
emilmont 80:8e73be2a2ac1 562 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 563 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 564
emilmont 80:8e73be2a2ac1 565 /* Bit 2 : Short-cut between DOWN event and STOP task. */
emilmont 80:8e73be2a2ac1 566 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
emilmont 80:8e73be2a2ac1 567 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
emilmont 80:8e73be2a2ac1 568 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 569 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 570
emilmont 80:8e73be2a2ac1 571 /* Bit 1 : Short-cut between RADY event and STOP task. */
emilmont 80:8e73be2a2ac1 572 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
emilmont 80:8e73be2a2ac1 573 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
emilmont 80:8e73be2a2ac1 574 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 575 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 576
emilmont 80:8e73be2a2ac1 577 /* Bit 0 : Short-cut between READY event and SAMPLE task. */
emilmont 80:8e73be2a2ac1 578 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
emilmont 80:8e73be2a2ac1 579 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
emilmont 80:8e73be2a2ac1 580 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 581 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 582
emilmont 80:8e73be2a2ac1 583 /* Register: COMP_INTENSET */
emilmont 80:8e73be2a2ac1 584 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 585
emilmont 80:8e73be2a2ac1 586 /* Bit 3 : Enable interrupt on CROSS event. */
emilmont 80:8e73be2a2ac1 587 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
emilmont 80:8e73be2a2ac1 588 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
emilmont 80:8e73be2a2ac1 589 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 590 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 591 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 592
emilmont 80:8e73be2a2ac1 593 /* Bit 2 : Enable interrupt on UP event. */
emilmont 80:8e73be2a2ac1 594 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
emilmont 80:8e73be2a2ac1 595 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
emilmont 80:8e73be2a2ac1 596 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 597 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 598 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 599
emilmont 80:8e73be2a2ac1 600 /* Bit 1 : Enable interrupt on DOWN event. */
emilmont 80:8e73be2a2ac1 601 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
emilmont 80:8e73be2a2ac1 602 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
emilmont 80:8e73be2a2ac1 603 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 604 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 605 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 606
emilmont 80:8e73be2a2ac1 607 /* Bit 0 : Enable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 608 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 609 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 610 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 611 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 612 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 613
emilmont 80:8e73be2a2ac1 614 /* Register: COMP_INTENCLR */
emilmont 80:8e73be2a2ac1 615 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 616
emilmont 80:8e73be2a2ac1 617 /* Bit 3 : Disable interrupt on CROSS event. */
emilmont 80:8e73be2a2ac1 618 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
emilmont 80:8e73be2a2ac1 619 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
emilmont 80:8e73be2a2ac1 620 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 621 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 622 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 623
emilmont 80:8e73be2a2ac1 624 /* Bit 2 : Disable interrupt on UP event. */
emilmont 80:8e73be2a2ac1 625 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
emilmont 80:8e73be2a2ac1 626 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
emilmont 80:8e73be2a2ac1 627 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 628 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 629 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 630
emilmont 80:8e73be2a2ac1 631 /* Bit 1 : Disable interrupt on DOWN event. */
emilmont 80:8e73be2a2ac1 632 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
emilmont 80:8e73be2a2ac1 633 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
emilmont 80:8e73be2a2ac1 634 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 635 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 636 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 637
emilmont 80:8e73be2a2ac1 638 /* Bit 0 : Disable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 639 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 640 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 641 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 642 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 643 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 644
emilmont 80:8e73be2a2ac1 645 /* Register: COMP_RESULT */
emilmont 80:8e73be2a2ac1 646 /* Description: Compare result. */
emilmont 80:8e73be2a2ac1 647
emilmont 80:8e73be2a2ac1 648 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
emilmont 80:8e73be2a2ac1 649 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
emilmont 80:8e73be2a2ac1 650 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
emilmont 80:8e73be2a2ac1 651 #define COMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
emilmont 80:8e73be2a2ac1 652 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
emilmont 80:8e73be2a2ac1 653
emilmont 80:8e73be2a2ac1 654 /* Register: COMP_ENABLE */
emilmont 80:8e73be2a2ac1 655 /* Description: Enable the COMP. */
emilmont 80:8e73be2a2ac1 656
emilmont 80:8e73be2a2ac1 657 /* Bits 1..0 : Enable or disable COMP. */
emilmont 80:8e73be2a2ac1 658 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 659 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 660 #define COMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled COMP. */
emilmont 80:8e73be2a2ac1 661 #define COMP_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable COMP. */
emilmont 80:8e73be2a2ac1 662
emilmont 80:8e73be2a2ac1 663 /* Register: COMP_PSEL */
emilmont 80:8e73be2a2ac1 664 /* Description: Input pin select. */
emilmont 80:8e73be2a2ac1 665
emilmont 80:8e73be2a2ac1 666 /* Bits 2..0 : Analog input pin select. */
emilmont 80:8e73be2a2ac1 667 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
emilmont 80:8e73be2a2ac1 668 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
emilmont 80:8e73be2a2ac1 669 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
emilmont 80:8e73be2a2ac1 670 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
emilmont 80:8e73be2a2ac1 671 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
emilmont 80:8e73be2a2ac1 672 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
emilmont 80:8e73be2a2ac1 673 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
emilmont 80:8e73be2a2ac1 674 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
emilmont 80:8e73be2a2ac1 675 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
emilmont 80:8e73be2a2ac1 676 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
emilmont 80:8e73be2a2ac1 677
emilmont 80:8e73be2a2ac1 678 /* Register: COMP_REFSEL */
emilmont 80:8e73be2a2ac1 679 /* Description: Reference select. */
emilmont 80:8e73be2a2ac1 680
emilmont 80:8e73be2a2ac1 681 /* Bits 2..0 : Reference select. */
emilmont 80:8e73be2a2ac1 682 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
emilmont 80:8e73be2a2ac1 683 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
emilmont 80:8e73be2a2ac1 684 #define COMP_REFSEL_REFSEL_Int1V5 (0UL) /*!< Use internal 1V5 as reference. */
emilmont 80:8e73be2a2ac1 685 #define COMP_REFSEL_REFSEL_Int2V0 (1UL) /*!< Use internal 2V0 as reference. */
emilmont 80:8e73be2a2ac1 686 #define COMP_REFSEL_REFSEL_Int2V5 (2UL) /*!< Use internal 2V5 as reference. */
emilmont 80:8e73be2a2ac1 687 #define COMP_REFSEL_REFSEL_Supply (4UL) /*!< Use supply as reference. */
emilmont 80:8e73be2a2ac1 688 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< Use external analog reference as reference. */
emilmont 80:8e73be2a2ac1 689
emilmont 80:8e73be2a2ac1 690 /* Register: COMP_EXTREFSEL */
emilmont 80:8e73be2a2ac1 691 /* Description: External reference select. */
emilmont 80:8e73be2a2ac1 692
emilmont 80:8e73be2a2ac1 693 /* Bit 0 : External analog reference pin selection. */
emilmont 80:8e73be2a2ac1 694 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
emilmont 80:8e73be2a2ac1 695 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
emilmont 80:8e73be2a2ac1 696 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
emilmont 80:8e73be2a2ac1 697 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
emilmont 80:8e73be2a2ac1 698
emilmont 80:8e73be2a2ac1 699 /* Register: COMP_TH */
emilmont 80:8e73be2a2ac1 700 /* Description: Threshold configuration for hysteresis unit. */
emilmont 80:8e73be2a2ac1 701
emilmont 80:8e73be2a2ac1 702 /* Bits 13..8 : VDOWN configuration. */
emilmont 80:8e73be2a2ac1 703 #define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */
emilmont 80:8e73be2a2ac1 704 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
emilmont 80:8e73be2a2ac1 705
emilmont 80:8e73be2a2ac1 706 /* Bits 5..0 : VUP configuration. */
emilmont 80:8e73be2a2ac1 707 #define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */
emilmont 80:8e73be2a2ac1 708 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
emilmont 80:8e73be2a2ac1 709
emilmont 80:8e73be2a2ac1 710 /* Register: COMP_MODE */
emilmont 80:8e73be2a2ac1 711 /* Description: Mode configuration. */
emilmont 80:8e73be2a2ac1 712
emilmont 80:8e73be2a2ac1 713 /* Bit 8 : Main operation mode. */
emilmont 80:8e73be2a2ac1 714 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
emilmont 80:8e73be2a2ac1 715 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
emilmont 80:8e73be2a2ac1 716 #define COMP_MODE_MAIN_Single (0UL) /*!< Single ended mode. */
emilmont 80:8e73be2a2ac1 717 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode. */
emilmont 80:8e73be2a2ac1 718
emilmont 80:8e73be2a2ac1 719 /* Bits 1..0 : Speed and power mode. */
emilmont 80:8e73be2a2ac1 720 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
emilmont 80:8e73be2a2ac1 721 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
emilmont 80:8e73be2a2ac1 722 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode. */
emilmont 80:8e73be2a2ac1 723 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode. */
emilmont 80:8e73be2a2ac1 724 #define COMP_MODE_SP_High (2UL) /*!< High speed mode. */
emilmont 80:8e73be2a2ac1 725
emilmont 80:8e73be2a2ac1 726 /* Register: COMP_POWER */
emilmont 80:8e73be2a2ac1 727 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 728
emilmont 80:8e73be2a2ac1 729 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 730 #define COMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 731 #define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 732 #define COMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 733 #define COMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 734
emilmont 80:8e73be2a2ac1 735
emilmont 80:8e73be2a2ac1 736 /* Peripheral: ECB */
emilmont 80:8e73be2a2ac1 737 /* Description: AES ECB Mode Encryption. */
emilmont 80:8e73be2a2ac1 738
emilmont 80:8e73be2a2ac1 739 /* Register: ECB_INTENSET */
emilmont 80:8e73be2a2ac1 740 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 741
emilmont 80:8e73be2a2ac1 742 /* Bit 1 : Enable interrupt on ERRORECB event. */
emilmont 80:8e73be2a2ac1 743 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
emilmont 80:8e73be2a2ac1 744 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
emilmont 80:8e73be2a2ac1 745 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 746 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 747 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 748
emilmont 80:8e73be2a2ac1 749 /* Bit 0 : Enable interrupt on ENDECB event. */
emilmont 80:8e73be2a2ac1 750 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
emilmont 80:8e73be2a2ac1 751 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
emilmont 80:8e73be2a2ac1 752 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 753 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 754 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 755
emilmont 80:8e73be2a2ac1 756 /* Register: ECB_INTENCLR */
emilmont 80:8e73be2a2ac1 757 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 758
emilmont 80:8e73be2a2ac1 759 /* Bit 1 : Disable interrupt on ERRORECB event. */
emilmont 80:8e73be2a2ac1 760 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
emilmont 80:8e73be2a2ac1 761 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
emilmont 80:8e73be2a2ac1 762 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 763 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 764 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 765
emilmont 80:8e73be2a2ac1 766 /* Bit 0 : Disable interrupt on ENDECB event. */
emilmont 80:8e73be2a2ac1 767 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
emilmont 80:8e73be2a2ac1 768 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
emilmont 80:8e73be2a2ac1 769 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 770 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 771 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 772
emilmont 80:8e73be2a2ac1 773 /* Register: ECB_POWER */
emilmont 80:8e73be2a2ac1 774 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 775
emilmont 80:8e73be2a2ac1 776 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 777 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 778 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 779 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 780 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 781
emilmont 80:8e73be2a2ac1 782
emilmont 80:8e73be2a2ac1 783 /* Peripheral: FICR */
emilmont 80:8e73be2a2ac1 784 /* Description: Factory Information Configuration. */
emilmont 80:8e73be2a2ac1 785
emilmont 80:8e73be2a2ac1 786 /* Register: FICR_PPFC */
emilmont 80:8e73be2a2ac1 787 /* Description: Pre-programmed factory code present. */
emilmont 80:8e73be2a2ac1 788
emilmont 80:8e73be2a2ac1 789 /* Bits 7..0 : Pre-programmed factory code present. */
emilmont 80:8e73be2a2ac1 790 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
emilmont 80:8e73be2a2ac1 791 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
emilmont 80:8e73be2a2ac1 792 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
emilmont 80:8e73be2a2ac1 793 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
emilmont 80:8e73be2a2ac1 794
emilmont 80:8e73be2a2ac1 795 /* Register: FICR_CONFIGID */
emilmont 80:8e73be2a2ac1 796 /* Description: Configuration identifier. */
emilmont 80:8e73be2a2ac1 797
emilmont 80:8e73be2a2ac1 798 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
emilmont 80:8e73be2a2ac1 799 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
emilmont 80:8e73be2a2ac1 800 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
emilmont 80:8e73be2a2ac1 801
emilmont 80:8e73be2a2ac1 802 /* Bits 15..0 : Hardware Identification Number. */
emilmont 80:8e73be2a2ac1 803 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
emilmont 80:8e73be2a2ac1 804 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
emilmont 80:8e73be2a2ac1 805
emilmont 80:8e73be2a2ac1 806 /* Register: FICR_DEVICEADDRTYPE */
emilmont 80:8e73be2a2ac1 807 /* Description: Device address type. */
emilmont 80:8e73be2a2ac1 808
emilmont 80:8e73be2a2ac1 809 /* Bit 0 : Device address type. */
emilmont 80:8e73be2a2ac1 810 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
emilmont 80:8e73be2a2ac1 811 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
emilmont 80:8e73be2a2ac1 812 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
emilmont 80:8e73be2a2ac1 813 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
emilmont 80:8e73be2a2ac1 814
emilmont 80:8e73be2a2ac1 815 /* Register: FICR_OVERRIDEEN */
emilmont 80:8e73be2a2ac1 816 /* Description: Radio calibration override enable. */
emilmont 80:8e73be2a2ac1 817
emilmont 80:8e73be2a2ac1 818 /* Bit 3 : Override default values for BLE_1Mbit mode. */
emilmont 80:8e73be2a2ac1 819 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
emilmont 80:8e73be2a2ac1 820 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
emilmont 80:8e73be2a2ac1 821 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
emilmont 80:8e73be2a2ac1 822 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
emilmont 80:8e73be2a2ac1 823
emilmont 80:8e73be2a2ac1 824
emilmont 80:8e73be2a2ac1 825 /* Peripheral: GPIO */
emilmont 80:8e73be2a2ac1 826 /* Description: General purpose input and output. */
emilmont 80:8e73be2a2ac1 827
emilmont 80:8e73be2a2ac1 828 /* Register: GPIO_OUT */
emilmont 80:8e73be2a2ac1 829 /* Description: Write GPIO port. */
emilmont 80:8e73be2a2ac1 830
emilmont 80:8e73be2a2ac1 831 /* Bit 31 : Pin 31. */
emilmont 80:8e73be2a2ac1 832 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
emilmont 80:8e73be2a2ac1 833 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
emilmont 80:8e73be2a2ac1 834 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 835 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 836
emilmont 80:8e73be2a2ac1 837 /* Bit 30 : Pin 30. */
emilmont 80:8e73be2a2ac1 838 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
emilmont 80:8e73be2a2ac1 839 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
emilmont 80:8e73be2a2ac1 840 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 841 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 842
emilmont 80:8e73be2a2ac1 843 /* Bit 29 : Pin 29. */
emilmont 80:8e73be2a2ac1 844 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
emilmont 80:8e73be2a2ac1 845 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
emilmont 80:8e73be2a2ac1 846 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 847 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 848
emilmont 80:8e73be2a2ac1 849 /* Bit 28 : Pin 28. */
emilmont 80:8e73be2a2ac1 850 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
emilmont 80:8e73be2a2ac1 851 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
emilmont 80:8e73be2a2ac1 852 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 853 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 854
emilmont 80:8e73be2a2ac1 855 /* Bit 27 : Pin 27. */
emilmont 80:8e73be2a2ac1 856 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
emilmont 80:8e73be2a2ac1 857 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
emilmont 80:8e73be2a2ac1 858 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 859 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 860
emilmont 80:8e73be2a2ac1 861 /* Bit 26 : Pin 26. */
emilmont 80:8e73be2a2ac1 862 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
emilmont 80:8e73be2a2ac1 863 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
emilmont 80:8e73be2a2ac1 864 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 865 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 866
emilmont 80:8e73be2a2ac1 867 /* Bit 25 : Pin 25. */
emilmont 80:8e73be2a2ac1 868 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
emilmont 80:8e73be2a2ac1 869 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
emilmont 80:8e73be2a2ac1 870 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 871 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 872
emilmont 80:8e73be2a2ac1 873 /* Bit 24 : Pin 24. */
emilmont 80:8e73be2a2ac1 874 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
emilmont 80:8e73be2a2ac1 875 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
emilmont 80:8e73be2a2ac1 876 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 877 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 878
emilmont 80:8e73be2a2ac1 879 /* Bit 23 : Pin 23. */
emilmont 80:8e73be2a2ac1 880 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
emilmont 80:8e73be2a2ac1 881 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
emilmont 80:8e73be2a2ac1 882 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 883 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 884
emilmont 80:8e73be2a2ac1 885 /* Bit 22 : Pin 22. */
emilmont 80:8e73be2a2ac1 886 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
emilmont 80:8e73be2a2ac1 887 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
emilmont 80:8e73be2a2ac1 888 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 889 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 890
emilmont 80:8e73be2a2ac1 891 /* Bit 21 : Pin 21. */
emilmont 80:8e73be2a2ac1 892 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
emilmont 80:8e73be2a2ac1 893 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
emilmont 80:8e73be2a2ac1 894 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 895 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 896
emilmont 80:8e73be2a2ac1 897 /* Bit 20 : Pin 20. */
emilmont 80:8e73be2a2ac1 898 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
emilmont 80:8e73be2a2ac1 899 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
emilmont 80:8e73be2a2ac1 900 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 901 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 902
emilmont 80:8e73be2a2ac1 903 /* Bit 19 : Pin 19. */
emilmont 80:8e73be2a2ac1 904 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
emilmont 80:8e73be2a2ac1 905 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
emilmont 80:8e73be2a2ac1 906 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 907 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 908
emilmont 80:8e73be2a2ac1 909 /* Bit 18 : Pin 18. */
emilmont 80:8e73be2a2ac1 910 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
emilmont 80:8e73be2a2ac1 911 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
emilmont 80:8e73be2a2ac1 912 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 913 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 914
emilmont 80:8e73be2a2ac1 915 /* Bit 17 : Pin 17. */
emilmont 80:8e73be2a2ac1 916 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
emilmont 80:8e73be2a2ac1 917 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
emilmont 80:8e73be2a2ac1 918 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 919 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 920
emilmont 80:8e73be2a2ac1 921 /* Bit 16 : Pin 16. */
emilmont 80:8e73be2a2ac1 922 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
emilmont 80:8e73be2a2ac1 923 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
emilmont 80:8e73be2a2ac1 924 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 925 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 926
emilmont 80:8e73be2a2ac1 927 /* Bit 15 : Pin 15. */
emilmont 80:8e73be2a2ac1 928 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
emilmont 80:8e73be2a2ac1 929 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
emilmont 80:8e73be2a2ac1 930 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 931 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 932
emilmont 80:8e73be2a2ac1 933 /* Bit 14 : Pin 14. */
emilmont 80:8e73be2a2ac1 934 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
emilmont 80:8e73be2a2ac1 935 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
emilmont 80:8e73be2a2ac1 936 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 937 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 938
emilmont 80:8e73be2a2ac1 939 /* Bit 13 : Pin 13. */
emilmont 80:8e73be2a2ac1 940 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
emilmont 80:8e73be2a2ac1 941 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
emilmont 80:8e73be2a2ac1 942 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 943 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 944
emilmont 80:8e73be2a2ac1 945 /* Bit 12 : Pin 12. */
emilmont 80:8e73be2a2ac1 946 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
emilmont 80:8e73be2a2ac1 947 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
emilmont 80:8e73be2a2ac1 948 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 949 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 950
emilmont 80:8e73be2a2ac1 951 /* Bit 11 : Pin 11. */
emilmont 80:8e73be2a2ac1 952 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
emilmont 80:8e73be2a2ac1 953 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
emilmont 80:8e73be2a2ac1 954 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 955 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 956
emilmont 80:8e73be2a2ac1 957 /* Bit 10 : Pin 10. */
emilmont 80:8e73be2a2ac1 958 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
emilmont 80:8e73be2a2ac1 959 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
emilmont 80:8e73be2a2ac1 960 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 961 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 962
emilmont 80:8e73be2a2ac1 963 /* Bit 9 : Pin 9. */
emilmont 80:8e73be2a2ac1 964 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
emilmont 80:8e73be2a2ac1 965 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
emilmont 80:8e73be2a2ac1 966 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 967 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 968
emilmont 80:8e73be2a2ac1 969 /* Bit 8 : Pin 8. */
emilmont 80:8e73be2a2ac1 970 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
emilmont 80:8e73be2a2ac1 971 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
emilmont 80:8e73be2a2ac1 972 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 973 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 974
emilmont 80:8e73be2a2ac1 975 /* Bit 7 : Pin 7. */
emilmont 80:8e73be2a2ac1 976 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
emilmont 80:8e73be2a2ac1 977 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
emilmont 80:8e73be2a2ac1 978 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 979 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 980
emilmont 80:8e73be2a2ac1 981 /* Bit 6 : Pin 6. */
emilmont 80:8e73be2a2ac1 982 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
emilmont 80:8e73be2a2ac1 983 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
emilmont 80:8e73be2a2ac1 984 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 985 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 986
emilmont 80:8e73be2a2ac1 987 /* Bit 5 : Pin 5. */
emilmont 80:8e73be2a2ac1 988 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
emilmont 80:8e73be2a2ac1 989 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
emilmont 80:8e73be2a2ac1 990 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 991 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 992
emilmont 80:8e73be2a2ac1 993 /* Bit 4 : Pin 4. */
emilmont 80:8e73be2a2ac1 994 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
emilmont 80:8e73be2a2ac1 995 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
emilmont 80:8e73be2a2ac1 996 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 997 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 998
emilmont 80:8e73be2a2ac1 999 /* Bit 3 : Pin 3. */
emilmont 80:8e73be2a2ac1 1000 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
emilmont 80:8e73be2a2ac1 1001 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
emilmont 80:8e73be2a2ac1 1002 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1003 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1004
emilmont 80:8e73be2a2ac1 1005 /* Bit 2 : Pin 2. */
emilmont 80:8e73be2a2ac1 1006 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
emilmont 80:8e73be2a2ac1 1007 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
emilmont 80:8e73be2a2ac1 1008 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1009 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1010
emilmont 80:8e73be2a2ac1 1011 /* Bit 1 : Pin 1. */
emilmont 80:8e73be2a2ac1 1012 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
emilmont 80:8e73be2a2ac1 1013 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
emilmont 80:8e73be2a2ac1 1014 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1015 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1016
emilmont 80:8e73be2a2ac1 1017 /* Bit 0 : Pin 0. */
emilmont 80:8e73be2a2ac1 1018 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
emilmont 80:8e73be2a2ac1 1019 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
emilmont 80:8e73be2a2ac1 1020 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1021 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1022
emilmont 80:8e73be2a2ac1 1023 /* Register: GPIO_OUTSET */
emilmont 80:8e73be2a2ac1 1024 /* Description: Set individual bits in GPIO port. */
emilmont 80:8e73be2a2ac1 1025
emilmont 80:8e73be2a2ac1 1026 /* Bit 31 : Pin 31. */
emilmont 80:8e73be2a2ac1 1027 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
emilmont 80:8e73be2a2ac1 1028 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
emilmont 80:8e73be2a2ac1 1029 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1030 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1031 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1032
emilmont 80:8e73be2a2ac1 1033 /* Bit 30 : Pin 30. */
emilmont 80:8e73be2a2ac1 1034 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
emilmont 80:8e73be2a2ac1 1035 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
emilmont 80:8e73be2a2ac1 1036 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1037 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1038 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1039
emilmont 80:8e73be2a2ac1 1040 /* Bit 29 : Pin 29. */
emilmont 80:8e73be2a2ac1 1041 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
emilmont 80:8e73be2a2ac1 1042 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
emilmont 80:8e73be2a2ac1 1043 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1044 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1045 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1046
emilmont 80:8e73be2a2ac1 1047 /* Bit 28 : Pin 28. */
emilmont 80:8e73be2a2ac1 1048 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
emilmont 80:8e73be2a2ac1 1049 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
emilmont 80:8e73be2a2ac1 1050 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1051 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1052 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1053
emilmont 80:8e73be2a2ac1 1054 /* Bit 27 : Pin 27. */
emilmont 80:8e73be2a2ac1 1055 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
emilmont 80:8e73be2a2ac1 1056 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
emilmont 80:8e73be2a2ac1 1057 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1058 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1059 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1060
emilmont 80:8e73be2a2ac1 1061 /* Bit 26 : Pin 26. */
emilmont 80:8e73be2a2ac1 1062 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
emilmont 80:8e73be2a2ac1 1063 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
emilmont 80:8e73be2a2ac1 1064 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1065 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1066 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1067
emilmont 80:8e73be2a2ac1 1068 /* Bit 25 : Pin 25. */
emilmont 80:8e73be2a2ac1 1069 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
emilmont 80:8e73be2a2ac1 1070 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
emilmont 80:8e73be2a2ac1 1071 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1072 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1073 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1074
emilmont 80:8e73be2a2ac1 1075 /* Bit 24 : Pin 24. */
emilmont 80:8e73be2a2ac1 1076 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
emilmont 80:8e73be2a2ac1 1077 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
emilmont 80:8e73be2a2ac1 1078 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1079 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1080 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1081
emilmont 80:8e73be2a2ac1 1082 /* Bit 23 : Pin 23. */
emilmont 80:8e73be2a2ac1 1083 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
emilmont 80:8e73be2a2ac1 1084 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
emilmont 80:8e73be2a2ac1 1085 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1086 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1087 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1088
emilmont 80:8e73be2a2ac1 1089 /* Bit 22 : Pin 22. */
emilmont 80:8e73be2a2ac1 1090 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
emilmont 80:8e73be2a2ac1 1091 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
emilmont 80:8e73be2a2ac1 1092 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1093 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1094 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1095
emilmont 80:8e73be2a2ac1 1096 /* Bit 21 : Pin 21. */
emilmont 80:8e73be2a2ac1 1097 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
emilmont 80:8e73be2a2ac1 1098 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
emilmont 80:8e73be2a2ac1 1099 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1100 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1101 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1102
emilmont 80:8e73be2a2ac1 1103 /* Bit 20 : Pin 20. */
emilmont 80:8e73be2a2ac1 1104 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
emilmont 80:8e73be2a2ac1 1105 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
emilmont 80:8e73be2a2ac1 1106 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1107 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1108 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1109
emilmont 80:8e73be2a2ac1 1110 /* Bit 19 : Pin 19. */
emilmont 80:8e73be2a2ac1 1111 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
emilmont 80:8e73be2a2ac1 1112 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
emilmont 80:8e73be2a2ac1 1113 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1114 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1115 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1116
emilmont 80:8e73be2a2ac1 1117 /* Bit 18 : Pin 18. */
emilmont 80:8e73be2a2ac1 1118 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
emilmont 80:8e73be2a2ac1 1119 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
emilmont 80:8e73be2a2ac1 1120 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1121 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1122 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1123
emilmont 80:8e73be2a2ac1 1124 /* Bit 17 : Pin 17. */
emilmont 80:8e73be2a2ac1 1125 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
emilmont 80:8e73be2a2ac1 1126 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
emilmont 80:8e73be2a2ac1 1127 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1128 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1129 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1130
emilmont 80:8e73be2a2ac1 1131 /* Bit 16 : Pin 16. */
emilmont 80:8e73be2a2ac1 1132 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
emilmont 80:8e73be2a2ac1 1133 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
emilmont 80:8e73be2a2ac1 1134 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1135 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1136 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1137
emilmont 80:8e73be2a2ac1 1138 /* Bit 15 : Pin 15. */
emilmont 80:8e73be2a2ac1 1139 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
emilmont 80:8e73be2a2ac1 1140 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
emilmont 80:8e73be2a2ac1 1141 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1142 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1143 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1144
emilmont 80:8e73be2a2ac1 1145 /* Bit 14 : Pin 14. */
emilmont 80:8e73be2a2ac1 1146 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
emilmont 80:8e73be2a2ac1 1147 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
emilmont 80:8e73be2a2ac1 1148 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1149 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1150 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1151
emilmont 80:8e73be2a2ac1 1152 /* Bit 13 : Pin 13. */
emilmont 80:8e73be2a2ac1 1153 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
emilmont 80:8e73be2a2ac1 1154 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
emilmont 80:8e73be2a2ac1 1155 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1156 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1157 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1158
emilmont 80:8e73be2a2ac1 1159 /* Bit 12 : Pin 12. */
emilmont 80:8e73be2a2ac1 1160 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
emilmont 80:8e73be2a2ac1 1161 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
emilmont 80:8e73be2a2ac1 1162 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1163 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1164 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1165
emilmont 80:8e73be2a2ac1 1166 /* Bit 11 : Pin 11. */
emilmont 80:8e73be2a2ac1 1167 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
emilmont 80:8e73be2a2ac1 1168 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
emilmont 80:8e73be2a2ac1 1169 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1170 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1171 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1172
emilmont 80:8e73be2a2ac1 1173 /* Bit 10 : Pin 10. */
emilmont 80:8e73be2a2ac1 1174 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
emilmont 80:8e73be2a2ac1 1175 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
emilmont 80:8e73be2a2ac1 1176 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1177 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1178 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1179
emilmont 80:8e73be2a2ac1 1180 /* Bit 9 : Pin 9. */
emilmont 80:8e73be2a2ac1 1181 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
emilmont 80:8e73be2a2ac1 1182 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
emilmont 80:8e73be2a2ac1 1183 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1184 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1185 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1186
emilmont 80:8e73be2a2ac1 1187 /* Bit 8 : Pin 8. */
emilmont 80:8e73be2a2ac1 1188 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
emilmont 80:8e73be2a2ac1 1189 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
emilmont 80:8e73be2a2ac1 1190 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1191 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1192 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1193
emilmont 80:8e73be2a2ac1 1194 /* Bit 7 : Pin 7. */
emilmont 80:8e73be2a2ac1 1195 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
emilmont 80:8e73be2a2ac1 1196 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
emilmont 80:8e73be2a2ac1 1197 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1198 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1199 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1200
emilmont 80:8e73be2a2ac1 1201 /* Bit 6 : Pin 6. */
emilmont 80:8e73be2a2ac1 1202 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
emilmont 80:8e73be2a2ac1 1203 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
emilmont 80:8e73be2a2ac1 1204 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1205 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1206 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1207
emilmont 80:8e73be2a2ac1 1208 /* Bit 5 : Pin 5. */
emilmont 80:8e73be2a2ac1 1209 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
emilmont 80:8e73be2a2ac1 1210 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
emilmont 80:8e73be2a2ac1 1211 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1212 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1213 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1214
emilmont 80:8e73be2a2ac1 1215 /* Bit 4 : Pin 4. */
emilmont 80:8e73be2a2ac1 1216 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
emilmont 80:8e73be2a2ac1 1217 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
emilmont 80:8e73be2a2ac1 1218 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1219 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1220 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1221
emilmont 80:8e73be2a2ac1 1222 /* Bit 3 : Pin 3. */
emilmont 80:8e73be2a2ac1 1223 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
emilmont 80:8e73be2a2ac1 1224 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
emilmont 80:8e73be2a2ac1 1225 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1226 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1227 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1228
emilmont 80:8e73be2a2ac1 1229 /* Bit 2 : Pin 2. */
emilmont 80:8e73be2a2ac1 1230 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
emilmont 80:8e73be2a2ac1 1231 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
emilmont 80:8e73be2a2ac1 1232 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1233 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1234 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1235
emilmont 80:8e73be2a2ac1 1236 /* Bit 1 : Pin 1. */
emilmont 80:8e73be2a2ac1 1237 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
emilmont 80:8e73be2a2ac1 1238 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
emilmont 80:8e73be2a2ac1 1239 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1240 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1241 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1242
emilmont 80:8e73be2a2ac1 1243 /* Bit 0 : Pin 0. */
emilmont 80:8e73be2a2ac1 1244 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
emilmont 80:8e73be2a2ac1 1245 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
emilmont 80:8e73be2a2ac1 1246 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1247 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1248 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
emilmont 80:8e73be2a2ac1 1249
emilmont 80:8e73be2a2ac1 1250 /* Register: GPIO_OUTCLR */
emilmont 80:8e73be2a2ac1 1251 /* Description: Clear individual bits in GPIO port. */
emilmont 80:8e73be2a2ac1 1252
emilmont 80:8e73be2a2ac1 1253 /* Bit 31 : Pin 31. */
emilmont 80:8e73be2a2ac1 1254 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
emilmont 80:8e73be2a2ac1 1255 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
emilmont 80:8e73be2a2ac1 1256 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1257 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1258 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1259
emilmont 80:8e73be2a2ac1 1260 /* Bit 30 : Pin 30. */
emilmont 80:8e73be2a2ac1 1261 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
emilmont 80:8e73be2a2ac1 1262 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
emilmont 80:8e73be2a2ac1 1263 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1264 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1265 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1266
emilmont 80:8e73be2a2ac1 1267 /* Bit 29 : Pin 29. */
emilmont 80:8e73be2a2ac1 1268 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
emilmont 80:8e73be2a2ac1 1269 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
emilmont 80:8e73be2a2ac1 1270 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1271 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1272 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1273
emilmont 80:8e73be2a2ac1 1274 /* Bit 28 : Pin 28. */
emilmont 80:8e73be2a2ac1 1275 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
emilmont 80:8e73be2a2ac1 1276 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
emilmont 80:8e73be2a2ac1 1277 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1278 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1279 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1280
emilmont 80:8e73be2a2ac1 1281 /* Bit 27 : Pin 27. */
emilmont 80:8e73be2a2ac1 1282 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
emilmont 80:8e73be2a2ac1 1283 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
emilmont 80:8e73be2a2ac1 1284 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1285 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1286 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1287
emilmont 80:8e73be2a2ac1 1288 /* Bit 26 : Pin 26. */
emilmont 80:8e73be2a2ac1 1289 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
emilmont 80:8e73be2a2ac1 1290 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
emilmont 80:8e73be2a2ac1 1291 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1292 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1293 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1294
emilmont 80:8e73be2a2ac1 1295 /* Bit 25 : Pin 25. */
emilmont 80:8e73be2a2ac1 1296 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
emilmont 80:8e73be2a2ac1 1297 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
emilmont 80:8e73be2a2ac1 1298 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1299 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1300 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1301
emilmont 80:8e73be2a2ac1 1302 /* Bit 24 : Pin 24. */
emilmont 80:8e73be2a2ac1 1303 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
emilmont 80:8e73be2a2ac1 1304 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
emilmont 80:8e73be2a2ac1 1305 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1306 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1307 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1308
emilmont 80:8e73be2a2ac1 1309 /* Bit 23 : Pin 23. */
emilmont 80:8e73be2a2ac1 1310 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
emilmont 80:8e73be2a2ac1 1311 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
emilmont 80:8e73be2a2ac1 1312 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1313 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1314 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1315
emilmont 80:8e73be2a2ac1 1316 /* Bit 22 : Pin 22. */
emilmont 80:8e73be2a2ac1 1317 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
emilmont 80:8e73be2a2ac1 1318 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
emilmont 80:8e73be2a2ac1 1319 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1320 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1321 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1322
emilmont 80:8e73be2a2ac1 1323 /* Bit 21 : Pin 21. */
emilmont 80:8e73be2a2ac1 1324 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
emilmont 80:8e73be2a2ac1 1325 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
emilmont 80:8e73be2a2ac1 1326 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1327 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1328 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1329
emilmont 80:8e73be2a2ac1 1330 /* Bit 20 : Pin 20. */
emilmont 80:8e73be2a2ac1 1331 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
emilmont 80:8e73be2a2ac1 1332 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
emilmont 80:8e73be2a2ac1 1333 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1334 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1335 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1336
emilmont 80:8e73be2a2ac1 1337 /* Bit 19 : Pin 19. */
emilmont 80:8e73be2a2ac1 1338 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
emilmont 80:8e73be2a2ac1 1339 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
emilmont 80:8e73be2a2ac1 1340 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1341 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1342 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1343
emilmont 80:8e73be2a2ac1 1344 /* Bit 18 : Pin 18. */
emilmont 80:8e73be2a2ac1 1345 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
emilmont 80:8e73be2a2ac1 1346 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
emilmont 80:8e73be2a2ac1 1347 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1348 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1349 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1350
emilmont 80:8e73be2a2ac1 1351 /* Bit 17 : Pin 17. */
emilmont 80:8e73be2a2ac1 1352 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
emilmont 80:8e73be2a2ac1 1353 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
emilmont 80:8e73be2a2ac1 1354 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1355 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1356 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1357
emilmont 80:8e73be2a2ac1 1358 /* Bit 16 : Pin 16. */
emilmont 80:8e73be2a2ac1 1359 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
emilmont 80:8e73be2a2ac1 1360 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
emilmont 80:8e73be2a2ac1 1361 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1362 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1363 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1364
emilmont 80:8e73be2a2ac1 1365 /* Bit 15 : Pin 15. */
emilmont 80:8e73be2a2ac1 1366 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
emilmont 80:8e73be2a2ac1 1367 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
emilmont 80:8e73be2a2ac1 1368 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1369 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1370 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1371
emilmont 80:8e73be2a2ac1 1372 /* Bit 14 : Pin 14. */
emilmont 80:8e73be2a2ac1 1373 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
emilmont 80:8e73be2a2ac1 1374 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
emilmont 80:8e73be2a2ac1 1375 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1376 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1377 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1378
emilmont 80:8e73be2a2ac1 1379 /* Bit 13 : Pin 13. */
emilmont 80:8e73be2a2ac1 1380 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
emilmont 80:8e73be2a2ac1 1381 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
emilmont 80:8e73be2a2ac1 1382 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1383 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1384 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1385
emilmont 80:8e73be2a2ac1 1386 /* Bit 12 : Pin 12. */
emilmont 80:8e73be2a2ac1 1387 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
emilmont 80:8e73be2a2ac1 1388 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
emilmont 80:8e73be2a2ac1 1389 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1390 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1391 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1392
emilmont 80:8e73be2a2ac1 1393 /* Bit 11 : Pin 11. */
emilmont 80:8e73be2a2ac1 1394 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
emilmont 80:8e73be2a2ac1 1395 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
emilmont 80:8e73be2a2ac1 1396 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1397 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1398 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1399
emilmont 80:8e73be2a2ac1 1400 /* Bit 10 : Pin 10. */
emilmont 80:8e73be2a2ac1 1401 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
emilmont 80:8e73be2a2ac1 1402 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
emilmont 80:8e73be2a2ac1 1403 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1404 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1405 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1406
emilmont 80:8e73be2a2ac1 1407 /* Bit 9 : Pin 9. */
emilmont 80:8e73be2a2ac1 1408 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
emilmont 80:8e73be2a2ac1 1409 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
emilmont 80:8e73be2a2ac1 1410 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1411 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1412 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1413
emilmont 80:8e73be2a2ac1 1414 /* Bit 8 : Pin 8. */
emilmont 80:8e73be2a2ac1 1415 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
emilmont 80:8e73be2a2ac1 1416 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
emilmont 80:8e73be2a2ac1 1417 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1418 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1419 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1420
emilmont 80:8e73be2a2ac1 1421 /* Bit 7 : Pin 7. */
emilmont 80:8e73be2a2ac1 1422 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
emilmont 80:8e73be2a2ac1 1423 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
emilmont 80:8e73be2a2ac1 1424 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1425 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1426 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1427
emilmont 80:8e73be2a2ac1 1428 /* Bit 6 : Pin 6. */
emilmont 80:8e73be2a2ac1 1429 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
emilmont 80:8e73be2a2ac1 1430 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
emilmont 80:8e73be2a2ac1 1431 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1432 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1433 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1434
emilmont 80:8e73be2a2ac1 1435 /* Bit 5 : Pin 5. */
emilmont 80:8e73be2a2ac1 1436 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
emilmont 80:8e73be2a2ac1 1437 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
emilmont 80:8e73be2a2ac1 1438 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1439 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1440 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1441
emilmont 80:8e73be2a2ac1 1442 /* Bit 4 : Pin 4. */
emilmont 80:8e73be2a2ac1 1443 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
emilmont 80:8e73be2a2ac1 1444 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
emilmont 80:8e73be2a2ac1 1445 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1446 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1447 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1448
emilmont 80:8e73be2a2ac1 1449 /* Bit 3 : Pin 3. */
emilmont 80:8e73be2a2ac1 1450 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
emilmont 80:8e73be2a2ac1 1451 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
emilmont 80:8e73be2a2ac1 1452 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1453 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1454 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1455
emilmont 80:8e73be2a2ac1 1456 /* Bit 2 : Pin 2. */
emilmont 80:8e73be2a2ac1 1457 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
emilmont 80:8e73be2a2ac1 1458 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
emilmont 80:8e73be2a2ac1 1459 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1460 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1461 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1462
emilmont 80:8e73be2a2ac1 1463 /* Bit 1 : Pin 1. */
emilmont 80:8e73be2a2ac1 1464 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
emilmont 80:8e73be2a2ac1 1465 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
emilmont 80:8e73be2a2ac1 1466 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1467 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1468 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1469
emilmont 80:8e73be2a2ac1 1470 /* Bit 0 : Pin 0. */
emilmont 80:8e73be2a2ac1 1471 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
emilmont 80:8e73be2a2ac1 1472 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
emilmont 80:8e73be2a2ac1 1473 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
emilmont 80:8e73be2a2ac1 1474 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
emilmont 80:8e73be2a2ac1 1475 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
emilmont 80:8e73be2a2ac1 1476
emilmont 80:8e73be2a2ac1 1477 /* Register: GPIO_IN */
emilmont 80:8e73be2a2ac1 1478 /* Description: Read GPIO port. */
emilmont 80:8e73be2a2ac1 1479
emilmont 80:8e73be2a2ac1 1480 /* Bit 31 : Pin 31. */
emilmont 80:8e73be2a2ac1 1481 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
emilmont 80:8e73be2a2ac1 1482 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
emilmont 80:8e73be2a2ac1 1483 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1484 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1485
emilmont 80:8e73be2a2ac1 1486 /* Bit 30 : Pin 30. */
emilmont 80:8e73be2a2ac1 1487 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
emilmont 80:8e73be2a2ac1 1488 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
emilmont 80:8e73be2a2ac1 1489 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1490 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1491
emilmont 80:8e73be2a2ac1 1492 /* Bit 29 : Pin 29. */
emilmont 80:8e73be2a2ac1 1493 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
emilmont 80:8e73be2a2ac1 1494 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
emilmont 80:8e73be2a2ac1 1495 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1496 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1497
emilmont 80:8e73be2a2ac1 1498 /* Bit 28 : Pin 28. */
emilmont 80:8e73be2a2ac1 1499 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
emilmont 80:8e73be2a2ac1 1500 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
emilmont 80:8e73be2a2ac1 1501 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1502 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1503
emilmont 80:8e73be2a2ac1 1504 /* Bit 27 : Pin 27. */
emilmont 80:8e73be2a2ac1 1505 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
emilmont 80:8e73be2a2ac1 1506 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
emilmont 80:8e73be2a2ac1 1507 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1508 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1509
emilmont 80:8e73be2a2ac1 1510 /* Bit 26 : Pin 26. */
emilmont 80:8e73be2a2ac1 1511 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
emilmont 80:8e73be2a2ac1 1512 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
emilmont 80:8e73be2a2ac1 1513 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1514 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1515
emilmont 80:8e73be2a2ac1 1516 /* Bit 25 : Pin 25. */
emilmont 80:8e73be2a2ac1 1517 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
emilmont 80:8e73be2a2ac1 1518 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
emilmont 80:8e73be2a2ac1 1519 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1520 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1521
emilmont 80:8e73be2a2ac1 1522 /* Bit 24 : Pin 24. */
emilmont 80:8e73be2a2ac1 1523 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
emilmont 80:8e73be2a2ac1 1524 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
emilmont 80:8e73be2a2ac1 1525 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1526 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1527
emilmont 80:8e73be2a2ac1 1528 /* Bit 23 : Pin 23. */
emilmont 80:8e73be2a2ac1 1529 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
emilmont 80:8e73be2a2ac1 1530 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
emilmont 80:8e73be2a2ac1 1531 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1532 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1533
emilmont 80:8e73be2a2ac1 1534 /* Bit 22 : Pin 22. */
emilmont 80:8e73be2a2ac1 1535 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
emilmont 80:8e73be2a2ac1 1536 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
emilmont 80:8e73be2a2ac1 1537 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1538 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1539
emilmont 80:8e73be2a2ac1 1540 /* Bit 21 : Pin 21. */
emilmont 80:8e73be2a2ac1 1541 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
emilmont 80:8e73be2a2ac1 1542 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
emilmont 80:8e73be2a2ac1 1543 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1544 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1545
emilmont 80:8e73be2a2ac1 1546 /* Bit 20 : Pin 20. */
emilmont 80:8e73be2a2ac1 1547 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
emilmont 80:8e73be2a2ac1 1548 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
emilmont 80:8e73be2a2ac1 1549 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1550 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1551
emilmont 80:8e73be2a2ac1 1552 /* Bit 19 : Pin 19. */
emilmont 80:8e73be2a2ac1 1553 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
emilmont 80:8e73be2a2ac1 1554 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
emilmont 80:8e73be2a2ac1 1555 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1556 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1557
emilmont 80:8e73be2a2ac1 1558 /* Bit 18 : Pin 18. */
emilmont 80:8e73be2a2ac1 1559 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
emilmont 80:8e73be2a2ac1 1560 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
emilmont 80:8e73be2a2ac1 1561 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1562 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1563
emilmont 80:8e73be2a2ac1 1564 /* Bit 17 : Pin 17. */
emilmont 80:8e73be2a2ac1 1565 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
emilmont 80:8e73be2a2ac1 1566 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
emilmont 80:8e73be2a2ac1 1567 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1568 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1569
emilmont 80:8e73be2a2ac1 1570 /* Bit 16 : Pin 16. */
emilmont 80:8e73be2a2ac1 1571 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
emilmont 80:8e73be2a2ac1 1572 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
emilmont 80:8e73be2a2ac1 1573 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1574 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1575
emilmont 80:8e73be2a2ac1 1576 /* Bit 15 : Pin 15. */
emilmont 80:8e73be2a2ac1 1577 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
emilmont 80:8e73be2a2ac1 1578 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
emilmont 80:8e73be2a2ac1 1579 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1580 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1581
emilmont 80:8e73be2a2ac1 1582 /* Bit 14 : Pin 14. */
emilmont 80:8e73be2a2ac1 1583 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
emilmont 80:8e73be2a2ac1 1584 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
emilmont 80:8e73be2a2ac1 1585 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1586 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1587
emilmont 80:8e73be2a2ac1 1588 /* Bit 13 : Pin 13. */
emilmont 80:8e73be2a2ac1 1589 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
emilmont 80:8e73be2a2ac1 1590 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
emilmont 80:8e73be2a2ac1 1591 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1592 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1593
emilmont 80:8e73be2a2ac1 1594 /* Bit 12 : Pin 12. */
emilmont 80:8e73be2a2ac1 1595 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
emilmont 80:8e73be2a2ac1 1596 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
emilmont 80:8e73be2a2ac1 1597 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1598 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1599
emilmont 80:8e73be2a2ac1 1600 /* Bit 11 : Pin 11. */
emilmont 80:8e73be2a2ac1 1601 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
emilmont 80:8e73be2a2ac1 1602 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
emilmont 80:8e73be2a2ac1 1603 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1604 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1605
emilmont 80:8e73be2a2ac1 1606 /* Bit 10 : Pin 10. */
emilmont 80:8e73be2a2ac1 1607 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
emilmont 80:8e73be2a2ac1 1608 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
emilmont 80:8e73be2a2ac1 1609 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1610 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1611
emilmont 80:8e73be2a2ac1 1612 /* Bit 9 : Pin 9. */
emilmont 80:8e73be2a2ac1 1613 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
emilmont 80:8e73be2a2ac1 1614 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
emilmont 80:8e73be2a2ac1 1615 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1616 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1617
emilmont 80:8e73be2a2ac1 1618 /* Bit 8 : Pin 8. */
emilmont 80:8e73be2a2ac1 1619 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
emilmont 80:8e73be2a2ac1 1620 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
emilmont 80:8e73be2a2ac1 1621 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1622 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1623
emilmont 80:8e73be2a2ac1 1624 /* Bit 7 : Pin 7. */
emilmont 80:8e73be2a2ac1 1625 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
emilmont 80:8e73be2a2ac1 1626 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
emilmont 80:8e73be2a2ac1 1627 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1628 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1629
emilmont 80:8e73be2a2ac1 1630 /* Bit 6 : Pin 6. */
emilmont 80:8e73be2a2ac1 1631 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
emilmont 80:8e73be2a2ac1 1632 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
emilmont 80:8e73be2a2ac1 1633 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1634 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1635
emilmont 80:8e73be2a2ac1 1636 /* Bit 5 : Pin 5. */
emilmont 80:8e73be2a2ac1 1637 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
emilmont 80:8e73be2a2ac1 1638 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
emilmont 80:8e73be2a2ac1 1639 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1640 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1641
emilmont 80:8e73be2a2ac1 1642 /* Bit 4 : Pin 4. */
emilmont 80:8e73be2a2ac1 1643 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
emilmont 80:8e73be2a2ac1 1644 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
emilmont 80:8e73be2a2ac1 1645 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1646 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1647
emilmont 80:8e73be2a2ac1 1648 /* Bit 3 : Pin 3. */
emilmont 80:8e73be2a2ac1 1649 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
emilmont 80:8e73be2a2ac1 1650 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
emilmont 80:8e73be2a2ac1 1651 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1652 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1653
emilmont 80:8e73be2a2ac1 1654 /* Bit 2 : Pin 2. */
emilmont 80:8e73be2a2ac1 1655 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
emilmont 80:8e73be2a2ac1 1656 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
emilmont 80:8e73be2a2ac1 1657 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1658 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1659
emilmont 80:8e73be2a2ac1 1660 /* Bit 1 : Pin 1. */
emilmont 80:8e73be2a2ac1 1661 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
emilmont 80:8e73be2a2ac1 1662 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
emilmont 80:8e73be2a2ac1 1663 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1664 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1665
emilmont 80:8e73be2a2ac1 1666 /* Bit 0 : Pin 0. */
emilmont 80:8e73be2a2ac1 1667 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
emilmont 80:8e73be2a2ac1 1668 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
emilmont 80:8e73be2a2ac1 1669 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
emilmont 80:8e73be2a2ac1 1670 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
emilmont 80:8e73be2a2ac1 1671
emilmont 80:8e73be2a2ac1 1672 /* Register: GPIO_DIR */
emilmont 80:8e73be2a2ac1 1673 /* Description: Direction of GPIO pins. */
emilmont 80:8e73be2a2ac1 1674
emilmont 80:8e73be2a2ac1 1675 /* Bit 31 : Pin 31. */
emilmont 80:8e73be2a2ac1 1676 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
emilmont 80:8e73be2a2ac1 1677 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
emilmont 80:8e73be2a2ac1 1678 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1679 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1680
emilmont 80:8e73be2a2ac1 1681 /* Bit 30 : Pin 30. */
emilmont 80:8e73be2a2ac1 1682 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
emilmont 80:8e73be2a2ac1 1683 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
emilmont 80:8e73be2a2ac1 1684 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1685 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1686
emilmont 80:8e73be2a2ac1 1687 /* Bit 29 : Pin 29. */
emilmont 80:8e73be2a2ac1 1688 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
emilmont 80:8e73be2a2ac1 1689 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
emilmont 80:8e73be2a2ac1 1690 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1691 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1692
emilmont 80:8e73be2a2ac1 1693 /* Bit 28 : Pin 28. */
emilmont 80:8e73be2a2ac1 1694 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
emilmont 80:8e73be2a2ac1 1695 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
emilmont 80:8e73be2a2ac1 1696 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1697 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1698
emilmont 80:8e73be2a2ac1 1699 /* Bit 27 : Pin 27. */
emilmont 80:8e73be2a2ac1 1700 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
emilmont 80:8e73be2a2ac1 1701 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
emilmont 80:8e73be2a2ac1 1702 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1703 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1704
emilmont 80:8e73be2a2ac1 1705 /* Bit 26 : Pin 26. */
emilmont 80:8e73be2a2ac1 1706 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
emilmont 80:8e73be2a2ac1 1707 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
emilmont 80:8e73be2a2ac1 1708 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1709 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1710
emilmont 80:8e73be2a2ac1 1711 /* Bit 25 : Pin 25. */
emilmont 80:8e73be2a2ac1 1712 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
emilmont 80:8e73be2a2ac1 1713 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
emilmont 80:8e73be2a2ac1 1714 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1715 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1716
emilmont 80:8e73be2a2ac1 1717 /* Bit 24 : Pin 24. */
emilmont 80:8e73be2a2ac1 1718 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
emilmont 80:8e73be2a2ac1 1719 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
emilmont 80:8e73be2a2ac1 1720 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1721 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1722
emilmont 80:8e73be2a2ac1 1723 /* Bit 23 : Pin 23. */
emilmont 80:8e73be2a2ac1 1724 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
emilmont 80:8e73be2a2ac1 1725 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
emilmont 80:8e73be2a2ac1 1726 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1727 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1728
emilmont 80:8e73be2a2ac1 1729 /* Bit 22 : Pin 22. */
emilmont 80:8e73be2a2ac1 1730 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
emilmont 80:8e73be2a2ac1 1731 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
emilmont 80:8e73be2a2ac1 1732 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1733 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1734
emilmont 80:8e73be2a2ac1 1735 /* Bit 21 : Pin 21. */
emilmont 80:8e73be2a2ac1 1736 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
emilmont 80:8e73be2a2ac1 1737 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
emilmont 80:8e73be2a2ac1 1738 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1739 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1740
emilmont 80:8e73be2a2ac1 1741 /* Bit 20 : Pin 20. */
emilmont 80:8e73be2a2ac1 1742 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
emilmont 80:8e73be2a2ac1 1743 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
emilmont 80:8e73be2a2ac1 1744 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1745 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1746
emilmont 80:8e73be2a2ac1 1747 /* Bit 19 : Pin 19. */
emilmont 80:8e73be2a2ac1 1748 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
emilmont 80:8e73be2a2ac1 1749 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
emilmont 80:8e73be2a2ac1 1750 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1751 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1752
emilmont 80:8e73be2a2ac1 1753 /* Bit 18 : Pin 18. */
emilmont 80:8e73be2a2ac1 1754 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
emilmont 80:8e73be2a2ac1 1755 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
emilmont 80:8e73be2a2ac1 1756 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1757 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1758
emilmont 80:8e73be2a2ac1 1759 /* Bit 17 : Pin 17. */
emilmont 80:8e73be2a2ac1 1760 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
emilmont 80:8e73be2a2ac1 1761 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
emilmont 80:8e73be2a2ac1 1762 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1763 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1764
emilmont 80:8e73be2a2ac1 1765 /* Bit 16 : Pin 16. */
emilmont 80:8e73be2a2ac1 1766 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
emilmont 80:8e73be2a2ac1 1767 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
emilmont 80:8e73be2a2ac1 1768 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1769 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1770
emilmont 80:8e73be2a2ac1 1771 /* Bit 15 : Pin 15. */
emilmont 80:8e73be2a2ac1 1772 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
emilmont 80:8e73be2a2ac1 1773 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
emilmont 80:8e73be2a2ac1 1774 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1775 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1776
emilmont 80:8e73be2a2ac1 1777 /* Bit 14 : Pin 14. */
emilmont 80:8e73be2a2ac1 1778 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
emilmont 80:8e73be2a2ac1 1779 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
emilmont 80:8e73be2a2ac1 1780 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1781 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1782
emilmont 80:8e73be2a2ac1 1783 /* Bit 13 : Pin 13. */
emilmont 80:8e73be2a2ac1 1784 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
emilmont 80:8e73be2a2ac1 1785 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
emilmont 80:8e73be2a2ac1 1786 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1787 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1788
emilmont 80:8e73be2a2ac1 1789 /* Bit 12 : Pin 12. */
emilmont 80:8e73be2a2ac1 1790 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
emilmont 80:8e73be2a2ac1 1791 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
emilmont 80:8e73be2a2ac1 1792 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1793 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1794
emilmont 80:8e73be2a2ac1 1795 /* Bit 11 : Pin 11. */
emilmont 80:8e73be2a2ac1 1796 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
emilmont 80:8e73be2a2ac1 1797 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
emilmont 80:8e73be2a2ac1 1798 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1799 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1800
emilmont 80:8e73be2a2ac1 1801 /* Bit 10 : Pin 10. */
emilmont 80:8e73be2a2ac1 1802 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
emilmont 80:8e73be2a2ac1 1803 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
emilmont 80:8e73be2a2ac1 1804 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1805 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1806
emilmont 80:8e73be2a2ac1 1807 /* Bit 9 : Pin 9. */
emilmont 80:8e73be2a2ac1 1808 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
emilmont 80:8e73be2a2ac1 1809 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
emilmont 80:8e73be2a2ac1 1810 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1811 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1812
emilmont 80:8e73be2a2ac1 1813 /* Bit 8 : Pin 8. */
emilmont 80:8e73be2a2ac1 1814 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
emilmont 80:8e73be2a2ac1 1815 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
emilmont 80:8e73be2a2ac1 1816 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1817 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1818
emilmont 80:8e73be2a2ac1 1819 /* Bit 7 : Pin 7. */
emilmont 80:8e73be2a2ac1 1820 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
emilmont 80:8e73be2a2ac1 1821 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
emilmont 80:8e73be2a2ac1 1822 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1823 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1824
emilmont 80:8e73be2a2ac1 1825 /* Bit 6 : Pin 6. */
emilmont 80:8e73be2a2ac1 1826 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
emilmont 80:8e73be2a2ac1 1827 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
emilmont 80:8e73be2a2ac1 1828 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1829 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1830
emilmont 80:8e73be2a2ac1 1831 /* Bit 5 : Pin 5. */
emilmont 80:8e73be2a2ac1 1832 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
emilmont 80:8e73be2a2ac1 1833 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
emilmont 80:8e73be2a2ac1 1834 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1835 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1836
emilmont 80:8e73be2a2ac1 1837 /* Bit 4 : Pin 4. */
emilmont 80:8e73be2a2ac1 1838 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
emilmont 80:8e73be2a2ac1 1839 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
emilmont 80:8e73be2a2ac1 1840 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1841 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1842
emilmont 80:8e73be2a2ac1 1843 /* Bit 3 : Pin 3. */
emilmont 80:8e73be2a2ac1 1844 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
emilmont 80:8e73be2a2ac1 1845 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
emilmont 80:8e73be2a2ac1 1846 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1847 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1848
emilmont 80:8e73be2a2ac1 1849 /* Bit 2 : Pin 2. */
emilmont 80:8e73be2a2ac1 1850 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
emilmont 80:8e73be2a2ac1 1851 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
emilmont 80:8e73be2a2ac1 1852 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1853 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1854
emilmont 80:8e73be2a2ac1 1855 /* Bit 1 : Pin 1. */
emilmont 80:8e73be2a2ac1 1856 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
emilmont 80:8e73be2a2ac1 1857 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
emilmont 80:8e73be2a2ac1 1858 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1859 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1860
emilmont 80:8e73be2a2ac1 1861 /* Bit 0 : Pin 0. */
emilmont 80:8e73be2a2ac1 1862 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
emilmont 80:8e73be2a2ac1 1863 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
emilmont 80:8e73be2a2ac1 1864 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1865 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1866
emilmont 80:8e73be2a2ac1 1867 /* Register: GPIO_DIRSET */
emilmont 80:8e73be2a2ac1 1868 /* Description: DIR set register. */
emilmont 80:8e73be2a2ac1 1869
emilmont 80:8e73be2a2ac1 1870 /* Bit 31 : Set as output pin 31. */
emilmont 80:8e73be2a2ac1 1871 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
emilmont 80:8e73be2a2ac1 1872 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
emilmont 80:8e73be2a2ac1 1873 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1874 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1875 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1876
emilmont 80:8e73be2a2ac1 1877 /* Bit 30 : Set as output pin 30. */
emilmont 80:8e73be2a2ac1 1878 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
emilmont 80:8e73be2a2ac1 1879 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
emilmont 80:8e73be2a2ac1 1880 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1881 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1882 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1883
emilmont 80:8e73be2a2ac1 1884 /* Bit 29 : Set as output pin 29. */
emilmont 80:8e73be2a2ac1 1885 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
emilmont 80:8e73be2a2ac1 1886 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
emilmont 80:8e73be2a2ac1 1887 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1888 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1889 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1890
emilmont 80:8e73be2a2ac1 1891 /* Bit 28 : Set as output pin 28. */
emilmont 80:8e73be2a2ac1 1892 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
emilmont 80:8e73be2a2ac1 1893 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
emilmont 80:8e73be2a2ac1 1894 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1895 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1896 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1897
emilmont 80:8e73be2a2ac1 1898 /* Bit 27 : Set as output pin 27. */
emilmont 80:8e73be2a2ac1 1899 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
emilmont 80:8e73be2a2ac1 1900 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
emilmont 80:8e73be2a2ac1 1901 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1902 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1903 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1904
emilmont 80:8e73be2a2ac1 1905 /* Bit 26 : Set as output pin 26. */
emilmont 80:8e73be2a2ac1 1906 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
emilmont 80:8e73be2a2ac1 1907 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
emilmont 80:8e73be2a2ac1 1908 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1909 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1910 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1911
emilmont 80:8e73be2a2ac1 1912 /* Bit 25 : Set as output pin 25. */
emilmont 80:8e73be2a2ac1 1913 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
emilmont 80:8e73be2a2ac1 1914 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
emilmont 80:8e73be2a2ac1 1915 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1916 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1917 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1918
emilmont 80:8e73be2a2ac1 1919 /* Bit 24 : Set as output pin 24. */
emilmont 80:8e73be2a2ac1 1920 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
emilmont 80:8e73be2a2ac1 1921 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
emilmont 80:8e73be2a2ac1 1922 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1923 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1924 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1925
emilmont 80:8e73be2a2ac1 1926 /* Bit 23 : Set as output pin 23. */
emilmont 80:8e73be2a2ac1 1927 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
emilmont 80:8e73be2a2ac1 1928 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
emilmont 80:8e73be2a2ac1 1929 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1930 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1931 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1932
emilmont 80:8e73be2a2ac1 1933 /* Bit 22 : Set as output pin 22. */
emilmont 80:8e73be2a2ac1 1934 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
emilmont 80:8e73be2a2ac1 1935 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
emilmont 80:8e73be2a2ac1 1936 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1937 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1938 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1939
emilmont 80:8e73be2a2ac1 1940 /* Bit 21 : Set as output pin 21. */
emilmont 80:8e73be2a2ac1 1941 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
emilmont 80:8e73be2a2ac1 1942 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
emilmont 80:8e73be2a2ac1 1943 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1944 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1945 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1946
emilmont 80:8e73be2a2ac1 1947 /* Bit 20 : Set as output pin 20. */
emilmont 80:8e73be2a2ac1 1948 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
emilmont 80:8e73be2a2ac1 1949 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
emilmont 80:8e73be2a2ac1 1950 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1951 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1952 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1953
emilmont 80:8e73be2a2ac1 1954 /* Bit 19 : Set as output pin 19. */
emilmont 80:8e73be2a2ac1 1955 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
emilmont 80:8e73be2a2ac1 1956 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
emilmont 80:8e73be2a2ac1 1957 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1958 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1959 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1960
emilmont 80:8e73be2a2ac1 1961 /* Bit 18 : Set as output pin 18. */
emilmont 80:8e73be2a2ac1 1962 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
emilmont 80:8e73be2a2ac1 1963 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
emilmont 80:8e73be2a2ac1 1964 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1965 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1966 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1967
emilmont 80:8e73be2a2ac1 1968 /* Bit 17 : Set as output pin 17. */
emilmont 80:8e73be2a2ac1 1969 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
emilmont 80:8e73be2a2ac1 1970 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
emilmont 80:8e73be2a2ac1 1971 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1972 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1973 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1974
emilmont 80:8e73be2a2ac1 1975 /* Bit 16 : Set as output pin 16. */
emilmont 80:8e73be2a2ac1 1976 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
emilmont 80:8e73be2a2ac1 1977 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
emilmont 80:8e73be2a2ac1 1978 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1979 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1980 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1981
emilmont 80:8e73be2a2ac1 1982 /* Bit 15 : Set as output pin 15. */
emilmont 80:8e73be2a2ac1 1983 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
emilmont 80:8e73be2a2ac1 1984 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
emilmont 80:8e73be2a2ac1 1985 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1986 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1987 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1988
emilmont 80:8e73be2a2ac1 1989 /* Bit 14 : Set as output pin 14. */
emilmont 80:8e73be2a2ac1 1990 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
emilmont 80:8e73be2a2ac1 1991 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
emilmont 80:8e73be2a2ac1 1992 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 1993 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 1994 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 1995
emilmont 80:8e73be2a2ac1 1996 /* Bit 13 : Set as output pin 13. */
emilmont 80:8e73be2a2ac1 1997 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
emilmont 80:8e73be2a2ac1 1998 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
emilmont 80:8e73be2a2ac1 1999 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2000 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2001 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2002
emilmont 80:8e73be2a2ac1 2003 /* Bit 12 : Set as output pin 12. */
emilmont 80:8e73be2a2ac1 2004 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
emilmont 80:8e73be2a2ac1 2005 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
emilmont 80:8e73be2a2ac1 2006 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2007 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2008 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2009
emilmont 80:8e73be2a2ac1 2010 /* Bit 11 : Set as output pin 11. */
emilmont 80:8e73be2a2ac1 2011 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
emilmont 80:8e73be2a2ac1 2012 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
emilmont 80:8e73be2a2ac1 2013 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2014 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2015 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2016
emilmont 80:8e73be2a2ac1 2017 /* Bit 10 : Set as output pin 10. */
emilmont 80:8e73be2a2ac1 2018 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
emilmont 80:8e73be2a2ac1 2019 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
emilmont 80:8e73be2a2ac1 2020 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2021 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2022 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2023
emilmont 80:8e73be2a2ac1 2024 /* Bit 9 : Set as output pin 9. */
emilmont 80:8e73be2a2ac1 2025 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
emilmont 80:8e73be2a2ac1 2026 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
emilmont 80:8e73be2a2ac1 2027 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2028 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2029 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2030
emilmont 80:8e73be2a2ac1 2031 /* Bit 8 : Set as output pin 8. */
emilmont 80:8e73be2a2ac1 2032 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
emilmont 80:8e73be2a2ac1 2033 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
emilmont 80:8e73be2a2ac1 2034 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2035 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2036 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2037
emilmont 80:8e73be2a2ac1 2038 /* Bit 7 : Set as output pin 7. */
emilmont 80:8e73be2a2ac1 2039 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
emilmont 80:8e73be2a2ac1 2040 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
emilmont 80:8e73be2a2ac1 2041 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2042 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2043 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2044
emilmont 80:8e73be2a2ac1 2045 /* Bit 6 : Set as output pin 6. */
emilmont 80:8e73be2a2ac1 2046 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
emilmont 80:8e73be2a2ac1 2047 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
emilmont 80:8e73be2a2ac1 2048 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2049 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2050 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2051
emilmont 80:8e73be2a2ac1 2052 /* Bit 5 : Set as output pin 5. */
emilmont 80:8e73be2a2ac1 2053 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
emilmont 80:8e73be2a2ac1 2054 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
emilmont 80:8e73be2a2ac1 2055 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2056 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2057 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2058
emilmont 80:8e73be2a2ac1 2059 /* Bit 4 : Set as output pin 4. */
emilmont 80:8e73be2a2ac1 2060 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
emilmont 80:8e73be2a2ac1 2061 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
emilmont 80:8e73be2a2ac1 2062 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2063 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2064 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2065
emilmont 80:8e73be2a2ac1 2066 /* Bit 3 : Set as output pin 3. */
emilmont 80:8e73be2a2ac1 2067 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
emilmont 80:8e73be2a2ac1 2068 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
emilmont 80:8e73be2a2ac1 2069 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2070 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2071 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2072
emilmont 80:8e73be2a2ac1 2073 /* Bit 2 : Set as output pin 2. */
emilmont 80:8e73be2a2ac1 2074 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
emilmont 80:8e73be2a2ac1 2075 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
emilmont 80:8e73be2a2ac1 2076 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2077 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2078 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2079
emilmont 80:8e73be2a2ac1 2080 /* Bit 1 : Set as output pin 1. */
emilmont 80:8e73be2a2ac1 2081 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
emilmont 80:8e73be2a2ac1 2082 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
emilmont 80:8e73be2a2ac1 2083 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2084 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2085 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2086
emilmont 80:8e73be2a2ac1 2087 /* Bit 0 : Set as output pin 0. */
emilmont 80:8e73be2a2ac1 2088 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
emilmont 80:8e73be2a2ac1 2089 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
emilmont 80:8e73be2a2ac1 2090 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2091 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2092 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
emilmont 80:8e73be2a2ac1 2093
emilmont 80:8e73be2a2ac1 2094 /* Register: GPIO_DIRCLR */
emilmont 80:8e73be2a2ac1 2095 /* Description: DIR clear register. */
emilmont 80:8e73be2a2ac1 2096
emilmont 80:8e73be2a2ac1 2097 /* Bit 31 : Set as input pin 31. */
emilmont 80:8e73be2a2ac1 2098 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
emilmont 80:8e73be2a2ac1 2099 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
emilmont 80:8e73be2a2ac1 2100 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2101 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2102 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2103
emilmont 80:8e73be2a2ac1 2104 /* Bit 30 : Set as input pin 30. */
emilmont 80:8e73be2a2ac1 2105 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
emilmont 80:8e73be2a2ac1 2106 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
emilmont 80:8e73be2a2ac1 2107 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2108 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2109 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2110
emilmont 80:8e73be2a2ac1 2111 /* Bit 29 : Set as input pin 29. */
emilmont 80:8e73be2a2ac1 2112 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
emilmont 80:8e73be2a2ac1 2113 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
emilmont 80:8e73be2a2ac1 2114 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2115 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2116 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2117
emilmont 80:8e73be2a2ac1 2118 /* Bit 28 : Set as input pin 28. */
emilmont 80:8e73be2a2ac1 2119 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
emilmont 80:8e73be2a2ac1 2120 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
emilmont 80:8e73be2a2ac1 2121 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2122 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2123 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2124
emilmont 80:8e73be2a2ac1 2125 /* Bit 27 : Set as input pin 27. */
emilmont 80:8e73be2a2ac1 2126 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
emilmont 80:8e73be2a2ac1 2127 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
emilmont 80:8e73be2a2ac1 2128 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2129 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2130 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2131
emilmont 80:8e73be2a2ac1 2132 /* Bit 26 : Set as input pin 26. */
emilmont 80:8e73be2a2ac1 2133 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
emilmont 80:8e73be2a2ac1 2134 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
emilmont 80:8e73be2a2ac1 2135 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2136 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2137 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2138
emilmont 80:8e73be2a2ac1 2139 /* Bit 25 : Set as input pin 25. */
emilmont 80:8e73be2a2ac1 2140 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
emilmont 80:8e73be2a2ac1 2141 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
emilmont 80:8e73be2a2ac1 2142 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2143 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2144 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2145
emilmont 80:8e73be2a2ac1 2146 /* Bit 24 : Set as input pin 24. */
emilmont 80:8e73be2a2ac1 2147 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
emilmont 80:8e73be2a2ac1 2148 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
emilmont 80:8e73be2a2ac1 2149 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2150 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2151 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2152
emilmont 80:8e73be2a2ac1 2153 /* Bit 23 : Set as input pin 23. */
emilmont 80:8e73be2a2ac1 2154 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
emilmont 80:8e73be2a2ac1 2155 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
emilmont 80:8e73be2a2ac1 2156 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2157 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2158 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2159
emilmont 80:8e73be2a2ac1 2160 /* Bit 22 : Set as input pin 22. */
emilmont 80:8e73be2a2ac1 2161 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
emilmont 80:8e73be2a2ac1 2162 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
emilmont 80:8e73be2a2ac1 2163 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2164 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2165 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2166
emilmont 80:8e73be2a2ac1 2167 /* Bit 21 : Set as input pin 21. */
emilmont 80:8e73be2a2ac1 2168 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
emilmont 80:8e73be2a2ac1 2169 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
emilmont 80:8e73be2a2ac1 2170 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2171 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2172 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2173
emilmont 80:8e73be2a2ac1 2174 /* Bit 20 : Set as input pin 20. */
emilmont 80:8e73be2a2ac1 2175 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
emilmont 80:8e73be2a2ac1 2176 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
emilmont 80:8e73be2a2ac1 2177 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2178 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2179 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2180
emilmont 80:8e73be2a2ac1 2181 /* Bit 19 : Set as input pin 19. */
emilmont 80:8e73be2a2ac1 2182 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
emilmont 80:8e73be2a2ac1 2183 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
emilmont 80:8e73be2a2ac1 2184 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2185 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2186 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2187
emilmont 80:8e73be2a2ac1 2188 /* Bit 18 : Set as input pin 18. */
emilmont 80:8e73be2a2ac1 2189 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
emilmont 80:8e73be2a2ac1 2190 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
emilmont 80:8e73be2a2ac1 2191 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2192 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2193 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2194
emilmont 80:8e73be2a2ac1 2195 /* Bit 17 : Set as input pin 17. */
emilmont 80:8e73be2a2ac1 2196 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
emilmont 80:8e73be2a2ac1 2197 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
emilmont 80:8e73be2a2ac1 2198 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2199 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2200 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2201
emilmont 80:8e73be2a2ac1 2202 /* Bit 16 : Set as input pin 16. */
emilmont 80:8e73be2a2ac1 2203 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
emilmont 80:8e73be2a2ac1 2204 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
emilmont 80:8e73be2a2ac1 2205 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2206 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2207 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2208
emilmont 80:8e73be2a2ac1 2209 /* Bit 15 : Set as input pin 15. */
emilmont 80:8e73be2a2ac1 2210 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
emilmont 80:8e73be2a2ac1 2211 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
emilmont 80:8e73be2a2ac1 2212 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2213 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2214 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2215
emilmont 80:8e73be2a2ac1 2216 /* Bit 14 : Set as input pin 14. */
emilmont 80:8e73be2a2ac1 2217 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
emilmont 80:8e73be2a2ac1 2218 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
emilmont 80:8e73be2a2ac1 2219 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2220 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2221 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2222
emilmont 80:8e73be2a2ac1 2223 /* Bit 13 : Set as input pin 13. */
emilmont 80:8e73be2a2ac1 2224 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
emilmont 80:8e73be2a2ac1 2225 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
emilmont 80:8e73be2a2ac1 2226 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2227 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2228 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2229
emilmont 80:8e73be2a2ac1 2230 /* Bit 12 : Set as input pin 12. */
emilmont 80:8e73be2a2ac1 2231 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
emilmont 80:8e73be2a2ac1 2232 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
emilmont 80:8e73be2a2ac1 2233 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2234 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2235 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2236
emilmont 80:8e73be2a2ac1 2237 /* Bit 11 : Set as input pin 11. */
emilmont 80:8e73be2a2ac1 2238 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
emilmont 80:8e73be2a2ac1 2239 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
emilmont 80:8e73be2a2ac1 2240 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2241 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2242 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2243
emilmont 80:8e73be2a2ac1 2244 /* Bit 10 : Set as input pin 10. */
emilmont 80:8e73be2a2ac1 2245 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
emilmont 80:8e73be2a2ac1 2246 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
emilmont 80:8e73be2a2ac1 2247 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2248 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2249 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2250
emilmont 80:8e73be2a2ac1 2251 /* Bit 9 : Set as input pin 9. */
emilmont 80:8e73be2a2ac1 2252 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
emilmont 80:8e73be2a2ac1 2253 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
emilmont 80:8e73be2a2ac1 2254 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2255 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2256 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2257
emilmont 80:8e73be2a2ac1 2258 /* Bit 8 : Set as input pin 8. */
emilmont 80:8e73be2a2ac1 2259 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
emilmont 80:8e73be2a2ac1 2260 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
emilmont 80:8e73be2a2ac1 2261 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2262 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2263 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2264
emilmont 80:8e73be2a2ac1 2265 /* Bit 7 : Set as input pin 7. */
emilmont 80:8e73be2a2ac1 2266 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
emilmont 80:8e73be2a2ac1 2267 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
emilmont 80:8e73be2a2ac1 2268 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2269 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2270 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2271
emilmont 80:8e73be2a2ac1 2272 /* Bit 6 : Set as input pin 6. */
emilmont 80:8e73be2a2ac1 2273 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
emilmont 80:8e73be2a2ac1 2274 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
emilmont 80:8e73be2a2ac1 2275 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2276 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2277 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2278
emilmont 80:8e73be2a2ac1 2279 /* Bit 5 : Set as input pin 5. */
emilmont 80:8e73be2a2ac1 2280 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
emilmont 80:8e73be2a2ac1 2281 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
emilmont 80:8e73be2a2ac1 2282 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2283 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2284 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2285
emilmont 80:8e73be2a2ac1 2286 /* Bit 4 : Set as input pin 4. */
emilmont 80:8e73be2a2ac1 2287 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
emilmont 80:8e73be2a2ac1 2288 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
emilmont 80:8e73be2a2ac1 2289 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2290 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2291 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2292
emilmont 80:8e73be2a2ac1 2293 /* Bit 3 : Set as input pin 3. */
emilmont 80:8e73be2a2ac1 2294 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
emilmont 80:8e73be2a2ac1 2295 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
emilmont 80:8e73be2a2ac1 2296 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2297 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2298 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2299
emilmont 80:8e73be2a2ac1 2300 /* Bit 2 : Set as input pin 2. */
emilmont 80:8e73be2a2ac1 2301 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
emilmont 80:8e73be2a2ac1 2302 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
emilmont 80:8e73be2a2ac1 2303 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2304 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2305 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2306
emilmont 80:8e73be2a2ac1 2307 /* Bit 1 : Set as input pin 1. */
emilmont 80:8e73be2a2ac1 2308 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
emilmont 80:8e73be2a2ac1 2309 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
emilmont 80:8e73be2a2ac1 2310 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2311 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2312 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2313
emilmont 80:8e73be2a2ac1 2314 /* Bit 0 : Set as input pin 0. */
emilmont 80:8e73be2a2ac1 2315 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
emilmont 80:8e73be2a2ac1 2316 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
emilmont 80:8e73be2a2ac1 2317 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
emilmont 80:8e73be2a2ac1 2318 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
emilmont 80:8e73be2a2ac1 2319 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
emilmont 80:8e73be2a2ac1 2320
emilmont 80:8e73be2a2ac1 2321 /* Register: GPIO_PIN_CNF */
emilmont 80:8e73be2a2ac1 2322 /* Description: Configuration of GPIO pins. */
emilmont 80:8e73be2a2ac1 2323
emilmont 80:8e73be2a2ac1 2324 /* Bits 17..16 : Pin sensing mechanism. */
emilmont 80:8e73be2a2ac1 2325 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
emilmont 80:8e73be2a2ac1 2326 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
emilmont 80:8e73be2a2ac1 2327 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 2328 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
emilmont 80:8e73be2a2ac1 2329 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
emilmont 80:8e73be2a2ac1 2330
emilmont 80:8e73be2a2ac1 2331 /* Bits 10..8 : Drive configuration. */
emilmont 80:8e73be2a2ac1 2332 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
emilmont 80:8e73be2a2ac1 2333 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
emilmont 80:8e73be2a2ac1 2334 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
emilmont 80:8e73be2a2ac1 2335 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
emilmont 80:8e73be2a2ac1 2336 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
emilmont 80:8e73be2a2ac1 2337 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
emilmont 80:8e73be2a2ac1 2338 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
emilmont 80:8e73be2a2ac1 2339 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
emilmont 80:8e73be2a2ac1 2340 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
emilmont 80:8e73be2a2ac1 2341 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
emilmont 80:8e73be2a2ac1 2342
emilmont 80:8e73be2a2ac1 2343 /* Bits 3..2 : Pull-up or -down configuration. */
emilmont 80:8e73be2a2ac1 2344 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
emilmont 80:8e73be2a2ac1 2345 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
emilmont 80:8e73be2a2ac1 2346 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
emilmont 80:8e73be2a2ac1 2347 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
emilmont 80:8e73be2a2ac1 2348 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
emilmont 80:8e73be2a2ac1 2349
emilmont 80:8e73be2a2ac1 2350 /* Bit 1 : Connect or disconnect input path. */
emilmont 80:8e73be2a2ac1 2351 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
emilmont 80:8e73be2a2ac1 2352 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
emilmont 80:8e73be2a2ac1 2353 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
emilmont 80:8e73be2a2ac1 2354 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
emilmont 80:8e73be2a2ac1 2355
emilmont 80:8e73be2a2ac1 2356 /* Bit 0 : Pin direction. */
emilmont 80:8e73be2a2ac1 2357 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
emilmont 80:8e73be2a2ac1 2358 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
emilmont 80:8e73be2a2ac1 2359 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
emilmont 80:8e73be2a2ac1 2360 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
emilmont 80:8e73be2a2ac1 2361
emilmont 80:8e73be2a2ac1 2362
emilmont 80:8e73be2a2ac1 2363 /* Peripheral: GPIOTE */
emilmont 80:8e73be2a2ac1 2364 /* Description: GPIO tasks and events. */
emilmont 80:8e73be2a2ac1 2365
emilmont 80:8e73be2a2ac1 2366 /* Register: GPIOTE_INTENSET */
emilmont 80:8e73be2a2ac1 2367 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 2368
emilmont 80:8e73be2a2ac1 2369 /* Bit 31 : Enable interrupt on PORT event. */
emilmont 80:8e73be2a2ac1 2370 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
emilmont 80:8e73be2a2ac1 2371 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
emilmont 80:8e73be2a2ac1 2372 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2373 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2374 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2375
emilmont 80:8e73be2a2ac1 2376 /* Bit 3 : Enable interrupt on IN[3] event. */
emilmont 80:8e73be2a2ac1 2377 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
emilmont 80:8e73be2a2ac1 2378 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
emilmont 80:8e73be2a2ac1 2379 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2380 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2381 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2382
emilmont 80:8e73be2a2ac1 2383 /* Bit 2 : Enable interrupt on IN[2] event. */
emilmont 80:8e73be2a2ac1 2384 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
emilmont 80:8e73be2a2ac1 2385 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
emilmont 80:8e73be2a2ac1 2386 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2387 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2388 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2389
emilmont 80:8e73be2a2ac1 2390 /* Bit 1 : Enable interrupt on IN[1] event. */
emilmont 80:8e73be2a2ac1 2391 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
emilmont 80:8e73be2a2ac1 2392 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
emilmont 80:8e73be2a2ac1 2393 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2394 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2395 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2396
emilmont 80:8e73be2a2ac1 2397 /* Bit 0 : Enable interrupt on IN[0] event. */
emilmont 80:8e73be2a2ac1 2398 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
emilmont 80:8e73be2a2ac1 2399 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
emilmont 80:8e73be2a2ac1 2400 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2401 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2402 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2403
emilmont 80:8e73be2a2ac1 2404 /* Register: GPIOTE_INTENCLR */
emilmont 80:8e73be2a2ac1 2405 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 2406
emilmont 80:8e73be2a2ac1 2407 /* Bit 31 : Disable interrupt on PORT event. */
emilmont 80:8e73be2a2ac1 2408 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
emilmont 80:8e73be2a2ac1 2409 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
emilmont 80:8e73be2a2ac1 2410 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2411 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2412 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2413
emilmont 80:8e73be2a2ac1 2414 /* Bit 3 : Disable interrupt on IN[3] event. */
emilmont 80:8e73be2a2ac1 2415 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
emilmont 80:8e73be2a2ac1 2416 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
emilmont 80:8e73be2a2ac1 2417 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2418 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2419 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2420
emilmont 80:8e73be2a2ac1 2421 /* Bit 2 : Disable interrupt on IN[2] event. */
emilmont 80:8e73be2a2ac1 2422 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
emilmont 80:8e73be2a2ac1 2423 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
emilmont 80:8e73be2a2ac1 2424 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2425 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2426 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2427
emilmont 80:8e73be2a2ac1 2428 /* Bit 1 : Disable interrupt on IN[1] event. */
emilmont 80:8e73be2a2ac1 2429 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
emilmont 80:8e73be2a2ac1 2430 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
emilmont 80:8e73be2a2ac1 2431 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2432 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2433 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2434
emilmont 80:8e73be2a2ac1 2435 /* Bit 0 : Disable interrupt on IN[0] event. */
emilmont 80:8e73be2a2ac1 2436 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
emilmont 80:8e73be2a2ac1 2437 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
emilmont 80:8e73be2a2ac1 2438 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2439 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2440 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2441
emilmont 80:8e73be2a2ac1 2442 /* Register: GPIOTE_CONFIG */
emilmont 80:8e73be2a2ac1 2443 /* Description: Channel configuration registers. */
emilmont 80:8e73be2a2ac1 2444
emilmont 80:8e73be2a2ac1 2445 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
emilmont 80:8e73be2a2ac1 2446 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
emilmont 80:8e73be2a2ac1 2447 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
emilmont 80:8e73be2a2ac1 2448 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
emilmont 80:8e73be2a2ac1 2449 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
emilmont 80:8e73be2a2ac1 2450
emilmont 80:8e73be2a2ac1 2451 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
emilmont 80:8e73be2a2ac1 2452 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
emilmont 80:8e73be2a2ac1 2453 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
emilmont 80:8e73be2a2ac1 2454 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
emilmont 80:8e73be2a2ac1 2455 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
emilmont 80:8e73be2a2ac1 2456 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
emilmont 80:8e73be2a2ac1 2457
emilmont 80:8e73be2a2ac1 2458 /* Bits 12..8 : Pin select. */
emilmont 80:8e73be2a2ac1 2459 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
emilmont 80:8e73be2a2ac1 2460 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
emilmont 80:8e73be2a2ac1 2461
emilmont 80:8e73be2a2ac1 2462 /* Bits 1..0 : Mode */
emilmont 80:8e73be2a2ac1 2463 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
emilmont 80:8e73be2a2ac1 2464 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
emilmont 80:8e73be2a2ac1 2465 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 2466 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
emilmont 80:8e73be2a2ac1 2467 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
emilmont 80:8e73be2a2ac1 2468
emilmont 80:8e73be2a2ac1 2469 /* Register: GPIOTE_POWER */
emilmont 80:8e73be2a2ac1 2470 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 2471
emilmont 80:8e73be2a2ac1 2472 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 2473 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 2474 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 2475 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 2476 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 2477
emilmont 80:8e73be2a2ac1 2478
emilmont 80:8e73be2a2ac1 2479 /* Peripheral: LPCOMP */
emilmont 80:8e73be2a2ac1 2480 /* Description: Wakeup Comparator. */
emilmont 80:8e73be2a2ac1 2481
emilmont 80:8e73be2a2ac1 2482 /* Register: LPCOMP_SHORTS */
emilmont 80:8e73be2a2ac1 2483 /* Description: Shortcut for the LPCOMP. */
emilmont 80:8e73be2a2ac1 2484
emilmont 80:8e73be2a2ac1 2485 /* Bit 4 : Short-cut between CROSS event and STOP task. */
emilmont 80:8e73be2a2ac1 2486 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
emilmont 80:8e73be2a2ac1 2487 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
emilmont 80:8e73be2a2ac1 2488 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 2489 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 2490
emilmont 80:8e73be2a2ac1 2491 /* Bit 3 : Short-cut between UP event and STOP task. */
emilmont 80:8e73be2a2ac1 2492 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
emilmont 80:8e73be2a2ac1 2493 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
emilmont 80:8e73be2a2ac1 2494 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 2495 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 2496
emilmont 80:8e73be2a2ac1 2497 /* Bit 2 : Short-cut between DOWN event and STOP task. */
emilmont 80:8e73be2a2ac1 2498 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
emilmont 80:8e73be2a2ac1 2499 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
emilmont 80:8e73be2a2ac1 2500 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 2501 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 2502
emilmont 80:8e73be2a2ac1 2503 /* Bit 1 : Short-cut between RADY event and STOP task. */
emilmont 80:8e73be2a2ac1 2504 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
emilmont 80:8e73be2a2ac1 2505 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
emilmont 80:8e73be2a2ac1 2506 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 2507 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 2508
emilmont 80:8e73be2a2ac1 2509 /* Bit 0 : Short-cut between READY event and SAMPLE task. */
emilmont 80:8e73be2a2ac1 2510 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
emilmont 80:8e73be2a2ac1 2511 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
emilmont 80:8e73be2a2ac1 2512 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 2513 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 2514
emilmont 80:8e73be2a2ac1 2515 /* Register: LPCOMP_INTENSET */
emilmont 80:8e73be2a2ac1 2516 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 2517
emilmont 80:8e73be2a2ac1 2518 /* Bit 3 : Enable interrupt on CROSS event. */
emilmont 80:8e73be2a2ac1 2519 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
emilmont 80:8e73be2a2ac1 2520 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
emilmont 80:8e73be2a2ac1 2521 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2522 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2523 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2524
emilmont 80:8e73be2a2ac1 2525 /* Bit 2 : Enable interrupt on UP event. */
emilmont 80:8e73be2a2ac1 2526 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
emilmont 80:8e73be2a2ac1 2527 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
emilmont 80:8e73be2a2ac1 2528 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2529 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2530 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2531
emilmont 80:8e73be2a2ac1 2532 /* Bit 1 : Enable interrupt on DOWN event. */
emilmont 80:8e73be2a2ac1 2533 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
emilmont 80:8e73be2a2ac1 2534 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
emilmont 80:8e73be2a2ac1 2535 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2536 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2537 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2538
emilmont 80:8e73be2a2ac1 2539 /* Bit 0 : Enable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 2540 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 2541 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 2542 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2543 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2544 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 2545
emilmont 80:8e73be2a2ac1 2546 /* Register: LPCOMP_INTENCLR */
emilmont 80:8e73be2a2ac1 2547 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 2548
emilmont 80:8e73be2a2ac1 2549 /* Bit 3 : Disable interrupt on CROSS event. */
emilmont 80:8e73be2a2ac1 2550 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
emilmont 80:8e73be2a2ac1 2551 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
emilmont 80:8e73be2a2ac1 2552 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2553 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2554 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2555
emilmont 80:8e73be2a2ac1 2556 /* Bit 2 : Disable interrupt on UP event. */
emilmont 80:8e73be2a2ac1 2557 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
emilmont 80:8e73be2a2ac1 2558 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
emilmont 80:8e73be2a2ac1 2559 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2560 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2561 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2562
emilmont 80:8e73be2a2ac1 2563 /* Bit 1 : Disable interrupt on DOWN event. */
emilmont 80:8e73be2a2ac1 2564 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
emilmont 80:8e73be2a2ac1 2565 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
emilmont 80:8e73be2a2ac1 2566 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2567 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2568 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2569
emilmont 80:8e73be2a2ac1 2570 /* Bit 0 : Disable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 2571 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 2572 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 2573 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 2574 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 2575 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 2576
emilmont 80:8e73be2a2ac1 2577 /* Register: LPCOMP_RESULT */
emilmont 80:8e73be2a2ac1 2578 /* Description: Result of last compare. */
emilmont 80:8e73be2a2ac1 2579
emilmont 80:8e73be2a2ac1 2580 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
emilmont 80:8e73be2a2ac1 2581 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
emilmont 80:8e73be2a2ac1 2582 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
emilmont 80:8e73be2a2ac1 2583 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
emilmont 80:8e73be2a2ac1 2584 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
emilmont 80:8e73be2a2ac1 2585
emilmont 80:8e73be2a2ac1 2586 /* Register: LPCOMP_ENABLE */
emilmont 80:8e73be2a2ac1 2587 /* Description: Enable the LPCOMP. */
emilmont 80:8e73be2a2ac1 2588
emilmont 80:8e73be2a2ac1 2589 /* Bits 1..0 : Enable or disable LPCOMP. */
emilmont 80:8e73be2a2ac1 2590 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 2591 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 2592 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
emilmont 80:8e73be2a2ac1 2593 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
emilmont 80:8e73be2a2ac1 2594
emilmont 80:8e73be2a2ac1 2595 /* Register: LPCOMP_PSEL */
emilmont 80:8e73be2a2ac1 2596 /* Description: Input pin select. */
emilmont 80:8e73be2a2ac1 2597
emilmont 80:8e73be2a2ac1 2598 /* Bits 2..0 : Analog input pin select. */
emilmont 80:8e73be2a2ac1 2599 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
emilmont 80:8e73be2a2ac1 2600 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
emilmont 80:8e73be2a2ac1 2601 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
emilmont 80:8e73be2a2ac1 2602 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
emilmont 80:8e73be2a2ac1 2603 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
emilmont 80:8e73be2a2ac1 2604 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
emilmont 80:8e73be2a2ac1 2605 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
emilmont 80:8e73be2a2ac1 2606 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
emilmont 80:8e73be2a2ac1 2607 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
emilmont 80:8e73be2a2ac1 2608 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
emilmont 80:8e73be2a2ac1 2609
emilmont 80:8e73be2a2ac1 2610 /* Register: LPCOMP_REFSEL */
emilmont 80:8e73be2a2ac1 2611 /* Description: Reference select. */
emilmont 80:8e73be2a2ac1 2612
emilmont 80:8e73be2a2ac1 2613 /* Bits 2..0 : Reference select. */
emilmont 80:8e73be2a2ac1 2614 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
emilmont 80:8e73be2a2ac1 2615 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
emilmont 80:8e73be2a2ac1 2616 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use analog supply with a 1/8 prescaler as reference. */
emilmont 80:8e73be2a2ac1 2617 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use analog supply with a 2/8 prescaler as reference. */
emilmont 80:8e73be2a2ac1 2618 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use analog supply with a 3/8 prescaler as reference. */
emilmont 80:8e73be2a2ac1 2619 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use analog supply with a 4/8 prescaler as reference. */
emilmont 80:8e73be2a2ac1 2620 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use analog supply with a 5/8 prescaler as reference. */
emilmont 80:8e73be2a2ac1 2621 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use analog supply with a 6/8 prescaler as reference. */
emilmont 80:8e73be2a2ac1 2622 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use analog supply with a 7/8 prescaler as reference. */
emilmont 80:8e73be2a2ac1 2623 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
emilmont 80:8e73be2a2ac1 2624
emilmont 80:8e73be2a2ac1 2625 /* Register: LPCOMP_EXTREFSEL */
emilmont 80:8e73be2a2ac1 2626 /* Description: External reference select. */
emilmont 80:8e73be2a2ac1 2627
emilmont 80:8e73be2a2ac1 2628 /* Bit 0 : External analog reference pin selection. */
emilmont 80:8e73be2a2ac1 2629 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
emilmont 80:8e73be2a2ac1 2630 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
emilmont 80:8e73be2a2ac1 2631 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
emilmont 80:8e73be2a2ac1 2632 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
emilmont 80:8e73be2a2ac1 2633
emilmont 80:8e73be2a2ac1 2634 /* Register: LPCOMP_ANADETECT */
emilmont 80:8e73be2a2ac1 2635 /* Description: Analog detect configuration. */
emilmont 80:8e73be2a2ac1 2636
emilmont 80:8e73be2a2ac1 2637 /* Bits 1..0 : Analog detect configuration. */
emilmont 80:8e73be2a2ac1 2638 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
emilmont 80:8e73be2a2ac1 2639 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
emilmont 80:8e73be2a2ac1 2640 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
emilmont 80:8e73be2a2ac1 2641 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
emilmont 80:8e73be2a2ac1 2642 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
emilmont 80:8e73be2a2ac1 2643
emilmont 80:8e73be2a2ac1 2644 /* Register: LPCOMP_POWER */
emilmont 80:8e73be2a2ac1 2645 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 2646
emilmont 80:8e73be2a2ac1 2647 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 2648 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 2649 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 2650 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 2651 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 2652
emilmont 80:8e73be2a2ac1 2653
emilmont 80:8e73be2a2ac1 2654 /* Peripheral: MPU */
emilmont 80:8e73be2a2ac1 2655 /* Description: Memory Protection Unit. */
emilmont 80:8e73be2a2ac1 2656
emilmont 80:8e73be2a2ac1 2657 /* Register: MPU_PERR0 */
emilmont 80:8e73be2a2ac1 2658 /* Description: Configuration of peripherals in mpu regions. */
emilmont 80:8e73be2a2ac1 2659
emilmont 80:8e73be2a2ac1 2660 /* Bit 31 : PPI region configuration. */
emilmont 80:8e73be2a2ac1 2661 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
emilmont 80:8e73be2a2ac1 2662 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
emilmont 80:8e73be2a2ac1 2663 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2664 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2665
emilmont 80:8e73be2a2ac1 2666 /* Bit 30 : NVMC region configuration. */
emilmont 80:8e73be2a2ac1 2667 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
emilmont 80:8e73be2a2ac1 2668 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
emilmont 80:8e73be2a2ac1 2669 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2670 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2671
emilmont 80:8e73be2a2ac1 2672 /* Bit 19 : LPCOMP_COMP region configuration. */
emilmont 80:8e73be2a2ac1 2673 #define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /*!< Position of LPCOMP_COMP field. */
emilmont 80:8e73be2a2ac1 2674 #define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /*!< Bit mask of LPCOMP_COMP field. */
emilmont 80:8e73be2a2ac1 2675 #define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2676 #define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2677
emilmont 80:8e73be2a2ac1 2678 /* Bit 18 : QDEC region configuration. */
emilmont 80:8e73be2a2ac1 2679 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
emilmont 80:8e73be2a2ac1 2680 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
emilmont 80:8e73be2a2ac1 2681 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2682 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2683
emilmont 80:8e73be2a2ac1 2684 /* Bit 17 : RTC1 region configuration. */
emilmont 80:8e73be2a2ac1 2685 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
emilmont 80:8e73be2a2ac1 2686 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
emilmont 80:8e73be2a2ac1 2687 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2688 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2689
emilmont 80:8e73be2a2ac1 2690 /* Bit 16 : WDT region configuration. */
emilmont 80:8e73be2a2ac1 2691 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
emilmont 80:8e73be2a2ac1 2692 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
emilmont 80:8e73be2a2ac1 2693 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2694 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2695
emilmont 80:8e73be2a2ac1 2696 /* Bit 15 : CCM and AAR region configuration. */
emilmont 80:8e73be2a2ac1 2697 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
emilmont 80:8e73be2a2ac1 2698 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
emilmont 80:8e73be2a2ac1 2699 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2700 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2701
emilmont 80:8e73be2a2ac1 2702 /* Bit 14 : ECB region configuration. */
emilmont 80:8e73be2a2ac1 2703 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
emilmont 80:8e73be2a2ac1 2704 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
emilmont 80:8e73be2a2ac1 2705 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2706 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2707
emilmont 80:8e73be2a2ac1 2708 /* Bit 13 : RNG region configuration. */
emilmont 80:8e73be2a2ac1 2709 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
emilmont 80:8e73be2a2ac1 2710 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
emilmont 80:8e73be2a2ac1 2711 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2712 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2713
emilmont 80:8e73be2a2ac1 2714 /* Bit 12 : TEMP region configuration. */
emilmont 80:8e73be2a2ac1 2715 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
emilmont 80:8e73be2a2ac1 2716 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
emilmont 80:8e73be2a2ac1 2717 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2718 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2719
emilmont 80:8e73be2a2ac1 2720 /* Bit 11 : RTC0 region configuration. */
emilmont 80:8e73be2a2ac1 2721 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
emilmont 80:8e73be2a2ac1 2722 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
emilmont 80:8e73be2a2ac1 2723 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2724 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2725
emilmont 80:8e73be2a2ac1 2726 /* Bit 10 : TIMER2 region configuration. */
emilmont 80:8e73be2a2ac1 2727 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
emilmont 80:8e73be2a2ac1 2728 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
emilmont 80:8e73be2a2ac1 2729 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2730 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2731
emilmont 80:8e73be2a2ac1 2732 /* Bit 9 : TIMER1 region configuration. */
emilmont 80:8e73be2a2ac1 2733 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
emilmont 80:8e73be2a2ac1 2734 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
emilmont 80:8e73be2a2ac1 2735 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2736 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2737
emilmont 80:8e73be2a2ac1 2738 /* Bit 8 : TIMER0 region configuration. */
emilmont 80:8e73be2a2ac1 2739 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
emilmont 80:8e73be2a2ac1 2740 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
emilmont 80:8e73be2a2ac1 2741 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2742 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2743
emilmont 80:8e73be2a2ac1 2744 /* Bit 7 : ADC region configuration. */
emilmont 80:8e73be2a2ac1 2745 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
emilmont 80:8e73be2a2ac1 2746 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
emilmont 80:8e73be2a2ac1 2747 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2748 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2749
emilmont 80:8e73be2a2ac1 2750 /* Bit 6 : GPIOTE region configuration. */
emilmont 80:8e73be2a2ac1 2751 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
emilmont 80:8e73be2a2ac1 2752 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
emilmont 80:8e73be2a2ac1 2753 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2754 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2755
emilmont 80:8e73be2a2ac1 2756 /* Bit 4 : SPI1 and TWI1 region configuration. */
emilmont 80:8e73be2a2ac1 2757 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
emilmont 80:8e73be2a2ac1 2758 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
emilmont 80:8e73be2a2ac1 2759 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2760 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2761
emilmont 80:8e73be2a2ac1 2762 /* Bit 3 : SPI0 and TWI0 region configuration. */
emilmont 80:8e73be2a2ac1 2763 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
emilmont 80:8e73be2a2ac1 2764 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
emilmont 80:8e73be2a2ac1 2765 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2766 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2767
emilmont 80:8e73be2a2ac1 2768 /* Bit 2 : UART0 region configuration. */
emilmont 80:8e73be2a2ac1 2769 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
emilmont 80:8e73be2a2ac1 2770 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
emilmont 80:8e73be2a2ac1 2771 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2772 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2773
emilmont 80:8e73be2a2ac1 2774 /* Bit 1 : RADIO region configuration. */
emilmont 80:8e73be2a2ac1 2775 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
emilmont 80:8e73be2a2ac1 2776 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
emilmont 80:8e73be2a2ac1 2777 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2778 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2779
emilmont 80:8e73be2a2ac1 2780 /* Bit 0 : POWER_CLOCK region configuration. */
emilmont 80:8e73be2a2ac1 2781 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
emilmont 80:8e73be2a2ac1 2782 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
emilmont 80:8e73be2a2ac1 2783 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
emilmont 80:8e73be2a2ac1 2784 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
emilmont 80:8e73be2a2ac1 2785
emilmont 80:8e73be2a2ac1 2786 /* Register: MPU_PROTENSET0 */
emilmont 80:8e73be2a2ac1 2787 /* Description: Protection bit enable set register for low addresses. */
emilmont 80:8e73be2a2ac1 2788
emilmont 80:8e73be2a2ac1 2789 /* Bit 31 : Protection enable for region 31. */
emilmont 80:8e73be2a2ac1 2790 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
emilmont 80:8e73be2a2ac1 2791 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
emilmont 80:8e73be2a2ac1 2792 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2793 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2794 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2795
emilmont 80:8e73be2a2ac1 2796 /* Bit 30 : Protection enable for region 30. */
emilmont 80:8e73be2a2ac1 2797 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
emilmont 80:8e73be2a2ac1 2798 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
emilmont 80:8e73be2a2ac1 2799 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2800 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2801 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2802
emilmont 80:8e73be2a2ac1 2803 /* Bit 29 : Protection enable for region 29. */
emilmont 80:8e73be2a2ac1 2804 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
emilmont 80:8e73be2a2ac1 2805 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
emilmont 80:8e73be2a2ac1 2806 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2807 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2808 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2809
emilmont 80:8e73be2a2ac1 2810 /* Bit 28 : Protection enable for region 28. */
emilmont 80:8e73be2a2ac1 2811 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
emilmont 80:8e73be2a2ac1 2812 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
emilmont 80:8e73be2a2ac1 2813 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2814 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2815 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2816
emilmont 80:8e73be2a2ac1 2817 /* Bit 27 : Protection enable for region 27. */
emilmont 80:8e73be2a2ac1 2818 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
emilmont 80:8e73be2a2ac1 2819 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
emilmont 80:8e73be2a2ac1 2820 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2821 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2822 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2823
emilmont 80:8e73be2a2ac1 2824 /* Bit 26 : Protection enable for region 26. */
emilmont 80:8e73be2a2ac1 2825 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
emilmont 80:8e73be2a2ac1 2826 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
emilmont 80:8e73be2a2ac1 2827 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2828 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2829 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2830
emilmont 80:8e73be2a2ac1 2831 /* Bit 25 : Protection enable for region 25. */
emilmont 80:8e73be2a2ac1 2832 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
emilmont 80:8e73be2a2ac1 2833 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
emilmont 80:8e73be2a2ac1 2834 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2835 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2836 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2837
emilmont 80:8e73be2a2ac1 2838 /* Bit 24 : Protection enable for region 24. */
emilmont 80:8e73be2a2ac1 2839 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
emilmont 80:8e73be2a2ac1 2840 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
emilmont 80:8e73be2a2ac1 2841 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2842 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2843 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2844
emilmont 80:8e73be2a2ac1 2845 /* Bit 23 : Protection enable for region 23. */
emilmont 80:8e73be2a2ac1 2846 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
emilmont 80:8e73be2a2ac1 2847 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
emilmont 80:8e73be2a2ac1 2848 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2849 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2850 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2851
emilmont 80:8e73be2a2ac1 2852 /* Bit 22 : Protection enable for region 22. */
emilmont 80:8e73be2a2ac1 2853 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
emilmont 80:8e73be2a2ac1 2854 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
emilmont 80:8e73be2a2ac1 2855 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2856 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2857 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2858
emilmont 80:8e73be2a2ac1 2859 /* Bit 21 : Protection enable for region 21. */
emilmont 80:8e73be2a2ac1 2860 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
emilmont 80:8e73be2a2ac1 2861 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
emilmont 80:8e73be2a2ac1 2862 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2863 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2864 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2865
emilmont 80:8e73be2a2ac1 2866 /* Bit 20 : Protection enable for region 20. */
emilmont 80:8e73be2a2ac1 2867 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
emilmont 80:8e73be2a2ac1 2868 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
emilmont 80:8e73be2a2ac1 2869 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2870 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2871 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2872
emilmont 80:8e73be2a2ac1 2873 /* Bit 19 : Protection enable for region 19. */
emilmont 80:8e73be2a2ac1 2874 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
emilmont 80:8e73be2a2ac1 2875 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
emilmont 80:8e73be2a2ac1 2876 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2877 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2878 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2879
emilmont 80:8e73be2a2ac1 2880 /* Bit 18 : Protection enable for region 18. */
emilmont 80:8e73be2a2ac1 2881 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
emilmont 80:8e73be2a2ac1 2882 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
emilmont 80:8e73be2a2ac1 2883 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2884 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2885 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2886
emilmont 80:8e73be2a2ac1 2887 /* Bit 17 : Protection enable for region 17. */
emilmont 80:8e73be2a2ac1 2888 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
emilmont 80:8e73be2a2ac1 2889 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
emilmont 80:8e73be2a2ac1 2890 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2891 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2892 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2893
emilmont 80:8e73be2a2ac1 2894 /* Bit 16 : Protection enable for region 16. */
emilmont 80:8e73be2a2ac1 2895 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
emilmont 80:8e73be2a2ac1 2896 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
emilmont 80:8e73be2a2ac1 2897 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2898 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2899 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2900
emilmont 80:8e73be2a2ac1 2901 /* Bit 15 : Protection enable for region 15. */
emilmont 80:8e73be2a2ac1 2902 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
emilmont 80:8e73be2a2ac1 2903 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
emilmont 80:8e73be2a2ac1 2904 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2905 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2906 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2907
emilmont 80:8e73be2a2ac1 2908 /* Bit 14 : Protection enable for region 14. */
emilmont 80:8e73be2a2ac1 2909 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
emilmont 80:8e73be2a2ac1 2910 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
emilmont 80:8e73be2a2ac1 2911 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2912 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2913 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2914
emilmont 80:8e73be2a2ac1 2915 /* Bit 13 : Protection enable for region 13. */
emilmont 80:8e73be2a2ac1 2916 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
emilmont 80:8e73be2a2ac1 2917 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
emilmont 80:8e73be2a2ac1 2918 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2919 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2920 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2921
emilmont 80:8e73be2a2ac1 2922 /* Bit 12 : Protection enable for region 12. */
emilmont 80:8e73be2a2ac1 2923 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
emilmont 80:8e73be2a2ac1 2924 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
emilmont 80:8e73be2a2ac1 2925 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2926 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2927 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2928
emilmont 80:8e73be2a2ac1 2929 /* Bit 11 : Protection enable for region 11. */
emilmont 80:8e73be2a2ac1 2930 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
emilmont 80:8e73be2a2ac1 2931 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
emilmont 80:8e73be2a2ac1 2932 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2933 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2934 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2935
emilmont 80:8e73be2a2ac1 2936 /* Bit 10 : Protection enable for region 10. */
emilmont 80:8e73be2a2ac1 2937 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
emilmont 80:8e73be2a2ac1 2938 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
emilmont 80:8e73be2a2ac1 2939 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2940 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2941 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2942
emilmont 80:8e73be2a2ac1 2943 /* Bit 9 : Protection enable for region 9. */
emilmont 80:8e73be2a2ac1 2944 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
emilmont 80:8e73be2a2ac1 2945 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
emilmont 80:8e73be2a2ac1 2946 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2947 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2948 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2949
emilmont 80:8e73be2a2ac1 2950 /* Bit 8 : Protection enable for region 8. */
emilmont 80:8e73be2a2ac1 2951 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
emilmont 80:8e73be2a2ac1 2952 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
emilmont 80:8e73be2a2ac1 2953 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2954 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2955 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2956
emilmont 80:8e73be2a2ac1 2957 /* Bit 7 : Protection enable for region 7. */
emilmont 80:8e73be2a2ac1 2958 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
emilmont 80:8e73be2a2ac1 2959 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
emilmont 80:8e73be2a2ac1 2960 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2961 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2962 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2963
emilmont 80:8e73be2a2ac1 2964 /* Bit 6 : Protection enable for region 6. */
emilmont 80:8e73be2a2ac1 2965 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
emilmont 80:8e73be2a2ac1 2966 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
emilmont 80:8e73be2a2ac1 2967 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2968 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2969 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2970
emilmont 80:8e73be2a2ac1 2971 /* Bit 5 : Protection enable for region 5. */
emilmont 80:8e73be2a2ac1 2972 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
emilmont 80:8e73be2a2ac1 2973 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
emilmont 80:8e73be2a2ac1 2974 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2975 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2976 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2977
emilmont 80:8e73be2a2ac1 2978 /* Bit 4 : Protection enable for region 4. */
emilmont 80:8e73be2a2ac1 2979 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
emilmont 80:8e73be2a2ac1 2980 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
emilmont 80:8e73be2a2ac1 2981 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2982 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2983 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2984
emilmont 80:8e73be2a2ac1 2985 /* Bit 3 : Protection enable for region 3. */
emilmont 80:8e73be2a2ac1 2986 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
emilmont 80:8e73be2a2ac1 2987 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
emilmont 80:8e73be2a2ac1 2988 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2989 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2990 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2991
emilmont 80:8e73be2a2ac1 2992 /* Bit 2 : Protection enable for region 2. */
emilmont 80:8e73be2a2ac1 2993 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
emilmont 80:8e73be2a2ac1 2994 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
emilmont 80:8e73be2a2ac1 2995 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 2996 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 2997 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 2998
emilmont 80:8e73be2a2ac1 2999 /* Bit 1 : Protection enable for region 1. */
emilmont 80:8e73be2a2ac1 3000 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
emilmont 80:8e73be2a2ac1 3001 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
emilmont 80:8e73be2a2ac1 3002 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3003 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3004 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3005
emilmont 80:8e73be2a2ac1 3006 /* Bit 0 : Protection enable for region 0. */
emilmont 80:8e73be2a2ac1 3007 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
emilmont 80:8e73be2a2ac1 3008 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
emilmont 80:8e73be2a2ac1 3009 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3010 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3011 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3012
emilmont 80:8e73be2a2ac1 3013 /* Register: MPU_PROTENSET1 */
emilmont 80:8e73be2a2ac1 3014 /* Description: Protection bit enable set register for high addresses. */
emilmont 80:8e73be2a2ac1 3015
emilmont 80:8e73be2a2ac1 3016 /* Bit 31 : Protection enable for region 63. */
emilmont 80:8e73be2a2ac1 3017 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
emilmont 80:8e73be2a2ac1 3018 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
emilmont 80:8e73be2a2ac1 3019 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3020 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3021 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3022
emilmont 80:8e73be2a2ac1 3023 /* Bit 30 : Protection enable for region 62. */
emilmont 80:8e73be2a2ac1 3024 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
emilmont 80:8e73be2a2ac1 3025 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
emilmont 80:8e73be2a2ac1 3026 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3027 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3028 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3029
emilmont 80:8e73be2a2ac1 3030 /* Bit 29 : Protection enable for region 61. */
emilmont 80:8e73be2a2ac1 3031 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
emilmont 80:8e73be2a2ac1 3032 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
emilmont 80:8e73be2a2ac1 3033 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3034 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3035 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3036
emilmont 80:8e73be2a2ac1 3037 /* Bit 28 : Protection enable for region 60. */
emilmont 80:8e73be2a2ac1 3038 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
emilmont 80:8e73be2a2ac1 3039 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
emilmont 80:8e73be2a2ac1 3040 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3041 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3042 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3043
emilmont 80:8e73be2a2ac1 3044 /* Bit 27 : Protection enable for region 59. */
emilmont 80:8e73be2a2ac1 3045 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
emilmont 80:8e73be2a2ac1 3046 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
emilmont 80:8e73be2a2ac1 3047 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3048 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3049 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3050
emilmont 80:8e73be2a2ac1 3051 /* Bit 26 : Protection enable for region 58. */
emilmont 80:8e73be2a2ac1 3052 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
emilmont 80:8e73be2a2ac1 3053 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
emilmont 80:8e73be2a2ac1 3054 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3055 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3056 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3057
emilmont 80:8e73be2a2ac1 3058 /* Bit 25 : Protection enable for region 57. */
emilmont 80:8e73be2a2ac1 3059 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
emilmont 80:8e73be2a2ac1 3060 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
emilmont 80:8e73be2a2ac1 3061 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3062 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3063 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3064
emilmont 80:8e73be2a2ac1 3065 /* Bit 24 : Protection enable for region 56. */
emilmont 80:8e73be2a2ac1 3066 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
emilmont 80:8e73be2a2ac1 3067 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
emilmont 80:8e73be2a2ac1 3068 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3069 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3070 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3071
emilmont 80:8e73be2a2ac1 3072 /* Bit 23 : Protection enable for region 55. */
emilmont 80:8e73be2a2ac1 3073 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
emilmont 80:8e73be2a2ac1 3074 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
emilmont 80:8e73be2a2ac1 3075 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3076 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3077 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3078
emilmont 80:8e73be2a2ac1 3079 /* Bit 22 : Protection enable for region 54. */
emilmont 80:8e73be2a2ac1 3080 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
emilmont 80:8e73be2a2ac1 3081 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
emilmont 80:8e73be2a2ac1 3082 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3083 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3084 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3085
emilmont 80:8e73be2a2ac1 3086 /* Bit 21 : Protection enable for region 53. */
emilmont 80:8e73be2a2ac1 3087 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
emilmont 80:8e73be2a2ac1 3088 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
emilmont 80:8e73be2a2ac1 3089 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3090 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3091 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3092
emilmont 80:8e73be2a2ac1 3093 /* Bit 20 : Protection enable for region 52. */
emilmont 80:8e73be2a2ac1 3094 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
emilmont 80:8e73be2a2ac1 3095 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
emilmont 80:8e73be2a2ac1 3096 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3097 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3098 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3099
emilmont 80:8e73be2a2ac1 3100 /* Bit 19 : Protection enable for region 51. */
emilmont 80:8e73be2a2ac1 3101 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
emilmont 80:8e73be2a2ac1 3102 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
emilmont 80:8e73be2a2ac1 3103 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3104 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3105 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3106
emilmont 80:8e73be2a2ac1 3107 /* Bit 18 : Protection enable for region 50. */
emilmont 80:8e73be2a2ac1 3108 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
emilmont 80:8e73be2a2ac1 3109 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
emilmont 80:8e73be2a2ac1 3110 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3111 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3112 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3113
emilmont 80:8e73be2a2ac1 3114 /* Bit 17 : Protection enable for region 49. */
emilmont 80:8e73be2a2ac1 3115 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
emilmont 80:8e73be2a2ac1 3116 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
emilmont 80:8e73be2a2ac1 3117 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3118 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3119 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3120
emilmont 80:8e73be2a2ac1 3121 /* Bit 16 : Protection enable for region 48. */
emilmont 80:8e73be2a2ac1 3122 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
emilmont 80:8e73be2a2ac1 3123 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
emilmont 80:8e73be2a2ac1 3124 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3125 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3126 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3127
emilmont 80:8e73be2a2ac1 3128 /* Bit 15 : Protection enable for region 47. */
emilmont 80:8e73be2a2ac1 3129 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
emilmont 80:8e73be2a2ac1 3130 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
emilmont 80:8e73be2a2ac1 3131 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3132 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3133 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3134
emilmont 80:8e73be2a2ac1 3135 /* Bit 14 : Protection enable for region 46. */
emilmont 80:8e73be2a2ac1 3136 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
emilmont 80:8e73be2a2ac1 3137 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
emilmont 80:8e73be2a2ac1 3138 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3139 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3140 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3141
emilmont 80:8e73be2a2ac1 3142 /* Bit 13 : Protection enable for region 45. */
emilmont 80:8e73be2a2ac1 3143 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
emilmont 80:8e73be2a2ac1 3144 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
emilmont 80:8e73be2a2ac1 3145 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3146 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3147 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3148
emilmont 80:8e73be2a2ac1 3149 /* Bit 12 : Protection enable for region 44. */
emilmont 80:8e73be2a2ac1 3150 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
emilmont 80:8e73be2a2ac1 3151 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
emilmont 80:8e73be2a2ac1 3152 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3153 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3154 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3155
emilmont 80:8e73be2a2ac1 3156 /* Bit 11 : Protection enable for region 43. */
emilmont 80:8e73be2a2ac1 3157 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
emilmont 80:8e73be2a2ac1 3158 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
emilmont 80:8e73be2a2ac1 3159 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3160 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3161 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3162
emilmont 80:8e73be2a2ac1 3163 /* Bit 10 : Protection enable for region 42. */
emilmont 80:8e73be2a2ac1 3164 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
emilmont 80:8e73be2a2ac1 3165 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
emilmont 80:8e73be2a2ac1 3166 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3167 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3168 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3169
emilmont 80:8e73be2a2ac1 3170 /* Bit 9 : Protection enable for region 41. */
emilmont 80:8e73be2a2ac1 3171 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
emilmont 80:8e73be2a2ac1 3172 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
emilmont 80:8e73be2a2ac1 3173 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3174 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3175 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3176
emilmont 80:8e73be2a2ac1 3177 /* Bit 8 : Protection enable for region 40. */
emilmont 80:8e73be2a2ac1 3178 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
emilmont 80:8e73be2a2ac1 3179 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
emilmont 80:8e73be2a2ac1 3180 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3181 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3182 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3183
emilmont 80:8e73be2a2ac1 3184 /* Bit 7 : Protection enable for region 39. */
emilmont 80:8e73be2a2ac1 3185 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
emilmont 80:8e73be2a2ac1 3186 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
emilmont 80:8e73be2a2ac1 3187 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3188 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3189 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3190
emilmont 80:8e73be2a2ac1 3191 /* Bit 6 : Protection enable for region 38. */
emilmont 80:8e73be2a2ac1 3192 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
emilmont 80:8e73be2a2ac1 3193 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
emilmont 80:8e73be2a2ac1 3194 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3195 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3196 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3197
emilmont 80:8e73be2a2ac1 3198 /* Bit 5 : Protection enable for region 37. */
emilmont 80:8e73be2a2ac1 3199 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
emilmont 80:8e73be2a2ac1 3200 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
emilmont 80:8e73be2a2ac1 3201 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3202 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3203 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3204
emilmont 80:8e73be2a2ac1 3205 /* Bit 4 : Protection enable for region 36. */
emilmont 80:8e73be2a2ac1 3206 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
emilmont 80:8e73be2a2ac1 3207 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
emilmont 80:8e73be2a2ac1 3208 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3209 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3210 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3211
emilmont 80:8e73be2a2ac1 3212 /* Bit 3 : Protection enable for region 35. */
emilmont 80:8e73be2a2ac1 3213 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
emilmont 80:8e73be2a2ac1 3214 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
emilmont 80:8e73be2a2ac1 3215 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3216 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3217 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3218
emilmont 80:8e73be2a2ac1 3219 /* Bit 2 : Protection enable for region 34. */
emilmont 80:8e73be2a2ac1 3220 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
emilmont 80:8e73be2a2ac1 3221 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
emilmont 80:8e73be2a2ac1 3222 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3223 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3224 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3225
emilmont 80:8e73be2a2ac1 3226 /* Bit 1 : Protection enable for region 33. */
emilmont 80:8e73be2a2ac1 3227 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
emilmont 80:8e73be2a2ac1 3228 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
emilmont 80:8e73be2a2ac1 3229 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3230 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3231 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3232
emilmont 80:8e73be2a2ac1 3233 /* Bit 0 : Protection enable for region 32. */
emilmont 80:8e73be2a2ac1 3234 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
emilmont 80:8e73be2a2ac1 3235 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
emilmont 80:8e73be2a2ac1 3236 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3237 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3238 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
emilmont 80:8e73be2a2ac1 3239
emilmont 80:8e73be2a2ac1 3240 /* Register: MPU_DISABLEINDEBUG */
emilmont 80:8e73be2a2ac1 3241 /* Description: Disable protection mechanism in debug mode. */
emilmont 80:8e73be2a2ac1 3242
emilmont 80:8e73be2a2ac1 3243 /* Bit 0 : Disable protection mechanism in debug mode. */
emilmont 80:8e73be2a2ac1 3244 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
emilmont 80:8e73be2a2ac1 3245 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
emilmont 80:8e73be2a2ac1 3246 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
emilmont 80:8e73be2a2ac1 3247 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
emilmont 80:8e73be2a2ac1 3248
emilmont 80:8e73be2a2ac1 3249
emilmont 80:8e73be2a2ac1 3250 /* Peripheral: NVMC */
emilmont 80:8e73be2a2ac1 3251 /* Description: Non Volatile Memory Controller. */
emilmont 80:8e73be2a2ac1 3252
emilmont 80:8e73be2a2ac1 3253 /* Register: NVMC_READY */
emilmont 80:8e73be2a2ac1 3254 /* Description: Ready flag. */
emilmont 80:8e73be2a2ac1 3255
emilmont 80:8e73be2a2ac1 3256 /* Bit 0 : NVMC ready. */
emilmont 80:8e73be2a2ac1 3257 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 3258 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 3259 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
emilmont 80:8e73be2a2ac1 3260 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
emilmont 80:8e73be2a2ac1 3261
emilmont 80:8e73be2a2ac1 3262 /* Register: NVMC_CONFIG */
emilmont 80:8e73be2a2ac1 3263 /* Description: Configuration register. */
emilmont 80:8e73be2a2ac1 3264
emilmont 80:8e73be2a2ac1 3265 /* Bits 1..0 : Program write enable. */
emilmont 80:8e73be2a2ac1 3266 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
emilmont 80:8e73be2a2ac1 3267 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
emilmont 80:8e73be2a2ac1 3268 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
emilmont 80:8e73be2a2ac1 3269 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
emilmont 80:8e73be2a2ac1 3270 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
emilmont 80:8e73be2a2ac1 3271
emilmont 80:8e73be2a2ac1 3272 /* Register: NVMC_ERASEALL */
emilmont 80:8e73be2a2ac1 3273 /* Description: Register for erasing all non-volatile user memory. */
emilmont 80:8e73be2a2ac1 3274
emilmont 80:8e73be2a2ac1 3275 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
emilmont 80:8e73be2a2ac1 3276 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
emilmont 80:8e73be2a2ac1 3277 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
emilmont 80:8e73be2a2ac1 3278 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
emilmont 80:8e73be2a2ac1 3279 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
emilmont 80:8e73be2a2ac1 3280
emilmont 80:8e73be2a2ac1 3281 /* Register: NVMC_ERASEUICR */
emilmont 80:8e73be2a2ac1 3282 /* Description: Register for start erasing User Information Congfiguration Registers. */
emilmont 80:8e73be2a2ac1 3283
emilmont 80:8e73be2a2ac1 3284 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
emilmont 80:8e73be2a2ac1 3285 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
emilmont 80:8e73be2a2ac1 3286 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
emilmont 80:8e73be2a2ac1 3287 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
emilmont 80:8e73be2a2ac1 3288 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
emilmont 80:8e73be2a2ac1 3289
emilmont 80:8e73be2a2ac1 3290
emilmont 80:8e73be2a2ac1 3291 /* Peripheral: POWER */
emilmont 80:8e73be2a2ac1 3292 /* Description: Power Control. */
emilmont 80:8e73be2a2ac1 3293
emilmont 80:8e73be2a2ac1 3294 /* Register: POWER_INTENSET */
emilmont 80:8e73be2a2ac1 3295 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 3296
emilmont 80:8e73be2a2ac1 3297 /* Bit 2 : Enable interrupt on POFWARN event. */
emilmont 80:8e73be2a2ac1 3298 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
emilmont 80:8e73be2a2ac1 3299 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
emilmont 80:8e73be2a2ac1 3300 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 3301 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 3302 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 3303
emilmont 80:8e73be2a2ac1 3304 /* Register: POWER_INTENCLR */
emilmont 80:8e73be2a2ac1 3305 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 3306
emilmont 80:8e73be2a2ac1 3307 /* Bit 2 : Disable interrupt on POFWARN event. */
emilmont 80:8e73be2a2ac1 3308 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
emilmont 80:8e73be2a2ac1 3309 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
emilmont 80:8e73be2a2ac1 3310 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 3311 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 3312 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 3313
emilmont 80:8e73be2a2ac1 3314 /* Register: POWER_RESETREAS */
emilmont 80:8e73be2a2ac1 3315 /* Description: Reset reason. */
emilmont 80:8e73be2a2ac1 3316
emilmont 80:8e73be2a2ac1 3317 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
emilmont 80:8e73be2a2ac1 3318 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
emilmont 80:8e73be2a2ac1 3319 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
emilmont 80:8e73be2a2ac1 3320
emilmont 80:8e73be2a2ac1 3321 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
emilmont 80:8e73be2a2ac1 3322 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
emilmont 80:8e73be2a2ac1 3323 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
emilmont 80:8e73be2a2ac1 3324
emilmont 80:8e73be2a2ac1 3325 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
emilmont 80:8e73be2a2ac1 3326 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
emilmont 80:8e73be2a2ac1 3327 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
emilmont 80:8e73be2a2ac1 3328
emilmont 80:8e73be2a2ac1 3329 /* Bit 3 : Reset from CPU lock-up detected. */
emilmont 80:8e73be2a2ac1 3330 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
emilmont 80:8e73be2a2ac1 3331 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
emilmont 80:8e73be2a2ac1 3332
emilmont 80:8e73be2a2ac1 3333 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
emilmont 80:8e73be2a2ac1 3334 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
emilmont 80:8e73be2a2ac1 3335 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
emilmont 80:8e73be2a2ac1 3336
emilmont 80:8e73be2a2ac1 3337 /* Bit 1 : Reset from watchdog detected. */
emilmont 80:8e73be2a2ac1 3338 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
emilmont 80:8e73be2a2ac1 3339 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
emilmont 80:8e73be2a2ac1 3340
emilmont 80:8e73be2a2ac1 3341 /* Bit 0 : Reset from pin-reset detected. */
emilmont 80:8e73be2a2ac1 3342 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
emilmont 80:8e73be2a2ac1 3343 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
emilmont 80:8e73be2a2ac1 3344
emilmont 80:8e73be2a2ac1 3345 /* Register: POWER_SYSTEMOFF */
emilmont 80:8e73be2a2ac1 3346 /* Description: System off register. */
emilmont 80:8e73be2a2ac1 3347
emilmont 80:8e73be2a2ac1 3348 /* Bit 0 : Enter system off mode. */
emilmont 80:8e73be2a2ac1 3349 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
emilmont 80:8e73be2a2ac1 3350 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
emilmont 80:8e73be2a2ac1 3351 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
emilmont 80:8e73be2a2ac1 3352
emilmont 80:8e73be2a2ac1 3353 /* Register: POWER_POFCON */
emilmont 80:8e73be2a2ac1 3354 /* Description: Power failure configuration. */
emilmont 80:8e73be2a2ac1 3355
emilmont 80:8e73be2a2ac1 3356 /* Bits 2..1 : Set threshold level. */
emilmont 80:8e73be2a2ac1 3357 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
emilmont 80:8e73be2a2ac1 3358 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
emilmont 80:8e73be2a2ac1 3359 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
emilmont 80:8e73be2a2ac1 3360 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
emilmont 80:8e73be2a2ac1 3361 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
emilmont 80:8e73be2a2ac1 3362 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
emilmont 80:8e73be2a2ac1 3363
emilmont 80:8e73be2a2ac1 3364 /* Bit 0 : Power failure comparator enable. */
emilmont 80:8e73be2a2ac1 3365 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
emilmont 80:8e73be2a2ac1 3366 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
emilmont 80:8e73be2a2ac1 3367 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 3368 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 3369
emilmont 80:8e73be2a2ac1 3370 /* Register: POWER_GPREGRET */
emilmont 80:8e73be2a2ac1 3371 /* Description: General purpose retention register. This register is a retained register. */
emilmont 80:8e73be2a2ac1 3372
emilmont 80:8e73be2a2ac1 3373 /* Bits 7..0 : General purpose retention register. */
emilmont 80:8e73be2a2ac1 3374 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
emilmont 80:8e73be2a2ac1 3375 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
emilmont 80:8e73be2a2ac1 3376
emilmont 80:8e73be2a2ac1 3377 /* Register: POWER_RAMON */
emilmont 80:8e73be2a2ac1 3378 /* Description: Ram on/off. */
emilmont 80:8e73be2a2ac1 3379
emilmont 80:8e73be2a2ac1 3380 /* Bit 19 : RAM block 3 behaviour in OFF mode. */
emilmont 80:8e73be2a2ac1 3381 #define POWER_RAMON_OFFRAM3_Pos (19UL) /*!< Position of OFFRAM3 field. */
emilmont 80:8e73be2a2ac1 3382 #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
emilmont 80:8e73be2a2ac1 3383 #define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
emilmont 80:8e73be2a2ac1 3384 #define POWER_RAMON_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
emilmont 80:8e73be2a2ac1 3385
emilmont 80:8e73be2a2ac1 3386 /* Bit 18 : RAM block 2 behaviour in OFF mode. */
emilmont 80:8e73be2a2ac1 3387 #define POWER_RAMON_OFFRAM2_Pos (18UL) /*!< Position of OFFRAM2 field. */
emilmont 80:8e73be2a2ac1 3388 #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
emilmont 80:8e73be2a2ac1 3389 #define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
emilmont 80:8e73be2a2ac1 3390 #define POWER_RAMON_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
emilmont 80:8e73be2a2ac1 3391
emilmont 80:8e73be2a2ac1 3392 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
emilmont 80:8e73be2a2ac1 3393 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
emilmont 80:8e73be2a2ac1 3394 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
emilmont 80:8e73be2a2ac1 3395 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
emilmont 80:8e73be2a2ac1 3396 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
emilmont 80:8e73be2a2ac1 3397
emilmont 80:8e73be2a2ac1 3398 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
emilmont 80:8e73be2a2ac1 3399 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
emilmont 80:8e73be2a2ac1 3400 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
emilmont 80:8e73be2a2ac1 3401 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
emilmont 80:8e73be2a2ac1 3402 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
emilmont 80:8e73be2a2ac1 3403
emilmont 80:8e73be2a2ac1 3404 /* Bit 3 : RAM block 3 behaviour in ON mode. */
emilmont 80:8e73be2a2ac1 3405 #define POWER_RAMON_ONRAM3_Pos (3UL) /*!< Position of ONRAM3 field. */
emilmont 80:8e73be2a2ac1 3406 #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
emilmont 80:8e73be2a2ac1 3407 #define POWER_RAMON_ONRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in ON mode. */
emilmont 80:8e73be2a2ac1 3408 #define POWER_RAMON_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
emilmont 80:8e73be2a2ac1 3409
emilmont 80:8e73be2a2ac1 3410 /* Bit 2 : RAM block 2 behaviour in ON mode. */
emilmont 80:8e73be2a2ac1 3411 #define POWER_RAMON_ONRAM2_Pos (2UL) /*!< Position of ONRAM2 field. */
emilmont 80:8e73be2a2ac1 3412 #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
emilmont 80:8e73be2a2ac1 3413 #define POWER_RAMON_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
emilmont 80:8e73be2a2ac1 3414 #define POWER_RAMON_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
emilmont 80:8e73be2a2ac1 3415
emilmont 80:8e73be2a2ac1 3416 /* Bit 1 : RAM block 1 behaviour in ON mode. */
emilmont 80:8e73be2a2ac1 3417 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
emilmont 80:8e73be2a2ac1 3418 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
emilmont 80:8e73be2a2ac1 3419 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
emilmont 80:8e73be2a2ac1 3420 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
emilmont 80:8e73be2a2ac1 3421
emilmont 80:8e73be2a2ac1 3422 /* Bit 0 : RAM block 0 behaviour in ON mode. */
emilmont 80:8e73be2a2ac1 3423 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
emilmont 80:8e73be2a2ac1 3424 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
emilmont 80:8e73be2a2ac1 3425 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
emilmont 80:8e73be2a2ac1 3426 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
emilmont 80:8e73be2a2ac1 3427
emilmont 80:8e73be2a2ac1 3428 /* Register: POWER_RESET */
emilmont 80:8e73be2a2ac1 3429 /* Description: Pin reset functionality configuration register. This register is a retained register. */
emilmont 80:8e73be2a2ac1 3430
emilmont 80:8e73be2a2ac1 3431 /* Bit 0 : Enable pin reset in debug interface mode. */
emilmont 80:8e73be2a2ac1 3432 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
emilmont 80:8e73be2a2ac1 3433 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
emilmont 80:8e73be2a2ac1 3434 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
emilmont 80:8e73be2a2ac1 3435 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
emilmont 80:8e73be2a2ac1 3436
emilmont 80:8e73be2a2ac1 3437 /* Register: POWER_DCDCEN */
emilmont 80:8e73be2a2ac1 3438 /* Description: DCDC converter enable configuration register. */
emilmont 80:8e73be2a2ac1 3439
emilmont 80:8e73be2a2ac1 3440 /* Bit 0 : Enable DCDC converter. */
emilmont 80:8e73be2a2ac1 3441 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
emilmont 80:8e73be2a2ac1 3442 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
emilmont 80:8e73be2a2ac1 3443 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
emilmont 80:8e73be2a2ac1 3444 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
emilmont 80:8e73be2a2ac1 3445
emilmont 80:8e73be2a2ac1 3446
emilmont 80:8e73be2a2ac1 3447 /* Peripheral: PPI */
emilmont 80:8e73be2a2ac1 3448 /* Description: PPI controller. */
emilmont 80:8e73be2a2ac1 3449
emilmont 80:8e73be2a2ac1 3450 /* Register: PPI_CHEN */
emilmont 80:8e73be2a2ac1 3451 /* Description: Channel enable. */
emilmont 80:8e73be2a2ac1 3452
emilmont 80:8e73be2a2ac1 3453 /* Bit 31 : Enable PPI channel 31. */
emilmont 80:8e73be2a2ac1 3454 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
emilmont 80:8e73be2a2ac1 3455 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
emilmont 80:8e73be2a2ac1 3456 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3457 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3458
emilmont 80:8e73be2a2ac1 3459 /* Bit 30 : Enable PPI channel 30. */
emilmont 80:8e73be2a2ac1 3460 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
emilmont 80:8e73be2a2ac1 3461 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
emilmont 80:8e73be2a2ac1 3462 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3463 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3464
emilmont 80:8e73be2a2ac1 3465 /* Bit 29 : Enable PPI channel 29. */
emilmont 80:8e73be2a2ac1 3466 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
emilmont 80:8e73be2a2ac1 3467 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
emilmont 80:8e73be2a2ac1 3468 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3469 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3470
emilmont 80:8e73be2a2ac1 3471 /* Bit 28 : Enable PPI channel 28. */
emilmont 80:8e73be2a2ac1 3472 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
emilmont 80:8e73be2a2ac1 3473 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
emilmont 80:8e73be2a2ac1 3474 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3475 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3476
emilmont 80:8e73be2a2ac1 3477 /* Bit 27 : Enable PPI channel 27. */
emilmont 80:8e73be2a2ac1 3478 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
emilmont 80:8e73be2a2ac1 3479 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
emilmont 80:8e73be2a2ac1 3480 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3481 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3482
emilmont 80:8e73be2a2ac1 3483 /* Bit 26 : Enable PPI channel 26. */
emilmont 80:8e73be2a2ac1 3484 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
emilmont 80:8e73be2a2ac1 3485 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
emilmont 80:8e73be2a2ac1 3486 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3487 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3488
emilmont 80:8e73be2a2ac1 3489 /* Bit 25 : Enable PPI channel 25. */
emilmont 80:8e73be2a2ac1 3490 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
emilmont 80:8e73be2a2ac1 3491 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
emilmont 80:8e73be2a2ac1 3492 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3493 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3494
emilmont 80:8e73be2a2ac1 3495 /* Bit 24 : Enable PPI channel 24. */
emilmont 80:8e73be2a2ac1 3496 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
emilmont 80:8e73be2a2ac1 3497 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
emilmont 80:8e73be2a2ac1 3498 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3499 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3500
emilmont 80:8e73be2a2ac1 3501 /* Bit 23 : Enable PPI channel 23. */
emilmont 80:8e73be2a2ac1 3502 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
emilmont 80:8e73be2a2ac1 3503 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
emilmont 80:8e73be2a2ac1 3504 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3505 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3506
emilmont 80:8e73be2a2ac1 3507 /* Bit 22 : Enable PPI channel 22. */
emilmont 80:8e73be2a2ac1 3508 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
emilmont 80:8e73be2a2ac1 3509 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
emilmont 80:8e73be2a2ac1 3510 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3511 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3512
emilmont 80:8e73be2a2ac1 3513 /* Bit 21 : Enable PPI channel 21. */
emilmont 80:8e73be2a2ac1 3514 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
emilmont 80:8e73be2a2ac1 3515 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
emilmont 80:8e73be2a2ac1 3516 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3517 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3518
emilmont 80:8e73be2a2ac1 3519 /* Bit 20 : Enable PPI channel 20. */
emilmont 80:8e73be2a2ac1 3520 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
emilmont 80:8e73be2a2ac1 3521 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
emilmont 80:8e73be2a2ac1 3522 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3523 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3524
emilmont 80:8e73be2a2ac1 3525 /* Bit 15 : Enable PPI channel 15. */
emilmont 80:8e73be2a2ac1 3526 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
emilmont 80:8e73be2a2ac1 3527 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
emilmont 80:8e73be2a2ac1 3528 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3529 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3530
emilmont 80:8e73be2a2ac1 3531 /* Bit 14 : Enable PPI channel 14. */
emilmont 80:8e73be2a2ac1 3532 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
emilmont 80:8e73be2a2ac1 3533 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
emilmont 80:8e73be2a2ac1 3534 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3535 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3536
emilmont 80:8e73be2a2ac1 3537 /* Bit 13 : Enable PPI channel 13. */
emilmont 80:8e73be2a2ac1 3538 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
emilmont 80:8e73be2a2ac1 3539 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
emilmont 80:8e73be2a2ac1 3540 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3541 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3542
emilmont 80:8e73be2a2ac1 3543 /* Bit 12 : Enable PPI channel 12. */
emilmont 80:8e73be2a2ac1 3544 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
emilmont 80:8e73be2a2ac1 3545 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
emilmont 80:8e73be2a2ac1 3546 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3547 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3548
emilmont 80:8e73be2a2ac1 3549 /* Bit 11 : Enable PPI channel 11. */
emilmont 80:8e73be2a2ac1 3550 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
emilmont 80:8e73be2a2ac1 3551 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
emilmont 80:8e73be2a2ac1 3552 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3553 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3554
emilmont 80:8e73be2a2ac1 3555 /* Bit 10 : Enable PPI channel 10. */
emilmont 80:8e73be2a2ac1 3556 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
emilmont 80:8e73be2a2ac1 3557 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
emilmont 80:8e73be2a2ac1 3558 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3559 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3560
emilmont 80:8e73be2a2ac1 3561 /* Bit 9 : Enable PPI channel 9. */
emilmont 80:8e73be2a2ac1 3562 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
emilmont 80:8e73be2a2ac1 3563 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
emilmont 80:8e73be2a2ac1 3564 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3565 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3566
emilmont 80:8e73be2a2ac1 3567 /* Bit 8 : Enable PPI channel 8. */
emilmont 80:8e73be2a2ac1 3568 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
emilmont 80:8e73be2a2ac1 3569 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
emilmont 80:8e73be2a2ac1 3570 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3571 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3572
emilmont 80:8e73be2a2ac1 3573 /* Bit 7 : Enable PPI channel 7. */
emilmont 80:8e73be2a2ac1 3574 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
emilmont 80:8e73be2a2ac1 3575 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
emilmont 80:8e73be2a2ac1 3576 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3577 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3578
emilmont 80:8e73be2a2ac1 3579 /* Bit 6 : Enable PPI channel 6. */
emilmont 80:8e73be2a2ac1 3580 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
emilmont 80:8e73be2a2ac1 3581 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
emilmont 80:8e73be2a2ac1 3582 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3583 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3584
emilmont 80:8e73be2a2ac1 3585 /* Bit 5 : Enable PPI channel 5. */
emilmont 80:8e73be2a2ac1 3586 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
emilmont 80:8e73be2a2ac1 3587 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
emilmont 80:8e73be2a2ac1 3588 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3589 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3590
emilmont 80:8e73be2a2ac1 3591 /* Bit 4 : Enable PPI channel 4. */
emilmont 80:8e73be2a2ac1 3592 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
emilmont 80:8e73be2a2ac1 3593 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
emilmont 80:8e73be2a2ac1 3594 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3595 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3596
emilmont 80:8e73be2a2ac1 3597 /* Bit 3 : Enable PPI channel 3. */
emilmont 80:8e73be2a2ac1 3598 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
emilmont 80:8e73be2a2ac1 3599 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
emilmont 80:8e73be2a2ac1 3600 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
emilmont 80:8e73be2a2ac1 3601 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
emilmont 80:8e73be2a2ac1 3602
emilmont 80:8e73be2a2ac1 3603 /* Bit 2 : Enable PPI channel 2. */
emilmont 80:8e73be2a2ac1 3604 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
emilmont 80:8e73be2a2ac1 3605 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
emilmont 80:8e73be2a2ac1 3606 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3607 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3608
emilmont 80:8e73be2a2ac1 3609 /* Bit 1 : Enable PPI channel 1. */
emilmont 80:8e73be2a2ac1 3610 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
emilmont 80:8e73be2a2ac1 3611 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
emilmont 80:8e73be2a2ac1 3612 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3613 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3614
emilmont 80:8e73be2a2ac1 3615 /* Bit 0 : Enable PPI channel 0. */
emilmont 80:8e73be2a2ac1 3616 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
emilmont 80:8e73be2a2ac1 3617 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
emilmont 80:8e73be2a2ac1 3618 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3619 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3620
emilmont 80:8e73be2a2ac1 3621 /* Register: PPI_CHENSET */
emilmont 80:8e73be2a2ac1 3622 /* Description: Channel enable set. */
emilmont 80:8e73be2a2ac1 3623
emilmont 80:8e73be2a2ac1 3624 /* Bit 31 : Enable PPI channel 31. */
emilmont 80:8e73be2a2ac1 3625 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
emilmont 80:8e73be2a2ac1 3626 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
emilmont 80:8e73be2a2ac1 3627 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3628 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3629 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3630
emilmont 80:8e73be2a2ac1 3631 /* Bit 30 : Enable PPI channel 30. */
emilmont 80:8e73be2a2ac1 3632 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
emilmont 80:8e73be2a2ac1 3633 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
emilmont 80:8e73be2a2ac1 3634 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3635 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3636 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3637
emilmont 80:8e73be2a2ac1 3638 /* Bit 29 : Enable PPI channel 29. */
emilmont 80:8e73be2a2ac1 3639 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
emilmont 80:8e73be2a2ac1 3640 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
emilmont 80:8e73be2a2ac1 3641 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3642 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3643 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3644
emilmont 80:8e73be2a2ac1 3645 /* Bit 28 : Enable PPI channel 28. */
emilmont 80:8e73be2a2ac1 3646 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
emilmont 80:8e73be2a2ac1 3647 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
emilmont 80:8e73be2a2ac1 3648 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3649 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3650 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3651
emilmont 80:8e73be2a2ac1 3652 /* Bit 27 : Enable PPI channel 27. */
emilmont 80:8e73be2a2ac1 3653 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
emilmont 80:8e73be2a2ac1 3654 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
emilmont 80:8e73be2a2ac1 3655 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3656 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3657 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3658
emilmont 80:8e73be2a2ac1 3659 /* Bit 26 : Enable PPI channel 26. */
emilmont 80:8e73be2a2ac1 3660 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
emilmont 80:8e73be2a2ac1 3661 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
emilmont 80:8e73be2a2ac1 3662 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3663 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3664 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3665
emilmont 80:8e73be2a2ac1 3666 /* Bit 25 : Enable PPI channel 25. */
emilmont 80:8e73be2a2ac1 3667 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
emilmont 80:8e73be2a2ac1 3668 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
emilmont 80:8e73be2a2ac1 3669 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3670 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3671 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3672
emilmont 80:8e73be2a2ac1 3673 /* Bit 24 : Enable PPI channel 24. */
emilmont 80:8e73be2a2ac1 3674 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
emilmont 80:8e73be2a2ac1 3675 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
emilmont 80:8e73be2a2ac1 3676 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3677 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3678 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3679
emilmont 80:8e73be2a2ac1 3680 /* Bit 23 : Enable PPI channel 23. */
emilmont 80:8e73be2a2ac1 3681 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
emilmont 80:8e73be2a2ac1 3682 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
emilmont 80:8e73be2a2ac1 3683 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3684 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3685 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3686
emilmont 80:8e73be2a2ac1 3687 /* Bit 22 : Enable PPI channel 22. */
emilmont 80:8e73be2a2ac1 3688 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
emilmont 80:8e73be2a2ac1 3689 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
emilmont 80:8e73be2a2ac1 3690 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3691 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3692 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3693
emilmont 80:8e73be2a2ac1 3694 /* Bit 21 : Enable PPI channel 21. */
emilmont 80:8e73be2a2ac1 3695 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
emilmont 80:8e73be2a2ac1 3696 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
emilmont 80:8e73be2a2ac1 3697 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3698 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3699 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3700
emilmont 80:8e73be2a2ac1 3701 /* Bit 20 : Enable PPI channel 20. */
emilmont 80:8e73be2a2ac1 3702 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
emilmont 80:8e73be2a2ac1 3703 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
emilmont 80:8e73be2a2ac1 3704 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3705 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3706 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3707
emilmont 80:8e73be2a2ac1 3708 /* Bit 15 : Enable PPI channel 15. */
emilmont 80:8e73be2a2ac1 3709 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
emilmont 80:8e73be2a2ac1 3710 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
emilmont 80:8e73be2a2ac1 3711 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3712 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3713 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3714
emilmont 80:8e73be2a2ac1 3715 /* Bit 14 : Enable PPI channel 14. */
emilmont 80:8e73be2a2ac1 3716 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
emilmont 80:8e73be2a2ac1 3717 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
emilmont 80:8e73be2a2ac1 3718 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3719 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3720 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3721
emilmont 80:8e73be2a2ac1 3722 /* Bit 13 : Enable PPI channel 13. */
emilmont 80:8e73be2a2ac1 3723 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
emilmont 80:8e73be2a2ac1 3724 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
emilmont 80:8e73be2a2ac1 3725 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3726 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3727 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3728
emilmont 80:8e73be2a2ac1 3729 /* Bit 12 : Enable PPI channel 12. */
emilmont 80:8e73be2a2ac1 3730 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
emilmont 80:8e73be2a2ac1 3731 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
emilmont 80:8e73be2a2ac1 3732 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3733 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3734 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3735
emilmont 80:8e73be2a2ac1 3736 /* Bit 11 : Enable PPI channel 11. */
emilmont 80:8e73be2a2ac1 3737 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
emilmont 80:8e73be2a2ac1 3738 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
emilmont 80:8e73be2a2ac1 3739 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3740 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3741 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3742
emilmont 80:8e73be2a2ac1 3743 /* Bit 10 : Enable PPI channel 10. */
emilmont 80:8e73be2a2ac1 3744 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
emilmont 80:8e73be2a2ac1 3745 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
emilmont 80:8e73be2a2ac1 3746 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3747 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3748 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3749
emilmont 80:8e73be2a2ac1 3750 /* Bit 9 : Enable PPI channel 9. */
emilmont 80:8e73be2a2ac1 3751 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
emilmont 80:8e73be2a2ac1 3752 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
emilmont 80:8e73be2a2ac1 3753 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3754 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3755 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3756
emilmont 80:8e73be2a2ac1 3757 /* Bit 8 : Enable PPI channel 8. */
emilmont 80:8e73be2a2ac1 3758 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
emilmont 80:8e73be2a2ac1 3759 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
emilmont 80:8e73be2a2ac1 3760 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3761 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3762 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3763
emilmont 80:8e73be2a2ac1 3764 /* Bit 7 : Enable PPI channel 7. */
emilmont 80:8e73be2a2ac1 3765 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
emilmont 80:8e73be2a2ac1 3766 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
emilmont 80:8e73be2a2ac1 3767 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3768 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3769 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3770
emilmont 80:8e73be2a2ac1 3771 /* Bit 6 : Enable PPI channel 6. */
emilmont 80:8e73be2a2ac1 3772 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
emilmont 80:8e73be2a2ac1 3773 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
emilmont 80:8e73be2a2ac1 3774 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3775 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3776 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3777
emilmont 80:8e73be2a2ac1 3778 /* Bit 5 : Enable PPI channel 5. */
emilmont 80:8e73be2a2ac1 3779 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
emilmont 80:8e73be2a2ac1 3780 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
emilmont 80:8e73be2a2ac1 3781 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3782 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3783 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3784
emilmont 80:8e73be2a2ac1 3785 /* Bit 4 : Enable PPI channel 4. */
emilmont 80:8e73be2a2ac1 3786 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
emilmont 80:8e73be2a2ac1 3787 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
emilmont 80:8e73be2a2ac1 3788 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3789 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3790 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3791
emilmont 80:8e73be2a2ac1 3792 /* Bit 3 : Enable PPI channel 3. */
emilmont 80:8e73be2a2ac1 3793 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
emilmont 80:8e73be2a2ac1 3794 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
emilmont 80:8e73be2a2ac1 3795 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3796 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3797 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3798
emilmont 80:8e73be2a2ac1 3799 /* Bit 2 : Enable PPI channel 2. */
emilmont 80:8e73be2a2ac1 3800 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
emilmont 80:8e73be2a2ac1 3801 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
emilmont 80:8e73be2a2ac1 3802 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3803 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3804 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3805
emilmont 80:8e73be2a2ac1 3806 /* Bit 1 : Enable PPI channel 1. */
emilmont 80:8e73be2a2ac1 3807 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
emilmont 80:8e73be2a2ac1 3808 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
emilmont 80:8e73be2a2ac1 3809 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3810 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3811 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3812
emilmont 80:8e73be2a2ac1 3813 /* Bit 0 : Enable PPI channel 0. */
emilmont 80:8e73be2a2ac1 3814 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
emilmont 80:8e73be2a2ac1 3815 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
emilmont 80:8e73be2a2ac1 3816 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3817 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3818 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
emilmont 80:8e73be2a2ac1 3819
emilmont 80:8e73be2a2ac1 3820 /* Register: PPI_CHENCLR */
emilmont 80:8e73be2a2ac1 3821 /* Description: Channel enable clear. */
emilmont 80:8e73be2a2ac1 3822
emilmont 80:8e73be2a2ac1 3823 /* Bit 31 : Disable PPI channel 31. */
emilmont 80:8e73be2a2ac1 3824 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
emilmont 80:8e73be2a2ac1 3825 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
emilmont 80:8e73be2a2ac1 3826 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3827 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3828 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3829
emilmont 80:8e73be2a2ac1 3830 /* Bit 30 : Disable PPI channel 30. */
emilmont 80:8e73be2a2ac1 3831 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
emilmont 80:8e73be2a2ac1 3832 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
emilmont 80:8e73be2a2ac1 3833 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3834 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3835 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3836
emilmont 80:8e73be2a2ac1 3837 /* Bit 29 : Disable PPI channel 29. */
emilmont 80:8e73be2a2ac1 3838 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
emilmont 80:8e73be2a2ac1 3839 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
emilmont 80:8e73be2a2ac1 3840 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3841 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3842 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3843
emilmont 80:8e73be2a2ac1 3844 /* Bit 28 : Disable PPI channel 28. */
emilmont 80:8e73be2a2ac1 3845 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
emilmont 80:8e73be2a2ac1 3846 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
emilmont 80:8e73be2a2ac1 3847 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3848 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3849 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3850
emilmont 80:8e73be2a2ac1 3851 /* Bit 27 : Disable PPI channel 27. */
emilmont 80:8e73be2a2ac1 3852 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
emilmont 80:8e73be2a2ac1 3853 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
emilmont 80:8e73be2a2ac1 3854 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3855 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3856 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3857
emilmont 80:8e73be2a2ac1 3858 /* Bit 26 : Disable PPI channel 26. */
emilmont 80:8e73be2a2ac1 3859 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
emilmont 80:8e73be2a2ac1 3860 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
emilmont 80:8e73be2a2ac1 3861 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3862 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3863 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3864
emilmont 80:8e73be2a2ac1 3865 /* Bit 25 : Disable PPI channel 25. */
emilmont 80:8e73be2a2ac1 3866 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
emilmont 80:8e73be2a2ac1 3867 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
emilmont 80:8e73be2a2ac1 3868 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3869 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3870 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3871
emilmont 80:8e73be2a2ac1 3872 /* Bit 24 : Disable PPI channel 24. */
emilmont 80:8e73be2a2ac1 3873 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
emilmont 80:8e73be2a2ac1 3874 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
emilmont 80:8e73be2a2ac1 3875 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3876 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3877 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3878
emilmont 80:8e73be2a2ac1 3879 /* Bit 23 : Disable PPI channel 23. */
emilmont 80:8e73be2a2ac1 3880 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
emilmont 80:8e73be2a2ac1 3881 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
emilmont 80:8e73be2a2ac1 3882 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3883 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3884 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3885
emilmont 80:8e73be2a2ac1 3886 /* Bit 22 : Disable PPI channel 22. */
emilmont 80:8e73be2a2ac1 3887 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
emilmont 80:8e73be2a2ac1 3888 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
emilmont 80:8e73be2a2ac1 3889 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3890 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3891 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3892
emilmont 80:8e73be2a2ac1 3893 /* Bit 21 : Disable PPI channel 21. */
emilmont 80:8e73be2a2ac1 3894 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
emilmont 80:8e73be2a2ac1 3895 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
emilmont 80:8e73be2a2ac1 3896 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3897 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3898 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3899
emilmont 80:8e73be2a2ac1 3900 /* Bit 20 : Disable PPI channel 20. */
emilmont 80:8e73be2a2ac1 3901 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
emilmont 80:8e73be2a2ac1 3902 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
emilmont 80:8e73be2a2ac1 3903 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3904 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3905 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3906
emilmont 80:8e73be2a2ac1 3907 /* Bit 15 : Disable PPI channel 15. */
emilmont 80:8e73be2a2ac1 3908 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
emilmont 80:8e73be2a2ac1 3909 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
emilmont 80:8e73be2a2ac1 3910 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3911 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3912 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3913
emilmont 80:8e73be2a2ac1 3914 /* Bit 14 : Disable PPI channel 14. */
emilmont 80:8e73be2a2ac1 3915 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
emilmont 80:8e73be2a2ac1 3916 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
emilmont 80:8e73be2a2ac1 3917 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3918 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3919 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3920
emilmont 80:8e73be2a2ac1 3921 /* Bit 13 : Disable PPI channel 13. */
emilmont 80:8e73be2a2ac1 3922 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
emilmont 80:8e73be2a2ac1 3923 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
emilmont 80:8e73be2a2ac1 3924 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3925 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3926 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3927
emilmont 80:8e73be2a2ac1 3928 /* Bit 12 : Disable PPI channel 12. */
emilmont 80:8e73be2a2ac1 3929 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
emilmont 80:8e73be2a2ac1 3930 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
emilmont 80:8e73be2a2ac1 3931 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3932 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3933 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3934
emilmont 80:8e73be2a2ac1 3935 /* Bit 11 : Disable PPI channel 11. */
emilmont 80:8e73be2a2ac1 3936 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
emilmont 80:8e73be2a2ac1 3937 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
emilmont 80:8e73be2a2ac1 3938 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3939 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3940 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3941
emilmont 80:8e73be2a2ac1 3942 /* Bit 10 : Disable PPI channel 10. */
emilmont 80:8e73be2a2ac1 3943 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
emilmont 80:8e73be2a2ac1 3944 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
emilmont 80:8e73be2a2ac1 3945 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3946 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3947 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3948
emilmont 80:8e73be2a2ac1 3949 /* Bit 9 : Disable PPI channel 9. */
emilmont 80:8e73be2a2ac1 3950 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
emilmont 80:8e73be2a2ac1 3951 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
emilmont 80:8e73be2a2ac1 3952 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3953 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3954 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3955
emilmont 80:8e73be2a2ac1 3956 /* Bit 8 : Disable PPI channel 8. */
emilmont 80:8e73be2a2ac1 3957 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
emilmont 80:8e73be2a2ac1 3958 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
emilmont 80:8e73be2a2ac1 3959 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3960 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3961 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3962
emilmont 80:8e73be2a2ac1 3963 /* Bit 7 : Disable PPI channel 7. */
emilmont 80:8e73be2a2ac1 3964 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
emilmont 80:8e73be2a2ac1 3965 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
emilmont 80:8e73be2a2ac1 3966 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3967 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3968 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3969
emilmont 80:8e73be2a2ac1 3970 /* Bit 6 : Disable PPI channel 6. */
emilmont 80:8e73be2a2ac1 3971 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
emilmont 80:8e73be2a2ac1 3972 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
emilmont 80:8e73be2a2ac1 3973 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3974 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3975 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3976
emilmont 80:8e73be2a2ac1 3977 /* Bit 5 : Disable PPI channel 5. */
emilmont 80:8e73be2a2ac1 3978 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
emilmont 80:8e73be2a2ac1 3979 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
emilmont 80:8e73be2a2ac1 3980 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3981 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3982 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3983
emilmont 80:8e73be2a2ac1 3984 /* Bit 4 : Disable PPI channel 4. */
emilmont 80:8e73be2a2ac1 3985 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
emilmont 80:8e73be2a2ac1 3986 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
emilmont 80:8e73be2a2ac1 3987 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3988 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3989 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3990
emilmont 80:8e73be2a2ac1 3991 /* Bit 3 : Disable PPI channel 3. */
emilmont 80:8e73be2a2ac1 3992 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
emilmont 80:8e73be2a2ac1 3993 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
emilmont 80:8e73be2a2ac1 3994 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 3995 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 3996 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 3997
emilmont 80:8e73be2a2ac1 3998 /* Bit 2 : Disable PPI channel 2. */
emilmont 80:8e73be2a2ac1 3999 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
emilmont 80:8e73be2a2ac1 4000 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
emilmont 80:8e73be2a2ac1 4001 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 4002 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 4003 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 4004
emilmont 80:8e73be2a2ac1 4005 /* Bit 1 : Disable PPI channel 1. */
emilmont 80:8e73be2a2ac1 4006 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
emilmont 80:8e73be2a2ac1 4007 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
emilmont 80:8e73be2a2ac1 4008 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 4009 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 4010 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 4011
emilmont 80:8e73be2a2ac1 4012 /* Bit 0 : Disable PPI channel 0. */
emilmont 80:8e73be2a2ac1 4013 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
emilmont 80:8e73be2a2ac1 4014 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
emilmont 80:8e73be2a2ac1 4015 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
emilmont 80:8e73be2a2ac1 4016 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
emilmont 80:8e73be2a2ac1 4017 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
emilmont 80:8e73be2a2ac1 4018
emilmont 80:8e73be2a2ac1 4019 /* Register: PPI_CHG */
emilmont 80:8e73be2a2ac1 4020 /* Description: Channel group configuration. */
emilmont 80:8e73be2a2ac1 4021
emilmont 80:8e73be2a2ac1 4022 /* Bit 31 : Include CH31 in channel group. */
emilmont 80:8e73be2a2ac1 4023 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
emilmont 80:8e73be2a2ac1 4024 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
emilmont 80:8e73be2a2ac1 4025 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4026 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4027
emilmont 80:8e73be2a2ac1 4028 /* Bit 30 : Include CH30 in channel group. */
emilmont 80:8e73be2a2ac1 4029 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
emilmont 80:8e73be2a2ac1 4030 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
emilmont 80:8e73be2a2ac1 4031 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4032 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4033
emilmont 80:8e73be2a2ac1 4034 /* Bit 29 : Include CH29 in channel group. */
emilmont 80:8e73be2a2ac1 4035 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
emilmont 80:8e73be2a2ac1 4036 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
emilmont 80:8e73be2a2ac1 4037 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4038 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4039
emilmont 80:8e73be2a2ac1 4040 /* Bit 28 : Include CH28 in channel group. */
emilmont 80:8e73be2a2ac1 4041 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
emilmont 80:8e73be2a2ac1 4042 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
emilmont 80:8e73be2a2ac1 4043 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4044 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4045
emilmont 80:8e73be2a2ac1 4046 /* Bit 27 : Include CH27 in channel group. */
emilmont 80:8e73be2a2ac1 4047 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
emilmont 80:8e73be2a2ac1 4048 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
emilmont 80:8e73be2a2ac1 4049 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4050 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4051
emilmont 80:8e73be2a2ac1 4052 /* Bit 26 : Include CH26 in channel group. */
emilmont 80:8e73be2a2ac1 4053 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
emilmont 80:8e73be2a2ac1 4054 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
emilmont 80:8e73be2a2ac1 4055 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4056 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4057
emilmont 80:8e73be2a2ac1 4058 /* Bit 25 : Include CH25 in channel group. */
emilmont 80:8e73be2a2ac1 4059 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
emilmont 80:8e73be2a2ac1 4060 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
emilmont 80:8e73be2a2ac1 4061 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4062 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4063
emilmont 80:8e73be2a2ac1 4064 /* Bit 24 : Include CH24 in channel group. */
emilmont 80:8e73be2a2ac1 4065 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
emilmont 80:8e73be2a2ac1 4066 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
emilmont 80:8e73be2a2ac1 4067 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4068 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4069
emilmont 80:8e73be2a2ac1 4070 /* Bit 23 : Include CH23 in channel group. */
emilmont 80:8e73be2a2ac1 4071 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
emilmont 80:8e73be2a2ac1 4072 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
emilmont 80:8e73be2a2ac1 4073 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4074 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4075
emilmont 80:8e73be2a2ac1 4076 /* Bit 22 : Include CH22 in channel group. */
emilmont 80:8e73be2a2ac1 4077 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
emilmont 80:8e73be2a2ac1 4078 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
emilmont 80:8e73be2a2ac1 4079 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4080 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4081
emilmont 80:8e73be2a2ac1 4082 /* Bit 21 : Include CH21 in channel group. */
emilmont 80:8e73be2a2ac1 4083 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
emilmont 80:8e73be2a2ac1 4084 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
emilmont 80:8e73be2a2ac1 4085 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4086 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4087
emilmont 80:8e73be2a2ac1 4088 /* Bit 20 : Include CH20 in channel group. */
emilmont 80:8e73be2a2ac1 4089 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
emilmont 80:8e73be2a2ac1 4090 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
emilmont 80:8e73be2a2ac1 4091 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4092 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4093
emilmont 80:8e73be2a2ac1 4094 /* Bit 15 : Include CH15 in channel group. */
emilmont 80:8e73be2a2ac1 4095 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
emilmont 80:8e73be2a2ac1 4096 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
emilmont 80:8e73be2a2ac1 4097 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4098 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4099
emilmont 80:8e73be2a2ac1 4100 /* Bit 14 : Include CH14 in channel group. */
emilmont 80:8e73be2a2ac1 4101 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
emilmont 80:8e73be2a2ac1 4102 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
emilmont 80:8e73be2a2ac1 4103 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4104 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4105
emilmont 80:8e73be2a2ac1 4106 /* Bit 13 : Include CH13 in channel group. */
emilmont 80:8e73be2a2ac1 4107 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
emilmont 80:8e73be2a2ac1 4108 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
emilmont 80:8e73be2a2ac1 4109 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4110 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4111
emilmont 80:8e73be2a2ac1 4112 /* Bit 12 : Include CH12 in channel group. */
emilmont 80:8e73be2a2ac1 4113 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
emilmont 80:8e73be2a2ac1 4114 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
emilmont 80:8e73be2a2ac1 4115 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4116 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4117
emilmont 80:8e73be2a2ac1 4118 /* Bit 11 : Include CH11 in channel group. */
emilmont 80:8e73be2a2ac1 4119 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
emilmont 80:8e73be2a2ac1 4120 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
emilmont 80:8e73be2a2ac1 4121 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4122 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4123
emilmont 80:8e73be2a2ac1 4124 /* Bit 10 : Include CH10 in channel group. */
emilmont 80:8e73be2a2ac1 4125 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
emilmont 80:8e73be2a2ac1 4126 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
emilmont 80:8e73be2a2ac1 4127 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4128 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4129
emilmont 80:8e73be2a2ac1 4130 /* Bit 9 : Include CH9 in channel group. */
emilmont 80:8e73be2a2ac1 4131 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
emilmont 80:8e73be2a2ac1 4132 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
emilmont 80:8e73be2a2ac1 4133 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4134 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4135
emilmont 80:8e73be2a2ac1 4136 /* Bit 8 : Include CH8 in channel group. */
emilmont 80:8e73be2a2ac1 4137 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
emilmont 80:8e73be2a2ac1 4138 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
emilmont 80:8e73be2a2ac1 4139 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4140 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4141
emilmont 80:8e73be2a2ac1 4142 /* Bit 7 : Include CH7 in channel group. */
emilmont 80:8e73be2a2ac1 4143 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
emilmont 80:8e73be2a2ac1 4144 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
emilmont 80:8e73be2a2ac1 4145 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4146 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4147
emilmont 80:8e73be2a2ac1 4148 /* Bit 6 : Include CH6 in channel group. */
emilmont 80:8e73be2a2ac1 4149 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
emilmont 80:8e73be2a2ac1 4150 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
emilmont 80:8e73be2a2ac1 4151 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4152 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4153
emilmont 80:8e73be2a2ac1 4154 /* Bit 5 : Include CH5 in channel group. */
emilmont 80:8e73be2a2ac1 4155 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
emilmont 80:8e73be2a2ac1 4156 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
emilmont 80:8e73be2a2ac1 4157 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4158 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4159
emilmont 80:8e73be2a2ac1 4160 /* Bit 4 : Include CH4 in channel group. */
emilmont 80:8e73be2a2ac1 4161 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
emilmont 80:8e73be2a2ac1 4162 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
emilmont 80:8e73be2a2ac1 4163 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4164 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4165
emilmont 80:8e73be2a2ac1 4166 /* Bit 3 : Include CH3 in channel group. */
emilmont 80:8e73be2a2ac1 4167 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
emilmont 80:8e73be2a2ac1 4168 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
emilmont 80:8e73be2a2ac1 4169 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4170 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4171
emilmont 80:8e73be2a2ac1 4172 /* Bit 2 : Include CH2 in channel group. */
emilmont 80:8e73be2a2ac1 4173 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
emilmont 80:8e73be2a2ac1 4174 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
emilmont 80:8e73be2a2ac1 4175 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4176 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4177
emilmont 80:8e73be2a2ac1 4178 /* Bit 1 : Include CH1 in channel group. */
emilmont 80:8e73be2a2ac1 4179 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
emilmont 80:8e73be2a2ac1 4180 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
emilmont 80:8e73be2a2ac1 4181 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4182 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4183
emilmont 80:8e73be2a2ac1 4184 /* Bit 0 : Include CH0 in channel group. */
emilmont 80:8e73be2a2ac1 4185 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
emilmont 80:8e73be2a2ac1 4186 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
emilmont 80:8e73be2a2ac1 4187 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
emilmont 80:8e73be2a2ac1 4188 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
emilmont 80:8e73be2a2ac1 4189
emilmont 80:8e73be2a2ac1 4190
emilmont 80:8e73be2a2ac1 4191 /* Peripheral: PU */
emilmont 80:8e73be2a2ac1 4192 /* Description: Patch unit. */
emilmont 80:8e73be2a2ac1 4193
emilmont 80:8e73be2a2ac1 4194 /* Register: PU_PATCHADDR */
emilmont 80:8e73be2a2ac1 4195 /* Description: Relative address of patch instructions. */
emilmont 80:8e73be2a2ac1 4196
emilmont 80:8e73be2a2ac1 4197 /* Bits 24..0 : Relative address of patch instructions. */
emilmont 80:8e73be2a2ac1 4198 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
emilmont 80:8e73be2a2ac1 4199 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
emilmont 80:8e73be2a2ac1 4200
emilmont 80:8e73be2a2ac1 4201 /* Register: PU_PATCHEN */
emilmont 80:8e73be2a2ac1 4202 /* Description: Patch enable register. */
emilmont 80:8e73be2a2ac1 4203
emilmont 80:8e73be2a2ac1 4204 /* Bit 7 : Patch 7 enabled. */
emilmont 80:8e73be2a2ac1 4205 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
emilmont 80:8e73be2a2ac1 4206 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
emilmont 80:8e73be2a2ac1 4207 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4208 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4209
emilmont 80:8e73be2a2ac1 4210 /* Bit 6 : Patch 6 enabled. */
emilmont 80:8e73be2a2ac1 4211 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
emilmont 80:8e73be2a2ac1 4212 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
emilmont 80:8e73be2a2ac1 4213 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4214 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4215
emilmont 80:8e73be2a2ac1 4216 /* Bit 5 : Patch 5 enabled. */
emilmont 80:8e73be2a2ac1 4217 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
emilmont 80:8e73be2a2ac1 4218 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
emilmont 80:8e73be2a2ac1 4219 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4220 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4221
emilmont 80:8e73be2a2ac1 4222 /* Bit 4 : Patch 4 enabled. */
emilmont 80:8e73be2a2ac1 4223 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
emilmont 80:8e73be2a2ac1 4224 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
emilmont 80:8e73be2a2ac1 4225 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4226 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4227
emilmont 80:8e73be2a2ac1 4228 /* Bit 3 : Patch 3 enabled. */
emilmont 80:8e73be2a2ac1 4229 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
emilmont 80:8e73be2a2ac1 4230 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
emilmont 80:8e73be2a2ac1 4231 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4232 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4233
emilmont 80:8e73be2a2ac1 4234 /* Bit 2 : Patch 2 enabled. */
emilmont 80:8e73be2a2ac1 4235 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
emilmont 80:8e73be2a2ac1 4236 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
emilmont 80:8e73be2a2ac1 4237 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4238 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4239
emilmont 80:8e73be2a2ac1 4240 /* Bit 1 : Patch 1 enabled. */
emilmont 80:8e73be2a2ac1 4241 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
emilmont 80:8e73be2a2ac1 4242 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
emilmont 80:8e73be2a2ac1 4243 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4244 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4245
emilmont 80:8e73be2a2ac1 4246 /* Bit 0 : Patch 0 enabled. */
emilmont 80:8e73be2a2ac1 4247 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
emilmont 80:8e73be2a2ac1 4248 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
emilmont 80:8e73be2a2ac1 4249 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4250 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4251
emilmont 80:8e73be2a2ac1 4252 /* Register: PU_PATCHENSET */
emilmont 80:8e73be2a2ac1 4253 /* Description: Patch enable register. */
emilmont 80:8e73be2a2ac1 4254
emilmont 80:8e73be2a2ac1 4255 /* Bit 7 : Patch 7 enabled. */
emilmont 80:8e73be2a2ac1 4256 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
emilmont 80:8e73be2a2ac1 4257 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
emilmont 80:8e73be2a2ac1 4258 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4259 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4260 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
emilmont 80:8e73be2a2ac1 4261
emilmont 80:8e73be2a2ac1 4262 /* Bit 6 : Patch 6 enabled. */
emilmont 80:8e73be2a2ac1 4263 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
emilmont 80:8e73be2a2ac1 4264 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
emilmont 80:8e73be2a2ac1 4265 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4266 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4267 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
emilmont 80:8e73be2a2ac1 4268
emilmont 80:8e73be2a2ac1 4269 /* Bit 5 : Patch 5 enabled. */
emilmont 80:8e73be2a2ac1 4270 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
emilmont 80:8e73be2a2ac1 4271 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
emilmont 80:8e73be2a2ac1 4272 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4273 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4274 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
emilmont 80:8e73be2a2ac1 4275
emilmont 80:8e73be2a2ac1 4276 /* Bit 4 : Patch 4 enabled. */
emilmont 80:8e73be2a2ac1 4277 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
emilmont 80:8e73be2a2ac1 4278 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
emilmont 80:8e73be2a2ac1 4279 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4280 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4281 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
emilmont 80:8e73be2a2ac1 4282
emilmont 80:8e73be2a2ac1 4283 /* Bit 3 : Patch 3 enabled. */
emilmont 80:8e73be2a2ac1 4284 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
emilmont 80:8e73be2a2ac1 4285 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
emilmont 80:8e73be2a2ac1 4286 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4287 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4288 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
emilmont 80:8e73be2a2ac1 4289
emilmont 80:8e73be2a2ac1 4290 /* Bit 2 : Patch 2 enabled. */
emilmont 80:8e73be2a2ac1 4291 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
emilmont 80:8e73be2a2ac1 4292 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
emilmont 80:8e73be2a2ac1 4293 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4294 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4295 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
emilmont 80:8e73be2a2ac1 4296
emilmont 80:8e73be2a2ac1 4297 /* Bit 1 : Patch 1 enabled. */
emilmont 80:8e73be2a2ac1 4298 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
emilmont 80:8e73be2a2ac1 4299 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
emilmont 80:8e73be2a2ac1 4300 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4301 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4302 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
emilmont 80:8e73be2a2ac1 4303
emilmont 80:8e73be2a2ac1 4304 /* Bit 0 : Patch 0 enabled. */
emilmont 80:8e73be2a2ac1 4305 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
emilmont 80:8e73be2a2ac1 4306 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
emilmont 80:8e73be2a2ac1 4307 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4308 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4309 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
emilmont 80:8e73be2a2ac1 4310
emilmont 80:8e73be2a2ac1 4311 /* Register: PU_PATCHENCLR */
emilmont 80:8e73be2a2ac1 4312 /* Description: Patch disable register. */
emilmont 80:8e73be2a2ac1 4313
emilmont 80:8e73be2a2ac1 4314 /* Bit 7 : Patch 7 enabled. */
emilmont 80:8e73be2a2ac1 4315 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
emilmont 80:8e73be2a2ac1 4316 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
emilmont 80:8e73be2a2ac1 4317 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4318 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4319 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
emilmont 80:8e73be2a2ac1 4320
emilmont 80:8e73be2a2ac1 4321 /* Bit 6 : Patch 6 enabled. */
emilmont 80:8e73be2a2ac1 4322 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
emilmont 80:8e73be2a2ac1 4323 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
emilmont 80:8e73be2a2ac1 4324 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4325 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4326 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
emilmont 80:8e73be2a2ac1 4327
emilmont 80:8e73be2a2ac1 4328 /* Bit 5 : Patch 5 enabled. */
emilmont 80:8e73be2a2ac1 4329 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
emilmont 80:8e73be2a2ac1 4330 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
emilmont 80:8e73be2a2ac1 4331 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4332 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4333 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
emilmont 80:8e73be2a2ac1 4334
emilmont 80:8e73be2a2ac1 4335 /* Bit 4 : Patch 4 enabled. */
emilmont 80:8e73be2a2ac1 4336 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
emilmont 80:8e73be2a2ac1 4337 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
emilmont 80:8e73be2a2ac1 4338 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4339 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4340 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
emilmont 80:8e73be2a2ac1 4341
emilmont 80:8e73be2a2ac1 4342 /* Bit 3 : Patch 3 enabled. */
emilmont 80:8e73be2a2ac1 4343 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
emilmont 80:8e73be2a2ac1 4344 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
emilmont 80:8e73be2a2ac1 4345 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4346 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4347 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
emilmont 80:8e73be2a2ac1 4348
emilmont 80:8e73be2a2ac1 4349 /* Bit 2 : Patch 2 enabled. */
emilmont 80:8e73be2a2ac1 4350 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
emilmont 80:8e73be2a2ac1 4351 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
emilmont 80:8e73be2a2ac1 4352 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4353 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4354 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
emilmont 80:8e73be2a2ac1 4355
emilmont 80:8e73be2a2ac1 4356 /* Bit 1 : Patch 1 enabled. */
emilmont 80:8e73be2a2ac1 4357 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
emilmont 80:8e73be2a2ac1 4358 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
emilmont 80:8e73be2a2ac1 4359 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4360 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4361 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
emilmont 80:8e73be2a2ac1 4362
emilmont 80:8e73be2a2ac1 4363 /* Bit 0 : Patch 0 enabled. */
emilmont 80:8e73be2a2ac1 4364 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
emilmont 80:8e73be2a2ac1 4365 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
emilmont 80:8e73be2a2ac1 4366 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
emilmont 80:8e73be2a2ac1 4367 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
emilmont 80:8e73be2a2ac1 4368 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
emilmont 80:8e73be2a2ac1 4369
emilmont 80:8e73be2a2ac1 4370
emilmont 80:8e73be2a2ac1 4371 /* Peripheral: QDEC */
emilmont 80:8e73be2a2ac1 4372 /* Description: Rotary decoder. */
emilmont 80:8e73be2a2ac1 4373
emilmont 80:8e73be2a2ac1 4374 /* Register: QDEC_SHORTS */
emilmont 80:8e73be2a2ac1 4375 /* Description: Shortcut for the QDEC. */
emilmont 80:8e73be2a2ac1 4376
emilmont 80:8e73be2a2ac1 4377 /* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */
emilmont 80:8e73be2a2ac1 4378 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
emilmont 80:8e73be2a2ac1 4379 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
emilmont 80:8e73be2a2ac1 4380 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4381 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4382
emilmont 80:8e73be2a2ac1 4383 /* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */
emilmont 80:8e73be2a2ac1 4384 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
emilmont 80:8e73be2a2ac1 4385 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
emilmont 80:8e73be2a2ac1 4386 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4387 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4388
emilmont 80:8e73be2a2ac1 4389 /* Register: QDEC_INTENSET */
emilmont 80:8e73be2a2ac1 4390 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 4391
emilmont 80:8e73be2a2ac1 4392 /* Bit 2 : Enable interrupt on ACCOF event. */
emilmont 80:8e73be2a2ac1 4393 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
emilmont 80:8e73be2a2ac1 4394 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
emilmont 80:8e73be2a2ac1 4395 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4396 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4397 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4398
emilmont 80:8e73be2a2ac1 4399 /* Bit 1 : Enable interrupt on REPORTRDY event. */
emilmont 80:8e73be2a2ac1 4400 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
emilmont 80:8e73be2a2ac1 4401 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
emilmont 80:8e73be2a2ac1 4402 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4403 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4404 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4405
emilmont 80:8e73be2a2ac1 4406 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
emilmont 80:8e73be2a2ac1 4407 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
emilmont 80:8e73be2a2ac1 4408 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
emilmont 80:8e73be2a2ac1 4409 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4410 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4411 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4412
emilmont 80:8e73be2a2ac1 4413 /* Register: QDEC_INTENCLR */
emilmont 80:8e73be2a2ac1 4414 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 4415
emilmont 80:8e73be2a2ac1 4416 /* Bit 2 : Disable interrupt on ACCOF event. */
emilmont 80:8e73be2a2ac1 4417 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
emilmont 80:8e73be2a2ac1 4418 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
emilmont 80:8e73be2a2ac1 4419 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4420 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4421 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4422
emilmont 80:8e73be2a2ac1 4423 /* Bit 1 : Disable interrupt on REPORTRDY event. */
emilmont 80:8e73be2a2ac1 4424 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
emilmont 80:8e73be2a2ac1 4425 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
emilmont 80:8e73be2a2ac1 4426 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4427 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4428 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4429
emilmont 80:8e73be2a2ac1 4430 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
emilmont 80:8e73be2a2ac1 4431 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
emilmont 80:8e73be2a2ac1 4432 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
emilmont 80:8e73be2a2ac1 4433 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4434 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4435 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4436
emilmont 80:8e73be2a2ac1 4437 /* Register: QDEC_ENABLE */
emilmont 80:8e73be2a2ac1 4438 /* Description: Enable the QDEC. */
emilmont 80:8e73be2a2ac1 4439
emilmont 80:8e73be2a2ac1 4440 /* Bit 0 : Enable or disable QDEC. */
emilmont 80:8e73be2a2ac1 4441 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 4442 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 4443 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
emilmont 80:8e73be2a2ac1 4444 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
emilmont 80:8e73be2a2ac1 4445
emilmont 80:8e73be2a2ac1 4446 /* Register: QDEC_LEDPOL */
emilmont 80:8e73be2a2ac1 4447 /* Description: LED output pin polarity. */
emilmont 80:8e73be2a2ac1 4448
emilmont 80:8e73be2a2ac1 4449 /* Bit 0 : LED output pin polarity. */
emilmont 80:8e73be2a2ac1 4450 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
emilmont 80:8e73be2a2ac1 4451 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
emilmont 80:8e73be2a2ac1 4452 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
emilmont 80:8e73be2a2ac1 4453 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
emilmont 80:8e73be2a2ac1 4454
emilmont 80:8e73be2a2ac1 4455 /* Register: QDEC_SAMPLEPER */
emilmont 80:8e73be2a2ac1 4456 /* Description: Sample period. */
emilmont 80:8e73be2a2ac1 4457
emilmont 80:8e73be2a2ac1 4458 /* Bits 2..0 : Sample period. */
emilmont 80:8e73be2a2ac1 4459 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
emilmont 80:8e73be2a2ac1 4460 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
emilmont 80:8e73be2a2ac1 4461 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
emilmont 80:8e73be2a2ac1 4462 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
emilmont 80:8e73be2a2ac1 4463 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
emilmont 80:8e73be2a2ac1 4464 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
emilmont 80:8e73be2a2ac1 4465 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
emilmont 80:8e73be2a2ac1 4466 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
emilmont 80:8e73be2a2ac1 4467 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
emilmont 80:8e73be2a2ac1 4468 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
emilmont 80:8e73be2a2ac1 4469
emilmont 80:8e73be2a2ac1 4470 /* Register: QDEC_SAMPLE */
emilmont 80:8e73be2a2ac1 4471 /* Description: Motion sample value. */
emilmont 80:8e73be2a2ac1 4472
emilmont 80:8e73be2a2ac1 4473 /* Bits 31..0 : Last sample taken in compliment to 2. */
emilmont 80:8e73be2a2ac1 4474 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
emilmont 80:8e73be2a2ac1 4475 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
emilmont 80:8e73be2a2ac1 4476
emilmont 80:8e73be2a2ac1 4477 /* Register: QDEC_REPORTPER */
emilmont 80:8e73be2a2ac1 4478 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
emilmont 80:8e73be2a2ac1 4479
emilmont 80:8e73be2a2ac1 4480 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
emilmont 80:8e73be2a2ac1 4481 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
emilmont 80:8e73be2a2ac1 4482 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
emilmont 80:8e73be2a2ac1 4483 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
emilmont 80:8e73be2a2ac1 4484 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
emilmont 80:8e73be2a2ac1 4485 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
emilmont 80:8e73be2a2ac1 4486 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
emilmont 80:8e73be2a2ac1 4487 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
emilmont 80:8e73be2a2ac1 4488 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
emilmont 80:8e73be2a2ac1 4489 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
emilmont 80:8e73be2a2ac1 4490 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
emilmont 80:8e73be2a2ac1 4491
emilmont 80:8e73be2a2ac1 4492 /* Register: QDEC_DBFEN */
emilmont 80:8e73be2a2ac1 4493 /* Description: Enable debouncer input filters. */
emilmont 80:8e73be2a2ac1 4494
emilmont 80:8e73be2a2ac1 4495 /* Bit 0 : Enable debounce input filters. */
emilmont 80:8e73be2a2ac1 4496 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
emilmont 80:8e73be2a2ac1 4497 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
emilmont 80:8e73be2a2ac1 4498 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
emilmont 80:8e73be2a2ac1 4499 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
emilmont 80:8e73be2a2ac1 4500
emilmont 80:8e73be2a2ac1 4501 /* Register: QDEC_LEDPRE */
emilmont 80:8e73be2a2ac1 4502 /* Description: Time LED is switched ON before the sample. */
emilmont 80:8e73be2a2ac1 4503
emilmont 80:8e73be2a2ac1 4504 /* Bits 7..0 : Period in us the LED in switched on prior to sampling. */
emilmont 80:8e73be2a2ac1 4505 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
emilmont 80:8e73be2a2ac1 4506 #define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
emilmont 80:8e73be2a2ac1 4507
emilmont 80:8e73be2a2ac1 4508 /* Register: QDEC_ACCDBL */
emilmont 80:8e73be2a2ac1 4509 /* Description: Accumulated double (error) transitions register. */
emilmont 80:8e73be2a2ac1 4510
emilmont 80:8e73be2a2ac1 4511 /* Bits 3..0 : Accumulated double (error) transitions. */
emilmont 80:8e73be2a2ac1 4512 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
emilmont 80:8e73be2a2ac1 4513 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
emilmont 80:8e73be2a2ac1 4514
emilmont 80:8e73be2a2ac1 4515 /* Register: QDEC_ACCDBLREAD */
emilmont 80:8e73be2a2ac1 4516 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
emilmont 80:8e73be2a2ac1 4517
emilmont 80:8e73be2a2ac1 4518 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
emilmont 80:8e73be2a2ac1 4519 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
emilmont 80:8e73be2a2ac1 4520 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
emilmont 80:8e73be2a2ac1 4521
emilmont 80:8e73be2a2ac1 4522 /* Register: QDEC_POWER */
emilmont 80:8e73be2a2ac1 4523 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 4524
emilmont 80:8e73be2a2ac1 4525 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 4526 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 4527 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 4528 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 4529 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 4530
emilmont 80:8e73be2a2ac1 4531
emilmont 80:8e73be2a2ac1 4532 /* Peripheral: RADIO */
emilmont 80:8e73be2a2ac1 4533 /* Description: The radio. */
emilmont 80:8e73be2a2ac1 4534
emilmont 80:8e73be2a2ac1 4535 /* Register: RADIO_SHORTS */
emilmont 80:8e73be2a2ac1 4536 /* Description: Shortcut for the radio. */
emilmont 80:8e73be2a2ac1 4537
emilmont 80:8e73be2a2ac1 4538 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
emilmont 80:8e73be2a2ac1 4539 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
emilmont 80:8e73be2a2ac1 4540 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
emilmont 80:8e73be2a2ac1 4541 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4542 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4543
emilmont 80:8e73be2a2ac1 4544 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
emilmont 80:8e73be2a2ac1 4545 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
emilmont 80:8e73be2a2ac1 4546 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
emilmont 80:8e73be2a2ac1 4547 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4548 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4549
emilmont 80:8e73be2a2ac1 4550 /* Bit 5 : Shortcut between END event and START task. */
emilmont 80:8e73be2a2ac1 4551 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
emilmont 80:8e73be2a2ac1 4552 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
emilmont 80:8e73be2a2ac1 4553 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4554 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4555
emilmont 80:8e73be2a2ac1 4556 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
emilmont 80:8e73be2a2ac1 4557 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
emilmont 80:8e73be2a2ac1 4558 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
emilmont 80:8e73be2a2ac1 4559 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4560 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4561
emilmont 80:8e73be2a2ac1 4562 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
emilmont 80:8e73be2a2ac1 4563 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
emilmont 80:8e73be2a2ac1 4564 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
emilmont 80:8e73be2a2ac1 4565 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4566 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4567
emilmont 80:8e73be2a2ac1 4568 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
emilmont 80:8e73be2a2ac1 4569 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
emilmont 80:8e73be2a2ac1 4570 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
emilmont 80:8e73be2a2ac1 4571 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4572 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4573
emilmont 80:8e73be2a2ac1 4574 /* Bit 1 : Shortcut between END event and DISABLE task. */
emilmont 80:8e73be2a2ac1 4575 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
emilmont 80:8e73be2a2ac1 4576 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
emilmont 80:8e73be2a2ac1 4577 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4578 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4579
emilmont 80:8e73be2a2ac1 4580 /* Bit 0 : Shortcut between READY event and START task. */
emilmont 80:8e73be2a2ac1 4581 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
emilmont 80:8e73be2a2ac1 4582 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
emilmont 80:8e73be2a2ac1 4583 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 4584 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 4585
emilmont 80:8e73be2a2ac1 4586 /* Register: RADIO_INTENSET */
emilmont 80:8e73be2a2ac1 4587 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 4588
emilmont 80:8e73be2a2ac1 4589 /* Bit 10 : Enable interrupt on BCMATCH event. */
emilmont 80:8e73be2a2ac1 4590 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
emilmont 80:8e73be2a2ac1 4591 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
emilmont 80:8e73be2a2ac1 4592 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4593 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4594 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4595
emilmont 80:8e73be2a2ac1 4596 /* Bit 7 : Enable interrupt on RSSIEND event. */
emilmont 80:8e73be2a2ac1 4597 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
emilmont 80:8e73be2a2ac1 4598 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
emilmont 80:8e73be2a2ac1 4599 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4600 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4601 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4602
emilmont 80:8e73be2a2ac1 4603 /* Bit 6 : Enable interrupt on DEVMISS event. */
emilmont 80:8e73be2a2ac1 4604 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
emilmont 80:8e73be2a2ac1 4605 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
emilmont 80:8e73be2a2ac1 4606 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4607 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4608 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4609
emilmont 80:8e73be2a2ac1 4610 /* Bit 5 : Enable interrupt on DEVMATCH event. */
emilmont 80:8e73be2a2ac1 4611 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
emilmont 80:8e73be2a2ac1 4612 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
emilmont 80:8e73be2a2ac1 4613 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4614 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4615 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4616
emilmont 80:8e73be2a2ac1 4617 /* Bit 4 : Enable interrupt on DISABLED event. */
emilmont 80:8e73be2a2ac1 4618 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
emilmont 80:8e73be2a2ac1 4619 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
emilmont 80:8e73be2a2ac1 4620 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4621 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4622 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4623
emilmont 80:8e73be2a2ac1 4624 /* Bit 3 : Enable interrupt on END event. */
emilmont 80:8e73be2a2ac1 4625 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
emilmont 80:8e73be2a2ac1 4626 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
emilmont 80:8e73be2a2ac1 4627 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4628 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4629 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4630
emilmont 80:8e73be2a2ac1 4631 /* Bit 2 : Enable interrupt on PAYLOAD event. */
emilmont 80:8e73be2a2ac1 4632 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
emilmont 80:8e73be2a2ac1 4633 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
emilmont 80:8e73be2a2ac1 4634 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4635 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4636 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4637
emilmont 80:8e73be2a2ac1 4638 /* Bit 1 : Enable interrupt on ADDRESS event. */
emilmont 80:8e73be2a2ac1 4639 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
emilmont 80:8e73be2a2ac1 4640 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
emilmont 80:8e73be2a2ac1 4641 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4642 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4643 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4644
emilmont 80:8e73be2a2ac1 4645 /* Bit 0 : Enable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 4646 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 4647 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 4648 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4649 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4650 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 4651
emilmont 80:8e73be2a2ac1 4652 /* Register: RADIO_INTENCLR */
emilmont 80:8e73be2a2ac1 4653 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 4654
emilmont 80:8e73be2a2ac1 4655 /* Bit 10 : Disable interrupt on BCMATCH event. */
emilmont 80:8e73be2a2ac1 4656 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
emilmont 80:8e73be2a2ac1 4657 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
emilmont 80:8e73be2a2ac1 4658 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4659 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4660 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4661
emilmont 80:8e73be2a2ac1 4662 /* Bit 7 : Disable interrupt on RSSIEND event. */
emilmont 80:8e73be2a2ac1 4663 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
emilmont 80:8e73be2a2ac1 4664 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
emilmont 80:8e73be2a2ac1 4665 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4666 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4667 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4668
emilmont 80:8e73be2a2ac1 4669 /* Bit 6 : Disable interrupt on DEVMISS event. */
emilmont 80:8e73be2a2ac1 4670 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
emilmont 80:8e73be2a2ac1 4671 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
emilmont 80:8e73be2a2ac1 4672 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4673 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4674 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4675
emilmont 80:8e73be2a2ac1 4676 /* Bit 5 : Disable interrupt on DEVMATCH event. */
emilmont 80:8e73be2a2ac1 4677 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
emilmont 80:8e73be2a2ac1 4678 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
emilmont 80:8e73be2a2ac1 4679 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4680 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4681 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4682
emilmont 80:8e73be2a2ac1 4683 /* Bit 4 : Disable interrupt on DISABLED event. */
emilmont 80:8e73be2a2ac1 4684 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
emilmont 80:8e73be2a2ac1 4685 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
emilmont 80:8e73be2a2ac1 4686 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4687 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4688 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4689
emilmont 80:8e73be2a2ac1 4690 /* Bit 3 : Disable interrupt on END event. */
emilmont 80:8e73be2a2ac1 4691 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
emilmont 80:8e73be2a2ac1 4692 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
emilmont 80:8e73be2a2ac1 4693 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4694 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4695 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4696
emilmont 80:8e73be2a2ac1 4697 /* Bit 2 : Disable interrupt on PAYLOAD event. */
emilmont 80:8e73be2a2ac1 4698 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
emilmont 80:8e73be2a2ac1 4699 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
emilmont 80:8e73be2a2ac1 4700 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4701 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4702 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4703
emilmont 80:8e73be2a2ac1 4704 /* Bit 1 : Disable interrupt on ADDRESS event. */
emilmont 80:8e73be2a2ac1 4705 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
emilmont 80:8e73be2a2ac1 4706 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
emilmont 80:8e73be2a2ac1 4707 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4708 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4709 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4710
emilmont 80:8e73be2a2ac1 4711 /* Bit 0 : Disable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 4712 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 4713 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 4714 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 4715 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 4716 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 4717
emilmont 80:8e73be2a2ac1 4718 /* Register: RADIO_CRCSTATUS */
emilmont 80:8e73be2a2ac1 4719 /* Description: CRC status of received packet. */
emilmont 80:8e73be2a2ac1 4720
emilmont 80:8e73be2a2ac1 4721 /* Bit 0 : CRC status of received packet. */
emilmont 80:8e73be2a2ac1 4722 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
emilmont 80:8e73be2a2ac1 4723 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
emilmont 80:8e73be2a2ac1 4724 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
emilmont 80:8e73be2a2ac1 4725 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
emilmont 80:8e73be2a2ac1 4726
emilmont 80:8e73be2a2ac1 4727 /* Register: RADIO_RXMATCH */
emilmont 80:8e73be2a2ac1 4728 /* Description: Received address. */
emilmont 80:8e73be2a2ac1 4729
emilmont 80:8e73be2a2ac1 4730 /* Bits 2..0 : Logical address in which previous packet was received. */
emilmont 80:8e73be2a2ac1 4731 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
emilmont 80:8e73be2a2ac1 4732 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
emilmont 80:8e73be2a2ac1 4733
emilmont 80:8e73be2a2ac1 4734 /* Register: RADIO_RXCRC */
emilmont 80:8e73be2a2ac1 4735 /* Description: Received CRC. */
emilmont 80:8e73be2a2ac1 4736
emilmont 80:8e73be2a2ac1 4737 /* Bits 23..0 : CRC field of previously received packet. */
emilmont 80:8e73be2a2ac1 4738 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
emilmont 80:8e73be2a2ac1 4739 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
emilmont 80:8e73be2a2ac1 4740
emilmont 80:8e73be2a2ac1 4741 /* Register: RADIO_DAI */
emilmont 80:8e73be2a2ac1 4742 /* Description: Device address match index. */
emilmont 80:8e73be2a2ac1 4743
emilmont 80:8e73be2a2ac1 4744 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */
emilmont 80:8e73be2a2ac1 4745 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
emilmont 80:8e73be2a2ac1 4746 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
emilmont 80:8e73be2a2ac1 4747
emilmont 80:8e73be2a2ac1 4748 /* Register: RADIO_FREQUENCY */
emilmont 80:8e73be2a2ac1 4749 /* Description: Frequency. */
emilmont 80:8e73be2a2ac1 4750
emilmont 80:8e73be2a2ac1 4751 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
emilmont 80:8e73be2a2ac1 4752 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
emilmont 80:8e73be2a2ac1 4753 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
emilmont 80:8e73be2a2ac1 4754
emilmont 80:8e73be2a2ac1 4755 /* Register: RADIO_TXPOWER */
emilmont 80:8e73be2a2ac1 4756 /* Description: Output power. */
emilmont 80:8e73be2a2ac1 4757
emilmont 80:8e73be2a2ac1 4758 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
emilmont 80:8e73be2a2ac1 4759 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
emilmont 80:8e73be2a2ac1 4760 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
emilmont 80:8e73be2a2ac1 4761 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
emilmont 80:8e73be2a2ac1 4762 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
emilmont 80:8e73be2a2ac1 4763 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
emilmont 80:8e73be2a2ac1 4764 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
emilmont 80:8e73be2a2ac1 4765 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
emilmont 80:8e73be2a2ac1 4766 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
emilmont 80:8e73be2a2ac1 4767 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
emilmont 80:8e73be2a2ac1 4768 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
emilmont 80:8e73be2a2ac1 4769
emilmont 80:8e73be2a2ac1 4770 /* Register: RADIO_MODE */
emilmont 80:8e73be2a2ac1 4771 /* Description: Data rate and modulation. */
emilmont 80:8e73be2a2ac1 4772
emilmont 80:8e73be2a2ac1 4773 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
emilmont 80:8e73be2a2ac1 4774 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
emilmont 80:8e73be2a2ac1 4775 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
emilmont 80:8e73be2a2ac1 4776 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
emilmont 80:8e73be2a2ac1 4777 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
emilmont 80:8e73be2a2ac1 4778 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
emilmont 80:8e73be2a2ac1 4779 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
emilmont 80:8e73be2a2ac1 4780
emilmont 80:8e73be2a2ac1 4781 /* Register: RADIO_PCNF0 */
emilmont 80:8e73be2a2ac1 4782 /* Description: Packet configuration 0. */
emilmont 80:8e73be2a2ac1 4783
emilmont 80:8e73be2a2ac1 4784 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4785 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
emilmont 80:8e73be2a2ac1 4786 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
emilmont 80:8e73be2a2ac1 4787
emilmont 80:8e73be2a2ac1 4788 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4789 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
emilmont 80:8e73be2a2ac1 4790 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
emilmont 80:8e73be2a2ac1 4791
emilmont 80:8e73be2a2ac1 4792 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4793 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
emilmont 80:8e73be2a2ac1 4794 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
emilmont 80:8e73be2a2ac1 4795
emilmont 80:8e73be2a2ac1 4796 /* Register: RADIO_PCNF1 */
emilmont 80:8e73be2a2ac1 4797 /* Description: Packet configuration 1. */
emilmont 80:8e73be2a2ac1 4798
emilmont 80:8e73be2a2ac1 4799 /* Bit 25 : Packet whitening enable. */
emilmont 80:8e73be2a2ac1 4800 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
emilmont 80:8e73be2a2ac1 4801 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
emilmont 80:8e73be2a2ac1 4802 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
emilmont 80:8e73be2a2ac1 4803 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
emilmont 80:8e73be2a2ac1 4804
emilmont 80:8e73be2a2ac1 4805 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4806 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
emilmont 80:8e73be2a2ac1 4807 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
emilmont 80:8e73be2a2ac1 4808 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
emilmont 80:8e73be2a2ac1 4809 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
emilmont 80:8e73be2a2ac1 4810
emilmont 80:8e73be2a2ac1 4811 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4812 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
emilmont 80:8e73be2a2ac1 4813 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
emilmont 80:8e73be2a2ac1 4814
emilmont 80:8e73be2a2ac1 4815 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4816 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
emilmont 80:8e73be2a2ac1 4817 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
emilmont 80:8e73be2a2ac1 4818
emilmont 80:8e73be2a2ac1 4819 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
emilmont 80:8e73be2a2ac1 4820 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
emilmont 80:8e73be2a2ac1 4821 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
emilmont 80:8e73be2a2ac1 4822
emilmont 80:8e73be2a2ac1 4823 /* Register: RADIO_PREFIX0 */
emilmont 80:8e73be2a2ac1 4824 /* Description: Prefixes bytes for logical addresses 0 to 3. */
emilmont 80:8e73be2a2ac1 4825
emilmont 80:8e73be2a2ac1 4826 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4827 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
emilmont 80:8e73be2a2ac1 4828 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
emilmont 80:8e73be2a2ac1 4829
emilmont 80:8e73be2a2ac1 4830 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4831 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
emilmont 80:8e73be2a2ac1 4832 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
emilmont 80:8e73be2a2ac1 4833
emilmont 80:8e73be2a2ac1 4834 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4835 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
emilmont 80:8e73be2a2ac1 4836 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
emilmont 80:8e73be2a2ac1 4837
emilmont 80:8e73be2a2ac1 4838 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4839 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
emilmont 80:8e73be2a2ac1 4840 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
emilmont 80:8e73be2a2ac1 4841
emilmont 80:8e73be2a2ac1 4842 /* Register: RADIO_PREFIX1 */
emilmont 80:8e73be2a2ac1 4843 /* Description: Prefixes bytes for logical addresses 4 to 7. */
emilmont 80:8e73be2a2ac1 4844
emilmont 80:8e73be2a2ac1 4845 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4846 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
emilmont 80:8e73be2a2ac1 4847 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
emilmont 80:8e73be2a2ac1 4848
emilmont 80:8e73be2a2ac1 4849 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4850 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
emilmont 80:8e73be2a2ac1 4851 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
emilmont 80:8e73be2a2ac1 4852
emilmont 80:8e73be2a2ac1 4853 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4854 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
emilmont 80:8e73be2a2ac1 4855 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
emilmont 80:8e73be2a2ac1 4856
emilmont 80:8e73be2a2ac1 4857 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4858 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
emilmont 80:8e73be2a2ac1 4859 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
emilmont 80:8e73be2a2ac1 4860
emilmont 80:8e73be2a2ac1 4861 /* Register: RADIO_TXADDRESS */
emilmont 80:8e73be2a2ac1 4862 /* Description: Transmit address select. */
emilmont 80:8e73be2a2ac1 4863
emilmont 80:8e73be2a2ac1 4864 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4865 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
emilmont 80:8e73be2a2ac1 4866 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
emilmont 80:8e73be2a2ac1 4867
emilmont 80:8e73be2a2ac1 4868 /* Register: RADIO_RXADDRESSES */
emilmont 80:8e73be2a2ac1 4869 /* Description: Receive address select. */
emilmont 80:8e73be2a2ac1 4870
emilmont 80:8e73be2a2ac1 4871 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4872 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
emilmont 80:8e73be2a2ac1 4873 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
emilmont 80:8e73be2a2ac1 4874 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
emilmont 80:8e73be2a2ac1 4875 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
emilmont 80:8e73be2a2ac1 4876
emilmont 80:8e73be2a2ac1 4877 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4878 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
emilmont 80:8e73be2a2ac1 4879 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
emilmont 80:8e73be2a2ac1 4880 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
emilmont 80:8e73be2a2ac1 4881 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
emilmont 80:8e73be2a2ac1 4882
emilmont 80:8e73be2a2ac1 4883 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4884 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
emilmont 80:8e73be2a2ac1 4885 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
emilmont 80:8e73be2a2ac1 4886 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
emilmont 80:8e73be2a2ac1 4887 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
emilmont 80:8e73be2a2ac1 4888
emilmont 80:8e73be2a2ac1 4889 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4890 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
emilmont 80:8e73be2a2ac1 4891 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
emilmont 80:8e73be2a2ac1 4892 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
emilmont 80:8e73be2a2ac1 4893 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
emilmont 80:8e73be2a2ac1 4894
emilmont 80:8e73be2a2ac1 4895 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4896 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
emilmont 80:8e73be2a2ac1 4897 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
emilmont 80:8e73be2a2ac1 4898 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
emilmont 80:8e73be2a2ac1 4899 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
emilmont 80:8e73be2a2ac1 4900
emilmont 80:8e73be2a2ac1 4901 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4902 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
emilmont 80:8e73be2a2ac1 4903 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
emilmont 80:8e73be2a2ac1 4904 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
emilmont 80:8e73be2a2ac1 4905 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
emilmont 80:8e73be2a2ac1 4906
emilmont 80:8e73be2a2ac1 4907 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4908 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
emilmont 80:8e73be2a2ac1 4909 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
emilmont 80:8e73be2a2ac1 4910 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
emilmont 80:8e73be2a2ac1 4911 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
emilmont 80:8e73be2a2ac1 4912
emilmont 80:8e73be2a2ac1 4913 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4914 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
emilmont 80:8e73be2a2ac1 4915 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
emilmont 80:8e73be2a2ac1 4916 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
emilmont 80:8e73be2a2ac1 4917 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
emilmont 80:8e73be2a2ac1 4918
emilmont 80:8e73be2a2ac1 4919 /* Register: RADIO_CRCCNF */
emilmont 80:8e73be2a2ac1 4920 /* Description: CRC configuration. */
emilmont 80:8e73be2a2ac1 4921
emilmont 80:8e73be2a2ac1 4922 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4923 #define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /*!< Position of SKIP_ADDR field. */
emilmont 80:8e73be2a2ac1 4924 #define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /*!< Bit mask of SKIP_ADDR field. */
emilmont 80:8e73be2a2ac1 4925 #define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
emilmont 80:8e73be2a2ac1 4926 #define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
emilmont 80:8e73be2a2ac1 4927
emilmont 80:8e73be2a2ac1 4928 /* Bits 1..0 : CRC length. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4929 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
emilmont 80:8e73be2a2ac1 4930 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
emilmont 80:8e73be2a2ac1 4931 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
emilmont 80:8e73be2a2ac1 4932 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
emilmont 80:8e73be2a2ac1 4933 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
emilmont 80:8e73be2a2ac1 4934 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
emilmont 80:8e73be2a2ac1 4935
emilmont 80:8e73be2a2ac1 4936 /* Register: RADIO_CRCPOLY */
emilmont 80:8e73be2a2ac1 4937 /* Description: CRC polynomial. */
emilmont 80:8e73be2a2ac1 4938
emilmont 80:8e73be2a2ac1 4939 /* Bits 23..1 : CRC polynomial. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4940 #define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /*!< Position of CRCPOLY field. */
emilmont 80:8e73be2a2ac1 4941 #define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
emilmont 80:8e73be2a2ac1 4942
emilmont 80:8e73be2a2ac1 4943 /* Register: RADIO_CRCINIT */
emilmont 80:8e73be2a2ac1 4944 /* Description: CRC initial value. */
emilmont 80:8e73be2a2ac1 4945
emilmont 80:8e73be2a2ac1 4946 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
emilmont 80:8e73be2a2ac1 4947 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
emilmont 80:8e73be2a2ac1 4948 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
emilmont 80:8e73be2a2ac1 4949
emilmont 80:8e73be2a2ac1 4950 /* Register: RADIO_TEST */
emilmont 80:8e73be2a2ac1 4951 /* Description: Test features enable register. */
emilmont 80:8e73be2a2ac1 4952
emilmont 80:8e73be2a2ac1 4953 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
emilmont 80:8e73be2a2ac1 4954 #define RADIO_TEST_PLL_LOCK_Pos (1UL) /*!< Position of PLL_LOCK field. */
emilmont 80:8e73be2a2ac1 4955 #define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /*!< Bit mask of PLL_LOCK field. */
emilmont 80:8e73be2a2ac1 4956 #define RADIO_TEST_PLL_LOCK_Disabled (0UL) /*!< PLL lock disabled. */
emilmont 80:8e73be2a2ac1 4957 #define RADIO_TEST_PLL_LOCK_Enabled (1UL) /*!< PLL lock enabled. */
emilmont 80:8e73be2a2ac1 4958
emilmont 80:8e73be2a2ac1 4959 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
emilmont 80:8e73be2a2ac1 4960 #define RADIO_TEST_CONST_CARRIER_Pos (0UL) /*!< Position of CONST_CARRIER field. */
emilmont 80:8e73be2a2ac1 4961 #define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /*!< Bit mask of CONST_CARRIER field. */
emilmont 80:8e73be2a2ac1 4962 #define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
emilmont 80:8e73be2a2ac1 4963 #define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
emilmont 80:8e73be2a2ac1 4964
emilmont 80:8e73be2a2ac1 4965 /* Register: RADIO_TIFS */
emilmont 80:8e73be2a2ac1 4966 /* Description: Inter Frame Spacing in microseconds. */
emilmont 80:8e73be2a2ac1 4967
emilmont 80:8e73be2a2ac1 4968 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
emilmont 80:8e73be2a2ac1 4969 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
emilmont 80:8e73be2a2ac1 4970 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
emilmont 80:8e73be2a2ac1 4971
emilmont 80:8e73be2a2ac1 4972 /* Register: RADIO_RSSISAMPLE */
emilmont 80:8e73be2a2ac1 4973 /* Description: RSSI sample. */
emilmont 80:8e73be2a2ac1 4974
emilmont 80:8e73be2a2ac1 4975 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
emilmont 80:8e73be2a2ac1 4976 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
emilmont 80:8e73be2a2ac1 4977 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
emilmont 80:8e73be2a2ac1 4978
emilmont 80:8e73be2a2ac1 4979 /* Register: RADIO_STATE */
emilmont 80:8e73be2a2ac1 4980 /* Description: Current radio state. */
emilmont 80:8e73be2a2ac1 4981
emilmont 80:8e73be2a2ac1 4982 /* Bits 3..0 : Current radio state. */
emilmont 80:8e73be2a2ac1 4983 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
emilmont 80:8e73be2a2ac1 4984 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
emilmont 80:8e73be2a2ac1 4985 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
emilmont 80:8e73be2a2ac1 4986 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
emilmont 80:8e73be2a2ac1 4987 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
emilmont 80:8e73be2a2ac1 4988 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
emilmont 80:8e73be2a2ac1 4989 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
emilmont 80:8e73be2a2ac1 4990 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
emilmont 80:8e73be2a2ac1 4991 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
emilmont 80:8e73be2a2ac1 4992 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
emilmont 80:8e73be2a2ac1 4993 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
emilmont 80:8e73be2a2ac1 4994
emilmont 80:8e73be2a2ac1 4995 /* Register: RADIO_DATAWHITEIV */
emilmont 80:8e73be2a2ac1 4996 /* Description: Data whitening initial value. */
emilmont 80:8e73be2a2ac1 4997
emilmont 80:8e73be2a2ac1 4998 /* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
emilmont 80:8e73be2a2ac1 4999 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
emilmont 80:8e73be2a2ac1 5000 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
emilmont 80:8e73be2a2ac1 5001
emilmont 80:8e73be2a2ac1 5002 /* Register: RADIO_DAP */
emilmont 80:8e73be2a2ac1 5003 /* Description: Device address prefix. */
emilmont 80:8e73be2a2ac1 5004
emilmont 80:8e73be2a2ac1 5005 /* Bits 15..0 : Device address prefix. */
emilmont 80:8e73be2a2ac1 5006 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
emilmont 80:8e73be2a2ac1 5007 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
emilmont 80:8e73be2a2ac1 5008
emilmont 80:8e73be2a2ac1 5009 /* Register: RADIO_DACNF */
emilmont 80:8e73be2a2ac1 5010 /* Description: Device address match configuration. */
emilmont 80:8e73be2a2ac1 5011
emilmont 80:8e73be2a2ac1 5012 /* Bit 15 : TxAdd for device address 7. */
emilmont 80:8e73be2a2ac1 5013 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
emilmont 80:8e73be2a2ac1 5014 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
emilmont 80:8e73be2a2ac1 5015
emilmont 80:8e73be2a2ac1 5016 /* Bit 14 : TxAdd for device address 6. */
emilmont 80:8e73be2a2ac1 5017 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
emilmont 80:8e73be2a2ac1 5018 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
emilmont 80:8e73be2a2ac1 5019
emilmont 80:8e73be2a2ac1 5020 /* Bit 13 : TxAdd for device address 5. */
emilmont 80:8e73be2a2ac1 5021 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
emilmont 80:8e73be2a2ac1 5022 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
emilmont 80:8e73be2a2ac1 5023
emilmont 80:8e73be2a2ac1 5024 /* Bit 12 : TxAdd for device address 4. */
emilmont 80:8e73be2a2ac1 5025 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
emilmont 80:8e73be2a2ac1 5026 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
emilmont 80:8e73be2a2ac1 5027
emilmont 80:8e73be2a2ac1 5028 /* Bit 11 : TxAdd for device address 3. */
emilmont 80:8e73be2a2ac1 5029 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
emilmont 80:8e73be2a2ac1 5030 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
emilmont 80:8e73be2a2ac1 5031
emilmont 80:8e73be2a2ac1 5032 /* Bit 10 : TxAdd for device address 2. */
emilmont 80:8e73be2a2ac1 5033 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
emilmont 80:8e73be2a2ac1 5034 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
emilmont 80:8e73be2a2ac1 5035
emilmont 80:8e73be2a2ac1 5036 /* Bit 9 : TxAdd for device address 1. */
emilmont 80:8e73be2a2ac1 5037 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
emilmont 80:8e73be2a2ac1 5038 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
emilmont 80:8e73be2a2ac1 5039
emilmont 80:8e73be2a2ac1 5040 /* Bit 8 : TxAdd for device address 0. */
emilmont 80:8e73be2a2ac1 5041 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
emilmont 80:8e73be2a2ac1 5042 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
emilmont 80:8e73be2a2ac1 5043
emilmont 80:8e73be2a2ac1 5044 /* Bit 7 : Enable or disable device address matching using device address 7. */
emilmont 80:8e73be2a2ac1 5045 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
emilmont 80:8e73be2a2ac1 5046 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
emilmont 80:8e73be2a2ac1 5047 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 5048 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 5049
emilmont 80:8e73be2a2ac1 5050 /* Bit 6 : Enable or disable device address matching using device address 6. */
emilmont 80:8e73be2a2ac1 5051 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
emilmont 80:8e73be2a2ac1 5052 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
emilmont 80:8e73be2a2ac1 5053 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 5054 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 5055
emilmont 80:8e73be2a2ac1 5056 /* Bit 5 : Enable or disable device address matching using device address 5. */
emilmont 80:8e73be2a2ac1 5057 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
emilmont 80:8e73be2a2ac1 5058 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
emilmont 80:8e73be2a2ac1 5059 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 5060 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 5061
emilmont 80:8e73be2a2ac1 5062 /* Bit 4 : Enable or disable device address matching using device address 4. */
emilmont 80:8e73be2a2ac1 5063 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
emilmont 80:8e73be2a2ac1 5064 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
emilmont 80:8e73be2a2ac1 5065 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 5066 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 5067
emilmont 80:8e73be2a2ac1 5068 /* Bit 3 : Enable or disable device address matching using device address 3. */
emilmont 80:8e73be2a2ac1 5069 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
emilmont 80:8e73be2a2ac1 5070 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
emilmont 80:8e73be2a2ac1 5071 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 5072 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 5073
emilmont 80:8e73be2a2ac1 5074 /* Bit 2 : Enable or disable device address matching using device address 2. */
emilmont 80:8e73be2a2ac1 5075 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
emilmont 80:8e73be2a2ac1 5076 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
emilmont 80:8e73be2a2ac1 5077 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 5078 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 5079
emilmont 80:8e73be2a2ac1 5080 /* Bit 1 : Enable or disable device address matching using device address 1. */
emilmont 80:8e73be2a2ac1 5081 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
emilmont 80:8e73be2a2ac1 5082 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
emilmont 80:8e73be2a2ac1 5083 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 5084 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 5085
emilmont 80:8e73be2a2ac1 5086 /* Bit 0 : Enable or disable device address matching using device address 0. */
emilmont 80:8e73be2a2ac1 5087 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
emilmont 80:8e73be2a2ac1 5088 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
emilmont 80:8e73be2a2ac1 5089 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 5090 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 5091
emilmont 80:8e73be2a2ac1 5092 /* Register: RADIO_OVERRIDE0 */
emilmont 80:8e73be2a2ac1 5093 /* Description: Trim value override register 0. */
emilmont 80:8e73be2a2ac1 5094
emilmont 80:8e73be2a2ac1 5095 /* Bits 31..0 : Trim value override register 0. */
emilmont 80:8e73be2a2ac1 5096 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
emilmont 80:8e73be2a2ac1 5097 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
emilmont 80:8e73be2a2ac1 5098
emilmont 80:8e73be2a2ac1 5099 /* Register: RADIO_OVERRIDE1 */
emilmont 80:8e73be2a2ac1 5100 /* Description: Trim value override register 1. */
emilmont 80:8e73be2a2ac1 5101
emilmont 80:8e73be2a2ac1 5102 /* Bits 31..0 : Trim value override register 1. */
emilmont 80:8e73be2a2ac1 5103 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
emilmont 80:8e73be2a2ac1 5104 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
emilmont 80:8e73be2a2ac1 5105
emilmont 80:8e73be2a2ac1 5106 /* Register: RADIO_OVERRIDE2 */
emilmont 80:8e73be2a2ac1 5107 /* Description: Trim value override register 2. */
emilmont 80:8e73be2a2ac1 5108
emilmont 80:8e73be2a2ac1 5109 /* Bits 31..0 : Trim value override register 2. */
emilmont 80:8e73be2a2ac1 5110 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
emilmont 80:8e73be2a2ac1 5111 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
emilmont 80:8e73be2a2ac1 5112
emilmont 80:8e73be2a2ac1 5113 /* Register: RADIO_OVERRIDE3 */
emilmont 80:8e73be2a2ac1 5114 /* Description: Trim value override register 3. */
emilmont 80:8e73be2a2ac1 5115
emilmont 80:8e73be2a2ac1 5116 /* Bits 31..0 : Trim value override register 3. */
emilmont 80:8e73be2a2ac1 5117 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
emilmont 80:8e73be2a2ac1 5118 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
emilmont 80:8e73be2a2ac1 5119
emilmont 80:8e73be2a2ac1 5120 /* Register: RADIO_OVERRIDE4 */
emilmont 80:8e73be2a2ac1 5121 /* Description: Trim value override register 4. */
emilmont 80:8e73be2a2ac1 5122
emilmont 80:8e73be2a2ac1 5123 /* Bit 31 : Enable or disable override of default trim values. */
emilmont 80:8e73be2a2ac1 5124 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 5125 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 5126 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
emilmont 80:8e73be2a2ac1 5127 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
emilmont 80:8e73be2a2ac1 5128
emilmont 80:8e73be2a2ac1 5129 /* Bits 27..0 : Trim value override register 4. */
emilmont 80:8e73be2a2ac1 5130 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
emilmont 80:8e73be2a2ac1 5131 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
emilmont 80:8e73be2a2ac1 5132
emilmont 80:8e73be2a2ac1 5133 /* Register: RADIO_POWER */
emilmont 80:8e73be2a2ac1 5134 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 5135
emilmont 80:8e73be2a2ac1 5136 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 5137 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 5138 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 5139 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 5140 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 5141
emilmont 80:8e73be2a2ac1 5142
emilmont 80:8e73be2a2ac1 5143 /* Peripheral: RNG */
emilmont 80:8e73be2a2ac1 5144 /* Description: Random Number Generator. */
emilmont 80:8e73be2a2ac1 5145
emilmont 80:8e73be2a2ac1 5146 /* Register: RNG_SHORTS */
emilmont 80:8e73be2a2ac1 5147 /* Description: Shortcut for the RNG. */
emilmont 80:8e73be2a2ac1 5148
emilmont 80:8e73be2a2ac1 5149 /* Bit 0 : Short-cut between VALRDY event and STOP task. */
emilmont 80:8e73be2a2ac1 5150 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
emilmont 80:8e73be2a2ac1 5151 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
emilmont 80:8e73be2a2ac1 5152 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5153 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5154
emilmont 80:8e73be2a2ac1 5155 /* Register: RNG_INTENSET */
emilmont 80:8e73be2a2ac1 5156 /* Description: Interrupt enable set register */
emilmont 80:8e73be2a2ac1 5157
emilmont 80:8e73be2a2ac1 5158 /* Bit 0 : Enable interrupt on VALRDY event. */
emilmont 80:8e73be2a2ac1 5159 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
emilmont 80:8e73be2a2ac1 5160 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
emilmont 80:8e73be2a2ac1 5161 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5162 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5163 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5164
emilmont 80:8e73be2a2ac1 5165 /* Register: RNG_INTENCLR */
emilmont 80:8e73be2a2ac1 5166 /* Description: Interrupt enable clear register */
emilmont 80:8e73be2a2ac1 5167
emilmont 80:8e73be2a2ac1 5168 /* Bit 0 : Disable interrupt on VALRDY event. */
emilmont 80:8e73be2a2ac1 5169 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
emilmont 80:8e73be2a2ac1 5170 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
emilmont 80:8e73be2a2ac1 5171 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5172 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5173 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5174
emilmont 80:8e73be2a2ac1 5175 /* Register: RNG_CONFIG */
emilmont 80:8e73be2a2ac1 5176 /* Description: Configuration register. */
emilmont 80:8e73be2a2ac1 5177
emilmont 80:8e73be2a2ac1 5178 /* Bit 0 : Digital error correction enable. */
emilmont 80:8e73be2a2ac1 5179 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
emilmont 80:8e73be2a2ac1 5180 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
emilmont 80:8e73be2a2ac1 5181 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
emilmont 80:8e73be2a2ac1 5182 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
emilmont 80:8e73be2a2ac1 5183
emilmont 80:8e73be2a2ac1 5184 /* Register: RNG_VALUE */
emilmont 80:8e73be2a2ac1 5185 /* Description: RNG random number. */
emilmont 80:8e73be2a2ac1 5186
emilmont 80:8e73be2a2ac1 5187 /* Bits 7..0 : Generated random number. */
emilmont 80:8e73be2a2ac1 5188 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
emilmont 80:8e73be2a2ac1 5189 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
emilmont 80:8e73be2a2ac1 5190
emilmont 80:8e73be2a2ac1 5191 /* Register: RNG_POWER */
emilmont 80:8e73be2a2ac1 5192 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 5193
emilmont 80:8e73be2a2ac1 5194 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 5195 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 5196 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 5197 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 5198 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 5199
emilmont 80:8e73be2a2ac1 5200
emilmont 80:8e73be2a2ac1 5201 /* Peripheral: RTC */
emilmont 80:8e73be2a2ac1 5202 /* Description: Real time counter 0. */
emilmont 80:8e73be2a2ac1 5203
emilmont 80:8e73be2a2ac1 5204 /* Register: RTC_INTENSET */
emilmont 80:8e73be2a2ac1 5205 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 5206
emilmont 80:8e73be2a2ac1 5207 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
emilmont 80:8e73be2a2ac1 5208 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5209 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5210 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5211 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5212 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5213
emilmont 80:8e73be2a2ac1 5214 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
emilmont 80:8e73be2a2ac1 5215 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5216 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5217 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5218 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5219 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5220
emilmont 80:8e73be2a2ac1 5221 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
emilmont 80:8e73be2a2ac1 5222 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5223 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5224 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5225 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5226 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5227
emilmont 80:8e73be2a2ac1 5228 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
emilmont 80:8e73be2a2ac1 5229 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5230 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5231 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5232 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5233 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5234
emilmont 80:8e73be2a2ac1 5235 /* Bit 1 : Enable interrupt on OVRFLW event. */
emilmont 80:8e73be2a2ac1 5236 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5237 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5238 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5239 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5240 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5241
emilmont 80:8e73be2a2ac1 5242 /* Bit 0 : Enable interrupt on TICK event. */
emilmont 80:8e73be2a2ac1 5243 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
emilmont 80:8e73be2a2ac1 5244 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
emilmont 80:8e73be2a2ac1 5245 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5246 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5247 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5248
emilmont 80:8e73be2a2ac1 5249 /* Register: RTC_INTENCLR */
emilmont 80:8e73be2a2ac1 5250 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 5251
emilmont 80:8e73be2a2ac1 5252 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
emilmont 80:8e73be2a2ac1 5253 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5254 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5255 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5256 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5257 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5258
emilmont 80:8e73be2a2ac1 5259 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
emilmont 80:8e73be2a2ac1 5260 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5261 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5262 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5263 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5264 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5265
emilmont 80:8e73be2a2ac1 5266 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
emilmont 80:8e73be2a2ac1 5267 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5268 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5269 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5270 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5271 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5272
emilmont 80:8e73be2a2ac1 5273 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
emilmont 80:8e73be2a2ac1 5274 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5275 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5276 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5277 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5278 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5279
emilmont 80:8e73be2a2ac1 5280 /* Bit 1 : Disable interrupt on OVRFLW event. */
emilmont 80:8e73be2a2ac1 5281 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5282 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5283 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5284 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5285 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5286
emilmont 80:8e73be2a2ac1 5287 /* Bit 0 : Disable interrupt on TICK event. */
emilmont 80:8e73be2a2ac1 5288 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
emilmont 80:8e73be2a2ac1 5289 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
emilmont 80:8e73be2a2ac1 5290 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5291 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5292 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5293
emilmont 80:8e73be2a2ac1 5294 /* Register: RTC_EVTEN */
emilmont 80:8e73be2a2ac1 5295 /* Description: Configures event enable routing to PPI for each RTC event. */
emilmont 80:8e73be2a2ac1 5296
emilmont 80:8e73be2a2ac1 5297 /* Bit 19 : COMPARE[3] event enable. */
emilmont 80:8e73be2a2ac1 5298 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5299 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5300 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5301 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5302
emilmont 80:8e73be2a2ac1 5303 /* Bit 18 : COMPARE[2] event enable. */
emilmont 80:8e73be2a2ac1 5304 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5305 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5306 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5307 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5308
emilmont 80:8e73be2a2ac1 5309 /* Bit 17 : COMPARE[1] event enable. */
emilmont 80:8e73be2a2ac1 5310 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5311 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5312 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5313 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5314
emilmont 80:8e73be2a2ac1 5315 /* Bit 16 : COMPARE[0] event enable. */
emilmont 80:8e73be2a2ac1 5316 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5317 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5318 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5319 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5320
emilmont 80:8e73be2a2ac1 5321 /* Bit 1 : OVRFLW event enable. */
emilmont 80:8e73be2a2ac1 5322 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5323 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5324 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5325 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5326
emilmont 80:8e73be2a2ac1 5327 /* Bit 0 : TICK event enable. */
emilmont 80:8e73be2a2ac1 5328 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
emilmont 80:8e73be2a2ac1 5329 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
emilmont 80:8e73be2a2ac1 5330 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5331 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5332
emilmont 80:8e73be2a2ac1 5333 /* Register: RTC_EVTENSET */
emilmont 80:8e73be2a2ac1 5334 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
emilmont 80:8e73be2a2ac1 5335
emilmont 80:8e73be2a2ac1 5336 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
emilmont 80:8e73be2a2ac1 5337 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5338 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5339 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5340 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5341 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
emilmont 80:8e73be2a2ac1 5342
emilmont 80:8e73be2a2ac1 5343 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
emilmont 80:8e73be2a2ac1 5344 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5345 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5346 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5347 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5348 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
emilmont 80:8e73be2a2ac1 5349
emilmont 80:8e73be2a2ac1 5350 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
emilmont 80:8e73be2a2ac1 5351 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5352 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5353 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5354 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5355 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
emilmont 80:8e73be2a2ac1 5356
emilmont 80:8e73be2a2ac1 5357 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
emilmont 80:8e73be2a2ac1 5358 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5359 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5360 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5361 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5362 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
emilmont 80:8e73be2a2ac1 5363
emilmont 80:8e73be2a2ac1 5364 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
emilmont 80:8e73be2a2ac1 5365 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5366 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5367 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5368 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5369 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
emilmont 80:8e73be2a2ac1 5370
emilmont 80:8e73be2a2ac1 5371 /* Bit 0 : Enable routing to PPI of TICK event. */
emilmont 80:8e73be2a2ac1 5372 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
emilmont 80:8e73be2a2ac1 5373 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
emilmont 80:8e73be2a2ac1 5374 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5375 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5376 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
emilmont 80:8e73be2a2ac1 5377
emilmont 80:8e73be2a2ac1 5378 /* Register: RTC_EVTENCLR */
emilmont 80:8e73be2a2ac1 5379 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
emilmont 80:8e73be2a2ac1 5380
emilmont 80:8e73be2a2ac1 5381 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
emilmont 80:8e73be2a2ac1 5382 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5383 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5384 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5385 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5386 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
emilmont 80:8e73be2a2ac1 5387
emilmont 80:8e73be2a2ac1 5388 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
emilmont 80:8e73be2a2ac1 5389 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5390 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5391 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5392 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5393 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
emilmont 80:8e73be2a2ac1 5394
emilmont 80:8e73be2a2ac1 5395 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
emilmont 80:8e73be2a2ac1 5396 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5397 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5398 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5399 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5400 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
emilmont 80:8e73be2a2ac1 5401
emilmont 80:8e73be2a2ac1 5402 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
emilmont 80:8e73be2a2ac1 5403 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5404 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5405 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5406 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5407 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
emilmont 80:8e73be2a2ac1 5408
emilmont 80:8e73be2a2ac1 5409 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
emilmont 80:8e73be2a2ac1 5410 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5411 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
emilmont 80:8e73be2a2ac1 5412 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5413 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5414 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
emilmont 80:8e73be2a2ac1 5415
emilmont 80:8e73be2a2ac1 5416 /* Bit 0 : Disable routing to PPI of TICK event. */
emilmont 80:8e73be2a2ac1 5417 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
emilmont 80:8e73be2a2ac1 5418 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
emilmont 80:8e73be2a2ac1 5419 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
emilmont 80:8e73be2a2ac1 5420 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
emilmont 80:8e73be2a2ac1 5421 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
emilmont 80:8e73be2a2ac1 5422
emilmont 80:8e73be2a2ac1 5423 /* Register: RTC_COUNTER */
emilmont 80:8e73be2a2ac1 5424 /* Description: Current COUNTER value. */
emilmont 80:8e73be2a2ac1 5425
emilmont 80:8e73be2a2ac1 5426 /* Bits 23..0 : Counter value. */
emilmont 80:8e73be2a2ac1 5427 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
emilmont 80:8e73be2a2ac1 5428 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
emilmont 80:8e73be2a2ac1 5429
emilmont 80:8e73be2a2ac1 5430 /* Register: RTC_PRESCALER */
emilmont 80:8e73be2a2ac1 5431 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
emilmont 80:8e73be2a2ac1 5432
emilmont 80:8e73be2a2ac1 5433 /* Bits 11..0 : RTC PRESCALER value. */
emilmont 80:8e73be2a2ac1 5434 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
emilmont 80:8e73be2a2ac1 5435 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
emilmont 80:8e73be2a2ac1 5436
emilmont 80:8e73be2a2ac1 5437 /* Register: RTC_CC */
emilmont 80:8e73be2a2ac1 5438 /* Description: Capture/compare registers. */
emilmont 80:8e73be2a2ac1 5439
emilmont 80:8e73be2a2ac1 5440 /* Bits 23..0 : Compare value. */
emilmont 80:8e73be2a2ac1 5441 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
emilmont 80:8e73be2a2ac1 5442 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
emilmont 80:8e73be2a2ac1 5443
emilmont 80:8e73be2a2ac1 5444 /* Register: RTC_POWER */
emilmont 80:8e73be2a2ac1 5445 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 5446
emilmont 80:8e73be2a2ac1 5447 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 5448 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 5449 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 5450 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 5451 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 5452
emilmont 80:8e73be2a2ac1 5453
emilmont 80:8e73be2a2ac1 5454 /* Peripheral: SPI */
emilmont 80:8e73be2a2ac1 5455 /* Description: SPI master 0. */
emilmont 80:8e73be2a2ac1 5456
emilmont 80:8e73be2a2ac1 5457 /* Register: SPI_INTENSET */
emilmont 80:8e73be2a2ac1 5458 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 5459
emilmont 80:8e73be2a2ac1 5460 /* Bit 2 : Enable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 5461 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 5462 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 5463 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5464 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5465 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5466
emilmont 80:8e73be2a2ac1 5467 /* Register: SPI_INTENCLR */
emilmont 80:8e73be2a2ac1 5468 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 5469
emilmont 80:8e73be2a2ac1 5470 /* Bit 2 : Disable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 5471 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
emilmont 80:8e73be2a2ac1 5472 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
emilmont 80:8e73be2a2ac1 5473 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5474 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5475 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5476
emilmont 80:8e73be2a2ac1 5477 /* Register: SPI_ENABLE */
emilmont 80:8e73be2a2ac1 5478 /* Description: Enable SPI. */
emilmont 80:8e73be2a2ac1 5479
emilmont 80:8e73be2a2ac1 5480 /* Bits 2..0 : Enable or disable SPI. */
emilmont 80:8e73be2a2ac1 5481 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 5482 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 5483 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
emilmont 80:8e73be2a2ac1 5484 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
emilmont 80:8e73be2a2ac1 5485
emilmont 80:8e73be2a2ac1 5486 /* Register: SPI_RXD */
emilmont 80:8e73be2a2ac1 5487 /* Description: RX data. */
emilmont 80:8e73be2a2ac1 5488
emilmont 80:8e73be2a2ac1 5489 /* Bits 7..0 : RX data from last transfer. */
emilmont 80:8e73be2a2ac1 5490 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
emilmont 80:8e73be2a2ac1 5491 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
emilmont 80:8e73be2a2ac1 5492
emilmont 80:8e73be2a2ac1 5493 /* Register: SPI_TXD */
emilmont 80:8e73be2a2ac1 5494 /* Description: TX data. */
emilmont 80:8e73be2a2ac1 5495
emilmont 80:8e73be2a2ac1 5496 /* Bits 7..0 : TX data for next transfer. */
emilmont 80:8e73be2a2ac1 5497 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
emilmont 80:8e73be2a2ac1 5498 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
emilmont 80:8e73be2a2ac1 5499
emilmont 80:8e73be2a2ac1 5500 /* Register: SPI_FREQUENCY */
emilmont 80:8e73be2a2ac1 5501 /* Description: SPI frequency */
emilmont 80:8e73be2a2ac1 5502
emilmont 80:8e73be2a2ac1 5503 /* Bits 31..0 : SPI data rate. */
emilmont 80:8e73be2a2ac1 5504 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
emilmont 80:8e73be2a2ac1 5505 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
emilmont 80:8e73be2a2ac1 5506 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
emilmont 80:8e73be2a2ac1 5507 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
emilmont 80:8e73be2a2ac1 5508 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
emilmont 80:8e73be2a2ac1 5509 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
emilmont 80:8e73be2a2ac1 5510 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
emilmont 80:8e73be2a2ac1 5511 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
emilmont 80:8e73be2a2ac1 5512 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
emilmont 80:8e73be2a2ac1 5513
emilmont 80:8e73be2a2ac1 5514 /* Register: SPI_CONFIG */
emilmont 80:8e73be2a2ac1 5515 /* Description: Configuration register. */
emilmont 80:8e73be2a2ac1 5516
emilmont 80:8e73be2a2ac1 5517 /* Bit 2 : Serial clock (SCK) polarity. */
emilmont 80:8e73be2a2ac1 5518 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
emilmont 80:8e73be2a2ac1 5519 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
emilmont 80:8e73be2a2ac1 5520 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
emilmont 80:8e73be2a2ac1 5521 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
emilmont 80:8e73be2a2ac1 5522
emilmont 80:8e73be2a2ac1 5523 /* Bit 1 : Serial clock (SCK) phase. */
emilmont 80:8e73be2a2ac1 5524 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
emilmont 80:8e73be2a2ac1 5525 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
emilmont 80:8e73be2a2ac1 5526 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
emilmont 80:8e73be2a2ac1 5527 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
emilmont 80:8e73be2a2ac1 5528
emilmont 80:8e73be2a2ac1 5529 /* Bit 0 : Bit order. */
emilmont 80:8e73be2a2ac1 5530 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
emilmont 80:8e73be2a2ac1 5531 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
emilmont 80:8e73be2a2ac1 5532 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
emilmont 80:8e73be2a2ac1 5533 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
emilmont 80:8e73be2a2ac1 5534
emilmont 80:8e73be2a2ac1 5535 /* Register: SPI_POWER */
emilmont 80:8e73be2a2ac1 5536 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 5537
emilmont 80:8e73be2a2ac1 5538 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 5539 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 5540 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 5541 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 5542 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 5543
emilmont 80:8e73be2a2ac1 5544
emilmont 80:8e73be2a2ac1 5545 /* Peripheral: SPIS */
emilmont 80:8e73be2a2ac1 5546 /* Description: SPI slave 1. */
emilmont 80:8e73be2a2ac1 5547
emilmont 80:8e73be2a2ac1 5548 /* Register: SPIS_SHORTS */
emilmont 80:8e73be2a2ac1 5549 /* Description: Shortcuts for SPIS. */
emilmont 80:8e73be2a2ac1 5550
emilmont 80:8e73be2a2ac1 5551 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
emilmont 80:8e73be2a2ac1 5552 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
emilmont 80:8e73be2a2ac1 5553 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
emilmont 80:8e73be2a2ac1 5554 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5555 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5556
emilmont 80:8e73be2a2ac1 5557 /* Register: SPIS_INTENSET */
emilmont 80:8e73be2a2ac1 5558 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 5559
emilmont 80:8e73be2a2ac1 5560 /* Bit 10 : Enable interrupt on ACQUIRED event. */
emilmont 80:8e73be2a2ac1 5561 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
emilmont 80:8e73be2a2ac1 5562 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
emilmont 80:8e73be2a2ac1 5563 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5564 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5565 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5566
emilmont 80:8e73be2a2ac1 5567 /* Bit 1 : Enable interrupt on END event. */
emilmont 80:8e73be2a2ac1 5568 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
emilmont 80:8e73be2a2ac1 5569 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
emilmont 80:8e73be2a2ac1 5570 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5571 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5572 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5573
emilmont 80:8e73be2a2ac1 5574 /* Register: SPIS_INTENCLR */
emilmont 80:8e73be2a2ac1 5575 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 5576
emilmont 80:8e73be2a2ac1 5577 /* Bit 10 : Disable interrupt on ACQUIRED event. */
emilmont 80:8e73be2a2ac1 5578 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
emilmont 80:8e73be2a2ac1 5579 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
emilmont 80:8e73be2a2ac1 5580 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5581 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5582 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5583
emilmont 80:8e73be2a2ac1 5584 /* Bit 1 : Disable interrupt on END event. */
emilmont 80:8e73be2a2ac1 5585 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
emilmont 80:8e73be2a2ac1 5586 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
emilmont 80:8e73be2a2ac1 5587 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5588 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5589 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5590
emilmont 80:8e73be2a2ac1 5591 /* Register: SPIS_SEMSTAT */
emilmont 80:8e73be2a2ac1 5592 /* Description: Semaphore status. */
emilmont 80:8e73be2a2ac1 5593
emilmont 80:8e73be2a2ac1 5594 /* Bits 1..0 : Semaphore status. */
emilmont 80:8e73be2a2ac1 5595 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
emilmont 80:8e73be2a2ac1 5596 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
emilmont 80:8e73be2a2ac1 5597 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
emilmont 80:8e73be2a2ac1 5598 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
emilmont 80:8e73be2a2ac1 5599 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
emilmont 80:8e73be2a2ac1 5600 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
emilmont 80:8e73be2a2ac1 5601
emilmont 80:8e73be2a2ac1 5602 /* Register: SPIS_STATUS */
emilmont 80:8e73be2a2ac1 5603 /* Description: Status from last transaction. */
emilmont 80:8e73be2a2ac1 5604
emilmont 80:8e73be2a2ac1 5605 /* Bit 1 : RX buffer overflow detected, and prevented. */
emilmont 80:8e73be2a2ac1 5606 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
emilmont 80:8e73be2a2ac1 5607 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
emilmont 80:8e73be2a2ac1 5608 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
emilmont 80:8e73be2a2ac1 5609 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
emilmont 80:8e73be2a2ac1 5610 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
emilmont 80:8e73be2a2ac1 5611
emilmont 80:8e73be2a2ac1 5612 /* Bit 0 : TX buffer overread detected, and prevented. */
emilmont 80:8e73be2a2ac1 5613 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
emilmont 80:8e73be2a2ac1 5614 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
emilmont 80:8e73be2a2ac1 5615 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
emilmont 80:8e73be2a2ac1 5616 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
emilmont 80:8e73be2a2ac1 5617 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
emilmont 80:8e73be2a2ac1 5618
emilmont 80:8e73be2a2ac1 5619 /* Register: SPIS_ENABLE */
emilmont 80:8e73be2a2ac1 5620 /* Description: Enable SPIS. */
emilmont 80:8e73be2a2ac1 5621
emilmont 80:8e73be2a2ac1 5622 /* Bits 2..0 : Enable or disable SPIS. */
emilmont 80:8e73be2a2ac1 5623 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 5624 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 5625 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
emilmont 80:8e73be2a2ac1 5626 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
emilmont 80:8e73be2a2ac1 5627
emilmont 80:8e73be2a2ac1 5628 /* Register: SPIS_MAXRX */
emilmont 80:8e73be2a2ac1 5629 /* Description: Maximum number of bytes in the receive buffer. */
emilmont 80:8e73be2a2ac1 5630
emilmont 80:8e73be2a2ac1 5631 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
emilmont 80:8e73be2a2ac1 5632 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
emilmont 80:8e73be2a2ac1 5633 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
emilmont 80:8e73be2a2ac1 5634
emilmont 80:8e73be2a2ac1 5635 /* Register: SPIS_AMOUNTRX */
emilmont 80:8e73be2a2ac1 5636 /* Description: Number of bytes received in last granted transaction. */
emilmont 80:8e73be2a2ac1 5637
emilmont 80:8e73be2a2ac1 5638 /* Bits 7..0 : Number of bytes received in last granted transaction. */
emilmont 80:8e73be2a2ac1 5639 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
emilmont 80:8e73be2a2ac1 5640 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
emilmont 80:8e73be2a2ac1 5641
emilmont 80:8e73be2a2ac1 5642 /* Register: SPIS_MAXTX */
emilmont 80:8e73be2a2ac1 5643 /* Description: Maximum number of bytes in the transmit buffer. */
emilmont 80:8e73be2a2ac1 5644
emilmont 80:8e73be2a2ac1 5645 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
emilmont 80:8e73be2a2ac1 5646 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
emilmont 80:8e73be2a2ac1 5647 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
emilmont 80:8e73be2a2ac1 5648
emilmont 80:8e73be2a2ac1 5649 /* Register: SPIS_AMOUNTTX */
emilmont 80:8e73be2a2ac1 5650 /* Description: Number of bytes transmitted in last granted transaction. */
emilmont 80:8e73be2a2ac1 5651
emilmont 80:8e73be2a2ac1 5652 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
emilmont 80:8e73be2a2ac1 5653 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
emilmont 80:8e73be2a2ac1 5654 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
emilmont 80:8e73be2a2ac1 5655
emilmont 80:8e73be2a2ac1 5656 /* Register: SPIS_CONFIG */
emilmont 80:8e73be2a2ac1 5657 /* Description: Configuration register. */
emilmont 80:8e73be2a2ac1 5658
emilmont 80:8e73be2a2ac1 5659 /* Bit 2 : Serial clock (SCK) polarity. */
emilmont 80:8e73be2a2ac1 5660 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
emilmont 80:8e73be2a2ac1 5661 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
emilmont 80:8e73be2a2ac1 5662 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
emilmont 80:8e73be2a2ac1 5663 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
emilmont 80:8e73be2a2ac1 5664
emilmont 80:8e73be2a2ac1 5665 /* Bit 1 : Serial clock (SCK) phase. */
emilmont 80:8e73be2a2ac1 5666 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
emilmont 80:8e73be2a2ac1 5667 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
emilmont 80:8e73be2a2ac1 5668 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
emilmont 80:8e73be2a2ac1 5669 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
emilmont 80:8e73be2a2ac1 5670
emilmont 80:8e73be2a2ac1 5671 /* Bit 0 : Bit order. */
emilmont 80:8e73be2a2ac1 5672 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
emilmont 80:8e73be2a2ac1 5673 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
emilmont 80:8e73be2a2ac1 5674 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
emilmont 80:8e73be2a2ac1 5675 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
emilmont 80:8e73be2a2ac1 5676
emilmont 80:8e73be2a2ac1 5677 /* Register: SPIS_DEF */
emilmont 80:8e73be2a2ac1 5678 /* Description: Default character. */
emilmont 80:8e73be2a2ac1 5679
emilmont 80:8e73be2a2ac1 5680 /* Bits 7..0 : Default character. */
emilmont 80:8e73be2a2ac1 5681 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
emilmont 80:8e73be2a2ac1 5682 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
emilmont 80:8e73be2a2ac1 5683
emilmont 80:8e73be2a2ac1 5684 /* Register: SPIS_ORC */
emilmont 80:8e73be2a2ac1 5685 /* Description: Over-read character. */
emilmont 80:8e73be2a2ac1 5686
emilmont 80:8e73be2a2ac1 5687 /* Bits 7..0 : Over-read character. */
emilmont 80:8e73be2a2ac1 5688 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
emilmont 80:8e73be2a2ac1 5689 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
emilmont 80:8e73be2a2ac1 5690
emilmont 80:8e73be2a2ac1 5691 /* Register: SPIS_POWER */
emilmont 80:8e73be2a2ac1 5692 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 5693
emilmont 80:8e73be2a2ac1 5694 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 5695 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 5696 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 5697 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 5698 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 5699
emilmont 80:8e73be2a2ac1 5700
emilmont 80:8e73be2a2ac1 5701 /* Peripheral: TEMP */
emilmont 80:8e73be2a2ac1 5702 /* Description: Temperature Sensor. */
emilmont 80:8e73be2a2ac1 5703
emilmont 80:8e73be2a2ac1 5704 /* Register: TEMP_INTENSET */
emilmont 80:8e73be2a2ac1 5705 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 5706
emilmont 80:8e73be2a2ac1 5707 /* Bit 0 : Enable interrupt on DATARDY event. */
emilmont 80:8e73be2a2ac1 5708 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
emilmont 80:8e73be2a2ac1 5709 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
emilmont 80:8e73be2a2ac1 5710 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5711 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5712 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5713
emilmont 80:8e73be2a2ac1 5714 /* Register: TEMP_INTENCLR */
emilmont 80:8e73be2a2ac1 5715 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 5716
emilmont 80:8e73be2a2ac1 5717 /* Bit 0 : Disable interrupt on DATARDY event. */
emilmont 80:8e73be2a2ac1 5718 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
emilmont 80:8e73be2a2ac1 5719 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
emilmont 80:8e73be2a2ac1 5720 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5721 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5722 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5723
emilmont 80:8e73be2a2ac1 5724 /* Register: TEMP_POWER */
emilmont 80:8e73be2a2ac1 5725 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 5726
emilmont 80:8e73be2a2ac1 5727 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 5728 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 5729 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 5730 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 5731 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 5732
emilmont 80:8e73be2a2ac1 5733
emilmont 80:8e73be2a2ac1 5734 /* Peripheral: TIMER */
emilmont 80:8e73be2a2ac1 5735 /* Description: Timer 0. */
emilmont 80:8e73be2a2ac1 5736
emilmont 80:8e73be2a2ac1 5737 /* Register: TIMER_SHORTS */
emilmont 80:8e73be2a2ac1 5738 /* Description: Shortcuts for Timer. */
emilmont 80:8e73be2a2ac1 5739
emilmont 80:8e73be2a2ac1 5740 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
emilmont 80:8e73be2a2ac1 5741 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
emilmont 80:8e73be2a2ac1 5742 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
emilmont 80:8e73be2a2ac1 5743 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5744 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5745
emilmont 80:8e73be2a2ac1 5746 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
emilmont 80:8e73be2a2ac1 5747 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
emilmont 80:8e73be2a2ac1 5748 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
emilmont 80:8e73be2a2ac1 5749 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5750 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5751
emilmont 80:8e73be2a2ac1 5752 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
emilmont 80:8e73be2a2ac1 5753 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
emilmont 80:8e73be2a2ac1 5754 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
emilmont 80:8e73be2a2ac1 5755 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5756 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5757
emilmont 80:8e73be2a2ac1 5758 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
emilmont 80:8e73be2a2ac1 5759 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
emilmont 80:8e73be2a2ac1 5760 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
emilmont 80:8e73be2a2ac1 5761 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5762 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5763
emilmont 80:8e73be2a2ac1 5764 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
emilmont 80:8e73be2a2ac1 5765 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
emilmont 80:8e73be2a2ac1 5766 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
emilmont 80:8e73be2a2ac1 5767 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5768 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5769
emilmont 80:8e73be2a2ac1 5770 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
emilmont 80:8e73be2a2ac1 5771 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
emilmont 80:8e73be2a2ac1 5772 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
emilmont 80:8e73be2a2ac1 5773 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5774 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5775
emilmont 80:8e73be2a2ac1 5776 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
emilmont 80:8e73be2a2ac1 5777 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
emilmont 80:8e73be2a2ac1 5778 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
emilmont 80:8e73be2a2ac1 5779 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5780 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5781
emilmont 80:8e73be2a2ac1 5782 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
emilmont 80:8e73be2a2ac1 5783 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
emilmont 80:8e73be2a2ac1 5784 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
emilmont 80:8e73be2a2ac1 5785 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5786 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5787
emilmont 80:8e73be2a2ac1 5788 /* Register: TIMER_INTENSET */
emilmont 80:8e73be2a2ac1 5789 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 5790
emilmont 80:8e73be2a2ac1 5791 /* Bit 19 : Enable interrupt on COMPARE[3] */
emilmont 80:8e73be2a2ac1 5792 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5793 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5794 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5795 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5796 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5797
emilmont 80:8e73be2a2ac1 5798 /* Bit 18 : Enable interrupt on COMPARE[2] */
emilmont 80:8e73be2a2ac1 5799 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5800 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5801 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5802 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5803 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5804
emilmont 80:8e73be2a2ac1 5805 /* Bit 17 : Enable interrupt on COMPARE[1] */
emilmont 80:8e73be2a2ac1 5806 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5807 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5808 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5809 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5810 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5811
emilmont 80:8e73be2a2ac1 5812 /* Bit 16 : Enable interrupt on COMPARE[0] */
emilmont 80:8e73be2a2ac1 5813 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5814 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5815 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5816 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5817 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5818
emilmont 80:8e73be2a2ac1 5819 /* Register: TIMER_INTENCLR */
emilmont 80:8e73be2a2ac1 5820 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 5821
emilmont 80:8e73be2a2ac1 5822 /* Bit 19 : Disable interrupt on COMPARE[3] */
emilmont 80:8e73be2a2ac1 5823 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5824 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
emilmont 80:8e73be2a2ac1 5825 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5826 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5827 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5828
emilmont 80:8e73be2a2ac1 5829 /* Bit 18 : Disable interrupt on COMPARE[2] */
emilmont 80:8e73be2a2ac1 5830 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5831 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
emilmont 80:8e73be2a2ac1 5832 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5833 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5834 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5835
emilmont 80:8e73be2a2ac1 5836 /* Bit 17 : Disable interrupt on COMPARE[1] */
emilmont 80:8e73be2a2ac1 5837 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5838 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
emilmont 80:8e73be2a2ac1 5839 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5840 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5841 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5842
emilmont 80:8e73be2a2ac1 5843 /* Bit 16 : Disable interrupt on COMPARE[0] */
emilmont 80:8e73be2a2ac1 5844 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5845 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
emilmont 80:8e73be2a2ac1 5846 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5847 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5848 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5849
emilmont 80:8e73be2a2ac1 5850 /* Register: TIMER_MODE */
emilmont 80:8e73be2a2ac1 5851 /* Description: Timer Mode selection. */
emilmont 80:8e73be2a2ac1 5852
emilmont 80:8e73be2a2ac1 5853 /* Bit 0 : Select Normal or Counter mode. */
emilmont 80:8e73be2a2ac1 5854 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
emilmont 80:8e73be2a2ac1 5855 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
emilmont 80:8e73be2a2ac1 5856 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
emilmont 80:8e73be2a2ac1 5857 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
emilmont 80:8e73be2a2ac1 5858
emilmont 80:8e73be2a2ac1 5859 /* Register: TIMER_BITMODE */
emilmont 80:8e73be2a2ac1 5860 /* Description: Sets timer behaviour. */
emilmont 80:8e73be2a2ac1 5861
emilmont 80:8e73be2a2ac1 5862 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
emilmont 80:8e73be2a2ac1 5863 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
emilmont 80:8e73be2a2ac1 5864 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
emilmont 80:8e73be2a2ac1 5865 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
emilmont 80:8e73be2a2ac1 5866 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
emilmont 80:8e73be2a2ac1 5867 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
emilmont 80:8e73be2a2ac1 5868 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
emilmont 80:8e73be2a2ac1 5869
emilmont 80:8e73be2a2ac1 5870 /* Register: TIMER_PRESCALER */
emilmont 80:8e73be2a2ac1 5871 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
emilmont 80:8e73be2a2ac1 5872
emilmont 80:8e73be2a2ac1 5873 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
emilmont 80:8e73be2a2ac1 5874 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
emilmont 80:8e73be2a2ac1 5875 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
emilmont 80:8e73be2a2ac1 5876
emilmont 80:8e73be2a2ac1 5877 /* Register: TIMER_POWER */
emilmont 80:8e73be2a2ac1 5878 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 5879
emilmont 80:8e73be2a2ac1 5880 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 5881 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 5882 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 5883 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 5884 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 5885
emilmont 80:8e73be2a2ac1 5886
emilmont 80:8e73be2a2ac1 5887 /* Peripheral: TWI */
emilmont 80:8e73be2a2ac1 5888 /* Description: Two-wire interface master 0. */
emilmont 80:8e73be2a2ac1 5889
emilmont 80:8e73be2a2ac1 5890 /* Register: TWI_SHORTS */
emilmont 80:8e73be2a2ac1 5891 /* Description: Shortcuts for TWI. */
emilmont 80:8e73be2a2ac1 5892
emilmont 80:8e73be2a2ac1 5893 /* Bit 1 : Shortcut between BB event and the STOP task. */
emilmont 80:8e73be2a2ac1 5894 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
emilmont 80:8e73be2a2ac1 5895 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
emilmont 80:8e73be2a2ac1 5896 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5897 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5898
emilmont 80:8e73be2a2ac1 5899 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
emilmont 80:8e73be2a2ac1 5900 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
emilmont 80:8e73be2a2ac1 5901 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
emilmont 80:8e73be2a2ac1 5902 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 5903 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 5904
emilmont 80:8e73be2a2ac1 5905 /* Register: TWI_INTENSET */
emilmont 80:8e73be2a2ac1 5906 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 5907
emilmont 80:8e73be2a2ac1 5908 /* Bit 14 : Enable interrupt on BB event. */
emilmont 80:8e73be2a2ac1 5909 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
emilmont 80:8e73be2a2ac1 5910 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
emilmont 80:8e73be2a2ac1 5911 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5912 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5913 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5914
emilmont 80:8e73be2a2ac1 5915 /* Bit 9 : Enable interrupt on ERROR event. */
emilmont 80:8e73be2a2ac1 5916 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
emilmont 80:8e73be2a2ac1 5917 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
emilmont 80:8e73be2a2ac1 5918 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5919 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5920 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5921
emilmont 80:8e73be2a2ac1 5922 /* Bit 7 : Enable interrupt on TXDSENT event. */
emilmont 80:8e73be2a2ac1 5923 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
emilmont 80:8e73be2a2ac1 5924 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
emilmont 80:8e73be2a2ac1 5925 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5926 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5927 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5928
emilmont 80:8e73be2a2ac1 5929 /* Bit 2 : Enable interrupt on READY event. */
emilmont 80:8e73be2a2ac1 5930 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
emilmont 80:8e73be2a2ac1 5931 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
emilmont 80:8e73be2a2ac1 5932 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5933 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5934 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5935
emilmont 80:8e73be2a2ac1 5936 /* Bit 1 : Enable interrupt on STOPPED event. */
emilmont 80:8e73be2a2ac1 5937 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
emilmont 80:8e73be2a2ac1 5938 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
emilmont 80:8e73be2a2ac1 5939 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5940 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5941 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 5942
emilmont 80:8e73be2a2ac1 5943 /* Register: TWI_INTENCLR */
emilmont 80:8e73be2a2ac1 5944 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 5945
emilmont 80:8e73be2a2ac1 5946 /* Bit 14 : Disable interrupt on BB event. */
emilmont 80:8e73be2a2ac1 5947 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
emilmont 80:8e73be2a2ac1 5948 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
emilmont 80:8e73be2a2ac1 5949 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5950 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5951 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5952
emilmont 80:8e73be2a2ac1 5953 /* Bit 9 : Disable interrupt on ERROR event. */
emilmont 80:8e73be2a2ac1 5954 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
emilmont 80:8e73be2a2ac1 5955 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
emilmont 80:8e73be2a2ac1 5956 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5957 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5958 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5959
emilmont 80:8e73be2a2ac1 5960 /* Bit 7 : Disable interrupt on TXDSENT event. */
emilmont 80:8e73be2a2ac1 5961 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
emilmont 80:8e73be2a2ac1 5962 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
emilmont 80:8e73be2a2ac1 5963 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5964 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5965 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5966
emilmont 80:8e73be2a2ac1 5967 /* Bit 2 : Disable interrupt on RXDREADY event. */
emilmont 80:8e73be2a2ac1 5968 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
emilmont 80:8e73be2a2ac1 5969 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
emilmont 80:8e73be2a2ac1 5970 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5971 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5972 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5973
emilmont 80:8e73be2a2ac1 5974 /* Bit 1 : Disable interrupt on STOPPED event. */
emilmont 80:8e73be2a2ac1 5975 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
emilmont 80:8e73be2a2ac1 5976 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
emilmont 80:8e73be2a2ac1 5977 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 5978 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 5979 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 5980
emilmont 80:8e73be2a2ac1 5981 /* Register: TWI_ERRORSRC */
emilmont 80:8e73be2a2ac1 5982 /* Description: Two-wire error source. Write error field to 1 to clear error. */
emilmont 80:8e73be2a2ac1 5983
emilmont 80:8e73be2a2ac1 5984 /* Bit 2 : NACK received after sending a data byte. */
emilmont 80:8e73be2a2ac1 5985 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
emilmont 80:8e73be2a2ac1 5986 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
emilmont 80:8e73be2a2ac1 5987 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
emilmont 80:8e73be2a2ac1 5988 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
emilmont 80:8e73be2a2ac1 5989 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
emilmont 80:8e73be2a2ac1 5990
emilmont 80:8e73be2a2ac1 5991 /* Bit 1 : NACK received after sending the address. */
emilmont 80:8e73be2a2ac1 5992 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
emilmont 80:8e73be2a2ac1 5993 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
emilmont 80:8e73be2a2ac1 5994 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
emilmont 80:8e73be2a2ac1 5995 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
emilmont 80:8e73be2a2ac1 5996 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
emilmont 80:8e73be2a2ac1 5997
emilmont 80:8e73be2a2ac1 5998 /* Register: TWI_ENABLE */
emilmont 80:8e73be2a2ac1 5999 /* Description: Enable two-wire master. */
emilmont 80:8e73be2a2ac1 6000
emilmont 80:8e73be2a2ac1 6001 /* Bits 2..0 : Enable or disable W2M */
emilmont 80:8e73be2a2ac1 6002 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 6003 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 6004 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 6005 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 6006
emilmont 80:8e73be2a2ac1 6007 /* Register: TWI_RXD */
emilmont 80:8e73be2a2ac1 6008 /* Description: RX data register. */
emilmont 80:8e73be2a2ac1 6009
emilmont 80:8e73be2a2ac1 6010 /* Bits 7..0 : RX data from last transfer. */
emilmont 80:8e73be2a2ac1 6011 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
emilmont 80:8e73be2a2ac1 6012 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
emilmont 80:8e73be2a2ac1 6013
emilmont 80:8e73be2a2ac1 6014 /* Register: TWI_TXD */
emilmont 80:8e73be2a2ac1 6015 /* Description: TX data register. */
emilmont 80:8e73be2a2ac1 6016
emilmont 80:8e73be2a2ac1 6017 /* Bits 7..0 : TX data for next transfer. */
emilmont 80:8e73be2a2ac1 6018 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
emilmont 80:8e73be2a2ac1 6019 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
emilmont 80:8e73be2a2ac1 6020
emilmont 80:8e73be2a2ac1 6021 /* Register: TWI_FREQUENCY */
emilmont 80:8e73be2a2ac1 6022 /* Description: Two-wire frequency. */
emilmont 80:8e73be2a2ac1 6023
emilmont 80:8e73be2a2ac1 6024 /* Bits 31..0 : Two-wire master clock frequency. */
emilmont 80:8e73be2a2ac1 6025 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
emilmont 80:8e73be2a2ac1 6026 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
emilmont 80:8e73be2a2ac1 6027 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
emilmont 80:8e73be2a2ac1 6028 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
emilmont 80:8e73be2a2ac1 6029 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
emilmont 80:8e73be2a2ac1 6030
emilmont 80:8e73be2a2ac1 6031 /* Register: TWI_ADDRESS */
emilmont 80:8e73be2a2ac1 6032 /* Description: Address used in the two-wire transfer. */
emilmont 80:8e73be2a2ac1 6033
emilmont 80:8e73be2a2ac1 6034 /* Bits 6..0 : Two-wire address. */
emilmont 80:8e73be2a2ac1 6035 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
emilmont 80:8e73be2a2ac1 6036 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
emilmont 80:8e73be2a2ac1 6037
emilmont 80:8e73be2a2ac1 6038 /* Register: TWI_POWER */
emilmont 80:8e73be2a2ac1 6039 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 6040
emilmont 80:8e73be2a2ac1 6041 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 6042 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 6043 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 6044 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 6045 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 6046
emilmont 80:8e73be2a2ac1 6047
emilmont 80:8e73be2a2ac1 6048 /* Peripheral: UART */
emilmont 80:8e73be2a2ac1 6049 /* Description: Universal Asynchronous Receiver/Transmitter. */
emilmont 80:8e73be2a2ac1 6050
emilmont 80:8e73be2a2ac1 6051 /* Register: UART_SHORTS */
emilmont 80:8e73be2a2ac1 6052 /* Description: Shortcuts for TWI. */
emilmont 80:8e73be2a2ac1 6053
emilmont 80:8e73be2a2ac1 6054 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
emilmont 80:8e73be2a2ac1 6055 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
emilmont 80:8e73be2a2ac1 6056 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
emilmont 80:8e73be2a2ac1 6057 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 6058 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 6059
emilmont 80:8e73be2a2ac1 6060 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */
emilmont 80:8e73be2a2ac1 6061 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
emilmont 80:8e73be2a2ac1 6062 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
emilmont 80:8e73be2a2ac1 6063 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
emilmont 80:8e73be2a2ac1 6064 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
emilmont 80:8e73be2a2ac1 6065
emilmont 80:8e73be2a2ac1 6066 /* Register: UART_INTENSET */
emilmont 80:8e73be2a2ac1 6067 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 6068
emilmont 80:8e73be2a2ac1 6069 /* Bit 17 : Enable interrupt on RXTO event. */
emilmont 80:8e73be2a2ac1 6070 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
emilmont 80:8e73be2a2ac1 6071 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
emilmont 80:8e73be2a2ac1 6072 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6073 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6074 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 6075
emilmont 80:8e73be2a2ac1 6076 /* Bit 9 : Enable interrupt on ERROR event. */
emilmont 80:8e73be2a2ac1 6077 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
emilmont 80:8e73be2a2ac1 6078 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
emilmont 80:8e73be2a2ac1 6079 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6080 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6081 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 6082
emilmont 80:8e73be2a2ac1 6083 /* Bit 7 : Enable interrupt on TXRDY event. */
emilmont 80:8e73be2a2ac1 6084 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
emilmont 80:8e73be2a2ac1 6085 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
emilmont 80:8e73be2a2ac1 6086 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6087 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6088 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 6089
emilmont 80:8e73be2a2ac1 6090 /* Bit 2 : Enable interrupt on RXRDY event. */
emilmont 80:8e73be2a2ac1 6091 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
emilmont 80:8e73be2a2ac1 6092 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
emilmont 80:8e73be2a2ac1 6093 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6094 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6095 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 6096
emilmont 80:8e73be2a2ac1 6097 /* Bit 1 : Enable interrupt on NCTS event. */
emilmont 80:8e73be2a2ac1 6098 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
emilmont 80:8e73be2a2ac1 6099 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
emilmont 80:8e73be2a2ac1 6100 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6101 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6102 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 6103
emilmont 80:8e73be2a2ac1 6104 /* Bit 0 : Enable interrupt on CTS event. */
emilmont 80:8e73be2a2ac1 6105 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
emilmont 80:8e73be2a2ac1 6106 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
emilmont 80:8e73be2a2ac1 6107 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6108 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6109 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 6110
emilmont 80:8e73be2a2ac1 6111 /* Register: UART_INTENCLR */
emilmont 80:8e73be2a2ac1 6112 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 6113
emilmont 80:8e73be2a2ac1 6114 /* Bit 17 : Disable interrupt on RXTO event. */
emilmont 80:8e73be2a2ac1 6115 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
emilmont 80:8e73be2a2ac1 6116 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
emilmont 80:8e73be2a2ac1 6117 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6118 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6119 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 6120
emilmont 80:8e73be2a2ac1 6121 /* Bit 9 : Disable interrupt on ERROR event. */
emilmont 80:8e73be2a2ac1 6122 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
emilmont 80:8e73be2a2ac1 6123 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
emilmont 80:8e73be2a2ac1 6124 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6125 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6126 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 6127
emilmont 80:8e73be2a2ac1 6128 /* Bit 7 : Disable interrupt on TXRDY event. */
emilmont 80:8e73be2a2ac1 6129 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
emilmont 80:8e73be2a2ac1 6130 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
emilmont 80:8e73be2a2ac1 6131 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6132 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6133 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 6134
emilmont 80:8e73be2a2ac1 6135 /* Bit 2 : Disable interrupt on RXRDY event. */
emilmont 80:8e73be2a2ac1 6136 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
emilmont 80:8e73be2a2ac1 6137 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
emilmont 80:8e73be2a2ac1 6138 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6139 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6140 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 6141
emilmont 80:8e73be2a2ac1 6142 /* Bit 1 : Disable interrupt on NCTS event. */
emilmont 80:8e73be2a2ac1 6143 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
emilmont 80:8e73be2a2ac1 6144 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
emilmont 80:8e73be2a2ac1 6145 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6146 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6147 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 6148
emilmont 80:8e73be2a2ac1 6149 /* Bit 0 : Disable interrupt on CTS event. */
emilmont 80:8e73be2a2ac1 6150 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
emilmont 80:8e73be2a2ac1 6151 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
emilmont 80:8e73be2a2ac1 6152 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6153 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6154 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 6155
emilmont 80:8e73be2a2ac1 6156 /* Register: UART_ERRORSRC */
emilmont 80:8e73be2a2ac1 6157 /* Description: Error source. Write error field to 1 to clear error. */
emilmont 80:8e73be2a2ac1 6158
emilmont 80:8e73be2a2ac1 6159 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
emilmont 80:8e73be2a2ac1 6160 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
emilmont 80:8e73be2a2ac1 6161 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
emilmont 80:8e73be2a2ac1 6162 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
emilmont 80:8e73be2a2ac1 6163 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
emilmont 80:8e73be2a2ac1 6164 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
emilmont 80:8e73be2a2ac1 6165
emilmont 80:8e73be2a2ac1 6166 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
emilmont 80:8e73be2a2ac1 6167 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
emilmont 80:8e73be2a2ac1 6168 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
emilmont 80:8e73be2a2ac1 6169 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
emilmont 80:8e73be2a2ac1 6170 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
emilmont 80:8e73be2a2ac1 6171 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
emilmont 80:8e73be2a2ac1 6172
emilmont 80:8e73be2a2ac1 6173 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
emilmont 80:8e73be2a2ac1 6174 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
emilmont 80:8e73be2a2ac1 6175 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
emilmont 80:8e73be2a2ac1 6176 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
emilmont 80:8e73be2a2ac1 6177 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
emilmont 80:8e73be2a2ac1 6178 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
emilmont 80:8e73be2a2ac1 6179
emilmont 80:8e73be2a2ac1 6180 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
emilmont 80:8e73be2a2ac1 6181 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
emilmont 80:8e73be2a2ac1 6182 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
emilmont 80:8e73be2a2ac1 6183 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
emilmont 80:8e73be2a2ac1 6184 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
emilmont 80:8e73be2a2ac1 6185 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
emilmont 80:8e73be2a2ac1 6186
emilmont 80:8e73be2a2ac1 6187 /* Register: UART_ENABLE */
emilmont 80:8e73be2a2ac1 6188 /* Description: Enable UART and acquire IOs. */
emilmont 80:8e73be2a2ac1 6189
emilmont 80:8e73be2a2ac1 6190 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
emilmont 80:8e73be2a2ac1 6191 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
emilmont 80:8e73be2a2ac1 6192 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
emilmont 80:8e73be2a2ac1 6193 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
emilmont 80:8e73be2a2ac1 6194 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
emilmont 80:8e73be2a2ac1 6195
emilmont 80:8e73be2a2ac1 6196 /* Register: UART_RXD */
emilmont 80:8e73be2a2ac1 6197 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */
emilmont 80:8e73be2a2ac1 6198
emilmont 80:8e73be2a2ac1 6199 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
emilmont 80:8e73be2a2ac1 6200 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
emilmont 80:8e73be2a2ac1 6201 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
emilmont 80:8e73be2a2ac1 6202
emilmont 80:8e73be2a2ac1 6203 /* Register: UART_TXD */
emilmont 80:8e73be2a2ac1 6204 /* Description: TXD register. */
emilmont 80:8e73be2a2ac1 6205
emilmont 80:8e73be2a2ac1 6206 /* Bits 7..0 : TX data for transfer. */
emilmont 80:8e73be2a2ac1 6207 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
emilmont 80:8e73be2a2ac1 6208 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
emilmont 80:8e73be2a2ac1 6209
emilmont 80:8e73be2a2ac1 6210 /* Register: UART_BAUDRATE */
emilmont 80:8e73be2a2ac1 6211 /* Description: UART Baudrate. */
emilmont 80:8e73be2a2ac1 6212
emilmont 80:8e73be2a2ac1 6213 /* Bits 31..0 : UART baudrate. */
emilmont 80:8e73be2a2ac1 6214 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
emilmont 80:8e73be2a2ac1 6215 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
emilmont 80:8e73be2a2ac1 6216 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
emilmont 80:8e73be2a2ac1 6217 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
emilmont 80:8e73be2a2ac1 6218 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
emilmont 80:8e73be2a2ac1 6219 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
emilmont 80:8e73be2a2ac1 6220 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
emilmont 80:8e73be2a2ac1 6221 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
emilmont 80:8e73be2a2ac1 6222 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
emilmont 80:8e73be2a2ac1 6223 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
emilmont 80:8e73be2a2ac1 6224 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
emilmont 80:8e73be2a2ac1 6225 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
emilmont 80:8e73be2a2ac1 6226 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
emilmont 80:8e73be2a2ac1 6227 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
emilmont 80:8e73be2a2ac1 6228 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
emilmont 80:8e73be2a2ac1 6229 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
emilmont 80:8e73be2a2ac1 6230 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
emilmont 80:8e73be2a2ac1 6231 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
emilmont 80:8e73be2a2ac1 6232
emilmont 80:8e73be2a2ac1 6233 /* Register: UART_CONFIG */
emilmont 80:8e73be2a2ac1 6234 /* Description: Configuration of parity and hardware flow control register. */
emilmont 80:8e73be2a2ac1 6235
emilmont 80:8e73be2a2ac1 6236 /* Bits 3..1 : Include parity bit. */
emilmont 80:8e73be2a2ac1 6237 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
emilmont 80:8e73be2a2ac1 6238 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
emilmont 80:8e73be2a2ac1 6239 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
emilmont 80:8e73be2a2ac1 6240 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
emilmont 80:8e73be2a2ac1 6241
emilmont 80:8e73be2a2ac1 6242 /* Bit 0 : Hardware flow control. */
emilmont 80:8e73be2a2ac1 6243 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
emilmont 80:8e73be2a2ac1 6244 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
emilmont 80:8e73be2a2ac1 6245 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
emilmont 80:8e73be2a2ac1 6246 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
emilmont 80:8e73be2a2ac1 6247
emilmont 80:8e73be2a2ac1 6248 /* Register: UART_POWER */
emilmont 80:8e73be2a2ac1 6249 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 6250
emilmont 80:8e73be2a2ac1 6251 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 6252 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 6253 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 6254 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 6255 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 6256
emilmont 80:8e73be2a2ac1 6257
emilmont 80:8e73be2a2ac1 6258 /* Peripheral: UICR */
emilmont 80:8e73be2a2ac1 6259 /* Description: User Information Configuration. */
emilmont 80:8e73be2a2ac1 6260
emilmont 80:8e73be2a2ac1 6261 /* Register: UICR_RBPCONF */
emilmont 80:8e73be2a2ac1 6262 /* Description: Readback protection configuration. */
emilmont 80:8e73be2a2ac1 6263
emilmont 80:8e73be2a2ac1 6264 /* Bits 15..8 : Readback protect all code in the device. */
emilmont 80:8e73be2a2ac1 6265 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
emilmont 80:8e73be2a2ac1 6266 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
emilmont 80:8e73be2a2ac1 6267 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 6268 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 6269
emilmont 80:8e73be2a2ac1 6270 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
emilmont 80:8e73be2a2ac1 6271 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
emilmont 80:8e73be2a2ac1 6272 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
emilmont 80:8e73be2a2ac1 6273 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
emilmont 80:8e73be2a2ac1 6274 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
emilmont 80:8e73be2a2ac1 6275
emilmont 80:8e73be2a2ac1 6276 /* Register: UICR_XTALFREQ */
emilmont 80:8e73be2a2ac1 6277 /* Description: Reset value for CLOCK XTALFREQ register. */
emilmont 80:8e73be2a2ac1 6278
emilmont 80:8e73be2a2ac1 6279 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
emilmont 80:8e73be2a2ac1 6280 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
emilmont 80:8e73be2a2ac1 6281 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
emilmont 80:8e73be2a2ac1 6282 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
emilmont 80:8e73be2a2ac1 6283 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
emilmont 80:8e73be2a2ac1 6284
emilmont 80:8e73be2a2ac1 6285 /* Register: UICR_FWID */
emilmont 80:8e73be2a2ac1 6286 /* Description: Firmware ID. */
emilmont 80:8e73be2a2ac1 6287
emilmont 80:8e73be2a2ac1 6288 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
emilmont 80:8e73be2a2ac1 6289 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
emilmont 80:8e73be2a2ac1 6290 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
emilmont 80:8e73be2a2ac1 6291
emilmont 80:8e73be2a2ac1 6292
emilmont 80:8e73be2a2ac1 6293 /* Peripheral: WDT */
emilmont 80:8e73be2a2ac1 6294 /* Description: Watchdog Timer. */
emilmont 80:8e73be2a2ac1 6295
emilmont 80:8e73be2a2ac1 6296 /* Register: WDT_INTENSET */
emilmont 80:8e73be2a2ac1 6297 /* Description: Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 6298
emilmont 80:8e73be2a2ac1 6299 /* Bit 0 : Enable interrupt on TIMEOUT event. */
emilmont 80:8e73be2a2ac1 6300 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
emilmont 80:8e73be2a2ac1 6301 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
emilmont 80:8e73be2a2ac1 6302 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6303 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6304 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
emilmont 80:8e73be2a2ac1 6305
emilmont 80:8e73be2a2ac1 6306 /* Register: WDT_INTENCLR */
emilmont 80:8e73be2a2ac1 6307 /* Description: Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 6308
emilmont 80:8e73be2a2ac1 6309 /* Bit 0 : Disable interrupt on TIMEOUT event. */
emilmont 80:8e73be2a2ac1 6310 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
emilmont 80:8e73be2a2ac1 6311 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
emilmont 80:8e73be2a2ac1 6312 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
emilmont 80:8e73be2a2ac1 6313 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
emilmont 80:8e73be2a2ac1 6314 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
emilmont 80:8e73be2a2ac1 6315
emilmont 80:8e73be2a2ac1 6316 /* Register: WDT_RUNSTATUS */
emilmont 80:8e73be2a2ac1 6317 /* Description: Watchdog running status. */
emilmont 80:8e73be2a2ac1 6318
emilmont 80:8e73be2a2ac1 6319 /* Bit 0 : Watchdog running status. */
emilmont 80:8e73be2a2ac1 6320 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
emilmont 80:8e73be2a2ac1 6321 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
emilmont 80:8e73be2a2ac1 6322 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
emilmont 80:8e73be2a2ac1 6323 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
emilmont 80:8e73be2a2ac1 6324
emilmont 80:8e73be2a2ac1 6325 /* Register: WDT_REQSTATUS */
emilmont 80:8e73be2a2ac1 6326 /* Description: Request status. */
emilmont 80:8e73be2a2ac1 6327
emilmont 80:8e73be2a2ac1 6328 /* Bit 7 : Request status for RR[7]. */
emilmont 80:8e73be2a2ac1 6329 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
emilmont 80:8e73be2a2ac1 6330 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
emilmont 80:8e73be2a2ac1 6331 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
emilmont 80:8e73be2a2ac1 6332 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
emilmont 80:8e73be2a2ac1 6333
emilmont 80:8e73be2a2ac1 6334 /* Bit 6 : Request status for RR[6]. */
emilmont 80:8e73be2a2ac1 6335 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
emilmont 80:8e73be2a2ac1 6336 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
emilmont 80:8e73be2a2ac1 6337 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
emilmont 80:8e73be2a2ac1 6338 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
emilmont 80:8e73be2a2ac1 6339
emilmont 80:8e73be2a2ac1 6340 /* Bit 5 : Request status for RR[5]. */
emilmont 80:8e73be2a2ac1 6341 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
emilmont 80:8e73be2a2ac1 6342 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
emilmont 80:8e73be2a2ac1 6343 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
emilmont 80:8e73be2a2ac1 6344 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
emilmont 80:8e73be2a2ac1 6345
emilmont 80:8e73be2a2ac1 6346 /* Bit 4 : Request status for RR[4]. */
emilmont 80:8e73be2a2ac1 6347 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
emilmont 80:8e73be2a2ac1 6348 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
emilmont 80:8e73be2a2ac1 6349 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
emilmont 80:8e73be2a2ac1 6350 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
emilmont 80:8e73be2a2ac1 6351
emilmont 80:8e73be2a2ac1 6352 /* Bit 3 : Request status for RR[3]. */
emilmont 80:8e73be2a2ac1 6353 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
emilmont 80:8e73be2a2ac1 6354 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
emilmont 80:8e73be2a2ac1 6355 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
emilmont 80:8e73be2a2ac1 6356 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
emilmont 80:8e73be2a2ac1 6357
emilmont 80:8e73be2a2ac1 6358 /* Bit 2 : Request status for RR[2]. */
emilmont 80:8e73be2a2ac1 6359 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
emilmont 80:8e73be2a2ac1 6360 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
emilmont 80:8e73be2a2ac1 6361 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
emilmont 80:8e73be2a2ac1 6362 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
emilmont 80:8e73be2a2ac1 6363
emilmont 80:8e73be2a2ac1 6364 /* Bit 1 : Request status for RR[1]. */
emilmont 80:8e73be2a2ac1 6365 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
emilmont 80:8e73be2a2ac1 6366 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
emilmont 80:8e73be2a2ac1 6367 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
emilmont 80:8e73be2a2ac1 6368 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
emilmont 80:8e73be2a2ac1 6369
emilmont 80:8e73be2a2ac1 6370 /* Bit 0 : Request status for RR[0]. */
emilmont 80:8e73be2a2ac1 6371 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
emilmont 80:8e73be2a2ac1 6372 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
emilmont 80:8e73be2a2ac1 6373 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
emilmont 80:8e73be2a2ac1 6374 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
emilmont 80:8e73be2a2ac1 6375
emilmont 80:8e73be2a2ac1 6376 /* Register: WDT_RREN */
emilmont 80:8e73be2a2ac1 6377 /* Description: Reload request enable. */
emilmont 80:8e73be2a2ac1 6378
emilmont 80:8e73be2a2ac1 6379 /* Bit 7 : Enable or disable RR[7] register. */
emilmont 80:8e73be2a2ac1 6380 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
emilmont 80:8e73be2a2ac1 6381 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
emilmont 80:8e73be2a2ac1 6382 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
emilmont 80:8e73be2a2ac1 6383 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
emilmont 80:8e73be2a2ac1 6384
emilmont 80:8e73be2a2ac1 6385 /* Bit 6 : Enable or disable RR[6] register. */
emilmont 80:8e73be2a2ac1 6386 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
emilmont 80:8e73be2a2ac1 6387 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
emilmont 80:8e73be2a2ac1 6388 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
emilmont 80:8e73be2a2ac1 6389 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
emilmont 80:8e73be2a2ac1 6390
emilmont 80:8e73be2a2ac1 6391 /* Bit 5 : Enable or disable RR[5] register. */
emilmont 80:8e73be2a2ac1 6392 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
emilmont 80:8e73be2a2ac1 6393 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
emilmont 80:8e73be2a2ac1 6394 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
emilmont 80:8e73be2a2ac1 6395 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
emilmont 80:8e73be2a2ac1 6396
emilmont 80:8e73be2a2ac1 6397 /* Bit 4 : Enable or disable RR[4] register. */
emilmont 80:8e73be2a2ac1 6398 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
emilmont 80:8e73be2a2ac1 6399 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
emilmont 80:8e73be2a2ac1 6400 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
emilmont 80:8e73be2a2ac1 6401 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
emilmont 80:8e73be2a2ac1 6402
emilmont 80:8e73be2a2ac1 6403 /* Bit 3 : Enable or disable RR[3] register. */
emilmont 80:8e73be2a2ac1 6404 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
emilmont 80:8e73be2a2ac1 6405 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
emilmont 80:8e73be2a2ac1 6406 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
emilmont 80:8e73be2a2ac1 6407 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
emilmont 80:8e73be2a2ac1 6408
emilmont 80:8e73be2a2ac1 6409 /* Bit 2 : Enable or disable RR[2] register. */
emilmont 80:8e73be2a2ac1 6410 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
emilmont 80:8e73be2a2ac1 6411 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
emilmont 80:8e73be2a2ac1 6412 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
emilmont 80:8e73be2a2ac1 6413 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
emilmont 80:8e73be2a2ac1 6414
emilmont 80:8e73be2a2ac1 6415 /* Bit 1 : Enable or disable RR[1] register. */
emilmont 80:8e73be2a2ac1 6416 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
emilmont 80:8e73be2a2ac1 6417 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
emilmont 80:8e73be2a2ac1 6418 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
emilmont 80:8e73be2a2ac1 6419 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
emilmont 80:8e73be2a2ac1 6420
emilmont 80:8e73be2a2ac1 6421 /* Bit 0 : Enable or disable RR[0] register. */
emilmont 80:8e73be2a2ac1 6422 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
emilmont 80:8e73be2a2ac1 6423 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
emilmont 80:8e73be2a2ac1 6424 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
emilmont 80:8e73be2a2ac1 6425 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
emilmont 80:8e73be2a2ac1 6426
emilmont 80:8e73be2a2ac1 6427 /* Register: WDT_CONFIG */
emilmont 80:8e73be2a2ac1 6428 /* Description: Configuration register. */
emilmont 80:8e73be2a2ac1 6429
emilmont 80:8e73be2a2ac1 6430 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
emilmont 80:8e73be2a2ac1 6431 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
emilmont 80:8e73be2a2ac1 6432 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
emilmont 80:8e73be2a2ac1 6433 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
emilmont 80:8e73be2a2ac1 6434 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
emilmont 80:8e73be2a2ac1 6435
emilmont 80:8e73be2a2ac1 6436 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
emilmont 80:8e73be2a2ac1 6437 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
emilmont 80:8e73be2a2ac1 6438 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
emilmont 80:8e73be2a2ac1 6439 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
emilmont 80:8e73be2a2ac1 6440 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
emilmont 80:8e73be2a2ac1 6441
emilmont 80:8e73be2a2ac1 6442 /* Register: WDT_RR */
emilmont 80:8e73be2a2ac1 6443 /* Description: Reload requests registers. */
emilmont 80:8e73be2a2ac1 6444
emilmont 80:8e73be2a2ac1 6445 /* Bits 31..0 : Reload register. */
emilmont 80:8e73be2a2ac1 6446 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
emilmont 80:8e73be2a2ac1 6447 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
emilmont 80:8e73be2a2ac1 6448 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
emilmont 80:8e73be2a2ac1 6449
emilmont 80:8e73be2a2ac1 6450 /* Register: WDT_POWER */
emilmont 80:8e73be2a2ac1 6451 /* Description: Peripheral power control. */
emilmont 80:8e73be2a2ac1 6452
emilmont 80:8e73be2a2ac1 6453 /* Bit 0 : Peripheral power control. */
emilmont 80:8e73be2a2ac1 6454 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
emilmont 80:8e73be2a2ac1 6455 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
emilmont 80:8e73be2a2ac1 6456 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
emilmont 80:8e73be2a2ac1 6457 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
emilmont 80:8e73be2a2ac1 6458
emilmont 80:8e73be2a2ac1 6459
emilmont 80:8e73be2a2ac1 6460 /*lint --flb "Leave library region" */
emilmont 80:8e73be2a2ac1 6461 #endif