erez i
version_2.0
Dependents: cc3000_ping_demo_try_2
Fork of
mbed
by 
mbed official
TARGET_NUCLEO_L152RE/stm32l1xx_rcc.h@77:869cf507173a, 2014-02-14 (annotated)
- Committer:
- emilmont
- Date:
- Fri Feb 14 14:36:43 2014 +0000
- Revision:
- 77:869cf507173a
- Child:
- 81:7d30d6019079
Release 77 of the mbed library
Main changes:
* Add target NUCLEO_F030R8
* Add target NUCLEO_F401RE
* Add target NUCLEO_F103RB
* Add target NUCLEO_L152RE
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32l1xx_rcc.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| emilmont | 77:869cf507173a | 5 | * @version V1.3.0 |
| emilmont | 77:869cf507173a | 6 | * @date 31-January-2014 |
| emilmont | 77:869cf507173a | 7 | * @brief This file contains all the functions prototypes for the RCC |
| emilmont | 77:869cf507173a | 8 | * firmware library. |
| emilmont | 77:869cf507173a | 9 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 10 | * @attention |
| emilmont | 77:869cf507173a | 11 | * |
| emilmont | 77:869cf507173a | 12 | * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 13 | * |
| emilmont | 77:869cf507173a | 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
| emilmont | 77:869cf507173a | 15 | * You may not use this file except in compliance with the License. |
| emilmont | 77:869cf507173a | 16 | * You may obtain a copy of the License at: |
| emilmont | 77:869cf507173a | 17 | * |
| emilmont | 77:869cf507173a | 18 | * http://www.st.com/software_license_agreement_liberty_v2 |
| emilmont | 77:869cf507173a | 19 | * |
| emilmont | 77:869cf507173a | 20 | * Unless required by applicable law or agreed to in writing, software |
| emilmont | 77:869cf507173a | 21 | * distributed under the License is distributed on an "AS IS" BASIS, |
| emilmont | 77:869cf507173a | 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| emilmont | 77:869cf507173a | 23 | * See the License for the specific language governing permissions and |
| emilmont | 77:869cf507173a | 24 | * limitations under the License. |
| emilmont | 77:869cf507173a | 25 | * |
| emilmont | 77:869cf507173a | 26 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 27 | */ |
| emilmont | 77:869cf507173a | 28 | |
| emilmont | 77:869cf507173a | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 30 | #ifndef __STM32L1xx_RCC_H |
| emilmont | 77:869cf507173a | 31 | #define __STM32L1xx_RCC_H |
| emilmont | 77:869cf507173a | 32 | |
| emilmont | 77:869cf507173a | 33 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 34 | extern "C" { |
| emilmont | 77:869cf507173a | 35 | #endif |
| emilmont | 77:869cf507173a | 36 | |
| emilmont | 77:869cf507173a | 37 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 38 | #include "stm32l1xx.h" |
| emilmont | 77:869cf507173a | 39 | |
| emilmont | 77:869cf507173a | 40 | /** @addtogroup STM32L1xx_StdPeriph_Driver |
| emilmont | 77:869cf507173a | 41 | * @{ |
| emilmont | 77:869cf507173a | 42 | */ |
| emilmont | 77:869cf507173a | 43 | |
| emilmont | 77:869cf507173a | 44 | /** @addtogroup RCC |
| emilmont | 77:869cf507173a | 45 | * @{ |
| emilmont | 77:869cf507173a | 46 | */ |
| emilmont | 77:869cf507173a | 47 | |
| emilmont | 77:869cf507173a | 48 | /* Exported types ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 49 | |
| emilmont | 77:869cf507173a | 50 | typedef struct |
| emilmont | 77:869cf507173a | 51 | { |
| emilmont | 77:869cf507173a | 52 | uint32_t SYSCLK_Frequency; |
| emilmont | 77:869cf507173a | 53 | uint32_t HCLK_Frequency; |
| emilmont | 77:869cf507173a | 54 | uint32_t PCLK1_Frequency; |
| emilmont | 77:869cf507173a | 55 | uint32_t PCLK2_Frequency; |
| emilmont | 77:869cf507173a | 56 | }RCC_ClocksTypeDef; |
| emilmont | 77:869cf507173a | 57 | |
| emilmont | 77:869cf507173a | 58 | /* Exported constants --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 59 | |
| emilmont | 77:869cf507173a | 60 | /** @defgroup RCC_Exported_Constants |
| emilmont | 77:869cf507173a | 61 | * @{ |
| emilmont | 77:869cf507173a | 62 | */ |
| emilmont | 77:869cf507173a | 63 | |
| emilmont | 77:869cf507173a | 64 | /** @defgroup RCC_HSE_configuration |
| emilmont | 77:869cf507173a | 65 | * @{ |
| emilmont | 77:869cf507173a | 66 | */ |
| emilmont | 77:869cf507173a | 67 | |
| emilmont | 77:869cf507173a | 68 | #define RCC_HSE_OFF ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 69 | #define RCC_HSE_ON ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 70 | #define RCC_HSE_Bypass ((uint8_t)0x05) |
| emilmont | 77:869cf507173a | 71 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
| emilmont | 77:869cf507173a | 72 | ((HSE) == RCC_HSE_Bypass)) |
| emilmont | 77:869cf507173a | 73 | |
| emilmont | 77:869cf507173a | 74 | /** |
| emilmont | 77:869cf507173a | 75 | * @} |
| emilmont | 77:869cf507173a | 76 | */ |
| emilmont | 77:869cf507173a | 77 | |
| emilmont | 77:869cf507173a | 78 | /** @defgroup RCC_MSI_Clock_Range |
| emilmont | 77:869cf507173a | 79 | * @{ |
| emilmont | 77:869cf507173a | 80 | */ |
| emilmont | 77:869cf507173a | 81 | |
| emilmont | 77:869cf507173a | 82 | #define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ |
| emilmont | 77:869cf507173a | 83 | #define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */ |
| emilmont | 77:869cf507173a | 84 | #define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ |
| emilmont | 77:869cf507173a | 85 | #define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ |
| emilmont | 77:869cf507173a | 86 | #define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ |
| emilmont | 77:869cf507173a | 87 | #define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ |
| emilmont | 77:869cf507173a | 88 | #define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ |
| emilmont | 77:869cf507173a | 89 | |
| emilmont | 77:869cf507173a | 90 | #define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \ |
| emilmont | 77:869cf507173a | 91 | ((RANGE) == RCC_MSIRange_1) || \ |
| emilmont | 77:869cf507173a | 92 | ((RANGE) == RCC_MSIRange_2) || \ |
| emilmont | 77:869cf507173a | 93 | ((RANGE) == RCC_MSIRange_3) || \ |
| emilmont | 77:869cf507173a | 94 | ((RANGE) == RCC_MSIRange_4) || \ |
| emilmont | 77:869cf507173a | 95 | ((RANGE) == RCC_MSIRange_5) || \ |
| emilmont | 77:869cf507173a | 96 | ((RANGE) == RCC_MSIRange_6)) |
| emilmont | 77:869cf507173a | 97 | |
| emilmont | 77:869cf507173a | 98 | /** |
| emilmont | 77:869cf507173a | 99 | * @} |
| emilmont | 77:869cf507173a | 100 | */ |
| emilmont | 77:869cf507173a | 101 | |
| emilmont | 77:869cf507173a | 102 | /** @defgroup RCC_PLL_Clock_Source |
| emilmont | 77:869cf507173a | 103 | * @{ |
| emilmont | 77:869cf507173a | 104 | */ |
| emilmont | 77:869cf507173a | 105 | |
| emilmont | 77:869cf507173a | 106 | #define RCC_PLLSource_HSI ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 107 | #define RCC_PLLSource_HSE ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 108 | |
| emilmont | 77:869cf507173a | 109 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ |
| emilmont | 77:869cf507173a | 110 | ((SOURCE) == RCC_PLLSource_HSE)) |
| emilmont | 77:869cf507173a | 111 | /** |
| emilmont | 77:869cf507173a | 112 | * @} |
| emilmont | 77:869cf507173a | 113 | */ |
| emilmont | 77:869cf507173a | 114 | |
| emilmont | 77:869cf507173a | 115 | /** @defgroup RCC_PLL_Multiplication_Factor |
| emilmont | 77:869cf507173a | 116 | * @{ |
| emilmont | 77:869cf507173a | 117 | */ |
| emilmont | 77:869cf507173a | 118 | |
| emilmont | 77:869cf507173a | 119 | #define RCC_PLLMul_3 ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 120 | #define RCC_PLLMul_4 ((uint8_t)0x04) |
| emilmont | 77:869cf507173a | 121 | #define RCC_PLLMul_6 ((uint8_t)0x08) |
| emilmont | 77:869cf507173a | 122 | #define RCC_PLLMul_8 ((uint8_t)0x0C) |
| emilmont | 77:869cf507173a | 123 | #define RCC_PLLMul_12 ((uint8_t)0x10) |
| emilmont | 77:869cf507173a | 124 | #define RCC_PLLMul_16 ((uint8_t)0x14) |
| emilmont | 77:869cf507173a | 125 | #define RCC_PLLMul_24 ((uint8_t)0x18) |
| emilmont | 77:869cf507173a | 126 | #define RCC_PLLMul_32 ((uint8_t)0x1C) |
| emilmont | 77:869cf507173a | 127 | #define RCC_PLLMul_48 ((uint8_t)0x20) |
| emilmont | 77:869cf507173a | 128 | |
| emilmont | 77:869cf507173a | 129 | |
| emilmont | 77:869cf507173a | 130 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \ |
| emilmont | 77:869cf507173a | 131 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \ |
| emilmont | 77:869cf507173a | 132 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \ |
| emilmont | 77:869cf507173a | 133 | ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \ |
| emilmont | 77:869cf507173a | 134 | ((MUL) == RCC_PLLMul_48)) |
| emilmont | 77:869cf507173a | 135 | /** |
| emilmont | 77:869cf507173a | 136 | * @} |
| emilmont | 77:869cf507173a | 137 | */ |
| emilmont | 77:869cf507173a | 138 | |
| emilmont | 77:869cf507173a | 139 | /** @defgroup RCC_PLL_Divider_Factor |
| emilmont | 77:869cf507173a | 140 | * @{ |
| emilmont | 77:869cf507173a | 141 | */ |
| emilmont | 77:869cf507173a | 142 | |
| emilmont | 77:869cf507173a | 143 | #define RCC_PLLDiv_2 ((uint8_t)0x40) |
| emilmont | 77:869cf507173a | 144 | #define RCC_PLLDiv_3 ((uint8_t)0x80) |
| emilmont | 77:869cf507173a | 145 | #define RCC_PLLDiv_4 ((uint8_t)0xC0) |
| emilmont | 77:869cf507173a | 146 | |
| emilmont | 77:869cf507173a | 147 | |
| emilmont | 77:869cf507173a | 148 | #define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \ |
| emilmont | 77:869cf507173a | 149 | ((DIV) == RCC_PLLDiv_4)) |
| emilmont | 77:869cf507173a | 150 | /** |
| emilmont | 77:869cf507173a | 151 | * @} |
| emilmont | 77:869cf507173a | 152 | */ |
| emilmont | 77:869cf507173a | 153 | |
| emilmont | 77:869cf507173a | 154 | /** @defgroup RCC_System_Clock_Source |
| emilmont | 77:869cf507173a | 155 | * @{ |
| emilmont | 77:869cf507173a | 156 | */ |
| emilmont | 77:869cf507173a | 157 | |
| emilmont | 77:869cf507173a | 158 | #define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI |
| emilmont | 77:869cf507173a | 159 | #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI |
| emilmont | 77:869cf507173a | 160 | #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE |
| emilmont | 77:869cf507173a | 161 | #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL |
| emilmont | 77:869cf507173a | 162 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \ |
| emilmont | 77:869cf507173a | 163 | ((SOURCE) == RCC_SYSCLKSource_HSI) || \ |
| emilmont | 77:869cf507173a | 164 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
| emilmont | 77:869cf507173a | 165 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
| emilmont | 77:869cf507173a | 166 | /** |
| emilmont | 77:869cf507173a | 167 | * @} |
| emilmont | 77:869cf507173a | 168 | */ |
| emilmont | 77:869cf507173a | 169 | |
| emilmont | 77:869cf507173a | 170 | /** @defgroup RCC_AHB_Clock_Source |
| emilmont | 77:869cf507173a | 171 | * @{ |
| emilmont | 77:869cf507173a | 172 | */ |
| emilmont | 77:869cf507173a | 173 | |
| emilmont | 77:869cf507173a | 174 | #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 |
| emilmont | 77:869cf507173a | 175 | #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 |
| emilmont | 77:869cf507173a | 176 | #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 |
| emilmont | 77:869cf507173a | 177 | #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 |
| emilmont | 77:869cf507173a | 178 | #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 |
| emilmont | 77:869cf507173a | 179 | #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 |
| emilmont | 77:869cf507173a | 180 | #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 |
| emilmont | 77:869cf507173a | 181 | #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 |
| emilmont | 77:869cf507173a | 182 | #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 |
| emilmont | 77:869cf507173a | 183 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ |
| emilmont | 77:869cf507173a | 184 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
| emilmont | 77:869cf507173a | 185 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
| emilmont | 77:869cf507173a | 186 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
| emilmont | 77:869cf507173a | 187 | ((HCLK) == RCC_SYSCLK_Div512)) |
| emilmont | 77:869cf507173a | 188 | /** |
| emilmont | 77:869cf507173a | 189 | * @} |
| emilmont | 77:869cf507173a | 190 | */ |
| emilmont | 77:869cf507173a | 191 | |
| emilmont | 77:869cf507173a | 192 | /** @defgroup RCC_APB1_APB2_Clock_Source |
| emilmont | 77:869cf507173a | 193 | * @{ |
| emilmont | 77:869cf507173a | 194 | */ |
| emilmont | 77:869cf507173a | 195 | |
| emilmont | 77:869cf507173a | 196 | #define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1 |
| emilmont | 77:869cf507173a | 197 | #define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2 |
| emilmont | 77:869cf507173a | 198 | #define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4 |
| emilmont | 77:869cf507173a | 199 | #define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8 |
| emilmont | 77:869cf507173a | 200 | #define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16 |
| emilmont | 77:869cf507173a | 201 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ |
| emilmont | 77:869cf507173a | 202 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
| emilmont | 77:869cf507173a | 203 | ((PCLK) == RCC_HCLK_Div16)) |
| emilmont | 77:869cf507173a | 204 | /** |
| emilmont | 77:869cf507173a | 205 | * @} |
| emilmont | 77:869cf507173a | 206 | */ |
| emilmont | 77:869cf507173a | 207 | |
| emilmont | 77:869cf507173a | 208 | |
| emilmont | 77:869cf507173a | 209 | /** @defgroup RCC_Interrupt_Source |
| emilmont | 77:869cf507173a | 210 | * @{ |
| emilmont | 77:869cf507173a | 211 | */ |
| emilmont | 77:869cf507173a | 212 | |
| emilmont | 77:869cf507173a | 213 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 214 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
| emilmont | 77:869cf507173a | 215 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
| emilmont | 77:869cf507173a | 216 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
| emilmont | 77:869cf507173a | 217 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
| emilmont | 77:869cf507173a | 218 | #define RCC_IT_MSIRDY ((uint8_t)0x20) |
| emilmont | 77:869cf507173a | 219 | #define RCC_IT_LSECSS ((uint8_t)0x40) |
| emilmont | 77:869cf507173a | 220 | #define RCC_IT_CSS ((uint8_t)0x80) |
| emilmont | 77:869cf507173a | 221 | |
| emilmont | 77:869cf507173a | 222 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) |
| emilmont | 77:869cf507173a | 223 | |
| emilmont | 77:869cf507173a | 224 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
| emilmont | 77:869cf507173a | 225 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
| emilmont | 77:869cf507173a | 226 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \ |
| emilmont | 77:869cf507173a | 227 | ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_LSECSS)) |
| emilmont | 77:869cf507173a | 228 | |
| emilmont | 77:869cf507173a | 229 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00)) |
| emilmont | 77:869cf507173a | 230 | |
| emilmont | 77:869cf507173a | 231 | /** |
| emilmont | 77:869cf507173a | 232 | * @} |
| emilmont | 77:869cf507173a | 233 | */ |
| emilmont | 77:869cf507173a | 234 | |
| emilmont | 77:869cf507173a | 235 | /** @defgroup RCC_LSE_Configuration |
| emilmont | 77:869cf507173a | 236 | * @{ |
| emilmont | 77:869cf507173a | 237 | */ |
| emilmont | 77:869cf507173a | 238 | |
| emilmont | 77:869cf507173a | 239 | #define RCC_LSE_OFF ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 240 | #define RCC_LSE_ON ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 241 | #define RCC_LSE_Bypass ((uint8_t)0x05) |
| emilmont | 77:869cf507173a | 242 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
| emilmont | 77:869cf507173a | 243 | ((LSE) == RCC_LSE_Bypass)) |
| emilmont | 77:869cf507173a | 244 | /** |
| emilmont | 77:869cf507173a | 245 | * @} |
| emilmont | 77:869cf507173a | 246 | */ |
| emilmont | 77:869cf507173a | 247 | |
| emilmont | 77:869cf507173a | 248 | /** @defgroup RCC_RTC_Clock_Source |
| emilmont | 77:869cf507173a | 249 | * @{ |
| emilmont | 77:869cf507173a | 250 | */ |
| emilmont | 77:869cf507173a | 251 | |
| emilmont | 77:869cf507173a | 252 | #define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE |
| emilmont | 77:869cf507173a | 253 | #define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI |
| emilmont | 77:869cf507173a | 254 | #define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE |
| emilmont | 77:869cf507173a | 255 | #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0) |
| emilmont | 77:869cf507173a | 256 | #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1) |
| emilmont | 77:869cf507173a | 257 | #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE) |
| emilmont | 77:869cf507173a | 258 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ |
| emilmont | 77:869cf507173a | 259 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
| emilmont | 77:869cf507173a | 260 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ |
| emilmont | 77:869cf507173a | 261 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ |
| emilmont | 77:869cf507173a | 262 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ |
| emilmont | 77:869cf507173a | 263 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div16)) |
| emilmont | 77:869cf507173a | 264 | /** |
| emilmont | 77:869cf507173a | 265 | * @} |
| emilmont | 77:869cf507173a | 266 | */ |
| emilmont | 77:869cf507173a | 267 | |
| emilmont | 77:869cf507173a | 268 | /** @defgroup RCC_AHB_Peripherals |
| emilmont | 77:869cf507173a | 269 | * @{ |
| emilmont | 77:869cf507173a | 270 | */ |
| emilmont | 77:869cf507173a | 271 | |
| emilmont | 77:869cf507173a | 272 | #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN |
| emilmont | 77:869cf507173a | 273 | #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN |
| emilmont | 77:869cf507173a | 274 | #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN |
| emilmont | 77:869cf507173a | 275 | #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN |
| emilmont | 77:869cf507173a | 276 | #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN |
| emilmont | 77:869cf507173a | 277 | #define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN |
| emilmont | 77:869cf507173a | 278 | #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN |
| emilmont | 77:869cf507173a | 279 | #define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN |
| emilmont | 77:869cf507173a | 280 | #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN |
| emilmont | 77:869cf507173a | 281 | #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN |
| emilmont | 77:869cf507173a | 282 | #define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN |
| emilmont | 77:869cf507173a | 283 | #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN |
| emilmont | 77:869cf507173a | 284 | #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN |
| emilmont | 77:869cf507173a | 285 | #define RCC_AHBPeriph_AES RCC_AHBENR_AESEN |
| emilmont | 77:869cf507173a | 286 | #define RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN |
| emilmont | 77:869cf507173a | 287 | |
| emilmont | 77:869cf507173a | 288 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00)) |
| emilmont | 77:869cf507173a | 289 | #define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00)) |
| emilmont | 77:869cf507173a | 290 | |
| emilmont | 77:869cf507173a | 291 | /** |
| emilmont | 77:869cf507173a | 292 | * @} |
| emilmont | 77:869cf507173a | 293 | */ |
| emilmont | 77:869cf507173a | 294 | |
| emilmont | 77:869cf507173a | 295 | /** @defgroup RCC_APB2_Peripherals |
| emilmont | 77:869cf507173a | 296 | * @{ |
| emilmont | 77:869cf507173a | 297 | */ |
| emilmont | 77:869cf507173a | 298 | |
| emilmont | 77:869cf507173a | 299 | #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN |
| emilmont | 77:869cf507173a | 300 | #define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN |
| emilmont | 77:869cf507173a | 301 | #define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN |
| emilmont | 77:869cf507173a | 302 | #define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN |
| emilmont | 77:869cf507173a | 303 | #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN |
| emilmont | 77:869cf507173a | 304 | #define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN |
| emilmont | 77:869cf507173a | 305 | #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN |
| emilmont | 77:869cf507173a | 306 | #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN |
| emilmont | 77:869cf507173a | 307 | |
| emilmont | 77:869cf507173a | 308 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00)) |
| emilmont | 77:869cf507173a | 309 | /** |
| emilmont | 77:869cf507173a | 310 | * @} |
| emilmont | 77:869cf507173a | 311 | */ |
| emilmont | 77:869cf507173a | 312 | |
| emilmont | 77:869cf507173a | 313 | /** @defgroup RCC_APB1_Peripherals |
| emilmont | 77:869cf507173a | 314 | * @{ |
| emilmont | 77:869cf507173a | 315 | */ |
| emilmont | 77:869cf507173a | 316 | |
| emilmont | 77:869cf507173a | 317 | #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN |
| emilmont | 77:869cf507173a | 318 | #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN |
| emilmont | 77:869cf507173a | 319 | #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN |
| emilmont | 77:869cf507173a | 320 | #define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN |
| emilmont | 77:869cf507173a | 321 | #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN |
| emilmont | 77:869cf507173a | 322 | #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN |
| emilmont | 77:869cf507173a | 323 | #define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN |
| emilmont | 77:869cf507173a | 324 | #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN |
| emilmont | 77:869cf507173a | 325 | #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN |
| emilmont | 77:869cf507173a | 326 | #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN |
| emilmont | 77:869cf507173a | 327 | #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN |
| emilmont | 77:869cf507173a | 328 | #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN |
| emilmont | 77:869cf507173a | 329 | #define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN |
| emilmont | 77:869cf507173a | 330 | #define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN |
| emilmont | 77:869cf507173a | 331 | #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN |
| emilmont | 77:869cf507173a | 332 | #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN |
| emilmont | 77:869cf507173a | 333 | #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN |
| emilmont | 77:869cf507173a | 334 | #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN |
| emilmont | 77:869cf507173a | 335 | #define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN |
| emilmont | 77:869cf507173a | 336 | #define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN |
| emilmont | 77:869cf507173a | 337 | |
| emilmont | 77:869cf507173a | 338 | |
| emilmont | 77:869cf507173a | 339 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00)) |
| emilmont | 77:869cf507173a | 340 | /** |
| emilmont | 77:869cf507173a | 341 | * @} |
| emilmont | 77:869cf507173a | 342 | */ |
| emilmont | 77:869cf507173a | 343 | |
| emilmont | 77:869cf507173a | 344 | /** @defgroup RCC_MCO_Clock_Source |
| emilmont | 77:869cf507173a | 345 | * @{ |
| emilmont | 77:869cf507173a | 346 | */ |
| emilmont | 77:869cf507173a | 347 | |
| emilmont | 77:869cf507173a | 348 | #define RCC_MCOSource_NoClock ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 349 | #define RCC_MCOSource_SYSCLK ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 350 | #define RCC_MCOSource_HSI ((uint8_t)0x02) |
| emilmont | 77:869cf507173a | 351 | #define RCC_MCOSource_MSI ((uint8_t)0x03) |
| emilmont | 77:869cf507173a | 352 | #define RCC_MCOSource_HSE ((uint8_t)0x04) |
| emilmont | 77:869cf507173a | 353 | #define RCC_MCOSource_PLLCLK ((uint8_t)0x05) |
| emilmont | 77:869cf507173a | 354 | #define RCC_MCOSource_LSI ((uint8_t)0x06) |
| emilmont | 77:869cf507173a | 355 | #define RCC_MCOSource_LSE ((uint8_t)0x07) |
| emilmont | 77:869cf507173a | 356 | |
| emilmont | 77:869cf507173a | 357 | #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \ |
| emilmont | 77:869cf507173a | 358 | ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \ |
| emilmont | 77:869cf507173a | 359 | ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \ |
| emilmont | 77:869cf507173a | 360 | ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE)) |
| emilmont | 77:869cf507173a | 361 | /** |
| emilmont | 77:869cf507173a | 362 | * @} |
| emilmont | 77:869cf507173a | 363 | */ |
| emilmont | 77:869cf507173a | 364 | |
| emilmont | 77:869cf507173a | 365 | /** @defgroup RCC_MCO_Output_Divider |
| emilmont | 77:869cf507173a | 366 | * @{ |
| emilmont | 77:869cf507173a | 367 | */ |
| emilmont | 77:869cf507173a | 368 | |
| emilmont | 77:869cf507173a | 369 | #define RCC_MCODiv_1 ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 370 | #define RCC_MCODiv_2 ((uint8_t)0x10) |
| emilmont | 77:869cf507173a | 371 | #define RCC_MCODiv_4 ((uint8_t)0x20) |
| emilmont | 77:869cf507173a | 372 | #define RCC_MCODiv_8 ((uint8_t)0x30) |
| emilmont | 77:869cf507173a | 373 | #define RCC_MCODiv_16 ((uint8_t)0x40) |
| emilmont | 77:869cf507173a | 374 | |
| emilmont | 77:869cf507173a | 375 | #define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \ |
| emilmont | 77:869cf507173a | 376 | ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \ |
| emilmont | 77:869cf507173a | 377 | ((DIV) == RCC_MCODiv_16)) |
| emilmont | 77:869cf507173a | 378 | /** |
| emilmont | 77:869cf507173a | 379 | * @} |
| emilmont | 77:869cf507173a | 380 | */ |
| emilmont | 77:869cf507173a | 381 | |
| emilmont | 77:869cf507173a | 382 | /** @defgroup RCC_Flag |
| emilmont | 77:869cf507173a | 383 | * @{ |
| emilmont | 77:869cf507173a | 384 | */ |
| emilmont | 77:869cf507173a | 385 | |
| emilmont | 77:869cf507173a | 386 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21) |
| emilmont | 77:869cf507173a | 387 | #define RCC_FLAG_MSIRDY ((uint8_t)0x29) |
| emilmont | 77:869cf507173a | 388 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) |
| emilmont | 77:869cf507173a | 389 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
| emilmont | 77:869cf507173a | 390 | #define RCC_FLAG_LSERDY ((uint8_t)0x49) |
| emilmont | 77:869cf507173a | 391 | #define RCC_FLAG_LSECSS ((uint8_t)0x4A) |
| emilmont | 77:869cf507173a | 392 | #define RCC_FLAG_LSIRDY ((uint8_t)0x41) |
| emilmont | 77:869cf507173a | 393 | #define RCC_FLAG_OBLRST ((uint8_t)0x59) |
| emilmont | 77:869cf507173a | 394 | #define RCC_FLAG_PINRST ((uint8_t)0x5A) |
| emilmont | 77:869cf507173a | 395 | #define RCC_FLAG_PORRST ((uint8_t)0x5B) |
| emilmont | 77:869cf507173a | 396 | #define RCC_FLAG_SFTRST ((uint8_t)0x5C) |
| emilmont | 77:869cf507173a | 397 | #define RCC_FLAG_IWDGRST ((uint8_t)0x5D) |
| emilmont | 77:869cf507173a | 398 | #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) |
| emilmont | 77:869cf507173a | 399 | #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) |
| emilmont | 77:869cf507173a | 400 | |
| emilmont | 77:869cf507173a | 401 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| emilmont | 77:869cf507173a | 402 | ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \ |
| emilmont | 77:869cf507173a | 403 | ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \ |
| emilmont | 77:869cf507173a | 404 | ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ |
| emilmont | 77:869cf507173a | 405 | ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ |
| emilmont | 77:869cf507173a | 406 | ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ |
| emilmont | 77:869cf507173a | 407 | ((FLAG) == RCC_FLAG_OBLRST)|| ((FLAG) == RCC_FLAG_LSECSS)) |
| emilmont | 77:869cf507173a | 408 | |
| emilmont | 77:869cf507173a | 409 | #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
| emilmont | 77:869cf507173a | 410 | #define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F) |
| emilmont | 77:869cf507173a | 411 | |
| emilmont | 77:869cf507173a | 412 | /** |
| emilmont | 77:869cf507173a | 413 | * @} |
| emilmont | 77:869cf507173a | 414 | */ |
| emilmont | 77:869cf507173a | 415 | |
| emilmont | 77:869cf507173a | 416 | /** |
| emilmont | 77:869cf507173a | 417 | * @} |
| emilmont | 77:869cf507173a | 418 | */ |
| emilmont | 77:869cf507173a | 419 | |
| emilmont | 77:869cf507173a | 420 | /* Exported macro ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 421 | /* Exported functions ------------------------------------------------------- */ |
| emilmont | 77:869cf507173a | 422 | |
| emilmont | 77:869cf507173a | 423 | /* Function used to set the RCC clock configuration to the default reset state */ |
| emilmont | 77:869cf507173a | 424 | void RCC_DeInit(void); |
| emilmont | 77:869cf507173a | 425 | |
| emilmont | 77:869cf507173a | 426 | /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ |
| emilmont | 77:869cf507173a | 427 | void RCC_HSEConfig(uint8_t RCC_HSE); |
| emilmont | 77:869cf507173a | 428 | ErrorStatus RCC_WaitForHSEStartUp(void); |
| emilmont | 77:869cf507173a | 429 | void RCC_MSIRangeConfig(uint32_t RCC_MSIRange); |
| emilmont | 77:869cf507173a | 430 | void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue); |
| emilmont | 77:869cf507173a | 431 | void RCC_MSICmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 432 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); |
| emilmont | 77:869cf507173a | 433 | void RCC_HSICmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 434 | void RCC_LSEConfig(uint8_t RCC_LSE); |
| emilmont | 77:869cf507173a | 435 | void RCC_LSICmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 436 | void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv); |
| emilmont | 77:869cf507173a | 437 | void RCC_PLLCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 438 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 439 | void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 440 | void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv); |
| emilmont | 77:869cf507173a | 441 | |
| emilmont | 77:869cf507173a | 442 | /* System, AHB and APB busses clocks configuration functions ******************/ |
| emilmont | 77:869cf507173a | 443 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); |
| emilmont | 77:869cf507173a | 444 | uint8_t RCC_GetSYSCLKSource(void); |
| emilmont | 77:869cf507173a | 445 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK); |
| emilmont | 77:869cf507173a | 446 | void RCC_PCLK1Config(uint32_t RCC_HCLK); |
| emilmont | 77:869cf507173a | 447 | void RCC_PCLK2Config(uint32_t RCC_HCLK); |
| emilmont | 77:869cf507173a | 448 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); |
| emilmont | 77:869cf507173a | 449 | |
| emilmont | 77:869cf507173a | 450 | /* Peripheral clocks configuration functions **********************************/ |
| emilmont | 77:869cf507173a | 451 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); |
| emilmont | 77:869cf507173a | 452 | void RCC_RTCCLKCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 453 | void RCC_RTCResetCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 454 | |
| emilmont | 77:869cf507173a | 455 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 456 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 457 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 458 | |
| emilmont | 77:869cf507173a | 459 | void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 460 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 461 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 462 | |
| emilmont | 77:869cf507173a | 463 | void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 464 | void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 465 | void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 466 | |
| emilmont | 77:869cf507173a | 467 | /* Interrupts and flags management functions **********************************/ |
| emilmont | 77:869cf507173a | 468 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 469 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
| emilmont | 77:869cf507173a | 470 | void RCC_ClearFlag(void); |
| emilmont | 77:869cf507173a | 471 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
| emilmont | 77:869cf507173a | 472 | void RCC_ClearITPendingBit(uint8_t RCC_IT); |
| emilmont | 77:869cf507173a | 473 | |
| emilmont | 77:869cf507173a | 474 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 475 | } |
| emilmont | 77:869cf507173a | 476 | #endif |
| emilmont | 77:869cf507173a | 477 | |
| emilmont | 77:869cf507173a | 478 | #endif /* __STM32L1xx_RCC_H */ |
| emilmont | 77:869cf507173a | 479 | |
| emilmont | 77:869cf507173a | 480 | /** |
| emilmont | 77:869cf507173a | 481 | * @} |
| emilmont | 77:869cf507173a | 482 | */ |
| emilmont | 77:869cf507173a | 483 | |
| emilmont | 77:869cf507173a | 484 | /** |
| emilmont | 77:869cf507173a | 485 | * @} |
| emilmont | 77:869cf507173a | 486 | */ |
| emilmont | 77:869cf507173a | 487 | |
| emilmont | 77:869cf507173a | 488 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |