version_2.0

Dependents:   cc3000_ping_demo_try_2

Fork of mbed by mbed official

Committer:
emilmont
Date:
Fri Feb 14 14:36:43 2014 +0000
Revision:
77:869cf507173a
Child:
81:7d30d6019079
Release 77 of the mbed library

Main changes:
* Add target NUCLEO_F030R8
* Add target NUCLEO_F401RE
* Add target NUCLEO_F103RB
* Add target NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32l1xx_fsmc.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 31-January-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the FSMC firmware
emilmont 77:869cf507173a 8 * library.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
emilmont 77:869cf507173a 12 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
emilmont 77:869cf507173a 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
emilmont 77:869cf507173a 15 * You may not use this file except in compliance with the License.
emilmont 77:869cf507173a 16 * You may obtain a copy of the License at:
emilmont 77:869cf507173a 17 *
emilmont 77:869cf507173a 18 * http://www.st.com/software_license_agreement_liberty_v2
emilmont 77:869cf507173a 19 *
emilmont 77:869cf507173a 20 * Unless required by applicable law or agreed to in writing, software
emilmont 77:869cf507173a 21 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 77:869cf507173a 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 77:869cf507173a 23 * See the License for the specific language governing permissions and
emilmont 77:869cf507173a 24 * limitations under the License.
emilmont 77:869cf507173a 25 *
emilmont 77:869cf507173a 26 ******************************************************************************
emilmont 77:869cf507173a 27 */
emilmont 77:869cf507173a 28
emilmont 77:869cf507173a 29 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 30 #ifndef __STM32L1xx_FSMC_H
emilmont 77:869cf507173a 31 #define __STM32L1xx_FSMC_H
emilmont 77:869cf507173a 32
emilmont 77:869cf507173a 33 #ifdef __cplusplus
emilmont 77:869cf507173a 34 extern "C" {
emilmont 77:869cf507173a 35 #endif
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 38 #include "stm32l1xx.h"
emilmont 77:869cf507173a 39
emilmont 77:869cf507173a 40 /** @addtogroup STM32L1xx_StdPeriph_Driver
emilmont 77:869cf507173a 41 * @{
emilmont 77:869cf507173a 42 */
emilmont 77:869cf507173a 43
emilmont 77:869cf507173a 44 /** @addtogroup FSMC
emilmont 77:869cf507173a 45 * @{
emilmont 77:869cf507173a 46 */
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50 /**
emilmont 77:869cf507173a 51 * @brief Timing parameters For NOR/SRAM Banks
emilmont 77:869cf507173a 52 */
emilmont 77:869cf507173a 53
emilmont 77:869cf507173a 54 typedef struct
emilmont 77:869cf507173a 55 {
emilmont 77:869cf507173a 56 uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont 77:869cf507173a 57 the duration of the address setup time.
emilmont 77:869cf507173a 58 This parameter can be a value between 0 and 0xF.
emilmont 77:869cf507173a 59 @note It is not used with synchronous NOR Flash memories. */
emilmont 77:869cf507173a 60
emilmont 77:869cf507173a 61 uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
emilmont 77:869cf507173a 62 the duration of the address hold time.
emilmont 77:869cf507173a 63 This parameter can be a value between 0 and 0xF.
emilmont 77:869cf507173a 64 @note It is not used with synchronous NOR Flash memories.*/
emilmont 77:869cf507173a 65
emilmont 77:869cf507173a 66 uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont 77:869cf507173a 67 the duration of the data setup time.
emilmont 77:869cf507173a 68 This parameter can be a value between 0 and 0xFF.
emilmont 77:869cf507173a 69 @note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
emilmont 77:869cf507173a 70
emilmont 77:869cf507173a 71 uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
emilmont 77:869cf507173a 72 the duration of the bus turnaround.
emilmont 77:869cf507173a 73 This parameter can be a value between 0 and 0xF.
emilmont 77:869cf507173a 74 @note It is only used for multiplexed NOR Flash memories. */
emilmont 77:869cf507173a 75
emilmont 77:869cf507173a 76 uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
emilmont 77:869cf507173a 77 This parameter can be a value between 1 and 0xF.
emilmont 77:869cf507173a 78 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
emilmont 77:869cf507173a 79
emilmont 77:869cf507173a 80 uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
emilmont 77:869cf507173a 81 to the memory before getting the first data.
emilmont 77:869cf507173a 82 The parameter value depends on the memory type as shown below:
emilmont 77:869cf507173a 83 - It must be set to 0 in case of a CRAM
emilmont 77:869cf507173a 84 - It is don't care in asynchronous NOR, SRAM or ROM accesses
emilmont 77:869cf507173a 85 - It may assume a value between 0 and 0xF in NOR Flash memories
emilmont 77:869cf507173a 86 with synchronous burst mode enable */
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
emilmont 77:869cf507173a 89 This parameter can be a value of @ref FSMC_Access_Mode */
emilmont 77:869cf507173a 90 }FSMC_NORSRAMTimingInitTypeDef;
emilmont 77:869cf507173a 91
emilmont 77:869cf507173a 92 /**
emilmont 77:869cf507173a 93 * @brief FSMC NOR/SRAM Init structure definition
emilmont 77:869cf507173a 94 */
emilmont 77:869cf507173a 95
emilmont 77:869cf507173a 96 typedef struct
emilmont 77:869cf507173a 97 {
emilmont 77:869cf507173a 98 uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
emilmont 77:869cf507173a 99 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
emilmont 77:869cf507173a 100
emilmont 77:869cf507173a 101 uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
emilmont 77:869cf507173a 102 multiplexed on the databus or not.
emilmont 77:869cf507173a 103 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
emilmont 77:869cf507173a 104
emilmont 77:869cf507173a 105 uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
emilmont 77:869cf507173a 106 the corresponding memory bank.
emilmont 77:869cf507173a 107 This parameter can be a value of @ref FSMC_Memory_Type */
emilmont 77:869cf507173a 108
emilmont 77:869cf507173a 109 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont 77:869cf507173a 110 This parameter can be a value of @ref FSMC_Data_Width */
emilmont 77:869cf507173a 111
emilmont 77:869cf507173a 112 uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
emilmont 77:869cf507173a 113 valid only with synchronous burst Flash memories.
emilmont 77:869cf507173a 114 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
emilmont 77:869cf507173a 115
emilmont 77:869cf507173a 116 uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
emilmont 77:869cf507173a 117 valid only with asynchronous Flash memories.
emilmont 77:869cf507173a 118 This parameter can be a value of @ref FSMC_AsynchronousWait */
emilmont 77:869cf507173a 119
emilmont 77:869cf507173a 120 uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
emilmont 77:869cf507173a 121 the Flash memory in burst mode.
emilmont 77:869cf507173a 122 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
emilmont 77:869cf507173a 123
emilmont 77:869cf507173a 124 uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
emilmont 77:869cf507173a 125 memory, valid only when accessing Flash memories in burst mode.
emilmont 77:869cf507173a 126 This parameter can be a value of @ref FSMC_Wrap_Mode */
emilmont 77:869cf507173a 127
emilmont 77:869cf507173a 128 uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
emilmont 77:869cf507173a 129 clock cycle before the wait state or during the wait state,
emilmont 77:869cf507173a 130 valid only when accessing memories in burst mode.
emilmont 77:869cf507173a 131 This parameter can be a value of @ref FSMC_Wait_Timing */
emilmont 77:869cf507173a 132
emilmont 77:869cf507173a 133 uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
emilmont 77:869cf507173a 134 This parameter can be a value of @ref FSMC_Write_Operation */
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
emilmont 77:869cf507173a 137 signal, valid for Flash memory access in burst mode.
emilmont 77:869cf507173a 138 This parameter can be a value of @ref FSMC_Wait_Signal */
emilmont 77:869cf507173a 139
emilmont 77:869cf507173a 140 uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
emilmont 77:869cf507173a 141 This parameter can be a value of @ref FSMC_Extended_Mode */
emilmont 77:869cf507173a 142
emilmont 77:869cf507173a 143 uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
emilmont 77:869cf507173a 144 This parameter can be a value of @ref FSMC_Write_Burst */
emilmont 77:869cf507173a 145
emilmont 77:869cf507173a 146 FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
emilmont 77:869cf507173a 147
emilmont 77:869cf507173a 148 FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
emilmont 77:869cf507173a 149 }FSMC_NORSRAMInitTypeDef;
emilmont 77:869cf507173a 150
emilmont 77:869cf507173a 151 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 152
emilmont 77:869cf507173a 153 /** @defgroup FSMC_Exported_Constants
emilmont 77:869cf507173a 154 * @{
emilmont 77:869cf507173a 155 */
emilmont 77:869cf507173a 156
emilmont 77:869cf507173a 157 /** @defgroup FSMC_NORSRAM_Bank
emilmont 77:869cf507173a 158 * @{
emilmont 77:869cf507173a 159 */
emilmont 77:869cf507173a 160 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
emilmont 77:869cf507173a 161 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 162 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 163 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
emilmont 77:869cf507173a 164
emilmont 77:869cf507173a 165 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
emilmont 77:869cf507173a 166 ((BANK) == FSMC_Bank1_NORSRAM2) || \
emilmont 77:869cf507173a 167 ((BANK) == FSMC_Bank1_NORSRAM3) || \
emilmont 77:869cf507173a 168 ((BANK) == FSMC_Bank1_NORSRAM4))
emilmont 77:869cf507173a 169 /**
emilmont 77:869cf507173a 170 * @}
emilmont 77:869cf507173a 171 */
emilmont 77:869cf507173a 172
emilmont 77:869cf507173a 173 /** @defgroup NOR_SRAM_Controller
emilmont 77:869cf507173a 174 * @{
emilmont 77:869cf507173a 175 */
emilmont 77:869cf507173a 176
emilmont 77:869cf507173a 177 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
emilmont 77:869cf507173a 178 * @{
emilmont 77:869cf507173a 179 */
emilmont 77:869cf507173a 180
emilmont 77:869cf507173a 181 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 182 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
emilmont 77:869cf507173a 183 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
emilmont 77:869cf507173a 184 ((MUX) == FSMC_DataAddressMux_Enable))
emilmont 77:869cf507173a 185
emilmont 77:869cf507173a 186 /**
emilmont 77:869cf507173a 187 * @}
emilmont 77:869cf507173a 188 */
emilmont 77:869cf507173a 189
emilmont 77:869cf507173a 190 /** @defgroup FSMC_Memory_Type
emilmont 77:869cf507173a 191 * @{
emilmont 77:869cf507173a 192 */
emilmont 77:869cf507173a 193
emilmont 77:869cf507173a 194 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
emilmont 77:869cf507173a 195 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
emilmont 77:869cf507173a 196 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
emilmont 77:869cf507173a 197 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
emilmont 77:869cf507173a 198 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
emilmont 77:869cf507173a 199 ((MEMORY) == FSMC_MemoryType_NOR))
emilmont 77:869cf507173a 200
emilmont 77:869cf507173a 201 /**
emilmont 77:869cf507173a 202 * @}
emilmont 77:869cf507173a 203 */
emilmont 77:869cf507173a 204
emilmont 77:869cf507173a 205 /** @defgroup FSMC_Data_Width
emilmont 77:869cf507173a 206 * @{
emilmont 77:869cf507173a 207 */
emilmont 77:869cf507173a 208
emilmont 77:869cf507173a 209 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
emilmont 77:869cf507173a 210 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
emilmont 77:869cf507173a 211 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
emilmont 77:869cf507173a 212 ((WIDTH) == FSMC_MemoryDataWidth_16b))
emilmont 77:869cf507173a 213
emilmont 77:869cf507173a 214 /**
emilmont 77:869cf507173a 215 * @}
emilmont 77:869cf507173a 216 */
emilmont 77:869cf507173a 217
emilmont 77:869cf507173a 218 /** @defgroup FSMC_Burst_Access_Mode
emilmont 77:869cf507173a 219 * @{
emilmont 77:869cf507173a 220 */
emilmont 77:869cf507173a 221
emilmont 77:869cf507173a 222 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 223 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
emilmont 77:869cf507173a 224 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
emilmont 77:869cf507173a 225 ((STATE) == FSMC_BurstAccessMode_Enable))
emilmont 77:869cf507173a 226 /**
emilmont 77:869cf507173a 227 * @}
emilmont 77:869cf507173a 228 */
emilmont 77:869cf507173a 229
emilmont 77:869cf507173a 230 /** @defgroup FSMC_AsynchronousWait
emilmont 77:869cf507173a 231 * @{
emilmont 77:869cf507173a 232 */
emilmont 77:869cf507173a 233 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 234 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
emilmont 77:869cf507173a 235 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
emilmont 77:869cf507173a 236 ((STATE) == FSMC_AsynchronousWait_Enable))
emilmont 77:869cf507173a 237
emilmont 77:869cf507173a 238 /**
emilmont 77:869cf507173a 239 * @}
emilmont 77:869cf507173a 240 */
emilmont 77:869cf507173a 241
emilmont 77:869cf507173a 242 /** @defgroup FSMC_Wait_Signal_Polarity
emilmont 77:869cf507173a 243 * @{
emilmont 77:869cf507173a 244 */
emilmont 77:869cf507173a 245
emilmont 77:869cf507173a 246 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
emilmont 77:869cf507173a 247 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
emilmont 77:869cf507173a 248 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
emilmont 77:869cf507173a 249 ((POLARITY) == FSMC_WaitSignalPolarity_High))
emilmont 77:869cf507173a 250
emilmont 77:869cf507173a 251 /**
emilmont 77:869cf507173a 252 * @}
emilmont 77:869cf507173a 253 */
emilmont 77:869cf507173a 254
emilmont 77:869cf507173a 255 /** @defgroup FSMC_Wrap_Mode
emilmont 77:869cf507173a 256 * @{
emilmont 77:869cf507173a 257 */
emilmont 77:869cf507173a 258
emilmont 77:869cf507173a 259 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 260 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
emilmont 77:869cf507173a 261 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
emilmont 77:869cf507173a 262 ((MODE) == FSMC_WrapMode_Enable))
emilmont 77:869cf507173a 263
emilmont 77:869cf507173a 264 /**
emilmont 77:869cf507173a 265 * @}
emilmont 77:869cf507173a 266 */
emilmont 77:869cf507173a 267
emilmont 77:869cf507173a 268 /** @defgroup FSMC_Wait_Timing
emilmont 77:869cf507173a 269 * @{
emilmont 77:869cf507173a 270 */
emilmont 77:869cf507173a 271
emilmont 77:869cf507173a 272 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
emilmont 77:869cf507173a 273 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
emilmont 77:869cf507173a 274 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
emilmont 77:869cf507173a 275 ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
emilmont 77:869cf507173a 276
emilmont 77:869cf507173a 277 /**
emilmont 77:869cf507173a 278 * @}
emilmont 77:869cf507173a 279 */
emilmont 77:869cf507173a 280
emilmont 77:869cf507173a 281 /** @defgroup FSMC_Write_Operation
emilmont 77:869cf507173a 282 * @{
emilmont 77:869cf507173a 283 */
emilmont 77:869cf507173a 284
emilmont 77:869cf507173a 285 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 286 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
emilmont 77:869cf507173a 287 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
emilmont 77:869cf507173a 288 ((OPERATION) == FSMC_WriteOperation_Enable))
emilmont 77:869cf507173a 289
emilmont 77:869cf507173a 290 /**
emilmont 77:869cf507173a 291 * @}
emilmont 77:869cf507173a 292 */
emilmont 77:869cf507173a 293
emilmont 77:869cf507173a 294 /** @defgroup FSMC_Wait_Signal
emilmont 77:869cf507173a 295 * @{
emilmont 77:869cf507173a 296 */
emilmont 77:869cf507173a 297
emilmont 77:869cf507173a 298 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 299 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
emilmont 77:869cf507173a 300 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
emilmont 77:869cf507173a 301 ((SIGNAL) == FSMC_WaitSignal_Enable))
emilmont 77:869cf507173a 302 /**
emilmont 77:869cf507173a 303 * @}
emilmont 77:869cf507173a 304 */
emilmont 77:869cf507173a 305
emilmont 77:869cf507173a 306 /** @defgroup FSMC_Extended_Mode
emilmont 77:869cf507173a 307 * @{
emilmont 77:869cf507173a 308 */
emilmont 77:869cf507173a 309
emilmont 77:869cf507173a 310 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 311 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
emilmont 77:869cf507173a 312
emilmont 77:869cf507173a 313 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
emilmont 77:869cf507173a 314 ((MODE) == FSMC_ExtendedMode_Enable))
emilmont 77:869cf507173a 315
emilmont 77:869cf507173a 316 /**
emilmont 77:869cf507173a 317 * @}
emilmont 77:869cf507173a 318 */
emilmont 77:869cf507173a 319
emilmont 77:869cf507173a 320 /** @defgroup FSMC_Write_Burst
emilmont 77:869cf507173a 321 * @{
emilmont 77:869cf507173a 322 */
emilmont 77:869cf507173a 323
emilmont 77:869cf507173a 324 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 325 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
emilmont 77:869cf507173a 326 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
emilmont 77:869cf507173a 327 ((BURST) == FSMC_WriteBurst_Enable))
emilmont 77:869cf507173a 328 /**
emilmont 77:869cf507173a 329 * @}
emilmont 77:869cf507173a 330 */
emilmont 77:869cf507173a 331
emilmont 77:869cf507173a 332 /** @defgroup FSMC_Address_Setup_Time
emilmont 77:869cf507173a 333 * @{
emilmont 77:869cf507173a 334 */
emilmont 77:869cf507173a 335
emilmont 77:869cf507173a 336 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
emilmont 77:869cf507173a 337
emilmont 77:869cf507173a 338 /**
emilmont 77:869cf507173a 339 * @}
emilmont 77:869cf507173a 340 */
emilmont 77:869cf507173a 341
emilmont 77:869cf507173a 342 /** @defgroup FSMC_Address_Hold_Time
emilmont 77:869cf507173a 343 * @{
emilmont 77:869cf507173a 344 */
emilmont 77:869cf507173a 345
emilmont 77:869cf507173a 346 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
emilmont 77:869cf507173a 347
emilmont 77:869cf507173a 348 /**
emilmont 77:869cf507173a 349 * @}
emilmont 77:869cf507173a 350 */
emilmont 77:869cf507173a 351
emilmont 77:869cf507173a 352 /** @defgroup FSMC_Data_Setup_Time
emilmont 77:869cf507173a 353 * @{
emilmont 77:869cf507173a 354 */
emilmont 77:869cf507173a 355
emilmont 77:869cf507173a 356 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
emilmont 77:869cf507173a 357
emilmont 77:869cf507173a 358 /**
emilmont 77:869cf507173a 359 * @}
emilmont 77:869cf507173a 360 */
emilmont 77:869cf507173a 361
emilmont 77:869cf507173a 362 /** @defgroup FSMC_Bus_Turn_around_Duration
emilmont 77:869cf507173a 363 * @{
emilmont 77:869cf507173a 364 */
emilmont 77:869cf507173a 365
emilmont 77:869cf507173a 366 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
emilmont 77:869cf507173a 367
emilmont 77:869cf507173a 368 /**
emilmont 77:869cf507173a 369 * @}
emilmont 77:869cf507173a 370 */
emilmont 77:869cf507173a 371
emilmont 77:869cf507173a 372 /** @defgroup FSMC_CLK_Division
emilmont 77:869cf507173a 373 * @{
emilmont 77:869cf507173a 374 */
emilmont 77:869cf507173a 375
emilmont 77:869cf507173a 376 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
emilmont 77:869cf507173a 377
emilmont 77:869cf507173a 378 /**
emilmont 77:869cf507173a 379 * @}
emilmont 77:869cf507173a 380 */
emilmont 77:869cf507173a 381
emilmont 77:869cf507173a 382 /** @defgroup FSMC_Data_Latency
emilmont 77:869cf507173a 383 * @{
emilmont 77:869cf507173a 384 */
emilmont 77:869cf507173a 385
emilmont 77:869cf507173a 386 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
emilmont 77:869cf507173a 387
emilmont 77:869cf507173a 388 /**
emilmont 77:869cf507173a 389 * @}
emilmont 77:869cf507173a 390 */
emilmont 77:869cf507173a 391
emilmont 77:869cf507173a 392 /** @defgroup FSMC_Access_Mode
emilmont 77:869cf507173a 393 * @{
emilmont 77:869cf507173a 394 */
emilmont 77:869cf507173a 395
emilmont 77:869cf507173a 396 #define FSMC_AccessMode_A ((uint32_t)0x00000000)
emilmont 77:869cf507173a 397 #define FSMC_AccessMode_B ((uint32_t)0x10000000)
emilmont 77:869cf507173a 398 #define FSMC_AccessMode_C ((uint32_t)0x20000000)
emilmont 77:869cf507173a 399 #define FSMC_AccessMode_D ((uint32_t)0x30000000)
emilmont 77:869cf507173a 400 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
emilmont 77:869cf507173a 401 ((MODE) == FSMC_AccessMode_B) || \
emilmont 77:869cf507173a 402 ((MODE) == FSMC_AccessMode_C) || \
emilmont 77:869cf507173a 403 ((MODE) == FSMC_AccessMode_D))
emilmont 77:869cf507173a 404
emilmont 77:869cf507173a 405 /**
emilmont 77:869cf507173a 406 * @}
emilmont 77:869cf507173a 407 */
emilmont 77:869cf507173a 408
emilmont 77:869cf507173a 409 /**
emilmont 77:869cf507173a 410 * @}
emilmont 77:869cf507173a 411 */
emilmont 77:869cf507173a 412
emilmont 77:869cf507173a 413 /**
emilmont 77:869cf507173a 414 * @}
emilmont 77:869cf507173a 415 */
emilmont 77:869cf507173a 416
emilmont 77:869cf507173a 417 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 418 /* Exported functions ------------------------------------------------------- */
emilmont 77:869cf507173a 419 /* NOR/SRAM Controller functions **********************************************/
emilmont 77:869cf507173a 420 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
emilmont 77:869cf507173a 421 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
emilmont 77:869cf507173a 422 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
emilmont 77:869cf507173a 423 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
emilmont 77:869cf507173a 424
emilmont 77:869cf507173a 425 #ifdef __cplusplus
emilmont 77:869cf507173a 426 }
emilmont 77:869cf507173a 427 #endif
emilmont 77:869cf507173a 428
emilmont 77:869cf507173a 429 #endif /*__STM32L1xx_FSMC_H */
emilmont 77:869cf507173a 430 /**
emilmont 77:869cf507173a 431 * @}
emilmont 77:869cf507173a 432 */
emilmont 77:869cf507173a 433
emilmont 77:869cf507173a 434 /**
emilmont 77:869cf507173a 435 * @}
emilmont 77:869cf507173a 436 */
emilmont 77:869cf507173a 437
emilmont 77:869cf507173a 438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/