erez i / mbed

version_2.0

Dependents:   cc3000_ping_demo_try_2

Fork of mbed by mbed official

TARGET_NUCLEO_F030R8/stm32f0xx_syscfg.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:
emilmont
Date:
Fri Feb 14 14:36:43 2014 +0000
Revision:
77:869cf507173a
Child:
81:7d30d6019079
Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f0xx_syscfg.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 16-January-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the SYSCFG firmware
emilmont 77:869cf507173a 8 * library.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
emilmont 77:869cf507173a 12 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
emilmont 77:869cf507173a 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
emilmont 77:869cf507173a 15 * You may not use this file except in compliance with the License.
emilmont 77:869cf507173a 16 * You may obtain a copy of the License at:
emilmont 77:869cf507173a 17 *
emilmont 77:869cf507173a 18 * http://www.st.com/software_license_agreement_liberty_v2
emilmont 77:869cf507173a 19 *
emilmont 77:869cf507173a 20 * Unless required by applicable law or agreed to in writing, software
emilmont 77:869cf507173a 21 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 77:869cf507173a 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 77:869cf507173a 23 * See the License for the specific language governing permissions and
emilmont 77:869cf507173a 24 * limitations under the License.
emilmont 77:869cf507173a 25 *
emilmont 77:869cf507173a 26 ******************************************************************************
emilmont 77:869cf507173a 27 */
emilmont 77:869cf507173a 28
emilmont 77:869cf507173a 29 /*!< Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 30 #ifndef __STM32F0XX_SYSCFG_H
emilmont 77:869cf507173a 31 #define __STM32F0XX_SYSCFG_H
emilmont 77:869cf507173a 32
emilmont 77:869cf507173a 33 #ifdef __cplusplus
emilmont 77:869cf507173a 34 extern "C" {
emilmont 77:869cf507173a 35 #endif
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37 /*!< Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 38 #include "stm32f0xx.h"
emilmont 77:869cf507173a 39
emilmont 77:869cf507173a 40 /** @addtogroup STM32F0xx_StdPeriph_Driver
emilmont 77:869cf507173a 41 * @{
emilmont 77:869cf507173a 42 */
emilmont 77:869cf507173a 43
emilmont 77:869cf507173a 44 /** @addtogroup SYSCFG
emilmont 77:869cf507173a 45 * @{
emilmont 77:869cf507173a 46 */
emilmont 77:869cf507173a 47 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 48 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50 /** @defgroup SYSCFG_Exported_Constants
emilmont 77:869cf507173a 51 * @{
emilmont 77:869cf507173a 52 */
emilmont 77:869cf507173a 53
emilmont 77:869cf507173a 54 /** @defgroup SYSCFG_EXTI_Port_Sources
emilmont 77:869cf507173a 55 * @{
emilmont 77:869cf507173a 56 */
emilmont 77:869cf507173a 57 #define EXTI_PortSourceGPIOA ((uint8_t)0x00)
emilmont 77:869cf507173a 58 #define EXTI_PortSourceGPIOB ((uint8_t)0x01)
emilmont 77:869cf507173a 59 #define EXTI_PortSourceGPIOC ((uint8_t)0x02)
emilmont 77:869cf507173a 60 #define EXTI_PortSourceGPIOD ((uint8_t)0x03) /*!< not available for STM32F031 devices */
emilmont 77:869cf507173a 61 #define EXTI_PortSourceGPIOE ((uint8_t)0x04) /*!< only available for STM32F072 devices */
emilmont 77:869cf507173a 62 #define EXTI_PortSourceGPIOF ((uint8_t)0x05)
emilmont 77:869cf507173a 63
emilmont 77:869cf507173a 64 #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
emilmont 77:869cf507173a 65 ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
emilmont 77:869cf507173a 66 ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
emilmont 77:869cf507173a 67 ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
emilmont 77:869cf507173a 68 ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
emilmont 77:869cf507173a 69 ((PORTSOURCE) == EXTI_PortSourceGPIOF))
emilmont 77:869cf507173a 70 /**
emilmont 77:869cf507173a 71 * @}
emilmont 77:869cf507173a 72 */
emilmont 77:869cf507173a 73
emilmont 77:869cf507173a 74 /** @defgroup SYSCFG_EXTI_Pin_sources
emilmont 77:869cf507173a 75 * @{
emilmont 77:869cf507173a 76 */
emilmont 77:869cf507173a 77 #define EXTI_PinSource0 ((uint8_t)0x00)
emilmont 77:869cf507173a 78 #define EXTI_PinSource1 ((uint8_t)0x01)
emilmont 77:869cf507173a 79 #define EXTI_PinSource2 ((uint8_t)0x02)
emilmont 77:869cf507173a 80 #define EXTI_PinSource3 ((uint8_t)0x03)
emilmont 77:869cf507173a 81 #define EXTI_PinSource4 ((uint8_t)0x04)
emilmont 77:869cf507173a 82 #define EXTI_PinSource5 ((uint8_t)0x05)
emilmont 77:869cf507173a 83 #define EXTI_PinSource6 ((uint8_t)0x06)
emilmont 77:869cf507173a 84 #define EXTI_PinSource7 ((uint8_t)0x07)
emilmont 77:869cf507173a 85 #define EXTI_PinSource8 ((uint8_t)0x08)
emilmont 77:869cf507173a 86 #define EXTI_PinSource9 ((uint8_t)0x09)
emilmont 77:869cf507173a 87 #define EXTI_PinSource10 ((uint8_t)0x0A)
emilmont 77:869cf507173a 88 #define EXTI_PinSource11 ((uint8_t)0x0B)
emilmont 77:869cf507173a 89 #define EXTI_PinSource12 ((uint8_t)0x0C)
emilmont 77:869cf507173a 90 #define EXTI_PinSource13 ((uint8_t)0x0D)
emilmont 77:869cf507173a 91 #define EXTI_PinSource14 ((uint8_t)0x0E)
emilmont 77:869cf507173a 92 #define EXTI_PinSource15 ((uint8_t)0x0F)
emilmont 77:869cf507173a 93
emilmont 77:869cf507173a 94 #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
emilmont 77:869cf507173a 95 ((PINSOURCE) == EXTI_PinSource1) || \
emilmont 77:869cf507173a 96 ((PINSOURCE) == EXTI_PinSource2) || \
emilmont 77:869cf507173a 97 ((PINSOURCE) == EXTI_PinSource3) || \
emilmont 77:869cf507173a 98 ((PINSOURCE) == EXTI_PinSource4) || \
emilmont 77:869cf507173a 99 ((PINSOURCE) == EXTI_PinSource5) || \
emilmont 77:869cf507173a 100 ((PINSOURCE) == EXTI_PinSource6) || \
emilmont 77:869cf507173a 101 ((PINSOURCE) == EXTI_PinSource7) || \
emilmont 77:869cf507173a 102 ((PINSOURCE) == EXTI_PinSource8) || \
emilmont 77:869cf507173a 103 ((PINSOURCE) == EXTI_PinSource9) || \
emilmont 77:869cf507173a 104 ((PINSOURCE) == EXTI_PinSource10) || \
emilmont 77:869cf507173a 105 ((PINSOURCE) == EXTI_PinSource11) || \
emilmont 77:869cf507173a 106 ((PINSOURCE) == EXTI_PinSource12) || \
emilmont 77:869cf507173a 107 ((PINSOURCE) == EXTI_PinSource13) || \
emilmont 77:869cf507173a 108 ((PINSOURCE) == EXTI_PinSource14) || \
emilmont 77:869cf507173a 109 ((PINSOURCE) == EXTI_PinSource15))
emilmont 77:869cf507173a 110 /**
emilmont 77:869cf507173a 111 * @}
emilmont 77:869cf507173a 112 */
emilmont 77:869cf507173a 113
emilmont 77:869cf507173a 114 /** @defgroup SYSCFG_Memory_Remap_Config
emilmont 77:869cf507173a 115 * @{
emilmont 77:869cf507173a 116 */
emilmont 77:869cf507173a 117 #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
emilmont 77:869cf507173a 118 #define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
emilmont 77:869cf507173a 119 #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
emilmont 77:869cf507173a 120
emilmont 77:869cf507173a 121
emilmont 77:869cf507173a 122 #define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
emilmont 77:869cf507173a 123 ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
emilmont 77:869cf507173a 124 ((REMAP) == SYSCFG_MemoryRemap_SRAM))
emilmont 77:869cf507173a 125
emilmont 77:869cf507173a 126 /**
emilmont 77:869cf507173a 127 * @}
emilmont 77:869cf507173a 128 */
emilmont 77:869cf507173a 129
emilmont 77:869cf507173a 130 /** @defgroup SYSCFG_DMA_Remap_Config
emilmont 77:869cf507173a 131 * @{
emilmont 77:869cf507173a 132 */
emilmont 77:869cf507173a 133 #define SYSCFG_DMARemap_TIM3 SYSCFG_CFGR1_TIM3_DMA_RMP /* Remap TIM3 DMA requests from channel4 to channel6,
emilmont 77:869cf507173a 134 available only for STM32F072 devices */
emilmont 77:869cf507173a 135 #define SYSCFG_DMARemap_TIM2 SYSCFG_CFGR1_TIM2_DMA_RMP /* Remap TIM2 DMA requests from channel3/4 to channel7,
emilmont 77:869cf507173a 136 available only for STM32F072 devices */
emilmont 77:869cf507173a 137 #define SYSCFG_DMARemap_TIM1 SYSCFG_CFGR1_TIM1_DMA_RMP /* Remap TIM1 DMA requests from channel2/3/4 to channel6,
emilmont 77:869cf507173a 138 available only for STM32F072 devices */
emilmont 77:869cf507173a 139 #define SYSCFG_DMARemap_I2C1 SYSCFG_CFGR1_I2C1_DMA_RMP /* Remap I2C1 DMA requests from channel3/2 to channel7/6,
emilmont 77:869cf507173a 140 available only for STM32F072 devices */
emilmont 77:869cf507173a 141 #define SYSCFG_DMARemap_USART3 SYSCFG_CFGR1_USART3_DMA_RMP /* Remap USART3 DMA requests from channel6/7 to channel3/2,
emilmont 77:869cf507173a 142 available only for STM32F072 devices */
emilmont 77:869cf507173a 143 #define SYSCFG_DMARemap_USART2 SYSCFG_CFGR1_USART2_DMA_RMP /* Remap USART2 DMA requests from channel4/5 to channel6/7,
emilmont 77:869cf507173a 144 available only for STM32F072 devices */
emilmont 77:869cf507173a 145 #define SYSCFG_DMARemap_SPI2 SYSCFG_CFGR1_SPI2_DMA_RMP /* Remap SPI2 DMA requests from channel4/5 to channel6/7,
emilmont 77:869cf507173a 146 available only for STM32F072 devices */
emilmont 77:869cf507173a 147 #define SYSCFG_DMARemap_TIM17_2 SYSCFG_CFGR1_TIM17_DMA_RMP2 /* Remap TIM17 DMA requests from channel1/2 to channel7,
emilmont 77:869cf507173a 148 available only for STM32F072 devices */
emilmont 77:869cf507173a 149 #define SYSCFG_DMARemap_TIM16_2 SYSCFG_CFGR1_TIM16_DMA_RMP2 /* Remap TIM16 DMA requests from channel3/4 to channel6,
emilmont 77:869cf507173a 150 available only for STM32F072 devices */
emilmont 77:869cf507173a 151 #define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */
emilmont 77:869cf507173a 152 #define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */
emilmont 77:869cf507173a 153 #define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
emilmont 77:869cf507173a 154 #define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
emilmont 77:869cf507173a 155 #define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */
emilmont 77:869cf507173a 156
emilmont 77:869cf507173a 157 #define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
emilmont 77:869cf507173a 158 ((REMAP) == SYSCFG_DMARemap_TIM16) || \
emilmont 77:869cf507173a 159 ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
emilmont 77:869cf507173a 160 ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
emilmont 77:869cf507173a 161 ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \
emilmont 77:869cf507173a 162 ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \
emilmont 77:869cf507173a 163 ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \
emilmont 77:869cf507173a 164 ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \
emilmont 77:869cf507173a 165 ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \
emilmont 77:869cf507173a 166 ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \
emilmont 77:869cf507173a 167 ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \
emilmont 77:869cf507173a 168 ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \
emilmont 77:869cf507173a 169 ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \
emilmont 77:869cf507173a 170 ((REMAP) == SYSCFG_DMARemap_ADC1))
emilmont 77:869cf507173a 171
emilmont 77:869cf507173a 172 /**
emilmont 77:869cf507173a 173 * @}
emilmont 77:869cf507173a 174 */
emilmont 77:869cf507173a 175
emilmont 77:869cf507173a 176 /** @defgroup SYSCFG_I2C_FastModePlus_Config
emilmont 77:869cf507173a 177 * @{
emilmont 77:869cf507173a 178 */
emilmont 77:869cf507173a 179 #define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */
emilmont 77:869cf507173a 180 #define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */
emilmont 77:869cf507173a 181 #define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */
emilmont 77:869cf507173a 182 #define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */
emilmont 77:869cf507173a 183 #define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0031 and STM32F030 devices) */
emilmont 77:869cf507173a 184 #define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins, available only for STM32F072 devices */
emilmont 77:869cf507173a 185 #define SYSCFG_I2CFastModePlus_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9 (only for STM32F031 and STM32F030 devices) */
emilmont 77:869cf507173a 186 #define SYSCFG_I2CFastModePlus_PA10 SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10(only for STM32F031 and STM32F030 devices) */
emilmont 77:869cf507173a 187
emilmont 77:869cf507173a 188 #define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
emilmont 77:869cf507173a 189 ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
emilmont 77:869cf507173a 190 ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
emilmont 77:869cf507173a 191 ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
emilmont 77:869cf507173a 192 ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
emilmont 77:869cf507173a 193 ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \
emilmont 77:869cf507173a 194 ((PIN) == SYSCFG_I2CFastModePlus_PA9) || \
emilmont 77:869cf507173a 195 ((PIN) == SYSCFG_I2CFastModePlus_PA10))
emilmont 77:869cf507173a 196
emilmont 77:869cf507173a 197
emilmont 77:869cf507173a 198 /**
emilmont 77:869cf507173a 199 * @}
emilmont 77:869cf507173a 200 */
emilmont 77:869cf507173a 201
emilmont 77:869cf507173a 202 /** @defgroup SYSCFG_Lock_Config
emilmont 77:869cf507173a 203 * @{
emilmont 77:869cf507173a 204 */
emilmont 77:869cf507173a 205 #define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1, not available for STM32F030 devices */
emilmont 77:869cf507173a 206 #define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */
emilmont 77:869cf507173a 207 #define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */
emilmont 77:869cf507173a 208
emilmont 77:869cf507173a 209 #define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
emilmont 77:869cf507173a 210 ((CONFIG) == SYSCFG_Break_SRAMParity) || \
emilmont 77:869cf507173a 211 ((CONFIG) == SYSCFG_Break_Lockup))
emilmont 77:869cf507173a 212
emilmont 77:869cf507173a 213 /**
emilmont 77:869cf507173a 214 * @}
emilmont 77:869cf507173a 215 */
emilmont 77:869cf507173a 216
emilmont 77:869cf507173a 217 /** @defgroup SYSCFG_flags_definition
emilmont 77:869cf507173a 218 * @{
emilmont 77:869cf507173a 219 */
emilmont 77:869cf507173a 220
emilmont 77:869cf507173a 221 #define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
emilmont 77:869cf507173a 222
emilmont 77:869cf507173a 223 #define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
emilmont 77:869cf507173a 224
emilmont 77:869cf507173a 225 /**
emilmont 77:869cf507173a 226 * @}
emilmont 77:869cf507173a 227 */
emilmont 77:869cf507173a 228
emilmont 77:869cf507173a 229 /**
emilmont 77:869cf507173a 230 * @}
emilmont 77:869cf507173a 231 */
emilmont 77:869cf507173a 232
emilmont 77:869cf507173a 233 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 234 /* Exported functions ------------------------------------------------------- */
emilmont 77:869cf507173a 235
emilmont 77:869cf507173a 236 /* Function used to set the SYSCFG configuration to the default reset state **/
emilmont 77:869cf507173a 237 void SYSCFG_DeInit(void);
emilmont 77:869cf507173a 238
emilmont 77:869cf507173a 239 /* SYSCFG configuration functions *********************************************/
emilmont 77:869cf507173a 240 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
emilmont 77:869cf507173a 241 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
emilmont 77:869cf507173a 242 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
emilmont 77:869cf507173a 243 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
emilmont 77:869cf507173a 244 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
emilmont 77:869cf507173a 245 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
emilmont 77:869cf507173a 246 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
emilmont 77:869cf507173a 247
emilmont 77:869cf507173a 248 #ifdef __cplusplus
emilmont 77:869cf507173a 249 }
emilmont 77:869cf507173a 250 #endif
emilmont 77:869cf507173a 251
emilmont 77:869cf507173a 252 #endif /*__STM32F0XX_SYSCFG_H */
emilmont 77:869cf507173a 253
emilmont 77:869cf507173a 254 /**
emilmont 77:869cf507173a 255 * @}
emilmont 77:869cf507173a 256 */
emilmont 77:869cf507173a 257
emilmont 77:869cf507173a 258 /**
emilmont 77:869cf507173a 259 * @}
emilmont 77:869cf507173a 260 */
emilmont 77:869cf507173a 261
emilmont 77:869cf507173a 262 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/