version_2.0

Dependents:   cc3000_ping_demo_try_2

Fork of mbed by mbed official

Committer:
bogdanm
Date:
Wed Mar 19 18:28:32 2014 +0000
Revision:
81:7d30d6019079
Parent:
77:869cf507173a
Release 81 of the mbed library

Main changes:

- Updates and fixes for many targets
- LPC1768: serial interface code fixes
- nRF51822 targets now output a .hex file
- More exporters
- More flexible GPIO API

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32l1xx_syscfg.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 31-January-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the SYSCFG
emilmont 77:869cf507173a 8 * firmware library.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
bogdanm 81:7d30d6019079 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
bogdanm 81:7d30d6019079 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 81:7d30d6019079 15 * are permitted provided that the following conditions are met:
bogdanm 81:7d30d6019079 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 81:7d30d6019079 17 * this list of conditions and the following disclaimer.
bogdanm 81:7d30d6019079 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 81:7d30d6019079 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 81:7d30d6019079 20 * and/or other materials provided with the distribution.
bogdanm 81:7d30d6019079 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 81:7d30d6019079 22 * may be used to endorse or promote products derived from this software
bogdanm 81:7d30d6019079 23 * without specific prior written permission.
emilmont 77:869cf507173a 24 *
bogdanm 81:7d30d6019079 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 81:7d30d6019079 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 81:7d30d6019079 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 81:7d30d6019079 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 81:7d30d6019079 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 81:7d30d6019079 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 81:7d30d6019079 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 81:7d30d6019079 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 81:7d30d6019079 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 81:7d30d6019079 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 35 *
emilmont 77:869cf507173a 36 ******************************************************************************
emilmont 77:869cf507173a 37 */
emilmont 77:869cf507173a 38
emilmont 77:869cf507173a 39 /*!< Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 40 #ifndef __STM32L1xx_SYSCFG_H
emilmont 77:869cf507173a 41 #define __STM32L1xx_SYSCFG_H
emilmont 77:869cf507173a 42
emilmont 77:869cf507173a 43 #ifdef __cplusplus
emilmont 77:869cf507173a 44 extern "C" {
emilmont 77:869cf507173a 45 #endif
emilmont 77:869cf507173a 46
emilmont 77:869cf507173a 47 /*!< Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 48 #include "stm32l1xx.h"
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50 /** @addtogroup STM32L1xx_StdPeriph_Driver
emilmont 77:869cf507173a 51 * @{
emilmont 77:869cf507173a 52 */
emilmont 77:869cf507173a 53
emilmont 77:869cf507173a 54 /** @addtogroup SYSCFG
emilmont 77:869cf507173a 55 * @{
emilmont 77:869cf507173a 56 */
emilmont 77:869cf507173a 57
emilmont 77:869cf507173a 58 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 59 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 60
emilmont 77:869cf507173a 61 /** @defgroup SYSCFG_Exported_Constants
emilmont 77:869cf507173a 62 * @{
emilmont 77:869cf507173a 63 */
emilmont 77:869cf507173a 64
emilmont 77:869cf507173a 65 /** @defgroup EXTI_Port_Sources
emilmont 77:869cf507173a 66 * @{
emilmont 77:869cf507173a 67 */
emilmont 77:869cf507173a 68 #define EXTI_PortSourceGPIOA ((uint8_t)0x00)
emilmont 77:869cf507173a 69 #define EXTI_PortSourceGPIOB ((uint8_t)0x01)
emilmont 77:869cf507173a 70 #define EXTI_PortSourceGPIOC ((uint8_t)0x02)
emilmont 77:869cf507173a 71 #define EXTI_PortSourceGPIOD ((uint8_t)0x03)
emilmont 77:869cf507173a 72 #define EXTI_PortSourceGPIOE ((uint8_t)0x04)
emilmont 77:869cf507173a 73 #define EXTI_PortSourceGPIOH ((uint8_t)0x05)
emilmont 77:869cf507173a 74 #define EXTI_PortSourceGPIOF ((uint8_t)0x06)
emilmont 77:869cf507173a 75 #define EXTI_PortSourceGPIOG ((uint8_t)0x07)
emilmont 77:869cf507173a 76
emilmont 77:869cf507173a 77 #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
emilmont 77:869cf507173a 78 ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
emilmont 77:869cf507173a 79 ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
emilmont 77:869cf507173a 80 ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
emilmont 77:869cf507173a 81 ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
emilmont 77:869cf507173a 82 ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
emilmont 77:869cf507173a 83 ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
emilmont 77:869cf507173a 84 ((PORTSOURCE) == EXTI_PortSourceGPIOH))
emilmont 77:869cf507173a 85 /**
emilmont 77:869cf507173a 86 * @}
emilmont 77:869cf507173a 87 */
emilmont 77:869cf507173a 88
emilmont 77:869cf507173a 89 /** @defgroup EXTI_Pin_sources
emilmont 77:869cf507173a 90 * @{
emilmont 77:869cf507173a 91 */
emilmont 77:869cf507173a 92 #define EXTI_PinSource0 ((uint8_t)0x00)
emilmont 77:869cf507173a 93 #define EXTI_PinSource1 ((uint8_t)0x01)
emilmont 77:869cf507173a 94 #define EXTI_PinSource2 ((uint8_t)0x02)
emilmont 77:869cf507173a 95 #define EXTI_PinSource3 ((uint8_t)0x03)
emilmont 77:869cf507173a 96 #define EXTI_PinSource4 ((uint8_t)0x04)
emilmont 77:869cf507173a 97 #define EXTI_PinSource5 ((uint8_t)0x05)
emilmont 77:869cf507173a 98 #define EXTI_PinSource6 ((uint8_t)0x06)
emilmont 77:869cf507173a 99 #define EXTI_PinSource7 ((uint8_t)0x07)
emilmont 77:869cf507173a 100 #define EXTI_PinSource8 ((uint8_t)0x08)
emilmont 77:869cf507173a 101 #define EXTI_PinSource9 ((uint8_t)0x09)
emilmont 77:869cf507173a 102 #define EXTI_PinSource10 ((uint8_t)0x0A)
emilmont 77:869cf507173a 103 #define EXTI_PinSource11 ((uint8_t)0x0B)
emilmont 77:869cf507173a 104 #define EXTI_PinSource12 ((uint8_t)0x0C)
emilmont 77:869cf507173a 105 #define EXTI_PinSource13 ((uint8_t)0x0D)
emilmont 77:869cf507173a 106 #define EXTI_PinSource14 ((uint8_t)0x0E)
emilmont 77:869cf507173a 107 #define EXTI_PinSource15 ((uint8_t)0x0F)
emilmont 77:869cf507173a 108 #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
emilmont 77:869cf507173a 109 ((PINSOURCE) == EXTI_PinSource1) || \
emilmont 77:869cf507173a 110 ((PINSOURCE) == EXTI_PinSource2) || \
emilmont 77:869cf507173a 111 ((PINSOURCE) == EXTI_PinSource3) || \
emilmont 77:869cf507173a 112 ((PINSOURCE) == EXTI_PinSource4) || \
emilmont 77:869cf507173a 113 ((PINSOURCE) == EXTI_PinSource5) || \
emilmont 77:869cf507173a 114 ((PINSOURCE) == EXTI_PinSource6) || \
emilmont 77:869cf507173a 115 ((PINSOURCE) == EXTI_PinSource7) || \
emilmont 77:869cf507173a 116 ((PINSOURCE) == EXTI_PinSource8) || \
emilmont 77:869cf507173a 117 ((PINSOURCE) == EXTI_PinSource9) || \
emilmont 77:869cf507173a 118 ((PINSOURCE) == EXTI_PinSource10) || \
emilmont 77:869cf507173a 119 ((PINSOURCE) == EXTI_PinSource11) || \
emilmont 77:869cf507173a 120 ((PINSOURCE) == EXTI_PinSource12) || \
emilmont 77:869cf507173a 121 ((PINSOURCE) == EXTI_PinSource13) || \
emilmont 77:869cf507173a 122 ((PINSOURCE) == EXTI_PinSource14) || \
emilmont 77:869cf507173a 123 ((PINSOURCE) == EXTI_PinSource15))
emilmont 77:869cf507173a 124 /**
emilmont 77:869cf507173a 125 * @}
emilmont 77:869cf507173a 126 */
emilmont 77:869cf507173a 127
emilmont 77:869cf507173a 128 /** @defgroup SYSCFG_Memory_Remap_Config
emilmont 77:869cf507173a 129 * @{
emilmont 77:869cf507173a 130 */
emilmont 77:869cf507173a 131 #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
emilmont 77:869cf507173a 132 #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
emilmont 77:869cf507173a 133 #define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
emilmont 77:869cf507173a 134 #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
emilmont 77:869cf507173a 137 ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
emilmont 77:869cf507173a 138 ((REMAP) == SYSCFG_MemoryRemap_FSMC) || \
emilmont 77:869cf507173a 139 ((REMAP) == SYSCFG_MemoryRemap_SRAM))
emilmont 77:869cf507173a 140
emilmont 77:869cf507173a 141 /**
emilmont 77:869cf507173a 142 * @}
emilmont 77:869cf507173a 143 */
emilmont 77:869cf507173a 144
emilmont 77:869cf507173a 145 /** @defgroup RI_Resistor
emilmont 77:869cf507173a 146 * @{
emilmont 77:869cf507173a 147 */
emilmont 77:869cf507173a 148
emilmont 77:869cf507173a 149 #define RI_Resistor_10KPU COMP_CSR_10KPU
emilmont 77:869cf507173a 150 #define RI_Resistor_400KPU COMP_CSR_400KPU
emilmont 77:869cf507173a 151 #define RI_Resistor_10KPD COMP_CSR_10KPD
emilmont 77:869cf507173a 152 #define RI_Resistor_400KPD COMP_CSR_400KPD
emilmont 77:869cf507173a 153
emilmont 77:869cf507173a 154 #define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \
emilmont 77:869cf507173a 155 ((RESISTOR) == COMP_CSR_400KPU) || \
emilmont 77:869cf507173a 156 ((RESISTOR) == COMP_CSR_10KPD) || \
emilmont 77:869cf507173a 157 ((RESISTOR) == COMP_CSR_400KPD))
emilmont 77:869cf507173a 158
emilmont 77:869cf507173a 159 /**
emilmont 77:869cf507173a 160 * @}
emilmont 77:869cf507173a 161 */
emilmont 77:869cf507173a 162
emilmont 77:869cf507173a 163 /** @defgroup RI_Channel
emilmont 77:869cf507173a 164 * @{
emilmont 77:869cf507173a 165 */
emilmont 77:869cf507173a 166
emilmont 77:869cf507173a 167 #define RI_Channel_3 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 168 #define RI_Channel_8 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 169 #define RI_Channel_13 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 170
emilmont 77:869cf507173a 171 #define IS_RI_CHANNEL(CHANNEL) (((CHANNEL) == RI_Channel_3) || \
emilmont 77:869cf507173a 172 ((CHANNEL) == RI_Channel_8) || \
emilmont 77:869cf507173a 173 ((CHANNEL) == RI_Channel_13))
emilmont 77:869cf507173a 174
emilmont 77:869cf507173a 175 /**
emilmont 77:869cf507173a 176 * @}
emilmont 77:869cf507173a 177 */
emilmont 77:869cf507173a 178
emilmont 77:869cf507173a 179 /** @defgroup RI_ChannelSpeed
emilmont 77:869cf507173a 180 * @{
emilmont 77:869cf507173a 181 */
emilmont 77:869cf507173a 182
emilmont 77:869cf507173a 183 #define RI_ChannelSpeed_Fast ((uint32_t)0x00000000)
emilmont 77:869cf507173a 184 #define RI_ChannelSpeed_Slow ((uint32_t)0x00000001)
emilmont 77:869cf507173a 185
emilmont 77:869cf507173a 186 #define IS_RI_CHANNELSPEED(SPEED) (((SPEED) == RI_ChannelSpeed_Fast) || \
emilmont 77:869cf507173a 187 ((SPEED) == RI_ChannelSpeed_Slow))
emilmont 77:869cf507173a 188
emilmont 77:869cf507173a 189 /**
emilmont 77:869cf507173a 190 * @}
emilmont 77:869cf507173a 191 */
emilmont 77:869cf507173a 192
emilmont 77:869cf507173a 193 /** @defgroup RI_InputCapture
emilmont 77:869cf507173a 194 * @{
emilmont 77:869cf507173a 195 */
emilmont 77:869cf507173a 196
emilmont 77:869cf507173a 197 #define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
emilmont 77:869cf507173a 198 #define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
emilmont 77:869cf507173a 199 #define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
emilmont 77:869cf507173a 200 #define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
emilmont 77:869cf507173a 201
emilmont 77:869cf507173a 202 #define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))
emilmont 77:869cf507173a 203 /**
emilmont 77:869cf507173a 204 * @}
emilmont 77:869cf507173a 205 */
emilmont 77:869cf507173a 206
emilmont 77:869cf507173a 207 /** @defgroup TIM_Select
emilmont 77:869cf507173a 208 * @{
emilmont 77:869cf507173a 209 */
emilmont 77:869cf507173a 210
emilmont 77:869cf507173a 211 #define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */
emilmont 77:869cf507173a 212 #define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */
emilmont 77:869cf507173a 213 #define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */
emilmont 77:869cf507173a 214 #define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */
emilmont 77:869cf507173a 215
emilmont 77:869cf507173a 216 #define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \
emilmont 77:869cf507173a 217 ((TIM) == TIM_Select_TIM2) || \
emilmont 77:869cf507173a 218 ((TIM) == TIM_Select_TIM3) || \
emilmont 77:869cf507173a 219 ((TIM) == TIM_Select_TIM4))
emilmont 77:869cf507173a 220
emilmont 77:869cf507173a 221 /**
emilmont 77:869cf507173a 222 * @}
emilmont 77:869cf507173a 223 */
emilmont 77:869cf507173a 224
emilmont 77:869cf507173a 225 /** @defgroup RI_InputCaptureRouting
emilmont 77:869cf507173a 226 * @{
emilmont 77:869cf507173a 227 */
emilmont 77:869cf507173a 228 /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
emilmont 77:869cf507173a 229 #define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */
emilmont 77:869cf507173a 230 #define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */
emilmont 77:869cf507173a 231 #define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */
emilmont 77:869cf507173a 232 #define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */
emilmont 77:869cf507173a 233 #define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */
emilmont 77:869cf507173a 234 #define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */
emilmont 77:869cf507173a 235 #define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */
emilmont 77:869cf507173a 236 #define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */
emilmont 77:869cf507173a 237 #define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */
emilmont 77:869cf507173a 238 #define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */
emilmont 77:869cf507173a 239 #define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */
emilmont 77:869cf507173a 240 #define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */
emilmont 77:869cf507173a 241 #define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */
emilmont 77:869cf507173a 242 #define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */
emilmont 77:869cf507173a 243 #define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */
emilmont 77:869cf507173a 244 #define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */
emilmont 77:869cf507173a 245
emilmont 77:869cf507173a 246 #define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \
emilmont 77:869cf507173a 247 ((ROUTING) == RI_InputCaptureRouting_1) || \
emilmont 77:869cf507173a 248 ((ROUTING) == RI_InputCaptureRouting_2) || \
emilmont 77:869cf507173a 249 ((ROUTING) == RI_InputCaptureRouting_3) || \
emilmont 77:869cf507173a 250 ((ROUTING) == RI_InputCaptureRouting_4) || \
emilmont 77:869cf507173a 251 ((ROUTING) == RI_InputCaptureRouting_5) || \
emilmont 77:869cf507173a 252 ((ROUTING) == RI_InputCaptureRouting_6) || \
emilmont 77:869cf507173a 253 ((ROUTING) == RI_InputCaptureRouting_7) || \
emilmont 77:869cf507173a 254 ((ROUTING) == RI_InputCaptureRouting_8) || \
emilmont 77:869cf507173a 255 ((ROUTING) == RI_InputCaptureRouting_9) || \
emilmont 77:869cf507173a 256 ((ROUTING) == RI_InputCaptureRouting_10) || \
emilmont 77:869cf507173a 257 ((ROUTING) == RI_InputCaptureRouting_11) || \
emilmont 77:869cf507173a 258 ((ROUTING) == RI_InputCaptureRouting_12) || \
emilmont 77:869cf507173a 259 ((ROUTING) == RI_InputCaptureRouting_13) || \
emilmont 77:869cf507173a 260 ((ROUTING) == RI_InputCaptureRouting_14) || \
emilmont 77:869cf507173a 261 ((ROUTING) == RI_InputCaptureRouting_15))
emilmont 77:869cf507173a 262
emilmont 77:869cf507173a 263 /**
emilmont 77:869cf507173a 264 * @}
emilmont 77:869cf507173a 265 */
emilmont 77:869cf507173a 266
emilmont 77:869cf507173a 267 /** @defgroup RI_IOSwitch
emilmont 77:869cf507173a 268 * @{
emilmont 77:869cf507173a 269 */
emilmont 77:869cf507173a 270
emilmont 77:869cf507173a 271 /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
emilmont 77:869cf507173a 272 #define RI_IOSwitch_CH0 ((uint32_t)0x80000001)
emilmont 77:869cf507173a 273 #define RI_IOSwitch_CH1 ((uint32_t)0x80000002)
emilmont 77:869cf507173a 274 #define RI_IOSwitch_CH2 ((uint32_t)0x80000004)
emilmont 77:869cf507173a 275 #define RI_IOSwitch_CH3 ((uint32_t)0x80000008)
emilmont 77:869cf507173a 276 #define RI_IOSwitch_CH4 ((uint32_t)0x80000010)
emilmont 77:869cf507173a 277 #define RI_IOSwitch_CH5 ((uint32_t)0x80000020)
emilmont 77:869cf507173a 278 #define RI_IOSwitch_CH6 ((uint32_t)0x80000040)
emilmont 77:869cf507173a 279 #define RI_IOSwitch_CH7 ((uint32_t)0x80000080)
emilmont 77:869cf507173a 280 #define RI_IOSwitch_CH8 ((uint32_t)0x80000100)
emilmont 77:869cf507173a 281 #define RI_IOSwitch_CH9 ((uint32_t)0x80000200)
emilmont 77:869cf507173a 282 #define RI_IOSwitch_CH10 ((uint32_t)0x80000400)
emilmont 77:869cf507173a 283 #define RI_IOSwitch_CH11 ((uint32_t)0x80000800)
emilmont 77:869cf507173a 284 #define RI_IOSwitch_CH12 ((uint32_t)0x80001000)
emilmont 77:869cf507173a 285 #define RI_IOSwitch_CH13 ((uint32_t)0x80002000)
emilmont 77:869cf507173a 286 #define RI_IOSwitch_CH14 ((uint32_t)0x80004000)
emilmont 77:869cf507173a 287 #define RI_IOSwitch_CH15 ((uint32_t)0x80008000)
emilmont 77:869cf507173a 288 #define RI_IOSwitch_CH31 ((uint32_t)0x80010000)
emilmont 77:869cf507173a 289 #define RI_IOSwitch_CH18 ((uint32_t)0x80040000)
emilmont 77:869cf507173a 290 #define RI_IOSwitch_CH19 ((uint32_t)0x80080000)
emilmont 77:869cf507173a 291 #define RI_IOSwitch_CH20 ((uint32_t)0x80100000)
emilmont 77:869cf507173a 292 #define RI_IOSwitch_CH21 ((uint32_t)0x80200000)
emilmont 77:869cf507173a 293 #define RI_IOSwitch_CH22 ((uint32_t)0x80400000)
emilmont 77:869cf507173a 294 #define RI_IOSwitch_CH23 ((uint32_t)0x80800000)
emilmont 77:869cf507173a 295 #define RI_IOSwitch_CH24 ((uint32_t)0x81000000)
emilmont 77:869cf507173a 296 #define RI_IOSwitch_CH25 ((uint32_t)0x82000000)
emilmont 77:869cf507173a 297 #define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect
emilmont 77:869cf507173a 298 selected channel to COMP1 non inverting input */
emilmont 77:869cf507173a 299 #define RI_IOSwitch_CH27 ((uint32_t)0x88000000)
emilmont 77:869cf507173a 300 #define RI_IOSwitch_CH28 ((uint32_t)0x90000000)
emilmont 77:869cf507173a 301 #define RI_IOSwitch_CH29 ((uint32_t)0xA0000000)
emilmont 77:869cf507173a 302 #define RI_IOSwitch_CH30 ((uint32_t)0xC0000000)
emilmont 77:869cf507173a 303
emilmont 77:869cf507173a 304 /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
emilmont 77:869cf507173a 305 #define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 306 #define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 307 #define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 308 #define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 309 #define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 310 #define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 311 #define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 312 #define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 313 #define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 314 #define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 315 #define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 316 #define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 317 #define RI_IOSwitch_GR4_4 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 318 #define RI_IOSwitch_CH0b ((uint32_t)0x00010000)
emilmont 77:869cf507173a 319 #define RI_IOSwitch_CH1b ((uint32_t)0x00020000)
emilmont 77:869cf507173a 320 #define RI_IOSwitch_CH2b ((uint32_t)0x00040000)
emilmont 77:869cf507173a 321 #define RI_IOSwitch_CH3b ((uint32_t)0x00080000)
emilmont 77:869cf507173a 322 #define RI_IOSwitch_CH6b ((uint32_t)0x00100000)
emilmont 77:869cf507173a 323 #define RI_IOSwitch_CH7b ((uint32_t)0x00200000)
emilmont 77:869cf507173a 324 #define RI_IOSwitch_CH8b ((uint32_t)0x00400000)
emilmont 77:869cf507173a 325 #define RI_IOSwitch_CH9b ((uint32_t)0x00800000)
emilmont 77:869cf507173a 326 #define RI_IOSwitch_CH10b ((uint32_t)0x01000000)
emilmont 77:869cf507173a 327 #define RI_IOSwitch_CH11b ((uint32_t)0x02000000)
emilmont 77:869cf507173a 328 #define RI_IOSwitch_CH12b ((uint32_t)0x04000000)
emilmont 77:869cf507173a 329 #define RI_IOSwitch_GR6_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 330 #define RI_IOSwitch_GR6_4 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 331 #define RI_IOSwitch_GR5_4 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 332
emilmont 77:869cf507173a 333
emilmont 77:869cf507173a 334 #define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \
emilmont 77:869cf507173a 335 ((IOSWITCH) == RI_IOSwitch_CH1) || \
emilmont 77:869cf507173a 336 ((IOSWITCH) == RI_IOSwitch_CH2) || \
emilmont 77:869cf507173a 337 ((IOSWITCH) == RI_IOSwitch_CH3) || \
emilmont 77:869cf507173a 338 ((IOSWITCH) == RI_IOSwitch_CH4) || \
emilmont 77:869cf507173a 339 ((IOSWITCH) == RI_IOSwitch_CH5) || \
emilmont 77:869cf507173a 340 ((IOSWITCH) == RI_IOSwitch_CH6) || \
emilmont 77:869cf507173a 341 ((IOSWITCH) == RI_IOSwitch_CH7) || \
emilmont 77:869cf507173a 342 ((IOSWITCH) == RI_IOSwitch_CH8) || \
emilmont 77:869cf507173a 343 ((IOSWITCH) == RI_IOSwitch_CH9) || \
emilmont 77:869cf507173a 344 ((IOSWITCH) == RI_IOSwitch_CH10) || \
emilmont 77:869cf507173a 345 ((IOSWITCH) == RI_IOSwitch_CH11) || \
emilmont 77:869cf507173a 346 ((IOSWITCH) == RI_IOSwitch_CH12) || \
emilmont 77:869cf507173a 347 ((IOSWITCH) == RI_IOSwitch_CH13) || \
emilmont 77:869cf507173a 348 ((IOSWITCH) == RI_IOSwitch_CH14) || \
emilmont 77:869cf507173a 349 ((IOSWITCH) == RI_IOSwitch_CH15) || \
emilmont 77:869cf507173a 350 ((IOSWITCH) == RI_IOSwitch_CH18) || \
emilmont 77:869cf507173a 351 ((IOSWITCH) == RI_IOSwitch_CH19) || \
emilmont 77:869cf507173a 352 ((IOSWITCH) == RI_IOSwitch_CH20) || \
emilmont 77:869cf507173a 353 ((IOSWITCH) == RI_IOSwitch_CH21) || \
emilmont 77:869cf507173a 354 ((IOSWITCH) == RI_IOSwitch_CH22) || \
emilmont 77:869cf507173a 355 ((IOSWITCH) == RI_IOSwitch_CH23) || \
emilmont 77:869cf507173a 356 ((IOSWITCH) == RI_IOSwitch_CH24) || \
emilmont 77:869cf507173a 357 ((IOSWITCH) == RI_IOSwitch_CH25) || \
emilmont 77:869cf507173a 358 ((IOSWITCH) == RI_IOSwitch_VCOMP) || \
emilmont 77:869cf507173a 359 ((IOSWITCH) == RI_IOSwitch_CH27) || \
emilmont 77:869cf507173a 360 ((IOSWITCH) == RI_IOSwitch_CH28) || \
emilmont 77:869cf507173a 361 ((IOSWITCH) == RI_IOSwitch_CH29) || \
emilmont 77:869cf507173a 362 ((IOSWITCH) == RI_IOSwitch_CH30) || \
emilmont 77:869cf507173a 363 ((IOSWITCH) == RI_IOSwitch_CH31) || \
emilmont 77:869cf507173a 364 ((IOSWITCH) == RI_IOSwitch_GR10_1) || \
emilmont 77:869cf507173a 365 ((IOSWITCH) == RI_IOSwitch_GR10_2) || \
emilmont 77:869cf507173a 366 ((IOSWITCH) == RI_IOSwitch_GR10_3) || \
emilmont 77:869cf507173a 367 ((IOSWITCH) == RI_IOSwitch_GR10_4) || \
emilmont 77:869cf507173a 368 ((IOSWITCH) == RI_IOSwitch_GR6_1) || \
emilmont 77:869cf507173a 369 ((IOSWITCH) == RI_IOSwitch_GR6_2) || \
emilmont 77:869cf507173a 370 ((IOSWITCH) == RI_IOSwitch_GR6_3) || \
emilmont 77:869cf507173a 371 ((IOSWITCH) == RI_IOSwitch_GR6_4) || \
emilmont 77:869cf507173a 372 ((IOSWITCH) == RI_IOSwitch_GR5_1) || \
emilmont 77:869cf507173a 373 ((IOSWITCH) == RI_IOSwitch_GR5_2) || \
emilmont 77:869cf507173a 374 ((IOSWITCH) == RI_IOSwitch_GR5_3) || \
emilmont 77:869cf507173a 375 ((IOSWITCH) == RI_IOSwitch_GR5_4) || \
emilmont 77:869cf507173a 376 ((IOSWITCH) == RI_IOSwitch_GR4_1) || \
emilmont 77:869cf507173a 377 ((IOSWITCH) == RI_IOSwitch_GR4_2) || \
emilmont 77:869cf507173a 378 ((IOSWITCH) == RI_IOSwitch_GR4_3) || \
emilmont 77:869cf507173a 379 ((IOSWITCH) == RI_IOSwitch_GR4_4) || \
emilmont 77:869cf507173a 380 ((IOSWITCH) == RI_IOSwitch_CH0b) || \
emilmont 77:869cf507173a 381 ((IOSWITCH) == RI_IOSwitch_CH1b) || \
emilmont 77:869cf507173a 382 ((IOSWITCH) == RI_IOSwitch_CH2b) || \
emilmont 77:869cf507173a 383 ((IOSWITCH) == RI_IOSwitch_CH3b) || \
emilmont 77:869cf507173a 384 ((IOSWITCH) == RI_IOSwitch_CH6b) || \
emilmont 77:869cf507173a 385 ((IOSWITCH) == RI_IOSwitch_CH7b) || \
emilmont 77:869cf507173a 386 ((IOSWITCH) == RI_IOSwitch_CH8b) || \
emilmont 77:869cf507173a 387 ((IOSWITCH) == RI_IOSwitch_CH9b) || \
emilmont 77:869cf507173a 388 ((IOSWITCH) == RI_IOSwitch_CH10b) || \
emilmont 77:869cf507173a 389 ((IOSWITCH) == RI_IOSwitch_CH11b) || \
emilmont 77:869cf507173a 390 ((IOSWITCH) == RI_IOSwitch_CH12b))
emilmont 77:869cf507173a 391
emilmont 77:869cf507173a 392 /**
emilmont 77:869cf507173a 393 * @}
emilmont 77:869cf507173a 394 */
emilmont 77:869cf507173a 395
emilmont 77:869cf507173a 396 /** @defgroup RI_Port
emilmont 77:869cf507173a 397 * @{
emilmont 77:869cf507173a 398 */
emilmont 77:869cf507173a 399
emilmont 77:869cf507173a 400 #define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */
emilmont 77:869cf507173a 401 #define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */
emilmont 77:869cf507173a 402 #define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */
emilmont 77:869cf507173a 403 #define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */
emilmont 77:869cf507173a 404 #define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */
emilmont 77:869cf507173a 405 #define RI_PortF ((uint8_t)0x06) /*!< GPIOF selected */
emilmont 77:869cf507173a 406 #define RI_PortG ((uint8_t)0x07) /*!< GPIOG selected */
emilmont 77:869cf507173a 407
emilmont 77:869cf507173a 408 #define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \
emilmont 77:869cf507173a 409 ((PORT) == RI_PortB) || \
emilmont 77:869cf507173a 410 ((PORT) == RI_PortC) || \
emilmont 77:869cf507173a 411 ((PORT) == RI_PortD) || \
emilmont 77:869cf507173a 412 ((PORT) == RI_PortE) || \
emilmont 77:869cf507173a 413 ((PORT) == RI_PortF) || \
emilmont 77:869cf507173a 414 ((PORT) == RI_PortG))
emilmont 77:869cf507173a 415 /**
emilmont 77:869cf507173a 416 * @}
emilmont 77:869cf507173a 417 */
emilmont 77:869cf507173a 418
emilmont 77:869cf507173a 419 /** @defgroup RI_Pin define
emilmont 77:869cf507173a 420 * @{
emilmont 77:869cf507173a 421 */
emilmont 77:869cf507173a 422 #define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
emilmont 77:869cf507173a 423 #define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
emilmont 77:869cf507173a 424 #define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
emilmont 77:869cf507173a 425 #define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
emilmont 77:869cf507173a 426 #define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
emilmont 77:869cf507173a 427 #define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
emilmont 77:869cf507173a 428 #define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
emilmont 77:869cf507173a 429 #define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
emilmont 77:869cf507173a 430 #define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
emilmont 77:869cf507173a 431 #define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
emilmont 77:869cf507173a 432 #define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
emilmont 77:869cf507173a 433 #define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
emilmont 77:869cf507173a 434 #define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
emilmont 77:869cf507173a 435 #define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
emilmont 77:869cf507173a 436 #define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
emilmont 77:869cf507173a 437 #define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
emilmont 77:869cf507173a 438 #define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
emilmont 77:869cf507173a 439
emilmont 77:869cf507173a 440 #define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)
emilmont 77:869cf507173a 441
emilmont 77:869cf507173a 442 /**
emilmont 77:869cf507173a 443 * @}
emilmont 77:869cf507173a 444 */
emilmont 77:869cf507173a 445
emilmont 77:869cf507173a 446 /**
emilmont 77:869cf507173a 447 * @}
emilmont 77:869cf507173a 448 */
emilmont 77:869cf507173a 449
emilmont 77:869cf507173a 450 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 451 /* Exported functions ------------------------------------------------------- */
emilmont 77:869cf507173a 452
emilmont 77:869cf507173a 453 /* Function used to set the SYSCFG and RI configuration to the default reset state **/
emilmont 77:869cf507173a 454 void SYSCFG_DeInit(void);
emilmont 77:869cf507173a 455 void SYSCFG_RIDeInit(void);
emilmont 77:869cf507173a 456
emilmont 77:869cf507173a 457 /* SYSCFG Initialization and Configuration functions **************************/
emilmont 77:869cf507173a 458 void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
emilmont 77:869cf507173a 459 uint32_t SYSCFG_GetBootMode(void);
emilmont 77:869cf507173a 460 void SYSCFG_USBPuCmd(FunctionalState NewState);
emilmont 77:869cf507173a 461 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
emilmont 77:869cf507173a 462
emilmont 77:869cf507173a 463 /* RI Initialization and Configuration functions ******************************/
emilmont 77:869cf507173a 464 void SYSCFG_RITIMSelect(uint32_t TIM_Select);
emilmont 77:869cf507173a 465 void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);
emilmont 77:869cf507173a 466 void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);
emilmont 77:869cf507173a 467 void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed);
emilmont 77:869cf507173a 468 void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);
emilmont 77:869cf507173a 469 void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);
emilmont 77:869cf507173a 470 void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState);
emilmont 77:869cf507173a 471
emilmont 77:869cf507173a 472 #ifdef __cplusplus
emilmont 77:869cf507173a 473 }
emilmont 77:869cf507173a 474 #endif
emilmont 77:869cf507173a 475
emilmont 77:869cf507173a 476 #endif /*__STM32L1xx_SYSCFG_H */
emilmont 77:869cf507173a 477
emilmont 77:869cf507173a 478 /**
emilmont 77:869cf507173a 479 * @}
emilmont 77:869cf507173a 480 */
emilmont 77:869cf507173a 481
emilmont 77:869cf507173a 482 /**
emilmont 77:869cf507173a 483 * @}
emilmont 77:869cf507173a 484 */
emilmont 77:869cf507173a 485
emilmont 77:869cf507173a 486 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/