mbed - version_2.0

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version_2.0

TARGET_NUCLEO_F302R8/stm32f30x_hrtim.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/**
bogdanm	82:6473597d706e	2	******************************************************************************
bogdanm	82:6473597d706e	3	* @file stm32f30x_hrtim.h
bogdanm	82:6473597d706e	4	* @author MCD Application Team
bogdanm	82:6473597d706e	5	* @version V1.1.0
bogdanm	82:6473597d706e	6	* @date 27-February-2014
bogdanm	82:6473597d706e	7	* @brief This file contains all the functions prototypes for the HRTIM firmware
bogdanm	82:6473597d706e	8	* library.
bogdanm	82:6473597d706e	9	******************************************************************************
bogdanm	82:6473597d706e	10	* @attention
bogdanm	82:6473597d706e	11	*
bogdanm	82:6473597d706e	12	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	82:6473597d706e	13	*
bogdanm	82:6473597d706e	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	82:6473597d706e	15	* are permitted provided that the following conditions are met:
bogdanm	82:6473597d706e	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	82:6473597d706e	17	* this list of conditions and the following disclaimer.
bogdanm	82:6473597d706e	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	82:6473597d706e	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	82:6473597d706e	20	* and/or other materials provided with the distribution.
bogdanm	82:6473597d706e	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	82:6473597d706e	22	* may be used to endorse or promote products derived from this software
bogdanm	82:6473597d706e	23	* without specific prior written permission.
bogdanm	82:6473597d706e	24	*
bogdanm	82:6473597d706e	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	82:6473597d706e	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	82:6473597d706e	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	82:6473597d706e	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	82:6473597d706e	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	82:6473597d706e	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	82:6473597d706e	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	82:6473597d706e	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	82:6473597d706e	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	82:6473597d706e	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	82:6473597d706e	35	*
bogdanm	82:6473597d706e	36	******************************************************************************
bogdanm	82:6473597d706e	37	*/
bogdanm	82:6473597d706e	38
bogdanm	82:6473597d706e	39	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	82:6473597d706e	40	#ifndef __STM32F30x_HRTIM_H
bogdanm	82:6473597d706e	41	#define __STM32F30x_HRTIM_H
bogdanm	82:6473597d706e	42
bogdanm	82:6473597d706e	43	#ifdef __cplusplus
bogdanm	82:6473597d706e	44	extern "C" {
bogdanm	82:6473597d706e	45	#endif
bogdanm	82:6473597d706e	46
bogdanm	82:6473597d706e	47	/* Includes ------------------------------------------------------------------*/
bogdanm	82:6473597d706e	48	#include "stm32f30x.h"
bogdanm	82:6473597d706e	49
bogdanm	82:6473597d706e	50	/** @addtogroup STM32F30x_StdPeriph_Driver
bogdanm	82:6473597d706e	51	* @{
bogdanm	82:6473597d706e	52	*/
bogdanm	82:6473597d706e	53
bogdanm	82:6473597d706e	54	/** @addtogroup ADC
bogdanm	82:6473597d706e	55	* @{
bogdanm	82:6473597d706e	56	*/
bogdanm	82:6473597d706e	57
bogdanm	82:6473597d706e	58	/* Exported types ------------------------------------------------------------*/
bogdanm	82:6473597d706e	59
bogdanm	82:6473597d706e	60	/**
bogdanm	82:6473597d706e	61	* @brief HRTIM Configuration Structure definition - Time base related parameters
bogdanm	82:6473597d706e	62	*/
bogdanm	82:6473597d706e	63	typedef struct
bogdanm	82:6473597d706e	64	{
bogdanm	82:6473597d706e	65	uint32_t Period; /*!< Specifies the timer period
bogdanm	82:6473597d706e	66	The period value must be above 3 periods of the fHRTIM clock.
bogdanm	82:6473597d706e	67	Maximum value is = 0xFFDF */
bogdanm	82:6473597d706e	68	uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
bogdanm	82:6473597d706e	69	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm	82:6473597d706e	70	uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
bogdanm	82:6473597d706e	71	This parameter can be any value of @ref HRTIM_PrescalerRatio */
bogdanm	82:6473597d706e	72	uint32_t Mode; /*!< Specifies the counter operating mode
bogdanm	82:6473597d706e	73	This parameter can be any value of @ref HRTIM_Mode */
bogdanm	82:6473597d706e	74	} HRTIM_BaseInitTypeDef;
bogdanm	82:6473597d706e	75	/**
bogdanm	82:6473597d706e	76	* @brief Waveform mode initialization parameters definition
bogdanm	82:6473597d706e	77	*/
bogdanm	82:6473597d706e	78	typedef struct {
bogdanm	82:6473597d706e	79	uint32_t HalfModeEnable; /*!< Specifies whether or not half mode is enabled
bogdanm	82:6473597d706e	80	This parameter can be a combination of @ref HRTIM_HalfModeEnable */
bogdanm	82:6473597d706e	81	uint32_t StartOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
bogdanm	82:6473597d706e	82	This parameter can be a combination of @ref HRTIM_StartOnSyncInputEvent */
bogdanm	82:6473597d706e	83	uint32_t ResetOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
bogdanm	82:6473597d706e	84	This parameter can be a combination of @ref HRTIM_ResetOnSyncInputEvent */
bogdanm	82:6473597d706e	85	uint32_t DACSynchro; /*!< Indicates whether or not the a DAC synchronization event is generated
bogdanm	82:6473597d706e	86	This parameter can be any value of @ref HRTIM_DACSynchronization */
bogdanm	82:6473597d706e	87	uint32_t PreloadEnable; /*!< Specifies whether or not register preload is enabled
bogdanm	82:6473597d706e	88	This parameter can be a combination of @ref HRTIM_RegisterPreloadEnable */
bogdanm	82:6473597d706e	89	uint32_t UpdateGating; /*!< Specifies how the update occurs with respect to a burst DMA transaction or
bogdanm	82:6473597d706e	90	update enable inputs (Slave timers only)
bogdanm	82:6473597d706e	91	This parameter can be any value of @ref HRTIM_UpdateGating */
bogdanm	82:6473597d706e	92	uint32_t BurstMode; /*!< Specifies how the timer behaves during a burst mode operation
bogdanm	82:6473597d706e	93	This parameter can be a combination of @ref HRTIM_TimerBurstMode */
bogdanm	82:6473597d706e	94	uint32_t RepetitionUpdate; /*!< Specifies whether or not registers update is triggered by the repetition event
bogdanm	82:6473597d706e	95	This parameter can be a combination of @ref HRTIM_TimerRepetitionUpdate */
bogdanm	82:6473597d706e	96	} HRTIM_TimerInitTypeDef;
bogdanm	82:6473597d706e	97
bogdanm	82:6473597d706e	98	/**
bogdanm	82:6473597d706e	99	* @brief Basic output compare mode configuration definition
bogdanm	82:6473597d706e	100	*/
bogdanm	82:6473597d706e	101	typedef struct {
bogdanm	82:6473597d706e	102	uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
bogdanm	82:6473597d706e	103	This parameter can be a combination of @ref HRTIM_BasicOCMode */
bogdanm	82:6473597d706e	104	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm	82:6473597d706e	105	The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm	82:6473597d706e	106	uint32_t Polarity; /*!< Specifies the output polarity
bogdanm	82:6473597d706e	107	This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm	82:6473597d706e	108	uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm	82:6473597d706e	109	This parameter can be any value of @ref HRTIM_OutputIDLEState */
bogdanm	82:6473597d706e	110	} HRTIM_BasicOCChannelCfgTypeDef;
bogdanm	82:6473597d706e	111
bogdanm	82:6473597d706e	112	/**
bogdanm	82:6473597d706e	113	* @brief Basic PWM output mode configuration definition
bogdanm	82:6473597d706e	114	*/
bogdanm	82:6473597d706e	115	typedef struct {
bogdanm	82:6473597d706e	116	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm	82:6473597d706e	117	The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm	82:6473597d706e	118	uint32_t Polarity; /*!< Specifies the output polarity
bogdanm	82:6473597d706e	119	This parameter can be any value of @ref HRTIM_OutputPolarity */
bogdanm	82:6473597d706e	120	uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm	82:6473597d706e	121	This parameter can be any value of @ref HRTIM_OutputIDLEState */
bogdanm	82:6473597d706e	122	} HRTIM_BasicPWMChannelCfgTypeDef;
bogdanm	82:6473597d706e	123
bogdanm	82:6473597d706e	124	/**
bogdanm	82:6473597d706e	125	* @brief Basic capture mode configuration definition
bogdanm	82:6473597d706e	126	*/
bogdanm	82:6473597d706e	127	typedef struct {
bogdanm	82:6473597d706e	128	uint32_t CaptureUnit; /*!< Specifies the external event Channel
bogdanm	82:6473597d706e	129	This parameter can be any 'EEVx' value of @ref HRTIM_CaptureUnit */
bogdanm	82:6473597d706e	130	uint32_t Event; /*!< Specifies the external event triggering the capture
bogdanm	82:6473597d706e	131	This parameter can be any 'EEVx' value of @ref HRTIM_ExternalEventChannels */
bogdanm	82:6473597d706e	132	uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm	82:6473597d706e	133	This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
bogdanm	82:6473597d706e	134	uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
bogdanm	82:6473597d706e	135	This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
bogdanm	82:6473597d706e	136	uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm	82:6473597d706e	137	This parameter can be a value of @ref HRTIM_ExternalEventFilter */
bogdanm	82:6473597d706e	138	} HRTIM_BasicCaptureChannelCfgTypeDef;
bogdanm	82:6473597d706e	139
bogdanm	82:6473597d706e	140	/**
bogdanm	82:6473597d706e	141	* @brief Basic One Pulse mode configuration definition
bogdanm	82:6473597d706e	142	*/
bogdanm	82:6473597d706e	143	typedef struct {
bogdanm	82:6473597d706e	144	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm	82:6473597d706e	145	The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm	82:6473597d706e	146	uint32_t OutputPolarity; /*!< Specifies the output polarity
bogdanm	82:6473597d706e	147	This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm	82:6473597d706e	148	uint32_t OutputIdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm	82:6473597d706e	149	This parameter can be any value of @ref HRTIM_Output_IDLE_State */
bogdanm	82:6473597d706e	150	uint32_t Event; /*!< Specifies the external event triggering the pulse generation
bogdanm	82:6473597d706e	151	This parameter can be any 'EEVx' value of @ref HRTIM_Capture_Unit_Trigger */
bogdanm	82:6473597d706e	152	uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm	82:6473597d706e	153	This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
bogdanm	82:6473597d706e	154	uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
bogdanm	82:6473597d706e	155	This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
bogdanm	82:6473597d706e	156	uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm	82:6473597d706e	157	This parameter can be a value of @ref HRTIM_ExternalEventFilter */
bogdanm	82:6473597d706e	158	} HRTIM_BasicOnePulseChannelCfgTypeDef;
bogdanm	82:6473597d706e	159
bogdanm	82:6473597d706e	160	/**
bogdanm	82:6473597d706e	161	* @brief Timer configuration definition
bogdanm	82:6473597d706e	162	*/
bogdanm	82:6473597d706e	163	typedef struct {
bogdanm	82:6473597d706e	164	uint32_t PushPull; /*!< Specifies whether or not the push-pull mode is enabled
bogdanm	82:6473597d706e	165	This parameter can be a value of @ref HRTIM_TimerPushPullMode */
bogdanm	82:6473597d706e	166	uint32_t FaultEnable; /*!< Specifies which fault channels are enabled for the timer
bogdanm	82:6473597d706e	167	This parameter can be a combination of @ref HRTIM_TimerFaultEnabling */
bogdanm	82:6473597d706e	168	uint32_t FaultLock; /*!< Specifies whether or not fault enabling status is write protected
bogdanm	82:6473597d706e	169	This parameter can be a value of @ref HRTIM_TimerFaultLock */
bogdanm	82:6473597d706e	170	uint32_t DeadTimeInsertion; /*!< Specifies whether or not dead time insertion is enabled for the timer
bogdanm	82:6473597d706e	171	This parameter can be a value of @ref HRTIM_TimerDeadtimeInsertion */
bogdanm	82:6473597d706e	172	uint32_t DelayedProtectionMode; /*!< Specifies the delayed protection mode
bogdanm	82:6473597d706e	173	This parameter can be a value of @ref HRTIM_TimerDelayedProtectionMode */
bogdanm	82:6473597d706e	174	uint32_t UpdateTrigger; /*!< Specifies source(s) triggering the timer registers update
bogdanm	82:6473597d706e	175	This parameter can be a combination of @ref HRTIM_TimerUpdateTrigger */
bogdanm	82:6473597d706e	176	uint32_t ResetTrigger; /*!< Specifies source(s) triggering the timer counter reset
bogdanm	82:6473597d706e	177	This parameter can be a combination of @ref HRTIM_TimerResetTrigger */
bogdanm	82:6473597d706e	178	uint32_t ResetUpdate; /*!< Specifies whether or not registers update is triggered when the timer counter is reset
bogdanm	82:6473597d706e	179	This parameter can be a combination of @ref HRTIM_TimerResetUpdate */
bogdanm	82:6473597d706e	180	} HRTIM_TimerCfgTypeDef;
bogdanm	82:6473597d706e	181
bogdanm	82:6473597d706e	182	/**
bogdanm	82:6473597d706e	183	* @brief Compare unit configuration definition
bogdanm	82:6473597d706e	184	*/
bogdanm	82:6473597d706e	185	typedef struct {
bogdanm	82:6473597d706e	186	uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
bogdanm	82:6473597d706e	187	the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
bogdanm	82:6473597d706e	188	the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
bogdanm	82:6473597d706e	189	uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
bogdanm	82:6473597d706e	190	This parameter can be a value of @ref HRTIM_CompareUnitAutoDelayedMode */
bogdanm	82:6473597d706e	191	uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
bogdanm	82:6473597d706e	192	CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
bogdanm	82:6473597d706e	193	} HRTIM_CompareCfgTypeDef;
bogdanm	82:6473597d706e	194
bogdanm	82:6473597d706e	195	/**
bogdanm	82:6473597d706e	196	* @brief Capture unit configuration definition
bogdanm	82:6473597d706e	197	*/
bogdanm	82:6473597d706e	198	typedef struct {
bogdanm	82:6473597d706e	199	uint32_t Trigger; /*!< Specifies source(s) triggering the capture
bogdanm	82:6473597d706e	200	This parameter can be a combination of @ref HRTIM_CaptureUnitTrigger */
bogdanm	82:6473597d706e	201	} HRTIM_CaptureCfgTypeDef;
bogdanm	82:6473597d706e	202
bogdanm	82:6473597d706e	203	/**
bogdanm	82:6473597d706e	204	* @brief Output configuration definition
bogdanm	82:6473597d706e	205	*/
bogdanm	82:6473597d706e	206	typedef struct {
bogdanm	82:6473597d706e	207	uint32_t Polarity; /*!< Specifies the output polarity
bogdanm	82:6473597d706e	208	This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm	82:6473597d706e	209	uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
bogdanm	82:6473597d706e	210	This parameter can be any value of @ref HRTIM_OutputSetSource */
bogdanm	82:6473597d706e	211	uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
bogdanm	82:6473597d706e	212	This parameter can be any value of @ref HRTIM_OutputResetSource */
bogdanm	82:6473597d706e	213	uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
bogdanm	82:6473597d706e	214	This parameter can be any value of @ref HRTIM_OutputIdleMode */
bogdanm	82:6473597d706e	215	uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm	82:6473597d706e	216	This parameter can be any value of @ref HRTIM_OutputIDLEState */
bogdanm	82:6473597d706e	217	uint32_t FaultState; /*!< Specifies whether the output level is active or inactive when in FAULT state
bogdanm	82:6473597d706e	218	This parameter can be any value of @ref HRTIM_OutputFAULTState */
bogdanm	82:6473597d706e	219	uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
bogdanm	82:6473597d706e	220	This parameter can be any value of @ref HRTIM_OutputChopperModeEnable */
bogdanm	82:6473597d706e	221	uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state
bogdanm	82:6473597d706e	222	during a burst mode operation
bogdanm	82:6473597d706e	223	This parameters can be any value of @ref HRTIM_OutputBurstModeEntryDelayed */
bogdanm	82:6473597d706e	224	} HRTIM_OutputCfgTypeDef;
bogdanm	82:6473597d706e	225
bogdanm	82:6473597d706e	226	/**
bogdanm	82:6473597d706e	227	* @brief External event filtering in timing units configuration definition
bogdanm	82:6473597d706e	228	*/
bogdanm	82:6473597d706e	229	typedef struct {
bogdanm	82:6473597d706e	230	uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit
bogdanm	82:6473597d706e	231	This parameter can be a value of @ref HRTIM_TimerExternalEventFilter */
bogdanm	82:6473597d706e	232	uint32_t Latch; /*!< Specifies whether or not the signal is latched
bogdanm	82:6473597d706e	233	This parameter can be a value of @ref HRTIM_TimerExternalEventLatch */
bogdanm	82:6473597d706e	234	} HRTIM_TimerEventFilteringCfgTypeDef;
bogdanm	82:6473597d706e	235
bogdanm	82:6473597d706e	236	/**
bogdanm	82:6473597d706e	237	* @brief Dead time feature configuration definition
bogdanm	82:6473597d706e	238	*/
bogdanm	82:6473597d706e	239	typedef struct {
bogdanm	82:6473597d706e	240	uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler
bogdanm	82:6473597d706e	241	This parameter can be a number between 0x0 and = 0x7 */
bogdanm	82:6473597d706e	242	uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge
bogdanm	82:6473597d706e	243	This parameter can be a number between 0x0 and 0xFF */
bogdanm	82:6473597d706e	244	uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge
bogdanm	82:6473597d706e	245	This parameter can be a value of @ref HRTIM_DeadtimeRisingSign */
bogdanm	82:6473597d706e	246	uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected
bogdanm	82:6473597d706e	247	This parameter can be a value of @ref HRTIM_DeadtimeRisingLock */
bogdanm	82:6473597d706e	248	uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected
bogdanm	82:6473597d706e	249	This parameter can be a value of @ref HRTIM_DeadtimeRisingSignLock */
bogdanm	82:6473597d706e	250	uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge
bogdanm	82:6473597d706e	251	This parameter can be a number between 0x0 and 0xFF */
bogdanm	82:6473597d706e	252	uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge
bogdanm	82:6473597d706e	253	This parameter can be a value of @ref HRTIM_DeadtimeFallingSign */
bogdanm	82:6473597d706e	254	uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected
bogdanm	82:6473597d706e	255	This parameter can be a value of @ref HRTIM_DeadtimeFallingLock */
bogdanm	82:6473597d706e	256	uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected
bogdanm	82:6473597d706e	257	This parameter can be a value of @ref HRTIM_DeadtimeFallingSignLock */
bogdanm	82:6473597d706e	258	} HRTIM_DeadTimeCfgTypeDef;
bogdanm	82:6473597d706e	259
bogdanm	82:6473597d706e	260	/**
bogdanm	82:6473597d706e	261	* @brief Chopper mode configuration definition
bogdanm	82:6473597d706e	262	*/
bogdanm	82:6473597d706e	263	typedef struct {
bogdanm	82:6473597d706e	264	uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
bogdanm	82:6473597d706e	265	This parameter can be a value between 0 and 0xF */
bogdanm	82:6473597d706e	266	uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
bogdanm	82:6473597d706e	267	This parameter can be a value between 0 and 0x7 */
bogdanm	82:6473597d706e	268	uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
bogdanm	82:6473597d706e	269	This parameter can be a value between 0 and 0xF */
bogdanm	82:6473597d706e	270	} HRTIM_ChopperModeCfgTypeDef;
bogdanm	82:6473597d706e	271
bogdanm	82:6473597d706e	272	/**
bogdanm	82:6473597d706e	273	* @brief Master synchronization configuration definition
bogdanm	82:6473597d706e	274	*/
bogdanm	82:6473597d706e	275	typedef struct {
bogdanm	82:6473597d706e	276	uint32_t SyncInputSource; /*!< Specifies the external synchronization input source
bogdanm	82:6473597d706e	277	This parameter can be a value of @ref HRTIM_SynchronizationInputSource */
bogdanm	82:6473597d706e	278	uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
bogdanm	82:6473597d706e	279	This parameter can be a value of @ref HRTIM_SynchronizationOutputSource */
bogdanm	82:6473597d706e	280	uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization outputs
bogdanm	82:6473597d706e	281	This parameter can be a value of @ref HRTIM_SynchronizationOutputPolarity */
bogdanm	82:6473597d706e	282	} HRTIM_SynchroCfgTypeDef;
bogdanm	82:6473597d706e	283
bogdanm	82:6473597d706e	284	/**
bogdanm	82:6473597d706e	285	* @brief External event channel configuration definition
bogdanm	82:6473597d706e	286	*/
bogdanm	82:6473597d706e	287	typedef struct {
bogdanm	82:6473597d706e	288	uint32_t Source; /*!< Identifies the source of the external event
bogdanm	82:6473597d706e	289	This parameter can be a value of @ref HRTIM_ExternalEventSources */
bogdanm	82:6473597d706e	290	uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm	82:6473597d706e	291	This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
bogdanm	82:6473597d706e	292	uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event
bogdanm	82:6473597d706e	293	This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
bogdanm	82:6473597d706e	294	uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm	82:6473597d706e	295	This parameter can be a value of @ref HRTIM_ExternalEventFilter */
bogdanm	82:6473597d706e	296	uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event
bogdanm	82:6473597d706e	297	This parameter can be a value of @ref HRTIM_ExternalEventFastMode */
bogdanm	82:6473597d706e	298	} HRTIM_EventCfgTypeDef;
bogdanm	82:6473597d706e	299
bogdanm	82:6473597d706e	300	/**
bogdanm	82:6473597d706e	301	* @brief Fault channel configuration definition
bogdanm	82:6473597d706e	302	*/
bogdanm	82:6473597d706e	303	typedef struct {
bogdanm	82:6473597d706e	304	uint32_t Source; /*!< Identifies the source of the fault
bogdanm	82:6473597d706e	305	This parameter can be a value of @ref HRTIM_FaultSources */
bogdanm	82:6473597d706e	306	uint32_t Polarity; /*!< Specifies the polarity of the fault event
bogdanm	82:6473597d706e	307	This parameter can be a value of @ref HRTIM_FaultPolarity */
bogdanm	82:6473597d706e	308	uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter
bogdanm	82:6473597d706e	309	This parameter can be a value of @ref HRTIM_FaultFilter */
bogdanm	82:6473597d706e	310	uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected
bogdanm	82:6473597d706e	311	This parameter can be a value of @ref HRTIM_FaultLock */
bogdanm	82:6473597d706e	312	} HRTIM_FaultCfgTypeDef;
bogdanm	82:6473597d706e	313
bogdanm	82:6473597d706e	314	/**
bogdanm	82:6473597d706e	315	* @brief Burst mode configuration definition
bogdanm	82:6473597d706e	316	*/
bogdanm	82:6473597d706e	317	typedef struct {
bogdanm	82:6473597d706e	318	uint32_t Mode; /*!< Specifies the burst mode operating mode
bogdanm	82:6473597d706e	319	This parameter can be a value of @ref HRTIM_BurstModeOperatingMode */
bogdanm	82:6473597d706e	320	uint32_t ClockSource; /*!< Specifies the burst mode clock source
bogdanm	82:6473597d706e	321	This parameter can be a value of @ref HRTIM_BurstModeClockSource */
bogdanm	82:6473597d706e	322	uint32_t Prescaler; /*!< Specifies the burst mode prescaler
bogdanm	82:6473597d706e	323	This parameter can be a value of @ref HRTIM_BurstModePrescaler */
bogdanm	82:6473597d706e	324	uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER)
bogdanm	82:6473597d706e	325	This parameter can be a combination of @ref HRTIM_BurstModeRegisterPreloadEnable */
bogdanm	82:6473597d706e	326	uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation
bogdanm	82:6473597d706e	327	This parameter can be a combination of @ref HRTIM_BurstModeTrigger */
bogdanm	82:6473597d706e	328	uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state
bogdanm	82:6473597d706e	329	This parameter can be a number between 0x0 and 0xFFFF */
bogdanm	82:6473597d706e	330	uint32_t Period; /*!< Specifies burst mode repetition period
bogdanm	82:6473597d706e	331	This parameter can be a number between 0x1 and 0xFFFF */
bogdanm	82:6473597d706e	332	} HRTIM_BurstModeCfgTypeDef;
bogdanm	82:6473597d706e	333
bogdanm	82:6473597d706e	334	/**
bogdanm	82:6473597d706e	335	* @brief ADC trigger configuration definition
bogdanm	82:6473597d706e	336	*/
bogdanm	82:6473597d706e	337	typedef struct {
bogdanm	82:6473597d706e	338	uint32_t UpdateSource; /*!< Specifies the ADC trigger update source
bogdanm	82:6473597d706e	339	This parameter can be a combination of @ref HRTIM_ADCTriggerUpdateSource */
bogdanm	82:6473597d706e	340	uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion
bogdanm	82:6473597d706e	341	This parameter can be a combination of @ref HRTIM_ADCTriggerEvent */
bogdanm	82:6473597d706e	342	} HRTIM_ADCTriggerCfgTypeDef;
bogdanm	82:6473597d706e	343
bogdanm	82:6473597d706e	344
bogdanm	82:6473597d706e	345	/* Exported constants --------------------------------------------------------*/
bogdanm	82:6473597d706e	346	/** @defgroup HRTIM_Exported_Constants
bogdanm	82:6473597d706e	347	* @{
bogdanm	82:6473597d706e	348	*/
bogdanm	82:6473597d706e	349
bogdanm	82:6473597d706e	350	/** @defgroup HRTIM_TimerIndex
bogdanm	82:6473597d706e	351	* @{
bogdanm	82:6473597d706e	352	* @brief Constants defining the timer indexes
bogdanm	82:6473597d706e	353	*/
bogdanm	82:6473597d706e	354	#define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /!< Index associated to timer A /
bogdanm	82:6473597d706e	355	#define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /!< Index associated to timer B /
bogdanm	82:6473597d706e	356	#define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /!< Index associated to timer C /
bogdanm	82:6473597d706e	357	#define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /!< Index associated to timer D /
bogdanm	82:6473597d706e	358	#define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /!< Index associated to timer E /
bogdanm	82:6473597d706e	359	#define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /!< Index associated to master timer /
bogdanm	82:6473597d706e	360	#define HRTIM_COMMONINDEX (uint32_t)0x6 /!< Index associated to Common space /
bogdanm	82:6473597d706e	361
bogdanm	82:6473597d706e	362	#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
bogdanm	82:6473597d706e	363	(((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) \|\| \
bogdanm	82:6473597d706e	364	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) \|\| \
bogdanm	82:6473597d706e	365	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) \|\| \
bogdanm	82:6473597d706e	366	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) \|\| \
bogdanm	82:6473597d706e	367	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) \|\| \
bogdanm	82:6473597d706e	368	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
bogdanm	82:6473597d706e	369
bogdanm	82:6473597d706e	370	#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
bogdanm	82:6473597d706e	371	(((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) \|\| \
bogdanm	82:6473597d706e	372	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) \|\| \
bogdanm	82:6473597d706e	373	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) \|\| \
bogdanm	82:6473597d706e	374	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) \|\| \
bogdanm	82:6473597d706e	375	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
bogdanm	82:6473597d706e	376	/**
bogdanm	82:6473597d706e	377	* @}
bogdanm	82:6473597d706e	378	*/
bogdanm	82:6473597d706e	379
bogdanm	82:6473597d706e	380	/** @defgroup HRTIM_TimerIdentifier
bogdanm	82:6473597d706e	381	* @{
bogdanm	82:6473597d706e	382	* @brief Constants defining timer identifiers
bogdanm	82:6473597d706e	383	*/
bogdanm	82:6473597d706e	384	#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /!< Master identifier/
bogdanm	82:6473597d706e	385	#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /!< Timer A identifier /
bogdanm	82:6473597d706e	386	#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /!< Timer B identifier /
bogdanm	82:6473597d706e	387	#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /!< Timer C identifier /
bogdanm	82:6473597d706e	388	#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /!< Timer D identifier /
bogdanm	82:6473597d706e	389	#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /!< Timer E identifier /
bogdanm	82:6473597d706e	390
bogdanm	82:6473597d706e	391	#define IS_HRTIM_TIMERID(TIMERID)\
bogdanm	82:6473597d706e	392	(((TIMERID) == HRTIM_TIMERID_MASTER) \|\| \
bogdanm	82:6473597d706e	393	((TIMERID) == HRTIM_TIMERID_TIMER_A) \|\| \
bogdanm	82:6473597d706e	394	((TIMERID) == HRTIM_TIMERID_TIMER_B) \|\| \
bogdanm	82:6473597d706e	395	((TIMERID) == HRTIM_TIMERID_TIMER_C) \|\| \
bogdanm	82:6473597d706e	396	((TIMERID) == HRTIM_TIMERID_TIMER_D) \|\| \
bogdanm	82:6473597d706e	397	((TIMERID) == HRTIM_TIMERID_TIMER_E))
bogdanm	82:6473597d706e	398	/**
bogdanm	82:6473597d706e	399	* @}
bogdanm	82:6473597d706e	400	*/
bogdanm	82:6473597d706e	401
bogdanm	82:6473597d706e	402	/** @defgroup HRTIM_CompareUnit
bogdanm	82:6473597d706e	403	* @{
bogdanm	82:6473597d706e	404	* @brief Constants defining compare unit identifiers
bogdanm	82:6473597d706e	405	*/
bogdanm	82:6473597d706e	406	#define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /!< Compare unit 1 identifier /
bogdanm	82:6473597d706e	407	#define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /!< Compare unit 2 identifier /
bogdanm	82:6473597d706e	408	#define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /!< Compare unit 3 identifier /
bogdanm	82:6473597d706e	409	#define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /!< Compare unit 4 identifier /
bogdanm	82:6473597d706e	410
bogdanm	82:6473597d706e	411	#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
bogdanm	82:6473597d706e	412	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) \|\| \
bogdanm	82:6473597d706e	413	((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) \|\| \
bogdanm	82:6473597d706e	414	((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) \|\| \
bogdanm	82:6473597d706e	415	((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
bogdanm	82:6473597d706e	416	/**
bogdanm	82:6473597d706e	417	* @}
bogdanm	82:6473597d706e	418	*/
bogdanm	82:6473597d706e	419
bogdanm	82:6473597d706e	420	/** @defgroup HRTIM_CaptureUnit
bogdanm	82:6473597d706e	421	* @{
bogdanm	82:6473597d706e	422	* @brief Constants defining capture unit identifiers
bogdanm	82:6473597d706e	423	*/
bogdanm	82:6473597d706e	424	#define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /!< Capture unit 1 identifier /
bogdanm	82:6473597d706e	425	#define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /!< Capture unit 2 identifier /
bogdanm	82:6473597d706e	426
bogdanm	82:6473597d706e	427	#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
bogdanm	82:6473597d706e	428	(((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) \|\| \
bogdanm	82:6473597d706e	429	((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
bogdanm	82:6473597d706e	430	/**
bogdanm	82:6473597d706e	431	* @}
bogdanm	82:6473597d706e	432	*/
bogdanm	82:6473597d706e	433
bogdanm	82:6473597d706e	434	/** @defgroup HRTIM_TimerOutput
bogdanm	82:6473597d706e	435	* @{
bogdanm	82:6473597d706e	436	* @brief Constants defining timer output identifiers
bogdanm	82:6473597d706e	437	*/
bogdanm	82:6473597d706e	438	#define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /!< Timer A - Ouput 1 identifier /
bogdanm	82:6473597d706e	439	#define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /!< Timer A - Ouput 2 identifier /
bogdanm	82:6473597d706e	440	#define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /!< Timer B - Ouput 1 identifier /
bogdanm	82:6473597d706e	441	#define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /!< Timer B - Ouput 2 identifier /
bogdanm	82:6473597d706e	442	#define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /!< Timer C - Ouput 1 identifier /
bogdanm	82:6473597d706e	443	#define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /!< Timer C - Ouput 2 identifier /
bogdanm	82:6473597d706e	444	#define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /!< Timer D - Ouput 1 identifier /
bogdanm	82:6473597d706e	445	#define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /!< Timer D - Ouput 2 identifier /
bogdanm	82:6473597d706e	446	#define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /!< Timer E - Ouput 1 identifier /
bogdanm	82:6473597d706e	447	#define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /!< Timer E - Ouput 2 identifier /
bogdanm	82:6473597d706e	448
bogdanm	82:6473597d706e	449	#define IS_HRTIM_OUTPUT(OUTPUT)\
bogdanm	82:6473597d706e	450	(((OUTPUT) == HRTIM_OUTPUT_TA1) \|\| \
bogdanm	82:6473597d706e	451	((OUTPUT) == HRTIM_OUTPUT_TA2) \|\| \
bogdanm	82:6473597d706e	452	((OUTPUT) == HRTIM_OUTPUT_TB1) \|\| \
bogdanm	82:6473597d706e	453	((OUTPUT) == HRTIM_OUTPUT_TB2) \|\| \
bogdanm	82:6473597d706e	454	((OUTPUT) == HRTIM_OUTPUT_TC1) \|\| \
bogdanm	82:6473597d706e	455	((OUTPUT) == HRTIM_OUTPUT_TC2) \|\| \
bogdanm	82:6473597d706e	456	((OUTPUT) == HRTIM_OUTPUT_TD1) \|\| \
bogdanm	82:6473597d706e	457	((OUTPUT) == HRTIM_OUTPUT_TD2) \|\| \
bogdanm	82:6473597d706e	458	((OUTPUT) == HRTIM_OUTPUT_TE1) \|\| \
bogdanm	82:6473597d706e	459	((OUTPUT) == HRTIM_OUTPUT_TE2))
bogdanm	82:6473597d706e	460
bogdanm	82:6473597d706e	461	#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
bogdanm	82:6473597d706e	462	((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
bogdanm	82:6473597d706e	463	(((OUTPUT) == HRTIM_OUTPUT_TA1) \|\| \
bogdanm	82:6473597d706e	464	((OUTPUT) == HRTIM_OUTPUT_TA2))) \
bogdanm	82:6473597d706e	465	\|\| \
bogdanm	82:6473597d706e	466	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
bogdanm	82:6473597d706e	467	(((OUTPUT) == HRTIM_OUTPUT_TB1) \|\| \
bogdanm	82:6473597d706e	468	((OUTPUT) == HRTIM_OUTPUT_TB2))) \
bogdanm	82:6473597d706e	469	\|\| \
bogdanm	82:6473597d706e	470	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
bogdanm	82:6473597d706e	471	(((OUTPUT) == HRTIM_OUTPUT_TC1) \|\| \
bogdanm	82:6473597d706e	472	((OUTPUT) == HRTIM_OUTPUT_TC2))) \
bogdanm	82:6473597d706e	473	\|\| \
bogdanm	82:6473597d706e	474	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
bogdanm	82:6473597d706e	475	(((OUTPUT) == HRTIM_OUTPUT_TD1) \|\| \
bogdanm	82:6473597d706e	476	((OUTPUT) == HRTIM_OUTPUT_TD2))) \
bogdanm	82:6473597d706e	477	\|\| \
bogdanm	82:6473597d706e	478	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
bogdanm	82:6473597d706e	479	(((OUTPUT) == HRTIM_OUTPUT_TE1) \|\| \
bogdanm	82:6473597d706e	480	((OUTPUT) == HRTIM_OUTPUT_TE2))))
bogdanm	82:6473597d706e	481	/**
bogdanm	82:6473597d706e	482	* @}
bogdanm	82:6473597d706e	483	*/
bogdanm	82:6473597d706e	484
bogdanm	82:6473597d706e	485	/** @defgroup HRTIM_ADCTrigger
bogdanm	82:6473597d706e	486	* @{
bogdanm	82:6473597d706e	487	* @brief Constants defining ADC triggers identifiers
bogdanm	82:6473597d706e	488	*/
bogdanm	82:6473597d706e	489	#define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /!< ADC trigger 1 identifier /
bogdanm	82:6473597d706e	490	#define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /!< ADC trigger 1 identifier /
bogdanm	82:6473597d706e	491	#define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /!< ADC trigger 1 identifier /
bogdanm	82:6473597d706e	492	#define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /!< ADC trigger 1 identifier /
bogdanm	82:6473597d706e	493
bogdanm	82:6473597d706e	494	#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
bogdanm	82:6473597d706e	495	(((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) \|\| \
bogdanm	82:6473597d706e	496	((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) \|\| \
bogdanm	82:6473597d706e	497	((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) \|\| \
bogdanm	82:6473597d706e	498	((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
bogdanm	82:6473597d706e	499	/**
bogdanm	82:6473597d706e	500	* @}
bogdanm	82:6473597d706e	501	*/
bogdanm	82:6473597d706e	502
bogdanm	82:6473597d706e	503	/** @defgroup HRTIM_ExternalEventChannels
bogdanm	82:6473597d706e	504	* @{
bogdanm	82:6473597d706e	505	* @brief Constants defining external event channel identifiers
bogdanm	82:6473597d706e	506	*/
bogdanm	82:6473597d706e	507	#define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /!< Undefined event channel /
bogdanm	82:6473597d706e	508	#define HRTIM_EVENT_1 ((uint32_t)0x00000001) /!< External event channel 1 identifier /
bogdanm	82:6473597d706e	509	#define HRTIM_EVENT_2 ((uint32_t)0x00000002) /!< External event channel 2 identifier /
bogdanm	82:6473597d706e	510	#define HRTIM_EVENT_3 ((uint32_t)0x00000004) /!< External event channel 3 identifier /
bogdanm	82:6473597d706e	511	#define HRTIM_EVENT_4 ((uint32_t)0x00000008) /!< External event channel 4 identifier /
bogdanm	82:6473597d706e	512	#define HRTIM_EVENT_5 ((uint32_t)0x00000010) /!< External event channel 5 identifier /
bogdanm	82:6473597d706e	513	#define HRTIM_EVENT_6 ((uint32_t)0x00000020) /!< External event channel 6 identifier /
bogdanm	82:6473597d706e	514	#define HRTIM_EVENT_7 ((uint32_t)0x00000040) /!< External event channel 7 identifier /
bogdanm	82:6473597d706e	515	#define HRTIM_EVENT_8 ((uint32_t)0x00000080) /!< External event channel 8 identifier /
bogdanm	82:6473597d706e	516	#define HRTIM_EVENT_9 ((uint32_t)0x00000100) /!< External event channel 9 identifier /
bogdanm	82:6473597d706e	517	#define HRTIM_EVENT_10 ((uint32_t)0x00000200) /!< External event channel 10 identifier /
bogdanm	82:6473597d706e	518
bogdanm	82:6473597d706e	519	#define IS_HRTIM_EVENT(EVENT)\
bogdanm	82:6473597d706e	520	(((EVENT) == HRTIM_EVENT_1) \|\| \
bogdanm	82:6473597d706e	521	((EVENT) == HRTIM_EVENT_2) \|\| \
bogdanm	82:6473597d706e	522	((EVENT) == HRTIM_EVENT_3) \|\| \
bogdanm	82:6473597d706e	523	((EVENT) == HRTIM_EVENT_4) \|\| \
bogdanm	82:6473597d706e	524	((EVENT) == HRTIM_EVENT_5) \|\| \
bogdanm	82:6473597d706e	525	((EVENT) == HRTIM_EVENT_6) \|\| \
bogdanm	82:6473597d706e	526	((EVENT) == HRTIM_EVENT_7) \|\| \
bogdanm	82:6473597d706e	527	((EVENT) == HRTIM_EVENT_8) \|\| \
bogdanm	82:6473597d706e	528	((EVENT) == HRTIM_EVENT_9) \|\| \
bogdanm	82:6473597d706e	529	((EVENT) == HRTIM_EVENT_10))
bogdanm	82:6473597d706e	530	/**
bogdanm	82:6473597d706e	531	* @}
bogdanm	82:6473597d706e	532	*/
bogdanm	82:6473597d706e	533
bogdanm	82:6473597d706e	534	/** @defgroup HRTIM_FaultChannel
bogdanm	82:6473597d706e	535	* @{
bogdanm	82:6473597d706e	536	* @brief Constants defining fault channel identifiers
bogdanm	82:6473597d706e	537	*/
bogdanm	82:6473597d706e	538	#define HRTIM_FAULT_1 ((uint32_t)0x01) /!< Fault channel 1 identifier /
bogdanm	82:6473597d706e	539	#define HRTIM_FAULT_2 ((uint32_t)0x02) /!< Fault channel 2 identifier /
bogdanm	82:6473597d706e	540	#define HRTIM_FAULT_3 ((uint32_t)0x04) /!< Fault channel 3 identifier /
bogdanm	82:6473597d706e	541	#define HRTIM_FAULT_4 ((uint32_t)0x08) /!< Fault channel 4 identifier /
bogdanm	82:6473597d706e	542	#define HRTIM_FAULT_5 ((uint32_t)0x10) /!< Fault channel 5 identifier /
bogdanm	82:6473597d706e	543
bogdanm	82:6473597d706e	544	#define IS_HRTIM_FAULT(FAULT)\
bogdanm	82:6473597d706e	545	(((FAULT) == HRTIM_FAULT_1) \|\| \
bogdanm	82:6473597d706e	546	((FAULT) == HRTIM_FAULT_2) \|\| \
bogdanm	82:6473597d706e	547	((FAULT) == HRTIM_FAULT_3) \|\| \
bogdanm	82:6473597d706e	548	((FAULT) == HRTIM_FAULT_4) \|\| \
bogdanm	82:6473597d706e	549	((FAULT) == HRTIM_FAULT_5))
bogdanm	82:6473597d706e	550	/**
bogdanm	82:6473597d706e	551	* @}
bogdanm	82:6473597d706e	552	*/
bogdanm	82:6473597d706e	553
bogdanm	82:6473597d706e	554
bogdanm	82:6473597d706e	555	/** @defgroup HRTIM_PrescalerRatio
bogdanm	82:6473597d706e	556	* @{
bogdanm	82:6473597d706e	557	* @brief Constants defining timer high-resolution clock prescaler ratio.
bogdanm	82:6473597d706e	558	*/
bogdanm	82:6473597d706e	559	#define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) /
bogdanm	82:6473597d706e	560	#define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) /
bogdanm	82:6473597d706e	561	#define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) /
bogdanm	82:6473597d706e	562	#define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) /
bogdanm	82:6473597d706e	563	#define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) /
bogdanm	82:6473597d706e	564	#define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) /
bogdanm	82:6473597d706e	565	#define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) /
bogdanm	82:6473597d706e	566	#define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) /
bogdanm	82:6473597d706e	567
bogdanm	82:6473597d706e	568	#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
bogdanm	82:6473597d706e	569	(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) \|\| \
bogdanm	82:6473597d706e	570	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) \|\| \
bogdanm	82:6473597d706e	571	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) \|\| \
bogdanm	82:6473597d706e	572	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) \|\| \
bogdanm	82:6473597d706e	573	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) \|\| \
bogdanm	82:6473597d706e	574	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) \|\| \
bogdanm	82:6473597d706e	575	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) \|\| \
bogdanm	82:6473597d706e	576	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
bogdanm	82:6473597d706e	577	/**
bogdanm	82:6473597d706e	578	* @}
bogdanm	82:6473597d706e	579	*/
bogdanm	82:6473597d706e	580
bogdanm	82:6473597d706e	581	/** @defgroup HRTIM_Mode
bogdanm	82:6473597d706e	582	* @{
bogdanm	82:6473597d706e	583	* @brief Constants defining timer counter operating mode.
bogdanm	82:6473597d706e	584	*/
bogdanm	82:6473597d706e	585	#define HRTIM_MODE_CONTINOUS ((uint32_t)0x00000008) /!< The timer operates in continuous (free-running) mode /
bogdanm	82:6473597d706e	586	#define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /!< The timer operates in non retriggerable single-shot mode /
bogdanm	82:6473597d706e	587	#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /!< The timer operates in retriggerable single-shot mode /
bogdanm	82:6473597d706e	588
bogdanm	82:6473597d706e	589	#define IS_HRTIM_MODE(MODE)\
bogdanm	82:6473597d706e	590	(((MODE) == HRTIM_MODE_CONTINOUS) \|\| \
bogdanm	82:6473597d706e	591	((MODE) == HRTIM_MODE_SINGLESHOT) \|\| \
bogdanm	82:6473597d706e	592	((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
bogdanm	82:6473597d706e	593
bogdanm	82:6473597d706e	594	#define IS_HRTIM_MODE_ONEPULSE(MODE)\
bogdanm	82:6473597d706e	595	(((MODE) == HRTIM_MODE_SINGLESHOT) \|\| \
bogdanm	82:6473597d706e	596	((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
bogdanm	82:6473597d706e	597
bogdanm	82:6473597d706e	598	/**
bogdanm	82:6473597d706e	599	* @}
bogdanm	82:6473597d706e	600	*/
bogdanm	82:6473597d706e	601
bogdanm	82:6473597d706e	602	/** @defgroup HRTIM_HalfModeEnable
bogdanm	82:6473597d706e	603	* @{
bogdanm	82:6473597d706e	604	* @brief Constants defining half mode enabling status.
bogdanm	82:6473597d706e	605	*/
bogdanm	82:6473597d706e	606	#define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /!< Half mode is disabled /
bogdanm	82:6473597d706e	607	#define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /!< Half mode is enabled /
bogdanm	82:6473597d706e	608
bogdanm	82:6473597d706e	609	#define IS_HRTIM_HALFMODE(HALFMODE)\
bogdanm	82:6473597d706e	610	(((HALFMODE) == HRTIM_HALFMODE_DISABLED) \|\| \
bogdanm	82:6473597d706e	611	((HALFMODE) == HRTIM_HALFMODE_ENABLED))
bogdanm	82:6473597d706e	612	/**
bogdanm	82:6473597d706e	613	* @}
bogdanm	82:6473597d706e	614	*/
bogdanm	82:6473597d706e	615
bogdanm	82:6473597d706e	616	/** @defgroup HRTIM_StartOnSyncInputEvent
bogdanm	82:6473597d706e	617	* @{
bogdanm	82:6473597d706e	618	* @brief Constants defining the timer behavior following the synchronization event
bogdanm	82:6473597d706e	619	*/
bogdanm	82:6473597d706e	620	#define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /!< Synchronization input event has effect on the timer /
bogdanm	82:6473597d706e	621	#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /!< Synchronization input event starts the timer /
bogdanm	82:6473597d706e	622
bogdanm	82:6473597d706e	623	#define IS_HRTIM_SYNCSTART(SYNCSTART)\
bogdanm	82:6473597d706e	624	(((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) \|\| \
bogdanm	82:6473597d706e	625	((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
bogdanm	82:6473597d706e	626	/**
bogdanm	82:6473597d706e	627	* @}
bogdanm	82:6473597d706e	628	*/
bogdanm	82:6473597d706e	629
bogdanm	82:6473597d706e	630	/** @defgroup HRTIM_ResetOnSyncInputEvent
bogdanm	82:6473597d706e	631	* @{
bogdanm	82:6473597d706e	632	* @brief Constants defining the timer behavior following the synchronization event
bogdanm	82:6473597d706e	633	*/
bogdanm	82:6473597d706e	634	#define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /!< Synchronization input event has effect on the timer /
bogdanm	82:6473597d706e	635	#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /!< Synchronization input event resets the timer /
bogdanm	82:6473597d706e	636
bogdanm	82:6473597d706e	637	#define IS_HRTIM_SYNCRESET(SYNCRESET)\
bogdanm	82:6473597d706e	638	(((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) \|\| \
bogdanm	82:6473597d706e	639	((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
bogdanm	82:6473597d706e	640	/**
bogdanm	82:6473597d706e	641	* @}
bogdanm	82:6473597d706e	642	*/
bogdanm	82:6473597d706e	643
bogdanm	82:6473597d706e	644	/** @defgroup HRTIM_DACSynchronization
bogdanm	82:6473597d706e	645	* @{
bogdanm	82:6473597d706e	646	* @brief Constants defining on which output the DAC synchronization event is sent
bogdanm	82:6473597d706e	647	*/
bogdanm	82:6473597d706e	648	#define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /!< No DAC synchronization event generated /
bogdanm	82:6473597d706e	649	#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /!< DAC synchronization event generated on DACTrigOut1 output upon timer update /
bogdanm	82:6473597d706e	650	#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /!< DAC synchronization event generated on DACTrigOut2 output upon timer update /
bogdanm	82:6473597d706e	651	#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 \| HRTIM_MCR_DACSYNC_0) /!< DAC update generated on DACTrigOut3 output upon timer update /
bogdanm	82:6473597d706e	652
bogdanm	82:6473597d706e	653	#define IS_HRTIM_DACSYNC(DACSYNC)\
bogdanm	82:6473597d706e	654	(((DACSYNC) == HRTIM_DACSYNC_NONE) \|\| \
bogdanm	82:6473597d706e	655	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) \|\| \
bogdanm	82:6473597d706e	656	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) \|\| \
bogdanm	82:6473597d706e	657	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
bogdanm	82:6473597d706e	658	/**
bogdanm	82:6473597d706e	659	* @}
bogdanm	82:6473597d706e	660	*/
bogdanm	82:6473597d706e	661
bogdanm	82:6473597d706e	662	/** @defgroup HRTIM_RegisterPreloadEnable
bogdanm	82:6473597d706e	663	* @{
bogdanm	82:6473597d706e	664	* @brief Constants defining whether a write access into a preloadable
bogdanm	82:6473597d706e	665	* register is done into the active or the preload register.
bogdanm	82:6473597d706e	666	*/
bogdanm	82:6473597d706e	667	#define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /!< Preload disabled: the write access is directly done into the active register /
bogdanm	82:6473597d706e	668	#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /!< Preload enabled: the write access is done into the preload register /
bogdanm	82:6473597d706e	669
bogdanm	82:6473597d706e	670	#define IS_HRTIM_PRELOAD(PRELOAD)\
bogdanm	82:6473597d706e	671	(((PRELOAD) == HRTIM_PRELOAD_DISABLED) \|\| \
bogdanm	82:6473597d706e	672	((PRELOAD) == HRTIM_PRELOAD_ENABLED))
bogdanm	82:6473597d706e	673	/**
bogdanm	82:6473597d706e	674	* @}
bogdanm	82:6473597d706e	675	*/
bogdanm	82:6473597d706e	676
bogdanm	82:6473597d706e	677	/** @defgroup HRTIM_UpdateGating
bogdanm	82:6473597d706e	678	* @{
bogdanm	82:6473597d706e	679	* @brief Constants defining how the update occurs relatively to the burst DMA
bogdanm	82:6473597d706e	680	* transaction and the external update request on update enable inputs 1 to 3.
bogdanm	82:6473597d706e	681	*/
bogdanm	82:6473597d706e	682	#define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /!< Update done independently from the DMA burst transfer completion /
bogdanm	82:6473597d706e	683	#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /!< Update done when the DMA burst transfer is completed /
bogdanm	82:6473597d706e	684	#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /!< Update done on timer roll-over following a DMA burst transfer completion/
bogdanm	82:6473597d706e	685	#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 /
bogdanm	82:6473597d706e	686	#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 /
bogdanm	82:6473597d706e	687	#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 /
bogdanm	82:6473597d706e	688	#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 /
bogdanm	82:6473597d706e	689	#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 /
bogdanm	82:6473597d706e	690	#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 /
bogdanm	82:6473597d706e	691
bogdanm	82:6473597d706e	692	#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
bogdanm	82:6473597d706e	693	(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) \|\| \
bogdanm	82:6473597d706e	694	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) \|\| \
bogdanm	82:6473597d706e	695	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
bogdanm	82:6473597d706e	696
bogdanm	82:6473597d706e	697	#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
bogdanm	82:6473597d706e	698	(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) \|\| \
bogdanm	82:6473597d706e	699	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) \|\| \
bogdanm	82:6473597d706e	700	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) \|\| \
bogdanm	82:6473597d706e	701	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) \|\| \
bogdanm	82:6473597d706e	702	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) \|\| \
bogdanm	82:6473597d706e	703	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) \|\| \
bogdanm	82:6473597d706e	704	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) \|\| \
bogdanm	82:6473597d706e	705	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) \|\| \
bogdanm	82:6473597d706e	706	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
bogdanm	82:6473597d706e	707	/**
bogdanm	82:6473597d706e	708	* @}
bogdanm	82:6473597d706e	709	*/
bogdanm	82:6473597d706e	710
bogdanm	82:6473597d706e	711	/** @defgroup HRTIM_TimerBurstMode
bogdanm	82:6473597d706e	712	* @{
bogdanm	82:6473597d706e	713	* @brief Constants defining how the timer behaves during a burst
bogdanm	82:6473597d706e	714	mode operation.
bogdanm	82:6473597d706e	715	*/
bogdanm	82:6473597d706e	716	#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /!< Timer counter clock is maintained and the timer operates normally /
bogdanm	82:6473597d706e	717	#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /!< Timer counter clock is stopped and the counter is reset /
bogdanm	82:6473597d706e	718
bogdanm	82:6473597d706e	719	#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
bogdanm	82:6473597d706e	720	(((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) \|\| \
bogdanm	82:6473597d706e	721	((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
bogdanm	82:6473597d706e	722	/**
bogdanm	82:6473597d706e	723	* @}
bogdanm	82:6473597d706e	724	*/
bogdanm	82:6473597d706e	725
bogdanm	82:6473597d706e	726	/** @defgroup HRTIM_TimerRepetitionUpdate
bogdanm	82:6473597d706e	727	* @{
bogdanm	82:6473597d706e	728	* @brief Constants defining whether registers are updated when the timer
bogdanm	82:6473597d706e	729	* repetition period is completed (either due to roll-over or
bogdanm	82:6473597d706e	730	* reset events)
bogdanm	82:6473597d706e	731	*/
bogdanm	82:6473597d706e	732	#define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /!< Update on repetition disabled /
bogdanm	82:6473597d706e	733	#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /!< Update on repetition enabled /
bogdanm	82:6473597d706e	734
bogdanm	82:6473597d706e	735	#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
bogdanm	82:6473597d706e	736	(((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) \|\| \
bogdanm	82:6473597d706e	737	((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
bogdanm	82:6473597d706e	738	/**
bogdanm	82:6473597d706e	739	* @}
bogdanm	82:6473597d706e	740	*/
bogdanm	82:6473597d706e	741
bogdanm	82:6473597d706e	742
bogdanm	82:6473597d706e	743	/** @defgroup HRTIM_TimerPushPullMode
bogdanm	82:6473597d706e	744	* @{
bogdanm	82:6473597d706e	745	* @brief Constants defining whether or not the push-pull mode is enabled for
bogdanm	82:6473597d706e	746	* a timer.
bogdanm	82:6473597d706e	747	*/
bogdanm	82:6473597d706e	748	#define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /!< Push-Pull mode disabled /
bogdanm	82:6473597d706e	749	#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /!< Push-Pull mode enabled /
bogdanm	82:6473597d706e	750
bogdanm	82:6473597d706e	751	#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
bogdanm	82:6473597d706e	752	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) \|\| \
bogdanm	82:6473597d706e	753	((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
bogdanm	82:6473597d706e	754	/**
bogdanm	82:6473597d706e	755	* @}
bogdanm	82:6473597d706e	756	*/
bogdanm	82:6473597d706e	757
bogdanm	82:6473597d706e	758	/** @defgroup HRTIM_TimerFaultEnabling
bogdanm	82:6473597d706e	759	* @{
bogdanm	82:6473597d706e	760	* @brief Constants defining whether a faut channel is enabled for a timer
bogdanm	82:6473597d706e	761	*/
bogdanm	82:6473597d706e	762	#define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /!< No fault enabled /
bogdanm	82:6473597d706e	763	#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /!< Fault 1 enabled /
bogdanm	82:6473597d706e	764	#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /!< Fault 2 enabled /
bogdanm	82:6473597d706e	765	#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /!< Fault 3 enabled /
bogdanm	82:6473597d706e	766	#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /!< Fault 4 enabled /
bogdanm	82:6473597d706e	767	#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /!< Fault 5 enabled /
bogdanm	82:6473597d706e	768
bogdanm	82:6473597d706e	769	#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
bogdanm	82:6473597d706e	770
bogdanm	82:6473597d706e	771	/**
bogdanm	82:6473597d706e	772	* @}
bogdanm	82:6473597d706e	773	*/
bogdanm	82:6473597d706e	774
bogdanm	82:6473597d706e	775	/** @defgroup HRTIM_TimerFaultLock
bogdanm	82:6473597d706e	776	* @{
bogdanm	82:6473597d706e	777	* @brief Constants defining whether or not fault enabling bits are write
bogdanm	82:6473597d706e	778	* protected for a timer
bogdanm	82:6473597d706e	779	*/
bogdanm	82:6473597d706e	780	#define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /!< Timer fault enabling bits are read/write /
bogdanm	82:6473597d706e	781	#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTCLK) /!< Timer fault enabling bits are read only /
bogdanm	82:6473597d706e	782
bogdanm	82:6473597d706e	783	#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
bogdanm	82:6473597d706e	784	(((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) \|\| \
bogdanm	82:6473597d706e	785	((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
bogdanm	82:6473597d706e	786	/**
bogdanm	82:6473597d706e	787	* @}
bogdanm	82:6473597d706e	788	*/
bogdanm	82:6473597d706e	789
bogdanm	82:6473597d706e	790	/** @defgroup HRTIM_TimerDeadtimeInsertion
bogdanm	82:6473597d706e	791	* @{
bogdanm	82:6473597d706e	792	* @brief Constants defining whether or not fault the dead time insertion
bogdanm	82:6473597d706e	793	* feature is enabled for a timer
bogdanm	82:6473597d706e	794	*/
bogdanm	82:6473597d706e	795	#define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /!< Output 1 and output 2 signals are independent /
bogdanm	82:6473597d706e	796	#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /!< Deadtime is inserted between output 1 and output 2 /
bogdanm	82:6473597d706e	797
bogdanm	82:6473597d706e	798	#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMDEADTIMEINSERTION)\
bogdanm	82:6473597d706e	799	(((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) \|\| \
bogdanm	82:6473597d706e	800	((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))
bogdanm	82:6473597d706e	801	/**
bogdanm	82:6473597d706e	802	* @}
bogdanm	82:6473597d706e	803	*/
bogdanm	82:6473597d706e	804
bogdanm	82:6473597d706e	805	/** @defgroup HRTIM_TimerDelayedProtectionMode
bogdanm	82:6473597d706e	806	* @{
bogdanm	82:6473597d706e	807	* @brief Constants defining all possible delayed protection modes
bogdanm	82:6473597d706e	808	* for a timer. Also define the source and outputs on which the delayed
bogdanm	82:6473597d706e	809	* protection schemes are applied
bogdanm	82:6473597d706e	810	*/
bogdanm	82:6473597d706e	811	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /!< No action /
bogdanm	82:6473597d706e	812	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) /!< Output 1 delayed Idle on external Event 6 or 8 /
bogdanm	82:6473597d706e	813	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Output 2 delayed Idle on external Event 6 or 8 /
bogdanm	82:6473597d706e	814	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Output 1 and output 2 delayed Idle on external Event 6 or 8 /
bogdanm	82:6473597d706e	815	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Balanced Idle on external Event 6 or 8 /
bogdanm	82:6473597d706e	816	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRTEN) /!< Output 1 delayed Idle on external Event 7 or 9 /
bogdanm	82:6473597d706e	817	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Output 2 delayed Idle on external Event 7 or 9 /
bogdanm	82:6473597d706e	818	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Output 1 and output2 delayed Idle on external Event 7 or 9 /
bogdanm	82:6473597d706e	819	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Balanced Idle on external Event 7 or 9 /
bogdanm	82:6473597d706e	820
bogdanm	82:6473597d706e	821	#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMDELAYEDPROTECTION)\
bogdanm	82:6473597d706e	822	(((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) \|\| \
bogdanm	82:6473597d706e	823	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) \|\| \
bogdanm	82:6473597d706e	824	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) \|\| \
bogdanm	82:6473597d706e	825	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) \|\| \
bogdanm	82:6473597d706e	826	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) \|\| \
bogdanm	82:6473597d706e	827	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) \|\| \
bogdanm	82:6473597d706e	828	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) \|\| \
bogdanm	82:6473597d706e	829	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79) \|\| \
bogdanm	82:6473597d706e	830	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79))
bogdanm	82:6473597d706e	831	/**
bogdanm	82:6473597d706e	832	* @}
bogdanm	82:6473597d706e	833	*/
bogdanm	82:6473597d706e	834
bogdanm	82:6473597d706e	835	/** @defgroup HRTIM_TimerUpdateTrigger
bogdanm	82:6473597d706e	836	* @{
bogdanm	82:6473597d706e	837	* @brief Constants defining whether the registers update is done synchronously
bogdanm	82:6473597d706e	838	* with any other timer or master update
bogdanm	82:6473597d706e	839	*/
bogdanm	82:6473597d706e	840	#define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /!< Register update is disabled /
bogdanm	82:6473597d706e	841	#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /!< Register update is triggered by the master timer update /
bogdanm	82:6473597d706e	842	#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /!< Register update is triggered by the timer A update /
bogdanm	82:6473597d706e	843	#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /!< Register update is triggered by the timer B update /
bogdanm	82:6473597d706e	844	#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /!< Register update is triggered by the timer C update/
bogdanm	82:6473597d706e	845	#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /!< Register update is triggered by the timer D update /
bogdanm	82:6473597d706e	846	#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /!< Register update is triggered by the timer E update /
bogdanm	82:6473597d706e	847
bogdanm	82:6473597d706e	848	#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
bogdanm	82:6473597d706e	849	/**
bogdanm	82:6473597d706e	850	* @}
bogdanm	82:6473597d706e	851	*/
bogdanm	82:6473597d706e	852
bogdanm	82:6473597d706e	853	/** @defgroup HRTIM_TimerResetTrigger
bogdanm	82:6473597d706e	854	* @{
bogdanm	82:6473597d706e	855	* @brief Constants defining the events that can be selected to trigger the reset
bogdanm	82:6473597d706e	856	* of the timer counter
bogdanm	82:6473597d706e	857	*/
bogdanm	82:6473597d706e	858	#define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /!< No counter reset trigger /
bogdanm	82:6473597d706e	859	#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /!< The timer counter is reset upon update event /
bogdanm	82:6473597d706e	860	#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /!< The timer counter is reset upon Timer Compare 2 event /
bogdanm	82:6473597d706e	861	#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /!< The timer counter is reset upon Timer Compare 4 event /
bogdanm	82:6473597d706e	862	#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /!< The timer counter is reset upon master timer period event /
bogdanm	82:6473597d706e	863	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /!< The timer counter is reset upon master timer Compare 1 event /
bogdanm	82:6473597d706e	864	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /!< The timer counter is reset upon master timer Compare 2 event /
bogdanm	82:6473597d706e	865	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /!< The timer counter is reset upon master timer Compare 3 event /
bogdanm	82:6473597d706e	866	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /!< The timer counter is reset upon master timer Compare 4 event /
bogdanm	82:6473597d706e	867	#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /!< The timer counter is reset upon external event 1 /
bogdanm	82:6473597d706e	868	#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /!< The timer counter is reset upon external event 2 /
bogdanm	82:6473597d706e	869	#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /!< The timer counter is reset upon external event 3 /
bogdanm	82:6473597d706e	870	#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /!< The timer counter is reset upon external event 4 /
bogdanm	82:6473597d706e	871	#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /!< The timer counter is reset upon external event 5 /
bogdanm	82:6473597d706e	872	#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /!< The timer counter is reset upon external event 6 /
bogdanm	82:6473597d706e	873	#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /!< The timer counter is reset upon external event 7 /
bogdanm	82:6473597d706e	874	#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /!< The timer counter is reset upon external event 8 /
bogdanm	82:6473597d706e	875	#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /!< The timer counter is reset upon external event 9 /
bogdanm	82:6473597d706e	876	#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /!< The timer counter is reset upon external event 10 /
bogdanm	82:6473597d706e	877	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
bogdanm	82:6473597d706e	878	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
bogdanm	82:6473597d706e	879	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
bogdanm	82:6473597d706e	880	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
bogdanm	82:6473597d706e	881	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
bogdanm	82:6473597d706e	882	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
bogdanm	82:6473597d706e	883	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
bogdanm	82:6473597d706e	884	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
bogdanm	82:6473597d706e	885	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
bogdanm	82:6473597d706e	886	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /!< The timer counter is reset upon other timer Compare 1 event /
bogdanm	82:6473597d706e	887	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /!< The timer counter is reset upon other timer Compare 2 event /
bogdanm	82:6473597d706e	888	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /!< The timer counter is reset upon other timer Compare 4 event /
bogdanm	82:6473597d706e	889
bogdanm	82:6473597d706e	890	#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
bogdanm	82:6473597d706e	891
bogdanm	82:6473597d706e	892	/**
bogdanm	82:6473597d706e	893	* @}
bogdanm	82:6473597d706e	894	*/
bogdanm	82:6473597d706e	895
bogdanm	82:6473597d706e	896	/** @defgroup HRTIM_TimerResetUpdate
bogdanm	82:6473597d706e	897	* @{
bogdanm	82:6473597d706e	898	* @brief Constants defining whether the register are updated upon Timerx
bogdanm	82:6473597d706e	899	* counter reset or rollover to 0 after reaching the period value
bogdanm	82:6473597d706e	900	* in continuous mode
bogdanm	82:6473597d706e	901	*/
bogdanm	82:6473597d706e	902	#define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /!< Update by timer x reset / rollover disabled /
bogdanm	82:6473597d706e	903	#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /!< Update by timer x reset / rollover enabled /
bogdanm	82:6473597d706e	904
bogdanm	82:6473597d706e	905	#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
bogdanm	82:6473597d706e	906	(((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) \|\| \
bogdanm	82:6473597d706e	907	((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
bogdanm	82:6473597d706e	908	/**
bogdanm	82:6473597d706e	909	* @}
bogdanm	82:6473597d706e	910	*/
bogdanm	82:6473597d706e	911
bogdanm	82:6473597d706e	912	/** @defgroup HRTIM_CompareUnitAutoDelayedMode
bogdanm	82:6473597d706e	913	* @{
bogdanm	82:6473597d706e	914	* @brief Constants defining whether the compare register is behaving in
bogdanm	82:6473597d706e	915	* regular mode (compare match issued as soon as counter equal compare),
bogdanm	82:6473597d706e	916	* or in auto-delayed mode
bogdanm	82:6473597d706e	917	*/
bogdanm	82:6473597d706e	918	#define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /!< standard compare mode /
bogdanm	82:6473597d706e	919	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated only if a capture has occured /
bogdanm	82:6473597d706e	920	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) /
bogdanm	82:6473597d706e	921	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 \| HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) /
bogdanm	82:6473597d706e	922
bogdanm	82:6473597d706e	923	#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
bogdanm	82:6473597d706e	924	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
bogdanm	82:6473597d706e	925	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
bogdanm	82:6473597d706e	926	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
bogdanm	82:6473597d706e	927	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
bogdanm	82:6473597d706e	928
bogdanm	82:6473597d706e	929	/* Auto delayed mode is only available for compare units 2 and 4 */
bogdanm	82:6473597d706e	930	#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
bogdanm	82:6473597d706e	931	((((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) && \
bogdanm	82:6473597d706e	932	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
bogdanm	82:6473597d706e	933	\|\| \
bogdanm	82:6473597d706e	934	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
bogdanm	82:6473597d706e	935	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
bogdanm	82:6473597d706e	936	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
bogdanm	82:6473597d706e	937	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
bogdanm	82:6473597d706e	938	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
bogdanm	82:6473597d706e	939	\|\| \
bogdanm	82:6473597d706e	940	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) && \
bogdanm	82:6473597d706e	941	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
bogdanm	82:6473597d706e	942	\|\| \
bogdanm	82:6473597d706e	943	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
bogdanm	82:6473597d706e	944	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
bogdanm	82:6473597d706e	945	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
bogdanm	82:6473597d706e	946	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
bogdanm	82:6473597d706e	947	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
bogdanm	82:6473597d706e	948	/**
bogdanm	82:6473597d706e	949	* @}
bogdanm	82:6473597d706e	950	*/
bogdanm	82:6473597d706e	951
bogdanm	82:6473597d706e	952	/** @defgroup HRTIM_BasicOCMode
bogdanm	82:6473597d706e	953	* @{
bogdanm	82:6473597d706e	954	* @brief Constants defining the behavior of the output signal when the timer
bogdanm	82:6473597d706e	955	operates in basic output compare mode
bogdanm	82:6473597d706e	956	*/
bogdanm	82:6473597d706e	957	#define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /!< Output toggles when the timer counter reaches the compare value /
bogdanm	82:6473597d706e	958	#define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /!< Output forced to active level when the timer counter reaches the compare value /
bogdanm	82:6473597d706e	959	#define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /!< Output forced to inactive level when the timer counter reaches the compare value /
bogdanm	82:6473597d706e	960
bogdanm	82:6473597d706e	961	#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
bogdanm	82:6473597d706e	962	(((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) \|\| \
bogdanm	82:6473597d706e	963	((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) \|\| \
bogdanm	82:6473597d706e	964	((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
bogdanm	82:6473597d706e	965	/**
bogdanm	82:6473597d706e	966	* @}
bogdanm	82:6473597d706e	967	*/
bogdanm	82:6473597d706e	968
bogdanm	82:6473597d706e	969	/** @defgroup HRTIM_OutputPolarity
bogdanm	82:6473597d706e	970	* @{
bogdanm	82:6473597d706e	971	* @brief Constants defining the polarity of a timer output
bogdanm	82:6473597d706e	972	*/
bogdanm	82:6473597d706e	973	#define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /!< Output is active HIGH /
bogdanm	82:6473597d706e	974	#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /!< Output is active LOW /
bogdanm	82:6473597d706e	975
bogdanm	82:6473597d706e	976	#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
bogdanm	82:6473597d706e	977	(((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) \|\| \
bogdanm	82:6473597d706e	978	((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
bogdanm	82:6473597d706e	979	/**
bogdanm	82:6473597d706e	980	* @}
bogdanm	82:6473597d706e	981	*/
bogdanm	82:6473597d706e	982
bogdanm	82:6473597d706e	983	/** @defgroup HRTIM_OutputSetSource
bogdanm	82:6473597d706e	984	* @{
bogdanm	82:6473597d706e	985	* @brief Constants defining the events that can be selected to configure the
bogdanm	82:6473597d706e	986	* set crossbar of a timer output
bogdanm	82:6473597d706e	987	*/
bogdanm	82:6473597d706e	988	#define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /!< Reset the output set crossbar /
bogdanm	82:6473597d706e	989	#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces the output to its active state /
bogdanm	82:6473597d706e	990	#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /!< Timer period event forces the output to its active state /
bogdanm	82:6473597d706e	991	#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /!< Timer compare 1 event forces the output to its active state /
bogdanm	82:6473597d706e	992	#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /!< Timer compare 2 event forces the output to its active state /
bogdanm	82:6473597d706e	993	#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /!< Timer compare 3 event forces the output to its active state /
bogdanm	82:6473597d706e	994	#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /!< Timer compare 4 event forces the output to its active state /
bogdanm	82:6473597d706e	995	#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /!< The master timer period event forces the output to its active state /
bogdanm	82:6473597d706e	996	#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /!< Master Timer compare 1 event forces the output to its active state /
bogdanm	82:6473597d706e	997	#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /!< Master Timer compare 2 event forces the output to its active state /
bogdanm	82:6473597d706e	998	#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /!< Master Timer compare 3 event forces the output to its active state /
bogdanm	82:6473597d706e	999	#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /!< Master Timer compare 4 event forces the output to its active state /
bogdanm	82:6473597d706e	1000	#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
bogdanm	82:6473597d706e	1001	#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
bogdanm	82:6473597d706e	1002	#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
bogdanm	82:6473597d706e	1003	#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
bogdanm	82:6473597d706e	1004	#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
bogdanm	82:6473597d706e	1005	#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
bogdanm	82:6473597d706e	1006	#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
bogdanm	82:6473597d706e	1007	#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
bogdanm	82:6473597d706e	1008	#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
bogdanm	82:6473597d706e	1009	#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /!< External event 1 forces the output to its active state /
bogdanm	82:6473597d706e	1010	#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /!< External event 2 forces the output to its active state /
bogdanm	82:6473597d706e	1011	#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /!< External event 3 forces the output to its active state /
bogdanm	82:6473597d706e	1012	#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /!< External event 4 forces the output to its active state /
bogdanm	82:6473597d706e	1013	#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /!< External event 5 forces the output to its active state /
bogdanm	82:6473597d706e	1014	#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /!< External event 6 forces the output to its active state /
bogdanm	82:6473597d706e	1015	#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /!< External event 7 forces the output to its active state /
bogdanm	82:6473597d706e	1016	#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /!< External event 8 forces the output to its active state /
bogdanm	82:6473597d706e	1017	#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /!< External event 9 forces the output to its active state /
bogdanm	82:6473597d706e	1018	#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /!< External event 10 forces the output to its active state /
bogdanm	82:6473597d706e	1019	#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /!< Timer register update event forces the output to its active state /
bogdanm	82:6473597d706e	1020
bogdanm	82:6473597d706e	1021	#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
bogdanm	82:6473597d706e	1022	(((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) \|\| \
bogdanm	82:6473597d706e	1023	((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) \|\| \
bogdanm	82:6473597d706e	1024	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) \|\| \
bogdanm	82:6473597d706e	1025	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) \|\| \
bogdanm	82:6473597d706e	1026	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) \|\| \
bogdanm	82:6473597d706e	1027	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) \|\| \
bogdanm	82:6473597d706e	1028	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) \|\| \
bogdanm	82:6473597d706e	1029	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) \|\| \
bogdanm	82:6473597d706e	1030	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) \|\| \
bogdanm	82:6473597d706e	1031	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) \|\| \
bogdanm	82:6473597d706e	1032	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) \|\| \
bogdanm	82:6473597d706e	1033	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) \|\| \
bogdanm	82:6473597d706e	1034	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) \|\| \
bogdanm	82:6473597d706e	1035	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) \|\| \
bogdanm	82:6473597d706e	1036	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) \|\| \
bogdanm	82:6473597d706e	1037	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) \|\| \
bogdanm	82:6473597d706e	1038	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) \|\| \
bogdanm	82:6473597d706e	1039	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) \|\| \
bogdanm	82:6473597d706e	1040	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) \|\| \
bogdanm	82:6473597d706e	1041	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) \|\| \
bogdanm	82:6473597d706e	1042	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) \|\| \
bogdanm	82:6473597d706e	1043	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) \|\| \
bogdanm	82:6473597d706e	1044	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) \|\| \
bogdanm	82:6473597d706e	1045	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) \|\| \
bogdanm	82:6473597d706e	1046	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) \|\| \
bogdanm	82:6473597d706e	1047	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) \|\| \
bogdanm	82:6473597d706e	1048	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) \|\| \
bogdanm	82:6473597d706e	1049	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) \|\| \
bogdanm	82:6473597d706e	1050	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) \|\| \
bogdanm	82:6473597d706e	1051	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) \|\| \
bogdanm	82:6473597d706e	1052	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) \|\| \
bogdanm	82:6473597d706e	1053	((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
bogdanm	82:6473597d706e	1054	/**
bogdanm	82:6473597d706e	1055	* @}
bogdanm	82:6473597d706e	1056	*/
bogdanm	82:6473597d706e	1057
bogdanm	82:6473597d706e	1058	/** @defgroup HRTIM_OutputResetSource
bogdanm	82:6473597d706e	1059	* @{
bogdanm	82:6473597d706e	1060	* @brief Constants defining the events that can be selected to configure the
bogdanm	82:6473597d706e	1061	* set crossbar of a timer output
bogdanm	82:6473597d706e	1062	*/
bogdanm	82:6473597d706e	1063	#define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /!< Reset the output reset crossbar /
bogdanm	82:6473597d706e	1064	#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state /
bogdanm	82:6473597d706e	1065	#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /!< Timer period event forces the output to its inactive state /
bogdanm	82:6473597d706e	1066	#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /!< Timer compare 1 event forces the output to its inactive state /
bogdanm	82:6473597d706e	1067	#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /!< Timer compare 2 event forces the output to its inactive state /
bogdanm	82:6473597d706e	1068	#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /!< Timer compare 3 event forces the output to its inactive state /
bogdanm	82:6473597d706e	1069	#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /!< Timer compare 4 event forces the output to its inactive state /
bogdanm	82:6473597d706e	1070	#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /!< The master timer period event forces the output to its inactive state /
bogdanm	82:6473597d706e	1071	#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /!< Master Timer compare 1 event forces the output to its inactive state /
bogdanm	82:6473597d706e	1072	#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /!< Master Timer compare 2 event forces the output to its inactive state /
bogdanm	82:6473597d706e	1073	#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /!< Master Timer compare 3 event forces the output to its inactive state /
bogdanm	82:6473597d706e	1074	#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /!< Master Timer compare 4 event forces the output to its inactive state /
bogdanm	82:6473597d706e	1075	#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
bogdanm	82:6473597d706e	1076	#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
bogdanm	82:6473597d706e	1077	#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
bogdanm	82:6473597d706e	1078	#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
bogdanm	82:6473597d706e	1079	#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
bogdanm	82:6473597d706e	1080	#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
bogdanm	82:6473597d706e	1081	#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
bogdanm	82:6473597d706e	1082	#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
bogdanm	82:6473597d706e	1083	#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
bogdanm	82:6473597d706e	1084	#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /!< External event 1 forces the output to its inactive state /
bogdanm	82:6473597d706e	1085	#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /!< External event 2 forces the output to its inactive state /
bogdanm	82:6473597d706e	1086	#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /!< External event 3 forces the output to its inactive state /
bogdanm	82:6473597d706e	1087	#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /!< External event 4 forces the output to its inactive state /
bogdanm	82:6473597d706e	1088	#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /!< External event 5 forces the output to its inactive state /
bogdanm	82:6473597d706e	1089	#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /!< External event 6 forces the output to its inactive state /
bogdanm	82:6473597d706e	1090	#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /!< External event 7 forces the output to its inactive state /
bogdanm	82:6473597d706e	1091	#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /!< External event 8 forces the output to its inactive state /
bogdanm	82:6473597d706e	1092	#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /!< External event 9 forces the output to its inactive state /
bogdanm	82:6473597d706e	1093	#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /!< External event 10 forces the output to its inactive state /
bogdanm	82:6473597d706e	1094	#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /!< Timer register update event forces the output to its inactive state /
bogdanm	82:6473597d706e	1095
bogdanm	82:6473597d706e	1096	#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
bogdanm	82:6473597d706e	1097	(((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) \|\| \
bogdanm	82:6473597d706e	1098	((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) \|\| \
bogdanm	82:6473597d706e	1099	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) \|\| \
bogdanm	82:6473597d706e	1100	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) \|\| \
bogdanm	82:6473597d706e	1101	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) \|\| \
bogdanm	82:6473597d706e	1102	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) \|\| \
bogdanm	82:6473597d706e	1103	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) \|\| \
bogdanm	82:6473597d706e	1104	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) \|\| \
bogdanm	82:6473597d706e	1105	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) \|\| \
bogdanm	82:6473597d706e	1106	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) \|\| \
bogdanm	82:6473597d706e	1107	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) \|\| \
bogdanm	82:6473597d706e	1108	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) \|\| \
bogdanm	82:6473597d706e	1109	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) \|\| \
bogdanm	82:6473597d706e	1110	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) \|\| \
bogdanm	82:6473597d706e	1111	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) \|\| \
bogdanm	82:6473597d706e	1112	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) \|\| \
bogdanm	82:6473597d706e	1113	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) \|\| \
bogdanm	82:6473597d706e	1114	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) \|\| \
bogdanm	82:6473597d706e	1115	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) \|\| \
bogdanm	82:6473597d706e	1116	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) \|\| \
bogdanm	82:6473597d706e	1117	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) \|\| \
bogdanm	82:6473597d706e	1118	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) \|\| \
bogdanm	82:6473597d706e	1119	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) \|\| \
bogdanm	82:6473597d706e	1120	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) \|\| \
bogdanm	82:6473597d706e	1121	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) \|\| \
bogdanm	82:6473597d706e	1122	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) \|\| \
bogdanm	82:6473597d706e	1123	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) \|\| \
bogdanm	82:6473597d706e	1124	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) \|\| \
bogdanm	82:6473597d706e	1125	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) \|\| \
bogdanm	82:6473597d706e	1126	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) \|\| \
bogdanm	82:6473597d706e	1127	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) \|\| \
bogdanm	82:6473597d706e	1128	((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
bogdanm	82:6473597d706e	1129	/**
bogdanm	82:6473597d706e	1130	* @}
bogdanm	82:6473597d706e	1131	*/
bogdanm	82:6473597d706e	1132
bogdanm	82:6473597d706e	1133	/** @defgroup HRTIM_OutputIdleMode
bogdanm	82:6473597d706e	1134	* @{
bogdanm	82:6473597d706e	1135	* @brief Constants defining whether or not the timer output transition to its
bogdanm	82:6473597d706e	1136	IDLE state when burst mode is entered
bogdanm	82:6473597d706e	1137	*/
bogdanm	82:6473597d706e	1138	#define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /!< The output is not affected by the burst mode operation /
bogdanm	82:6473597d706e	1139	#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /!< The output is in idle state when requested by the burst mode controller /
bogdanm	82:6473597d706e	1140
bogdanm	82:6473597d706e	1141	#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
bogdanm	82:6473597d706e	1142	(((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) \|\| \
bogdanm	82:6473597d706e	1143	((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
bogdanm	82:6473597d706e	1144	/**
bogdanm	82:6473597d706e	1145	* @}
bogdanm	82:6473597d706e	1146	*/
bogdanm	82:6473597d706e	1147
bogdanm	82:6473597d706e	1148	/** @defgroup HRTIM_OutputIDLEState
bogdanm	82:6473597d706e	1149	* @{
bogdanm	82:6473597d706e	1150	* @brief Constants defining the IDLE state of a timer output
bogdanm	82:6473597d706e	1151	*/
bogdanm	82:6473597d706e	1152	#define HRTIM_OUTPUTIDLESTATE_INACTIVE (uint32_t)0x00000000 /!< Output at inactive level when in IDLE state /
bogdanm	82:6473597d706e	1153	#define HRTIM_OUTPUTIDLESTATE_ACTIVE (HRTIM_OUTR_IDLES1) /!< Output at active level when in IDLE state /
bogdanm	82:6473597d706e	1154
bogdanm	82:6473597d706e	1155	#define IS_HRTIM_OUTPUTIDLESTATE(OUTPUTIDLESTATE)\
bogdanm	82:6473597d706e	1156	(((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_INACTIVE) \|\| \
bogdanm	82:6473597d706e	1157	((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_ACTIVE))
bogdanm	82:6473597d706e	1158	/**
bogdanm	82:6473597d706e	1159	* @}
bogdanm	82:6473597d706e	1160	*/
bogdanm	82:6473597d706e	1161
bogdanm	82:6473597d706e	1162	/** @defgroup HRTIM_OutputFAULTState
bogdanm	82:6473597d706e	1163	* @{
bogdanm	82:6473597d706e	1164	* @brief Constants defining the FAULT state of a timer output
bogdanm	82:6473597d706e	1165	*/
bogdanm	82:6473597d706e	1166	#define HRTIM_OUTPUTFAULTSTATE_NONE (uint32_t)0x00000000 /!< The output is not affected by the fault input /
bogdanm	82:6473597d706e	1167	#define HRTIM_OUTPUTFAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /!< Output at active level when in FAULT state /
bogdanm	82:6473597d706e	1168	#define HRTIM_OUTPUTFAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /!< Output at inactive level when in FAULT state /
bogdanm	82:6473597d706e	1169	#define HRTIM_OUTPUTFAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 \| HRTIM_OUTR_FAULT1_0) /!< Output is tri-stated when in FAULT state /
bogdanm	82:6473597d706e	1170
bogdanm	82:6473597d706e	1171	#define IS_HRTIM_OUTPUTFAULTSTATE(OUTPUTFAULTSTATE)\
bogdanm	82:6473597d706e	1172	(((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_NONE) \|\| \
bogdanm	82:6473597d706e	1173	((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_ACTIVE) \|\| \
bogdanm	82:6473597d706e	1174	((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_INACTIVE) \|\| \
bogdanm	82:6473597d706e	1175	((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_HIGHZ))
bogdanm	82:6473597d706e	1176	/**
bogdanm	82:6473597d706e	1177	* @}
bogdanm	82:6473597d706e	1178	*/
bogdanm	82:6473597d706e	1179
bogdanm	82:6473597d706e	1180	/** @defgroup HRTIM_OutputChopperModeEnable
bogdanm	82:6473597d706e	1181	* @{
bogdanm	82:6473597d706e	1182	* @brief Constants defining whether or not chopper mode is enabled for a timer
bogdanm	82:6473597d706e	1183	output
bogdanm	82:6473597d706e	1184	*/
bogdanm	82:6473597d706e	1185	#define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /!< The output is not affected by the fault input /
bogdanm	82:6473597d706e	1186	#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /!< Output at active level when in FAULT state /
bogdanm	82:6473597d706e	1187
bogdanm	82:6473597d706e	1188	#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
bogdanm	82:6473597d706e	1189	(((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) \|\| \
bogdanm	82:6473597d706e	1190	((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
bogdanm	82:6473597d706e	1191	/**
bogdanm	82:6473597d706e	1192	* @}
bogdanm	82:6473597d706e	1193	*/
bogdanm	82:6473597d706e	1194
bogdanm	82:6473597d706e	1195	/** @defgroup HRTIM_OutputBurstModeEntryDelayed
bogdanm	82:6473597d706e	1196	* @{
bogdanm	82:6473597d706e	1197	* @brief Constants defining the idle mode entry is delayed by forcing a
bogdanm	82:6473597d706e	1198	deadtime insertion before switching the outputs to their idle state
bogdanm	82:6473597d706e	1199	*/
bogdanm	82:6473597d706e	1200	#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /!< The programmed Idle state is applied immediately to the Output /
bogdanm	82:6473597d706e	1201	#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /!< Deadtime is inserted on output before entering the idle mode /
bogdanm	82:6473597d706e	1202
bogdanm	82:6473597d706e	1203	#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
bogdanm	82:6473597d706e	1204	(((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) \|\| \
bogdanm	82:6473597d706e	1205	((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
bogdanm	82:6473597d706e	1206	/**
bogdanm	82:6473597d706e	1207	* @}
bogdanm	82:6473597d706e	1208	*/
bogdanm	82:6473597d706e	1209
bogdanm	82:6473597d706e	1210	/** @defgroup HRTIM_CaptureUnitTrigger
bogdanm	82:6473597d706e	1211	* @{
bogdanm	82:6473597d706e	1212	* @brief Constants defining the events that can be selected to trigger the
bogdanm	82:6473597d706e	1213	* capture of the timing unit counter
bogdanm	82:6473597d706e	1214	*/
bogdanm	82:6473597d706e	1215	#define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /!< Capture trigger is disabled /
bogdanm	82:6473597d706e	1216	#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /!< The update event triggers the Capture /
bogdanm	82:6473597d706e	1217	#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /!< The External event 1 triggers the Capture /
bogdanm	82:6473597d706e	1218	#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /!< The External event 2 triggers the Capture /
bogdanm	82:6473597d706e	1219	#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /!< The External event 3 triggers the Capture /
bogdanm	82:6473597d706e	1220	#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /!< The External event 4 triggers the Capture /
bogdanm	82:6473597d706e	1221	#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /!< The External event 5 triggers the Capture /
bogdanm	82:6473597d706e	1222	#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /!< The External event 6 triggers the Capture /
bogdanm	82:6473597d706e	1223	#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /!< The External event 7 triggers the Capture /
bogdanm	82:6473597d706e	1224	#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /!< The External event 8 triggers the Capture /
bogdanm	82:6473597d706e	1225	#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /!< The External event 9 triggers the Capture /
bogdanm	82:6473597d706e	1226	#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /!< The External event 10 triggers the Capture /
bogdanm	82:6473597d706e	1227	#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /!< Capture is triggered by TA1 output inactive to active transition /
bogdanm	82:6473597d706e	1228	#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /!< Capture is triggered by TA1 output active to inactive transition /
bogdanm	82:6473597d706e	1229	#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TA1CMP1) /!< Timer A Compare 1 triggers Capture /
bogdanm	82:6473597d706e	1230	#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TA1CMP2) /!< Timer A Compare 2 triggers Capture /
bogdanm	82:6473597d706e	1231	#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /!< Capture is triggered by TB1 output inactive to active transition /
bogdanm	82:6473597d706e	1232	#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /!< Capture is triggered by TB1 output active to inactive transition /
bogdanm	82:6473597d706e	1233	#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TB1CMP1) /!< Timer B Compare 1 triggers Capture /
bogdanm	82:6473597d706e	1234	#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TB1CMP2) /!< Timer B Compare 2 triggers Capture /
bogdanm	82:6473597d706e	1235	#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /!< Capture is triggered by TC1 output inactive to active transition /
bogdanm	82:6473597d706e	1236	#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /!< Capture is triggered by TC1 output active to inactive transition /
bogdanm	82:6473597d706e	1237	#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TC1CMP1) /!< Timer C Compare 1 triggers Capture /
bogdanm	82:6473597d706e	1238	#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TC1CMP2) /!< Timer C Compare 2 triggers Capture /
bogdanm	82:6473597d706e	1239	#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /!< Capture is triggered by TD1 output inactive to active transition /
bogdanm	82:6473597d706e	1240	#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /!< Capture is triggered by TD1 output active to inactive transition /
bogdanm	82:6473597d706e	1241	#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TD1CMP1) /!< Timer D Compare 1 triggers Capture /
bogdanm	82:6473597d706e	1242	#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TD1CMP2) /!< Timer D Compare 2 triggers Capture /
bogdanm	82:6473597d706e	1243	#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /!< Capture is triggered by TE1 output inactive to active transition /
bogdanm	82:6473597d706e	1244	#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /!< Capture is triggered by TE1 output active to inactive transition /
bogdanm	82:6473597d706e	1245	#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TE1CMP1) /!< Timer E Compare 1 triggers Capture /
bogdanm	82:6473597d706e	1246	#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TE1CMP2) /!< Timer E Compare 2 triggers Capture /
bogdanm	82:6473597d706e	1247
bogdanm	82:6473597d706e	1248	#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
bogdanm	82:6473597d706e	1249	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) \|\| \
bogdanm	82:6473597d706e	1250	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) \|\| \
bogdanm	82:6473597d706e	1251	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) \|\| \
bogdanm	82:6473597d706e	1252	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) \|\| \
bogdanm	82:6473597d706e	1253	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) \|\| \
bogdanm	82:6473597d706e	1254	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) \|\| \
bogdanm	82:6473597d706e	1255	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) \|\| \
bogdanm	82:6473597d706e	1256	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) \|\| \
bogdanm	82:6473597d706e	1257	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) \|\| \
bogdanm	82:6473597d706e	1258	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) \|\| \
bogdanm	82:6473597d706e	1259	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) \|\| \
bogdanm	82:6473597d706e	1260	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
bogdanm	82:6473597d706e	1261	\|\| \
bogdanm	82:6473597d706e	1262	(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
bogdanm	82:6473597d706e	1263	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
bogdanm	82:6473597d706e	1264	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
bogdanm	82:6473597d706e	1265	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
bogdanm	82:6473597d706e	1266	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2))) \
bogdanm	82:6473597d706e	1267	\|\| \
bogdanm	82:6473597d706e	1268	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
bogdanm	82:6473597d706e	1269	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
bogdanm	82:6473597d706e	1270	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
bogdanm	82:6473597d706e	1271	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
bogdanm	82:6473597d706e	1272	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2))) \
bogdanm	82:6473597d706e	1273	\|\| \
bogdanm	82:6473597d706e	1274	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
bogdanm	82:6473597d706e	1275	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
bogdanm	82:6473597d706e	1276	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
bogdanm	82:6473597d706e	1277	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
bogdanm	82:6473597d706e	1278	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2))) \
bogdanm	82:6473597d706e	1279	\|\| \
bogdanm	82:6473597d706e	1280	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
bogdanm	82:6473597d706e	1281	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
bogdanm	82:6473597d706e	1282	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
bogdanm	82:6473597d706e	1283	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
bogdanm	82:6473597d706e	1284	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \
bogdanm	82:6473597d706e	1285	\|\| \
bogdanm	82:6473597d706e	1286	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
bogdanm	82:6473597d706e	1287	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
bogdanm	82:6473597d706e	1288	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
bogdanm	82:6473597d706e	1289	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
bogdanm	82:6473597d706e	1290	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))))
bogdanm	82:6473597d706e	1291	/**
bogdanm	82:6473597d706e	1292	* @}
bogdanm	82:6473597d706e	1293	*/
bogdanm	82:6473597d706e	1294
bogdanm	82:6473597d706e	1295	/** @defgroup HRTIM_TimerExternalEventFilter
bogdanm	82:6473597d706e	1296	* @{
bogdanm	82:6473597d706e	1297	* @brief Constants defining the event filtering applied to external events
bogdanm	82:6473597d706e	1298	* by a timer
bogdanm	82:6473597d706e	1299	*/
bogdanm	82:6473597d706e	1300	#define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
bogdanm	82:6473597d706e	1301	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 1 /
bogdanm	82:6473597d706e	1302	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from counter reset/roll-over to Compare 2 /
bogdanm	82:6473597d706e	1303	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 3 /
bogdanm	82:6473597d706e	1304	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from counter reset/roll-over to Compare 4 /
bogdanm	82:6473597d706e	1305	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR1 source /
bogdanm	82:6473597d706e	1306	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR2 source /
bogdanm	82:6473597d706e	1307	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR3 source /
bogdanm	82:6473597d706e	1308	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /!< Blanking from another timing unit: TIMFLTR4 source /
bogdanm	82:6473597d706e	1309	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR5 source /
bogdanm	82:6473597d706e	1310	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR6 source /
bogdanm	82:6473597d706e	1311	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR7 source /
bogdanm	82:6473597d706e	1312	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from another timing unit: TIMFLTR8 source /
bogdanm	82:6473597d706e	1313	#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from counter reset/roll-over to Compare 2 /
bogdanm	82:6473597d706e	1314	#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Windowing from counter reset/roll-over to Compare 3 /
bogdanm	82:6473597d706e	1315	#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from another timing unit: TIMWIN source /
bogdanm	82:6473597d706e	1316
bogdanm	82:6473597d706e	1317	#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
bogdanm	82:6473597d706e	1318	(((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) \|\| \
bogdanm	82:6473597d706e	1319	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) \|\| \
bogdanm	82:6473597d706e	1320	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) \|\| \
bogdanm	82:6473597d706e	1321	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) \|\| \
bogdanm	82:6473597d706e	1322	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) \|\| \
bogdanm	82:6473597d706e	1323	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) \|\| \
bogdanm	82:6473597d706e	1324	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) \|\| \
bogdanm	82:6473597d706e	1325	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) \|\| \
bogdanm	82:6473597d706e	1326	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) \|\| \
bogdanm	82:6473597d706e	1327	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) \|\| \
bogdanm	82:6473597d706e	1328	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) \|\| \
bogdanm	82:6473597d706e	1329	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) \|\| \
bogdanm	82:6473597d706e	1330	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) \|\| \
bogdanm	82:6473597d706e	1331	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) \|\| \
bogdanm	82:6473597d706e	1332	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) \|\| \
bogdanm	82:6473597d706e	1333	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
bogdanm	82:6473597d706e	1334	/**
bogdanm	82:6473597d706e	1335	* @}
bogdanm	82:6473597d706e	1336	*/
bogdanm	82:6473597d706e	1337
bogdanm	82:6473597d706e	1338	/** @defgroup HRTIM_TimerExternalEventLatch
bogdanm	82:6473597d706e	1339	* @{
bogdanm	82:6473597d706e	1340	* @brief Constants defining whether or not the external event is
bogdanm	82:6473597d706e	1341	* memorized (latched) and generated as soon as the blanking period
bogdanm	82:6473597d706e	1342	* is completed or the window ends
bogdanm	82:6473597d706e	1343	*/
bogdanm	82:6473597d706e	1344	#define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /!< Event is ignored if it happens during a blank, or passed through during a window /
bogdanm	82:6473597d706e	1345	#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /!< Event 1 is latched and delayed till the end of the blanking or windowing period / /!< Blanking from counter reset/roll-over to Compare 1 /
bogdanm	82:6473597d706e	1346
bogdanm	82:6473597d706e	1347	#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
bogdanm	82:6473597d706e	1348	(((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) \|\| \
bogdanm	82:6473597d706e	1349	((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
bogdanm	82:6473597d706e	1350	/**
bogdanm	82:6473597d706e	1351	* @}
bogdanm	82:6473597d706e	1352	*/
bogdanm	82:6473597d706e	1353
bogdanm	82:6473597d706e	1354	/** @defgroup HRTIM_DeadtimeRisingSign
bogdanm	82:6473597d706e	1355	* @{
bogdanm	82:6473597d706e	1356	* @brief Constants defining whether the deadtime is positive or negative
bogdanm	82:6473597d706e	1357	* (overlapping signal) on rising edge
bogdanm	82:6473597d706e	1358	*/
bogdanm	82:6473597d706e	1359	#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /!< Positive deadtime on rising edge /
bogdanm	82:6473597d706e	1360	#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /!< Negative deadtime on rising edge /
bogdanm	82:6473597d706e	1361
bogdanm	82:6473597d706e	1362	#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
bogdanm	82:6473597d706e	1363	(((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) \|\| \
bogdanm	82:6473597d706e	1364	((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
bogdanm	82:6473597d706e	1365	/**
bogdanm	82:6473597d706e	1366	* @}
bogdanm	82:6473597d706e	1367	*/
bogdanm	82:6473597d706e	1368
bogdanm	82:6473597d706e	1369	/** @defgroup HRTIM_DeadtimeRisingLock
bogdanm	82:6473597d706e	1370	* @{
bogdanm	82:6473597d706e	1371	* @brief Constants defining whether or not the deadtime (rising sign and
bogdanm	82:6473597d706e	1372	* value) is write protected
bogdanm	82:6473597d706e	1373	*/
bogdanm	82:6473597d706e	1374	#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime rising value and sign is writable /
bogdanm	82:6473597d706e	1375	#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /!< Deadtime rising value and sign is read-only /
bogdanm	82:6473597d706e	1376
bogdanm	82:6473597d706e	1377	#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
bogdanm	82:6473597d706e	1378	(((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) \|\| \
bogdanm	82:6473597d706e	1379	((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
bogdanm	82:6473597d706e	1380	/**
bogdanm	82:6473597d706e	1381	* @}
bogdanm	82:6473597d706e	1382	*/
bogdanm	82:6473597d706e	1383
bogdanm	82:6473597d706e	1384	/** @defgroup HRTIM_DeadtimeRisingSignLock
bogdanm	82:6473597d706e	1385	* @{
bogdanm	82:6473597d706e	1386	* @brief Constants defining whether or not the deadtime rising sign is write
bogdanm	82:6473597d706e	1387	* protected
bogdanm	82:6473597d706e	1388	*/
bogdanm	82:6473597d706e	1389	#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime rising sign is writable /
bogdanm	82:6473597d706e	1390	#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /!< Deadtime rising sign is read-only /
bogdanm	82:6473597d706e	1391
bogdanm	82:6473597d706e	1392	#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
bogdanm	82:6473597d706e	1393	(((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) \|\| \
bogdanm	82:6473597d706e	1394	((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
bogdanm	82:6473597d706e	1395	/**
bogdanm	82:6473597d706e	1396	* @}
bogdanm	82:6473597d706e	1397	*/
bogdanm	82:6473597d706e	1398
bogdanm	82:6473597d706e	1399	/** @defgroup HRTIM_DeadtimeFallingSign
bogdanm	82:6473597d706e	1400	* @{
bogdanm	82:6473597d706e	1401	* @brief Constants defining whether the deadtime is positive or negative
bogdanm	82:6473597d706e	1402	* (overlapping signal) on falling edge
bogdanm	82:6473597d706e	1403	*/
bogdanm	82:6473597d706e	1404	#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /!< Positive deadtime on falling edge /
bogdanm	82:6473597d706e	1405	#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /!< Negative deadtime on falling edge /
bogdanm	82:6473597d706e	1406
bogdanm	82:6473597d706e	1407	#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
bogdanm	82:6473597d706e	1408	(((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) \|\| \
bogdanm	82:6473597d706e	1409	((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
bogdanm	82:6473597d706e	1410	/**
bogdanm	82:6473597d706e	1411	* @}
bogdanm	82:6473597d706e	1412	*/
bogdanm	82:6473597d706e	1413
bogdanm	82:6473597d706e	1414	/** @defgroup HRTIM_DeadtimeFallingLock
bogdanm	82:6473597d706e	1415	* @{
bogdanm	82:6473597d706e	1416	* @brief Constants defining whether or not the deadtime (falling sign and
bogdanm	82:6473597d706e	1417	* value) is write protected
bogdanm	82:6473597d706e	1418	*/
bogdanm	82:6473597d706e	1419	#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime falling value and sign is writable /
bogdanm	82:6473597d706e	1420	#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /!< Deadtime falling value and sign is read-only /
bogdanm	82:6473597d706e	1421
bogdanm	82:6473597d706e	1422	#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
bogdanm	82:6473597d706e	1423	(((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) \|\| \
bogdanm	82:6473597d706e	1424	((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
bogdanm	82:6473597d706e	1425	/**
bogdanm	82:6473597d706e	1426	* @}
bogdanm	82:6473597d706e	1427	*/
bogdanm	82:6473597d706e	1428
bogdanm	82:6473597d706e	1429	/** @defgroup HRTIM_DeadtimeFallingSignLock
bogdanm	82:6473597d706e	1430	* @{
bogdanm	82:6473597d706e	1431	* @brief Constants defining whether or not the deadtime falling sign is write
bogdanm	82:6473597d706e	1432	* protected
bogdanm	82:6473597d706e	1433	*/
bogdanm	82:6473597d706e	1434	#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime falling sign is writable /
bogdanm	82:6473597d706e	1435	#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /!< Deadtime falling sign is read-only /
bogdanm	82:6473597d706e	1436
bogdanm	82:6473597d706e	1437	#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
bogdanm	82:6473597d706e	1438	(((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) \|\| \
bogdanm	82:6473597d706e	1439	((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
bogdanm	82:6473597d706e	1440	/**
bogdanm	82:6473597d706e	1441	* @}
bogdanm	82:6473597d706e	1442	*/
bogdanm	82:6473597d706e	1443
bogdanm	82:6473597d706e	1444	/** @defgroup HRTIM_SynchronizationInputSource
bogdanm	82:6473597d706e	1445	* @{
bogdanm	82:6473597d706e	1446	* @brief Constants defining defining the synchronization input source
bogdanm	82:6473597d706e	1447	*/
bogdanm	82:6473597d706e	1448	#define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /!< disabled. HRTIM is not synchronized and runs in standalone mode /
bogdanm	82:6473597d706e	1449	#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /!< The HRTIM is synchronized with the on-chip timer /
bogdanm	82:6473597d706e	1450	#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 \| HRTIM_MCR_SYNC_IN_0) /!< A positive pulse on SYNCIN input triggers the HRTIM /
bogdanm	82:6473597d706e	1451
bogdanm	82:6473597d706e	1452	#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
bogdanm	82:6473597d706e	1453	(((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) \|\| \
bogdanm	82:6473597d706e	1454	((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) \|\| \
bogdanm	82:6473597d706e	1455	((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
bogdanm	82:6473597d706e	1456	/**
bogdanm	82:6473597d706e	1457	* @}
bogdanm	82:6473597d706e	1458	*/
bogdanm	82:6473597d706e	1459
bogdanm	82:6473597d706e	1460	/** @defgroup HRTIM_SynchronizationOutputSource
bogdanm	82:6473597d706e	1461	* @{
bogdanm	82:6473597d706e	1462	* @brief Constants defining the source and event to be sent on the
bogdanm	82:6473597d706e	1463	* synchronization outputs
bogdanm	82:6473597d706e	1464	*/
bogdanm	82:6473597d706e	1465	#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer start event /
bogdanm	82:6473597d706e	1466	#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer compare 1 event/
bogdanm	82:6473597d706e	1467	#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A start or reset events /
bogdanm	82:6473597d706e	1468	#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 \| HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A compare 1 event /
bogdanm	82:6473597d706e	1469
bogdanm	82:6473597d706e	1470	#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
bogdanm	82:6473597d706e	1471	(((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) \|\| \
bogdanm	82:6473597d706e	1472	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) \|\| \
bogdanm	82:6473597d706e	1473	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) \|\| \
bogdanm	82:6473597d706e	1474	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
bogdanm	82:6473597d706e	1475	/**
bogdanm	82:6473597d706e	1476	* @}
bogdanm	82:6473597d706e	1477	*/
bogdanm	82:6473597d706e	1478
bogdanm	82:6473597d706e	1479	/** @defgroup HRTIM_SynchronizationOutputPolarity
bogdanm	82:6473597d706e	1480	* @{
bogdanm	82:6473597d706e	1481	* @brief Constants defining the routing and conditioning of the synchronization output event
bogdanm	82:6473597d706e	1482	*/
bogdanm	82:6473597d706e	1483	#define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /!< Synchronization output event is disabled /
bogdanm	82:6473597d706e	1484	#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_0) /!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) /
bogdanm	82:6473597d706e	1485	#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 \| HRTIM_MCR_SYNC_OUT_0) /!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) /
bogdanm	82:6473597d706e	1486
bogdanm	82:6473597d706e	1487	#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
bogdanm	82:6473597d706e	1488	(((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) \|\| \
bogdanm	82:6473597d706e	1489	((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) \|\| \
bogdanm	82:6473597d706e	1490	((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
bogdanm	82:6473597d706e	1491	/**
bogdanm	82:6473597d706e	1492	* @}
bogdanm	82:6473597d706e	1493	*/
bogdanm	82:6473597d706e	1494
bogdanm	82:6473597d706e	1495	/** @defgroup HRTIM_ExternalEventSources
bogdanm	82:6473597d706e	1496	* @{
bogdanm	82:6473597d706e	1497	* @brief Constants defining available sources associated to external events
bogdanm	82:6473597d706e	1498	*/
bogdanm	82:6473597d706e	1499	#define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /!< External event source 1 /
bogdanm	82:6473597d706e	1500	#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /!< External event source 2 /
bogdanm	82:6473597d706e	1501	#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /!< External event source 3 /
bogdanm	82:6473597d706e	1502	#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 \| HRTIM_EECR1_EE1SRC_0) /!< External event source 4 /
bogdanm	82:6473597d706e	1503
bogdanm	82:6473597d706e	1504	#define IS_HRTIM_EVENTSRC(EVENTSRC)\
bogdanm	82:6473597d706e	1505	(((EVENTSRC) == HRTIM_EVENTSRC_1) \|\| \
bogdanm	82:6473597d706e	1506	((EVENTSRC) == HRTIM_EVENTSRC_2) \|\| \
bogdanm	82:6473597d706e	1507	((EVENTSRC) == HRTIM_EVENTSRC_3) \|\| \
bogdanm	82:6473597d706e	1508	((EVENTSRC) == HRTIM_EVENTSRC_4))
bogdanm	82:6473597d706e	1509	/**
bogdanm	82:6473597d706e	1510	* @}
bogdanm	82:6473597d706e	1511	*/
bogdanm	82:6473597d706e	1512
bogdanm	82:6473597d706e	1513	/** @defgroup HRTIM_ExternalEventPolarity
bogdanm	82:6473597d706e	1514	* @{
bogdanm	82:6473597d706e	1515	* @brief Constants defining the polarity of an external event
bogdanm	82:6473597d706e	1516	*/
bogdanm	82:6473597d706e	1517	#define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /!< External event is active high /
bogdanm	82:6473597d706e	1518	#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /!< External event is active low /
bogdanm	82:6473597d706e	1519
bogdanm	82:6473597d706e	1520	#define IS_HRTIM_EVENTPOLARITY(EVENTPOLARITY)\
bogdanm	82:6473597d706e	1521	(((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) \|\| \
bogdanm	82:6473597d706e	1522	((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))
bogdanm	82:6473597d706e	1523	/**
bogdanm	82:6473597d706e	1524	* @}
bogdanm	82:6473597d706e	1525	*/
bogdanm	82:6473597d706e	1526
bogdanm	82:6473597d706e	1527	/** @defgroup HRTIM_ExternalEventSensitivity
bogdanm	82:6473597d706e	1528	* @{
bogdanm	82:6473597d706e	1529	* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
bogdanm	82:6473597d706e	1530	* of an external event
bogdanm	82:6473597d706e	1531	*/
bogdanm	82:6473597d706e	1532	#define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /!< External event is active on level /
bogdanm	82:6473597d706e	1533	#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising edge /
bogdanm	82:6473597d706e	1534	#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /!< External event is active on Falling edge /
bogdanm	82:6473597d706e	1535	#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 \| HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising and Falling edges /
bogdanm	82:6473597d706e	1536
bogdanm	82:6473597d706e	1537	#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
bogdanm	82:6473597d706e	1538	(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) \|\| \
bogdanm	82:6473597d706e	1539	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) \|\| \
bogdanm	82:6473597d706e	1540	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) \|\| \
bogdanm	82:6473597d706e	1541	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
bogdanm	82:6473597d706e	1542	/**
bogdanm	82:6473597d706e	1543	* @}
bogdanm	82:6473597d706e	1544	*/
bogdanm	82:6473597d706e	1545
bogdanm	82:6473597d706e	1546	/** @defgroup HRTIM_ExternalEventFastMode
bogdanm	82:6473597d706e	1547	* @{
bogdanm	82:6473597d706e	1548	* @brief Constants defining whether or not an external event is programmed in
bogdanm	82:6473597d706e	1549	fast mode
bogdanm	82:6473597d706e	1550	*/
bogdanm	82:6473597d706e	1551	#define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /!< External Event is acting asynchronously on outputs (low latency mode) /
bogdanm	82:6473597d706e	1552	#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /!< External Event is re-synchronized by the HRTIM logic before acting on outputs /
bogdanm	82:6473597d706e	1553
bogdanm	82:6473597d706e	1554	#define IS_HRTIM_EVENTFASTMODE(EVENTFASTMODE)\
bogdanm	82:6473597d706e	1555	(((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) \|\| \
bogdanm	82:6473597d706e	1556	((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))
bogdanm	82:6473597d706e	1557
bogdanm	82:6473597d706e	1558	#define IS_HRTIM_FASTMODE_AVAILABLE(EVENT)\
bogdanm	82:6473597d706e	1559	(((EVENT) == HRTIM_EVENT_1) \|\| \
bogdanm	82:6473597d706e	1560	((EVENT) == HRTIM_EVENT_2) \|\| \
bogdanm	82:6473597d706e	1561	((EVENT) == HRTIM_EVENT_3) \|\| \
bogdanm	82:6473597d706e	1562	((EVENT) == HRTIM_EVENT_4) \|\| \
bogdanm	82:6473597d706e	1563	((EVENT) == HRTIM_EVENT_5))
bogdanm	82:6473597d706e	1564	/**
bogdanm	82:6473597d706e	1565	* @}
bogdanm	82:6473597d706e	1566	*/
bogdanm	82:6473597d706e	1567
bogdanm	82:6473597d706e	1568	/** @defgroup HRTIM_ExternalEventFilter
bogdanm	82:6473597d706e	1569	* @{
bogdanm	82:6473597d706e	1570	* @brief Constants defining the frequency used to sample an external event 6
bogdanm	82:6473597d706e	1571	* input and the length (N) of the digital filter applied
bogdanm	82:6473597d706e	1572	*/
bogdanm	82:6473597d706e	1573	#define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /!< Filter disabled /
bogdanm	82:6473597d706e	1574	#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fHRTIM, N=2 /
bogdanm	82:6473597d706e	1575	#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fHRTIM, N=4 /
bogdanm	82:6473597d706e	1576	#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fHRTIM, N=8 /
bogdanm	82:6473597d706e	1577	#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /!< fSAMPLING= fEEVS/2, N=6 /
bogdanm	82:6473597d706e	1578	#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/2, N=8 /
bogdanm	82:6473597d706e	1579	#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/4, N=6 /
bogdanm	82:6473597d706e	1580	#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/4, N=8 /
bogdanm	82:6473597d706e	1581	#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /!< fSAMPLING= fEEVS/8, N=6 /
bogdanm	82:6473597d706e	1582	#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/8, N=8 /
bogdanm	82:6473597d706e	1583	#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/16, N=5 /
bogdanm	82:6473597d706e	1584	#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/16, N=6 /
bogdanm	82:6473597d706e	1585	#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2) /!< fSAMPLING= fEEVS/16, N=8 /
bogdanm	82:6473597d706e	1586	#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/32, N=5 /
bogdanm	82:6473597d706e	1587	#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/32, N=6 /
bogdanm	82:6473597d706e	1588	#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/32, N=8 /
bogdanm	82:6473597d706e	1589
bogdanm	82:6473597d706e	1590	#define IS_HRTIM_EVENTFILTER(EVENTFILTER)\
bogdanm	82:6473597d706e	1591	(((EVENTFILTER) == HRTIM_EVENTFILTER_NONE) \|\| \
bogdanm	82:6473597d706e	1592	((EVENTFILTER) == HRTIM_EVENTFILTER_1) \|\| \
bogdanm	82:6473597d706e	1593	((EVENTFILTER) == HRTIM_EVENTFILTER_2) \|\| \
bogdanm	82:6473597d706e	1594	((EVENTFILTER) == HRTIM_EVENTFILTER_3) \|\| \
bogdanm	82:6473597d706e	1595	((EVENTFILTER) == HRTIM_EVENTFILTER_4) \|\| \
bogdanm	82:6473597d706e	1596	((EVENTFILTER) == HRTIM_EVENTFILTER_5) \|\| \
bogdanm	82:6473597d706e	1597	((EVENTFILTER) == HRTIM_EVENTFILTER_6) \|\| \
bogdanm	82:6473597d706e	1598	((EVENTFILTER) == HRTIM_EVENTFILTER_7) \|\| \
bogdanm	82:6473597d706e	1599	((EVENTFILTER) == HRTIM_EVENTFILTER_8) \|\| \
bogdanm	82:6473597d706e	1600	((EVENTFILTER) == HRTIM_EVENTFILTER_9) \|\| \
bogdanm	82:6473597d706e	1601	((EVENTFILTER) == HRTIM_EVENTFILTER_10) \|\| \
bogdanm	82:6473597d706e	1602	((EVENTFILTER) == HRTIM_EVENTFILTER_11) \|\| \
bogdanm	82:6473597d706e	1603	((EVENTFILTER) == HRTIM_EVENTFILTER_12) \|\| \
bogdanm	82:6473597d706e	1604	((EVENTFILTER) == HRTIM_EVENTFILTER_13) \|\| \
bogdanm	82:6473597d706e	1605	((EVENTFILTER) == HRTIM_EVENTFILTER_14) \|\| \
bogdanm	82:6473597d706e	1606	((EVENTFILTER) == HRTIM_EVENTFILTER_15))
bogdanm	82:6473597d706e	1607	/**
bogdanm	82:6473597d706e	1608	* @}
bogdanm	82:6473597d706e	1609	*/
bogdanm	82:6473597d706e	1610
bogdanm	82:6473597d706e	1611	/** @defgroup HRTIM_ ExternalEventPrescaler
bogdanm	82:6473597d706e	1612	* @{
bogdanm	82:6473597d706e	1613	* @brief Constants defining division ratio between the timer clock frequency
bogdanm	82:6473597d706e	1614	* fHRTIM) and the external event signal sampling clock (fEEVS)
bogdanm	82:6473597d706e	1615	* used by the digital filters
bogdanm	82:6473597d706e	1616	*/
bogdanm	82:6473597d706e	1617	#define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fEEVS=fHRTIM /
bogdanm	82:6473597d706e	1618	#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /!< fEEVS=fHRTIM / 2 /
bogdanm	82:6473597d706e	1619	#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /!< fEEVS=fHRTIM / 4 /
bogdanm	82:6473597d706e	1620	#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 \| HRTIM_EECR3_EEVSD_0) /!< fEEVS=fHRTIM / 8 /
bogdanm	82:6473597d706e	1621
bogdanm	82:6473597d706e	1622	#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
bogdanm	82:6473597d706e	1623	(((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) \|\| \
bogdanm	82:6473597d706e	1624	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) \|\| \
bogdanm	82:6473597d706e	1625	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) \|\| \
bogdanm	82:6473597d706e	1626	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
bogdanm	82:6473597d706e	1627	/**
bogdanm	82:6473597d706e	1628	* @}
bogdanm	82:6473597d706e	1629	*/
bogdanm	82:6473597d706e	1630
bogdanm	82:6473597d706e	1631	/** @defgroup HRTIM_FaultSources
bogdanm	82:6473597d706e	1632	* @{
bogdanm	82:6473597d706e	1633	* @brief Constants defining whether a faults is be triggered by any external
bogdanm	82:6473597d706e	1634	* or internal fault source
bogdanm	82:6473597d706e	1635	*/
bogdanm	82:6473597d706e	1636	#define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /!< Fault input is FLT input pin /
bogdanm	82:6473597d706e	1637	#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /!< Fault input is FLT_Int signal (e.g. internal comparator) /
bogdanm	82:6473597d706e	1638
bogdanm	82:6473597d706e	1639
bogdanm	82:6473597d706e	1640	#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
bogdanm	82:6473597d706e	1641	(((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) \|\| \
bogdanm	82:6473597d706e	1642	((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
bogdanm	82:6473597d706e	1643	/**
bogdanm	82:6473597d706e	1644	* @}
bogdanm	82:6473597d706e	1645	*/
bogdanm	82:6473597d706e	1646
bogdanm	82:6473597d706e	1647	/** @defgroup HRTIM_FaultPolarity
bogdanm	82:6473597d706e	1648	* @{
bogdanm	82:6473597d706e	1649	* @brief Constants defining the polarity of a fault event
bogdanm	82:6473597d706e	1650	*/
bogdanm	82:6473597d706e	1651	#define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /!< Fault input is active low /
bogdanm	82:6473597d706e	1652	#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /!< Fault input is active high /
bogdanm	82:6473597d706e	1653
bogdanm	82:6473597d706e	1654	#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
bogdanm	82:6473597d706e	1655	(((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) \|\| \
bogdanm	82:6473597d706e	1656	((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
bogdanm	82:6473597d706e	1657	/**
bogdanm	82:6473597d706e	1658	* @}
bogdanm	82:6473597d706e	1659	*/
bogdanm	82:6473597d706e	1660
bogdanm	82:6473597d706e	1661	/** @defgroup HRTIM_FaultFilter
bogdanm	82:6473597d706e	1662	* @{
bogdanm	82:6473597d706e	1663	* @ brief Constants defining the frequency used to sample the fault input and
bogdanm	82:6473597d706e	1664	* the length (N) of the digital filter applied
bogdanm	82:6473597d706e	1665	*/
bogdanm	82:6473597d706e	1666	#define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /!< Filter disabled /
bogdanm	82:6473597d706e	1667	#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=2 /
bogdanm	82:6473597d706e	1668	#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fHRTIM, N=4 /
bogdanm	82:6473597d706e	1669	#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=8 /
bogdanm	82:6473597d706e	1670	#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/2, N=6 /
bogdanm	82:6473597d706e	1671	#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/2, N=8 /
bogdanm	82:6473597d706e	1672	#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/4, N=6 /
bogdanm	82:6473597d706e	1673	#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/4, N=8 /
bogdanm	82:6473597d706e	1674	#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /!< fSAMPLING= fFLTS/8, N=6 /
bogdanm	82:6473597d706e	1675	#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/8, N=8 /
bogdanm	82:6473597d706e	1676	#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/16, N=5 /
bogdanm	82:6473597d706e	1677	#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/16, N=6 /
bogdanm	82:6473597d706e	1678	#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/16, N=8 /
bogdanm	82:6473597d706e	1679	#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32, N=5 /
bogdanm	82:6473597d706e	1680	#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/32, N=6 /
bogdanm	82:6473597d706e	1681	#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32, N=8 /
bogdanm	82:6473597d706e	1682
bogdanm	82:6473597d706e	1683	#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
bogdanm	82:6473597d706e	1684	(((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) \|\| \
bogdanm	82:6473597d706e	1685	((FAULTFILTER) == HRTIM_FAULTFILTER_1) \|\| \
bogdanm	82:6473597d706e	1686	((FAULTFILTER) == HRTIM_FAULTFILTER_2) \|\| \
bogdanm	82:6473597d706e	1687	((FAULTFILTER) == HRTIM_FAULTFILTER_3) \|\| \
bogdanm	82:6473597d706e	1688	((FAULTFILTER) == HRTIM_FAULTFILTER_4) \|\| \
bogdanm	82:6473597d706e	1689	((FAULTFILTER) == HRTIM_FAULTFILTER_5) \|\| \
bogdanm	82:6473597d706e	1690	((FAULTFILTER) == HRTIM_FAULTFILTER_6) \|\| \
bogdanm	82:6473597d706e	1691	((FAULTFILTER) == HRTIM_FAULTFILTER_7) \|\| \
bogdanm	82:6473597d706e	1692	((FAULTFILTER) == HRTIM_FAULTFILTER_8) \|\| \
bogdanm	82:6473597d706e	1693	((FAULTFILTER) == HRTIM_FAULTFILTER_9) \|\| \
bogdanm	82:6473597d706e	1694	((FAULTFILTER) == HRTIM_FAULTFILTER_10) \|\| \
bogdanm	82:6473597d706e	1695	((FAULTFILTER) == HRTIM_FAULTFILTER_11) \|\| \
bogdanm	82:6473597d706e	1696	((FAULTFILTER) == HRTIM_FAULTFILTER_12) \|\| \
bogdanm	82:6473597d706e	1697	((FAULTFILTER) == HRTIM_FAULTFILTER_13) \|\| \
bogdanm	82:6473597d706e	1698	((FAULTFILTER) == HRTIM_FAULTFILTER_14) \|\| \
bogdanm	82:6473597d706e	1699	((FAULTFILTER) == HRTIM_FAULTFILTER_15))
bogdanm	82:6473597d706e	1700	/**
bogdanm	82:6473597d706e	1701	* @}
bogdanm	82:6473597d706e	1702	*/
bogdanm	82:6473597d706e	1703
bogdanm	82:6473597d706e	1704	/** @defgroup HRTIM_FaultLock
bogdanm	82:6473597d706e	1705	* @{
bogdanm	82:6473597d706e	1706	* @brief Constants defining whether or not the fault programming bits are
bogdanm	82:6473597d706e	1707	write protected
bogdanm	82:6473597d706e	1708	*/
bogdanm	82:6473597d706e	1709	#define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /!< Fault settings bits are read/write /
bogdanm	82:6473597d706e	1710	#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /!< Fault settings bits are read only /
bogdanm	82:6473597d706e	1711
bogdanm	82:6473597d706e	1712	#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
bogdanm	82:6473597d706e	1713	(((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) \|\| \
bogdanm	82:6473597d706e	1714	((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
bogdanm	82:6473597d706e	1715	/**
bogdanm	82:6473597d706e	1716	* @}
bogdanm	82:6473597d706e	1717	*/
bogdanm	82:6473597d706e	1718
bogdanm	82:6473597d706e	1719	/** @defgroup HRTIM_ExternalFaultPrescaler
bogdanm	82:6473597d706e	1720	* @{
bogdanm	82:6473597d706e	1721	* @brief Constants defining the division ratio between the timer clock
bogdanm	82:6473597d706e	1722	* frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
bogdanm	82:6473597d706e	1723	* by the digital filters.
bogdanm	82:6473597d706e	1724	*/
bogdanm	82:6473597d706e	1725	#define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fFLTS=fHRTIM /
bogdanm	82:6473597d706e	1726	#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /!< fFLTS=fHRTIM / 2 /
bogdanm	82:6473597d706e	1727	#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /!< fFLTS=fHRTIM / 4 /
bogdanm	82:6473597d706e	1728	#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 \| HRTIM_FLTINR2_FLTSD_0) /!< fFLTS=fHRTIM / 8 /
bogdanm	82:6473597d706e	1729
bogdanm	82:6473597d706e	1730	#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
bogdanm	82:6473597d706e	1731	(((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) \|\| \
bogdanm	82:6473597d706e	1732	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) \|\| \
bogdanm	82:6473597d706e	1733	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) \|\| \
bogdanm	82:6473597d706e	1734	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
bogdanm	82:6473597d706e	1735	/**
bogdanm	82:6473597d706e	1736	* @}
bogdanm	82:6473597d706e	1737	*/
bogdanm	82:6473597d706e	1738
bogdanm	82:6473597d706e	1739	/** @defgroup HRTIM_BurstModeOperatingmode
bogdanm	82:6473597d706e	1740	* @{
bogdanm	82:6473597d706e	1741	* @brief Constants defining if the burst mode is entered once or if it is
bogdanm	82:6473597d706e	1742	* continuously operating
bogdanm	82:6473597d706e	1743	*/
bogdanm	82:6473597d706e	1744	#define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /!< Burst mode operates in single shot mode /
bogdanm	82:6473597d706e	1745	#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /!< Burst mode operates in continuous mode /
bogdanm	82:6473597d706e	1746
bogdanm	82:6473597d706e	1747	#define IS_HRTIM_BURSTMODE(BURSTMODE)\
bogdanm	82:6473597d706e	1748	(((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) \|\| \
bogdanm	82:6473597d706e	1749	((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
bogdanm	82:6473597d706e	1750	/**
bogdanm	82:6473597d706e	1751	* @}
bogdanm	82:6473597d706e	1752	*/
bogdanm	82:6473597d706e	1753
bogdanm	82:6473597d706e	1754	/** @defgroup HRTIM_BurstModeClockSource
bogdanm	82:6473597d706e	1755	* @{
bogdanm	82:6473597d706e	1756	* @brief Constants defining the clock source for the burst mode counter
bogdanm	82:6473597d706e	1757	*/
bogdanm	82:6473597d706e	1758	#define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /!< Master timer counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	82:6473597d706e	1759	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /!< Timer A counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	82:6473597d706e	1760	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /!< Timer B counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	82:6473597d706e	1761	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< Timer C counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	82:6473597d706e	1762	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /!< Timer D counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	82:6473597d706e	1763	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_0) /!< Timer E counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	82:6473597d706e	1764	#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1 (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1) /!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock /
bogdanm	82:6473597d706e	1765	#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2 (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock /
bogdanm	82:6473597d706e	1766	#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3 (HRTIM_BMCR_BMCLK_3) /!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock /
bogdanm	82:6473597d706e	1767	#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4 (HRTIM_BMCR_BMCLK_3 \| HRTIM_BMCR_BMCLK_0) /!< On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock /
bogdanm	82:6473597d706e	1768	#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 \| HRTIM_BMCR_BMCLK_1) /!< Prescaled fHRTIM clock is used as clock source for the burst mode counter /
bogdanm	82:6473597d706e	1769
bogdanm	82:6473597d706e	1770	#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
bogdanm	82:6473597d706e	1771	(((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) \|\| \
bogdanm	82:6473597d706e	1772	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) \|\| \
bogdanm	82:6473597d706e	1773	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) \|\| \
bogdanm	82:6473597d706e	1774	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) \|\| \
bogdanm	82:6473597d706e	1775	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) \|\| \
bogdanm	82:6473597d706e	1776	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) \|\| \
bogdanm	82:6473597d706e	1777	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1) \|\| \
bogdanm	82:6473597d706e	1778	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2) \|\| \
bogdanm	82:6473597d706e	1779	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3) \|\| \
bogdanm	82:6473597d706e	1780	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4) \|\| \
bogdanm	82:6473597d706e	1781	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
bogdanm	82:6473597d706e	1782	/**
bogdanm	82:6473597d706e	1783	* @}
bogdanm	82:6473597d706e	1784	*/
bogdanm	82:6473597d706e	1785
bogdanm	82:6473597d706e	1786	/** @defgroup HRTIM_BurstModePrescaler
bogdanm	82:6473597d706e	1787	* @{
bogdanm	82:6473597d706e	1788	* @brief Constants defining the prescaling ratio of the fHRTIM clock
bogdanm	82:6473597d706e	1789	* for the burst mode controller
bogdanm	82:6473597d706e	1790	*/
bogdanm	82:6473597d706e	1791	#define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fBRST = fHRTIM /
bogdanm	82:6473597d706e	1792	#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPSC_0) /!< fBRST = fHRTIM/2 /
bogdanm	82:6473597d706e	1793	#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPSC_1) /!< fBRST = fHRTIM/4 /
bogdanm	82:6473597d706e	1794	#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPSC_1 \| HRTIM_BMCR_BMPSC_0) /!< fBRST = fHRTIM/8 /
bogdanm	82:6473597d706e	1795	#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPSC_2) /!< fBRST = fHRTIM/16 /
bogdanm	82:6473597d706e	1796	#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPSC_2 \| HRTIM_BMCR_BMPSC_0) /!< fBRST = fHRTIM/32 /
bogdanm	82:6473597d706e	1797	#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPSC_2 \| HRTIM_BMCR_BMPSC_1) /!< fBRST = fHRTIM/64 /
bogdanm	82:6473597d706e	1798	#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPSC_2 \| HRTIM_BMCR_BMPSC_1 \| HRTIM_BMCR_BMPSC_0) /!< fBRST = fHRTIM/128 /
bogdanm	82:6473597d706e	1799	#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPSC_3) /!< fBRST = fHRTIM/256 /
bogdanm	82:6473597d706e	1800	#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPSC_3 \| HRTIM_BMCR_BMPSC_0) /!< fBRST = fHRTIM/512 /
bogdanm	82:6473597d706e	1801	#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPSC_3 \| HRTIM_BMCR_BMPSC_1) /!< fBRST = fHRTIM/1024 /
bogdanm	82:6473597d706e	1802	#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPSC_3 \| HRTIM_BMCR_BMPSC_1 \| HRTIM_BMCR_BMPSC_0) /!< fBRST = fHRTIM/2048/
bogdanm	82:6473597d706e	1803	#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPSC_3 \| HRTIM_BMCR_BMPSC_2) /!< fBRST = fHRTIM/4096 /
bogdanm	82:6473597d706e	1804	#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPSC_3 \| HRTIM_BMCR_BMPSC_2 \| HRTIM_BMCR_BMPSC_0) /!< fBRST = fHRTIM/8192 /
bogdanm	82:6473597d706e	1805	#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPSC_3 \| HRTIM_BMCR_BMPSC_2 \| HRTIM_BMCR_BMPSC_1) /!< fBRST = fHRTIM/16384 /
bogdanm	82:6473597d706e	1806	#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPSC_3 \| HRTIM_BMCR_BMPSC_2 \| HRTIM_BMCR_BMPSC_1 \| HRTIM_BMCR_BMPSC_0) /!< fBRST = fHRTIM/32768 /
bogdanm	82:6473597d706e	1807
bogdanm	82:6473597d706e	1808	#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
bogdanm	82:6473597d706e	1809	(((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) \|\| \
bogdanm	82:6473597d706e	1810	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) \|\| \
bogdanm	82:6473597d706e	1811	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) \|\| \
bogdanm	82:6473597d706e	1812	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) \|\| \
bogdanm	82:6473597d706e	1813	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) \|\| \
bogdanm	82:6473597d706e	1814	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) \|\| \
bogdanm	82:6473597d706e	1815	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) \|\| \
bogdanm	82:6473597d706e	1816	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) \|\| \
bogdanm	82:6473597d706e	1817	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) \|\| \
bogdanm	82:6473597d706e	1818	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) \|\| \
bogdanm	82:6473597d706e	1819	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) \|\| \
bogdanm	82:6473597d706e	1820	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) \|\| \
bogdanm	82:6473597d706e	1821	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) \|\| \
bogdanm	82:6473597d706e	1822	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) \|\| \
bogdanm	82:6473597d706e	1823	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) \|\| \
bogdanm	82:6473597d706e	1824	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
bogdanm	82:6473597d706e	1825	/**
bogdanm	82:6473597d706e	1826	* @}
bogdanm	82:6473597d706e	1827	*/
bogdanm	82:6473597d706e	1828
bogdanm	82:6473597d706e	1829	/** @defgroup HRTIM_BurstModeRegisterPreloadEnable
bogdanm	82:6473597d706e	1830	* @{
bogdanm	82:6473597d706e	1831	* @brief Constants defining whether or not burst mode registers preload
bogdanm	82:6473597d706e	1832	mechanism is enabled, i.e. a write access into a preloadable register
bogdanm	82:6473597d706e	1833	(HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
bogdanm	82:6473597d706e	1834	*/
bogdanm	82:6473597d706e	1835	#define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /!< Preload disabled: the write access is directly done into active registers /
bogdanm	82:6473597d706e	1836	#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /!< Preload enabled: the write access is done into preload registers /
bogdanm	82:6473597d706e	1837
bogdanm	82:6473597d706e	1838	#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
bogdanm	82:6473597d706e	1839	(((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) \|\| \
bogdanm	82:6473597d706e	1840	((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
bogdanm	82:6473597d706e	1841	/**
bogdanm	82:6473597d706e	1842	* @}
bogdanm	82:6473597d706e	1843	*/
bogdanm	82:6473597d706e	1844
bogdanm	82:6473597d706e	1845	/** @defgroup HRTIM_BurstModeTrigger
bogdanm	82:6473597d706e	1846	* @{
bogdanm	82:6473597d706e	1847	* @brief Constants defining the events that can be used tor trig the burst
bogdanm	82:6473597d706e	1848	* mode operation
bogdanm	82:6473597d706e	1849	*/
bogdanm	82:6473597d706e	1850	#define HRTIM_BURSTMODETRIGGER_SOFTWARE (uint32_t)0x00000000 /!< Software trigger /
bogdanm	82:6473597d706e	1851	#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /!< Master reset /
bogdanm	82:6473597d706e	1852	#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /!< Master repetition /
bogdanm	82:6473597d706e	1853	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /!< Master compare 1 /
bogdanm	82:6473597d706e	1854	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /!< Master compare 2 /
bogdanm	82:6473597d706e	1855	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /!< Master compare 3 /
bogdanm	82:6473597d706e	1856	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /!< Master compare 4 /
bogdanm	82:6473597d706e	1857	#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /!< Timer A reset /
bogdanm	82:6473597d706e	1858	#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /!< Timer A repetition /
bogdanm	82:6473597d706e	1859	#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /!< Timer A compare 1 /
bogdanm	82:6473597d706e	1860	#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /!< Timer A compare 2 /
bogdanm	82:6473597d706e	1861	#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /!< Timer B reset /
bogdanm	82:6473597d706e	1862	#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /!< Timer B repetition /
bogdanm	82:6473597d706e	1863	#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /!< Timer B compare 1 /
bogdanm	82:6473597d706e	1864	#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /!< Timer B compare 2 /
bogdanm	82:6473597d706e	1865	#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /!< Timer C reset /
bogdanm	82:6473597d706e	1866	#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /!< Timer C repetition /
bogdanm	82:6473597d706e	1867	#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /!< Timer C compare 1 /
bogdanm	82:6473597d706e	1868	#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /!< Timer C compare 2 /
bogdanm	82:6473597d706e	1869	#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /!< Timer D reset /
bogdanm	82:6473597d706e	1870	#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /!< Timer D repetition /
bogdanm	82:6473597d706e	1871	#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /!< Timer D compare 1 /
bogdanm	82:6473597d706e	1872	#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /!< Timer D compare 2 /
bogdanm	82:6473597d706e	1873	#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /!< Timer E reset /
bogdanm	82:6473597d706e	1874	#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /!< Timer E repetition /
bogdanm	82:6473597d706e	1875	#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /!< Timer E compare 1 /
bogdanm	82:6473597d706e	1876	#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /!< Timer E compare 2 /
bogdanm	82:6473597d706e	1877	#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /!< Timer A period following External Event 7 /
bogdanm	82:6473597d706e	1878	#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /!< Timer D period following External Event 8 /
bogdanm	82:6473597d706e	1879	#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /!< External Event 7 /
bogdanm	82:6473597d706e	1880	#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /!< External Event 8 /
bogdanm	82:6473597d706e	1881	#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /!< On-chip Event /
bogdanm	82:6473597d706e	1882
bogdanm	82:6473597d706e	1883	#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
bogdanm	82:6473597d706e	1884	(((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) \|\| \
bogdanm	82:6473597d706e	1885	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) \|\| \
bogdanm	82:6473597d706e	1886	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) \|\| \
bogdanm	82:6473597d706e	1887	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) \|\| \
bogdanm	82:6473597d706e	1888	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) \|\| \
bogdanm	82:6473597d706e	1889	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) \|\| \
bogdanm	82:6473597d706e	1890	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) \|\| \
bogdanm	82:6473597d706e	1891	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) \|\| \
bogdanm	82:6473597d706e	1892	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) \|\| \
bogdanm	82:6473597d706e	1893	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) \|\| \
bogdanm	82:6473597d706e	1894	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) \|\| \
bogdanm	82:6473597d706e	1895	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) \|\| \
bogdanm	82:6473597d706e	1896	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) \|\| \
bogdanm	82:6473597d706e	1897	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) \|\| \
bogdanm	82:6473597d706e	1898	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) \|\| \
bogdanm	82:6473597d706e	1899	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) \|\| \
bogdanm	82:6473597d706e	1900	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) \|\| \
bogdanm	82:6473597d706e	1901	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) \|\| \
bogdanm	82:6473597d706e	1902	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) \|\| \
bogdanm	82:6473597d706e	1903	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) \|\| \
bogdanm	82:6473597d706e	1904	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) \|\| \
bogdanm	82:6473597d706e	1905	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) \|\| \
bogdanm	82:6473597d706e	1906	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) \|\| \
bogdanm	82:6473597d706e	1907	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) \|\| \
bogdanm	82:6473597d706e	1908	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) \|\| \
bogdanm	82:6473597d706e	1909	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) \|\| \
bogdanm	82:6473597d706e	1910	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) \|\| \
bogdanm	82:6473597d706e	1911	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) \|\| \
bogdanm	82:6473597d706e	1912	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) \|\| \
bogdanm	82:6473597d706e	1913	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) \|\| \
bogdanm	82:6473597d706e	1914	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) \|\| \
bogdanm	82:6473597d706e	1915	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
bogdanm	82:6473597d706e	1916	/**
bogdanm	82:6473597d706e	1917	* @}
bogdanm	82:6473597d706e	1918	*/
bogdanm	82:6473597d706e	1919
bogdanm	82:6473597d706e	1920	/** @defgroup HRTIM_ADCTriggerUpdateSource
bogdanm	82:6473597d706e	1921	* @{
bogdanm	82:6473597d706e	1922	* @brief constants defining the source triggering the update of the
bogdanm	82:6473597d706e	1923	HRTIM_ADCxR register (transfer from preload to active register).
bogdanm	82:6473597d706e	1924	*/
bogdanm	82:6473597d706e	1925	#define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /!< Master timer /
bogdanm	82:6473597d706e	1926	#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /!< Timer A /
bogdanm	82:6473597d706e	1927	#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /!< Timer B /
bogdanm	82:6473597d706e	1928	#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 \| HRTIM_CR1_ADC1USRC_0) /!< Timer C /
bogdanm	82:6473597d706e	1929	#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /!< Timer D /
bogdanm	82:6473597d706e	1930	#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 \| HRTIM_CR1_ADC1USRC_0) /!< Timer E /
bogdanm	82:6473597d706e	1931
bogdanm	82:6473597d706e	1932	#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
bogdanm	82:6473597d706e	1933	(((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) \|\| \
bogdanm	82:6473597d706e	1934	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) \|\| \
bogdanm	82:6473597d706e	1935	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) \|\| \
bogdanm	82:6473597d706e	1936	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) \|\| \
bogdanm	82:6473597d706e	1937	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) \|\| \
bogdanm	82:6473597d706e	1938	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
bogdanm	82:6473597d706e	1939	/**
bogdanm	82:6473597d706e	1940	* @}
bogdanm	82:6473597d706e	1941	*/
bogdanm	82:6473597d706e	1942
bogdanm	82:6473597d706e	1943	/** @defgroup HRTIM_ADCTriggerEvent
bogdanm	82:6473597d706e	1944	* @{
bogdanm	82:6473597d706e	1945	* @brief constants defining the events triggering ADC conversion.
bogdanm	82:6473597d706e	1946	* HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
bogdanm	82:6473597d706e	1947	* HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
bogdanm	82:6473597d706e	1948	*/
bogdanm	82:6473597d706e	1949	#define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /!< No ADC trigger event /
bogdanm	82:6473597d706e	1950	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /!< ADC Trigger on master compare 1 /
bogdanm	82:6473597d706e	1951	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /!< ADC Trigger on master compare 2 /
bogdanm	82:6473597d706e	1952	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /!< ADC Trigger on master compare 3 /
bogdanm	82:6473597d706e	1953	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /!< ADC Trigger on master compare 4 /
bogdanm	82:6473597d706e	1954	#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /!< ADC Trigger on master period /
bogdanm	82:6473597d706e	1955	#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /!< ADC Trigger on external event 1 /
bogdanm	82:6473597d706e	1956	#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /!< ADC Trigger on external event 2 /
bogdanm	82:6473597d706e	1957	#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /!< ADC Trigger on external event 3 /
bogdanm	82:6473597d706e	1958	#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /!< ADC Trigger on external event 4 /
bogdanm	82:6473597d706e	1959	#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /!< ADC Trigger on external event 5 /
bogdanm	82:6473597d706e	1960	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /!< ADC Trigger on Timer A compare 2 /
bogdanm	82:6473597d706e	1961	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /!< ADC Trigger on Timer A compare 3 /
bogdanm	82:6473597d706e	1962	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /!< ADC Trigger on Timer A compare 4 /
bogdanm	82:6473597d706e	1963	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /!< ADC Trigger on Timer A period /
bogdanm	82:6473597d706e	1964	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /!< ADC Trigger on Timer A reset /
bogdanm	82:6473597d706e	1965	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /!< ADC Trigger on Timer B compare 2 /
bogdanm	82:6473597d706e	1966	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /!< ADC Trigger on Timer B compare 3 /
bogdanm	82:6473597d706e	1967	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /!< ADC Trigger on Timer B compare 4 /
bogdanm	82:6473597d706e	1968	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /!< ADC Trigger on Timer B period /
bogdanm	82:6473597d706e	1969	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /!< ADC Trigger on Timer B reset /
bogdanm	82:6473597d706e	1970	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /!< ADC Trigger on Timer C compare 2 /
bogdanm	82:6473597d706e	1971	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /!< ADC Trigger on Timer C compare 3 /
bogdanm	82:6473597d706e	1972	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /!< ADC Trigger on Timer C compare 4 /
bogdanm	82:6473597d706e	1973	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /!< ADC Trigger on Timer C period /
bogdanm	82:6473597d706e	1974	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /!< ADC Trigger on Timer D compare 2 /
bogdanm	82:6473597d706e	1975	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /!< ADC Trigger on Timer D compare 3 /
bogdanm	82:6473597d706e	1976	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /!< ADC Trigger on Timer D compare 4 /
bogdanm	82:6473597d706e	1977	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /!< ADC Trigger on Timer D period /
bogdanm	82:6473597d706e	1978	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /!< ADC Trigger on Timer E compare 2 /
bogdanm	82:6473597d706e	1979	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /!< ADC Trigger on Timer E compare 3 /
bogdanm	82:6473597d706e	1980	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /!< ADC Trigger on Timer E compare 4 /
bogdanm	82:6473597d706e	1981	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /!< ADC Trigger on Timer E period /
bogdanm	82:6473597d706e	1982
bogdanm	82:6473597d706e	1983	#define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /!< No ADC trigger event /
bogdanm	82:6473597d706e	1984	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /!< ADC Trigger on master compare 1 /
bogdanm	82:6473597d706e	1985	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /!< ADC Trigger on master compare 2 /
bogdanm	82:6473597d706e	1986	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /!< ADC Trigger on master compare 3 /
bogdanm	82:6473597d706e	1987	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /!< ADC Trigger on master compare 4 /
bogdanm	82:6473597d706e	1988	#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /!< ADC Trigger on master period /
bogdanm	82:6473597d706e	1989	#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /!< ADC Trigger on external event 6 /
bogdanm	82:6473597d706e	1990	#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /!< ADC Trigger on external event 7 /
bogdanm	82:6473597d706e	1991	#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /!< ADC Trigger on external event 8 /
bogdanm	82:6473597d706e	1992	#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /!< ADC Trigger on external event 9 /
bogdanm	82:6473597d706e	1993	#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /!< ADC Trigger on external event 10 /
bogdanm	82:6473597d706e	1994	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /!< ADC Trigger on Timer A compare 2 /
bogdanm	82:6473597d706e	1995	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /!< ADC Trigger on Timer A compare 3 /
bogdanm	82:6473597d706e	1996	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /!< ADC Trigger on Timer A compare 4 /
bogdanm	82:6473597d706e	1997	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /!< ADC Trigger on Timer A period /
bogdanm	82:6473597d706e	1998	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /!< ADC Trigger on Timer B compare 2 /
bogdanm	82:6473597d706e	1999	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /!< ADC Trigger on Timer B compare 3 /
bogdanm	82:6473597d706e	2000	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /!< ADC Trigger on Timer B compare 4 /
bogdanm	82:6473597d706e	2001	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /!< ADC Trigger on Timer B period /
bogdanm	82:6473597d706e	2002	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /!< ADC Trigger on Timer C compare 2 /
bogdanm	82:6473597d706e	2003	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /!< ADC Trigger on Timer C compare 3 /
bogdanm	82:6473597d706e	2004	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /!< ADC Trigger on Timer C compare 4 /
bogdanm	82:6473597d706e	2005	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /!< ADC Trigger on Timer C period /
bogdanm	82:6473597d706e	2006	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /!< ADC Trigger on Timer C reset /
bogdanm	82:6473597d706e	2007	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /!< ADC Trigger on Timer D compare 2 /
bogdanm	82:6473597d706e	2008	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /!< ADC Trigger on Timer D compare 3 /
bogdanm	82:6473597d706e	2009	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /!< ADC Trigger on Timer D compare 4 /
bogdanm	82:6473597d706e	2010	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /!< ADC Trigger on Timer D period /
bogdanm	82:6473597d706e	2011	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /!< ADC Trigger on Timer D reset /
bogdanm	82:6473597d706e	2012	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /!< ADC Trigger on Timer E compare 2 /
bogdanm	82:6473597d706e	2013	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /!< ADC Trigger on Timer E compare 3 /
bogdanm	82:6473597d706e	2014	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /!< ADC Trigger on Timer E compare 4 /
bogdanm	82:6473597d706e	2015	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /!< ADC Trigger on Timer E reset /
bogdanm	82:6473597d706e	2016
bogdanm	82:6473597d706e	2017	/**
bogdanm	82:6473597d706e	2018	* @}
bogdanm	82:6473597d706e	2019	*/
bogdanm	82:6473597d706e	2020
bogdanm	82:6473597d706e	2021	/** @defgroup HRTIM_DLLCalibrationRate
bogdanm	82:6473597d706e	2022	* @{
bogdanm	82:6473597d706e	2023	* @brief Constants defining the DLL calibration periods (in micro seconds)
bogdanm	82:6473597d706e	2024	*/
bogdanm	82:6473597d706e	2025
bogdanm	82:6473597d706e	2026	#define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /!< 1048576 tHRTIM (7.3 ms) */
bogdanm	82:6473597d706e	2027	#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /!< 131072 tHRTIM (910 µs) */
bogdanm	82:6473597d706e	2028	#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /!< 131072 tHRTIM (910 µs) */
bogdanm	82:6473597d706e	2029	#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 \| HRTIM_DLLCR_CALRTE_0) /!< 131072 tHRTIM (910 µs) */
bogdanm	82:6473597d706e	2030
bogdanm	82:6473597d706e	2031	#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
bogdanm	82:6473597d706e	2032	(((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) \|\| \
bogdanm	82:6473597d706e	2033	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) \|\| \
bogdanm	82:6473597d706e	2034	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) \|\| \
bogdanm	82:6473597d706e	2035	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
bogdanm	82:6473597d706e	2036	/**
bogdanm	82:6473597d706e	2037	* @}
bogdanm	82:6473597d706e	2038	*/
bogdanm	82:6473597d706e	2039
bogdanm	82:6473597d706e	2040	/** @defgroup HRTIM_BurstDMARegistersUpdate
bogdanm	82:6473597d706e	2041	* @{
bogdanm	82:6473597d706e	2042	* @brief Constants defining the registers that can be written during a burst
bogdanm	82:6473597d706e	2043	* DMA operation
bogdanm	82:6473597d706e	2044	*/
bogdanm	82:6473597d706e	2045	#define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /!< No register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2046	#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /!< MCR or TIMxCR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2047	#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /!< MICR or TIMxICR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2048	#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /!< MDIER or TIMxDIER register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2049	#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /!< MCNTR or CNTxCR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2050	#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /!< MPER or PERxR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2051	#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /!< MREPR or REPxR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2052	#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /!< MCMP1R or CMP1xR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2053	#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /!< MCMP2R or CMP2xR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2054	#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /!< MCMP3R or CMP3xR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2055	#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /!< MCMP4R or CMP4xR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2056	#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /!< TDxR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2057	#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /!< SET1R register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2058	#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /!< RST1R register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2059	#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /!< SET2R register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2060	#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /!< RST1R register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2061	#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /!< EEFxR1 register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2062	#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /!< EEFxR2 register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2063	#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /!< RSTxR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2064	#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /!< CHPxR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2065	#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /!< OUTxR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2066	#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /!< FLTxR register is updated by Burst DMA accesses /
bogdanm	82:6473597d706e	2067
bogdanm	82:6473597d706e	2068	#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
bogdanm	82:6473597d706e	2069	((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
bogdanm	82:6473597d706e	2070	\|\| \
bogdanm	82:6473597d706e	2071	(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm	82:6473597d706e	2072	\|\| \
bogdanm	82:6473597d706e	2073	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm	82:6473597d706e	2074	\|\| \
bogdanm	82:6473597d706e	2075	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm	82:6473597d706e	2076	\|\| \
bogdanm	82:6473597d706e	2077	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm	82:6473597d706e	2078	\|\| \
bogdanm	82:6473597d706e	2079	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
bogdanm	82:6473597d706e	2080	/**
bogdanm	82:6473597d706e	2081	* @}
bogdanm	82:6473597d706e	2082	*/
bogdanm	82:6473597d706e	2083
bogdanm	82:6473597d706e	2084	/** @defgroup HRTIM_BursttModeControl
bogdanm	82:6473597d706e	2085	* @{
bogdanm	82:6473597d706e	2086	* @brief Constants used to enable or disable the burst mode controller
bogdanm	82:6473597d706e	2087	*/
bogdanm	82:6473597d706e	2088	#define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /!< Burst mode disabled /
bogdanm	82:6473597d706e	2089	#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /!< Burst mode enabled /
bogdanm	82:6473597d706e	2090
bogdanm	82:6473597d706e	2091	#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
bogdanm	82:6473597d706e	2092	(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) \|\| \
bogdanm	82:6473597d706e	2093	((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
bogdanm	82:6473597d706e	2094	/**
bogdanm	82:6473597d706e	2095	* @}
bogdanm	82:6473597d706e	2096	*/
bogdanm	82:6473597d706e	2097
bogdanm	82:6473597d706e	2098	/** @defgroup HRTIM_FaultModeControl
bogdanm	82:6473597d706e	2099	* @{
bogdanm	82:6473597d706e	2100	* @brief Constants used to enable or disable the Fault mode
bogdanm	82:6473597d706e	2101	*/
bogdanm	82:6473597d706e	2102	#define HRTIM_FAULT_DISABLED (uint32_t)0x00000000 /!< Fault mode disabled /
bogdanm	82:6473597d706e	2103	#define HRTIM_FAULT_ENABLED (HRTIM_FLTINR1_FLT1E) /!< Fault mode enabled /
bogdanm	82:6473597d706e	2104
bogdanm	82:6473597d706e	2105	#define IS_HRTIM_FAULTCTL(FAULTCTL)\
bogdanm	82:6473597d706e	2106	(((FAULTCTL) == HRTIM_FAULT_DISABLED) \|\| \
bogdanm	82:6473597d706e	2107	((FAULTCTL) == HRTIM_FAULT_ENABLED))
bogdanm	82:6473597d706e	2108	/**
bogdanm	82:6473597d706e	2109	* @}
bogdanm	82:6473597d706e	2110	*/
bogdanm	82:6473597d706e	2111
bogdanm	82:6473597d706e	2112	/** @defgroup HRTIM_SoftwareTimerUpdate
bogdanm	82:6473597d706e	2113	* @{
bogdanm	82:6473597d706e	2114	* @brief Constants used to force timer registers update
bogdanm	82:6473597d706e	2115	*/
bogdanm	82:6473597d706e	2116	#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /!< Forces an immediate transfer from the preload to the active register in the master timer /
bogdanm	82:6473597d706e	2117	#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /!< Forces an immediate transfer from the preload to the active register in the timer A /
bogdanm	82:6473597d706e	2118	#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /!< Forces an immediate transfer from the preload to the active register in the timer B /
bogdanm	82:6473597d706e	2119	#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /!< Forces an immediate transfer from the preload to the active register in the timer C /
bogdanm	82:6473597d706e	2120	#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /!< Forces an immediate transfer from the preload to the active register in the timer D /
bogdanm	82:6473597d706e	2121	#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /!< Forces an immediate transfer from the preload to the active register in the timer E /
bogdanm	82:6473597d706e	2122
bogdanm	82:6473597d706e	2123	#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
bogdanm	82:6473597d706e	2124	/**
bogdanm	82:6473597d706e	2125	* @}
bogdanm	82:6473597d706e	2126	*/
bogdanm	82:6473597d706e	2127
bogdanm	82:6473597d706e	2128	/** @defgroup HRTIM_SoftwareTimerReset
bogdanm	82:6473597d706e	2129	* @{
bogdanm	82:6473597d706e	2130	* @brief Constants used to force timer counter reset
bogdanm	82:6473597d706e	2131	*/
bogdanm	82:6473597d706e	2132	#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /!< Resets the master timer counter /
bogdanm	82:6473597d706e	2133	#define HRTIM_TIMERRESET_A (HRTIM_CR2_TARST) /!< Resets the timer A counter /
bogdanm	82:6473597d706e	2134	#define HRTIM_TIMERRESET_B (HRTIM_CR2_TBRST) /!< Resets the timer B counter /
bogdanm	82:6473597d706e	2135	#define HRTIM_TIMERRESET_C (HRTIM_CR2_TCRST) /!< Resets the timer C counter /
bogdanm	82:6473597d706e	2136	#define HRTIM_TIMERRESET_D (HRTIM_CR2_TDRST) /!< Resets the timer D counter /
bogdanm	82:6473597d706e	2137	#define HRTIM_TIMERRESET_E (HRTIM_CR2_TERST) /!< Resets the timer E counter /
bogdanm	82:6473597d706e	2138
bogdanm	82:6473597d706e	2139	#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
bogdanm	82:6473597d706e	2140	/**
bogdanm	82:6473597d706e	2141	* @}
bogdanm	82:6473597d706e	2142	*/
bogdanm	82:6473597d706e	2143
bogdanm	82:6473597d706e	2144	/** @defgroup HRTIM_OutputLevel
bogdanm	82:6473597d706e	2145	* @{
bogdanm	82:6473597d706e	2146	* @brief Constants defining the level of a timer output
bogdanm	82:6473597d706e	2147	*/
bogdanm	82:6473597d706e	2148	#define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /!< Forces the output to its active state /
bogdanm	82:6473597d706e	2149	#define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /!< Forces the output to its inactive state /
bogdanm	82:6473597d706e	2150
bogdanm	82:6473597d706e	2151	#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
bogdanm	82:6473597d706e	2152	(((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) \|\| \
bogdanm	82:6473597d706e	2153	((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
bogdanm	82:6473597d706e	2154	/**
bogdanm	82:6473597d706e	2155	* @}
bogdanm	82:6473597d706e	2156	*/
bogdanm	82:6473597d706e	2157
bogdanm	82:6473597d706e	2158	/** @defgroup HRTIM_OutputState
bogdanm	82:6473597d706e	2159	* @{
bogdanm	82:6473597d706e	2160	* @brief Constants defining the state of a timer output
bogdanm	82:6473597d706e	2161	*/
bogdanm	82:6473597d706e	2162	#define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or
bogdanm	82:6473597d706e	2163	inactive level as programmed in the crossbar unit */
bogdanm	82:6473597d706e	2164	#define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the
bogdanm	82:6473597d706e	2165	outputs are disabled by software or during a burst mode operation */
bogdanm	82:6473597d706e	2166	#define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on
bogdanm	82:6473597d706e	2167	FAULTx inputs */
bogdanm	82:6473597d706e	2168	/**
bogdanm	82:6473597d706e	2169	* @}
bogdanm	82:6473597d706e	2170	*/
bogdanm	82:6473597d706e	2171
bogdanm	82:6473597d706e	2172	/** @defgroup HRTIM_BurstModeStatus
bogdanm	82:6473597d706e	2173	* @{
bogdanm	82:6473597d706e	2174	* @brief Constants defining the operating state of the burst mode controller
bogdanm	82:6473597d706e	2175	*/
bogdanm	82:6473597d706e	2176	#define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /!< Normal operation /
bogdanm	82:6473597d706e	2177	#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /!< Burst operation on-going /
bogdanm	82:6473597d706e	2178	/**
bogdanm	82:6473597d706e	2179	* @}
bogdanm	82:6473597d706e	2180	*/
bogdanm	82:6473597d706e	2181
bogdanm	82:6473597d706e	2182	/** @defgroup HRTIM_CurrentPushPullStatus
bogdanm	82:6473597d706e	2183	* @{
bogdanm	82:6473597d706e	2184	* @brief Constants defining on which output the signal is currently applied
bogdanm	82:6473597d706e	2185	* in push-pull mode
bogdanm	82:6473597d706e	2186	*/
bogdanm	82:6473597d706e	2187	#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /!< Signal applied on output 1 and output 2 forced inactive /
bogdanm	82:6473597d706e	2188	#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /!< Signal applied on output 2 and output 1 forced inactive /
bogdanm	82:6473597d706e	2189	/**
bogdanm	82:6473597d706e	2190	* @}
bogdanm	82:6473597d706e	2191	*/
bogdanm	82:6473597d706e	2192
bogdanm	82:6473597d706e	2193	/** @defgroup HRTIM_IdlePushPullStatus
bogdanm	82:6473597d706e	2194	* @{
bogdanm	82:6473597d706e	2195	* @brief Constants defining on which output the signal was applied, in
bogdanm	82:6473597d706e	2196	* push-pull mode balanced fault mode or delayed idle mode, when the
bogdanm	82:6473597d706e	2197	* protection was triggered
bogdanm	82:6473597d706e	2198	*/
bogdanm	82:6473597d706e	2199	#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /!< Protection occurred when the output 1 was active and output 2 forced inactive /
bogdanm	82:6473597d706e	2200	#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /!< Protection occurred when the output 2 was active and output 1 forced inactive /
bogdanm	82:6473597d706e	2201	/**
bogdanm	82:6473597d706e	2202	* @}
bogdanm	82:6473597d706e	2203	*/
bogdanm	82:6473597d706e	2204
bogdanm	82:6473597d706e	2205	/** @defgroup HRTIM_CommonInterrupt
bogdanm	82:6473597d706e	2206	* @{
bogdanm	82:6473597d706e	2207	*/
bogdanm	82:6473597d706e	2208	#define HRTIM_IT_FLT1 HRTIM_ISR_FLT1 /!< Fault 1 interrupt flag /
bogdanm	82:6473597d706e	2209	#define HRTIM_IT_FLT2 HRTIM_ISR_FLT2 /!< Fault 2 interrupt flag /
bogdanm	82:6473597d706e	2210	#define HRTIM_IT_FLT3 HRTIM_ISR_FLT3 /!< Fault 3 interrupt flag /
bogdanm	82:6473597d706e	2211	#define HRTIM_IT_FLT4 HRTIM_ISR_FLT4 /!< Fault 4 interrupt flag /
bogdanm	82:6473597d706e	2212	#define HRTIM_IT_FLT5 HRTIM_ISR_FLT5 /!< Fault 5 interrupt flag /
bogdanm	82:6473597d706e	2213	#define HRTIM_IT_SYSFLT HRTIM_ISR_SYSFLT /!< System Fault interrupt flag /
bogdanm	82:6473597d706e	2214	#define HRTIM_IT_DLLRDY HRTIM_ISR_DLLRDY /!< DLL ready interrupt flag /
bogdanm	82:6473597d706e	2215	#define HRTIM_IT_BMPER HRTIM_ISR_BMPER /!< Burst mode period interrupt flag /
bogdanm	82:6473597d706e	2216
bogdanm	82:6473597d706e	2217	#define IS_HRTIM_IT(IT)\
bogdanm	82:6473597d706e	2218	(((IT) == HRTIM_ISR_FLT1) \|\| \
bogdanm	82:6473597d706e	2219	((IT) == HRTIM_ISR_FLT2) \|\| \
bogdanm	82:6473597d706e	2220	((IT) == HRTIM_ISR_FLT3) \|\| \
bogdanm	82:6473597d706e	2221	((IT) == HRTIM_ISR_FLT4) \|\| \
bogdanm	82:6473597d706e	2222	((IT) == HRTIM_ISR_FLT5) \|\| \
bogdanm	82:6473597d706e	2223	((IT) == HRTIM_ISR_SYSFLT) \|\| \
bogdanm	82:6473597d706e	2224	((IT) == HRTIM_ISR_DLLRDY) \|\| \
bogdanm	82:6473597d706e	2225	((IT) == HRTIM_ISR_BMPER))
bogdanm	82:6473597d706e	2226	/**
bogdanm	82:6473597d706e	2227	* @}
bogdanm	82:6473597d706e	2228	*/
bogdanm	82:6473597d706e	2229
bogdanm	82:6473597d706e	2230	/** @defgroup HRTIM_MasterInterrupt
bogdanm	82:6473597d706e	2231	* @{
bogdanm	82:6473597d706e	2232	*/
bogdanm	82:6473597d706e	2233	#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /!< Master compare 1 interrupt flag /
bogdanm	82:6473597d706e	2234	#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /!< Master compare 2 interrupt flag /
bogdanm	82:6473597d706e	2235	#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /!< Master compare 3 interrupt flag /
bogdanm	82:6473597d706e	2236	#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /!< Master compare 4 interrupt flag /
bogdanm	82:6473597d706e	2237	#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /!< Master Repetition interrupt flag /
bogdanm	82:6473597d706e	2238	#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /!< Synchronization input interrupt flag /
bogdanm	82:6473597d706e	2239	#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /!< Master update interrupt flag /
bogdanm	82:6473597d706e	2240
bogdanm	82:6473597d706e	2241	#define IS_HRTIM_MASTER_IT(IT)\
bogdanm	82:6473597d706e	2242	(((IT) == HRTIM_MDIER_MCMP1IE) \|\| \
bogdanm	82:6473597d706e	2243	((IT) == HRTIM_MDIER_MCMP2IE) \|\| \
bogdanm	82:6473597d706e	2244	((IT) == HRTIM_MDIER_MCMP3IE) \|\| \
bogdanm	82:6473597d706e	2245	((IT) == HRTIM_MDIER_MCMP4IE) \|\| \
bogdanm	82:6473597d706e	2246	((IT) == HRTIM_MDIER_MREPIE) \|\| \
bogdanm	82:6473597d706e	2247	((IT) == HRTIM_MDIER_SYNCIE) \|\| \
bogdanm	82:6473597d706e	2248	((IT) == HRTIM_MDIER_MUPDIE))
bogdanm	82:6473597d706e	2249
bogdanm	82:6473597d706e	2250	/** @defgroup HRTIM_MasterFlag
bogdanm	82:6473597d706e	2251	* @{
bogdanm	82:6473597d706e	2252	*/
bogdanm	82:6473597d706e	2253	#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /!< Master compare 1 interrupt flag /
bogdanm	82:6473597d706e	2254	#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /!< Master compare 2 interrupt flag /
bogdanm	82:6473597d706e	2255	#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /!< Master compare 3 interrupt flag /
bogdanm	82:6473597d706e	2256	#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /!< Master compare 4 interrupt flag /
bogdanm	82:6473597d706e	2257	#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /!< Master Repetition interrupt flag /
bogdanm	82:6473597d706e	2258	#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /!< Synchronization input interrupt flag /
bogdanm	82:6473597d706e	2259	#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /!< Master update interrupt flag /
bogdanm	82:6473597d706e	2260
bogdanm	82:6473597d706e	2261	#define IS_HRTIM_MASTER_FLAG(FLAG)\
bogdanm	82:6473597d706e	2262	(((FLAG) == HRTIM_MISR_MCMP1) \|\| \
bogdanm	82:6473597d706e	2263	((FLAG) == HRTIM_MISR_MCMP2) \|\| \
bogdanm	82:6473597d706e	2264	((FLAG) == HRTIM_MISR_MCMP3) \|\| \
bogdanm	82:6473597d706e	2265	((FLAG) == HRTIM_MISR_MCMP4) \|\| \
bogdanm	82:6473597d706e	2266	((FLAG) == HRTIM_MISR_MREP) \|\| \
bogdanm	82:6473597d706e	2267	((FLAG) == HRTIM_MISR_SYNC) \|\| \
bogdanm	82:6473597d706e	2268	((FLAG) == HRTIM_MISR_MUPD))
bogdanm	82:6473597d706e	2269	/**
bogdanm	82:6473597d706e	2270	* @}
bogdanm	82:6473597d706e	2271	*/
bogdanm	82:6473597d706e	2272
bogdanm	82:6473597d706e	2273	/** @defgroup HRTIM_TimingUnitInterrupt
bogdanm	82:6473597d706e	2274	* @{
bogdanm	82:6473597d706e	2275	*/
bogdanm	82:6473597d706e	2276	#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /!< Timer compare 1 interrupt flag /
bogdanm	82:6473597d706e	2277	#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /!< Timer compare 2 interrupt flag /
bogdanm	82:6473597d706e	2278	#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /!< Timer compare 3 interrupt flag /
bogdanm	82:6473597d706e	2279	#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /!< Timer compare 4 interrupt flag /
bogdanm	82:6473597d706e	2280	#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /!< Timer repetition interrupt flag /
bogdanm	82:6473597d706e	2281	#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /!< Timer update interrupt flag /
bogdanm	82:6473597d706e	2282	#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /!< Timer capture 1 interrupt flag /
bogdanm	82:6473597d706e	2283	#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /!< Timer capture 2 interrupt flag /
bogdanm	82:6473597d706e	2284	#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /!< Timer output 1 set interrupt flag /
bogdanm	82:6473597d706e	2285	#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /!< Timer output 1 reset interrupt flag /
bogdanm	82:6473597d706e	2286	#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /!< Timer output 2 set interrupt flag /
bogdanm	82:6473597d706e	2287	#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /!< Timer output 2 reset interrupt flag /
bogdanm	82:6473597d706e	2288	#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /!< Timer reset interrupt flag /
bogdanm	82:6473597d706e	2289	#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRT1IE /!< Timer delay protection interrupt flag /
bogdanm	82:6473597d706e	2290
bogdanm	82:6473597d706e	2291	#define IS_HRTIM_TIM_IT(IT)\
bogdanm	82:6473597d706e	2292	(((IT) == HRTIM_TIMDIER_CMP1IE) \|\| \
bogdanm	82:6473597d706e	2293	((IT) == HRTIM_TIMDIER_CMP2IE) \|\| \
bogdanm	82:6473597d706e	2294	((IT) == HRTIM_TIMDIER_CMP3IE) \|\| \
bogdanm	82:6473597d706e	2295	((IT) == HRTIM_TIMDIER_CMP4IE) \|\| \
bogdanm	82:6473597d706e	2296	((IT) == HRTIM_TIMDIER_REPIE) \|\| \
bogdanm	82:6473597d706e	2297	((IT) == HRTIM_TIMDIER_UPDIE) \|\| \
bogdanm	82:6473597d706e	2298	((IT) == HRTIM_TIMDIER_CPT1IE) \|\| \
bogdanm	82:6473597d706e	2299	((IT) == HRTIM_TIMDIER_CPT2IE) \|\| \
bogdanm	82:6473597d706e	2300	((IT) == HRTIM_TIMDIER_SET1IE) \|\| \
bogdanm	82:6473597d706e	2301	((IT) == HRTIM_TIMDIER_RST1IE) \|\| \
bogdanm	82:6473597d706e	2302	((IT) == HRTIM_TIMDIER_SET2IE) \|\| \
bogdanm	82:6473597d706e	2303	((IT) == HRTIM_TIMDIER_RST2IE) \|\| \
bogdanm	82:6473597d706e	2304	((IT) == HRTIM_TIMDIER_RSTIE) \|\| \
bogdanm	82:6473597d706e	2305	((IT) == HRTIM_TIMDIER_DLYPRTIE))
bogdanm	82:6473597d706e	2306
bogdanm	82:6473597d706e	2307	/**
bogdanm	82:6473597d706e	2308	* @}
bogdanm	82:6473597d706e	2309	*/
bogdanm	82:6473597d706e	2310
bogdanm	82:6473597d706e	2311	/** @defgroup HRTIM_TimingUnitFlag
bogdanm	82:6473597d706e	2312	* @{
bogdanm	82:6473597d706e	2313	*/
bogdanm	82:6473597d706e	2314	#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /!< Timer compare 1 interrupt flag /
bogdanm	82:6473597d706e	2315	#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /!< Timer compare 2 interrupt flag /
bogdanm	82:6473597d706e	2316	#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /!< Timer compare 3 interrupt flag /
bogdanm	82:6473597d706e	2317	#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /!< Timer compare 4 interrupt flag /
bogdanm	82:6473597d706e	2318	#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /!< Timer repetition interrupt flag /
bogdanm	82:6473597d706e	2319	#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /!< Timer update interrupt flag /
bogdanm	82:6473597d706e	2320	#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /!< Timer capture 1 interrupt flag /
bogdanm	82:6473597d706e	2321	#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /!< Timer capture 2 interrupt flag /
bogdanm	82:6473597d706e	2322	#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /!< Timer output 1 set interrupt flag /
bogdanm	82:6473597d706e	2323	#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /!< Timer output 1 reset interrupt flag /
bogdanm	82:6473597d706e	2324	#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /!< Timer output 2 set interrupt flag /
bogdanm	82:6473597d706e	2325	#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /!< Timer output 2 reset interrupt flag /
bogdanm	82:6473597d706e	2326	#define HRTIM_TIM_FLAG_RST HRTIM_TIMDIER_RSTIE /!< Timer reset interrupt flag /
bogdanm	82:6473597d706e	2327	#define HRTIM_TIM_FLAG_DLYPRT1 HRTIM_TIMISR_DLYPRT /!< Timer delay protection interrupt flag /
bogdanm	82:6473597d706e	2328
bogdanm	82:6473597d706e	2329	#define IS_HRTIM_TIM_FLAG(FLAG)\
bogdanm	82:6473597d706e	2330	(((FLAG) == HRTIM_TIM_FLAG_CMP1) \|\| \
bogdanm	82:6473597d706e	2331	((FLAG) == HRTIM_TIM_FLAG_CMP2) \|\| \
bogdanm	82:6473597d706e	2332	((FLAG) == HRTIM_TIM_FLAG_CMP3) \|\| \
bogdanm	82:6473597d706e	2333	((FLAG) == HRTIM_TIM_FLAG_CMP4) \|\| \
bogdanm	82:6473597d706e	2334	((FLAG) == HRTIM_TIM_FLAG_REP) \|\| \
bogdanm	82:6473597d706e	2335	((FLAG) == HRTIM_TIM_FLAG_UPD) \|\| \
bogdanm	82:6473597d706e	2336	((FLAG) == HRTIM_TIM_FLAG_CPT1) \|\| \
bogdanm	82:6473597d706e	2337	((FLAG) == HRTIM_TIM_FLAG_CPT2) \|\| \
bogdanm	82:6473597d706e	2338	((FLAG) == HRTIM_TIM_FLAG_SET1) \|\| \
bogdanm	82:6473597d706e	2339	((FLAG) == HRTIM_TIM_FLAG_RST1) \|\| \
bogdanm	82:6473597d706e	2340	((FLAG) == HRTIM_TIM_FLAG_SET2) \|\| \
bogdanm	82:6473597d706e	2341	((FLAG) == HRTIM_TIM_FLAG_RST2) \|\| \
bogdanm	82:6473597d706e	2342	((FLAG) == HRTIM_TIM_FLAG_RST) \|\| \
bogdanm	82:6473597d706e	2343	((FLAG) == HRTIM_TIM_FLAG_DLYPRT1))
bogdanm	82:6473597d706e	2344
bogdanm	82:6473597d706e	2345	/**
bogdanm	82:6473597d706e	2346	* @}
bogdanm	82:6473597d706e	2347	*/
bogdanm	82:6473597d706e	2348
bogdanm	82:6473597d706e	2349	/** @defgroup HRTIM_MasterDMARequest
bogdanm	82:6473597d706e	2350	* @{
bogdanm	82:6473597d706e	2351	*/
bogdanm	82:6473597d706e	2352	#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /!< Master compare 1 DMA request flag /
bogdanm	82:6473597d706e	2353	#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /!< Master compare 2 DMA request flag /
bogdanm	82:6473597d706e	2354	#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /!< Master compare 3 DMA request flag /
bogdanm	82:6473597d706e	2355	#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /!< Master compare 4 DMA request flag /
bogdanm	82:6473597d706e	2356	#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /!< Master Repetition DMA request flag /
bogdanm	82:6473597d706e	2357	#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /!< Synchronization input DMA request flag /
bogdanm	82:6473597d706e	2358	#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /!< Master update DMA request flag /
bogdanm	82:6473597d706e	2359
bogdanm	82:6473597d706e	2360	#define IS_HRTIM_MASTER_DMA(DMA)\
bogdanm	82:6473597d706e	2361	(((DMA) == HRTIM_MDIER_MCMP1DE) \|\| \
bogdanm	82:6473597d706e	2362	((DMA) == HRTIM_MDIER_MCMP2DE) \|\| \
bogdanm	82:6473597d706e	2363	((DMA) == HRTIM_MDIER_MCMP3DE) \|\| \
bogdanm	82:6473597d706e	2364	((DMA) == HRTIM_MDIER_MCMP4DE) \|\| \
bogdanm	82:6473597d706e	2365	((DMA) == HRTIM_MDIER_MREPDE) \|\| \
bogdanm	82:6473597d706e	2366	((DMA) == HRTIM_MDIER_SYNCDE) \|\| \
bogdanm	82:6473597d706e	2367	((DMA) == HRTIM_MDIER_MUPDDE))
bogdanm	82:6473597d706e	2368	/**
bogdanm	82:6473597d706e	2369	* @}
bogdanm	82:6473597d706e	2370	*/
bogdanm	82:6473597d706e	2371
bogdanm	82:6473597d706e	2372	/** @defgroup HRTIM_TimingUnitDMARequest
bogdanm	82:6473597d706e	2373	* @{
bogdanm	82:6473597d706e	2374	*/
bogdanm	82:6473597d706e	2375	#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /!< Timer compare 1 interrupt flag /
bogdanm	82:6473597d706e	2376	#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /!< Timer compare 2 interrupt flag /
bogdanm	82:6473597d706e	2377	#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /!< Timer compare 3 interrupt flag /
bogdanm	82:6473597d706e	2378	#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /!< Timer compare 4 interrupt flag /
bogdanm	82:6473597d706e	2379	#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /!< Timer repetition interrupt flag /
bogdanm	82:6473597d706e	2380	#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /!< Timer update interrupt flag /
bogdanm	82:6473597d706e	2381	#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /!< Timer capture 1 interrupt flag /
bogdanm	82:6473597d706e	2382	#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /!< Timer capture 2 interrupt flag /
bogdanm	82:6473597d706e	2383	#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /!< Timer output 1 set interrupt flag /
bogdanm	82:6473597d706e	2384	#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /!< Timer output 1 reset interrupt flag /
bogdanm	82:6473597d706e	2385	#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /!< Timer output 2 set interrupt flag /
bogdanm	82:6473597d706e	2386	#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /!< Timer output 2 reset interrupt flag /
bogdanm	82:6473597d706e	2387	#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /!< Timer reset interrupt flag /
bogdanm	82:6473597d706e	2388	#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /!< Timer delay protection interrupt flag /
bogdanm	82:6473597d706e	2389
bogdanm	82:6473597d706e	2390	#define IS_HRTIM_TIM_DMA(DMA)\
bogdanm	82:6473597d706e	2391	(((DMA) == HRTIM_TIMDIER_CMP1DE) \|\| \
bogdanm	82:6473597d706e	2392	((DMA) == HRTIM_TIMDIER_CMP2DE) \|\| \
bogdanm	82:6473597d706e	2393	((DMA) == HRTIM_TIMDIER_CMP3DE) \|\| \
bogdanm	82:6473597d706e	2394	((DMA) == HRTIM_TIMDIER_CMP4DE) \|\| \
bogdanm	82:6473597d706e	2395	((DMA) == HRTIM_TIMDIER_REPDE) \|\| \
bogdanm	82:6473597d706e	2396	((DMA) == HRTIM_TIMDIER_UPDDE) \|\| \
bogdanm	82:6473597d706e	2397	((DMA) == HRTIM_TIMDIER_CPT1DE) \|\| \
bogdanm	82:6473597d706e	2398	((DMA) == HRTIM_TIMDIER_CPT2DE) \|\| \
bogdanm	82:6473597d706e	2399	((DMA) == HRTIM_TIMDIER_SET1DE) \|\| \
bogdanm	82:6473597d706e	2400	((DMA) == HRTIM_TIMDIER_RST1DE) \|\| \
bogdanm	82:6473597d706e	2401	((DMA) == HRTIM_TIMDIER_SET2DE) \|\| \
bogdanm	82:6473597d706e	2402	((DMA) == HRTIM_TIMDIER_RST2DE) \|\| \
bogdanm	82:6473597d706e	2403	((DMA) == HRTIM_TIMDIER_RSTDE) \|\| \
bogdanm	82:6473597d706e	2404	((DMA) == HRTIM_TIMDIER_DLYPRTDE))
bogdanm	82:6473597d706e	2405
bogdanm	82:6473597d706e	2406	/**
bogdanm	82:6473597d706e	2407	* @}
bogdanm	82:6473597d706e	2408	*/
bogdanm	82:6473597d706e	2409
bogdanm	82:6473597d706e	2410	/**
bogdanm	82:6473597d706e	2411	* @}
bogdanm	82:6473597d706e	2412	*/
bogdanm	82:6473597d706e	2413
bogdanm	82:6473597d706e	2414	/** @defgroup HRTIM_Instancedefinition
bogdanm	82:6473597d706e	2415	* @{
bogdanm	82:6473597d706e	2416	*/
bogdanm	82:6473597d706e	2417	#define IS_HRTIM_INSTANCE(INSTANCE) (INSTANCE) == HRTIM1)
bogdanm	82:6473597d706e	2418	/**
bogdanm	82:6473597d706e	2419	* @}
bogdanm	82:6473597d706e	2420	*/
bogdanm	82:6473597d706e	2421
bogdanm	82:6473597d706e	2422	/**
bogdanm	82:6473597d706e	2423	* @}
bogdanm	82:6473597d706e	2424	*/
bogdanm	82:6473597d706e	2425
bogdanm	82:6473597d706e	2426	/* Exported macro ------------------------------------------------------------*/
bogdanm	82:6473597d706e	2427
bogdanm	82:6473597d706e	2428
bogdanm	82:6473597d706e	2429	/** @brief Enables or disables the timer counter(s)
bogdanm	82:6473597d706e	2430	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	82:6473597d706e	2431	* @param __TIMERS__: timersto enable/disable
bogdanm	82:6473597d706e	2432	* This parameter can be any combinations of the following values:
bogdanm	82:6473597d706e	2433	* @arg HRTIM_TIMERID_MASTER: Master timer identifier
bogdanm	82:6473597d706e	2434	* @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
bogdanm	82:6473597d706e	2435	* @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
bogdanm	82:6473597d706e	2436	* @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
bogdanm	82:6473597d706e	2437	* @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
bogdanm	82:6473597d706e	2438	* @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
bogdanm	82:6473597d706e	2439	* @retval None
bogdanm	82:6473597d706e	2440	*/
bogdanm	82:6473597d706e	2441	#define __HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->HRTIM_MASTER.MCR \|= (__TIMERS__))
bogdanm	82:6473597d706e	2442
bogdanm	82:6473597d706e	2443	/* The counter of a timing unit is disabled only if all the timer outputs */
bogdanm	82:6473597d706e	2444	/* are disabled and no capture is configured */
bogdanm	82:6473597d706e	2445	#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN \| HRTIM_OENR_TA1OEN)
bogdanm	82:6473597d706e	2446	#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN \| HRTIM_OENR_TB1OEN)
bogdanm	82:6473597d706e	2447	#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN \| HRTIM_OENR_TC1OEN)
bogdanm	82:6473597d706e	2448	#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN \| HRTIM_OENR_TD1OEN)
bogdanm	82:6473597d706e	2449	#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN \| HRTIM_OENR_TE1OEN)
bogdanm	82:6473597d706e	2450	#define __HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
bogdanm	82:6473597d706e	2451	do {\
bogdanm	82:6473597d706e	2452	if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
bogdanm	82:6473597d706e	2453	{\
bogdanm	82:6473597d706e	2454	((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_MASTER);\
bogdanm	82:6473597d706e	2455	}\
bogdanm	82:6473597d706e	2456	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
bogdanm	82:6473597d706e	2457	{\
bogdanm	82:6473597d706e	2458	if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TAOEN_MASK) == RESET)\
bogdanm	82:6473597d706e	2459	{\
bogdanm	82:6473597d706e	2460	((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_A);\
bogdanm	82:6473597d706e	2461	}\
bogdanm	82:6473597d706e	2462	}\
bogdanm	82:6473597d706e	2463	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
bogdanm	82:6473597d706e	2464	{\
bogdanm	82:6473597d706e	2465	if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TBOEN_MASK) == RESET)\
bogdanm	82:6473597d706e	2466	{\
bogdanm	82:6473597d706e	2467	((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_B);\
bogdanm	82:6473597d706e	2468	}\
bogdanm	82:6473597d706e	2469	}\
bogdanm	82:6473597d706e	2470	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
bogdanm	82:6473597d706e	2471	{\
bogdanm	82:6473597d706e	2472	if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TCOEN_MASK) == RESET)\
bogdanm	82:6473597d706e	2473	{\
bogdanm	82:6473597d706e	2474	((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_C);\
bogdanm	82:6473597d706e	2475	}\
bogdanm	82:6473597d706e	2476	}\
bogdanm	82:6473597d706e	2477	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
bogdanm	82:6473597d706e	2478	{\
bogdanm	82:6473597d706e	2479	if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TDOEN_MASK) == RESET)\
bogdanm	82:6473597d706e	2480	{\
bogdanm	82:6473597d706e	2481	((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_D);\
bogdanm	82:6473597d706e	2482	}\
bogdanm	82:6473597d706e	2483	}\
bogdanm	82:6473597d706e	2484	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
bogdanm	82:6473597d706e	2485	{\
bogdanm	82:6473597d706e	2486	if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TEOEN_MASK) == RESET)\
bogdanm	82:6473597d706e	2487	{\
bogdanm	82:6473597d706e	2488	((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_E);\
bogdanm	82:6473597d706e	2489	}\
bogdanm	82:6473597d706e	2490	}\
bogdanm	82:6473597d706e	2491	} while(0)
bogdanm	82:6473597d706e	2492
bogdanm	82:6473597d706e	2493	/* Exported functions --------------------------------------------------------*/
bogdanm	82:6473597d706e	2494
bogdanm	82:6473597d706e	2495	/* Simple time base related functions *****************************************/
bogdanm	82:6473597d706e	2496	void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
bogdanm	82:6473597d706e	2497
bogdanm	82:6473597d706e	2498	void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
bogdanm	82:6473597d706e	2499
bogdanm	82:6473597d706e	2500	void HRTIM_SimpleBaseStart(HRTIM_TypeDef *hrtim, uint32_t TimerIdx);
bogdanm	82:6473597d706e	2501	void HRTIM_SimpleBaseStop(HRTIM_TypeDef *hrtim, uint32_t TimerIdx);
bogdanm	82:6473597d706e	2502
bogdanm	82:6473597d706e	2503	/* Simple output compare related functions ************************************/
bogdanm	82:6473597d706e	2504	void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
bogdanm	82:6473597d706e	2505
bogdanm	82:6473597d706e	2506	void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2507	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2508	uint32_t OCChannel,
bogdanm	82:6473597d706e	2509	HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg);
bogdanm	82:6473597d706e	2510
bogdanm	82:6473597d706e	2511	void HRTIM_SimpleOCStart(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2512	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2513	uint32_t OCChannel);
bogdanm	82:6473597d706e	2514	void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
bogdanm	82:6473597d706e	2515	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2516	uint32_t OCChannel);
bogdanm	82:6473597d706e	2517	/* Simple PWM output related functions ****************************************/
bogdanm	82:6473597d706e	2518	void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
bogdanm	82:6473597d706e	2519
bogdanm	82:6473597d706e	2520	void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2521	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2522	uint32_t PWMChannel,
bogdanm	82:6473597d706e	2523	HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg);
bogdanm	82:6473597d706e	2524
bogdanm	82:6473597d706e	2525	void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
bogdanm	82:6473597d706e	2526	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2527	uint32_t PWMChannel);
bogdanm	82:6473597d706e	2528	void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
bogdanm	82:6473597d706e	2529	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2530	uint32_t PWMChannel);
bogdanm	82:6473597d706e	2531	/* Simple capture related functions *******************************************/
bogdanm	82:6473597d706e	2532	void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
bogdanm	82:6473597d706e	2533
bogdanm	82:6473597d706e	2534	void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2535	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2536	uint32_t CaptureChannel,
bogdanm	82:6473597d706e	2537	HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg);
bogdanm	82:6473597d706e	2538
bogdanm	82:6473597d706e	2539	void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
bogdanm	82:6473597d706e	2540	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2541	uint32_t CaptureChannel);
bogdanm	82:6473597d706e	2542	void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
bogdanm	82:6473597d706e	2543	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2544	uint32_t CaptureChannel);
bogdanm	82:6473597d706e	2545	/* SImple one pulse related functions *****************************************/
bogdanm	82:6473597d706e	2546	void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
bogdanm	82:6473597d706e	2547
bogdanm	82:6473597d706e	2548	void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2549	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2550	uint32_t OnePulseChannel,
bogdanm	82:6473597d706e	2551	HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg);
bogdanm	82:6473597d706e	2552
bogdanm	82:6473597d706e	2553	void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
bogdanm	82:6473597d706e	2554	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2555	uint32_t OnePulseChannel);
bogdanm	82:6473597d706e	2556	void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIM_,
bogdanm	82:6473597d706e	2557	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2558	uint32_t OnePulseChannel);
bogdanm	82:6473597d706e	2559	/* Waveform related functions *************************************************/
bogdanm	82:6473597d706e	2560	void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
bogdanm	82:6473597d706e	2561	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2562	HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
bogdanm	82:6473597d706e	2563	HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct);
bogdanm	82:6473597d706e	2564
bogdanm	82:6473597d706e	2565	void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2566	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2567	HRTIM_TimerCfgTypeDef * HRTIM_TimerCfgStruct);
bogdanm	82:6473597d706e	2568
bogdanm	82:6473597d706e	2569	void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2570	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2571	uint32_t CompareUnit,
bogdanm	82:6473597d706e	2572	HRTIM_CompareCfgTypeDef* pCompareCfg);
bogdanm	82:6473597d706e	2573
bogdanm	82:6473597d706e	2574	void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
bogdanm	82:6473597d706e	2575	uint32_t CompareUnit,
bogdanm	82:6473597d706e	2576	uint32_t Compare);
bogdanm	82:6473597d706e	2577	void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2578	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2579	uint32_t CaptureUnit,
bogdanm	82:6473597d706e	2580	HRTIM_CaptureCfgTypeDef* pCaptureCfg);
bogdanm	82:6473597d706e	2581
bogdanm	82:6473597d706e	2582	void HRTIM_WaveformOuputConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2583	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2584	uint32_t Output,
bogdanm	82:6473597d706e	2585	HRTIM_OutputCfgTypeDef * pOutputCfg);
bogdanm	82:6473597d706e	2586
bogdanm	82:6473597d706e	2587	void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2588	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2589	uint32_t Event,
bogdanm	82:6473597d706e	2590	HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
bogdanm	82:6473597d706e	2591
bogdanm	82:6473597d706e	2592	void HRTIM_DeadTimeConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2593	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2594	HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
bogdanm	82:6473597d706e	2595
bogdanm	82:6473597d706e	2596	void HRTIM_ChopperModeConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2597	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2598	HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
bogdanm	82:6473597d706e	2599
bogdanm	82:6473597d706e	2600	void HRTIM_BurstDMAConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2601	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2602	uint32_t RegistersToUpdate);
bogdanm	82:6473597d706e	2603
bogdanm	82:6473597d706e	2604	void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx,
bogdanm	82:6473597d706e	2605	HRTIM_SynchroCfgTypeDef * pSynchroCfg);
bogdanm	82:6473597d706e	2606
bogdanm	82:6473597d706e	2607	void HRTIM_BurstModeConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2608	HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
bogdanm	82:6473597d706e	2609
bogdanm	82:6473597d706e	2610	void HRTIM_EventConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2611	uint32_t Event,
bogdanm	82:6473597d706e	2612	HRTIM_EventCfgTypeDef* pEventCfg);
bogdanm	82:6473597d706e	2613
bogdanm	82:6473597d706e	2614	void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2615	uint32_t Prescaler);
bogdanm	82:6473597d706e	2616
bogdanm	82:6473597d706e	2617	void HRTIM_FaultConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2618	HRTIM_FaultCfgTypeDef* pFaultCfg,
bogdanm	82:6473597d706e	2619	uint32_t Fault);
bogdanm	82:6473597d706e	2620
bogdanm	82:6473597d706e	2621	void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2622	uint32_t Prescaler);
bogdanm	82:6473597d706e	2623	void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable);
bogdanm	82:6473597d706e	2624
bogdanm	82:6473597d706e	2625	void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2626	uint32_t ADCTrigger,
bogdanm	82:6473597d706e	2627	HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
bogdanm	82:6473597d706e	2628
bogdanm	82:6473597d706e	2629	void HRTIM_WaveformCounterStart(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2630	uint32_t TimersToStart);
bogdanm	82:6473597d706e	2631
bogdanm	82:6473597d706e	2632	void HRTIM_WaveformCounterStop(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2633	uint32_t TimersToStop);
bogdanm	82:6473597d706e	2634
bogdanm	82:6473597d706e	2635	void HRTIM_WaveformOutputStart(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2636	uint32_t OuputsToStart);
bogdanm	82:6473597d706e	2637	void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIM_,
bogdanm	82:6473597d706e	2638	uint32_t OuputsToStop);
bogdanm	82:6473597d706e	2639
bogdanm	82:6473597d706e	2640	void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2641	uint32_t CalibrationRate);
bogdanm	82:6473597d706e	2642
bogdanm	82:6473597d706e	2643	/* Interrupt/flags and DMA management */
bogdanm	82:6473597d706e	2644	void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState);
bogdanm	82:6473597d706e	2645	void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState);
bogdanm	82:6473597d706e	2646
bogdanm	82:6473597d706e	2647	void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
bogdanm	82:6473597d706e	2648	void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
bogdanm	82:6473597d706e	2649
bogdanm	82:6473597d706e	2650	void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
bogdanm	82:6473597d706e	2651	void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
bogdanm	82:6473597d706e	2652
bogdanm	82:6473597d706e	2653	FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
bogdanm	82:6473597d706e	2654	FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
bogdanm	82:6473597d706e	2655
bogdanm	82:6473597d706e	2656	ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
bogdanm	82:6473597d706e	2657	ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
bogdanm	82:6473597d706e	2658
bogdanm	82:6473597d706e	2659
bogdanm	82:6473597d706e	2660	void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState);
bogdanm	82:6473597d706e	2661
bogdanm	82:6473597d706e	2662	void HRTIM_BurstModeCtl(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2663	uint32_t Enable);
bogdanm	82:6473597d706e	2664
bogdanm	82:6473597d706e	2665	void HRTIM_SoftwareCapture(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2666	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2667	uint32_t CaptureUnit);
bogdanm	82:6473597d706e	2668
bogdanm	82:6473597d706e	2669	void HRTIM_SoftwareUpdate(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2670	uint32_t TimersToUpdate);
bogdanm	82:6473597d706e	2671
bogdanm	82:6473597d706e	2672	void HRTIM_SoftwareReset(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2673	uint32_t TimersToReset);
bogdanm	82:6473597d706e	2674
bogdanm	82:6473597d706e	2675
bogdanm	82:6473597d706e	2676	uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2677	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2678	uint32_t CaptureUnit);
bogdanm	82:6473597d706e	2679
bogdanm	82:6473597d706e	2680	void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_,
bogdanm	82:6473597d706e	2681	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2682	uint32_t Output,
bogdanm	82:6473597d706e	2683	HRTIM_OutputCfgTypeDef * pOutputCfg);
bogdanm	82:6473597d706e	2684
bogdanm	82:6473597d706e	2685	void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2686	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2687	uint32_t Output,
bogdanm	82:6473597d706e	2688	uint32_t OutputLevel);
bogdanm	82:6473597d706e	2689
bogdanm	82:6473597d706e	2690	uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2691	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2692	uint32_t Output);
bogdanm	82:6473597d706e	2693
bogdanm	82:6473597d706e	2694	uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * hhrtim,
bogdanm	82:6473597d706e	2695	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2696	uint32_t Output);
bogdanm	82:6473597d706e	2697
bogdanm	82:6473597d706e	2698	uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2699	uint32_t TimerIdx,
bogdanm	82:6473597d706e	2700	uint32_t Output);
bogdanm	82:6473597d706e	2701
bogdanm	82:6473597d706e	2702	uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *hrtim);
bogdanm	82:6473597d706e	2703
bogdanm	82:6473597d706e	2704	uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2705	uint32_t TimerIdx);
bogdanm	82:6473597d706e	2706
bogdanm	82:6473597d706e	2707	uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *hrtim,
bogdanm	82:6473597d706e	2708	uint32_t TimerIdx);
bogdanm	82:6473597d706e	2709	/**
bogdanm	82:6473597d706e	2710	* @}
bogdanm	82:6473597d706e	2711	*/
bogdanm	82:6473597d706e	2712
bogdanm	82:6473597d706e	2713	/**
bogdanm	82:6473597d706e	2714	* @}
bogdanm	82:6473597d706e	2715	*/
bogdanm	82:6473597d706e	2716
bogdanm	82:6473597d706e	2717	#ifdef __cplusplus
bogdanm	82:6473597d706e	2718	}
bogdanm	82:6473597d706e	2719	#endif
bogdanm	82:6473597d706e	2720
bogdanm	82:6473597d706e	2721	#endif /* __STM32F30x_HRTIM_H */
bogdanm	82:6473597d706e	2722
bogdanm	82:6473597d706e	2723	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	25 Jun 2014
Imports:	10
Forks:	0
Commits:	87
Dependents:	1
Dependencies:	0
Followers:	2

TARGET_NUCLEO_F302R8/stm32f30x_hrtim.h@82:6473597d706e, 2014-04-07 (annotated)

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