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version_2.0
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TARGET_NUCLEO_L053R8/stm32l0xx_hal_uart.h@86:4f9a848d74c7, 2014-06-25 (annotated)
- Committer:
- erezi
- Date:
- Wed Jun 25 06:08:49 2014 +0000
- Revision:
- 86:4f9a848d74c7
- Parent:
- 84:0b3ab51c8877
version_2.0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 84:0b3ab51c8877 | 1 | /** |
| bogdanm | 84:0b3ab51c8877 | 2 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 3 | * @file stm32l0xx_hal_uart.h |
| bogdanm | 84:0b3ab51c8877 | 4 | * @author MCD Application Team |
| bogdanm | 84:0b3ab51c8877 | 5 | * @version V1.0.0 |
| bogdanm | 84:0b3ab51c8877 | 6 | * @date 22-April-2014 |
| bogdanm | 84:0b3ab51c8877 | 7 | * @brief Header file of UART HAL module. |
| bogdanm | 84:0b3ab51c8877 | 8 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 9 | * @attention |
| bogdanm | 84:0b3ab51c8877 | 10 | * |
| bogdanm | 84:0b3ab51c8877 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 84:0b3ab51c8877 | 12 | * |
| bogdanm | 84:0b3ab51c8877 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 84:0b3ab51c8877 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 84:0b3ab51c8877 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 84:0b3ab51c8877 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 84:0b3ab51c8877 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 84:0b3ab51c8877 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 84:0b3ab51c8877 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 84:0b3ab51c8877 | 22 | * without specific prior written permission. |
| bogdanm | 84:0b3ab51c8877 | 23 | * |
| bogdanm | 84:0b3ab51c8877 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 84:0b3ab51c8877 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 84:0b3ab51c8877 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 84:0b3ab51c8877 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 84:0b3ab51c8877 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 84:0b3ab51c8877 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 84:0b3ab51c8877 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 84:0b3ab51c8877 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 84:0b3ab51c8877 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 84:0b3ab51c8877 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 84:0b3ab51c8877 | 34 | * |
| bogdanm | 84:0b3ab51c8877 | 35 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 36 | */ |
| bogdanm | 84:0b3ab51c8877 | 37 | |
| bogdanm | 84:0b3ab51c8877 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 39 | #ifndef __STM32L0xx_HAL_UART_H |
| bogdanm | 84:0b3ab51c8877 | 40 | #define __STM32L0xx_HAL_UART_H |
| bogdanm | 84:0b3ab51c8877 | 41 | |
| bogdanm | 84:0b3ab51c8877 | 42 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 43 | extern "C" { |
| bogdanm | 84:0b3ab51c8877 | 44 | #endif |
| bogdanm | 84:0b3ab51c8877 | 45 | |
| bogdanm | 84:0b3ab51c8877 | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 47 | #include "stm32l0xx_hal_def.h" |
| bogdanm | 84:0b3ab51c8877 | 48 | |
| bogdanm | 84:0b3ab51c8877 | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 84:0b3ab51c8877 | 50 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 51 | */ |
| bogdanm | 84:0b3ab51c8877 | 52 | |
| bogdanm | 84:0b3ab51c8877 | 53 | /** @addtogroup UART |
| bogdanm | 84:0b3ab51c8877 | 54 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 55 | */ |
| bogdanm | 84:0b3ab51c8877 | 56 | |
| bogdanm | 84:0b3ab51c8877 | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 58 | |
| bogdanm | 84:0b3ab51c8877 | 59 | /** |
| bogdanm | 84:0b3ab51c8877 | 60 | * @brief UART Init Structure definition |
| bogdanm | 84:0b3ab51c8877 | 61 | */ |
| bogdanm | 84:0b3ab51c8877 | 62 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 63 | { |
| bogdanm | 84:0b3ab51c8877 | 64 | uint32_t BaudRate; /*!< This member configures the UART communication baud rate. |
| bogdanm | 84:0b3ab51c8877 | 65 | The baud rate register is computed using the following formula: |
| bogdanm | 84:0b3ab51c8877 | 66 | - If oversampling is 16 or in LIN mode, |
| bogdanm | 84:0b3ab51c8877 | 67 | Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) |
| bogdanm | 84:0b3ab51c8877 | 68 | - If oversampling is 8, |
| bogdanm | 84:0b3ab51c8877 | 69 | Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] |
| bogdanm | 84:0b3ab51c8877 | 70 | Baud Rate Register[3] = 0 |
| bogdanm | 84:0b3ab51c8877 | 71 | Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */ |
| bogdanm | 84:0b3ab51c8877 | 72 | |
| bogdanm | 84:0b3ab51c8877 | 73 | uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. |
| bogdanm | 84:0b3ab51c8877 | 74 | This parameter can be a value of @ref UART_Word_Length */ |
| bogdanm | 84:0b3ab51c8877 | 75 | |
| bogdanm | 84:0b3ab51c8877 | 76 | uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. |
| bogdanm | 84:0b3ab51c8877 | 77 | This parameter can be a value of @ref UART_Stop_Bits */ |
| bogdanm | 84:0b3ab51c8877 | 78 | |
| bogdanm | 84:0b3ab51c8877 | 79 | uint32_t Parity; /*!< Specifies the parity mode. |
| bogdanm | 84:0b3ab51c8877 | 80 | This parameter can be a value of @ref UART_Parity |
| bogdanm | 84:0b3ab51c8877 | 81 | @note When parity is enabled, the computed parity is inserted |
| bogdanm | 84:0b3ab51c8877 | 82 | at the MSB position of the transmitted data (9th bit when |
| bogdanm | 84:0b3ab51c8877 | 83 | the word length is set to 9 data bits; 8th bit when the |
| bogdanm | 84:0b3ab51c8877 | 84 | word length is set to 8 data bits). */ |
| bogdanm | 84:0b3ab51c8877 | 85 | |
| bogdanm | 84:0b3ab51c8877 | 86 | uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. |
| bogdanm | 84:0b3ab51c8877 | 87 | This parameter can be a value of @ref UART_Mode */ |
| bogdanm | 84:0b3ab51c8877 | 88 | |
| bogdanm | 84:0b3ab51c8877 | 89 | uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled |
| bogdanm | 84:0b3ab51c8877 | 90 | or disabled. |
| bogdanm | 84:0b3ab51c8877 | 91 | This parameter can be a value of @ref UART_Hardware_Flow_Control */ |
| bogdanm | 84:0b3ab51c8877 | 92 | |
| bogdanm | 84:0b3ab51c8877 | 93 | uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). |
| bogdanm | 84:0b3ab51c8877 | 94 | This parameter can be a value of @ref UART_Over_Sampling */ |
| bogdanm | 84:0b3ab51c8877 | 95 | |
| bogdanm | 84:0b3ab51c8877 | 96 | uint32_t OneBitSampling; /*!< Specifies wether a single sample or three samples' majority vote is selected. |
| bogdanm | 84:0b3ab51c8877 | 97 | Selecting the single sample method increases the receiver tolerance to clock |
| bogdanm | 84:0b3ab51c8877 | 98 | deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ |
| bogdanm | 84:0b3ab51c8877 | 99 | }UART_InitTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 100 | |
| bogdanm | 84:0b3ab51c8877 | 101 | /** |
| bogdanm | 84:0b3ab51c8877 | 102 | * @brief UART Advanced Features initalization structure definition |
| bogdanm | 84:0b3ab51c8877 | 103 | */ |
| bogdanm | 84:0b3ab51c8877 | 104 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 105 | { |
| bogdanm | 84:0b3ab51c8877 | 106 | uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several |
| bogdanm | 84:0b3ab51c8877 | 107 | Advanced Features may be initialized at the same time . |
| bogdanm | 84:0b3ab51c8877 | 108 | This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */ |
| bogdanm | 84:0b3ab51c8877 | 109 | |
| bogdanm | 84:0b3ab51c8877 | 110 | uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. |
| bogdanm | 84:0b3ab51c8877 | 111 | This parameter can be a value of @ref UART_Tx_Inv */ |
| bogdanm | 84:0b3ab51c8877 | 112 | |
| bogdanm | 84:0b3ab51c8877 | 113 | uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. |
| bogdanm | 84:0b3ab51c8877 | 114 | This parameter can be a value of @ref UART_Rx_Inv */ |
| bogdanm | 84:0b3ab51c8877 | 115 | |
| bogdanm | 84:0b3ab51c8877 | 116 | uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic |
| bogdanm | 84:0b3ab51c8877 | 117 | vs negative/inverted logic). |
| bogdanm | 84:0b3ab51c8877 | 118 | This parameter can be a value of @ref UART_Data_Inv */ |
| bogdanm | 84:0b3ab51c8877 | 119 | |
| bogdanm | 84:0b3ab51c8877 | 120 | uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. |
| bogdanm | 84:0b3ab51c8877 | 121 | This parameter can be a value of @ref UART_Rx_Tx_Swap */ |
| bogdanm | 84:0b3ab51c8877 | 122 | |
| bogdanm | 84:0b3ab51c8877 | 123 | uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. |
| bogdanm | 84:0b3ab51c8877 | 124 | This parameter can be a value of @ref UART_Overrun_Disable */ |
| bogdanm | 84:0b3ab51c8877 | 125 | |
| bogdanm | 84:0b3ab51c8877 | 126 | uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. |
| bogdanm | 84:0b3ab51c8877 | 127 | This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */ |
| bogdanm | 84:0b3ab51c8877 | 128 | |
| bogdanm | 84:0b3ab51c8877 | 129 | uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. |
| bogdanm | 84:0b3ab51c8877 | 130 | This parameter can be a value of @ref UART_AutoBaudRate_Enable */ |
| bogdanm | 84:0b3ab51c8877 | 131 | |
| bogdanm | 84:0b3ab51c8877 | 132 | uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate |
| bogdanm | 84:0b3ab51c8877 | 133 | detection is carried out. |
| bogdanm | 84:0b3ab51c8877 | 134 | This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */ |
| bogdanm | 84:0b3ab51c8877 | 135 | |
| bogdanm | 84:0b3ab51c8877 | 136 | uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. |
| bogdanm | 84:0b3ab51c8877 | 137 | This parameter can be a value of @ref UART_MSB_First */ |
| bogdanm | 84:0b3ab51c8877 | 138 | } UART_AdvFeatureInitTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 139 | |
| bogdanm | 84:0b3ab51c8877 | 140 | /** |
| bogdanm | 84:0b3ab51c8877 | 141 | * @brief HAL UART State structures definition |
| bogdanm | 84:0b3ab51c8877 | 142 | */ |
| bogdanm | 84:0b3ab51c8877 | 143 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 144 | { |
| bogdanm | 84:0b3ab51c8877 | 145 | HAL_UART_STATE_RESET = 0x00, /*!< Peripheral Reset state */ |
| bogdanm | 84:0b3ab51c8877 | 146 | HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
| bogdanm | 84:0b3ab51c8877 | 147 | HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 148 | HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 149 | HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 150 | HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 151 | HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| bogdanm | 84:0b3ab51c8877 | 152 | HAL_UART_STATE_ERROR = 0x04 /*!< Error */ |
| bogdanm | 84:0b3ab51c8877 | 153 | }HAL_UART_StateTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 154 | |
| bogdanm | 84:0b3ab51c8877 | 155 | /** |
| bogdanm | 84:0b3ab51c8877 | 156 | * @brief HAL UART Error Code structure definition |
| bogdanm | 84:0b3ab51c8877 | 157 | */ |
| bogdanm | 84:0b3ab51c8877 | 158 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 159 | { |
| bogdanm | 84:0b3ab51c8877 | 160 | HAL_UART_ERROR_NONE = 0x00, /*!< No error */ |
| bogdanm | 84:0b3ab51c8877 | 161 | HAL_UART_ERROR_PE = 0x01, /*!< Parity error */ |
| bogdanm | 84:0b3ab51c8877 | 162 | HAL_UART_ERROR_NE = 0x02, /*!< Noise error */ |
| bogdanm | 84:0b3ab51c8877 | 163 | HAL_UART_ERROR_FE = 0x04, /*!< frame error */ |
| bogdanm | 84:0b3ab51c8877 | 164 | HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */ |
| bogdanm | 84:0b3ab51c8877 | 165 | HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */ |
| bogdanm | 84:0b3ab51c8877 | 166 | }HAL_UART_ErrorTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 167 | |
| bogdanm | 84:0b3ab51c8877 | 168 | /** |
| bogdanm | 84:0b3ab51c8877 | 169 | * @brief UART clock sources definition |
| bogdanm | 84:0b3ab51c8877 | 170 | */ |
| bogdanm | 84:0b3ab51c8877 | 171 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 172 | { |
| bogdanm | 84:0b3ab51c8877 | 173 | UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ |
| bogdanm | 84:0b3ab51c8877 | 174 | UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ |
| bogdanm | 84:0b3ab51c8877 | 175 | UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ |
| bogdanm | 84:0b3ab51c8877 | 176 | UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ |
| bogdanm | 84:0b3ab51c8877 | 177 | UART_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */ |
| bogdanm | 84:0b3ab51c8877 | 178 | }UART_ClockSourceTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 179 | |
| bogdanm | 84:0b3ab51c8877 | 180 | /** |
| bogdanm | 84:0b3ab51c8877 | 181 | * @brief UART handle Structure definition |
| bogdanm | 84:0b3ab51c8877 | 182 | */ |
| bogdanm | 84:0b3ab51c8877 | 183 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 184 | { |
| bogdanm | 84:0b3ab51c8877 | 185 | USART_TypeDef *Instance; /* UART registers base address */ |
| bogdanm | 84:0b3ab51c8877 | 186 | |
| bogdanm | 84:0b3ab51c8877 | 187 | UART_InitTypeDef Init; /* UART communication parameters */ |
| bogdanm | 84:0b3ab51c8877 | 188 | |
| bogdanm | 84:0b3ab51c8877 | 189 | UART_AdvFeatureInitTypeDef AdvancedInit; /* UART Advanced Features initialization parameters */ |
| bogdanm | 84:0b3ab51c8877 | 190 | |
| bogdanm | 84:0b3ab51c8877 | 191 | uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */ |
| bogdanm | 84:0b3ab51c8877 | 192 | |
| bogdanm | 84:0b3ab51c8877 | 193 | uint16_t TxXferSize; /* UART Tx Transfer size */ |
| bogdanm | 84:0b3ab51c8877 | 194 | |
| bogdanm | 84:0b3ab51c8877 | 195 | uint16_t TxXferCount; /* UART Tx Transfer Counter */ |
| bogdanm | 84:0b3ab51c8877 | 196 | |
| bogdanm | 84:0b3ab51c8877 | 197 | uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */ |
| bogdanm | 84:0b3ab51c8877 | 198 | |
| bogdanm | 84:0b3ab51c8877 | 199 | uint16_t RxXferSize; /* UART Rx Transfer size */ |
| bogdanm | 84:0b3ab51c8877 | 200 | |
| bogdanm | 84:0b3ab51c8877 | 201 | uint16_t RxXferCount; /* UART Rx Transfer Counter */ |
| bogdanm | 84:0b3ab51c8877 | 202 | |
| bogdanm | 84:0b3ab51c8877 | 203 | uint16_t Mask; /* UART Rx RDR register mask */ |
| bogdanm | 84:0b3ab51c8877 | 204 | |
| bogdanm | 84:0b3ab51c8877 | 205 | DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */ |
| bogdanm | 84:0b3ab51c8877 | 206 | |
| bogdanm | 84:0b3ab51c8877 | 207 | DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */ |
| bogdanm | 84:0b3ab51c8877 | 208 | |
| bogdanm | 84:0b3ab51c8877 | 209 | HAL_LockTypeDef Lock; /* Locking object */ |
| bogdanm | 84:0b3ab51c8877 | 210 | |
| bogdanm | 84:0b3ab51c8877 | 211 | __IO HAL_UART_StateTypeDef State; /* UART communication state */ |
| bogdanm | 84:0b3ab51c8877 | 212 | |
| bogdanm | 84:0b3ab51c8877 | 213 | __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */ |
| bogdanm | 84:0b3ab51c8877 | 214 | |
| bogdanm | 84:0b3ab51c8877 | 215 | }UART_HandleTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 216 | |
| bogdanm | 84:0b3ab51c8877 | 217 | |
| bogdanm | 84:0b3ab51c8877 | 218 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 219 | /** @defgroup UART_Exported_Constants |
| bogdanm | 84:0b3ab51c8877 | 220 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 221 | */ |
| bogdanm | 84:0b3ab51c8877 | 222 | |
| bogdanm | 84:0b3ab51c8877 | 223 | /** @defgroup UART_Stop_Bits UART Number of Stop Bits |
| bogdanm | 84:0b3ab51c8877 | 224 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 225 | */ |
| bogdanm | 84:0b3ab51c8877 | 226 | #define UART_STOPBITS_1 ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 227 | #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) |
| bogdanm | 84:0b3ab51c8877 | 228 | #define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ |
| bogdanm | 84:0b3ab51c8877 | 229 | ((STOPBITS) == UART_STOPBITS_2)) |
| bogdanm | 84:0b3ab51c8877 | 230 | /** |
| bogdanm | 84:0b3ab51c8877 | 231 | * @} |
| bogdanm | 84:0b3ab51c8877 | 232 | */ |
| bogdanm | 84:0b3ab51c8877 | 233 | |
| bogdanm | 84:0b3ab51c8877 | 234 | /** @defgroup UART_Parity UART Parity |
| bogdanm | 84:0b3ab51c8877 | 235 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 236 | */ |
| bogdanm | 84:0b3ab51c8877 | 237 | #define UART_PARITY_NONE ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 238 | #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) |
| bogdanm | 84:0b3ab51c8877 | 239 | #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) |
| bogdanm | 84:0b3ab51c8877 | 240 | #define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ |
| bogdanm | 84:0b3ab51c8877 | 241 | ((PARITY) == UART_PARITY_EVEN) || \ |
| bogdanm | 84:0b3ab51c8877 | 242 | ((PARITY) == UART_PARITY_ODD)) |
| bogdanm | 84:0b3ab51c8877 | 243 | /** |
| bogdanm | 84:0b3ab51c8877 | 244 | * @} |
| bogdanm | 84:0b3ab51c8877 | 245 | */ |
| bogdanm | 84:0b3ab51c8877 | 246 | |
| bogdanm | 84:0b3ab51c8877 | 247 | /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control |
| bogdanm | 84:0b3ab51c8877 | 248 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 249 | */ |
| bogdanm | 84:0b3ab51c8877 | 250 | #define UART_HWCONTROL_NONE ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 251 | #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) |
| bogdanm | 84:0b3ab51c8877 | 252 | #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) |
| bogdanm | 84:0b3ab51c8877 | 253 | #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) |
| bogdanm | 84:0b3ab51c8877 | 254 | #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ |
| bogdanm | 84:0b3ab51c8877 | 255 | (((CONTROL) == UART_HWCONTROL_NONE) || \ |
| bogdanm | 84:0b3ab51c8877 | 256 | ((CONTROL) == UART_HWCONTROL_RTS) || \ |
| bogdanm | 84:0b3ab51c8877 | 257 | ((CONTROL) == UART_HWCONTROL_CTS) || \ |
| bogdanm | 84:0b3ab51c8877 | 258 | ((CONTROL) == UART_HWCONTROL_RTS_CTS)) |
| bogdanm | 84:0b3ab51c8877 | 259 | /** |
| bogdanm | 84:0b3ab51c8877 | 260 | * @} |
| bogdanm | 84:0b3ab51c8877 | 261 | */ |
| bogdanm | 84:0b3ab51c8877 | 262 | |
| bogdanm | 84:0b3ab51c8877 | 263 | /** @defgroup UART_Mode UART Transfer Mode |
| bogdanm | 84:0b3ab51c8877 | 264 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 265 | */ |
| bogdanm | 84:0b3ab51c8877 | 266 | #define UART_MODE_RX ((uint32_t)USART_CR1_RE) |
| bogdanm | 84:0b3ab51c8877 | 267 | #define UART_MODE_TX ((uint32_t)USART_CR1_TE) |
| bogdanm | 84:0b3ab51c8877 | 268 | #define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) |
| bogdanm | 84:0b3ab51c8877 | 269 | #define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00)) |
| bogdanm | 84:0b3ab51c8877 | 270 | /** |
| bogdanm | 84:0b3ab51c8877 | 271 | * @} |
| bogdanm | 84:0b3ab51c8877 | 272 | */ |
| bogdanm | 84:0b3ab51c8877 | 273 | |
| bogdanm | 84:0b3ab51c8877 | 274 | /** @defgroup UART_State UART State |
| bogdanm | 84:0b3ab51c8877 | 275 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 276 | */ |
| bogdanm | 84:0b3ab51c8877 | 277 | #define UART_STATE_DISABLE ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 278 | #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) |
| bogdanm | 84:0b3ab51c8877 | 279 | #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 280 | ((STATE) == UART_STATE_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 281 | /** |
| bogdanm | 84:0b3ab51c8877 | 282 | * @} |
| bogdanm | 84:0b3ab51c8877 | 283 | */ |
| bogdanm | 84:0b3ab51c8877 | 284 | |
| bogdanm | 84:0b3ab51c8877 | 285 | /** @defgroup UART_Over_Sampling UART Over Sampling |
| bogdanm | 84:0b3ab51c8877 | 286 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 287 | */ |
| bogdanm | 84:0b3ab51c8877 | 288 | #define UART_OVERSAMPLING_16 ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 289 | #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) |
| bogdanm | 84:0b3ab51c8877 | 290 | #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ |
| bogdanm | 84:0b3ab51c8877 | 291 | ((SAMPLING) == UART_OVERSAMPLING_8)) |
| bogdanm | 84:0b3ab51c8877 | 292 | /** |
| bogdanm | 84:0b3ab51c8877 | 293 | * @} |
| bogdanm | 84:0b3ab51c8877 | 294 | */ |
| bogdanm | 84:0b3ab51c8877 | 295 | |
| bogdanm | 84:0b3ab51c8877 | 296 | /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method |
| bogdanm | 84:0b3ab51c8877 | 297 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 298 | */ |
| bogdanm | 84:0b3ab51c8877 | 299 | #define UART_ONEBIT_SAMPLING_DISABLED ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 300 | #define UART_ONEBIT_SAMPLING_ENABLED ((uint32_t)USART_CR3_ONEBIT) |
| bogdanm | 84:0b3ab51c8877 | 301 | #define IS_UART_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == UART_ONEBIT_SAMPLING_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 302 | ((ONEBIT) == UART_ONEBIT_SAMPLING_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 303 | /** |
| bogdanm | 84:0b3ab51c8877 | 304 | * @} |
| bogdanm | 84:0b3ab51c8877 | 305 | */ |
| bogdanm | 84:0b3ab51c8877 | 306 | |
| bogdanm | 84:0b3ab51c8877 | 307 | |
| bogdanm | 84:0b3ab51c8877 | 308 | /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut |
| bogdanm | 84:0b3ab51c8877 | 309 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 310 | */ |
| bogdanm | 84:0b3ab51c8877 | 311 | #define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 312 | #define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) |
| bogdanm | 84:0b3ab51c8877 | 313 | #define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 314 | ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 315 | /** |
| bogdanm | 84:0b3ab51c8877 | 316 | * @} |
| bogdanm | 84:0b3ab51c8877 | 317 | */ |
| bogdanm | 84:0b3ab51c8877 | 318 | |
| bogdanm | 84:0b3ab51c8877 | 319 | /** @defgroup UART_LIN UART Local Interconnection Network mode |
| bogdanm | 84:0b3ab51c8877 | 320 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 321 | */ |
| bogdanm | 84:0b3ab51c8877 | 322 | #define UART_LIN_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 323 | #define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) |
| bogdanm | 84:0b3ab51c8877 | 324 | #define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 325 | ((LIN) == UART_LIN_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 326 | /** |
| bogdanm | 84:0b3ab51c8877 | 327 | * @} |
| bogdanm | 84:0b3ab51c8877 | 328 | */ |
| bogdanm | 84:0b3ab51c8877 | 329 | |
| bogdanm | 84:0b3ab51c8877 | 330 | /** @defgroup UART_LIN_Break_Detection UART LIN Break Detection |
| bogdanm | 84:0b3ab51c8877 | 331 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 332 | */ |
| bogdanm | 84:0b3ab51c8877 | 333 | #define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 334 | #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) |
| bogdanm | 84:0b3ab51c8877 | 335 | #define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ |
| bogdanm | 84:0b3ab51c8877 | 336 | ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) |
| bogdanm | 84:0b3ab51c8877 | 337 | /** |
| bogdanm | 84:0b3ab51c8877 | 338 | * @} |
| bogdanm | 84:0b3ab51c8877 | 339 | */ |
| bogdanm | 84:0b3ab51c8877 | 340 | |
| bogdanm | 84:0b3ab51c8877 | 341 | |
| bogdanm | 84:0b3ab51c8877 | 342 | |
| bogdanm | 84:0b3ab51c8877 | 343 | /** @defgroup UART_One_Bit UART One Bit sampling |
| bogdanm | 84:0b3ab51c8877 | 344 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 345 | */ |
| bogdanm | 84:0b3ab51c8877 | 346 | #define UART_ONE_BIT_SAMPLE_DISABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 347 | #define UART_ONE_BIT_SAMPLE_ENABLED ((uint32_t)USART_CR3_ONEBIT) |
| bogdanm | 84:0b3ab51c8877 | 348 | #define IS_UART_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 349 | ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 350 | /** |
| bogdanm | 84:0b3ab51c8877 | 351 | * @} |
| bogdanm | 84:0b3ab51c8877 | 352 | */ |
| bogdanm | 84:0b3ab51c8877 | 353 | |
| bogdanm | 84:0b3ab51c8877 | 354 | /** @defgroup UART_DMA_Tx UART DMA Tx |
| bogdanm | 84:0b3ab51c8877 | 355 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 356 | */ |
| bogdanm | 84:0b3ab51c8877 | 357 | #define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 358 | #define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) |
| bogdanm | 84:0b3ab51c8877 | 359 | #define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 360 | ((DMATX) == UART_DMA_TX_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 361 | /** |
| bogdanm | 84:0b3ab51c8877 | 362 | * @} |
| bogdanm | 84:0b3ab51c8877 | 363 | */ |
| bogdanm | 84:0b3ab51c8877 | 364 | |
| bogdanm | 84:0b3ab51c8877 | 365 | /** @defgroup UART_DMA_Rx UART DMA Rx |
| bogdanm | 84:0b3ab51c8877 | 366 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 367 | */ |
| bogdanm | 84:0b3ab51c8877 | 368 | #define UART_DMA_RX_DISABLE ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 369 | #define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) |
| bogdanm | 84:0b3ab51c8877 | 370 | #define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 371 | ((DMARX) == UART_DMA_RX_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 372 | /** |
| bogdanm | 84:0b3ab51c8877 | 373 | * @} |
| bogdanm | 84:0b3ab51c8877 | 374 | */ |
| bogdanm | 84:0b3ab51c8877 | 375 | |
| bogdanm | 84:0b3ab51c8877 | 376 | /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection |
| bogdanm | 84:0b3ab51c8877 | 377 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 378 | */ |
| bogdanm | 84:0b3ab51c8877 | 379 | #define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 380 | #define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) |
| bogdanm | 84:0b3ab51c8877 | 381 | #define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 382 | ((HDSEL) == UART_HALF_DUPLEX_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 383 | /** |
| bogdanm | 84:0b3ab51c8877 | 384 | * @} |
| bogdanm | 84:0b3ab51c8877 | 385 | */ |
| bogdanm | 84:0b3ab51c8877 | 386 | |
| bogdanm | 84:0b3ab51c8877 | 387 | /** @defgroup UART_Flags UART Status Flags |
| bogdanm | 84:0b3ab51c8877 | 388 | * Elements values convention: 0xXXXX |
| bogdanm | 84:0b3ab51c8877 | 389 | * - 0xXXXX : Flag mask in the ISR register |
| bogdanm | 84:0b3ab51c8877 | 390 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 391 | */ |
| bogdanm | 84:0b3ab51c8877 | 392 | #define UART_FLAG_REACK ((uint32_t)0x00400000) |
| bogdanm | 84:0b3ab51c8877 | 393 | #define UART_FLAG_TEACK ((uint32_t)0x00200000) |
| bogdanm | 84:0b3ab51c8877 | 394 | #define UART_FLAG_WUF ((uint32_t)0x00100000) |
| bogdanm | 84:0b3ab51c8877 | 395 | #define UART_FLAG_RWU ((uint32_t)0x00080000) |
| bogdanm | 84:0b3ab51c8877 | 396 | #define UART_FLAG_SBKF ((uint32_t)0x00040000 |
| bogdanm | 84:0b3ab51c8877 | 397 | #define UART_FLAG_CMF ((uint32_t)0x00020000) |
| bogdanm | 84:0b3ab51c8877 | 398 | #define UART_FLAG_BUSY ((uint32_t)0x00010000) |
| bogdanm | 84:0b3ab51c8877 | 399 | #define UART_FLAG_ABRF ((uint32_t)0x00008000) |
| bogdanm | 84:0b3ab51c8877 | 400 | #define UART_FLAG_ABRE ((uint32_t)0x00004000) |
| bogdanm | 84:0b3ab51c8877 | 401 | #define UART_FLAG_EOBF ((uint32_t)0x00001000) |
| bogdanm | 84:0b3ab51c8877 | 402 | #define UART_FLAG_RTOF ((uint32_t)0x00000800) |
| bogdanm | 84:0b3ab51c8877 | 403 | #define UART_FLAG_CTS ((uint32_t)0x00000400) |
| bogdanm | 84:0b3ab51c8877 | 404 | #define UART_FLAG_CTSIF ((uint32_t)0x00000200) |
| bogdanm | 84:0b3ab51c8877 | 405 | #define UART_FLAG_LBDF ((uint32_t)0x00000100) |
| bogdanm | 84:0b3ab51c8877 | 406 | #define UART_FLAG_TXE ((uint32_t)0x00000080) |
| bogdanm | 84:0b3ab51c8877 | 407 | #define UART_FLAG_TC ((uint32_t)0x00000040) |
| bogdanm | 84:0b3ab51c8877 | 408 | #define UART_FLAG_RXNE ((uint32_t)0x00000020) |
| bogdanm | 84:0b3ab51c8877 | 409 | #define UART_FLAG_IDLE ((uint32_t)0x00000010) |
| bogdanm | 84:0b3ab51c8877 | 410 | #define UART_FLAG_ORE ((uint32_t)0x00000008) |
| bogdanm | 84:0b3ab51c8877 | 411 | #define UART_FLAG_NE ((uint32_t)0x00000004) |
| bogdanm | 84:0b3ab51c8877 | 412 | #define UART_FLAG_FE ((uint32_t)0x00000002) |
| bogdanm | 84:0b3ab51c8877 | 413 | #define UART_FLAG_PE ((uint32_t)0x00000001) |
| bogdanm | 84:0b3ab51c8877 | 414 | /** |
| bogdanm | 84:0b3ab51c8877 | 415 | * @} |
| bogdanm | 84:0b3ab51c8877 | 416 | */ |
| bogdanm | 84:0b3ab51c8877 | 417 | |
| bogdanm | 84:0b3ab51c8877 | 418 | /** @defgroup UART_Interrupt_definition UART Interrupts Definition |
| bogdanm | 84:0b3ab51c8877 | 419 | * Elements values convention: 0000ZZZZ0XXYYYYYb |
| bogdanm | 84:0b3ab51c8877 | 420 | * - YYYYY : Interrupt source position in the XX register (5bits) |
| bogdanm | 84:0b3ab51c8877 | 421 | * - XX : Interrupt source register (2bits) |
| bogdanm | 84:0b3ab51c8877 | 422 | * - 01: CR1 register |
| bogdanm | 84:0b3ab51c8877 | 423 | * - 10: CR2 register |
| bogdanm | 84:0b3ab51c8877 | 424 | * - 11: CR3 register |
| bogdanm | 84:0b3ab51c8877 | 425 | * - ZZZZ : Flag position in the ISR register(4bits) |
| bogdanm | 84:0b3ab51c8877 | 426 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 427 | */ |
| bogdanm | 84:0b3ab51c8877 | 428 | #define UART_IT_PE ((uint32_t)0x0028) |
| bogdanm | 84:0b3ab51c8877 | 429 | #define UART_IT_TXE ((uint32_t)0x0727) |
| bogdanm | 84:0b3ab51c8877 | 430 | #define UART_IT_TC ((uint32_t)0x0626) |
| bogdanm | 84:0b3ab51c8877 | 431 | #define UART_IT_RXNE ((uint32_t)0x0525) |
| bogdanm | 84:0b3ab51c8877 | 432 | #define UART_IT_IDLE ((uint32_t)0x0424) |
| bogdanm | 84:0b3ab51c8877 | 433 | #define UART_IT_LBD ((uint32_t)0x0846) |
| bogdanm | 84:0b3ab51c8877 | 434 | #define UART_IT_CTS ((uint32_t)0x096A) |
| bogdanm | 84:0b3ab51c8877 | 435 | #define UART_IT_CM ((uint32_t)0x142E) |
| bogdanm | 84:0b3ab51c8877 | 436 | #define UART_IT_WUF ((uint32_t)0x1476) |
| bogdanm | 84:0b3ab51c8877 | 437 | |
| bogdanm | 84:0b3ab51c8877 | 438 | /** Elements values convention: 000000000XXYYYYYb |
| bogdanm | 84:0b3ab51c8877 | 439 | * - YYYYY : Interrupt source position in the XX register (5bits) |
| bogdanm | 84:0b3ab51c8877 | 440 | * - XX : Interrupt source register (2bits) |
| bogdanm | 84:0b3ab51c8877 | 441 | * - 01: CR1 register |
| bogdanm | 84:0b3ab51c8877 | 442 | * - 10: CR2 register |
| bogdanm | 84:0b3ab51c8877 | 443 | * - 11: CR3 register |
| bogdanm | 84:0b3ab51c8877 | 444 | */ |
| bogdanm | 84:0b3ab51c8877 | 445 | #define UART_IT_ERR ((uint32_t)0x0060) |
| bogdanm | 84:0b3ab51c8877 | 446 | |
| bogdanm | 84:0b3ab51c8877 | 447 | /** Elements values convention: 0000ZZZZ00000000b |
| bogdanm | 84:0b3ab51c8877 | 448 | * - ZZZZ : Flag position in the ISR register(4bits) |
| bogdanm | 84:0b3ab51c8877 | 449 | */ |
| bogdanm | 84:0b3ab51c8877 | 450 | #define UART_IT_ORE ((uint32_t)0x0300) |
| bogdanm | 84:0b3ab51c8877 | 451 | #define UART_IT_NE ((uint32_t)0x0200) |
| bogdanm | 84:0b3ab51c8877 | 452 | #define UART_IT_FE ((uint32_t)0x0100) |
| bogdanm | 84:0b3ab51c8877 | 453 | /** |
| bogdanm | 84:0b3ab51c8877 | 454 | * @} |
| bogdanm | 84:0b3ab51c8877 | 455 | */ |
| bogdanm | 84:0b3ab51c8877 | 456 | |
| bogdanm | 84:0b3ab51c8877 | 457 | /** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags |
| bogdanm | 84:0b3ab51c8877 | 458 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 459 | */ |
| bogdanm | 84:0b3ab51c8877 | 460 | #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 461 | #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 462 | #define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 463 | #define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 464 | #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 465 | #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 466 | #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 467 | #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 468 | #define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 469 | #define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 470 | #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 471 | #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ |
| bogdanm | 84:0b3ab51c8877 | 472 | /** |
| bogdanm | 84:0b3ab51c8877 | 473 | * @} |
| bogdanm | 84:0b3ab51c8877 | 474 | */ |
| bogdanm | 84:0b3ab51c8877 | 475 | |
| bogdanm | 84:0b3ab51c8877 | 476 | /** @defgroup UART_Request_Parameters UART Request Parameters |
| bogdanm | 84:0b3ab51c8877 | 477 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 478 | */ |
| bogdanm | 84:0b3ab51c8877 | 479 | #define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ |
| bogdanm | 84:0b3ab51c8877 | 480 | #define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ |
| bogdanm | 84:0b3ab51c8877 | 481 | #define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ |
| bogdanm | 84:0b3ab51c8877 | 482 | #define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ |
| bogdanm | 84:0b3ab51c8877 | 483 | #define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ |
| bogdanm | 84:0b3ab51c8877 | 484 | #define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \ |
| bogdanm | 84:0b3ab51c8877 | 485 | ((PARAM) == UART_SENDBREAK_REQUEST) || \ |
| bogdanm | 84:0b3ab51c8877 | 486 | ((PARAM) == UART_MUTE_MODE_REQUEST) || \ |
| bogdanm | 84:0b3ab51c8877 | 487 | ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \ |
| bogdanm | 84:0b3ab51c8877 | 488 | ((PARAM) == UART_TXDATA_FLUSH_REQUEST)) |
| bogdanm | 84:0b3ab51c8877 | 489 | /** |
| bogdanm | 84:0b3ab51c8877 | 490 | * @} |
| bogdanm | 84:0b3ab51c8877 | 491 | */ |
| bogdanm | 84:0b3ab51c8877 | 492 | |
| bogdanm | 84:0b3ab51c8877 | 493 | /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type |
| bogdanm | 84:0b3ab51c8877 | 494 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 495 | */ |
| bogdanm | 84:0b3ab51c8877 | 496 | #define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 497 | #define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) |
| bogdanm | 84:0b3ab51c8877 | 498 | #define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) |
| bogdanm | 84:0b3ab51c8877 | 499 | #define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) |
| bogdanm | 84:0b3ab51c8877 | 500 | #define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) |
| bogdanm | 84:0b3ab51c8877 | 501 | #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) |
| bogdanm | 84:0b3ab51c8877 | 502 | #define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) |
| bogdanm | 84:0b3ab51c8877 | 503 | #define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) |
| bogdanm | 84:0b3ab51c8877 | 504 | #define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) |
| bogdanm | 84:0b3ab51c8877 | 505 | #define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \ |
| bogdanm | 84:0b3ab51c8877 | 506 | UART_ADVFEATURE_TXINVERT_INIT | \ |
| bogdanm | 84:0b3ab51c8877 | 507 | UART_ADVFEATURE_RXINVERT_INIT | \ |
| bogdanm | 84:0b3ab51c8877 | 508 | UART_ADVFEATURE_DATAINVERT_INIT | \ |
| bogdanm | 84:0b3ab51c8877 | 509 | UART_ADVFEATURE_SWAP_INIT | \ |
| bogdanm | 84:0b3ab51c8877 | 510 | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ |
| bogdanm | 84:0b3ab51c8877 | 511 | UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ |
| bogdanm | 84:0b3ab51c8877 | 512 | UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ |
| bogdanm | 84:0b3ab51c8877 | 513 | UART_ADVFEATURE_MSBFIRST_INIT)) |
| bogdanm | 84:0b3ab51c8877 | 514 | /** |
| bogdanm | 84:0b3ab51c8877 | 515 | * @} |
| bogdanm | 84:0b3ab51c8877 | 516 | */ |
| bogdanm | 84:0b3ab51c8877 | 517 | |
| bogdanm | 84:0b3ab51c8877 | 518 | /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion |
| bogdanm | 84:0b3ab51c8877 | 519 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 520 | */ |
| bogdanm | 84:0b3ab51c8877 | 521 | #define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 522 | #define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) |
| bogdanm | 84:0b3ab51c8877 | 523 | #define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 524 | ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 525 | /** |
| bogdanm | 84:0b3ab51c8877 | 526 | * @} |
| bogdanm | 84:0b3ab51c8877 | 527 | */ |
| bogdanm | 84:0b3ab51c8877 | 528 | |
| bogdanm | 84:0b3ab51c8877 | 529 | /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion |
| bogdanm | 84:0b3ab51c8877 | 530 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 531 | */ |
| bogdanm | 84:0b3ab51c8877 | 532 | #define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 533 | #define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) |
| bogdanm | 84:0b3ab51c8877 | 534 | #define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 535 | ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 536 | /** |
| bogdanm | 84:0b3ab51c8877 | 537 | * @} |
| bogdanm | 84:0b3ab51c8877 | 538 | */ |
| bogdanm | 84:0b3ab51c8877 | 539 | |
| bogdanm | 84:0b3ab51c8877 | 540 | /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion |
| bogdanm | 84:0b3ab51c8877 | 541 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 542 | */ |
| bogdanm | 84:0b3ab51c8877 | 543 | #define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 544 | #define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) |
| bogdanm | 84:0b3ab51c8877 | 545 | #define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 546 | ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 547 | /** |
| bogdanm | 84:0b3ab51c8877 | 548 | * @} |
| bogdanm | 84:0b3ab51c8877 | 549 | */ |
| bogdanm | 84:0b3ab51c8877 | 550 | |
| bogdanm | 84:0b3ab51c8877 | 551 | /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap |
| bogdanm | 84:0b3ab51c8877 | 552 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 553 | */ |
| bogdanm | 84:0b3ab51c8877 | 554 | #define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 555 | #define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) |
| bogdanm | 84:0b3ab51c8877 | 556 | #define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 557 | ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 558 | /** |
| bogdanm | 84:0b3ab51c8877 | 559 | * @} |
| bogdanm | 84:0b3ab51c8877 | 560 | */ |
| bogdanm | 84:0b3ab51c8877 | 561 | |
| bogdanm | 84:0b3ab51c8877 | 562 | /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable |
| bogdanm | 84:0b3ab51c8877 | 563 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 564 | */ |
| bogdanm | 84:0b3ab51c8877 | 565 | #define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 566 | #define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) |
| bogdanm | 84:0b3ab51c8877 | 567 | #define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 568 | ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE)) |
| bogdanm | 84:0b3ab51c8877 | 569 | /** |
| bogdanm | 84:0b3ab51c8877 | 570 | * @} |
| bogdanm | 84:0b3ab51c8877 | 571 | */ |
| bogdanm | 84:0b3ab51c8877 | 572 | |
| bogdanm | 84:0b3ab51c8877 | 573 | /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable |
| bogdanm | 84:0b3ab51c8877 | 574 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 575 | */ |
| bogdanm | 84:0b3ab51c8877 | 576 | #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 577 | #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) |
| bogdanm | 84:0b3ab51c8877 | 578 | #define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 579 | ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 580 | /** |
| bogdanm | 84:0b3ab51c8877 | 581 | * @} |
| bogdanm | 84:0b3ab51c8877 | 582 | */ |
| bogdanm | 84:0b3ab51c8877 | 583 | |
| bogdanm | 84:0b3ab51c8877 | 584 | /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error |
| bogdanm | 84:0b3ab51c8877 | 585 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 586 | */ |
| bogdanm | 84:0b3ab51c8877 | 587 | #define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 588 | #define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) |
| bogdanm | 84:0b3ab51c8877 | 589 | #define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ |
| bogdanm | 84:0b3ab51c8877 | 590 | ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) |
| bogdanm | 84:0b3ab51c8877 | 591 | /** |
| bogdanm | 84:0b3ab51c8877 | 592 | * @} |
| bogdanm | 84:0b3ab51c8877 | 593 | */ |
| bogdanm | 84:0b3ab51c8877 | 594 | |
| bogdanm | 84:0b3ab51c8877 | 595 | /** @defgroup UART_MSB_First UART Advanced Feature MSB First |
| bogdanm | 84:0b3ab51c8877 | 596 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 597 | */ |
| bogdanm | 84:0b3ab51c8877 | 598 | #define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 599 | #define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) |
| bogdanm | 84:0b3ab51c8877 | 600 | #define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 601 | ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 602 | /** |
| bogdanm | 84:0b3ab51c8877 | 603 | * @} |
| bogdanm | 84:0b3ab51c8877 | 604 | */ |
| bogdanm | 84:0b3ab51c8877 | 605 | |
| bogdanm | 84:0b3ab51c8877 | 606 | /** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable |
| bogdanm | 84:0b3ab51c8877 | 607 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 608 | */ |
| bogdanm | 84:0b3ab51c8877 | 609 | #define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 610 | #define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) |
| bogdanm | 84:0b3ab51c8877 | 611 | #define IS_UART_ADVFEATURE_STOPMODE(STOPMODE) (((STOPMODE) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 612 | ((STOPMODE) == UART_ADVFEATURE_STOPMODE_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 613 | /** |
| bogdanm | 84:0b3ab51c8877 | 614 | * @} |
| bogdanm | 84:0b3ab51c8877 | 615 | */ |
| bogdanm | 84:0b3ab51c8877 | 616 | |
| bogdanm | 84:0b3ab51c8877 | 617 | /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable |
| bogdanm | 84:0b3ab51c8877 | 618 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 619 | */ |
| bogdanm | 84:0b3ab51c8877 | 620 | #define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 621 | #define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) |
| bogdanm | 84:0b3ab51c8877 | 622 | #define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 623 | ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE)) |
| bogdanm | 84:0b3ab51c8877 | 624 | /** |
| bogdanm | 84:0b3ab51c8877 | 625 | * @} |
| bogdanm | 84:0b3ab51c8877 | 626 | */ |
| bogdanm | 84:0b3ab51c8877 | 627 | |
| bogdanm | 84:0b3ab51c8877 | 628 | /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register |
| bogdanm | 84:0b3ab51c8877 | 629 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 630 | */ |
| bogdanm | 84:0b3ab51c8877 | 631 | #define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) |
| bogdanm | 84:0b3ab51c8877 | 632 | /** |
| bogdanm | 84:0b3ab51c8877 | 633 | * @} |
| bogdanm | 84:0b3ab51c8877 | 634 | */ |
| bogdanm | 84:0b3ab51c8877 | 635 | |
| bogdanm | 84:0b3ab51c8877 | 636 | /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection |
| bogdanm | 84:0b3ab51c8877 | 637 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 638 | */ |
| bogdanm | 84:0b3ab51c8877 | 639 | #define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000) |
| bogdanm | 84:0b3ab51c8877 | 640 | #define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) |
| bogdanm | 84:0b3ab51c8877 | 641 | #define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) |
| bogdanm | 84:0b3ab51c8877 | 642 | #define IS_UART_WAKEUP_SELECTION(WAKE) (((WAKE) == UART_WAKEUP_ON_ADDRESS) || \ |
| bogdanm | 84:0b3ab51c8877 | 643 | ((WAKE) == UART_WAKEUP_ON_STARTBIT) || \ |
| bogdanm | 84:0b3ab51c8877 | 644 | ((WAKE) == UART_WAKEUP_ON_READDATA_NONEMPTY)) |
| bogdanm | 84:0b3ab51c8877 | 645 | /** |
| bogdanm | 84:0b3ab51c8877 | 646 | * @} |
| bogdanm | 84:0b3ab51c8877 | 647 | */ |
| bogdanm | 84:0b3ab51c8877 | 648 | |
| bogdanm | 84:0b3ab51c8877 | 649 | /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity |
| bogdanm | 84:0b3ab51c8877 | 650 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 651 | */ |
| bogdanm | 84:0b3ab51c8877 | 652 | #define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 653 | #define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) |
| bogdanm | 84:0b3ab51c8877 | 654 | #define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \ |
| bogdanm | 84:0b3ab51c8877 | 655 | ((POLARITY) == UART_DE_POLARITY_LOW)) |
| bogdanm | 84:0b3ab51c8877 | 656 | /** |
| bogdanm | 84:0b3ab51c8877 | 657 | * @} |
| bogdanm | 84:0b3ab51c8877 | 658 | */ |
| bogdanm | 84:0b3ab51c8877 | 659 | |
| bogdanm | 84:0b3ab51c8877 | 660 | /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register |
| bogdanm | 84:0b3ab51c8877 | 661 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 662 | */ |
| bogdanm | 84:0b3ab51c8877 | 663 | #define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) |
| bogdanm | 84:0b3ab51c8877 | 664 | /** |
| bogdanm | 84:0b3ab51c8877 | 665 | * @} |
| bogdanm | 84:0b3ab51c8877 | 666 | */ |
| bogdanm | 84:0b3ab51c8877 | 667 | |
| bogdanm | 84:0b3ab51c8877 | 668 | /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register |
| bogdanm | 84:0b3ab51c8877 | 669 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 670 | */ |
| bogdanm | 84:0b3ab51c8877 | 671 | #define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) |
| bogdanm | 84:0b3ab51c8877 | 672 | /** |
| bogdanm | 84:0b3ab51c8877 | 673 | * @} |
| bogdanm | 84:0b3ab51c8877 | 674 | */ |
| bogdanm | 84:0b3ab51c8877 | 675 | |
| bogdanm | 84:0b3ab51c8877 | 676 | /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask |
| bogdanm | 84:0b3ab51c8877 | 677 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 678 | */ |
| bogdanm | 84:0b3ab51c8877 | 679 | #define UART_IT_MASK ((uint32_t)0x001F) |
| bogdanm | 84:0b3ab51c8877 | 680 | /** |
| bogdanm | 84:0b3ab51c8877 | 681 | * @} |
| bogdanm | 84:0b3ab51c8877 | 682 | */ |
| bogdanm | 84:0b3ab51c8877 | 683 | |
| bogdanm | 84:0b3ab51c8877 | 684 | /** |
| bogdanm | 84:0b3ab51c8877 | 685 | * @} |
| bogdanm | 84:0b3ab51c8877 | 686 | */ |
| bogdanm | 84:0b3ab51c8877 | 687 | |
| bogdanm | 84:0b3ab51c8877 | 688 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 689 | /** @defgroup UART_Exported_Macros |
| bogdanm | 84:0b3ab51c8877 | 690 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 691 | */ |
| bogdanm | 84:0b3ab51c8877 | 692 | |
| bogdanm | 84:0b3ab51c8877 | 693 | /** @brief Reset UART handle state |
| bogdanm | 84:0b3ab51c8877 | 694 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 695 | * The Handle Instance which can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 696 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 697 | */ |
| bogdanm | 84:0b3ab51c8877 | 698 | #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) |
| bogdanm | 84:0b3ab51c8877 | 699 | |
| bogdanm | 84:0b3ab51c8877 | 700 | /** @brief Checks whether the specified UART flag is set or not. |
| bogdanm | 84:0b3ab51c8877 | 701 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 702 | * This parameter can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 703 | * @param __FLAG__: specifies the flag to check. |
| bogdanm | 84:0b3ab51c8877 | 704 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 705 | * @arg UART_FLAG_REACK: Receive enable ackowledge flag |
| bogdanm | 84:0b3ab51c8877 | 706 | * @arg UART_FLAG_TEACK: Transmit enable ackowledge flag |
| bogdanm | 84:0b3ab51c8877 | 707 | * @arg UART_FLAG_WUF: Wake up from stop mode flag |
| bogdanm | 84:0b3ab51c8877 | 708 | * @arg UART_FLAG_RWU: Receiver wake up flag (is the UART in mute mode) |
| bogdanm | 84:0b3ab51c8877 | 709 | * @arg UART_FLAG_SBKF: Send Break flag |
| bogdanm | 84:0b3ab51c8877 | 710 | * @arg UART_FLAG_CMF: Character match flag |
| bogdanm | 84:0b3ab51c8877 | 711 | * @arg UART_FLAG_BUSY: Busy flag |
| bogdanm | 84:0b3ab51c8877 | 712 | * @arg UART_FLAG_ABRF: Auto Baud rate detection flag |
| bogdanm | 84:0b3ab51c8877 | 713 | * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag |
| bogdanm | 84:0b3ab51c8877 | 714 | * @arg UART_FLAG_EOBF: End of block flag |
| bogdanm | 84:0b3ab51c8877 | 715 | * @arg UART_FLAG_RTOF: Receiver timeout flag |
| bogdanm | 84:0b3ab51c8877 | 716 | * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) |
| bogdanm | 84:0b3ab51c8877 | 717 | * @arg UART_FLAG_LBD: LIN Break detection flag |
| bogdanm | 84:0b3ab51c8877 | 718 | * @arg UART_FLAG_TXE: Transmit data register empty flag |
| bogdanm | 84:0b3ab51c8877 | 719 | * @arg UART_FLAG_TC: Transmission Complete flag |
| bogdanm | 84:0b3ab51c8877 | 720 | * @arg UART_FLAG_RXNE: Receive data register not empty flag |
| bogdanm | 84:0b3ab51c8877 | 721 | * @arg UART_FLAG_IDLE: Idle Line detection flag |
| bogdanm | 84:0b3ab51c8877 | 722 | * @arg UART_FLAG_ORE: OverRun Error flag |
| bogdanm | 84:0b3ab51c8877 | 723 | * @arg UART_FLAG_NE: Noise Error flag |
| bogdanm | 84:0b3ab51c8877 | 724 | * @arg UART_FLAG_FE: Framing Error flag |
| bogdanm | 84:0b3ab51c8877 | 725 | * @arg UART_FLAG_PE: Parity Error flag |
| bogdanm | 84:0b3ab51c8877 | 726 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 727 | */ |
| bogdanm | 84:0b3ab51c8877 | 728 | #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) |
| bogdanm | 84:0b3ab51c8877 | 729 | |
| bogdanm | 84:0b3ab51c8877 | 730 | /** @brief Enables the specified UART interrupt. |
| bogdanm | 84:0b3ab51c8877 | 731 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 732 | * This parameter can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 733 | * @param __INTERRUPT__: specifies the UART interrupt source to enable. |
| bogdanm | 84:0b3ab51c8877 | 734 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 735 | * @arg UART_IT_WUF: Wakeup from stop mode interrupt |
| bogdanm | 84:0b3ab51c8877 | 736 | * @arg UART_IT_CM: Character match interrupt |
| bogdanm | 84:0b3ab51c8877 | 737 | * @arg UART_IT_CTS: CTS change interrupt |
| bogdanm | 84:0b3ab51c8877 | 738 | * @arg UART_IT_LBD: LIN Break detection interrupt |
| bogdanm | 84:0b3ab51c8877 | 739 | * @arg UART_IT_TXE: Transmit Data Register empty interrupt |
| bogdanm | 84:0b3ab51c8877 | 740 | * @arg UART_IT_TC: Transmission complete interrupt |
| bogdanm | 84:0b3ab51c8877 | 741 | * @arg UART_IT_RXNE: Receive Data register not empty interrupt |
| bogdanm | 84:0b3ab51c8877 | 742 | * @arg UART_IT_IDLE: Idle line detection interrupt |
| bogdanm | 84:0b3ab51c8877 | 743 | * @arg UART_IT_PE: Parity Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 744 | * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
| bogdanm | 84:0b3ab51c8877 | 745 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 746 | */ |
| bogdanm | 84:0b3ab51c8877 | 747 | #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & UART_IT_MASK))): \ |
| bogdanm | 84:0b3ab51c8877 | 748 | ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & UART_IT_MASK))): \ |
| bogdanm | 84:0b3ab51c8877 | 749 | ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & UART_IT_MASK)))) |
| bogdanm | 84:0b3ab51c8877 | 750 | |
| bogdanm | 84:0b3ab51c8877 | 751 | /** @brief Disables the specified UART interrupt. |
| bogdanm | 84:0b3ab51c8877 | 752 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 753 | * This parameter can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 754 | * @param __INTERRUPT__: specifies the UART interrupt source to disable. |
| bogdanm | 84:0b3ab51c8877 | 755 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 756 | * @arg UART_IT_WUF: Wakeup from stop mode interrupt |
| bogdanm | 84:0b3ab51c8877 | 757 | * @arg UART_IT_CM: Character match interrupt |
| bogdanm | 84:0b3ab51c8877 | 758 | * @arg UART_IT_CTS: CTS change interrupt |
| bogdanm | 84:0b3ab51c8877 | 759 | * @arg UART_IT_LBD: LIN Break detection interrupt |
| bogdanm | 84:0b3ab51c8877 | 760 | * @arg UART_IT_TXE: Transmit Data Register empty interrupt |
| bogdanm | 84:0b3ab51c8877 | 761 | * @arg UART_IT_TC: Transmission complete interrupt |
| bogdanm | 84:0b3ab51c8877 | 762 | * @arg UART_IT_RXNE: Receive Data register not empty interrupt |
| bogdanm | 84:0b3ab51c8877 | 763 | * @arg UART_IT_IDLE: Idle line detection interrupt |
| bogdanm | 84:0b3ab51c8877 | 764 | * @arg UART_IT_PE: Parity Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 765 | * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
| bogdanm | 84:0b3ab51c8877 | 766 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 767 | */ |
| bogdanm | 84:0b3ab51c8877 | 768 | #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & UART_IT_MASK))): \ |
| bogdanm | 84:0b3ab51c8877 | 769 | ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & UART_IT_MASK))): \ |
| bogdanm | 84:0b3ab51c8877 | 770 | ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & UART_IT_MASK)))) |
| bogdanm | 84:0b3ab51c8877 | 771 | |
| bogdanm | 84:0b3ab51c8877 | 772 | /** @brief Checks whether the specified UART interrupt has occurred or not. |
| bogdanm | 84:0b3ab51c8877 | 773 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 774 | * This parameter can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 775 | * @param __IT__: specifies the UART interrupt to check. |
| bogdanm | 84:0b3ab51c8877 | 776 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 777 | * @arg UART_IT_WUF: Wakeup from stop mode interrupt |
| bogdanm | 84:0b3ab51c8877 | 778 | * @arg UART_IT_CM: Character match interrupt |
| bogdanm | 84:0b3ab51c8877 | 779 | * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) |
| bogdanm | 84:0b3ab51c8877 | 780 | * @arg UART_IT_LBD: LIN Break detection interrupt |
| bogdanm | 84:0b3ab51c8877 | 781 | * @arg UART_IT_TXE: Transmit Data Register empty interrupt |
| bogdanm | 84:0b3ab51c8877 | 782 | * @arg UART_IT_TC: Transmission complete interrupt |
| bogdanm | 84:0b3ab51c8877 | 783 | * @arg UART_IT_RXNE: Receive Data register not empty interrupt |
| bogdanm | 84:0b3ab51c8877 | 784 | * @arg UART_IT_IDLE: Idle line detection interrupt |
| bogdanm | 84:0b3ab51c8877 | 785 | * @arg UART_IT_ORE: OverRun Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 786 | * @arg UART_IT_NE: Noise Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 787 | * @arg UART_IT_FE: Framing Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 788 | * @arg UART_IT_PE: Parity Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 789 | * @retval The new state of __IT__ (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 790 | */ |
| bogdanm | 84:0b3ab51c8877 | 791 | #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) |
| bogdanm | 84:0b3ab51c8877 | 792 | |
| bogdanm | 84:0b3ab51c8877 | 793 | /** @brief Checks whether the specified UART interrupt source is enabled. |
| bogdanm | 84:0b3ab51c8877 | 794 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 795 | * This parameter can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 796 | * @param __IT__: specifies the UART interrupt source to check. |
| bogdanm | 84:0b3ab51c8877 | 797 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 798 | * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) |
| bogdanm | 84:0b3ab51c8877 | 799 | * @arg UART_IT_LBD: LIN Break detection interrupt |
| bogdanm | 84:0b3ab51c8877 | 800 | * @arg UART_IT_TXE: Transmit Data Register empty interrupt |
| bogdanm | 84:0b3ab51c8877 | 801 | * @arg UART_IT_TC: Transmission complete interrupt |
| bogdanm | 84:0b3ab51c8877 | 802 | * @arg UART_IT_RXNE: Receive Data register not empty interrupt |
| bogdanm | 84:0b3ab51c8877 | 803 | * @arg UART_IT_IDLE: Idle line detection interrupt |
| bogdanm | 84:0b3ab51c8877 | 804 | * @arg UART_IT_ORE: OverRun Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 805 | * @arg UART_IT_NE: Noise Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 806 | * @arg UART_IT_FE: Framing Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 807 | * @arg UART_IT_PE: Parity Error interrupt |
| bogdanm | 84:0b3ab51c8877 | 808 | * @retval The new state of __IT__ (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 809 | */ |
| bogdanm | 84:0b3ab51c8877 | 810 | #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ |
| bogdanm | 84:0b3ab51c8877 | 811 | (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) |
| bogdanm | 84:0b3ab51c8877 | 812 | |
| bogdanm | 84:0b3ab51c8877 | 813 | /** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag. |
| bogdanm | 84:0b3ab51c8877 | 814 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 815 | * This parameter can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 816 | * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set |
| bogdanm | 84:0b3ab51c8877 | 817 | * to clear the corresponding interrupt |
| bogdanm | 84:0b3ab51c8877 | 818 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 819 | * @arg UART_CLEAR_PEF: Parity Error Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 820 | * @arg UART_CLEAR_FEF: Framing Error Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 821 | * @arg UART_CLEAR_NEF: Noise detected Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 822 | * @arg UART_CLEAR_OREF: OverRun Error Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 823 | * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 824 | * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 825 | * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 826 | * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 827 | * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 828 | * @arg UART_CLEAR_EOBF: End Of Block Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 829 | * @arg UART_CLEAR_CMF: Character Match Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 830 | * @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag |
| bogdanm | 84:0b3ab51c8877 | 831 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 832 | */ |
| bogdanm | 84:0b3ab51c8877 | 833 | #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__)) |
| bogdanm | 84:0b3ab51c8877 | 834 | |
| bogdanm | 84:0b3ab51c8877 | 835 | /** @brief Set a specific UART request flag. |
| bogdanm | 84:0b3ab51c8877 | 836 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 837 | * This parameter can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 838 | * @param __REQ__: specifies the request flag to set |
| bogdanm | 84:0b3ab51c8877 | 839 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 840 | * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request |
| bogdanm | 84:0b3ab51c8877 | 841 | * @arg UART_SENDBREAK_REQUEST: Send Break Request |
| bogdanm | 84:0b3ab51c8877 | 842 | * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request |
| bogdanm | 84:0b3ab51c8877 | 843 | * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request |
| bogdanm | 84:0b3ab51c8877 | 844 | * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request |
| bogdanm | 84:0b3ab51c8877 | 845 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 846 | */ |
| bogdanm | 84:0b3ab51c8877 | 847 | #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) |
| bogdanm | 84:0b3ab51c8877 | 848 | |
| bogdanm | 84:0b3ab51c8877 | 849 | /** @brief Enable UART |
| bogdanm | 84:0b3ab51c8877 | 850 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 851 | * The Handle Instance can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 852 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 853 | */ |
| bogdanm | 84:0b3ab51c8877 | 854 | #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) |
| bogdanm | 84:0b3ab51c8877 | 855 | |
| bogdanm | 84:0b3ab51c8877 | 856 | /** @brief Disable UART |
| bogdanm | 84:0b3ab51c8877 | 857 | * @param __HANDLE__: specifies the UART Handle. |
| bogdanm | 84:0b3ab51c8877 | 858 | * The Handle Instance can be USART1, USART2 or LPUART. |
| bogdanm | 84:0b3ab51c8877 | 859 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 860 | */ |
| bogdanm | 84:0b3ab51c8877 | 861 | #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) |
| bogdanm | 84:0b3ab51c8877 | 862 | |
| bogdanm | 84:0b3ab51c8877 | 863 | /** @brief BRR division operation to set BRR register with LPUART |
| bogdanm | 84:0b3ab51c8877 | 864 | * @param _PCLK_: LPUART clock |
| bogdanm | 84:0b3ab51c8877 | 865 | * @param _BAUD_: Baud rate set by the user |
| bogdanm | 84:0b3ab51c8877 | 866 | * @retval Division result |
| bogdanm | 84:0b3ab51c8877 | 867 | */ |
| bogdanm | 84:0b3ab51c8877 | 868 | #define __DIV_LPUART(_PCLK_, _BAUD_) (((_PCLK_)*256)/((_BAUD_))) |
| bogdanm | 84:0b3ab51c8877 | 869 | |
| bogdanm | 84:0b3ab51c8877 | 870 | /** @brief BRR division operation to set BRR register in 8-bit oversampling mode |
| bogdanm | 84:0b3ab51c8877 | 871 | * @param _PCLK_: UART clock |
| bogdanm | 84:0b3ab51c8877 | 872 | * @param _BAUD_: Baud rate set by the user |
| bogdanm | 84:0b3ab51c8877 | 873 | * @retval Division result |
| bogdanm | 84:0b3ab51c8877 | 874 | */ |
| bogdanm | 84:0b3ab51c8877 | 875 | #define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_))) |
| bogdanm | 84:0b3ab51c8877 | 876 | |
| bogdanm | 84:0b3ab51c8877 | 877 | /** @brief BRR division operation to set BRR register in 16-bit oversampling mode |
| bogdanm | 84:0b3ab51c8877 | 878 | * @param _PCLK_: UART clock |
| bogdanm | 84:0b3ab51c8877 | 879 | * @param _BAUD_: Baud rate set by the user |
| bogdanm | 84:0b3ab51c8877 | 880 | * @retval Division result |
| bogdanm | 84:0b3ab51c8877 | 881 | */ |
| bogdanm | 84:0b3ab51c8877 | 882 | #define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_))) |
| bogdanm | 84:0b3ab51c8877 | 883 | |
| bogdanm | 84:0b3ab51c8877 | 884 | /** @brief Check UART Baud rate |
| bogdanm | 84:0b3ab51c8877 | 885 | * @param BAUDRATE: Baudrate specified by the user |
| bogdanm | 84:0b3ab51c8877 | 886 | * The maximum Baud Rate is derived from the maximum clock on L0 (i.e. 32 MHz) |
| bogdanm | 84:0b3ab51c8877 | 887 | * divided by the smallest oversampling used on the USART (i.e. 8) |
| bogdanm | 84:0b3ab51c8877 | 888 | * @retval Test result (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 889 | */ |
| bogdanm | 84:0b3ab51c8877 | 890 | #define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4000001) |
| bogdanm | 84:0b3ab51c8877 | 891 | |
| bogdanm | 84:0b3ab51c8877 | 892 | /** @brief Check UART byte address |
| bogdanm | 84:0b3ab51c8877 | 893 | * @param ADDRESS: UART 8-bit address for wake-up process scheme |
| bogdanm | 84:0b3ab51c8877 | 894 | * @retval Test result (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 895 | */ |
| bogdanm | 84:0b3ab51c8877 | 896 | #define IS_UART_7B_ADDRESS(ADDRESS) ((ADDRESS) <= 0x7F) |
| bogdanm | 84:0b3ab51c8877 | 897 | |
| bogdanm | 84:0b3ab51c8877 | 898 | /** @brief Check UART 4-bit address |
| bogdanm | 84:0b3ab51c8877 | 899 | * @param ADDRESS: UART 4-bit address for wake-up process scheme |
| bogdanm | 84:0b3ab51c8877 | 900 | * @retval Test result (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 901 | */ |
| bogdanm | 84:0b3ab51c8877 | 902 | #define IS_UART_4B_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) |
| bogdanm | 84:0b3ab51c8877 | 903 | |
| bogdanm | 84:0b3ab51c8877 | 904 | /** @brief Check UART assertion time |
| bogdanm | 84:0b3ab51c8877 | 905 | * @param TIME: 5-bit value assertion time |
| bogdanm | 84:0b3ab51c8877 | 906 | * @retval Test result (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 907 | */ |
| bogdanm | 84:0b3ab51c8877 | 908 | #define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F) |
| bogdanm | 84:0b3ab51c8877 | 909 | |
| bogdanm | 84:0b3ab51c8877 | 910 | /** @brief Check UART deassertion time |
| bogdanm | 84:0b3ab51c8877 | 911 | * @param TIME: 5-bit value deassertion time |
| bogdanm | 84:0b3ab51c8877 | 912 | * @retval Test result (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 913 | */ |
| bogdanm | 84:0b3ab51c8877 | 914 | #define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F) |
| bogdanm | 84:0b3ab51c8877 | 915 | |
| bogdanm | 84:0b3ab51c8877 | 916 | /** |
| bogdanm | 84:0b3ab51c8877 | 917 | * @} |
| bogdanm | 84:0b3ab51c8877 | 918 | */ |
| bogdanm | 84:0b3ab51c8877 | 919 | /* Include UART HAL Extension module */ |
| bogdanm | 84:0b3ab51c8877 | 920 | #include "stm32l0xx_hal_uart_ex.h" |
| bogdanm | 84:0b3ab51c8877 | 921 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 922 | /* Initialization/de-initialization functions ********************************/ |
| bogdanm | 84:0b3ab51c8877 | 923 | HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 924 | HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 925 | HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); |
| bogdanm | 84:0b3ab51c8877 | 926 | HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); |
| bogdanm | 84:0b3ab51c8877 | 927 | HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 928 | void HAL_UART_MspInit(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 929 | void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 930 | |
| bogdanm | 84:0b3ab51c8877 | 931 | /* IO operation functions *****************************************************/ |
| bogdanm | 84:0b3ab51c8877 | 932 | HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 933 | HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 934 | HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 935 | HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 936 | HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 937 | HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 938 | HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 939 | HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 940 | HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 941 | void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 942 | void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 943 | void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 944 | void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 945 | void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 946 | void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 947 | void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 948 | |
| bogdanm | 84:0b3ab51c8877 | 949 | /* Peripheral Control and State functions ************************************/ |
| bogdanm | 84:0b3ab51c8877 | 950 | HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 951 | HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 952 | void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 953 | HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 954 | HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 955 | HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 956 | HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 957 | uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 958 | |
| bogdanm | 84:0b3ab51c8877 | 959 | /* Non-User functions ********************************************************/ |
| bogdanm | 84:0b3ab51c8877 | 960 | void UART_SetConfig(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 961 | HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 962 | HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 963 | void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); |
| bogdanm | 84:0b3ab51c8877 | 964 | /** |
| bogdanm | 84:0b3ab51c8877 | 965 | * @} |
| bogdanm | 84:0b3ab51c8877 | 966 | */ |
| bogdanm | 84:0b3ab51c8877 | 967 | |
| bogdanm | 84:0b3ab51c8877 | 968 | /** |
| bogdanm | 84:0b3ab51c8877 | 969 | * @} |
| bogdanm | 84:0b3ab51c8877 | 970 | */ |
| bogdanm | 84:0b3ab51c8877 | 971 | |
| bogdanm | 84:0b3ab51c8877 | 972 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 973 | } |
| bogdanm | 84:0b3ab51c8877 | 974 | #endif |
| bogdanm | 84:0b3ab51c8877 | 975 | |
| bogdanm | 84:0b3ab51c8877 | 976 | #endif /* __STM32L0xx_HAL_UART_H */ |
| bogdanm | 84:0b3ab51c8877 | 977 | |
| bogdanm | 84:0b3ab51c8877 | 978 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |