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TARGET_NUCLEO_L053R8/stm32l0xx_hal_smbus.h@86:4f9a848d74c7, 2014-06-25 (annotated)
- Committer:
- erezi
- Date:
- Wed Jun 25 06:08:49 2014 +0000
- Revision:
- 86:4f9a848d74c7
- Parent:
- 84:0b3ab51c8877
version_2.0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 84:0b3ab51c8877 | 1 | /** |
| bogdanm | 84:0b3ab51c8877 | 2 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 3 | * @file stm32l0xx_hal_smbus.h |
| bogdanm | 84:0b3ab51c8877 | 4 | * @author MCD Application Team |
| bogdanm | 84:0b3ab51c8877 | 5 | * @version V1.0.0 |
| bogdanm | 84:0b3ab51c8877 | 6 | * @date 22-April-2014 |
| bogdanm | 84:0b3ab51c8877 | 7 | * @brief Header file of SMBUS HAL module. |
| bogdanm | 84:0b3ab51c8877 | 8 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 9 | * @attention |
| bogdanm | 84:0b3ab51c8877 | 10 | * |
| bogdanm | 84:0b3ab51c8877 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 84:0b3ab51c8877 | 12 | * |
| bogdanm | 84:0b3ab51c8877 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 84:0b3ab51c8877 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 84:0b3ab51c8877 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 84:0b3ab51c8877 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 84:0b3ab51c8877 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 84:0b3ab51c8877 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 84:0b3ab51c8877 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 84:0b3ab51c8877 | 22 | * without specific prior written permission. |
| bogdanm | 84:0b3ab51c8877 | 23 | * |
| bogdanm | 84:0b3ab51c8877 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 84:0b3ab51c8877 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 84:0b3ab51c8877 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 84:0b3ab51c8877 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 84:0b3ab51c8877 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 84:0b3ab51c8877 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 84:0b3ab51c8877 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 84:0b3ab51c8877 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 84:0b3ab51c8877 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 84:0b3ab51c8877 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 84:0b3ab51c8877 | 34 | * |
| bogdanm | 84:0b3ab51c8877 | 35 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 36 | */ |
| bogdanm | 84:0b3ab51c8877 | 37 | |
| bogdanm | 84:0b3ab51c8877 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 39 | #ifndef __STM32L0xx_HAL_SMBUS_H |
| bogdanm | 84:0b3ab51c8877 | 40 | #define __STM32L0xx_HAL_SMBUS_H |
| bogdanm | 84:0b3ab51c8877 | 41 | |
| bogdanm | 84:0b3ab51c8877 | 42 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 43 | extern "C" { |
| bogdanm | 84:0b3ab51c8877 | 44 | #endif |
| bogdanm | 84:0b3ab51c8877 | 45 | |
| bogdanm | 84:0b3ab51c8877 | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 47 | #include "stm32l0xx_hal_def.h" |
| bogdanm | 84:0b3ab51c8877 | 48 | |
| bogdanm | 84:0b3ab51c8877 | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 84:0b3ab51c8877 | 50 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 51 | */ |
| bogdanm | 84:0b3ab51c8877 | 52 | |
| bogdanm | 84:0b3ab51c8877 | 53 | /** @addtogroup SMBUS |
| bogdanm | 84:0b3ab51c8877 | 54 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 55 | */ |
| bogdanm | 84:0b3ab51c8877 | 56 | |
| bogdanm | 84:0b3ab51c8877 | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 58 | |
| bogdanm | 84:0b3ab51c8877 | 59 | /** |
| bogdanm | 84:0b3ab51c8877 | 60 | * @brief SMBUS Configuration Structure definition |
| bogdanm | 84:0b3ab51c8877 | 61 | */ |
| bogdanm | 84:0b3ab51c8877 | 62 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 63 | { |
| bogdanm | 84:0b3ab51c8877 | 64 | uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. |
| bogdanm | 84:0b3ab51c8877 | 65 | This parameter calculated by referring to SMBUS initialization |
| bogdanm | 84:0b3ab51c8877 | 66 | section in Reference manual */ |
| bogdanm | 84:0b3ab51c8877 | 67 | |
| bogdanm | 84:0b3ab51c8877 | 68 | uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. |
| bogdanm | 84:0b3ab51c8877 | 69 | This parameter can be a a value of @ref SMBUS_Analog_Filter */ |
| bogdanm | 84:0b3ab51c8877 | 70 | |
| bogdanm | 84:0b3ab51c8877 | 71 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
| bogdanm | 84:0b3ab51c8877 | 72 | This parameter can be a 7-bit or 10-bit address. */ |
| bogdanm | 84:0b3ab51c8877 | 73 | |
| bogdanm | 84:0b3ab51c8877 | 74 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. |
| bogdanm | 84:0b3ab51c8877 | 75 | This parameter can be a value of @ref SMBUS_addressing_mode */ |
| bogdanm | 84:0b3ab51c8877 | 76 | |
| bogdanm | 84:0b3ab51c8877 | 77 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
| bogdanm | 84:0b3ab51c8877 | 78 | This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
| bogdanm | 84:0b3ab51c8877 | 79 | |
| bogdanm | 84:0b3ab51c8877 | 80 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
| bogdanm | 84:0b3ab51c8877 | 81 | This parameter can be a 7-bit address. */ |
| bogdanm | 84:0b3ab51c8877 | 82 | |
| bogdanm | 84:0b3ab51c8877 | 83 | uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected |
| bogdanm | 84:0b3ab51c8877 | 84 | This parameter can be a value of @ref SMBUS_own_address2_masks. */ |
| bogdanm | 84:0b3ab51c8877 | 85 | |
| bogdanm | 84:0b3ab51c8877 | 86 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
| bogdanm | 84:0b3ab51c8877 | 87 | This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ |
| bogdanm | 84:0b3ab51c8877 | 88 | |
| bogdanm | 84:0b3ab51c8877 | 89 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
| bogdanm | 84:0b3ab51c8877 | 90 | This parameter can be a value of @ref SMBUS_nostretch_mode */ |
| bogdanm | 84:0b3ab51c8877 | 91 | |
| bogdanm | 84:0b3ab51c8877 | 92 | uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. |
| bogdanm | 84:0b3ab51c8877 | 93 | This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
| bogdanm | 84:0b3ab51c8877 | 94 | |
| bogdanm | 84:0b3ab51c8877 | 95 | uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. |
| bogdanm | 84:0b3ab51c8877 | 96 | This parameter can be a value of @ref SMBUS_peripheral_mode */ |
| bogdanm | 84:0b3ab51c8877 | 97 | |
| bogdanm | 84:0b3ab51c8877 | 98 | uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. |
| bogdanm | 84:0b3ab51c8877 | 99 | (Enable bits and different timeout values) |
| bogdanm | 84:0b3ab51c8877 | 100 | This parameter calculated by referring to SMBUS initialization |
| bogdanm | 84:0b3ab51c8877 | 101 | section in Reference manual */ |
| bogdanm | 84:0b3ab51c8877 | 102 | } SMBUS_InitTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 103 | |
| bogdanm | 84:0b3ab51c8877 | 104 | /** |
| bogdanm | 84:0b3ab51c8877 | 105 | * @brief HAL State structures definition |
| bogdanm | 84:0b3ab51c8877 | 106 | */ |
| bogdanm | 84:0b3ab51c8877 | 107 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 108 | { |
| bogdanm | 84:0b3ab51c8877 | 109 | HAL_SMBUS_STATE_RESET = 0x00, /*!< SMBUS not yet initialized or disabled */ |
| bogdanm | 84:0b3ab51c8877 | 110 | HAL_SMBUS_STATE_READY = 0x01, /*!< SMBUS initialized and ready for use */ |
| bogdanm | 84:0b3ab51c8877 | 111 | HAL_SMBUS_STATE_BUSY = 0x02, /*!< SMBUS internal process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 112 | HAL_SMBUS_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 113 | HAL_SMBUS_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 114 | HAL_SMBUS_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 115 | HAL_SMBUS_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 116 | HAL_SMBUS_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| bogdanm | 84:0b3ab51c8877 | 117 | HAL_SMBUS_STATE_ERROR = 0x04, /*!< Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 118 | HAL_SMBUS_STATE_SLAVE_LISTEN = 0x08 /*!< Slave Address Listen Mode is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 119 | }HAL_SMBUS_StateTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 120 | |
| bogdanm | 84:0b3ab51c8877 | 121 | /** |
| bogdanm | 84:0b3ab51c8877 | 122 | * @brief HAL SMBUS Error Code structure definition |
| bogdanm | 84:0b3ab51c8877 | 123 | */ |
| bogdanm | 84:0b3ab51c8877 | 124 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 125 | { |
| bogdanm | 84:0b3ab51c8877 | 126 | HAL_SMBUS_ERROR_NONE = 0x00, /*!< No error */ |
| bogdanm | 84:0b3ab51c8877 | 127 | HAL_SMBUS_ERROR_BERR = 0x01, /*!< BERR error */ |
| bogdanm | 84:0b3ab51c8877 | 128 | HAL_SMBUS_ERROR_ARLO = 0x02, /*!< ARLO error */ |
| bogdanm | 84:0b3ab51c8877 | 129 | HAL_SMBUS_ERROR_ACKF = 0x04, /*!< ACKF error */ |
| bogdanm | 84:0b3ab51c8877 | 130 | HAL_SMBUS_ERROR_OVR = 0x08, /*!< OVR error */ |
| bogdanm | 84:0b3ab51c8877 | 131 | HAL_SMBUS_ERROR_HALTIMEOUT = 0x10, /*!< Timeout error */ |
| bogdanm | 84:0b3ab51c8877 | 132 | HAL_SMBUS_ERROR_BUSTIMEOUT = 0x20, /*!< Bus Timeout error */ |
| bogdanm | 84:0b3ab51c8877 | 133 | HAL_SMBUS_ERROR_ALERT = 0x40, /*!< Alert error */ |
| bogdanm | 84:0b3ab51c8877 | 134 | HAL_SMBUS_ERROR_PECERR = 0x80 /*!< PEC error */ |
| bogdanm | 84:0b3ab51c8877 | 135 | |
| bogdanm | 84:0b3ab51c8877 | 136 | }HAL_SMBUS_ErrorTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 137 | |
| bogdanm | 84:0b3ab51c8877 | 138 | /** |
| bogdanm | 84:0b3ab51c8877 | 139 | * @brief SMBUS handle Structure definition |
| bogdanm | 84:0b3ab51c8877 | 140 | */ |
| bogdanm | 84:0b3ab51c8877 | 141 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 142 | { |
| bogdanm | 84:0b3ab51c8877 | 143 | I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
| bogdanm | 84:0b3ab51c8877 | 144 | |
| bogdanm | 84:0b3ab51c8877 | 145 | SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
| bogdanm | 84:0b3ab51c8877 | 146 | |
| bogdanm | 84:0b3ab51c8877 | 147 | uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ |
| bogdanm | 84:0b3ab51c8877 | 148 | |
| bogdanm | 84:0b3ab51c8877 | 149 | uint16_t XferSize; /*!< SMBUS transfer size */ |
| bogdanm | 84:0b3ab51c8877 | 150 | |
| bogdanm | 84:0b3ab51c8877 | 151 | __IO uint16_t XferCount; /*!< SMBUS transfer counter */ |
| bogdanm | 84:0b3ab51c8877 | 152 | |
| bogdanm | 84:0b3ab51c8877 | 153 | __IO uint32_t XferOptions; /*!< SMBUS transfer options */ |
| bogdanm | 84:0b3ab51c8877 | 154 | |
| bogdanm | 84:0b3ab51c8877 | 155 | __IO HAL_SMBUS_StateTypeDef PreviousState; /*!< SMBUS communication Previous tate */ |
| bogdanm | 84:0b3ab51c8877 | 156 | |
| bogdanm | 84:0b3ab51c8877 | 157 | HAL_LockTypeDef Lock; /*!< SMBUS locking object */ |
| bogdanm | 84:0b3ab51c8877 | 158 | |
| bogdanm | 84:0b3ab51c8877 | 159 | __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ |
| bogdanm | 84:0b3ab51c8877 | 160 | |
| bogdanm | 84:0b3ab51c8877 | 161 | __IO HAL_SMBUS_ErrorTypeDef ErrorCode; /*!< SMBUS Error code */ |
| bogdanm | 84:0b3ab51c8877 | 162 | |
| bogdanm | 84:0b3ab51c8877 | 163 | }SMBUS_HandleTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 164 | |
| bogdanm | 84:0b3ab51c8877 | 165 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 166 | |
| bogdanm | 84:0b3ab51c8877 | 167 | /** @defgroup SMBUS_Exported_Constants |
| bogdanm | 84:0b3ab51c8877 | 168 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 169 | */ |
| bogdanm | 84:0b3ab51c8877 | 170 | |
| bogdanm | 84:0b3ab51c8877 | 171 | /** @defgroup SMBUS_Analog_Filter |
| bogdanm | 84:0b3ab51c8877 | 172 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 173 | */ |
| bogdanm | 84:0b3ab51c8877 | 174 | #define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 175 | #define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF |
| bogdanm | 84:0b3ab51c8877 | 176 | |
| bogdanm | 84:0b3ab51c8877 | 177 | #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 178 | ((FILTER) == SMBUS_ANALOGFILTER_DISABLED)) |
| bogdanm | 84:0b3ab51c8877 | 179 | /** |
| bogdanm | 84:0b3ab51c8877 | 180 | * @} |
| bogdanm | 84:0b3ab51c8877 | 181 | */ |
| bogdanm | 84:0b3ab51c8877 | 182 | |
| bogdanm | 84:0b3ab51c8877 | 183 | /** @defgroup SMBUS_addressing_mode |
| bogdanm | 84:0b3ab51c8877 | 184 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 185 | */ |
| bogdanm | 84:0b3ab51c8877 | 186 | #define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) |
| bogdanm | 84:0b3ab51c8877 | 187 | #define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) |
| bogdanm | 84:0b3ab51c8877 | 188 | |
| bogdanm | 84:0b3ab51c8877 | 189 | #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
| bogdanm | 84:0b3ab51c8877 | 190 | ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) |
| bogdanm | 84:0b3ab51c8877 | 191 | /** |
| bogdanm | 84:0b3ab51c8877 | 192 | * @} |
| bogdanm | 84:0b3ab51c8877 | 193 | */ |
| bogdanm | 84:0b3ab51c8877 | 194 | |
| bogdanm | 84:0b3ab51c8877 | 195 | /** @defgroup SMBUS_dual_addressing_mode |
| bogdanm | 84:0b3ab51c8877 | 196 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 197 | */ |
| bogdanm | 84:0b3ab51c8877 | 198 | |
| bogdanm | 84:0b3ab51c8877 | 199 | #define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 200 | #define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN |
| bogdanm | 84:0b3ab51c8877 | 201 | |
| bogdanm | 84:0b3ab51c8877 | 202 | #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 203 | ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 204 | /** |
| bogdanm | 84:0b3ab51c8877 | 205 | * @} |
| bogdanm | 84:0b3ab51c8877 | 206 | */ |
| bogdanm | 84:0b3ab51c8877 | 207 | |
| bogdanm | 84:0b3ab51c8877 | 208 | /** @defgroup SMBUS_own_address2_masks |
| bogdanm | 84:0b3ab51c8877 | 209 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 210 | */ |
| bogdanm | 84:0b3ab51c8877 | 211 | |
| bogdanm | 84:0b3ab51c8877 | 212 | #define SMBUS_OA2_NOMASK ((uint8_t)0x00) |
| bogdanm | 84:0b3ab51c8877 | 213 | #define SMBUS_OA2_MASK01 ((uint8_t)0x01) |
| bogdanm | 84:0b3ab51c8877 | 214 | #define SMBUS_OA2_MASK02 ((uint8_t)0x02) |
| bogdanm | 84:0b3ab51c8877 | 215 | #define SMBUS_OA2_MASK03 ((uint8_t)0x03) |
| bogdanm | 84:0b3ab51c8877 | 216 | #define SMBUS_OA2_MASK04 ((uint8_t)0x04) |
| bogdanm | 84:0b3ab51c8877 | 217 | #define SMBUS_OA2_MASK05 ((uint8_t)0x05) |
| bogdanm | 84:0b3ab51c8877 | 218 | #define SMBUS_OA2_MASK06 ((uint8_t)0x06) |
| bogdanm | 84:0b3ab51c8877 | 219 | #define SMBUS_OA2_MASK07 ((uint8_t)0x07) |
| bogdanm | 84:0b3ab51c8877 | 220 | |
| bogdanm | 84:0b3ab51c8877 | 221 | #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ |
| bogdanm | 84:0b3ab51c8877 | 222 | ((MASK) == SMBUS_OA2_MASK01) || \ |
| bogdanm | 84:0b3ab51c8877 | 223 | ((MASK) == SMBUS_OA2_MASK02) || \ |
| bogdanm | 84:0b3ab51c8877 | 224 | ((MASK) == SMBUS_OA2_MASK03) || \ |
| bogdanm | 84:0b3ab51c8877 | 225 | ((MASK) == SMBUS_OA2_MASK04) || \ |
| bogdanm | 84:0b3ab51c8877 | 226 | ((MASK) == SMBUS_OA2_MASK05) || \ |
| bogdanm | 84:0b3ab51c8877 | 227 | ((MASK) == SMBUS_OA2_MASK06) || \ |
| bogdanm | 84:0b3ab51c8877 | 228 | ((MASK) == SMBUS_OA2_MASK07)) |
| bogdanm | 84:0b3ab51c8877 | 229 | /** |
| bogdanm | 84:0b3ab51c8877 | 230 | * @} |
| bogdanm | 84:0b3ab51c8877 | 231 | */ |
| bogdanm | 84:0b3ab51c8877 | 232 | |
| bogdanm | 84:0b3ab51c8877 | 233 | |
| bogdanm | 84:0b3ab51c8877 | 234 | /** @defgroup SMBUS_general_call_addressing_mode |
| bogdanm | 84:0b3ab51c8877 | 235 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 236 | */ |
| bogdanm | 84:0b3ab51c8877 | 237 | #define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 238 | #define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN |
| bogdanm | 84:0b3ab51c8877 | 239 | |
| bogdanm | 84:0b3ab51c8877 | 240 | #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 241 | ((CALL) == SMBUS_GENERALCALL_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 242 | /** |
| bogdanm | 84:0b3ab51c8877 | 243 | * @} |
| bogdanm | 84:0b3ab51c8877 | 244 | */ |
| bogdanm | 84:0b3ab51c8877 | 245 | |
| bogdanm | 84:0b3ab51c8877 | 246 | /** @defgroup SMBUS_nostretch_mode |
| bogdanm | 84:0b3ab51c8877 | 247 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 248 | */ |
| bogdanm | 84:0b3ab51c8877 | 249 | #define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 250 | #define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH |
| bogdanm | 84:0b3ab51c8877 | 251 | |
| bogdanm | 84:0b3ab51c8877 | 252 | #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 253 | ((STRETCH) == SMBUS_NOSTRETCH_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 254 | /** |
| bogdanm | 84:0b3ab51c8877 | 255 | * @} |
| bogdanm | 84:0b3ab51c8877 | 256 | */ |
| bogdanm | 84:0b3ab51c8877 | 257 | |
| bogdanm | 84:0b3ab51c8877 | 258 | /** @defgroup SMBUS_packet_error_check_mode |
| bogdanm | 84:0b3ab51c8877 | 259 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 260 | */ |
| bogdanm | 84:0b3ab51c8877 | 261 | #define SMBUS_PEC_DISABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 262 | #define SMBUS_PEC_ENABLED I2C_CR1_PECEN |
| bogdanm | 84:0b3ab51c8877 | 263 | |
| bogdanm | 84:0b3ab51c8877 | 264 | #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 265 | ((PEC) == SMBUS_PEC_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 266 | /** |
| bogdanm | 84:0b3ab51c8877 | 267 | * @} |
| bogdanm | 84:0b3ab51c8877 | 268 | */ |
| bogdanm | 84:0b3ab51c8877 | 269 | |
| bogdanm | 84:0b3ab51c8877 | 270 | /** @defgroup SMBUS_peripheral_mode |
| bogdanm | 84:0b3ab51c8877 | 271 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 272 | */ |
| bogdanm | 84:0b3ab51c8877 | 273 | #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN) |
| bogdanm | 84:0b3ab51c8877 | 274 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 275 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN) |
| bogdanm | 84:0b3ab51c8877 | 276 | |
| bogdanm | 84:0b3ab51c8877 | 277 | #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
| bogdanm | 84:0b3ab51c8877 | 278 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
| bogdanm | 84:0b3ab51c8877 | 279 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
| bogdanm | 84:0b3ab51c8877 | 280 | /** |
| bogdanm | 84:0b3ab51c8877 | 281 | * @} |
| bogdanm | 84:0b3ab51c8877 | 282 | */ |
| bogdanm | 84:0b3ab51c8877 | 283 | |
| bogdanm | 84:0b3ab51c8877 | 284 | /** @defgroup SMBUS_ReloadEndMode_definition |
| bogdanm | 84:0b3ab51c8877 | 285 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 286 | */ |
| bogdanm | 84:0b3ab51c8877 | 287 | |
| bogdanm | 84:0b3ab51c8877 | 288 | #define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 289 | #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD |
| bogdanm | 84:0b3ab51c8877 | 290 | #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND |
| bogdanm | 84:0b3ab51c8877 | 291 | #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE |
| bogdanm | 84:0b3ab51c8877 | 292 | |
| bogdanm | 84:0b3ab51c8877 | 293 | #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ |
| bogdanm | 84:0b3ab51c8877 | 294 | ((MODE) == SMBUS_AUTOEND_MODE) || \ |
| bogdanm | 84:0b3ab51c8877 | 295 | ((MODE) == SMBUS_SOFTEND_MODE) || \ |
| bogdanm | 84:0b3ab51c8877 | 296 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ |
| bogdanm | 84:0b3ab51c8877 | 297 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ |
| bogdanm | 84:0b3ab51c8877 | 298 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) |
| bogdanm | 84:0b3ab51c8877 | 299 | |
| bogdanm | 84:0b3ab51c8877 | 300 | /** |
| bogdanm | 84:0b3ab51c8877 | 301 | * @} |
| bogdanm | 84:0b3ab51c8877 | 302 | */ |
| bogdanm | 84:0b3ab51c8877 | 303 | |
| bogdanm | 84:0b3ab51c8877 | 304 | /** @defgroup SMBUS_StartStopMode_definition |
| bogdanm | 84:0b3ab51c8877 | 305 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 306 | */ |
| bogdanm | 84:0b3ab51c8877 | 307 | |
| bogdanm | 84:0b3ab51c8877 | 308 | #define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 309 | #define SMBUS_GENERATE_STOP I2C_CR2_STOP |
| bogdanm | 84:0b3ab51c8877 | 310 | #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) |
| bogdanm | 84:0b3ab51c8877 | 311 | #define SMBUS_GENERATE_START_WRITE I2C_CR2_START |
| bogdanm | 84:0b3ab51c8877 | 312 | |
| bogdanm | 84:0b3ab51c8877 | 313 | #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ |
| bogdanm | 84:0b3ab51c8877 | 314 | ((REQUEST) == SMBUS_GENERATE_START_READ) || \ |
| bogdanm | 84:0b3ab51c8877 | 315 | ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ |
| bogdanm | 84:0b3ab51c8877 | 316 | ((REQUEST) == SMBUS_NO_STARTSTOP)) |
| bogdanm | 84:0b3ab51c8877 | 317 | /** |
| bogdanm | 84:0b3ab51c8877 | 318 | * @} |
| bogdanm | 84:0b3ab51c8877 | 319 | */ |
| bogdanm | 84:0b3ab51c8877 | 320 | |
| bogdanm | 84:0b3ab51c8877 | 321 | /** @defgroup SMBUS_XferOptions_definition |
| bogdanm | 84:0b3ab51c8877 | 322 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 323 | */ |
| bogdanm | 84:0b3ab51c8877 | 324 | |
| bogdanm | 84:0b3ab51c8877 | 325 | #define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE)) |
| bogdanm | 84:0b3ab51c8877 | 326 | #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) |
| bogdanm | 84:0b3ab51c8877 | 327 | #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| bogdanm | 84:0b3ab51c8877 | 328 | #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| bogdanm | 84:0b3ab51c8877 | 329 | #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| bogdanm | 84:0b3ab51c8877 | 330 | #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| bogdanm | 84:0b3ab51c8877 | 331 | |
| bogdanm | 84:0b3ab51c8877 | 332 | #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ |
| bogdanm | 84:0b3ab51c8877 | 333 | ((REQUEST) == SMBUS_NEXT_FRAME) || \ |
| bogdanm | 84:0b3ab51c8877 | 334 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
| bogdanm | 84:0b3ab51c8877 | 335 | ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
| bogdanm | 84:0b3ab51c8877 | 336 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
| bogdanm | 84:0b3ab51c8877 | 337 | ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) |
| bogdanm | 84:0b3ab51c8877 | 338 | |
| bogdanm | 84:0b3ab51c8877 | 339 | /** |
| bogdanm | 84:0b3ab51c8877 | 340 | * @} |
| bogdanm | 84:0b3ab51c8877 | 341 | */ |
| bogdanm | 84:0b3ab51c8877 | 342 | |
| bogdanm | 84:0b3ab51c8877 | 343 | /** @defgroup SMBUS_Interrupt_configuration_definition |
| bogdanm | 84:0b3ab51c8877 | 344 | * @brief SMBUS Interrupt definition |
| bogdanm | 84:0b3ab51c8877 | 345 | * Elements values convention: 0xXXXXXXXX |
| bogdanm | 84:0b3ab51c8877 | 346 | * - XXXXXXXX : Interrupt control mask |
| bogdanm | 84:0b3ab51c8877 | 347 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 348 | */ |
| bogdanm | 84:0b3ab51c8877 | 349 | #define SMBUS_IT_ERRI I2C_CR1_ERRIE |
| bogdanm | 84:0b3ab51c8877 | 350 | #define SMBUS_IT_TCI I2C_CR1_TCIE |
| bogdanm | 84:0b3ab51c8877 | 351 | #define SMBUS_IT_STOPI I2C_CR1_STOPIE |
| bogdanm | 84:0b3ab51c8877 | 352 | #define SMBUS_IT_NACKI I2C_CR1_NACKIE |
| bogdanm | 84:0b3ab51c8877 | 353 | #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE |
| bogdanm | 84:0b3ab51c8877 | 354 | #define SMBUS_IT_RXI I2C_CR1_RXIE |
| bogdanm | 84:0b3ab51c8877 | 355 | #define SMBUS_IT_TXI I2C_CR1_TXIE |
| bogdanm | 84:0b3ab51c8877 | 356 | #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) |
| bogdanm | 84:0b3ab51c8877 | 357 | #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) |
| bogdanm | 84:0b3ab51c8877 | 358 | #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) |
| bogdanm | 84:0b3ab51c8877 | 359 | #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) |
| bogdanm | 84:0b3ab51c8877 | 360 | /** |
| bogdanm | 84:0b3ab51c8877 | 361 | * @} |
| bogdanm | 84:0b3ab51c8877 | 362 | */ |
| bogdanm | 84:0b3ab51c8877 | 363 | |
| bogdanm | 84:0b3ab51c8877 | 364 | /** @defgroup SMBUS_Flag_definition |
| bogdanm | 84:0b3ab51c8877 | 365 | * @brief Flag definition |
| bogdanm | 84:0b3ab51c8877 | 366 | * Elements values convention: 0xXXXXYYYY |
| bogdanm | 84:0b3ab51c8877 | 367 | * - XXXXXXXX : Flag mask |
| bogdanm | 84:0b3ab51c8877 | 368 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 369 | */ |
| bogdanm | 84:0b3ab51c8877 | 370 | |
| bogdanm | 84:0b3ab51c8877 | 371 | #define SMBUS_FLAG_TXE I2C_ISR_TXE |
| bogdanm | 84:0b3ab51c8877 | 372 | #define SMBUS_FLAG_TXIS I2C_ISR_TXIS |
| bogdanm | 84:0b3ab51c8877 | 373 | #define SMBUS_FLAG_RXNE I2C_ISR_RXNE |
| bogdanm | 84:0b3ab51c8877 | 374 | #define SMBUS_FLAG_ADDR I2C_ISR_ADDR |
| bogdanm | 84:0b3ab51c8877 | 375 | #define SMBUS_FLAG_AF I2C_ISR_NACKF |
| bogdanm | 84:0b3ab51c8877 | 376 | #define SMBUS_FLAG_STOPF I2C_ISR_STOPF |
| bogdanm | 84:0b3ab51c8877 | 377 | #define SMBUS_FLAG_TC I2C_ISR_TC |
| bogdanm | 84:0b3ab51c8877 | 378 | #define SMBUS_FLAG_TCR I2C_ISR_TCR |
| bogdanm | 84:0b3ab51c8877 | 379 | #define SMBUS_FLAG_BERR I2C_ISR_BERR |
| bogdanm | 84:0b3ab51c8877 | 380 | #define SMBUS_FLAG_ARLO I2C_ISR_ARLO |
| bogdanm | 84:0b3ab51c8877 | 381 | #define SMBUS_FLAG_OVR I2C_ISR_OVR |
| bogdanm | 84:0b3ab51c8877 | 382 | #define SMBUS_FLAG_PECERR I2C_ISR_PECERR |
| bogdanm | 84:0b3ab51c8877 | 383 | #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT |
| bogdanm | 84:0b3ab51c8877 | 384 | #define SMBUS_FLAG_ALERT I2C_ISR_ALERT |
| bogdanm | 84:0b3ab51c8877 | 385 | #define SMBUS_FLAG_BUSY I2C_ISR_BUSY |
| bogdanm | 84:0b3ab51c8877 | 386 | #define SMBUS_FLAG_DIR I2C_ISR_DIR |
| bogdanm | 84:0b3ab51c8877 | 387 | /** |
| bogdanm | 84:0b3ab51c8877 | 388 | * @} |
| bogdanm | 84:0b3ab51c8877 | 389 | */ |
| bogdanm | 84:0b3ab51c8877 | 390 | |
| bogdanm | 84:0b3ab51c8877 | 391 | /** |
| bogdanm | 84:0b3ab51c8877 | 392 | * @} |
| bogdanm | 84:0b3ab51c8877 | 393 | */ |
| bogdanm | 84:0b3ab51c8877 | 394 | |
| bogdanm | 84:0b3ab51c8877 | 395 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 396 | /** @defgroup SMBUS_Exported_Macros |
| bogdanm | 84:0b3ab51c8877 | 397 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 398 | */ |
| bogdanm | 84:0b3ab51c8877 | 399 | |
| bogdanm | 84:0b3ab51c8877 | 400 | /** @brief Reset SMBUS handle state |
| bogdanm | 84:0b3ab51c8877 | 401 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 84:0b3ab51c8877 | 402 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 84:0b3ab51c8877 | 403 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 404 | */ |
| bogdanm | 84:0b3ab51c8877 | 405 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
| bogdanm | 84:0b3ab51c8877 | 406 | |
| bogdanm | 84:0b3ab51c8877 | 407 | /** @brief Enable or disable the specified SMBUS interrupts. |
| bogdanm | 84:0b3ab51c8877 | 408 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 84:0b3ab51c8877 | 409 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 84:0b3ab51c8877 | 410 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| bogdanm | 84:0b3ab51c8877 | 411 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 412 | * @arg SMBUS_IT_ERRI: Errors interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 413 | * @arg SMBUS_IT_TCI: Transfer complete interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 414 | * @arg SMBUS_IT_STOPI: STOP detection interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 415 | * @arg SMBUS_IT_NACKI: NACK received interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 416 | * @arg SMBUS_IT_ADDRI: Address match interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 417 | * @arg SMBUS_IT_RXI: RX interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 418 | * @arg SMBUS_IT_TXI: TX interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 419 | * |
| bogdanm | 84:0b3ab51c8877 | 420 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 421 | */ |
| bogdanm | 84:0b3ab51c8877 | 422 | |
| bogdanm | 84:0b3ab51c8877 | 423 | #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
| bogdanm | 84:0b3ab51c8877 | 424 | #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
| bogdanm | 84:0b3ab51c8877 | 425 | |
| bogdanm | 84:0b3ab51c8877 | 426 | /** @brief Checks if the specified SMBUS interrupt source is enabled or disabled. |
| bogdanm | 84:0b3ab51c8877 | 427 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 84:0b3ab51c8877 | 428 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 84:0b3ab51c8877 | 429 | * @param __INTERRUPT__: specifies the SMBUS interrupt source to check. |
| bogdanm | 84:0b3ab51c8877 | 430 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 431 | * @arg SMBUS_IT_ERRI: Errors interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 432 | * @arg SMBUS_IT_TCI: Transfer complete interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 433 | * @arg SMBUS_IT_STOPI: STOP detection interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 434 | * @arg SMBUS_IT_NACKI: NACK received interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 435 | * @arg SMBUS_IT_ADDRI: Address match interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 436 | * @arg SMBUS_IT_RXI: RX interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 437 | * @arg SMBUS_IT_TXI: TX interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 438 | * |
| bogdanm | 84:0b3ab51c8877 | 439 | * @retval The new state of __IT__ (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 440 | */ |
| bogdanm | 84:0b3ab51c8877 | 441 | #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| bogdanm | 84:0b3ab51c8877 | 442 | |
| bogdanm | 84:0b3ab51c8877 | 443 | /** @brief Checks whether the specified SMBUS flag is set or not. |
| bogdanm | 84:0b3ab51c8877 | 444 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 84:0b3ab51c8877 | 445 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 84:0b3ab51c8877 | 446 | * @param __FLAG__: specifies the flag to check. |
| bogdanm | 84:0b3ab51c8877 | 447 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 448 | * @arg SMBUS_FLAG_TXE: Transmit data register empty |
| bogdanm | 84:0b3ab51c8877 | 449 | * @arg SMBUS_FLAG_TXIS: Transmit interrupt status |
| bogdanm | 84:0b3ab51c8877 | 450 | * @arg SMBUS_FLAG_RXNE: Receive data register not empty |
| bogdanm | 84:0b3ab51c8877 | 451 | * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) |
| bogdanm | 84:0b3ab51c8877 | 452 | * @arg SMBUS_FLAG_AF NACK received flag |
| bogdanm | 84:0b3ab51c8877 | 453 | * @arg SMBUS_FLAG_STOPF: STOP detection flag |
| bogdanm | 84:0b3ab51c8877 | 454 | * @arg SMBUS_FLAG_TC: Transfer complete (master mode) |
| bogdanm | 84:0b3ab51c8877 | 455 | * @arg SMBUS_FLAG_TCR: Transfer complete reload |
| bogdanm | 84:0b3ab51c8877 | 456 | * @arg SMBUS_FLAG_BERR: Bus error |
| bogdanm | 84:0b3ab51c8877 | 457 | * @arg SMBUS_FLAG_ARLO: Arbitration lost |
| bogdanm | 84:0b3ab51c8877 | 458 | * @arg SMBUS_FLAG_OVR: Overrun/Underrun |
| bogdanm | 84:0b3ab51c8877 | 459 | * @arg SMBUS_FLAG_PECERR: PEC error in reception |
| bogdanm | 84:0b3ab51c8877 | 460 | * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag |
| bogdanm | 84:0b3ab51c8877 | 461 | * @arg SMBUS_FLAG_ALERT: SMBus alert |
| bogdanm | 84:0b3ab51c8877 | 462 | * @arg SMBUS_FLAG_BUSY: Bus busy |
| bogdanm | 84:0b3ab51c8877 | 463 | * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode) |
| bogdanm | 84:0b3ab51c8877 | 464 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 465 | */ |
| bogdanm | 84:0b3ab51c8877 | 466 | #define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF) |
| bogdanm | 84:0b3ab51c8877 | 467 | #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) |
| bogdanm | 84:0b3ab51c8877 | 468 | |
| bogdanm | 84:0b3ab51c8877 | 469 | /** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit. |
| bogdanm | 84:0b3ab51c8877 | 470 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 84:0b3ab51c8877 | 471 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 84:0b3ab51c8877 | 472 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 84:0b3ab51c8877 | 473 | * This parameter can be any combination of the following values: |
| bogdanm | 84:0b3ab51c8877 | 474 | * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) |
| bogdanm | 84:0b3ab51c8877 | 475 | * @arg SMBUS_FLAG_AF: NACK received flag |
| bogdanm | 84:0b3ab51c8877 | 476 | * @arg SMBUS_FLAG_STOPF: STOP detection flag |
| bogdanm | 84:0b3ab51c8877 | 477 | * @arg SMBUS_FLAG_BERR: Bus error |
| bogdanm | 84:0b3ab51c8877 | 478 | * @arg SMBUS_FLAG_ARLO: Arbitration lost |
| bogdanm | 84:0b3ab51c8877 | 479 | * @arg SMBUS_FLAG_OVR: Overrun/Underrun |
| bogdanm | 84:0b3ab51c8877 | 480 | * @arg SMBUS_FLAG_PECERR: PEC error in reception |
| bogdanm | 84:0b3ab51c8877 | 481 | * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag |
| bogdanm | 84:0b3ab51c8877 | 482 | * @arg SMBUS_FLAG_ALERT: SMBus alert |
| bogdanm | 84:0b3ab51c8877 | 483 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 484 | */ |
| bogdanm | 84:0b3ab51c8877 | 485 | #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= ((__FLAG__) & SMBUS_FLAG_MASK)) |
| bogdanm | 84:0b3ab51c8877 | 486 | |
| bogdanm | 84:0b3ab51c8877 | 487 | |
| bogdanm | 84:0b3ab51c8877 | 488 | #define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) |
| bogdanm | 84:0b3ab51c8877 | 489 | #define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) |
| bogdanm | 84:0b3ab51c8877 | 490 | |
| bogdanm | 84:0b3ab51c8877 | 491 | #define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) |
| bogdanm | 84:0b3ab51c8877 | 492 | #define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) |
| bogdanm | 84:0b3ab51c8877 | 493 | |
| bogdanm | 84:0b3ab51c8877 | 494 | #define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ |
| bogdanm | 84:0b3ab51c8877 | 495 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
| bogdanm | 84:0b3ab51c8877 | 496 | |
| bogdanm | 84:0b3ab51c8877 | 497 | #define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) |
| bogdanm | 84:0b3ab51c8877 | 498 | #define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) |
| bogdanm | 84:0b3ab51c8877 | 499 | #define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
| bogdanm | 84:0b3ab51c8877 | 500 | #define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) |
| bogdanm | 84:0b3ab51c8877 | 501 | #define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) |
| bogdanm | 84:0b3ab51c8877 | 502 | #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK) |
| bogdanm | 84:0b3ab51c8877 | 503 | |
| bogdanm | 84:0b3ab51c8877 | 504 | #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) |
| bogdanm | 84:0b3ab51c8877 | 505 | #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) |
| bogdanm | 84:0b3ab51c8877 | 506 | /** |
| bogdanm | 84:0b3ab51c8877 | 507 | * @} |
| bogdanm | 84:0b3ab51c8877 | 508 | */ |
| bogdanm | 84:0b3ab51c8877 | 509 | |
| bogdanm | 84:0b3ab51c8877 | 510 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 511 | /* Initialization and de-initialization functions ****************************/ |
| bogdanm | 84:0b3ab51c8877 | 512 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 513 | HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 514 | void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 515 | void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 516 | |
| bogdanm | 84:0b3ab51c8877 | 517 | /* IO operation functions ****************************************************/ |
| bogdanm | 84:0b3ab51c8877 | 518 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 519 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 520 | |
| bogdanm | 84:0b3ab51c8877 | 521 | /******* Blocking mode: Polling */ |
| bogdanm | 84:0b3ab51c8877 | 522 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 523 | |
| bogdanm | 84:0b3ab51c8877 | 524 | /******* Non-Blocking mode: Interrupt */ |
| bogdanm | 84:0b3ab51c8877 | 525 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| bogdanm | 84:0b3ab51c8877 | 526 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| bogdanm | 84:0b3ab51c8877 | 527 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
| bogdanm | 84:0b3ab51c8877 | 528 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| bogdanm | 84:0b3ab51c8877 | 529 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| bogdanm | 84:0b3ab51c8877 | 530 | HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 531 | |
| bogdanm | 84:0b3ab51c8877 | 532 | /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
| bogdanm | 84:0b3ab51c8877 | 533 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 534 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 535 | void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 536 | void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 537 | void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 538 | void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 539 | void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
| bogdanm | 84:0b3ab51c8877 | 540 | void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 541 | void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 542 | |
| bogdanm | 84:0b3ab51c8877 | 543 | /* Peripheral State and Errors functions *************************************/ |
| bogdanm | 84:0b3ab51c8877 | 544 | HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 545 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 84:0b3ab51c8877 | 546 | |
| bogdanm | 84:0b3ab51c8877 | 547 | /** |
| bogdanm | 84:0b3ab51c8877 | 548 | * @} |
| bogdanm | 84:0b3ab51c8877 | 549 | */ |
| bogdanm | 84:0b3ab51c8877 | 550 | |
| bogdanm | 84:0b3ab51c8877 | 551 | /** |
| bogdanm | 84:0b3ab51c8877 | 552 | * @} |
| bogdanm | 84:0b3ab51c8877 | 553 | */ |
| bogdanm | 84:0b3ab51c8877 | 554 | |
| bogdanm | 84:0b3ab51c8877 | 555 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 556 | } |
| bogdanm | 84:0b3ab51c8877 | 557 | #endif |
| bogdanm | 84:0b3ab51c8877 | 558 | |
| bogdanm | 84:0b3ab51c8877 | 559 | |
| bogdanm | 84:0b3ab51c8877 | 560 | #endif /* __STM32L0xx_HAL_SMBUS_H */ |
| bogdanm | 84:0b3ab51c8877 | 561 | |
| bogdanm | 84:0b3ab51c8877 | 562 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |