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TARGET_NUCLEO_F302R8/stm32f30x_tim.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
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82:6473597d706e 
version_2.0

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bogdanm 82:6473597d706e 1 /**
bogdanm 82:6473597d706e 2 ******************************************************************************
bogdanm 82:6473597d706e 3 * @file stm32f30x_tim.h
bogdanm 82:6473597d706e 4 * @author MCD Application Team
bogdanm 82:6473597d706e 5 * @version V1.1.0
bogdanm 82:6473597d706e 6 * @date 27-February-2014
bogdanm 82:6473597d706e 7 * @brief This file contains all the functions prototypes for the TIM firmware
bogdanm 82:6473597d706e 8 * library.
bogdanm 82:6473597d706e 9 ******************************************************************************
bogdanm 82:6473597d706e 10 * @attention
bogdanm 82:6473597d706e 11 *
bogdanm 82:6473597d706e 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 82:6473597d706e 13 *
bogdanm 82:6473597d706e 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 15 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 82:6473597d706e 17 * this list of conditions and the following disclaimer.
bogdanm 82:6473597d706e 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 82:6473597d706e 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 82:6473597d706e 20 * and/or other materials provided with the distribution.
bogdanm 82:6473597d706e 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 82:6473597d706e 22 * may be used to endorse or promote products derived from this software
bogdanm 82:6473597d706e 23 * without specific prior written permission.
bogdanm 82:6473597d706e 24 *
bogdanm 82:6473597d706e 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 82:6473597d706e 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 82:6473597d706e 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 82:6473597d706e 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 82:6473597d706e 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 82:6473597d706e 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 82:6473597d706e 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 82:6473597d706e 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 82:6473597d706e 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 35 *
bogdanm 82:6473597d706e 36 ******************************************************************************
bogdanm 82:6473597d706e 37 */
bogdanm 82:6473597d706e 38
bogdanm 82:6473597d706e 39 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 82:6473597d706e 40 #ifndef __STM32F30x_TIM_H
bogdanm 82:6473597d706e 41 #define __STM32F30x_TIM_H
bogdanm 82:6473597d706e 42
bogdanm 82:6473597d706e 43 #ifdef __cplusplus
bogdanm 82:6473597d706e 44 extern "C" {
bogdanm 82:6473597d706e 45 #endif
bogdanm 82:6473597d706e 46
bogdanm 82:6473597d706e 47 /* Includes ------------------------------------------------------------------*/
bogdanm 82:6473597d706e 48 #include "stm32f30x.h"
bogdanm 82:6473597d706e 49
bogdanm 82:6473597d706e 50 /** @addtogroup stm32f30x_StdPeriph_Driver
bogdanm 82:6473597d706e 51 * @{
bogdanm 82:6473597d706e 52 */
bogdanm 82:6473597d706e 53
bogdanm 82:6473597d706e 54 /** @addtogroup TIM
bogdanm 82:6473597d706e 55 * @{
bogdanm 82:6473597d706e 56 */
bogdanm 82:6473597d706e 57
bogdanm 82:6473597d706e 58 /* Exported types ------------------------------------------------------------*/
bogdanm 82:6473597d706e 59
bogdanm 82:6473597d706e 60 /**
bogdanm 82:6473597d706e 61 * @brief TIM Time Base Init structure definition
bogdanm 82:6473597d706e 62 * @note This structure is used with all TIMx except for TIM6 and TIM7.
bogdanm 82:6473597d706e 63 */
bogdanm 82:6473597d706e 64
bogdanm 82:6473597d706e 65 typedef struct
bogdanm 82:6473597d706e 66 {
bogdanm 82:6473597d706e 67 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm 82:6473597d706e 68 This parameter can be a number between 0x0000 and 0xFFFF */
bogdanm 82:6473597d706e 69
bogdanm 82:6473597d706e 70 uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
bogdanm 82:6473597d706e 71 This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm 82:6473597d706e 72
bogdanm 82:6473597d706e 73 uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
bogdanm 82:6473597d706e 74 Auto-Reload Register at the next update event.
bogdanm 82:6473597d706e 75 This parameter must be a number between 0x0000 and 0xFFFF. */
bogdanm 82:6473597d706e 76
bogdanm 82:6473597d706e 77 uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
bogdanm 82:6473597d706e 78 This parameter can be a value of @ref TIM_Clock_Division_CKD */
bogdanm 82:6473597d706e 79
bogdanm 82:6473597d706e 80 uint16_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm 82:6473597d706e 81 reaches zero, an update event is generated and counting restarts
bogdanm 82:6473597d706e 82 from the RCR value (N).
bogdanm 82:6473597d706e 83 This means in PWM mode that (N+1) corresponds to:
bogdanm 82:6473597d706e 84 - the number of PWM periods in edge-aligned mode
bogdanm 82:6473597d706e 85 - the number of half PWM period in center-aligned mode
bogdanm 82:6473597d706e 86 This parameter must be a number between 0x00 and 0xFF.
bogdanm 82:6473597d706e 87 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 82:6473597d706e 88 } TIM_TimeBaseInitTypeDef;
bogdanm 82:6473597d706e 89
bogdanm 82:6473597d706e 90 /**
bogdanm 82:6473597d706e 91 * @brief TIM Output Compare Init structure definition
bogdanm 82:6473597d706e 92 */
bogdanm 82:6473597d706e 93
bogdanm 82:6473597d706e 94 typedef struct
bogdanm 82:6473597d706e 95 {
bogdanm 82:6473597d706e 96 uint32_t TIM_OCMode; /*!< Specifies the TIM mode.
bogdanm 82:6473597d706e 97 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 82:6473597d706e 98
bogdanm 82:6473597d706e 99 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
bogdanm 82:6473597d706e 100 This parameter can be a value of @ref TIM_Output_Compare_State */
bogdanm 82:6473597d706e 101
bogdanm 82:6473597d706e 102 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
bogdanm 82:6473597d706e 103 This parameter can be a value of @ref TIM_Output_Compare_N_State
bogdanm 82:6473597d706e 104 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 82:6473597d706e 105
bogdanm 82:6473597d706e 106 uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 82:6473597d706e 107 This parameter can be a number between 0x0000 and 0xFFFF */
bogdanm 82:6473597d706e 108
bogdanm 82:6473597d706e 109 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
bogdanm 82:6473597d706e 110 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 82:6473597d706e 111
bogdanm 82:6473597d706e 112 uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 82:6473597d706e 113 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 82:6473597d706e 114 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 82:6473597d706e 115
bogdanm 82:6473597d706e 116 uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 82:6473597d706e 117 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 82:6473597d706e 118 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 82:6473597d706e 119
bogdanm 82:6473597d706e 120 uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 82:6473597d706e 121 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 82:6473597d706e 122 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 82:6473597d706e 123 } TIM_OCInitTypeDef;
bogdanm 82:6473597d706e 124
bogdanm 82:6473597d706e 125 /**
bogdanm 82:6473597d706e 126 * @brief TIM Input Capture Init structure definition
bogdanm 82:6473597d706e 127 */
bogdanm 82:6473597d706e 128
bogdanm 82:6473597d706e 129 typedef struct
bogdanm 82:6473597d706e 130 {
bogdanm 82:6473597d706e 131
bogdanm 82:6473597d706e 132 uint16_t TIM_Channel; /*!< Specifies the TIM channel.
bogdanm 82:6473597d706e 133 This parameter can be a value of @ref TIM_Channel */
bogdanm 82:6473597d706e 134
bogdanm 82:6473597d706e 135 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 82:6473597d706e 136 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 82:6473597d706e 137
bogdanm 82:6473597d706e 138 uint16_t TIM_ICSelection; /*!< Specifies the input.
bogdanm 82:6473597d706e 139 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 82:6473597d706e 140
bogdanm 82:6473597d706e 141 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 82:6473597d706e 142 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 82:6473597d706e 143
bogdanm 82:6473597d706e 144 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
bogdanm 82:6473597d706e 145 This parameter can be a number between 0x0 and 0xF */
bogdanm 82:6473597d706e 146 } TIM_ICInitTypeDef;
bogdanm 82:6473597d706e 147
bogdanm 82:6473597d706e 148 /**
bogdanm 82:6473597d706e 149 * @brief BDTR structure definition
bogdanm 82:6473597d706e 150 * @note This structure is used only with TIM1 and TIM8.
bogdanm 82:6473597d706e 151 */
bogdanm 82:6473597d706e 152
bogdanm 82:6473597d706e 153 typedef struct
bogdanm 82:6473597d706e 154 {
bogdanm 82:6473597d706e 155
bogdanm 82:6473597d706e 156 uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
bogdanm 82:6473597d706e 157 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm 82:6473597d706e 158
bogdanm 82:6473597d706e 159 uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
bogdanm 82:6473597d706e 160 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm 82:6473597d706e 161
bogdanm 82:6473597d706e 162 uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
bogdanm 82:6473597d706e 163 This parameter can be a value of @ref TIM_Lock_level */
bogdanm 82:6473597d706e 164
bogdanm 82:6473597d706e 165 uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
bogdanm 82:6473597d706e 166 switching-on of the outputs.
bogdanm 82:6473597d706e 167 This parameter can be a number between 0x00 and 0xFF */
bogdanm 82:6473597d706e 168
bogdanm 82:6473597d706e 169 uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
bogdanm 82:6473597d706e 170 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
bogdanm 82:6473597d706e 171
bogdanm 82:6473597d706e 172 uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
bogdanm 82:6473597d706e 173 This parameter can be a value of @ref TIM_Break_Polarity */
bogdanm 82:6473597d706e 174
bogdanm 82:6473597d706e 175 uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
bogdanm 82:6473597d706e 176 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
bogdanm 82:6473597d706e 177 } TIM_BDTRInitTypeDef;
bogdanm 82:6473597d706e 178
bogdanm 82:6473597d706e 179 /* Exported constants --------------------------------------------------------*/
bogdanm 82:6473597d706e 180
bogdanm 82:6473597d706e 181 /** @defgroup TIM_Exported_constants
bogdanm 82:6473597d706e 182 * @{
bogdanm 82:6473597d706e 183 */
bogdanm 82:6473597d706e 184
bogdanm 82:6473597d706e 185 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
bogdanm 82:6473597d706e 186 ((PERIPH) == TIM2) || \
bogdanm 82:6473597d706e 187 ((PERIPH) == TIM3) || \
bogdanm 82:6473597d706e 188 ((PERIPH) == TIM4) || \
bogdanm 82:6473597d706e 189 ((PERIPH) == TIM6) || \
bogdanm 82:6473597d706e 190 ((PERIPH) == TIM7) || \
bogdanm 82:6473597d706e 191 ((PERIPH) == TIM8) || \
bogdanm 82:6473597d706e 192 ((PERIPH) == TIM15) || \
bogdanm 82:6473597d706e 193 ((PERIPH) == TIM16) || \
bogdanm 82:6473597d706e 194 ((PERIPH) == TIM17))
bogdanm 82:6473597d706e 195 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */
bogdanm 82:6473597d706e 196 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
bogdanm 82:6473597d706e 197 ((PERIPH) == TIM2) || \
bogdanm 82:6473597d706e 198 ((PERIPH) == TIM3) || \
bogdanm 82:6473597d706e 199 ((PERIPH) == TIM4) || \
bogdanm 82:6473597d706e 200 ((PERIPH) == TIM8) || \
bogdanm 82:6473597d706e 201 ((PERIPH) == TIM15) || \
bogdanm 82:6473597d706e 202 ((PERIPH) == TIM16) || \
bogdanm 82:6473597d706e 203 ((PERIPH) == TIM17))
bogdanm 82:6473597d706e 204
bogdanm 82:6473597d706e 205 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */
bogdanm 82:6473597d706e 206 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
bogdanm 82:6473597d706e 207 ((PERIPH) == TIM2) || \
bogdanm 82:6473597d706e 208 ((PERIPH) == TIM3) || \
bogdanm 82:6473597d706e 209 ((PERIPH) == TIM4) || \
bogdanm 82:6473597d706e 210 ((PERIPH) == TIM8) || \
bogdanm 82:6473597d706e 211 ((PERIPH) == TIM15))
bogdanm 82:6473597d706e 212 /* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */
bogdanm 82:6473597d706e 213 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
bogdanm 82:6473597d706e 214 ((PERIPH) == TIM2) || \
bogdanm 82:6473597d706e 215 ((PERIPH) == TIM3) || \
bogdanm 82:6473597d706e 216 ((PERIPH) == TIM4) || \
bogdanm 82:6473597d706e 217 ((PERIPH) == TIM8))
bogdanm 82:6473597d706e 218 /* LIST4: TIM1 and TIM8 */
bogdanm 82:6473597d706e 219 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\
bogdanm 82:6473597d706e 220 ((PERIPH) == TIM8))
bogdanm 82:6473597d706e 221 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
bogdanm 82:6473597d706e 222 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
bogdanm 82:6473597d706e 223 ((PERIPH) == TIM2) || \
bogdanm 82:6473597d706e 224 ((PERIPH) == TIM3) || \
bogdanm 82:6473597d706e 225 ((PERIPH) == TIM4) || \
bogdanm 82:6473597d706e 226 ((PERIPH) == TIM6) || \
bogdanm 82:6473597d706e 227 ((PERIPH) == TIM7) || \
bogdanm 82:6473597d706e 228 ((PERIPH) == TIM8))
bogdanm 82:6473597d706e 229 /* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */
bogdanm 82:6473597d706e 230 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
bogdanm 82:6473597d706e 231 ((PERIPH) == TIM8) || \
bogdanm 82:6473597d706e 232 ((PERIPH) == TIM15) || \
bogdanm 82:6473597d706e 233 ((PERIPH) == TIM16) || \
bogdanm 82:6473597d706e 234 ((PERIPH) == TIM17))
bogdanm 82:6473597d706e 235
bogdanm 82:6473597d706e 236 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
bogdanm 82:6473597d706e 237 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
bogdanm 82:6473597d706e 238 ((PERIPH) == TIM2) || \
bogdanm 82:6473597d706e 239 ((PERIPH) == TIM3) || \
bogdanm 82:6473597d706e 240 ((PERIPH) == TIM4) || \
bogdanm 82:6473597d706e 241 ((PERIPH) == TIM6) || \
bogdanm 82:6473597d706e 242 ((PERIPH) == TIM7) || \
bogdanm 82:6473597d706e 243 ((PERIPH) == TIM8) || \
bogdanm 82:6473597d706e 244 ((PERIPH) == TIM15))
bogdanm 82:6473597d706e 245 /* LIST8: TIM16 (option register) */
bogdanm 82:6473597d706e 246 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)|| \
bogdanm 82:6473597d706e 247 ((PERIPH) == TIM1)||\
bogdanm 82:6473597d706e 248 ((PERIPH) == TIM8))
bogdanm 82:6473597d706e 249
bogdanm 82:6473597d706e 250 /** @defgroup TIM_Output_Compare_and_PWM_modes
bogdanm 82:6473597d706e 251 * @{
bogdanm 82:6473597d706e 252 */
bogdanm 82:6473597d706e 253
bogdanm 82:6473597d706e 254 #define TIM_OCMode_Timing ((uint32_t)0x00000)
bogdanm 82:6473597d706e 255 #define TIM_OCMode_Active ((uint32_t)0x00010)
bogdanm 82:6473597d706e 256 #define TIM_OCMode_Inactive ((uint32_t)0x00020)
bogdanm 82:6473597d706e 257 #define TIM_OCMode_Toggle ((uint32_t)0x00030)
bogdanm 82:6473597d706e 258 #define TIM_OCMode_PWM1 ((uint32_t)0x00060)
bogdanm 82:6473597d706e 259 #define TIM_OCMode_PWM2 ((uint32_t)0x00070)
bogdanm 82:6473597d706e 260
bogdanm 82:6473597d706e 261 #define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000)
bogdanm 82:6473597d706e 262 #define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010)
bogdanm 82:6473597d706e 263 #define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040)
bogdanm 82:6473597d706e 264 #define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050)
bogdanm 82:6473597d706e 265 #define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060)
bogdanm 82:6473597d706e 266 #define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070)
bogdanm 82:6473597d706e 267
bogdanm 82:6473597d706e 268 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
bogdanm 82:6473597d706e 269 ((MODE) == TIM_OCMode_Active) || \
bogdanm 82:6473597d706e 270 ((MODE) == TIM_OCMode_Inactive) || \
bogdanm 82:6473597d706e 271 ((MODE) == TIM_OCMode_Toggle)|| \
bogdanm 82:6473597d706e 272 ((MODE) == TIM_OCMode_PWM1) || \
bogdanm 82:6473597d706e 273 ((MODE) == TIM_OCMode_PWM2) || \
bogdanm 82:6473597d706e 274 ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
bogdanm 82:6473597d706e 275 ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
bogdanm 82:6473597d706e 276 ((MODE) == TIM_OCMode_Combined_PWM1) || \
bogdanm 82:6473597d706e 277 ((MODE) == TIM_OCMode_Combined_PWM2) || \
bogdanm 82:6473597d706e 278 ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
bogdanm 82:6473597d706e 279 ((MODE) == TIM_OCMode_Asymmetric_PWM2))
bogdanm 82:6473597d706e 280
bogdanm 82:6473597d706e 281 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
bogdanm 82:6473597d706e 282 ((MODE) == TIM_OCMode_Active) || \
bogdanm 82:6473597d706e 283 ((MODE) == TIM_OCMode_Inactive) || \
bogdanm 82:6473597d706e 284 ((MODE) == TIM_OCMode_Toggle)|| \
bogdanm 82:6473597d706e 285 ((MODE) == TIM_OCMode_PWM1) || \
bogdanm 82:6473597d706e 286 ((MODE) == TIM_OCMode_PWM2) || \
bogdanm 82:6473597d706e 287 ((MODE) == TIM_ForcedAction_Active) || \
bogdanm 82:6473597d706e 288 ((MODE) == TIM_ForcedAction_InActive) || \
bogdanm 82:6473597d706e 289 ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
bogdanm 82:6473597d706e 290 ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
bogdanm 82:6473597d706e 291 ((MODE) == TIM_OCMode_Combined_PWM1) || \
bogdanm 82:6473597d706e 292 ((MODE) == TIM_OCMode_Combined_PWM2) || \
bogdanm 82:6473597d706e 293 ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
bogdanm 82:6473597d706e 294 ((MODE) == TIM_OCMode_Asymmetric_PWM2))
bogdanm 82:6473597d706e 295 /**
bogdanm 82:6473597d706e 296 * @}
bogdanm 82:6473597d706e 297 */
bogdanm 82:6473597d706e 298
bogdanm 82:6473597d706e 299 /** @defgroup TIM_One_Pulse_Mode
bogdanm 82:6473597d706e 300 * @{
bogdanm 82:6473597d706e 301 */
bogdanm 82:6473597d706e 302
bogdanm 82:6473597d706e 303 #define TIM_OPMode_Single ((uint16_t)0x0008)
bogdanm 82:6473597d706e 304 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
bogdanm 82:6473597d706e 305 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
bogdanm 82:6473597d706e 306 ((MODE) == TIM_OPMode_Repetitive))
bogdanm 82:6473597d706e 307 /**
bogdanm 82:6473597d706e 308 * @}
bogdanm 82:6473597d706e 309 */
bogdanm 82:6473597d706e 310
bogdanm 82:6473597d706e 311 /** @defgroup TIM_Channel
bogdanm 82:6473597d706e 312 * @{
bogdanm 82:6473597d706e 313 */
bogdanm 82:6473597d706e 314
bogdanm 82:6473597d706e 315 #define TIM_Channel_1 ((uint16_t)0x0000)
bogdanm 82:6473597d706e 316 #define TIM_Channel_2 ((uint16_t)0x0004)
bogdanm 82:6473597d706e 317 #define TIM_Channel_3 ((uint16_t)0x0008)
bogdanm 82:6473597d706e 318 #define TIM_Channel_4 ((uint16_t)0x000C)
bogdanm 82:6473597d706e 319 #define TIM_Channel_5 ((uint16_t)0x0010)
bogdanm 82:6473597d706e 320 #define TIM_Channel_6 ((uint16_t)0x0014)
bogdanm 82:6473597d706e 321
bogdanm 82:6473597d706e 322 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
bogdanm 82:6473597d706e 323 ((CHANNEL) == TIM_Channel_2) || \
bogdanm 82:6473597d706e 324 ((CHANNEL) == TIM_Channel_3) || \
bogdanm 82:6473597d706e 325 ((CHANNEL) == TIM_Channel_4))
bogdanm 82:6473597d706e 326
bogdanm 82:6473597d706e 327 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
bogdanm 82:6473597d706e 328 ((CHANNEL) == TIM_Channel_2))
bogdanm 82:6473597d706e 329 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
bogdanm 82:6473597d706e 330 ((CHANNEL) == TIM_Channel_2) || \
bogdanm 82:6473597d706e 331 ((CHANNEL) == TIM_Channel_3))
bogdanm 82:6473597d706e 332 /**
bogdanm 82:6473597d706e 333 * @}
bogdanm 82:6473597d706e 334 */
bogdanm 82:6473597d706e 335
bogdanm 82:6473597d706e 336 /** @defgroup TIM_Clock_Division_CKD
bogdanm 82:6473597d706e 337 * @{
bogdanm 82:6473597d706e 338 */
bogdanm 82:6473597d706e 339
bogdanm 82:6473597d706e 340 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
bogdanm 82:6473597d706e 341 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
bogdanm 82:6473597d706e 342 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
bogdanm 82:6473597d706e 343 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
bogdanm 82:6473597d706e 344 ((DIV) == TIM_CKD_DIV2) || \
bogdanm 82:6473597d706e 345 ((DIV) == TIM_CKD_DIV4))
bogdanm 82:6473597d706e 346 /**
bogdanm 82:6473597d706e 347 * @}
bogdanm 82:6473597d706e 348 */
bogdanm 82:6473597d706e 349
bogdanm 82:6473597d706e 350 /** @defgroup TIM_Counter_Mode
bogdanm 82:6473597d706e 351 * @{
bogdanm 82:6473597d706e 352 */
bogdanm 82:6473597d706e 353
bogdanm 82:6473597d706e 354 #define TIM_CounterMode_Up ((uint16_t)0x0000)
bogdanm 82:6473597d706e 355 #define TIM_CounterMode_Down ((uint16_t)0x0010)
bogdanm 82:6473597d706e 356 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
bogdanm 82:6473597d706e 357 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
bogdanm 82:6473597d706e 358 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
bogdanm 82:6473597d706e 359 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
bogdanm 82:6473597d706e 360 ((MODE) == TIM_CounterMode_Down) || \
bogdanm 82:6473597d706e 361 ((MODE) == TIM_CounterMode_CenterAligned1) || \
bogdanm 82:6473597d706e 362 ((MODE) == TIM_CounterMode_CenterAligned2) || \
bogdanm 82:6473597d706e 363 ((MODE) == TIM_CounterMode_CenterAligned3))
bogdanm 82:6473597d706e 364 /**
bogdanm 82:6473597d706e 365 * @}
bogdanm 82:6473597d706e 366 */
bogdanm 82:6473597d706e 367
bogdanm 82:6473597d706e 368 /** @defgroup TIM_Output_Compare_Polarity
bogdanm 82:6473597d706e 369 * @{
bogdanm 82:6473597d706e 370 */
bogdanm 82:6473597d706e 371
bogdanm 82:6473597d706e 372 #define TIM_OCPolarity_High ((uint16_t)0x0000)
bogdanm 82:6473597d706e 373 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
bogdanm 82:6473597d706e 374 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
bogdanm 82:6473597d706e 375 ((POLARITY) == TIM_OCPolarity_Low))
bogdanm 82:6473597d706e 376 /**
bogdanm 82:6473597d706e 377 * @}
bogdanm 82:6473597d706e 378 */
bogdanm 82:6473597d706e 379
bogdanm 82:6473597d706e 380 /** @defgroup TIM_Output_Compare_N_Polarity
bogdanm 82:6473597d706e 381 * @{
bogdanm 82:6473597d706e 382 */
bogdanm 82:6473597d706e 383
bogdanm 82:6473597d706e 384 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
bogdanm 82:6473597d706e 385 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
bogdanm 82:6473597d706e 386 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
bogdanm 82:6473597d706e 387 ((POLARITY) == TIM_OCNPolarity_Low))
bogdanm 82:6473597d706e 388 /**
bogdanm 82:6473597d706e 389 * @}
bogdanm 82:6473597d706e 390 */
bogdanm 82:6473597d706e 391
bogdanm 82:6473597d706e 392 /** @defgroup TIM_Output_Compare_State
bogdanm 82:6473597d706e 393 * @{
bogdanm 82:6473597d706e 394 */
bogdanm 82:6473597d706e 395
bogdanm 82:6473597d706e 396 #define TIM_OutputState_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 397 #define TIM_OutputState_Enable ((uint16_t)0x0001)
bogdanm 82:6473597d706e 398 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
bogdanm 82:6473597d706e 399 ((STATE) == TIM_OutputState_Enable))
bogdanm 82:6473597d706e 400 /**
bogdanm 82:6473597d706e 401 * @}
bogdanm 82:6473597d706e 402 */
bogdanm 82:6473597d706e 403
bogdanm 82:6473597d706e 404 /** @defgroup TIM_Output_Compare_N_State
bogdanm 82:6473597d706e 405 * @{
bogdanm 82:6473597d706e 406 */
bogdanm 82:6473597d706e 407
bogdanm 82:6473597d706e 408 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 409 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
bogdanm 82:6473597d706e 410 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
bogdanm 82:6473597d706e 411 ((STATE) == TIM_OutputNState_Enable))
bogdanm 82:6473597d706e 412 /**
bogdanm 82:6473597d706e 413 * @}
bogdanm 82:6473597d706e 414 */
bogdanm 82:6473597d706e 415
bogdanm 82:6473597d706e 416 /** @defgroup TIM_Capture_Compare_State
bogdanm 82:6473597d706e 417 * @{
bogdanm 82:6473597d706e 418 */
bogdanm 82:6473597d706e 419
bogdanm 82:6473597d706e 420 #define TIM_CCx_Enable ((uint16_t)0x0001)
bogdanm 82:6473597d706e 421 #define TIM_CCx_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 422 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
bogdanm 82:6473597d706e 423 ((CCX) == TIM_CCx_Disable))
bogdanm 82:6473597d706e 424 /**
bogdanm 82:6473597d706e 425 * @}
bogdanm 82:6473597d706e 426 */
bogdanm 82:6473597d706e 427
bogdanm 82:6473597d706e 428 /** @defgroup TIM_Capture_Compare_N_State
bogdanm 82:6473597d706e 429 * @{
bogdanm 82:6473597d706e 430 */
bogdanm 82:6473597d706e 431
bogdanm 82:6473597d706e 432 #define TIM_CCxN_Enable ((uint16_t)0x0004)
bogdanm 82:6473597d706e 433 #define TIM_CCxN_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 434 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
bogdanm 82:6473597d706e 435 ((CCXN) == TIM_CCxN_Disable))
bogdanm 82:6473597d706e 436 /**
bogdanm 82:6473597d706e 437 * @}
bogdanm 82:6473597d706e 438 */
bogdanm 82:6473597d706e 439
bogdanm 82:6473597d706e 440 /** @defgroup TIM_Break_Input_enable_disable
bogdanm 82:6473597d706e 441 * @{
bogdanm 82:6473597d706e 442 */
bogdanm 82:6473597d706e 443
bogdanm 82:6473597d706e 444 #define TIM_Break_Enable ((uint16_t)0x1000)
bogdanm 82:6473597d706e 445 #define TIM_Break_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 446 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
bogdanm 82:6473597d706e 447 ((STATE) == TIM_Break_Disable))
bogdanm 82:6473597d706e 448 /**
bogdanm 82:6473597d706e 449 * @}
bogdanm 82:6473597d706e 450 */
bogdanm 82:6473597d706e 451
bogdanm 82:6473597d706e 452 /** @defgroup TIM_Break1_Input_enable_disable
bogdanm 82:6473597d706e 453 * @{
bogdanm 82:6473597d706e 454 */
bogdanm 82:6473597d706e 455
bogdanm 82:6473597d706e 456 #define TIM_Break1_Enable ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 457 #define TIM_Break1_Disable ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 458 #define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \
bogdanm 82:6473597d706e 459 ((STATE) == TIM_Break1_Disable))
bogdanm 82:6473597d706e 460 /**
bogdanm 82:6473597d706e 461 * @}
bogdanm 82:6473597d706e 462 */
bogdanm 82:6473597d706e 463
bogdanm 82:6473597d706e 464 /** @defgroup TIM_Break2_Input_enable_disable
bogdanm 82:6473597d706e 465 * @{
bogdanm 82:6473597d706e 466 */
bogdanm 82:6473597d706e 467
bogdanm 82:6473597d706e 468 #define TIM_Break2_Enable ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 469 #define TIM_Break2_Disable ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 470 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \
bogdanm 82:6473597d706e 471 ((STATE) == TIM_Break2_Disable))
bogdanm 82:6473597d706e 472 /**
bogdanm 82:6473597d706e 473 * @}
bogdanm 82:6473597d706e 474 */
bogdanm 82:6473597d706e 475
bogdanm 82:6473597d706e 476 /** @defgroup TIM_Break_Polarity
bogdanm 82:6473597d706e 477 * @{
bogdanm 82:6473597d706e 478 */
bogdanm 82:6473597d706e 479
bogdanm 82:6473597d706e 480 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
bogdanm 82:6473597d706e 481 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
bogdanm 82:6473597d706e 482 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
bogdanm 82:6473597d706e 483 ((POLARITY) == TIM_BreakPolarity_High))
bogdanm 82:6473597d706e 484 /**
bogdanm 82:6473597d706e 485 * @}
bogdanm 82:6473597d706e 486 */
bogdanm 82:6473597d706e 487
bogdanm 82:6473597d706e 488 /** @defgroup TIM_Break1_Polarity
bogdanm 82:6473597d706e 489 * @{
bogdanm 82:6473597d706e 490 */
bogdanm 82:6473597d706e 491
bogdanm 82:6473597d706e 492 #define TIM_Break1Polarity_Low ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 493 #define TIM_Break1Polarity_High ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 494 #define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \
bogdanm 82:6473597d706e 495 ((POLARITY) == TIM_Break1Polarity_High))
bogdanm 82:6473597d706e 496 /**
bogdanm 82:6473597d706e 497 * @}
bogdanm 82:6473597d706e 498 */
bogdanm 82:6473597d706e 499
bogdanm 82:6473597d706e 500 /** @defgroup TIM_Break2_Polarity
bogdanm 82:6473597d706e 501 * @{
bogdanm 82:6473597d706e 502 */
bogdanm 82:6473597d706e 503
bogdanm 82:6473597d706e 504 #define TIM_Break2Polarity_Low ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 505 #define TIM_Break2Polarity_High ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 506 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \
bogdanm 82:6473597d706e 507 ((POLARITY) == TIM_Break2Polarity_High))
bogdanm 82:6473597d706e 508 /**
bogdanm 82:6473597d706e 509 * @}
bogdanm 82:6473597d706e 510 */
bogdanm 82:6473597d706e 511
bogdanm 82:6473597d706e 512 /** @defgroup TIM_Break1_Filter
bogdanm 82:6473597d706e 513 * @{
bogdanm 82:6473597d706e 514 */
bogdanm 82:6473597d706e 515
bogdanm 82:6473597d706e 516 #define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF)
bogdanm 82:6473597d706e 517 /**
bogdanm 82:6473597d706e 518 * @}
bogdanm 82:6473597d706e 519 */
bogdanm 82:6473597d706e 520
bogdanm 82:6473597d706e 521 /** @defgroup TIM_Break2_Filter
bogdanm 82:6473597d706e 522 * @{
bogdanm 82:6473597d706e 523 */
bogdanm 82:6473597d706e 524
bogdanm 82:6473597d706e 525 #define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF)
bogdanm 82:6473597d706e 526 /**
bogdanm 82:6473597d706e 527 * @}
bogdanm 82:6473597d706e 528 */
bogdanm 82:6473597d706e 529
bogdanm 82:6473597d706e 530 /** @defgroup TIM_AOE_Bit_Set_Reset
bogdanm 82:6473597d706e 531 * @{
bogdanm 82:6473597d706e 532 */
bogdanm 82:6473597d706e 533
bogdanm 82:6473597d706e 534 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
bogdanm 82:6473597d706e 535 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 536 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
bogdanm 82:6473597d706e 537 ((STATE) == TIM_AutomaticOutput_Disable))
bogdanm 82:6473597d706e 538 /**
bogdanm 82:6473597d706e 539 * @}
bogdanm 82:6473597d706e 540 */
bogdanm 82:6473597d706e 541
bogdanm 82:6473597d706e 542 /** @defgroup TIM_Lock_level
bogdanm 82:6473597d706e 543 * @{
bogdanm 82:6473597d706e 544 */
bogdanm 82:6473597d706e 545
bogdanm 82:6473597d706e 546 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
bogdanm 82:6473597d706e 547 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
bogdanm 82:6473597d706e 548 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
bogdanm 82:6473597d706e 549 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
bogdanm 82:6473597d706e 550 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
bogdanm 82:6473597d706e 551 ((LEVEL) == TIM_LOCKLevel_1) || \
bogdanm 82:6473597d706e 552 ((LEVEL) == TIM_LOCKLevel_2) || \
bogdanm 82:6473597d706e 553 ((LEVEL) == TIM_LOCKLevel_3))
bogdanm 82:6473597d706e 554 /**
bogdanm 82:6473597d706e 555 * @}
bogdanm 82:6473597d706e 556 */
bogdanm 82:6473597d706e 557
bogdanm 82:6473597d706e 558 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm 82:6473597d706e 559 * @{
bogdanm 82:6473597d706e 560 */
bogdanm 82:6473597d706e 561
bogdanm 82:6473597d706e 562 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
bogdanm 82:6473597d706e 563 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 564 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
bogdanm 82:6473597d706e 565 ((STATE) == TIM_OSSIState_Disable))
bogdanm 82:6473597d706e 566 /**
bogdanm 82:6473597d706e 567 * @}
bogdanm 82:6473597d706e 568 */
bogdanm 82:6473597d706e 569
bogdanm 82:6473597d706e 570 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
bogdanm 82:6473597d706e 571 * @{
bogdanm 82:6473597d706e 572 */
bogdanm 82:6473597d706e 573
bogdanm 82:6473597d706e 574 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
bogdanm 82:6473597d706e 575 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 576 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
bogdanm 82:6473597d706e 577 ((STATE) == TIM_OSSRState_Disable))
bogdanm 82:6473597d706e 578 /**
bogdanm 82:6473597d706e 579 * @}
bogdanm 82:6473597d706e 580 */
bogdanm 82:6473597d706e 581
bogdanm 82:6473597d706e 582 /** @defgroup TIM_Output_Compare_Idle_State
bogdanm 82:6473597d706e 583 * @{
bogdanm 82:6473597d706e 584 */
bogdanm 82:6473597d706e 585
bogdanm 82:6473597d706e 586 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
bogdanm 82:6473597d706e 587 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
bogdanm 82:6473597d706e 588 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
bogdanm 82:6473597d706e 589 ((STATE) == TIM_OCIdleState_Reset))
bogdanm 82:6473597d706e 590 /**
bogdanm 82:6473597d706e 591 * @}
bogdanm 82:6473597d706e 592 */
bogdanm 82:6473597d706e 593
bogdanm 82:6473597d706e 594 /** @defgroup TIM_Output_Compare_N_Idle_State
bogdanm 82:6473597d706e 595 * @{
bogdanm 82:6473597d706e 596 */
bogdanm 82:6473597d706e 597
bogdanm 82:6473597d706e 598 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
bogdanm 82:6473597d706e 599 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
bogdanm 82:6473597d706e 600 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
bogdanm 82:6473597d706e 601 ((STATE) == TIM_OCNIdleState_Reset))
bogdanm 82:6473597d706e 602 /**
bogdanm 82:6473597d706e 603 * @}
bogdanm 82:6473597d706e 604 */
bogdanm 82:6473597d706e 605
bogdanm 82:6473597d706e 606 /** @defgroup TIM_Input_Capture_Polarity
bogdanm 82:6473597d706e 607 * @{
bogdanm 82:6473597d706e 608 */
bogdanm 82:6473597d706e 609
bogdanm 82:6473597d706e 610 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
bogdanm 82:6473597d706e 611 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
bogdanm 82:6473597d706e 612 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
bogdanm 82:6473597d706e 613 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
bogdanm 82:6473597d706e 614 ((POLARITY) == TIM_ICPolarity_Falling)|| \
bogdanm 82:6473597d706e 615 ((POLARITY) == TIM_ICPolarity_BothEdge))
bogdanm 82:6473597d706e 616 /**
bogdanm 82:6473597d706e 617 * @}
bogdanm 82:6473597d706e 618 */
bogdanm 82:6473597d706e 619
bogdanm 82:6473597d706e 620 /** @defgroup TIM_Input_Capture_Selection
bogdanm 82:6473597d706e 621 * @{
bogdanm 82:6473597d706e 622 */
bogdanm 82:6473597d706e 623
bogdanm 82:6473597d706e 624 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 82:6473597d706e 625 connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm 82:6473597d706e 626 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 82:6473597d706e 627 connected to IC2, IC1, IC4 or IC3, respectively. */
bogdanm 82:6473597d706e 628 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
bogdanm 82:6473597d706e 629 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
bogdanm 82:6473597d706e 630 ((SELECTION) == TIM_ICSelection_IndirectTI) || \
bogdanm 82:6473597d706e 631 ((SELECTION) == TIM_ICSelection_TRC))
bogdanm 82:6473597d706e 632 /**
bogdanm 82:6473597d706e 633 * @}
bogdanm 82:6473597d706e 634 */
bogdanm 82:6473597d706e 635
bogdanm 82:6473597d706e 636 /** @defgroup TIM_Input_Capture_Prescaler
bogdanm 82:6473597d706e 637 * @{
bogdanm 82:6473597d706e 638 */
bogdanm 82:6473597d706e 639
bogdanm 82:6473597d706e 640 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
bogdanm 82:6473597d706e 641 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
bogdanm 82:6473597d706e 642 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
bogdanm 82:6473597d706e 643 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
bogdanm 82:6473597d706e 644 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
bogdanm 82:6473597d706e 645 ((PRESCALER) == TIM_ICPSC_DIV2) || \
bogdanm 82:6473597d706e 646 ((PRESCALER) == TIM_ICPSC_DIV4) || \
bogdanm 82:6473597d706e 647 ((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm 82:6473597d706e 648 /**
bogdanm 82:6473597d706e 649 * @}
bogdanm 82:6473597d706e 650 */
bogdanm 82:6473597d706e 651
bogdanm 82:6473597d706e 652 /** @defgroup TIM_interrupt_sources
bogdanm 82:6473597d706e 653 * @{
bogdanm 82:6473597d706e 654 */
bogdanm 82:6473597d706e 655
bogdanm 82:6473597d706e 656 #define TIM_IT_Update ((uint16_t)0x0001)
bogdanm 82:6473597d706e 657 #define TIM_IT_CC1 ((uint16_t)0x0002)
bogdanm 82:6473597d706e 658 #define TIM_IT_CC2 ((uint16_t)0x0004)
bogdanm 82:6473597d706e 659 #define TIM_IT_CC3 ((uint16_t)0x0008)
bogdanm 82:6473597d706e 660 #define TIM_IT_CC4 ((uint16_t)0x0010)
bogdanm 82:6473597d706e 661 #define TIM_IT_COM ((uint16_t)0x0020)
bogdanm 82:6473597d706e 662 #define TIM_IT_Trigger ((uint16_t)0x0040)
bogdanm 82:6473597d706e 663 #define TIM_IT_Break ((uint16_t)0x0080)
bogdanm 82:6473597d706e 664 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
bogdanm 82:6473597d706e 665
bogdanm 82:6473597d706e 666 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
bogdanm 82:6473597d706e 667 ((IT) == TIM_IT_CC1) || \
bogdanm 82:6473597d706e 668 ((IT) == TIM_IT_CC2) || \
bogdanm 82:6473597d706e 669 ((IT) == TIM_IT_CC3) || \
bogdanm 82:6473597d706e 670 ((IT) == TIM_IT_CC4) || \
bogdanm 82:6473597d706e 671 ((IT) == TIM_IT_COM) || \
bogdanm 82:6473597d706e 672 ((IT) == TIM_IT_Trigger) || \
bogdanm 82:6473597d706e 673 ((IT) == TIM_IT_Break))
bogdanm 82:6473597d706e 674 /**
bogdanm 82:6473597d706e 675 * @}
bogdanm 82:6473597d706e 676 */
bogdanm 82:6473597d706e 677
bogdanm 82:6473597d706e 678 /** @defgroup TIM_DMA_Base_address
bogdanm 82:6473597d706e 679 * @{
bogdanm 82:6473597d706e 680 */
bogdanm 82:6473597d706e 681
bogdanm 82:6473597d706e 682 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
bogdanm 82:6473597d706e 683 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
bogdanm 82:6473597d706e 684 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
bogdanm 82:6473597d706e 685 #define TIM_DMABase_DIER ((uint16_t)0x0003)
bogdanm 82:6473597d706e 686 #define TIM_DMABase_SR ((uint16_t)0x0004)
bogdanm 82:6473597d706e 687 #define TIM_DMABase_EGR ((uint16_t)0x0005)
bogdanm 82:6473597d706e 688 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
bogdanm 82:6473597d706e 689 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
bogdanm 82:6473597d706e 690 #define TIM_DMABase_CCER ((uint16_t)0x0008)
bogdanm 82:6473597d706e 691 #define TIM_DMABase_CNT ((uint16_t)0x0009)
bogdanm 82:6473597d706e 692 #define TIM_DMABase_PSC ((uint16_t)0x000A)
bogdanm 82:6473597d706e 693 #define TIM_DMABase_ARR ((uint16_t)0x000B)
bogdanm 82:6473597d706e 694 #define TIM_DMABase_RCR ((uint16_t)0x000C)
bogdanm 82:6473597d706e 695 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
bogdanm 82:6473597d706e 696 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
bogdanm 82:6473597d706e 697 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
bogdanm 82:6473597d706e 698 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
bogdanm 82:6473597d706e 699 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
bogdanm 82:6473597d706e 700 #define TIM_DMABase_DCR ((uint16_t)0x0012)
bogdanm 82:6473597d706e 701 #define TIM_DMABase_OR ((uint16_t)0x0013)
bogdanm 82:6473597d706e 702 #define TIM_DMABase_CCMR3 ((uint16_t)0x0014)
bogdanm 82:6473597d706e 703 #define TIM_DMABase_CCR5 ((uint16_t)0x0015)
bogdanm 82:6473597d706e 704 #define TIM_DMABase_CCR6 ((uint16_t)0x0016)
bogdanm 82:6473597d706e 705 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
bogdanm 82:6473597d706e 706 ((BASE) == TIM_DMABase_CR2) || \
bogdanm 82:6473597d706e 707 ((BASE) == TIM_DMABase_SMCR) || \
bogdanm 82:6473597d706e 708 ((BASE) == TIM_DMABase_DIER) || \
bogdanm 82:6473597d706e 709 ((BASE) == TIM_DMABase_SR) || \
bogdanm 82:6473597d706e 710 ((BASE) == TIM_DMABase_EGR) || \
bogdanm 82:6473597d706e 711 ((BASE) == TIM_DMABase_CCMR1) || \
bogdanm 82:6473597d706e 712 ((BASE) == TIM_DMABase_CCMR2) || \
bogdanm 82:6473597d706e 713 ((BASE) == TIM_DMABase_CCER) || \
bogdanm 82:6473597d706e 714 ((BASE) == TIM_DMABase_CNT) || \
bogdanm 82:6473597d706e 715 ((BASE) == TIM_DMABase_PSC) || \
bogdanm 82:6473597d706e 716 ((BASE) == TIM_DMABase_ARR) || \
bogdanm 82:6473597d706e 717 ((BASE) == TIM_DMABase_RCR) || \
bogdanm 82:6473597d706e 718 ((BASE) == TIM_DMABase_CCR1) || \
bogdanm 82:6473597d706e 719 ((BASE) == TIM_DMABase_CCR2) || \
bogdanm 82:6473597d706e 720 ((BASE) == TIM_DMABase_CCR3) || \
bogdanm 82:6473597d706e 721 ((BASE) == TIM_DMABase_CCR4) || \
bogdanm 82:6473597d706e 722 ((BASE) == TIM_DMABase_BDTR) || \
bogdanm 82:6473597d706e 723 ((BASE) == TIM_DMABase_DCR) || \
bogdanm 82:6473597d706e 724 ((BASE) == TIM_DMABase_OR) || \
bogdanm 82:6473597d706e 725 ((BASE) == TIM_DMABase_CCMR3) || \
bogdanm 82:6473597d706e 726 ((BASE) == TIM_DMABase_CCR5) || \
bogdanm 82:6473597d706e 727 ((BASE) == TIM_DMABase_CCR6))
bogdanm 82:6473597d706e 728 /**
bogdanm 82:6473597d706e 729 * @}
bogdanm 82:6473597d706e 730 */
bogdanm 82:6473597d706e 731
bogdanm 82:6473597d706e 732 /** @defgroup TIM_DMA_Burst_Length
bogdanm 82:6473597d706e 733 * @{
bogdanm 82:6473597d706e 734 */
bogdanm 82:6473597d706e 735
bogdanm 82:6473597d706e 736 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
bogdanm 82:6473597d706e 737 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
bogdanm 82:6473597d706e 738 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
bogdanm 82:6473597d706e 739 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
bogdanm 82:6473597d706e 740 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
bogdanm 82:6473597d706e 741 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
bogdanm 82:6473597d706e 742 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
bogdanm 82:6473597d706e 743 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
bogdanm 82:6473597d706e 744 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
bogdanm 82:6473597d706e 745 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
bogdanm 82:6473597d706e 746 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
bogdanm 82:6473597d706e 747 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
bogdanm 82:6473597d706e 748 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
bogdanm 82:6473597d706e 749 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
bogdanm 82:6473597d706e 750 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
bogdanm 82:6473597d706e 751 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
bogdanm 82:6473597d706e 752 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
bogdanm 82:6473597d706e 753 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
bogdanm 82:6473597d706e 754 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
bogdanm 82:6473597d706e 755 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
bogdanm 82:6473597d706e 756 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
bogdanm 82:6473597d706e 757 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
bogdanm 82:6473597d706e 758 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
bogdanm 82:6473597d706e 759 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
bogdanm 82:6473597d706e 760 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
bogdanm 82:6473597d706e 761 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
bogdanm 82:6473597d706e 762 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
bogdanm 82:6473597d706e 763 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
bogdanm 82:6473597d706e 764 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
bogdanm 82:6473597d706e 765 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
bogdanm 82:6473597d706e 766 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
bogdanm 82:6473597d706e 767 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
bogdanm 82:6473597d706e 768 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
bogdanm 82:6473597d706e 769 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
bogdanm 82:6473597d706e 770 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
bogdanm 82:6473597d706e 771 ((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm 82:6473597d706e 772 /**
bogdanm 82:6473597d706e 773 * @}
bogdanm 82:6473597d706e 774 */
bogdanm 82:6473597d706e 775
bogdanm 82:6473597d706e 776 /** @defgroup TIM_DMA_sources
bogdanm 82:6473597d706e 777 * @{
bogdanm 82:6473597d706e 778 */
bogdanm 82:6473597d706e 779
bogdanm 82:6473597d706e 780 #define TIM_DMA_Update ((uint16_t)0x0100)
bogdanm 82:6473597d706e 781 #define TIM_DMA_CC1 ((uint16_t)0x0200)
bogdanm 82:6473597d706e 782 #define TIM_DMA_CC2 ((uint16_t)0x0400)
bogdanm 82:6473597d706e 783 #define TIM_DMA_CC3 ((uint16_t)0x0800)
bogdanm 82:6473597d706e 784 #define TIM_DMA_CC4 ((uint16_t)0x1000)
bogdanm 82:6473597d706e 785 #define TIM_DMA_COM ((uint16_t)0x2000)
bogdanm 82:6473597d706e 786 #define TIM_DMA_Trigger ((uint16_t)0x4000)
bogdanm 82:6473597d706e 787 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
bogdanm 82:6473597d706e 788
bogdanm 82:6473597d706e 789 /**
bogdanm 82:6473597d706e 790 * @}
bogdanm 82:6473597d706e 791 */
bogdanm 82:6473597d706e 792
bogdanm 82:6473597d706e 793 /** @defgroup TIM_External_Trigger_Prescaler
bogdanm 82:6473597d706e 794 * @{
bogdanm 82:6473597d706e 795 */
bogdanm 82:6473597d706e 796
bogdanm 82:6473597d706e 797 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
bogdanm 82:6473597d706e 798 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
bogdanm 82:6473597d706e 799 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
bogdanm 82:6473597d706e 800 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
bogdanm 82:6473597d706e 801 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
bogdanm 82:6473597d706e 802 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
bogdanm 82:6473597d706e 803 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
bogdanm 82:6473597d706e 804 ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
bogdanm 82:6473597d706e 805 /**
bogdanm 82:6473597d706e 806 * @}
bogdanm 82:6473597d706e 807 */
bogdanm 82:6473597d706e 808
bogdanm 82:6473597d706e 809 /** @defgroup TIM_Internal_Trigger_Selection
bogdanm 82:6473597d706e 810 * @{
bogdanm 82:6473597d706e 811 */
bogdanm 82:6473597d706e 812
bogdanm 82:6473597d706e 813 #define TIM_TS_ITR0 ((uint16_t)0x0000)
bogdanm 82:6473597d706e 814 #define TIM_TS_ITR1 ((uint16_t)0x0010)
bogdanm 82:6473597d706e 815 #define TIM_TS_ITR2 ((uint16_t)0x0020)
bogdanm 82:6473597d706e 816 #define TIM_TS_ITR3 ((uint16_t)0x0030)
bogdanm 82:6473597d706e 817 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
bogdanm 82:6473597d706e 818 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
bogdanm 82:6473597d706e 819 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
bogdanm 82:6473597d706e 820 #define TIM_TS_ETRF ((uint16_t)0x0070)
bogdanm 82:6473597d706e 821 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 82:6473597d706e 822 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 82:6473597d706e 823 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 82:6473597d706e 824 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 82:6473597d706e 825 ((SELECTION) == TIM_TS_TI1F_ED) || \
bogdanm 82:6473597d706e 826 ((SELECTION) == TIM_TS_TI1FP1) || \
bogdanm 82:6473597d706e 827 ((SELECTION) == TIM_TS_TI2FP2) || \
bogdanm 82:6473597d706e 828 ((SELECTION) == TIM_TS_ETRF))
bogdanm 82:6473597d706e 829 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 82:6473597d706e 830 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 82:6473597d706e 831 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 82:6473597d706e 832 ((SELECTION) == TIM_TS_ITR3))
bogdanm 82:6473597d706e 833 /**
bogdanm 82:6473597d706e 834 * @}
bogdanm 82:6473597d706e 835 */
bogdanm 82:6473597d706e 836
bogdanm 82:6473597d706e 837 /** @defgroup TIM_TIx_External_Clock_Source
bogdanm 82:6473597d706e 838 * @{
bogdanm 82:6473597d706e 839 */
bogdanm 82:6473597d706e 840
bogdanm 82:6473597d706e 841 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
bogdanm 82:6473597d706e 842 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
bogdanm 82:6473597d706e 843 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
bogdanm 82:6473597d706e 844
bogdanm 82:6473597d706e 845 /**
bogdanm 82:6473597d706e 846 * @}
bogdanm 82:6473597d706e 847 */
bogdanm 82:6473597d706e 848
bogdanm 82:6473597d706e 849 /** @defgroup TIM_External_Trigger_Polarity
bogdanm 82:6473597d706e 850 * @{
bogdanm 82:6473597d706e 851 */
bogdanm 82:6473597d706e 852 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
bogdanm 82:6473597d706e 853 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
bogdanm 82:6473597d706e 854 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
bogdanm 82:6473597d706e 855 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
bogdanm 82:6473597d706e 856 /**
bogdanm 82:6473597d706e 857 * @}
bogdanm 82:6473597d706e 858 */
bogdanm 82:6473597d706e 859
bogdanm 82:6473597d706e 860 /** @defgroup TIM_Prescaler_Reload_Mode
bogdanm 82:6473597d706e 861 * @{
bogdanm 82:6473597d706e 862 */
bogdanm 82:6473597d706e 863
bogdanm 82:6473597d706e 864 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
bogdanm 82:6473597d706e 865 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
bogdanm 82:6473597d706e 866 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
bogdanm 82:6473597d706e 867 ((RELOAD) == TIM_PSCReloadMode_Immediate))
bogdanm 82:6473597d706e 868 /**
bogdanm 82:6473597d706e 869 * @}
bogdanm 82:6473597d706e 870 */
bogdanm 82:6473597d706e 871
bogdanm 82:6473597d706e 872 /** @defgroup TIM_Forced_Action
bogdanm 82:6473597d706e 873 * @{
bogdanm 82:6473597d706e 874 */
bogdanm 82:6473597d706e 875
bogdanm 82:6473597d706e 876 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
bogdanm 82:6473597d706e 877 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
bogdanm 82:6473597d706e 878 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
bogdanm 82:6473597d706e 879 ((ACTION) == TIM_ForcedAction_InActive))
bogdanm 82:6473597d706e 880 /**
bogdanm 82:6473597d706e 881 * @}
bogdanm 82:6473597d706e 882 */
bogdanm 82:6473597d706e 883
bogdanm 82:6473597d706e 884 /** @defgroup TIM_Encoder_Mode
bogdanm 82:6473597d706e 885 * @{
bogdanm 82:6473597d706e 886 */
bogdanm 82:6473597d706e 887
bogdanm 82:6473597d706e 888 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
bogdanm 82:6473597d706e 889 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
bogdanm 82:6473597d706e 890 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
bogdanm 82:6473597d706e 891 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
bogdanm 82:6473597d706e 892 ((MODE) == TIM_EncoderMode_TI2) || \
bogdanm 82:6473597d706e 893 ((MODE) == TIM_EncoderMode_TI12))
bogdanm 82:6473597d706e 894 /**
bogdanm 82:6473597d706e 895 * @}
bogdanm 82:6473597d706e 896 */
bogdanm 82:6473597d706e 897
bogdanm 82:6473597d706e 898
bogdanm 82:6473597d706e 899 /** @defgroup TIM_Event_Source
bogdanm 82:6473597d706e 900 * @{
bogdanm 82:6473597d706e 901 */
bogdanm 82:6473597d706e 902
bogdanm 82:6473597d706e 903 #define TIM_EventSource_Update ((uint16_t)0x0001)
bogdanm 82:6473597d706e 904 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
bogdanm 82:6473597d706e 905 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
bogdanm 82:6473597d706e 906 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
bogdanm 82:6473597d706e 907 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
bogdanm 82:6473597d706e 908 #define TIM_EventSource_COM ((uint16_t)0x0020)
bogdanm 82:6473597d706e 909 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
bogdanm 82:6473597d706e 910 #define TIM_EventSource_Break ((uint16_t)0x0080)
bogdanm 82:6473597d706e 911 #define TIM_EventSource_Break2 ((uint16_t)0x0100)
bogdanm 82:6473597d706e 912 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000))
bogdanm 82:6473597d706e 913
bogdanm 82:6473597d706e 914 /**
bogdanm 82:6473597d706e 915 * @}
bogdanm 82:6473597d706e 916 */
bogdanm 82:6473597d706e 917
bogdanm 82:6473597d706e 918 /** @defgroup TIM_Update_Source
bogdanm 82:6473597d706e 919 * @{
bogdanm 82:6473597d706e 920 */
bogdanm 82:6473597d706e 921
bogdanm 82:6473597d706e 922 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
bogdanm 82:6473597d706e 923 or the setting of UG bit, or an update generation
bogdanm 82:6473597d706e 924 through the slave mode controller. */
bogdanm 82:6473597d706e 925 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
bogdanm 82:6473597d706e 926 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
bogdanm 82:6473597d706e 927 ((SOURCE) == TIM_UpdateSource_Regular))
bogdanm 82:6473597d706e 928 /**
bogdanm 82:6473597d706e 929 * @}
bogdanm 82:6473597d706e 930 */
bogdanm 82:6473597d706e 931
bogdanm 82:6473597d706e 932 /** @defgroup TIM_Output_Compare_Preload_State
bogdanm 82:6473597d706e 933 * @{
bogdanm 82:6473597d706e 934 */
bogdanm 82:6473597d706e 935
bogdanm 82:6473597d706e 936 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
bogdanm 82:6473597d706e 937 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 938 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
bogdanm 82:6473597d706e 939 ((STATE) == TIM_OCPreload_Disable))
bogdanm 82:6473597d706e 940 /**
bogdanm 82:6473597d706e 941 * @}
bogdanm 82:6473597d706e 942 */
bogdanm 82:6473597d706e 943
bogdanm 82:6473597d706e 944 /** @defgroup TIM_Output_Compare_Fast_State
bogdanm 82:6473597d706e 945 * @{
bogdanm 82:6473597d706e 946 */
bogdanm 82:6473597d706e 947
bogdanm 82:6473597d706e 948 #define TIM_OCFast_Enable ((uint16_t)0x0004)
bogdanm 82:6473597d706e 949 #define TIM_OCFast_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 950 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
bogdanm 82:6473597d706e 951 ((STATE) == TIM_OCFast_Disable))
bogdanm 82:6473597d706e 952
bogdanm 82:6473597d706e 953 /**
bogdanm 82:6473597d706e 954 * @}
bogdanm 82:6473597d706e 955 */
bogdanm 82:6473597d706e 956
bogdanm 82:6473597d706e 957 /** @defgroup TIM_Output_Compare_Clear_State
bogdanm 82:6473597d706e 958 * @{
bogdanm 82:6473597d706e 959 */
bogdanm 82:6473597d706e 960
bogdanm 82:6473597d706e 961 #define TIM_OCClear_Enable ((uint16_t)0x0080)
bogdanm 82:6473597d706e 962 #define TIM_OCClear_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 963 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
bogdanm 82:6473597d706e 964 ((STATE) == TIM_OCClear_Disable))
bogdanm 82:6473597d706e 965 /**
bogdanm 82:6473597d706e 966 * @}
bogdanm 82:6473597d706e 967 */
bogdanm 82:6473597d706e 968
bogdanm 82:6473597d706e 969 /** @defgroup TIM_Trigger_Output_Source
bogdanm 82:6473597d706e 970 * @{
bogdanm 82:6473597d706e 971 */
bogdanm 82:6473597d706e 972
bogdanm 82:6473597d706e 973 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
bogdanm 82:6473597d706e 974 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
bogdanm 82:6473597d706e 975 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
bogdanm 82:6473597d706e 976 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
bogdanm 82:6473597d706e 977 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
bogdanm 82:6473597d706e 978 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
bogdanm 82:6473597d706e 979 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
bogdanm 82:6473597d706e 980 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
bogdanm 82:6473597d706e 981 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
bogdanm 82:6473597d706e 982 ((SOURCE) == TIM_TRGOSource_Enable) || \
bogdanm 82:6473597d706e 983 ((SOURCE) == TIM_TRGOSource_Update) || \
bogdanm 82:6473597d706e 984 ((SOURCE) == TIM_TRGOSource_OC1) || \
bogdanm 82:6473597d706e 985 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
bogdanm 82:6473597d706e 986 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
bogdanm 82:6473597d706e 987 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
bogdanm 82:6473597d706e 988 ((SOURCE) == TIM_TRGOSource_OC4Ref))
bogdanm 82:6473597d706e 989
bogdanm 82:6473597d706e 990
bogdanm 82:6473597d706e 991 #define TIM_TRGO2Source_Reset ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 992 #define TIM_TRGO2Source_Enable ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 993 #define TIM_TRGO2Source_Update ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 994 #define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000)
bogdanm 82:6473597d706e 995 #define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 996 #define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000)
bogdanm 82:6473597d706e 997 #define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000)
bogdanm 82:6473597d706e 998 #define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000)
bogdanm 82:6473597d706e 999 #define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 1000 #define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000)
bogdanm 82:6473597d706e 1001 #define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000)
bogdanm 82:6473597d706e 1002 #define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000)
bogdanm 82:6473597d706e 1003 #define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000)
bogdanm 82:6473597d706e 1004 #define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000)
bogdanm 82:6473597d706e 1005 #define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000)
bogdanm 82:6473597d706e 1006 #define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000)
bogdanm 82:6473597d706e 1007 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \
bogdanm 82:6473597d706e 1008 ((SOURCE) == TIM_TRGO2Source_Enable) || \
bogdanm 82:6473597d706e 1009 ((SOURCE) == TIM_TRGO2Source_Update) || \
bogdanm 82:6473597d706e 1010 ((SOURCE) == TIM_TRGO2Source_OC1) || \
bogdanm 82:6473597d706e 1011 ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \
bogdanm 82:6473597d706e 1012 ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \
bogdanm 82:6473597d706e 1013 ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \
bogdanm 82:6473597d706e 1014 ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \
bogdanm 82:6473597d706e 1015 ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \
bogdanm 82:6473597d706e 1016 ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \
bogdanm 82:6473597d706e 1017 ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \
bogdanm 82:6473597d706e 1018 ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \
bogdanm 82:6473597d706e 1019 ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \
bogdanm 82:6473597d706e 1020 ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \
bogdanm 82:6473597d706e 1021 ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \
bogdanm 82:6473597d706e 1022 ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling))
bogdanm 82:6473597d706e 1023 /**
bogdanm 82:6473597d706e 1024 * @}
bogdanm 82:6473597d706e 1025 */
bogdanm 82:6473597d706e 1026
bogdanm 82:6473597d706e 1027 /** @defgroup TIM_Slave_Mode
bogdanm 82:6473597d706e 1028 * @{
bogdanm 82:6473597d706e 1029 */
bogdanm 82:6473597d706e 1030
bogdanm 82:6473597d706e 1031 #define TIM_SlaveMode_Reset ((uint32_t)0x00004)
bogdanm 82:6473597d706e 1032 #define TIM_SlaveMode_Gated ((uint32_t)0x00005)
bogdanm 82:6473597d706e 1033 #define TIM_SlaveMode_Trigger ((uint32_t)0x00006)
bogdanm 82:6473597d706e 1034 #define TIM_SlaveMode_External1 ((uint32_t)0x00007)
bogdanm 82:6473597d706e 1035 #define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000)
bogdanm 82:6473597d706e 1036 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
bogdanm 82:6473597d706e 1037 ((MODE) == TIM_SlaveMode_Gated) || \
bogdanm 82:6473597d706e 1038 ((MODE) == TIM_SlaveMode_Trigger) || \
bogdanm 82:6473597d706e 1039 ((MODE) == TIM_SlaveMode_External1) || \
bogdanm 82:6473597d706e 1040 ((MODE) == TIM_SlaveMode_Combined_ResetTrigger))
bogdanm 82:6473597d706e 1041 /**
bogdanm 82:6473597d706e 1042 * @}
bogdanm 82:6473597d706e 1043 */
bogdanm 82:6473597d706e 1044
bogdanm 82:6473597d706e 1045 /** @defgroup TIM_Master_Slave_Mode
bogdanm 82:6473597d706e 1046 * @{
bogdanm 82:6473597d706e 1047 */
bogdanm 82:6473597d706e 1048
bogdanm 82:6473597d706e 1049 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
bogdanm 82:6473597d706e 1050 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
bogdanm 82:6473597d706e 1051 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
bogdanm 82:6473597d706e 1052 ((STATE) == TIM_MasterSlaveMode_Disable))
bogdanm 82:6473597d706e 1053 /**
bogdanm 82:6473597d706e 1054 * @}
bogdanm 82:6473597d706e 1055 */
bogdanm 82:6473597d706e 1056 /** @defgroup TIM_Remap
bogdanm 82:6473597d706e 1057 * @{
bogdanm 82:6473597d706e 1058 */
bogdanm 82:6473597d706e 1059 #define TIM16_GPIO ((uint16_t)0x0000)
bogdanm 82:6473597d706e 1060 #define TIM16_RTC_CLK ((uint16_t)0x0001)
bogdanm 82:6473597d706e 1061 #define TIM16_HSEDiv32 ((uint16_t)0x0002)
bogdanm 82:6473597d706e 1062 #define TIM16_MCO ((uint16_t)0x0003)
bogdanm 82:6473597d706e 1063
bogdanm 82:6473597d706e 1064 #define TIM1_ADC1_AWDG1 ((uint16_t)0x0001)
bogdanm 82:6473597d706e 1065 #define TIM1_ADC1_AWDG2 ((uint16_t)0x0002)
bogdanm 82:6473597d706e 1066 #define TIM1_ADC1_AWDG3 ((uint16_t)0x0003)
bogdanm 82:6473597d706e 1067 #define TIM1_ADC4_AWDG1 ((uint16_t)0x0004)
bogdanm 82:6473597d706e 1068 #define TIM1_ADC4_AWDG2 ((uint16_t)0x0008)
bogdanm 82:6473597d706e 1069 #define TIM1_ADC4_AWDG3 ((uint16_t)0x000C)
bogdanm 82:6473597d706e 1070
bogdanm 82:6473597d706e 1071 #define TIM8_ADC2_AWDG1 ((uint16_t)0x0001)
bogdanm 82:6473597d706e 1072 #define TIM8_ADC2_AWDG2 ((uint16_t)0x0002)
bogdanm 82:6473597d706e 1073 #define TIM8_ADC2_AWDG3 ((uint16_t)0x0003)
bogdanm 82:6473597d706e 1074 #define TIM8_ADC3_AWDG1 ((uint16_t)0x0004)
bogdanm 82:6473597d706e 1075 #define TIM8_ADC3_AWDG2 ((uint16_t)0x0008)
bogdanm 82:6473597d706e 1076 #define TIM8_ADC3_AWDG3 ((uint16_t)0x000C)
bogdanm 82:6473597d706e 1077
bogdanm 82:6473597d706e 1078 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)|| \
bogdanm 82:6473597d706e 1079 ((TIM_REMAP) == TIM16_RTC_CLK) || \
bogdanm 82:6473597d706e 1080 ((TIM_REMAP) == TIM16_HSEDiv32) || \
bogdanm 82:6473597d706e 1081 ((TIM_REMAP) == TIM16_MCO) ||\
bogdanm 82:6473597d706e 1082 ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\
bogdanm 82:6473597d706e 1083 ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\
bogdanm 82:6473597d706e 1084 ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\
bogdanm 82:6473597d706e 1085 ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\
bogdanm 82:6473597d706e 1086 ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\
bogdanm 82:6473597d706e 1087 ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\
bogdanm 82:6473597d706e 1088 ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\
bogdanm 82:6473597d706e 1089 ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\
bogdanm 82:6473597d706e 1090 ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\
bogdanm 82:6473597d706e 1091 ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\
bogdanm 82:6473597d706e 1092 ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\
bogdanm 82:6473597d706e 1093 ((TIM_REMAP) == TIM8_ADC3_AWDG3))
bogdanm 82:6473597d706e 1094
bogdanm 82:6473597d706e 1095 /**
bogdanm 82:6473597d706e 1096 * @}
bogdanm 82:6473597d706e 1097 */
bogdanm 82:6473597d706e 1098 /** @defgroup TIM_Flags
bogdanm 82:6473597d706e 1099 * @{
bogdanm 82:6473597d706e 1100 */
bogdanm 82:6473597d706e 1101
bogdanm 82:6473597d706e 1102 #define TIM_FLAG_Update ((uint32_t)0x00001)
bogdanm 82:6473597d706e 1103 #define TIM_FLAG_CC1 ((uint32_t)0x00002)
bogdanm 82:6473597d706e 1104 #define TIM_FLAG_CC2 ((uint32_t)0x00004)
bogdanm 82:6473597d706e 1105 #define TIM_FLAG_CC3 ((uint32_t)0x00008)
bogdanm 82:6473597d706e 1106 #define TIM_FLAG_CC4 ((uint32_t)0x00010)
bogdanm 82:6473597d706e 1107 #define TIM_FLAG_COM ((uint32_t)0x00020)
bogdanm 82:6473597d706e 1108 #define TIM_FLAG_Trigger ((uint32_t)0x00040)
bogdanm 82:6473597d706e 1109 #define TIM_FLAG_Break ((uint32_t)0x00080)
bogdanm 82:6473597d706e 1110 #define TIM_FLAG_Break2 ((uint32_t)0x00100)
bogdanm 82:6473597d706e 1111 #define TIM_FLAG_CC1OF ((uint32_t)0x00200)
bogdanm 82:6473597d706e 1112 #define TIM_FLAG_CC2OF ((uint32_t)0x00400)
bogdanm 82:6473597d706e 1113 #define TIM_FLAG_CC3OF ((uint32_t)0x00800)
bogdanm 82:6473597d706e 1114 #define TIM_FLAG_CC4OF ((uint32_t)0x01000)
bogdanm 82:6473597d706e 1115 #define TIM_FLAG_CC5 ((uint32_t)0x10000)
bogdanm 82:6473597d706e 1116 #define TIM_FLAG_CC6 ((uint32_t)0x20000)
bogdanm 82:6473597d706e 1117 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
bogdanm 82:6473597d706e 1118 ((FLAG) == TIM_FLAG_CC1) || \
bogdanm 82:6473597d706e 1119 ((FLAG) == TIM_FLAG_CC2) || \
bogdanm 82:6473597d706e 1120 ((FLAG) == TIM_FLAG_CC3) || \
bogdanm 82:6473597d706e 1121 ((FLAG) == TIM_FLAG_CC4) || \
bogdanm 82:6473597d706e 1122 ((FLAG) == TIM_FLAG_COM) || \
bogdanm 82:6473597d706e 1123 ((FLAG) == TIM_FLAG_Trigger) || \
bogdanm 82:6473597d706e 1124 ((FLAG) == TIM_FLAG_Break) || \
bogdanm 82:6473597d706e 1125 ((FLAG) == TIM_FLAG_Break2) || \
bogdanm 82:6473597d706e 1126 ((FLAG) == TIM_FLAG_CC1OF) || \
bogdanm 82:6473597d706e 1127 ((FLAG) == TIM_FLAG_CC2OF) || \
bogdanm 82:6473597d706e 1128 ((FLAG) == TIM_FLAG_CC3OF) || \
bogdanm 82:6473597d706e 1129 ((FLAG) == TIM_FLAG_CC4OF) ||\
bogdanm 82:6473597d706e 1130 ((FLAG) == TIM_FLAG_CC5) ||\
bogdanm 82:6473597d706e 1131 ((FLAG) == TIM_FLAG_CC6))
bogdanm 82:6473597d706e 1132
bogdanm 82:6473597d706e 1133 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000))
bogdanm 82:6473597d706e 1134 /**
bogdanm 82:6473597d706e 1135 * @}
bogdanm 82:6473597d706e 1136 */
bogdanm 82:6473597d706e 1137
bogdanm 82:6473597d706e 1138 /** @defgroup TIM_OCReferenceClear
bogdanm 82:6473597d706e 1139 * @{
bogdanm 82:6473597d706e 1140 */
bogdanm 82:6473597d706e 1141 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
bogdanm 82:6473597d706e 1142 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
bogdanm 82:6473597d706e 1143 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
bogdanm 82:6473597d706e 1144 ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
bogdanm 82:6473597d706e 1145
bogdanm 82:6473597d706e 1146 /** @defgroup TIM_Input_Capture_Filer_Value
bogdanm 82:6473597d706e 1147 * @{
bogdanm 82:6473597d706e 1148 */
bogdanm 82:6473597d706e 1149
bogdanm 82:6473597d706e 1150 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 82:6473597d706e 1151 /**
bogdanm 82:6473597d706e 1152 * @}
bogdanm 82:6473597d706e 1153 */
bogdanm 82:6473597d706e 1154
bogdanm 82:6473597d706e 1155 /** @defgroup TIM_External_Trigger_Filter
bogdanm 82:6473597d706e 1156 * @{
bogdanm 82:6473597d706e 1157 */
bogdanm 82:6473597d706e 1158
bogdanm 82:6473597d706e 1159 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
bogdanm 82:6473597d706e 1160 /**
bogdanm 82:6473597d706e 1161 * @}
bogdanm 82:6473597d706e 1162 */
bogdanm 82:6473597d706e 1163
bogdanm 82:6473597d706e 1164 /** @defgroup TIM_Legacy
bogdanm 82:6473597d706e 1165 * @{
bogdanm 82:6473597d706e 1166 */
bogdanm 82:6473597d706e 1167
bogdanm 82:6473597d706e 1168 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
bogdanm 82:6473597d706e 1169 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
bogdanm 82:6473597d706e 1170 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
bogdanm 82:6473597d706e 1171 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
bogdanm 82:6473597d706e 1172 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
bogdanm 82:6473597d706e 1173 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
bogdanm 82:6473597d706e 1174 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
bogdanm 82:6473597d706e 1175 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
bogdanm 82:6473597d706e 1176 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
bogdanm 82:6473597d706e 1177 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
bogdanm 82:6473597d706e 1178 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
bogdanm 82:6473597d706e 1179 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
bogdanm 82:6473597d706e 1180 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
bogdanm 82:6473597d706e 1181 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
bogdanm 82:6473597d706e 1182 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
bogdanm 82:6473597d706e 1183 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
bogdanm 82:6473597d706e 1184 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
bogdanm 82:6473597d706e 1185 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
bogdanm 82:6473597d706e 1186 /**
bogdanm 82:6473597d706e 1187 * @}
bogdanm 82:6473597d706e 1188 */
bogdanm 82:6473597d706e 1189
bogdanm 82:6473597d706e 1190 /**
bogdanm 82:6473597d706e 1191 * @}
bogdanm 82:6473597d706e 1192 */
bogdanm 82:6473597d706e 1193
bogdanm 82:6473597d706e 1194 /* Exported macro ------------------------------------------------------------*/
bogdanm 82:6473597d706e 1195 /* Exported functions --------------------------------------------------------*/
bogdanm 82:6473597d706e 1196
bogdanm 82:6473597d706e 1197 /* TimeBase management ********************************************************/
bogdanm 82:6473597d706e 1198 void TIM_DeInit(TIM_TypeDef* TIMx);
bogdanm 82:6473597d706e 1199 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
bogdanm 82:6473597d706e 1200 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
bogdanm 82:6473597d706e 1201 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
bogdanm 82:6473597d706e 1202 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
bogdanm 82:6473597d706e 1203 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
bogdanm 82:6473597d706e 1204 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
bogdanm 82:6473597d706e 1205 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
bogdanm 82:6473597d706e 1206 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
bogdanm 82:6473597d706e 1207 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1208 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
bogdanm 82:6473597d706e 1209 void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1210 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1211 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
bogdanm 82:6473597d706e 1212 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
bogdanm 82:6473597d706e 1213 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1214
bogdanm 82:6473597d706e 1215 /* Output Compare management **************************************************/
bogdanm 82:6473597d706e 1216 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm 82:6473597d706e 1217 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm 82:6473597d706e 1218 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm 82:6473597d706e 1219 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm 82:6473597d706e 1220 void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm 82:6473597d706e 1221 void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm 82:6473597d706e 1222 void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1223 void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1224 void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1225 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm 82:6473597d706e 1226 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode);
bogdanm 82:6473597d706e 1227 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
bogdanm 82:6473597d706e 1228 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
bogdanm 82:6473597d706e 1229 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
bogdanm 82:6473597d706e 1230 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
bogdanm 82:6473597d706e 1231 void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5);
bogdanm 82:6473597d706e 1232 void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6);
bogdanm 82:6473597d706e 1233 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm 82:6473597d706e 1234 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm 82:6473597d706e 1235 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm 82:6473597d706e 1236 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm 82:6473597d706e 1237 void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm 82:6473597d706e 1238 void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm 82:6473597d706e 1239 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm 82:6473597d706e 1240 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm 82:6473597d706e 1241 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm 82:6473597d706e 1242 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm 82:6473597d706e 1243 void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm 82:6473597d706e 1244 void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm 82:6473597d706e 1245 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm 82:6473597d706e 1246 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm 82:6473597d706e 1247 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm 82:6473597d706e 1248 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm 82:6473597d706e 1249 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm 82:6473597d706e 1250 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm 82:6473597d706e 1251 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm 82:6473597d706e 1252 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm 82:6473597d706e 1253 void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm 82:6473597d706e 1254 void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm 82:6473597d706e 1255 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
bogdanm 82:6473597d706e 1256 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm 82:6473597d706e 1257 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm 82:6473597d706e 1258 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm 82:6473597d706e 1259 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm 82:6473597d706e 1260 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm 82:6473597d706e 1261 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm 82:6473597d706e 1262 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm 82:6473597d706e 1263 void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm 82:6473597d706e 1264 void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm 82:6473597d706e 1265 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
bogdanm 82:6473597d706e 1266 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
bogdanm 82:6473597d706e 1267
bogdanm 82:6473597d706e 1268 /* Input Capture management ***************************************************/
bogdanm 82:6473597d706e 1269 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm 82:6473597d706e 1270 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm 82:6473597d706e 1271 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm 82:6473597d706e 1272 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
bogdanm 82:6473597d706e 1273 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
bogdanm 82:6473597d706e 1274 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
bogdanm 82:6473597d706e 1275 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
bogdanm 82:6473597d706e 1276 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm 82:6473597d706e 1277 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm 82:6473597d706e 1278 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm 82:6473597d706e 1279 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm 82:6473597d706e 1280
bogdanm 82:6473597d706e 1281 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/
bogdanm 82:6473597d706e 1282 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
bogdanm 82:6473597d706e 1283 void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter);
bogdanm 82:6473597d706e 1284 void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter);
bogdanm 82:6473597d706e 1285 void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1286 void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1287 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
bogdanm 82:6473597d706e 1288 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1289 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1290 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1291
bogdanm 82:6473597d706e 1292 /* Interrupts, DMA and flags management ***************************************/
bogdanm 82:6473597d706e 1293 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
bogdanm 82:6473597d706e 1294 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
bogdanm 82:6473597d706e 1295 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG);
bogdanm 82:6473597d706e 1296 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
bogdanm 82:6473597d706e 1297 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
bogdanm 82:6473597d706e 1298 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
bogdanm 82:6473597d706e 1299 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
bogdanm 82:6473597d706e 1300 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
bogdanm 82:6473597d706e 1301 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1302
bogdanm 82:6473597d706e 1303 /* Clocks management **********************************************************/
bogdanm 82:6473597d706e 1304 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
bogdanm 82:6473597d706e 1305 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
bogdanm 82:6473597d706e 1306 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
bogdanm 82:6473597d706e 1307 uint16_t TIM_ICPolarity, uint16_t ICFilter);
bogdanm 82:6473597d706e 1308 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
bogdanm 82:6473597d706e 1309 uint16_t ExtTRGFilter);
bogdanm 82:6473597d706e 1310 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
bogdanm 82:6473597d706e 1311 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
bogdanm 82:6473597d706e 1312
bogdanm 82:6473597d706e 1313 /* Synchronization management *************************************************/
bogdanm 82:6473597d706e 1314 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
bogdanm 82:6473597d706e 1315 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
bogdanm 82:6473597d706e 1316 void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source);
bogdanm 82:6473597d706e 1317 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode);
bogdanm 82:6473597d706e 1318 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
bogdanm 82:6473597d706e 1319 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
bogdanm 82:6473597d706e 1320 uint16_t ExtTRGFilter);
bogdanm 82:6473597d706e 1321
bogdanm 82:6473597d706e 1322 /* Specific interface management **********************************************/
bogdanm 82:6473597d706e 1323 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
bogdanm 82:6473597d706e 1324 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
bogdanm 82:6473597d706e 1325 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm 82:6473597d706e 1326
bogdanm 82:6473597d706e 1327 /* Specific remapping management **********************************************/
bogdanm 82:6473597d706e 1328 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
bogdanm 82:6473597d706e 1329
bogdanm 82:6473597d706e 1330 #ifdef __cplusplus
bogdanm 82:6473597d706e 1331 }
bogdanm 82:6473597d706e 1332 #endif
bogdanm 82:6473597d706e 1333
bogdanm 82:6473597d706e 1334 #endif /*__STM32F30x_TIM_H */
bogdanm 82:6473597d706e 1335
bogdanm 82:6473597d706e 1336 /**
bogdanm 82:6473597d706e 1337 * @}
bogdanm 82:6473597d706e 1338 */
bogdanm 82:6473597d706e 1339
bogdanm 82:6473597d706e 1340 /**
bogdanm 82:6473597d706e 1341 * @}
bogdanm 82:6473597d706e 1342 */
bogdanm 82:6473597d706e 1343
bogdanm 82:6473597d706e 1344 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/