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TARGET_NUCLEO_F302R8/stm32f30x_dma.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
Parent:
82:6473597d706e 
version_2.0

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bogdanm 82:6473597d706e 1 /**
bogdanm 82:6473597d706e 2 ******************************************************************************
bogdanm 82:6473597d706e 3 * @file stm32f30x_dma.h
bogdanm 82:6473597d706e 4 * @author MCD Application Team
bogdanm 82:6473597d706e 5 * @version V1.1.0
bogdanm 82:6473597d706e 6 * @date 27-February-2014
bogdanm 82:6473597d706e 7 * @brief This file contains all the functions prototypes for the DMA firmware
bogdanm 82:6473597d706e 8 * library.
bogdanm 82:6473597d706e 9 ******************************************************************************
bogdanm 82:6473597d706e 10 * @attention
bogdanm 82:6473597d706e 11 *
bogdanm 82:6473597d706e 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 82:6473597d706e 13 *
bogdanm 82:6473597d706e 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 15 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 82:6473597d706e 17 * this list of conditions and the following disclaimer.
bogdanm 82:6473597d706e 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 82:6473597d706e 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 82:6473597d706e 20 * and/or other materials provided with the distribution.
bogdanm 82:6473597d706e 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 82:6473597d706e 22 * may be used to endorse or promote products derived from this software
bogdanm 82:6473597d706e 23 * without specific prior written permission.
bogdanm 82:6473597d706e 24 *
bogdanm 82:6473597d706e 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 82:6473597d706e 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 82:6473597d706e 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 82:6473597d706e 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 82:6473597d706e 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 82:6473597d706e 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 82:6473597d706e 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 82:6473597d706e 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 82:6473597d706e 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 35 *
bogdanm 82:6473597d706e 36 ******************************************************************************
bogdanm 82:6473597d706e 37 */
bogdanm 82:6473597d706e 38
bogdanm 82:6473597d706e 39 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 82:6473597d706e 40 #ifndef __STM32F30x_DMA_H
bogdanm 82:6473597d706e 41 #define __STM32F30x_DMA_H
bogdanm 82:6473597d706e 42
bogdanm 82:6473597d706e 43 #ifdef __cplusplus
bogdanm 82:6473597d706e 44 extern "C" {
bogdanm 82:6473597d706e 45 #endif
bogdanm 82:6473597d706e 46
bogdanm 82:6473597d706e 47 /* Includes ------------------------------------------------------------------*/
bogdanm 82:6473597d706e 48 #include "stm32f30x.h"
bogdanm 82:6473597d706e 49
bogdanm 82:6473597d706e 50 /** @addtogroup STM32F30x_StdPeriph_Driver
bogdanm 82:6473597d706e 51 * @{
bogdanm 82:6473597d706e 52 */
bogdanm 82:6473597d706e 53
bogdanm 82:6473597d706e 54 /** @addtogroup DMA
bogdanm 82:6473597d706e 55 * @{
bogdanm 82:6473597d706e 56 */
bogdanm 82:6473597d706e 57
bogdanm 82:6473597d706e 58 /* Exported types ------------------------------------------------------------*/
bogdanm 82:6473597d706e 59
bogdanm 82:6473597d706e 60 /**
bogdanm 82:6473597d706e 61 * @brief DMA Init structures definition
bogdanm 82:6473597d706e 62 */
bogdanm 82:6473597d706e 63 typedef struct
bogdanm 82:6473597d706e 64 {
bogdanm 82:6473597d706e 65 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
bogdanm 82:6473597d706e 66
bogdanm 82:6473597d706e 67 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
bogdanm 82:6473597d706e 68
bogdanm 82:6473597d706e 69 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
bogdanm 82:6473597d706e 70 This parameter can be a value of @ref DMA_data_transfer_direction */
bogdanm 82:6473597d706e 71
bogdanm 82:6473597d706e 72 uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
bogdanm 82:6473597d706e 73 The data unit is equal to the configuration set in DMA_PeripheralDataSize
bogdanm 82:6473597d706e 74 or DMA_MemoryDataSize members depending in the transfer direction. */
bogdanm 82:6473597d706e 75
bogdanm 82:6473597d706e 76 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
bogdanm 82:6473597d706e 77 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
bogdanm 82:6473597d706e 78
bogdanm 82:6473597d706e 79 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
bogdanm 82:6473597d706e 80 This parameter can be a value of @ref DMA_memory_incremented_mode */
bogdanm 82:6473597d706e 81
bogdanm 82:6473597d706e 82 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
bogdanm 82:6473597d706e 83 This parameter can be a value of @ref DMA_peripheral_data_size */
bogdanm 82:6473597d706e 84
bogdanm 82:6473597d706e 85 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
bogdanm 82:6473597d706e 86 This parameter can be a value of @ref DMA_memory_data_size */
bogdanm 82:6473597d706e 87
bogdanm 82:6473597d706e 88 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 82:6473597d706e 89 This parameter can be a value of @ref DMA_circular_normal_mode
bogdanm 82:6473597d706e 90 @note: The circular buffer mode cannot be used if the memory-to-memory
bogdanm 82:6473597d706e 91 data transfer is configured on the selected Channel */
bogdanm 82:6473597d706e 92
bogdanm 82:6473597d706e 93 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 82:6473597d706e 94 This parameter can be a value of @ref DMA_priority_level */
bogdanm 82:6473597d706e 95
bogdanm 82:6473597d706e 96 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
bogdanm 82:6473597d706e 97 This parameter can be a value of @ref DMA_memory_to_memory */
bogdanm 82:6473597d706e 98 }DMA_InitTypeDef;
bogdanm 82:6473597d706e 99
bogdanm 82:6473597d706e 100 /* Exported constants --------------------------------------------------------*/
bogdanm 82:6473597d706e 101
bogdanm 82:6473597d706e 102 /** @defgroup DMA_Exported_Constants
bogdanm 82:6473597d706e 103 * @{
bogdanm 82:6473597d706e 104 */
bogdanm 82:6473597d706e 105
bogdanm 82:6473597d706e 106 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
bogdanm 82:6473597d706e 107 ((PERIPH) == DMA1_Channel2) || \
bogdanm 82:6473597d706e 108 ((PERIPH) == DMA1_Channel3) || \
bogdanm 82:6473597d706e 109 ((PERIPH) == DMA1_Channel4) || \
bogdanm 82:6473597d706e 110 ((PERIPH) == DMA1_Channel5) || \
bogdanm 82:6473597d706e 111 ((PERIPH) == DMA1_Channel6) || \
bogdanm 82:6473597d706e 112 ((PERIPH) == DMA1_Channel7) || \
bogdanm 82:6473597d706e 113 ((PERIPH) == DMA2_Channel1) || \
bogdanm 82:6473597d706e 114 ((PERIPH) == DMA2_Channel2) || \
bogdanm 82:6473597d706e 115 ((PERIPH) == DMA2_Channel3) || \
bogdanm 82:6473597d706e 116 ((PERIPH) == DMA2_Channel4) || \
bogdanm 82:6473597d706e 117 ((PERIPH) == DMA2_Channel5))
bogdanm 82:6473597d706e 118
bogdanm 82:6473597d706e 119 /** @defgroup DMA_data_transfer_direction
bogdanm 82:6473597d706e 120 * @{
bogdanm 82:6473597d706e 121 */
bogdanm 82:6473597d706e 122
bogdanm 82:6473597d706e 123 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 124 #define DMA_DIR_PeripheralDST DMA_CCR_DIR
bogdanm 82:6473597d706e 125
bogdanm 82:6473597d706e 126 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
bogdanm 82:6473597d706e 127 ((DIR) == DMA_DIR_PeripheralDST))
bogdanm 82:6473597d706e 128 /**
bogdanm 82:6473597d706e 129 * @}
bogdanm 82:6473597d706e 130 */
bogdanm 82:6473597d706e 131
bogdanm 82:6473597d706e 132
bogdanm 82:6473597d706e 133 /** @defgroup DMA_peripheral_incremented_mode
bogdanm 82:6473597d706e 134 * @{
bogdanm 82:6473597d706e 135 */
bogdanm 82:6473597d706e 136
bogdanm 82:6473597d706e 137 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 138 #define DMA_PeripheralInc_Enable DMA_CCR_PINC
bogdanm 82:6473597d706e 139
bogdanm 82:6473597d706e 140 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
bogdanm 82:6473597d706e 141 ((STATE) == DMA_PeripheralInc_Enable))
bogdanm 82:6473597d706e 142 /**
bogdanm 82:6473597d706e 143 * @}
bogdanm 82:6473597d706e 144 */
bogdanm 82:6473597d706e 145
bogdanm 82:6473597d706e 146 /** @defgroup DMA_memory_incremented_mode
bogdanm 82:6473597d706e 147 * @{
bogdanm 82:6473597d706e 148 */
bogdanm 82:6473597d706e 149
bogdanm 82:6473597d706e 150 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 151 #define DMA_MemoryInc_Enable DMA_CCR_MINC
bogdanm 82:6473597d706e 152
bogdanm 82:6473597d706e 153 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
bogdanm 82:6473597d706e 154 ((STATE) == DMA_MemoryInc_Enable))
bogdanm 82:6473597d706e 155 /**
bogdanm 82:6473597d706e 156 * @}
bogdanm 82:6473597d706e 157 */
bogdanm 82:6473597d706e 158
bogdanm 82:6473597d706e 159 /** @defgroup DMA_peripheral_data_size
bogdanm 82:6473597d706e 160 * @{
bogdanm 82:6473597d706e 161 */
bogdanm 82:6473597d706e 162
bogdanm 82:6473597d706e 163 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 164 #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
bogdanm 82:6473597d706e 165 #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
bogdanm 82:6473597d706e 166
bogdanm 82:6473597d706e 167 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
bogdanm 82:6473597d706e 168 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
bogdanm 82:6473597d706e 169 ((SIZE) == DMA_PeripheralDataSize_Word))
bogdanm 82:6473597d706e 170 /**
bogdanm 82:6473597d706e 171 * @}
bogdanm 82:6473597d706e 172 */
bogdanm 82:6473597d706e 173
bogdanm 82:6473597d706e 174 /** @defgroup DMA_memory_data_size
bogdanm 82:6473597d706e 175 * @{
bogdanm 82:6473597d706e 176 */
bogdanm 82:6473597d706e 177
bogdanm 82:6473597d706e 178 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 179 #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
bogdanm 82:6473597d706e 180 #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
bogdanm 82:6473597d706e 181
bogdanm 82:6473597d706e 182 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
bogdanm 82:6473597d706e 183 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
bogdanm 82:6473597d706e 184 ((SIZE) == DMA_MemoryDataSize_Word))
bogdanm 82:6473597d706e 185 /**
bogdanm 82:6473597d706e 186 * @}
bogdanm 82:6473597d706e 187 */
bogdanm 82:6473597d706e 188
bogdanm 82:6473597d706e 189 /** @defgroup DMA_circular_normal_mode
bogdanm 82:6473597d706e 190 * @{
bogdanm 82:6473597d706e 191 */
bogdanm 82:6473597d706e 192
bogdanm 82:6473597d706e 193 #define DMA_Mode_Normal ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 194 #define DMA_Mode_Circular DMA_CCR_CIRC
bogdanm 82:6473597d706e 195
bogdanm 82:6473597d706e 196 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
bogdanm 82:6473597d706e 197 /**
bogdanm 82:6473597d706e 198 * @}
bogdanm 82:6473597d706e 199 */
bogdanm 82:6473597d706e 200
bogdanm 82:6473597d706e 201 /** @defgroup DMA_priority_level
bogdanm 82:6473597d706e 202 * @{
bogdanm 82:6473597d706e 203 */
bogdanm 82:6473597d706e 204
bogdanm 82:6473597d706e 205 #define DMA_Priority_VeryHigh DMA_CCR_PL
bogdanm 82:6473597d706e 206 #define DMA_Priority_High DMA_CCR_PL_1
bogdanm 82:6473597d706e 207 #define DMA_Priority_Medium DMA_CCR_PL_0
bogdanm 82:6473597d706e 208 #define DMA_Priority_Low ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 209
bogdanm 82:6473597d706e 210 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
bogdanm 82:6473597d706e 211 ((PRIORITY) == DMA_Priority_High) || \
bogdanm 82:6473597d706e 212 ((PRIORITY) == DMA_Priority_Medium) || \
bogdanm 82:6473597d706e 213 ((PRIORITY) == DMA_Priority_Low))
bogdanm 82:6473597d706e 214 /**
bogdanm 82:6473597d706e 215 * @}
bogdanm 82:6473597d706e 216 */
bogdanm 82:6473597d706e 217
bogdanm 82:6473597d706e 218 /** @defgroup DMA_memory_to_memory
bogdanm 82:6473597d706e 219 * @{
bogdanm 82:6473597d706e 220 */
bogdanm 82:6473597d706e 221
bogdanm 82:6473597d706e 222 #define DMA_M2M_Disable ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 223 #define DMA_M2M_Enable DMA_CCR_MEM2MEM
bogdanm 82:6473597d706e 224
bogdanm 82:6473597d706e 225 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
bogdanm 82:6473597d706e 226
bogdanm 82:6473597d706e 227 /**
bogdanm 82:6473597d706e 228 * @}
bogdanm 82:6473597d706e 229 */
bogdanm 82:6473597d706e 230
bogdanm 82:6473597d706e 231 /** @defgroup DMA_interrupts_definition
bogdanm 82:6473597d706e 232 * @{
bogdanm 82:6473597d706e 233 */
bogdanm 82:6473597d706e 234
bogdanm 82:6473597d706e 235 #define DMA_IT_TC ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 236 #define DMA_IT_HT ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 237 #define DMA_IT_TE ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 238 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
bogdanm 82:6473597d706e 239
bogdanm 82:6473597d706e 240 #define DMA1_IT_GL1 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 241 #define DMA1_IT_TC1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 242 #define DMA1_IT_HT1 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 243 #define DMA1_IT_TE1 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 244 #define DMA1_IT_GL2 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 245 #define DMA1_IT_TC2 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 246 #define DMA1_IT_HT2 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 247 #define DMA1_IT_TE2 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 248 #define DMA1_IT_GL3 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 249 #define DMA1_IT_TC3 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 250 #define DMA1_IT_HT3 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 251 #define DMA1_IT_TE3 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 252 #define DMA1_IT_GL4 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 253 #define DMA1_IT_TC4 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 254 #define DMA1_IT_HT4 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 255 #define DMA1_IT_TE4 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 256 #define DMA1_IT_GL5 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 257 #define DMA1_IT_TC5 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 258 #define DMA1_IT_HT5 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 259 #define DMA1_IT_TE5 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 260 #define DMA1_IT_GL6 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 261 #define DMA1_IT_TC6 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 262 #define DMA1_IT_HT6 ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 263 #define DMA1_IT_TE6 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 264 #define DMA1_IT_GL7 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 265 #define DMA1_IT_TC7 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 266 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 267 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 268
bogdanm 82:6473597d706e 269 #define DMA2_IT_GL1 ((uint32_t)0x10000001)
bogdanm 82:6473597d706e 270 #define DMA2_IT_TC1 ((uint32_t)0x10000002)
bogdanm 82:6473597d706e 271 #define DMA2_IT_HT1 ((uint32_t)0x10000004)
bogdanm 82:6473597d706e 272 #define DMA2_IT_TE1 ((uint32_t)0x10000008)
bogdanm 82:6473597d706e 273 #define DMA2_IT_GL2 ((uint32_t)0x10000010)
bogdanm 82:6473597d706e 274 #define DMA2_IT_TC2 ((uint32_t)0x10000020)
bogdanm 82:6473597d706e 275 #define DMA2_IT_HT2 ((uint32_t)0x10000040)
bogdanm 82:6473597d706e 276 #define DMA2_IT_TE2 ((uint32_t)0x10000080)
bogdanm 82:6473597d706e 277 #define DMA2_IT_GL3 ((uint32_t)0x10000100)
bogdanm 82:6473597d706e 278 #define DMA2_IT_TC3 ((uint32_t)0x10000200)
bogdanm 82:6473597d706e 279 #define DMA2_IT_HT3 ((uint32_t)0x10000400)
bogdanm 82:6473597d706e 280 #define DMA2_IT_TE3 ((uint32_t)0x10000800)
bogdanm 82:6473597d706e 281 #define DMA2_IT_GL4 ((uint32_t)0x10001000)
bogdanm 82:6473597d706e 282 #define DMA2_IT_TC4 ((uint32_t)0x10002000)
bogdanm 82:6473597d706e 283 #define DMA2_IT_HT4 ((uint32_t)0x10004000)
bogdanm 82:6473597d706e 284 #define DMA2_IT_TE4 ((uint32_t)0x10008000)
bogdanm 82:6473597d706e 285 #define DMA2_IT_GL5 ((uint32_t)0x10010000)
bogdanm 82:6473597d706e 286 #define DMA2_IT_TC5 ((uint32_t)0x10020000)
bogdanm 82:6473597d706e 287 #define DMA2_IT_HT5 ((uint32_t)0x10040000)
bogdanm 82:6473597d706e 288 #define DMA2_IT_TE5 ((uint32_t)0x10080000)
bogdanm 82:6473597d706e 289
bogdanm 82:6473597d706e 290 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
bogdanm 82:6473597d706e 291
bogdanm 82:6473597d706e 292 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
bogdanm 82:6473597d706e 293 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
bogdanm 82:6473597d706e 294 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
bogdanm 82:6473597d706e 295 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
bogdanm 82:6473597d706e 296 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
bogdanm 82:6473597d706e 297 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
bogdanm 82:6473597d706e 298 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
bogdanm 82:6473597d706e 299 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
bogdanm 82:6473597d706e 300 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
bogdanm 82:6473597d706e 301 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
bogdanm 82:6473597d706e 302 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
bogdanm 82:6473597d706e 303 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
bogdanm 82:6473597d706e 304 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
bogdanm 82:6473597d706e 305 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
bogdanm 82:6473597d706e 306 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
bogdanm 82:6473597d706e 307 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
bogdanm 82:6473597d706e 308 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
bogdanm 82:6473597d706e 309 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
bogdanm 82:6473597d706e 310 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
bogdanm 82:6473597d706e 311 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
bogdanm 82:6473597d706e 312 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
bogdanm 82:6473597d706e 313 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
bogdanm 82:6473597d706e 314 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
bogdanm 82:6473597d706e 315 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
bogdanm 82:6473597d706e 316
bogdanm 82:6473597d706e 317 /**
bogdanm 82:6473597d706e 318 * @}
bogdanm 82:6473597d706e 319 */
bogdanm 82:6473597d706e 320
bogdanm 82:6473597d706e 321 /** @defgroup DMA_flags_definition
bogdanm 82:6473597d706e 322 * @{
bogdanm 82:6473597d706e 323 */
bogdanm 82:6473597d706e 324
bogdanm 82:6473597d706e 325 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 326 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 327 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 328 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 329 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 330 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 331 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 332 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 333 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 334 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 335 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 336 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 337 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 338 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 339 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 340 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 341 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 342 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 343 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 344 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 345 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 346 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 347 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 348 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 349 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 350 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 351 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 352 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 353
bogdanm 82:6473597d706e 354 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
bogdanm 82:6473597d706e 355 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
bogdanm 82:6473597d706e 356 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
bogdanm 82:6473597d706e 357 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
bogdanm 82:6473597d706e 358 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
bogdanm 82:6473597d706e 359 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
bogdanm 82:6473597d706e 360 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
bogdanm 82:6473597d706e 361 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
bogdanm 82:6473597d706e 362 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
bogdanm 82:6473597d706e 363 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
bogdanm 82:6473597d706e 364 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
bogdanm 82:6473597d706e 365 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
bogdanm 82:6473597d706e 366 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
bogdanm 82:6473597d706e 367 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
bogdanm 82:6473597d706e 368 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
bogdanm 82:6473597d706e 369 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
bogdanm 82:6473597d706e 370 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
bogdanm 82:6473597d706e 371 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
bogdanm 82:6473597d706e 372 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
bogdanm 82:6473597d706e 373 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
bogdanm 82:6473597d706e 374
bogdanm 82:6473597d706e 375 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
bogdanm 82:6473597d706e 376
bogdanm 82:6473597d706e 377 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
bogdanm 82:6473597d706e 378 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
bogdanm 82:6473597d706e 379 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
bogdanm 82:6473597d706e 380 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
bogdanm 82:6473597d706e 381 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
bogdanm 82:6473597d706e 382 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
bogdanm 82:6473597d706e 383 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
bogdanm 82:6473597d706e 384 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
bogdanm 82:6473597d706e 385 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
bogdanm 82:6473597d706e 386 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
bogdanm 82:6473597d706e 387 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
bogdanm 82:6473597d706e 388 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
bogdanm 82:6473597d706e 389 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
bogdanm 82:6473597d706e 390 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
bogdanm 82:6473597d706e 391 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
bogdanm 82:6473597d706e 392 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
bogdanm 82:6473597d706e 393 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
bogdanm 82:6473597d706e 394 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
bogdanm 82:6473597d706e 395 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
bogdanm 82:6473597d706e 396 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
bogdanm 82:6473597d706e 397 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
bogdanm 82:6473597d706e 398 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
bogdanm 82:6473597d706e 399 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
bogdanm 82:6473597d706e 400 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
bogdanm 82:6473597d706e 401
bogdanm 82:6473597d706e 402 /**
bogdanm 82:6473597d706e 403 * @}
bogdanm 82:6473597d706e 404 */
bogdanm 82:6473597d706e 405
bogdanm 82:6473597d706e 406 /**
bogdanm 82:6473597d706e 407 * @}
bogdanm 82:6473597d706e 408 */
bogdanm 82:6473597d706e 409
bogdanm 82:6473597d706e 410 /* Exported macro ------------------------------------------------------------*/
bogdanm 82:6473597d706e 411 /* Exported functions ------------------------------------------------------- */
bogdanm 82:6473597d706e 412
bogdanm 82:6473597d706e 413 /* Function used to set the DMA configuration to the default reset state ******/
bogdanm 82:6473597d706e 414 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
bogdanm 82:6473597d706e 415
bogdanm 82:6473597d706e 416 /* Initialization and Configuration functions *********************************/
bogdanm 82:6473597d706e 417 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
bogdanm 82:6473597d706e 418 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
bogdanm 82:6473597d706e 419 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
bogdanm 82:6473597d706e 420
bogdanm 82:6473597d706e 421 /* Data Counter functions******************************************************/
bogdanm 82:6473597d706e 422 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
bogdanm 82:6473597d706e 423 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
bogdanm 82:6473597d706e 424
bogdanm 82:6473597d706e 425 /* Interrupts and flags management functions **********************************/
bogdanm 82:6473597d706e 426 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
bogdanm 82:6473597d706e 427 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
bogdanm 82:6473597d706e 428 void DMA_ClearFlag(uint32_t DMAy_FLAG);
bogdanm 82:6473597d706e 429 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
bogdanm 82:6473597d706e 430 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
bogdanm 82:6473597d706e 431
bogdanm 82:6473597d706e 432 #ifdef __cplusplus
bogdanm 82:6473597d706e 433 }
bogdanm 82:6473597d706e 434 #endif
bogdanm 82:6473597d706e 435
bogdanm 82:6473597d706e 436 #endif /*__STM32F30x_DMA_H */
bogdanm 82:6473597d706e 437
bogdanm 82:6473597d706e 438 /**
bogdanm 82:6473597d706e 439 * @}
bogdanm 82:6473597d706e 440 */
bogdanm 82:6473597d706e 441
bogdanm 82:6473597d706e 442 /**
bogdanm 82:6473597d706e 443 * @}
bogdanm 82:6473597d706e 444 */
bogdanm 82:6473597d706e 445
bogdanm 82:6473597d706e 446 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/