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TARGET_NUCLEO_F302R8/stm32f30x.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
Parent:
82:6473597d706e 
version_2.0

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bogdanm 82:6473597d706e 1 /**
bogdanm 82:6473597d706e 2 ******************************************************************************
bogdanm 82:6473597d706e 3 * @file stm32f30x.h
bogdanm 82:6473597d706e 4 * @author MCD Application Team
bogdanm 82:6473597d706e 5 * @version V1.1.0
bogdanm 82:6473597d706e 6 * @date 27-February-2014
bogdanm 82:6473597d706e 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
bogdanm 82:6473597d706e 8 * This file contains all the peripheral registers definitions, bits
bogdanm 82:6473597d706e 9 * definitions and memory mapping for STM32F30x devices.
bogdanm 82:6473597d706e 10 *
bogdanm 82:6473597d706e 11 * The file is the unique include file that the application programmer
bogdanm 82:6473597d706e 12 * is using in the C source code, usually in main.c. This file contains:
bogdanm 82:6473597d706e 13 * - Configuration section that allows to select:
bogdanm 82:6473597d706e 14 * - The device used in the target application
bogdanm 82:6473597d706e 15 * - To use or not the peripheral’s drivers in application code(i.e.
bogdanm 82:6473597d706e 16 * code will be based on direct access to peripheral’s registers
bogdanm 82:6473597d706e 17 * rather than drivers API), this option is controlled by
bogdanm 82:6473597d706e 18 * "#define USE_STDPERIPH_DRIVER"
bogdanm 82:6473597d706e 19 * - To change few application-specific parameters such as the HSE
bogdanm 82:6473597d706e 20 * crystal frequency
bogdanm 82:6473597d706e 21 * - Data structures and the address mapping for all peripherals
bogdanm 82:6473597d706e 22 * - Peripheral registers declarations and bits definition
bogdanm 82:6473597d706e 23 * - Macros to access peripheral registers hardware
bogdanm 82:6473597d706e 24 *
bogdanm 82:6473597d706e 25 ******************************************************************************
bogdanm 82:6473597d706e 26 * @attention
bogdanm 82:6473597d706e 27 *
bogdanm 82:6473597d706e 28 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 82:6473597d706e 29 *
bogdanm 82:6473597d706e 30 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 31 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 32 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 82:6473597d706e 33 * this list of conditions and the following disclaimer.
bogdanm 82:6473597d706e 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 82:6473597d706e 35 * this list of conditions and the following disclaimer in the documentation
bogdanm 82:6473597d706e 36 * and/or other materials provided with the distribution.
bogdanm 82:6473597d706e 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 82:6473597d706e 38 * may be used to endorse or promote products derived from this software
bogdanm 82:6473597d706e 39 * without specific prior written permission.
bogdanm 82:6473597d706e 40 *
bogdanm 82:6473597d706e 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 82:6473597d706e 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 82:6473597d706e 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 82:6473597d706e 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 82:6473597d706e 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 82:6473597d706e 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 82:6473597d706e 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 82:6473597d706e 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 82:6473597d706e 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 51 *
bogdanm 82:6473597d706e 52 ******************************************************************************
bogdanm 82:6473597d706e 53 */
bogdanm 82:6473597d706e 54
bogdanm 82:6473597d706e 55 /** @addtogroup CMSIS
bogdanm 82:6473597d706e 56 * @{
bogdanm 82:6473597d706e 57 */
bogdanm 82:6473597d706e 58
bogdanm 82:6473597d706e 59 /** @addtogroup stm32f30x
bogdanm 82:6473597d706e 60 * @{
bogdanm 82:6473597d706e 61 */
bogdanm 82:6473597d706e 62
bogdanm 82:6473597d706e 63 #ifndef __STM32F30x_H
bogdanm 82:6473597d706e 64 #define __STM32F30x_H
bogdanm 82:6473597d706e 65
bogdanm 82:6473597d706e 66 #ifdef __cplusplus
bogdanm 82:6473597d706e 67 extern "C" {
bogdanm 82:6473597d706e 68 #endif /* __cplusplus */
bogdanm 82:6473597d706e 69
bogdanm 82:6473597d706e 70 /** @addtogroup Library_configuration_section
bogdanm 82:6473597d706e 71 * @{
bogdanm 82:6473597d706e 72 */
bogdanm 82:6473597d706e 73
bogdanm 82:6473597d706e 74 /* Uncomment the line below according to the target STM32 device used in your
bogdanm 82:6473597d706e 75 application
bogdanm 82:6473597d706e 76 */
bogdanm 82:6473597d706e 77
bogdanm 82:6473597d706e 78 #if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F303x8) && !defined (STM32F301x8) && !defined (STM32F302x8)
bogdanm 82:6473597d706e 79 /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
bogdanm 82:6473597d706e 80 /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
bogdanm 82:6473597d706e 81 #define STM32F302x8 /*!< STM32F302K4, STM32F302K6, STM32F302K8, STM32F302C4, STM32F302C6, STM32F302C8,
bogdanm 82:6473597d706e 82 STM32F302R4, STM32F302R6 and STM32F302R8 Devices */
bogdanm 82:6473597d706e 83 #endif
bogdanm 82:6473597d706e 84
bogdanm 82:6473597d706e 85 /* Tip: To avoid modifying this file each time you need to switch between these
bogdanm 82:6473597d706e 86 devices, you can define the device in your toolchain compiler preprocessor.
bogdanm 82:6473597d706e 87 */
bogdanm 82:6473597d706e 88
bogdanm 82:6473597d706e 89 /* Old STM32F30X definition, maintained for legacy purpose */
bogdanm 82:6473597d706e 90 #if defined(STM32F30X)
bogdanm 82:6473597d706e 91 #define STM32F303xC
bogdanm 82:6473597d706e 92 #endif /* STM32F30X */
bogdanm 82:6473597d706e 93
bogdanm 82:6473597d706e 94 #if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F302x8)
bogdanm 82:6473597d706e 95 #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)"
bogdanm 82:6473597d706e 96 #endif
bogdanm 82:6473597d706e 97
bogdanm 82:6473597d706e 98 #if !defined (USE_STDPERIPH_DRIVER)
bogdanm 82:6473597d706e 99 /**
bogdanm 82:6473597d706e 100 * @brief Comment the line below if you will not use the peripherals drivers.
bogdanm 82:6473597d706e 101 In this case, these drivers will not be included and the application code will
bogdanm 82:6473597d706e 102 be based on direct access to peripherals registers
bogdanm 82:6473597d706e 103 */
bogdanm 82:6473597d706e 104 #define USE_STDPERIPH_DRIVER
bogdanm 82:6473597d706e 105 #endif /* USE_STDPERIPH_DRIVER */
bogdanm 82:6473597d706e 106
bogdanm 82:6473597d706e 107 /**
bogdanm 82:6473597d706e 108 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
bogdanm 82:6473597d706e 109 used in your application
bogdanm 82:6473597d706e 110
bogdanm 82:6473597d706e 111 Tip: To avoid modifying this file each time you need to use different HSE, you
bogdanm 82:6473597d706e 112 can define the HSE value in your toolchain compiler preprocessor.
bogdanm 82:6473597d706e 113 */
bogdanm 82:6473597d706e 114 #if !defined (HSE_VALUE)
bogdanm 82:6473597d706e 115 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External xtal in Hz */
bogdanm 82:6473597d706e 116 #endif /* HSE_VALUE */
bogdanm 82:6473597d706e 117
bogdanm 82:6473597d706e 118 /**
bogdanm 82:6473597d706e 119 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
bogdanm 82:6473597d706e 120 Timeout value
bogdanm 82:6473597d706e 121 */
bogdanm 82:6473597d706e 122 #if !defined (HSE_STARTUP_TIMEOUT)
bogdanm 82:6473597d706e 123 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
bogdanm 82:6473597d706e 124 #endif /* HSE_STARTUP_TIMEOUT */
bogdanm 82:6473597d706e 125
bogdanm 82:6473597d706e 126 /**
bogdanm 82:6473597d706e 127 * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
bogdanm 82:6473597d706e 128 Timeout value
bogdanm 82:6473597d706e 129 */
bogdanm 82:6473597d706e 130 #if !defined (HSI_STARTUP_TIMEOUT)
bogdanm 82:6473597d706e 131 #define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
bogdanm 82:6473597d706e 132 #endif /* HSI_STARTUP_TIMEOUT */
bogdanm 82:6473597d706e 133
bogdanm 82:6473597d706e 134 #if !defined (HSI_VALUE)
bogdanm 82:6473597d706e 135 #define HSI_VALUE ((uint32_t)8000000)
bogdanm 82:6473597d706e 136 #endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz.
bogdanm 82:6473597d706e 137 The real value may vary depending on the variations
bogdanm 82:6473597d706e 138 in voltage and temperature. */
bogdanm 82:6473597d706e 139 #if !defined (LSI_VALUE)
bogdanm 82:6473597d706e 140 #define LSI_VALUE ((uint32_t)40000)
bogdanm 82:6473597d706e 141 #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
bogdanm 82:6473597d706e 142 The real value may vary depending on the variations
bogdanm 82:6473597d706e 143 in voltage and temperature. */
bogdanm 82:6473597d706e 144 #if !defined (LSE_VALUE)
bogdanm 82:6473597d706e 145 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
bogdanm 82:6473597d706e 146 #endif /* LSE_VALUE */
bogdanm 82:6473597d706e 147
bogdanm 82:6473597d706e 148
bogdanm 82:6473597d706e 149 /**
bogdanm 82:6473597d706e 150 * @brief STM32F30x Standard Peripherals Library version number V1.1.0
bogdanm 82:6473597d706e 151 */
bogdanm 82:6473597d706e 152 #define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
bogdanm 82:6473597d706e 153 #define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
bogdanm 82:6473597d706e 154 #define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
bogdanm 82:6473597d706e 155 #define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
bogdanm 82:6473597d706e 156 #define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\
bogdanm 82:6473597d706e 157 |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\
bogdanm 82:6473597d706e 158 |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\
bogdanm 82:6473597d706e 159 |(__STM32F30X_STDPERIPH_VERSION_RC))
bogdanm 82:6473597d706e 160
bogdanm 82:6473597d706e 161 /**
bogdanm 82:6473597d706e 162 * @}
bogdanm 82:6473597d706e 163 */
bogdanm 82:6473597d706e 164
bogdanm 82:6473597d706e 165 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 82:6473597d706e 166 * @{
bogdanm 82:6473597d706e 167 */
bogdanm 82:6473597d706e 168
bogdanm 82:6473597d706e 169 /**
bogdanm 82:6473597d706e 170 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm 82:6473597d706e 171 */
bogdanm 82:6473597d706e 172 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
bogdanm 82:6473597d706e 173 #define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */
bogdanm 82:6473597d706e 174 #define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */
bogdanm 82:6473597d706e 175 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 82:6473597d706e 176 #define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */
bogdanm 82:6473597d706e 177
bogdanm 82:6473597d706e 178
bogdanm 82:6473597d706e 179 /**
bogdanm 82:6473597d706e 180 * @brief STM32F30X Interrupt Number Definition, according to the selected device
bogdanm 82:6473597d706e 181 * in @ref Library_configuration_section
bogdanm 82:6473597d706e 182 */
bogdanm 82:6473597d706e 183 typedef enum IRQn
bogdanm 82:6473597d706e 184 {
bogdanm 82:6473597d706e 185 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
bogdanm 82:6473597d706e 186 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 82:6473597d706e 187 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 82:6473597d706e 188 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 82:6473597d706e 189 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 82:6473597d706e 190 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 82:6473597d706e 191 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 82:6473597d706e 192 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 82:6473597d706e 193 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 82:6473597d706e 194 /****** STM32 specific Interrupt Numbers **********************************************************************/
bogdanm 82:6473597d706e 195 #ifdef STM32F303xC
bogdanm 82:6473597d706e 196 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 82:6473597d706e 197 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 82:6473597d706e 198 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
bogdanm 82:6473597d706e 199 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */
bogdanm 82:6473597d706e 200 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 82:6473597d706e 201 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 82:6473597d706e 202 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 82:6473597d706e 203 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 82:6473597d706e 204 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
bogdanm 82:6473597d706e 205 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 82:6473597d706e 206 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 82:6473597d706e 207 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
bogdanm 82:6473597d706e 208 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
bogdanm 82:6473597d706e 209 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
bogdanm 82:6473597d706e 210 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
bogdanm 82:6473597d706e 211 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
bogdanm 82:6473597d706e 212 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
bogdanm 82:6473597d706e 213 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
bogdanm 82:6473597d706e 214 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
bogdanm 82:6473597d706e 215 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
bogdanm 82:6473597d706e 216 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
bogdanm 82:6473597d706e 217 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 82:6473597d706e 218 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 82:6473597d706e 219 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 82:6473597d706e 220 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
bogdanm 82:6473597d706e 221 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
bogdanm 82:6473597d706e 222 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
bogdanm 82:6473597d706e 223 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 82:6473597d706e 224 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 82:6473597d706e 225 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 82:6473597d706e 226 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 82:6473597d706e 227 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 82:6473597d706e 228 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 82:6473597d706e 229 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 82:6473597d706e 230 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 82:6473597d706e 231 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 82:6473597d706e 232 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 82:6473597d706e 233 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 82:6473597d706e 234 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 82:6473597d706e 235 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 82:6473597d706e 236 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 82:6473597d706e 237 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
bogdanm 82:6473597d706e 238 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
bogdanm 82:6473597d706e 239 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
bogdanm 82:6473597d706e 240 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
bogdanm 82:6473597d706e 241 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
bogdanm 82:6473597d706e 242 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
bogdanm 82:6473597d706e 243 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
bogdanm 82:6473597d706e 244 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 82:6473597d706e 245 UART4_IRQn = 52, /*!< UART4 global Interrupt */
bogdanm 82:6473597d706e 246 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 82:6473597d706e 247 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
bogdanm 82:6473597d706e 248 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
bogdanm 82:6473597d706e 249 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
bogdanm 82:6473597d706e 250 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
bogdanm 82:6473597d706e 251 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
bogdanm 82:6473597d706e 252 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
bogdanm 82:6473597d706e 253 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
bogdanm 82:6473597d706e 254 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
bogdanm 82:6473597d706e 255 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */
bogdanm 82:6473597d706e 256 COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */
bogdanm 82:6473597d706e 257 COMP7_IRQn = 66, /*!< COMP7 global Interrupt */
bogdanm 82:6473597d706e 258 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
bogdanm 82:6473597d706e 259 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
bogdanm 82:6473597d706e 260 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
bogdanm 82:6473597d706e 261 FPU_IRQn = 81 /*!< Floating point Interrupt */
bogdanm 82:6473597d706e 262 #endif /* STM32F303xC */
bogdanm 82:6473597d706e 263 #ifdef STM32F334x8
bogdanm 82:6473597d706e 264 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 82:6473597d706e 265 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 82:6473597d706e 266 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
bogdanm 82:6473597d706e 267 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */
bogdanm 82:6473597d706e 268 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 82:6473597d706e 269 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 82:6473597d706e 270 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 82:6473597d706e 271 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 82:6473597d706e 272 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
bogdanm 82:6473597d706e 273 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 82:6473597d706e 274 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 82:6473597d706e 275 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
bogdanm 82:6473597d706e 276 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
bogdanm 82:6473597d706e 277 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
bogdanm 82:6473597d706e 278 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
bogdanm 82:6473597d706e 279 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
bogdanm 82:6473597d706e 280 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
bogdanm 82:6473597d706e 281 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
bogdanm 82:6473597d706e 282 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
bogdanm 82:6473597d706e 283 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */
bogdanm 82:6473597d706e 284 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */
bogdanm 82:6473597d706e 285 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 82:6473597d706e 286 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 82:6473597d706e 287 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 82:6473597d706e 288 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
bogdanm 82:6473597d706e 289 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
bogdanm 82:6473597d706e 290 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
bogdanm 82:6473597d706e 291 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 82:6473597d706e 292 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 82:6473597d706e 293 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 82:6473597d706e 294 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 82:6473597d706e 295 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 82:6473597d706e 296 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 82:6473597d706e 297 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 82:6473597d706e 298 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 82:6473597d706e 299 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 82:6473597d706e 300 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 82:6473597d706e 301 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
bogdanm 82:6473597d706e 302 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error interrupts */
bogdanm 82:6473597d706e 303 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 underrun error Interrupt */
bogdanm 82:6473597d706e 304 COMP2_IRQn = 64, /*!< COMP2 global Interrupt */
bogdanm 82:6473597d706e 305 COMP4_6_IRQn = 65, /*!< COMP6 and COMP4 global Interrupt */
bogdanm 82:6473597d706e 306 HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
bogdanm 82:6473597d706e 307 HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
bogdanm 82:6473597d706e 308 HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
bogdanm 82:6473597d706e 309 HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
bogdanm 82:6473597d706e 310 HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
bogdanm 82:6473597d706e 311 HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
bogdanm 82:6473597d706e 312 HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
bogdanm 82:6473597d706e 313 FPU_IRQn = 81 /*!< Floating point Interrupt */
bogdanm 82:6473597d706e 314 #endif /* STM32F334x8 */
bogdanm 82:6473597d706e 315 #ifdef STM32F302x8
bogdanm 82:6473597d706e 316 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 82:6473597d706e 317 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 82:6473597d706e 318 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
bogdanm 82:6473597d706e 319 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 20 */
bogdanm 82:6473597d706e 320 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 82:6473597d706e 321 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 82:6473597d706e 322 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 82:6473597d706e 323 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 82:6473597d706e 324 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
bogdanm 82:6473597d706e 325 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 82:6473597d706e 326 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 82:6473597d706e 327 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
bogdanm 82:6473597d706e 328 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
bogdanm 82:6473597d706e 329 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
bogdanm 82:6473597d706e 330 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
bogdanm 82:6473597d706e 331 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
bogdanm 82:6473597d706e 332 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
bogdanm 82:6473597d706e 333 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
bogdanm 82:6473597d706e 334 ADC1_IRQn = 18, /*!< ADC1 Interrupts */
bogdanm 82:6473597d706e 335 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
bogdanm 82:6473597d706e 336 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
bogdanm 82:6473597d706e 337 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 82:6473597d706e 338 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 82:6473597d706e 339 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 82:6473597d706e 340 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
bogdanm 82:6473597d706e 341 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
bogdanm 82:6473597d706e 342 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
bogdanm 82:6473597d706e 343 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 82:6473597d706e 344 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 82:6473597d706e 345 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 82:6473597d706e 346 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 82:6473597d706e 347 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 82:6473597d706e 348 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 82:6473597d706e 349 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 82:6473597d706e 350 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 82:6473597d706e 351 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 82:6473597d706e 352 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 82:6473597d706e 353 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 82:6473597d706e 354 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
bogdanm 82:6473597d706e 355 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
bogdanm 82:6473597d706e 356 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 82:6473597d706e 357 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
bogdanm 82:6473597d706e 358 COMP2_IRQn = 64, /*!< COMP2 global Interrupt */
bogdanm 82:6473597d706e 359 COMP4_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */
bogdanm 82:6473597d706e 360 COMP7_IRQn = 66, /*!< COMP7 global Interrupt */
bogdanm 82:6473597d706e 361 I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt */
bogdanm 82:6473597d706e 362 I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
bogdanm 82:6473597d706e 363 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
bogdanm 82:6473597d706e 364 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
bogdanm 82:6473597d706e 365 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
bogdanm 82:6473597d706e 366 FPU_IRQn = 81 /*!< Floating point Interrupt */
bogdanm 82:6473597d706e 367 #endif /* STM32F302x8 */
bogdanm 82:6473597d706e 368 } IRQn_Type;
bogdanm 82:6473597d706e 369
bogdanm 82:6473597d706e 370 /**
bogdanm 82:6473597d706e 371 * @}
bogdanm 82:6473597d706e 372 */
bogdanm 82:6473597d706e 373
bogdanm 82:6473597d706e 374 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 82:6473597d706e 375 #include "system_stm32f30x.h" /* STM32F30x System Header */
bogdanm 82:6473597d706e 376 #include <stdint.h>
bogdanm 82:6473597d706e 377
bogdanm 82:6473597d706e 378 /** @addtogroup Exported_types
bogdanm 82:6473597d706e 379 * @{
bogdanm 82:6473597d706e 380 */
bogdanm 82:6473597d706e 381 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
bogdanm 82:6473597d706e 382 typedef int32_t s32;
bogdanm 82:6473597d706e 383 typedef int16_t s16;
bogdanm 82:6473597d706e 384 typedef int8_t s8;
bogdanm 82:6473597d706e 385
bogdanm 82:6473597d706e 386 typedef const int32_t sc32; /*!< Read Only */
bogdanm 82:6473597d706e 387 typedef const int16_t sc16; /*!< Read Only */
bogdanm 82:6473597d706e 388 typedef const int8_t sc8; /*!< Read Only */
bogdanm 82:6473597d706e 389
bogdanm 82:6473597d706e 390 typedef __IO int32_t vs32;
bogdanm 82:6473597d706e 391 typedef __IO int16_t vs16;
bogdanm 82:6473597d706e 392 typedef __IO int8_t vs8;
bogdanm 82:6473597d706e 393
bogdanm 82:6473597d706e 394 typedef __I int32_t vsc32; /*!< Read Only */
bogdanm 82:6473597d706e 395 typedef __I int16_t vsc16; /*!< Read Only */
bogdanm 82:6473597d706e 396 typedef __I int8_t vsc8; /*!< Read Only */
bogdanm 82:6473597d706e 397
bogdanm 82:6473597d706e 398 typedef uint32_t u32;
bogdanm 82:6473597d706e 399 typedef uint16_t u16;
bogdanm 82:6473597d706e 400 typedef uint8_t u8;
bogdanm 82:6473597d706e 401
bogdanm 82:6473597d706e 402 typedef const uint32_t uc32; /*!< Read Only */
bogdanm 82:6473597d706e 403 typedef const uint16_t uc16; /*!< Read Only */
bogdanm 82:6473597d706e 404 typedef const uint8_t uc8; /*!< Read Only */
bogdanm 82:6473597d706e 405
bogdanm 82:6473597d706e 406 typedef __IO uint32_t vu32;
bogdanm 82:6473597d706e 407 typedef __IO uint16_t vu16;
bogdanm 82:6473597d706e 408 typedef __IO uint8_t vu8;
bogdanm 82:6473597d706e 409
bogdanm 82:6473597d706e 410 typedef __I uint32_t vuc32; /*!< Read Only */
bogdanm 82:6473597d706e 411 typedef __I uint16_t vuc16; /*!< Read Only */
bogdanm 82:6473597d706e 412 typedef __I uint8_t vuc8; /*!< Read Only */
bogdanm 82:6473597d706e 413
bogdanm 82:6473597d706e 414 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
bogdanm 82:6473597d706e 415
bogdanm 82:6473597d706e 416 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
bogdanm 82:6473597d706e 417 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
bogdanm 82:6473597d706e 418
bogdanm 82:6473597d706e 419 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
bogdanm 82:6473597d706e 420
bogdanm 82:6473597d706e 421 /**
bogdanm 82:6473597d706e 422 * @}
bogdanm 82:6473597d706e 423 */
bogdanm 82:6473597d706e 424
bogdanm 82:6473597d706e 425 /** @addtogroup Peripheral_registers_structures
bogdanm 82:6473597d706e 426 * @{
bogdanm 82:6473597d706e 427 */
bogdanm 82:6473597d706e 428
bogdanm 82:6473597d706e 429 /**
bogdanm 82:6473597d706e 430 * @brief Analog to Digital Converter
bogdanm 82:6473597d706e 431 */
bogdanm 82:6473597d706e 432
bogdanm 82:6473597d706e 433 typedef struct
bogdanm 82:6473597d706e 434 {
bogdanm 82:6473597d706e 435 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
bogdanm 82:6473597d706e 436 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
bogdanm 82:6473597d706e 437 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
bogdanm 82:6473597d706e 438 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
bogdanm 82:6473597d706e 439 uint32_t RESERVED0; /*!< Reserved, 0x010 */
bogdanm 82:6473597d706e 440 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
bogdanm 82:6473597d706e 441 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
bogdanm 82:6473597d706e 442 uint32_t RESERVED1; /*!< Reserved, 0x01C */
bogdanm 82:6473597d706e 443 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
bogdanm 82:6473597d706e 444 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
bogdanm 82:6473597d706e 445 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
bogdanm 82:6473597d706e 446 uint32_t RESERVED2; /*!< Reserved, 0x02C */
bogdanm 82:6473597d706e 447 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
bogdanm 82:6473597d706e 448 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
bogdanm 82:6473597d706e 449 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
bogdanm 82:6473597d706e 450 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
bogdanm 82:6473597d706e 451 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
bogdanm 82:6473597d706e 452 uint32_t RESERVED3; /*!< Reserved, 0x044 */
bogdanm 82:6473597d706e 453 uint32_t RESERVED4; /*!< Reserved, 0x048 */
bogdanm 82:6473597d706e 454 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
bogdanm 82:6473597d706e 455 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
bogdanm 82:6473597d706e 456 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
bogdanm 82:6473597d706e 457 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
bogdanm 82:6473597d706e 458 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
bogdanm 82:6473597d706e 459 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
bogdanm 82:6473597d706e 460 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
bogdanm 82:6473597d706e 461 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
bogdanm 82:6473597d706e 462 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
bogdanm 82:6473597d706e 463 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
bogdanm 82:6473597d706e 464 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
bogdanm 82:6473597d706e 465 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
bogdanm 82:6473597d706e 466 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
bogdanm 82:6473597d706e 467 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
bogdanm 82:6473597d706e 468 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
bogdanm 82:6473597d706e 469 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
bogdanm 82:6473597d706e 470 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
bogdanm 82:6473597d706e 471 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
bogdanm 82:6473597d706e 472
bogdanm 82:6473597d706e 473 } ADC_TypeDef;
bogdanm 82:6473597d706e 474
bogdanm 82:6473597d706e 475 typedef struct
bogdanm 82:6473597d706e 476 {
bogdanm 82:6473597d706e 477 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
bogdanm 82:6473597d706e 478 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
bogdanm 82:6473597d706e 479 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
bogdanm 82:6473597d706e 480 __IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm 82:6473597d706e 481 modes, Address offset: ADC1/3 base address + 0x30A */
bogdanm 82:6473597d706e 482 } ADC_Common_TypeDef;
bogdanm 82:6473597d706e 483
bogdanm 82:6473597d706e 484
bogdanm 82:6473597d706e 485 /**
bogdanm 82:6473597d706e 486 * @brief Controller Area Network TxMailBox
bogdanm 82:6473597d706e 487 */
bogdanm 82:6473597d706e 488 typedef struct
bogdanm 82:6473597d706e 489 {
bogdanm 82:6473597d706e 490 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
bogdanm 82:6473597d706e 491 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
bogdanm 82:6473597d706e 492 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
bogdanm 82:6473597d706e 493 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
bogdanm 82:6473597d706e 494 } CAN_TxMailBox_TypeDef;
bogdanm 82:6473597d706e 495
bogdanm 82:6473597d706e 496 /**
bogdanm 82:6473597d706e 497 * @brief Controller Area Network FIFOMailBox
bogdanm 82:6473597d706e 498 */
bogdanm 82:6473597d706e 499 typedef struct
bogdanm 82:6473597d706e 500 {
bogdanm 82:6473597d706e 501 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
bogdanm 82:6473597d706e 502 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
bogdanm 82:6473597d706e 503 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
bogdanm 82:6473597d706e 504 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
bogdanm 82:6473597d706e 505 } CAN_FIFOMailBox_TypeDef;
bogdanm 82:6473597d706e 506
bogdanm 82:6473597d706e 507 /**
bogdanm 82:6473597d706e 508 * @brief Controller Area Network FilterRegister
bogdanm 82:6473597d706e 509 */
bogdanm 82:6473597d706e 510 typedef struct
bogdanm 82:6473597d706e 511 {
bogdanm 82:6473597d706e 512 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
bogdanm 82:6473597d706e 513 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
bogdanm 82:6473597d706e 514 } CAN_FilterRegister_TypeDef;
bogdanm 82:6473597d706e 515
bogdanm 82:6473597d706e 516 /**
bogdanm 82:6473597d706e 517 * @brief Controller Area Network
bogdanm 82:6473597d706e 518 */
bogdanm 82:6473597d706e 519 typedef struct
bogdanm 82:6473597d706e 520 {
bogdanm 82:6473597d706e 521 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 522 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
bogdanm 82:6473597d706e 523 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
bogdanm 82:6473597d706e 524 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
bogdanm 82:6473597d706e 525 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
bogdanm 82:6473597d706e 526 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
bogdanm 82:6473597d706e 527 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
bogdanm 82:6473597d706e 528 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
bogdanm 82:6473597d706e 529 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
bogdanm 82:6473597d706e 530 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
bogdanm 82:6473597d706e 531 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
bogdanm 82:6473597d706e 532 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
bogdanm 82:6473597d706e 533 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
bogdanm 82:6473597d706e 534 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
bogdanm 82:6473597d706e 535 uint32_t RESERVED2; /*!< Reserved, 0x208 */
bogdanm 82:6473597d706e 536 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
bogdanm 82:6473597d706e 537 uint32_t RESERVED3; /*!< Reserved, 0x210 */
bogdanm 82:6473597d706e 538 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
bogdanm 82:6473597d706e 539 uint32_t RESERVED4; /*!< Reserved, 0x218 */
bogdanm 82:6473597d706e 540 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
bogdanm 82:6473597d706e 541 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
bogdanm 82:6473597d706e 542 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
bogdanm 82:6473597d706e 543 } CAN_TypeDef;
bogdanm 82:6473597d706e 544
bogdanm 82:6473597d706e 545
bogdanm 82:6473597d706e 546 /**
bogdanm 82:6473597d706e 547 * @brief Analog Comparators
bogdanm 82:6473597d706e 548 */
bogdanm 82:6473597d706e 549
bogdanm 82:6473597d706e 550 typedef struct
bogdanm 82:6473597d706e 551 {
bogdanm 82:6473597d706e 552 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
bogdanm 82:6473597d706e 553 } COMP_TypeDef;
bogdanm 82:6473597d706e 554
bogdanm 82:6473597d706e 555 /**
bogdanm 82:6473597d706e 556 * @brief CRC calculation unit
bogdanm 82:6473597d706e 557 */
bogdanm 82:6473597d706e 558
bogdanm 82:6473597d706e 559 typedef struct
bogdanm 82:6473597d706e 560 {
bogdanm 82:6473597d706e 561 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 82:6473597d706e 562 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 82:6473597d706e 563 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 82:6473597d706e 564 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 82:6473597d706e 565 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 82:6473597d706e 566 uint32_t RESERVED2; /*!< Reserved, 0x0C */
bogdanm 82:6473597d706e 567 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
bogdanm 82:6473597d706e 568 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
bogdanm 82:6473597d706e 569 } CRC_TypeDef;
bogdanm 82:6473597d706e 570
bogdanm 82:6473597d706e 571 /**
bogdanm 82:6473597d706e 572 * @brief Digital to Analog Converter
bogdanm 82:6473597d706e 573 */
bogdanm 82:6473597d706e 574
bogdanm 82:6473597d706e 575 typedef struct
bogdanm 82:6473597d706e 576 {
bogdanm 82:6473597d706e 577 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 578 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 82:6473597d706e 579 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 82:6473597d706e 580 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 82:6473597d706e 581 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 82:6473597d706e 582 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 82:6473597d706e 583 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 82:6473597d706e 584 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 82:6473597d706e 585 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 82:6473597d706e 586 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 82:6473597d706e 587 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 82:6473597d706e 588 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 82:6473597d706e 589 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 82:6473597d706e 590 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 82:6473597d706e 591 } DAC_TypeDef;
bogdanm 82:6473597d706e 592
bogdanm 82:6473597d706e 593 /**
bogdanm 82:6473597d706e 594 * @brief Debug MCU
bogdanm 82:6473597d706e 595 */
bogdanm 82:6473597d706e 596
bogdanm 82:6473597d706e 597 typedef struct
bogdanm 82:6473597d706e 598 {
bogdanm 82:6473597d706e 599 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 82:6473597d706e 600 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 82:6473597d706e 601 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 82:6473597d706e 602 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 82:6473597d706e 603 }DBGMCU_TypeDef;
bogdanm 82:6473597d706e 604
bogdanm 82:6473597d706e 605 /**
bogdanm 82:6473597d706e 606 * @brief DMA Controller
bogdanm 82:6473597d706e 607 */
bogdanm 82:6473597d706e 608
bogdanm 82:6473597d706e 609 typedef struct
bogdanm 82:6473597d706e 610 {
bogdanm 82:6473597d706e 611 __IO uint32_t CCR; /*!< DMA channel x configuration register */
bogdanm 82:6473597d706e 612 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
bogdanm 82:6473597d706e 613 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
bogdanm 82:6473597d706e 614 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
bogdanm 82:6473597d706e 615 } DMA_Channel_TypeDef;
bogdanm 82:6473597d706e 616
bogdanm 82:6473597d706e 617 typedef struct
bogdanm 82:6473597d706e 618 {
bogdanm 82:6473597d706e 619 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
bogdanm 82:6473597d706e 620 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
bogdanm 82:6473597d706e 621 } DMA_TypeDef;
bogdanm 82:6473597d706e 622
bogdanm 82:6473597d706e 623 /**
bogdanm 82:6473597d706e 624 * @brief External Interrupt/Event Controller
bogdanm 82:6473597d706e 625 */
bogdanm 82:6473597d706e 626
bogdanm 82:6473597d706e 627 typedef struct
bogdanm 82:6473597d706e 628 {
bogdanm 82:6473597d706e 629 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 82:6473597d706e 630 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
bogdanm 82:6473597d706e 631 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
bogdanm 82:6473597d706e 632 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 82:6473597d706e 633 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 82:6473597d706e 634 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
bogdanm 82:6473597d706e 635 uint32_t RESERVED1; /*!< Reserved, 0x18 */
bogdanm 82:6473597d706e 636 uint32_t RESERVED2; /*!< Reserved, 0x1C */
bogdanm 82:6473597d706e 637 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
bogdanm 82:6473597d706e 638 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
bogdanm 82:6473597d706e 639 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
bogdanm 82:6473597d706e 640 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
bogdanm 82:6473597d706e 641 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
bogdanm 82:6473597d706e 642 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
bogdanm 82:6473597d706e 643 }EXTI_TypeDef;
bogdanm 82:6473597d706e 644
bogdanm 82:6473597d706e 645 /**
bogdanm 82:6473597d706e 646 * @brief FLASH Registers
bogdanm 82:6473597d706e 647 */
bogdanm 82:6473597d706e 648
bogdanm 82:6473597d706e 649 typedef struct
bogdanm 82:6473597d706e 650 {
bogdanm 82:6473597d706e 651 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 652 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
bogdanm 82:6473597d706e 653 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
bogdanm 82:6473597d706e 654 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
bogdanm 82:6473597d706e 655 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
bogdanm 82:6473597d706e 656 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
bogdanm 82:6473597d706e 657 uint32_t RESERVED; /*!< Reserved, 0x18 */
bogdanm 82:6473597d706e 658 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
bogdanm 82:6473597d706e 659 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
bogdanm 82:6473597d706e 660
bogdanm 82:6473597d706e 661 } FLASH_TypeDef;
bogdanm 82:6473597d706e 662
bogdanm 82:6473597d706e 663 /**
bogdanm 82:6473597d706e 664 * @brief Option Bytes Registers
bogdanm 82:6473597d706e 665 */
bogdanm 82:6473597d706e 666 typedef struct
bogdanm 82:6473597d706e 667 {
bogdanm 82:6473597d706e 668 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
bogdanm 82:6473597d706e 669 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
bogdanm 82:6473597d706e 670 uint16_t RESERVED0; /*!< Reserved, 0x04 */
bogdanm 82:6473597d706e 671 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 82:6473597d706e 672 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
bogdanm 82:6473597d706e 673 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
bogdanm 82:6473597d706e 674 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
bogdanm 82:6473597d706e 675 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
bogdanm 82:6473597d706e 676 } OB_TypeDef;
bogdanm 82:6473597d706e 677
bogdanm 82:6473597d706e 678 /**
bogdanm 82:6473597d706e 679 * @brief General Purpose I/O
bogdanm 82:6473597d706e 680 */
bogdanm 82:6473597d706e 681
bogdanm 82:6473597d706e 682 typedef struct
bogdanm 82:6473597d706e 683 {
bogdanm 82:6473597d706e 684 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 82:6473597d706e 685 __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 82:6473597d706e 686 uint16_t RESERVED0; /*!< Reserved, 0x06 */
bogdanm 82:6473597d706e 687 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 82:6473597d706e 688 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 82:6473597d706e 689 __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 82:6473597d706e 690 uint16_t RESERVED1; /*!< Reserved, 0x12 */
bogdanm 82:6473597d706e 691 __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 82:6473597d706e 692 uint16_t RESERVED2; /*!< Reserved, 0x16 */
bogdanm 82:6473597d706e 693 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
bogdanm 82:6473597d706e 694 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 82:6473597d706e 695 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
bogdanm 82:6473597d706e 696 __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
bogdanm 82:6473597d706e 697 uint16_t RESERVED3; /*!< Reserved, 0x2A */
bogdanm 82:6473597d706e 698 }GPIO_TypeDef;
bogdanm 82:6473597d706e 699
bogdanm 82:6473597d706e 700 /**
bogdanm 82:6473597d706e 701 * @brief High resolution Timer (HRTIM)
bogdanm 82:6473597d706e 702 */
bogdanm 82:6473597d706e 703 /* HRTIM master definition */
bogdanm 82:6473597d706e 704 typedef struct
bogdanm 82:6473597d706e 705 {
bogdanm 82:6473597d706e 706 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 707 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
bogdanm 82:6473597d706e 708 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
bogdanm 82:6473597d706e 709 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
bogdanm 82:6473597d706e 710 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
bogdanm 82:6473597d706e 711 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
bogdanm 82:6473597d706e 712 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
bogdanm 82:6473597d706e 713 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
bogdanm 82:6473597d706e 714 uint32_t RESERVED0; /*!< Reserved, 0x20 */
bogdanm 82:6473597d706e 715 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
bogdanm 82:6473597d706e 716 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
bogdanm 82:6473597d706e 717 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
bogdanm 82:6473597d706e 718 }HRTIM_Master_TypeDef;
bogdanm 82:6473597d706e 719
bogdanm 82:6473597d706e 720 /* HRTIM slave definition */
bogdanm 82:6473597d706e 721 typedef struct
bogdanm 82:6473597d706e 722 {
bogdanm 82:6473597d706e 723 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 724 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
bogdanm 82:6473597d706e 725 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
bogdanm 82:6473597d706e 726 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 82:6473597d706e 727 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
bogdanm 82:6473597d706e 728 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
bogdanm 82:6473597d706e 729 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
bogdanm 82:6473597d706e 730 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
bogdanm 82:6473597d706e 731 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
bogdanm 82:6473597d706e 732 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
bogdanm 82:6473597d706e 733 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
bogdanm 82:6473597d706e 734 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
bogdanm 82:6473597d706e 735 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
bogdanm 82:6473597d706e 736 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
bogdanm 82:6473597d706e 737 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
bogdanm 82:6473597d706e 738 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
bogdanm 82:6473597d706e 739 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
bogdanm 82:6473597d706e 740 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
bogdanm 82:6473597d706e 741 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
bogdanm 82:6473597d706e 742 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
bogdanm 82:6473597d706e 743 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
bogdanm 82:6473597d706e 744 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
bogdanm 82:6473597d706e 745 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
bogdanm 82:6473597d706e 746 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
bogdanm 82:6473597d706e 747 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
bogdanm 82:6473597d706e 748 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
bogdanm 82:6473597d706e 749 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
bogdanm 82:6473597d706e 750 uint32_t RESERVED0[5];/*!< Reserved, */
bogdanm 82:6473597d706e 751 }HRTIM_Timerx_TypeDef;
bogdanm 82:6473597d706e 752
bogdanm 82:6473597d706e 753 /* HRTIM common register definition */
bogdanm 82:6473597d706e 754 typedef struct
bogdanm 82:6473597d706e 755 {
bogdanm 82:6473597d706e 756 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
bogdanm 82:6473597d706e 757 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
bogdanm 82:6473597d706e 758 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
bogdanm 82:6473597d706e 759 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
bogdanm 82:6473597d706e 760 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
bogdanm 82:6473597d706e 761 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
bogdanm 82:6473597d706e 762 __IO uint32_t DISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
bogdanm 82:6473597d706e 763 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
bogdanm 82:6473597d706e 764 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
bogdanm 82:6473597d706e 765 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
bogdanm 82:6473597d706e 766 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
bogdanm 82:6473597d706e 767 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
bogdanm 82:6473597d706e 768 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
bogdanm 82:6473597d706e 769 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
bogdanm 82:6473597d706e 770 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
bogdanm 82:6473597d706e 771 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
bogdanm 82:6473597d706e 772 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
bogdanm 82:6473597d706e 773 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
bogdanm 82:6473597d706e 774 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
bogdanm 82:6473597d706e 775 __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
bogdanm 82:6473597d706e 776 __IO uint32_t FLTINxR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
bogdanm 82:6473597d706e 777 __IO uint32_t FLTINxR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
bogdanm 82:6473597d706e 778 __IO uint32_t BDMUPDR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
bogdanm 82:6473597d706e 779 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
bogdanm 82:6473597d706e 780 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
bogdanm 82:6473597d706e 781 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
bogdanm 82:6473597d706e 782 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
bogdanm 82:6473597d706e 783 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
bogdanm 82:6473597d706e 784 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
bogdanm 82:6473597d706e 785 }HRTIM_Common_TypeDef;
bogdanm 82:6473597d706e 786
bogdanm 82:6473597d706e 787 /* HRTIM register definition */
bogdanm 82:6473597d706e 788 typedef struct {
bogdanm 82:6473597d706e 789 HRTIM_Master_TypeDef HRTIM_MASTER;
bogdanm 82:6473597d706e 790 uint32_t RESERVED0[20];
bogdanm 82:6473597d706e 791 HRTIM_Timerx_TypeDef HRTIM_TIMERx[5];
bogdanm 82:6473597d706e 792 uint32_t RESERVED1[32];
bogdanm 82:6473597d706e 793 HRTIM_Common_TypeDef HRTIM_COMMON;
bogdanm 82:6473597d706e 794 }HRTIM_TypeDef;
bogdanm 82:6473597d706e 795
bogdanm 82:6473597d706e 796 /**
bogdanm 82:6473597d706e 797 * @brief Operational Amplifier (OPAMP)
bogdanm 82:6473597d706e 798 */
bogdanm 82:6473597d706e 799
bogdanm 82:6473597d706e 800 typedef struct
bogdanm 82:6473597d706e 801 {
bogdanm 82:6473597d706e 802 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
bogdanm 82:6473597d706e 803 } OPAMP_TypeDef;
bogdanm 82:6473597d706e 804
bogdanm 82:6473597d706e 805
bogdanm 82:6473597d706e 806 /**
bogdanm 82:6473597d706e 807 * @brief System configuration controller
bogdanm 82:6473597d706e 808 */
bogdanm 82:6473597d706e 809
bogdanm 82:6473597d706e 810 typedef struct
bogdanm 82:6473597d706e 811 {
bogdanm 82:6473597d706e 812 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
bogdanm 82:6473597d706e 813 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
bogdanm 82:6473597d706e 814 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
bogdanm 82:6473597d706e 815 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
bogdanm 82:6473597d706e 816 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
bogdanm 82:6473597d706e 817 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
bogdanm 82:6473597d706e 818 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
bogdanm 82:6473597d706e 819 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
bogdanm 82:6473597d706e 820 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
bogdanm 82:6473597d706e 821 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
bogdanm 82:6473597d706e 822 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
bogdanm 82:6473597d706e 823 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
bogdanm 82:6473597d706e 824 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
bogdanm 82:6473597d706e 825 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
bogdanm 82:6473597d706e 826 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
bogdanm 82:6473597d706e 827 __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */
bogdanm 82:6473597d706e 828 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */
bogdanm 82:6473597d706e 829 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */
bogdanm 82:6473597d706e 830 } SYSCFG_TypeDef;
bogdanm 82:6473597d706e 831
bogdanm 82:6473597d706e 832 /**
bogdanm 82:6473597d706e 833 * @brief Inter-integrated Circuit Interface
bogdanm 82:6473597d706e 834 */
bogdanm 82:6473597d706e 835
bogdanm 82:6473597d706e 836 typedef struct
bogdanm 82:6473597d706e 837 {
bogdanm 82:6473597d706e 838 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 82:6473597d706e 839 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 82:6473597d706e 840 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
bogdanm 82:6473597d706e 841 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
bogdanm 82:6473597d706e 842 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
bogdanm 82:6473597d706e 843 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
bogdanm 82:6473597d706e 844 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
bogdanm 82:6473597d706e 845 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
bogdanm 82:6473597d706e 846 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
bogdanm 82:6473597d706e 847 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
bogdanm 82:6473597d706e 848 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
bogdanm 82:6473597d706e 849 }I2C_TypeDef;
bogdanm 82:6473597d706e 850
bogdanm 82:6473597d706e 851 /**
bogdanm 82:6473597d706e 852 * @brief Independent WATCHDOG
bogdanm 82:6473597d706e 853 */
bogdanm 82:6473597d706e 854
bogdanm 82:6473597d706e 855 typedef struct
bogdanm 82:6473597d706e 856 {
bogdanm 82:6473597d706e 857 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 82:6473597d706e 858 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 82:6473597d706e 859 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 82:6473597d706e 860 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 82:6473597d706e 861 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
bogdanm 82:6473597d706e 862 } IWDG_TypeDef;
bogdanm 82:6473597d706e 863
bogdanm 82:6473597d706e 864 /**
bogdanm 82:6473597d706e 865 * @brief Power Control
bogdanm 82:6473597d706e 866 */
bogdanm 82:6473597d706e 867
bogdanm 82:6473597d706e 868 typedef struct
bogdanm 82:6473597d706e 869 {
bogdanm 82:6473597d706e 870 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 871 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 82:6473597d706e 872 } PWR_TypeDef;
bogdanm 82:6473597d706e 873
bogdanm 82:6473597d706e 874 /**
bogdanm 82:6473597d706e 875 * @brief Reset and Clock Control
bogdanm 82:6473597d706e 876 */
bogdanm 82:6473597d706e 877 typedef struct
bogdanm 82:6473597d706e 878 {
bogdanm 82:6473597d706e 879 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 880 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
bogdanm 82:6473597d706e 881 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
bogdanm 82:6473597d706e 882 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
bogdanm 82:6473597d706e 883 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
bogdanm 82:6473597d706e 884 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
bogdanm 82:6473597d706e 885 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
bogdanm 82:6473597d706e 886 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
bogdanm 82:6473597d706e 887 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
bogdanm 82:6473597d706e 888 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
bogdanm 82:6473597d706e 889 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
bogdanm 82:6473597d706e 890 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
bogdanm 82:6473597d706e 891 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
bogdanm 82:6473597d706e 892 } RCC_TypeDef;
bogdanm 82:6473597d706e 893
bogdanm 82:6473597d706e 894 /**
bogdanm 82:6473597d706e 895 * @brief Real-Time Clock
bogdanm 82:6473597d706e 896 */
bogdanm 82:6473597d706e 897
bogdanm 82:6473597d706e 898 typedef struct
bogdanm 82:6473597d706e 899 {
bogdanm 82:6473597d706e 900 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 82:6473597d706e 901 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 82:6473597d706e 902 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 82:6473597d706e 903 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 82:6473597d706e 904 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 82:6473597d706e 905 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 82:6473597d706e 906 uint32_t RESERVED0; /*!< Reserved, 0x18 */
bogdanm 82:6473597d706e 907 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 82:6473597d706e 908 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 82:6473597d706e 909 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 82:6473597d706e 910 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 82:6473597d706e 911 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 82:6473597d706e 912 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 82:6473597d706e 913 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 82:6473597d706e 914 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 82:6473597d706e 915 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 82:6473597d706e 916 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 82:6473597d706e 917 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 82:6473597d706e 918 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 82:6473597d706e 919 uint32_t RESERVED7; /*!< Reserved, 0x4C */
bogdanm 82:6473597d706e 920 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
bogdanm 82:6473597d706e 921 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 82:6473597d706e 922 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 82:6473597d706e 923 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 82:6473597d706e 924 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 82:6473597d706e 925 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
bogdanm 82:6473597d706e 926 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
bogdanm 82:6473597d706e 927 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
bogdanm 82:6473597d706e 928 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
bogdanm 82:6473597d706e 929 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
bogdanm 82:6473597d706e 930 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
bogdanm 82:6473597d706e 931 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
bogdanm 82:6473597d706e 932 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
bogdanm 82:6473597d706e 933 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
bogdanm 82:6473597d706e 934 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
bogdanm 82:6473597d706e 935 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
bogdanm 82:6473597d706e 936 } RTC_TypeDef;
bogdanm 82:6473597d706e 937
bogdanm 82:6473597d706e 938
bogdanm 82:6473597d706e 939 /**
bogdanm 82:6473597d706e 940 * @brief Serial Peripheral Interface
bogdanm 82:6473597d706e 941 */
bogdanm 82:6473597d706e 942
bogdanm 82:6473597d706e 943 typedef struct
bogdanm 82:6473597d706e 944 {
bogdanm 82:6473597d706e 945 __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 82:6473597d706e 946 uint16_t RESERVED0; /*!< Reserved, 0x02 */
bogdanm 82:6473597d706e 947 __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
bogdanm 82:6473597d706e 948 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 82:6473597d706e 949 __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
bogdanm 82:6473597d706e 950 uint16_t RESERVED2; /*!< Reserved, 0x0A */
bogdanm 82:6473597d706e 951 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 82:6473597d706e 952 uint16_t RESERVED3; /*!< Reserved, 0x0E */
bogdanm 82:6473597d706e 953 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 82:6473597d706e 954 uint16_t RESERVED4; /*!< Reserved, 0x12 */
bogdanm 82:6473597d706e 955 __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 82:6473597d706e 956 uint16_t RESERVED5; /*!< Reserved, 0x16 */
bogdanm 82:6473597d706e 957 __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 82:6473597d706e 958 uint16_t RESERVED6; /*!< Reserved, 0x1A */
bogdanm 82:6473597d706e 959 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 82:6473597d706e 960 uint16_t RESERVED7; /*!< Reserved, 0x1E */
bogdanm 82:6473597d706e 961 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 82:6473597d706e 962 uint16_t RESERVED8; /*!< Reserved, 0x22 */
bogdanm 82:6473597d706e 963 } SPI_TypeDef;
bogdanm 82:6473597d706e 964
bogdanm 82:6473597d706e 965 /**
bogdanm 82:6473597d706e 966 * @brief TIM
bogdanm 82:6473597d706e 967 */
bogdanm 82:6473597d706e 968 typedef struct
bogdanm 82:6473597d706e 969 {
bogdanm 82:6473597d706e 970 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 82:6473597d706e 971 uint16_t RESERVED0; /*!< Reserved, 0x02 */
bogdanm 82:6473597d706e 972 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 82:6473597d706e 973 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
bogdanm 82:6473597d706e 974 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 82:6473597d706e 975 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 82:6473597d706e 976 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 82:6473597d706e 977 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 82:6473597d706e 978 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 82:6473597d706e 979 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 82:6473597d706e 980 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 82:6473597d706e 981 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
bogdanm 82:6473597d706e 982 uint16_t RESERVED9; /*!< Reserved, 0x2A */
bogdanm 82:6473597d706e 983 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 82:6473597d706e 984 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 82:6473597d706e 985 uint16_t RESERVED10; /*!< Reserved, 0x32 */
bogdanm 82:6473597d706e 986 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 82:6473597d706e 987 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 82:6473597d706e 988 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 82:6473597d706e 989 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 82:6473597d706e 990 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 82:6473597d706e 991 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 82:6473597d706e 992 uint16_t RESERVED12; /*!< Reserved, 0x4A */
bogdanm 82:6473597d706e 993 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
bogdanm 82:6473597d706e 994 uint16_t RESERVED13; /*!< Reserved, 0x4E */
bogdanm 82:6473597d706e 995 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 82:6473597d706e 996 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
bogdanm 82:6473597d706e 997 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
bogdanm 82:6473597d706e 998 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
bogdanm 82:6473597d706e 999 } TIM_TypeDef;
bogdanm 82:6473597d706e 1000
bogdanm 82:6473597d706e 1001
bogdanm 82:6473597d706e 1002 /**
bogdanm 82:6473597d706e 1003 * @brief Touch Sensing Controller (TSC)
bogdanm 82:6473597d706e 1004 */
bogdanm 82:6473597d706e 1005 typedef struct
bogdanm 82:6473597d706e 1006 {
bogdanm 82:6473597d706e 1007 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 1008 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
bogdanm 82:6473597d706e 1009 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
bogdanm 82:6473597d706e 1010 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
bogdanm 82:6473597d706e 1011 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
bogdanm 82:6473597d706e 1012 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
bogdanm 82:6473597d706e 1013 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
bogdanm 82:6473597d706e 1014 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
bogdanm 82:6473597d706e 1015 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
bogdanm 82:6473597d706e 1016 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
bogdanm 82:6473597d706e 1017 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
bogdanm 82:6473597d706e 1018 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
bogdanm 82:6473597d706e 1019 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
bogdanm 82:6473597d706e 1020 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
bogdanm 82:6473597d706e 1021 } TSC_TypeDef;
bogdanm 82:6473597d706e 1022
bogdanm 82:6473597d706e 1023 /**
bogdanm 82:6473597d706e 1024 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 82:6473597d706e 1025 */
bogdanm 82:6473597d706e 1026
bogdanm 82:6473597d706e 1027 typedef struct
bogdanm 82:6473597d706e 1028 {
bogdanm 82:6473597d706e 1029 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
bogdanm 82:6473597d706e 1030 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
bogdanm 82:6473597d706e 1031 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
bogdanm 82:6473597d706e 1032 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
bogdanm 82:6473597d706e 1033 uint16_t RESERVED1; /*!< Reserved, 0x0E */
bogdanm 82:6473597d706e 1034 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
bogdanm 82:6473597d706e 1035 uint16_t RESERVED2; /*!< Reserved, 0x12 */
bogdanm 82:6473597d706e 1036 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
bogdanm 82:6473597d706e 1037 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
bogdanm 82:6473597d706e 1038 uint16_t RESERVED3; /*!< Reserved, 0x1A */
bogdanm 82:6473597d706e 1039 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
bogdanm 82:6473597d706e 1040 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
bogdanm 82:6473597d706e 1041 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
bogdanm 82:6473597d706e 1042 uint16_t RESERVED4; /*!< Reserved, 0x26 */
bogdanm 82:6473597d706e 1043 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
bogdanm 82:6473597d706e 1044 uint16_t RESERVED5; /*!< Reserved, 0x2A */
bogdanm 82:6473597d706e 1045 } USART_TypeDef;
bogdanm 82:6473597d706e 1046
bogdanm 82:6473597d706e 1047 /**
bogdanm 82:6473597d706e 1048 * @brief Window WATCHDOG
bogdanm 82:6473597d706e 1049 */
bogdanm 82:6473597d706e 1050 typedef struct
bogdanm 82:6473597d706e 1051 {
bogdanm 82:6473597d706e 1052 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 82:6473597d706e 1053 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 82:6473597d706e 1054 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 82:6473597d706e 1055 } WWDG_TypeDef;
bogdanm 82:6473597d706e 1056
bogdanm 82:6473597d706e 1057
bogdanm 82:6473597d706e 1058 /** @addtogroup Peripheral_memory_map
bogdanm 82:6473597d706e 1059 * @{
bogdanm 82:6473597d706e 1060 */
bogdanm 82:6473597d706e 1061
bogdanm 82:6473597d706e 1062 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
bogdanm 82:6473597d706e 1063 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
bogdanm 82:6473597d706e 1064 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 82:6473597d706e 1065
bogdanm 82:6473597d706e 1066 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
bogdanm 82:6473597d706e 1067 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
bogdanm 82:6473597d706e 1068
bogdanm 82:6473597d706e 1069
bogdanm 82:6473597d706e 1070 /*!< Peripheral memory map */
bogdanm 82:6473597d706e 1071 #define APB1PERIPH_BASE PERIPH_BASE
bogdanm 82:6473597d706e 1072 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm 82:6473597d706e 1073 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 82:6473597d706e 1074 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
bogdanm 82:6473597d706e 1075 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm 82:6473597d706e 1076
bogdanm 82:6473597d706e 1077 /*!< APB1 peripherals */
bogdanm 82:6473597d706e 1078 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
bogdanm 82:6473597d706e 1079 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
bogdanm 82:6473597d706e 1080 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
bogdanm 82:6473597d706e 1081 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
bogdanm 82:6473597d706e 1082 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
bogdanm 82:6473597d706e 1083 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
bogdanm 82:6473597d706e 1084 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
bogdanm 82:6473597d706e 1085 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
bogdanm 82:6473597d706e 1086 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
bogdanm 82:6473597d706e 1087 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
bogdanm 82:6473597d706e 1088 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
bogdanm 82:6473597d706e 1089 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
bogdanm 82:6473597d706e 1090 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
bogdanm 82:6473597d706e 1091 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
bogdanm 82:6473597d706e 1092 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
bogdanm 82:6473597d706e 1093 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
bogdanm 82:6473597d706e 1094 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
bogdanm 82:6473597d706e 1095 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
bogdanm 82:6473597d706e 1096 #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400)
bogdanm 82:6473597d706e 1097 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
bogdanm 82:6473597d706e 1098 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
bogdanm 82:6473597d706e 1099 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
bogdanm 82:6473597d706e 1100 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
bogdanm 82:6473597d706e 1101 #define DAC_BASE DAC1_BASE
bogdanm 82:6473597d706e 1102
bogdanm 82:6473597d706e 1103 /*!< APB2 peripherals */
bogdanm 82:6473597d706e 1104 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
bogdanm 82:6473597d706e 1105 #define COMP_BASE (APB2PERIPH_BASE + 0x0000001C)
bogdanm 82:6473597d706e 1106 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
bogdanm 82:6473597d706e 1107 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
bogdanm 82:6473597d706e 1108 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
bogdanm 82:6473597d706e 1109 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
bogdanm 82:6473597d706e 1110 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
bogdanm 82:6473597d706e 1111 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
bogdanm 82:6473597d706e 1112 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
bogdanm 82:6473597d706e 1113 #define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038)
bogdanm 82:6473597d706e 1114 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
bogdanm 82:6473597d706e 1115 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
bogdanm 82:6473597d706e 1116 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
bogdanm 82:6473597d706e 1117 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
bogdanm 82:6473597d706e 1118 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
bogdanm 82:6473597d706e 1119 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
bogdanm 82:6473597d706e 1120 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
bogdanm 82:6473597d706e 1121 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
bogdanm 82:6473597d706e 1122 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
bogdanm 82:6473597d706e 1123 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
bogdanm 82:6473597d706e 1124 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
bogdanm 82:6473597d706e 1125 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
bogdanm 82:6473597d706e 1126 #define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400)
bogdanm 82:6473597d706e 1127 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
bogdanm 82:6473597d706e 1128 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
bogdanm 82:6473597d706e 1129 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
bogdanm 82:6473597d706e 1130 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
bogdanm 82:6473597d706e 1131 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
bogdanm 82:6473597d706e 1132 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
bogdanm 82:6473597d706e 1133
bogdanm 82:6473597d706e 1134 /*!< AHB1 peripherals */
bogdanm 82:6473597d706e 1135 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
bogdanm 82:6473597d706e 1136 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
bogdanm 82:6473597d706e 1137 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
bogdanm 82:6473597d706e 1138 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
bogdanm 82:6473597d706e 1139 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
bogdanm 82:6473597d706e 1140 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
bogdanm 82:6473597d706e 1141 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
bogdanm 82:6473597d706e 1142 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
bogdanm 82:6473597d706e 1143 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
bogdanm 82:6473597d706e 1144 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
bogdanm 82:6473597d706e 1145 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
bogdanm 82:6473597d706e 1146 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
bogdanm 82:6473597d706e 1147 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
bogdanm 82:6473597d706e 1148 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
bogdanm 82:6473597d706e 1149 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
bogdanm 82:6473597d706e 1150 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
bogdanm 82:6473597d706e 1151 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
bogdanm 82:6473597d706e 1152 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
bogdanm 82:6473597d706e 1153 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
bogdanm 82:6473597d706e 1154
bogdanm 82:6473597d706e 1155 /*!< AHB2 peripherals */
bogdanm 82:6473597d706e 1156 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
bogdanm 82:6473597d706e 1157 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
bogdanm 82:6473597d706e 1158 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
bogdanm 82:6473597d706e 1159 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
bogdanm 82:6473597d706e 1160 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
bogdanm 82:6473597d706e 1161 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
bogdanm 82:6473597d706e 1162
bogdanm 82:6473597d706e 1163 /*!< AHB3 peripherals */
bogdanm 82:6473597d706e 1164 #define ADC1_BASE (AHB3PERIPH_BASE + 0x0000)
bogdanm 82:6473597d706e 1165 #define ADC2_BASE (AHB3PERIPH_BASE + 0x0100)
bogdanm 82:6473597d706e 1166 #define ADC1_2_BASE (AHB3PERIPH_BASE + 0x0300)
bogdanm 82:6473597d706e 1167 #define ADC3_BASE (AHB3PERIPH_BASE + 0x0400)
bogdanm 82:6473597d706e 1168 #define ADC4_BASE (AHB3PERIPH_BASE + 0x0500)
bogdanm 82:6473597d706e 1169 #define ADC3_4_BASE (AHB3PERIPH_BASE + 0x0700)
bogdanm 82:6473597d706e 1170
bogdanm 82:6473597d706e 1171 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
bogdanm 82:6473597d706e 1172 /**
bogdanm 82:6473597d706e 1173 * @}
bogdanm 82:6473597d706e 1174 */
bogdanm 82:6473597d706e 1175
bogdanm 82:6473597d706e 1176 /** @addtogroup Peripheral_declaration
bogdanm 82:6473597d706e 1177 * @{
bogdanm 82:6473597d706e 1178 */
bogdanm 82:6473597d706e 1179 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 82:6473597d706e 1180 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 82:6473597d706e 1181 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm 82:6473597d706e 1182 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 82:6473597d706e 1183 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 82:6473597d706e 1184 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 82:6473597d706e 1185 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 82:6473597d706e 1186 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 82:6473597d706e 1187 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
bogdanm 82:6473597d706e 1188 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 82:6473597d706e 1189 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm 82:6473597d706e 1190 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
bogdanm 82:6473597d706e 1191 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 82:6473597d706e 1192 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 82:6473597d706e 1193 #define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm 82:6473597d706e 1194 #define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm 82:6473597d706e 1195 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 82:6473597d706e 1196 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 82:6473597d706e 1197 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm 82:6473597d706e 1198 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm 82:6473597d706e 1199 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 82:6473597d706e 1200 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
bogdanm 82:6473597d706e 1201 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
bogdanm 82:6473597d706e 1202 #define DAC DAC1
bogdanm 82:6473597d706e 1203 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 82:6473597d706e 1204 #define COMP ((COMP_TypeDef *) COMP_BASE)
bogdanm 82:6473597d706e 1205 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
bogdanm 82:6473597d706e 1206 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
bogdanm 82:6473597d706e 1207 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
bogdanm 82:6473597d706e 1208 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
bogdanm 82:6473597d706e 1209 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
bogdanm 82:6473597d706e 1210 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
bogdanm 82:6473597d706e 1211 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
bogdanm 82:6473597d706e 1212 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
bogdanm 82:6473597d706e 1213 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
bogdanm 82:6473597d706e 1214 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
bogdanm 82:6473597d706e 1215 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
bogdanm 82:6473597d706e 1216 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
bogdanm 82:6473597d706e 1217 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 82:6473597d706e 1218 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 82:6473597d706e 1219 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 82:6473597d706e 1220 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm 82:6473597d706e 1221 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 82:6473597d706e 1222 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm 82:6473597d706e 1223 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm 82:6473597d706e 1224 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm 82:6473597d706e 1225 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
bogdanm 82:6473597d706e 1226 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
bogdanm 82:6473597d706e 1227 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
bogdanm 82:6473597d706e 1228 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
bogdanm 82:6473597d706e 1229 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
bogdanm 82:6473597d706e 1230 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
bogdanm 82:6473597d706e 1231 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
bogdanm 82:6473597d706e 1232 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 82:6473597d706e 1233 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 82:6473597d706e 1234 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm 82:6473597d706e 1235 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm 82:6473597d706e 1236 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm 82:6473597d706e 1237 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm 82:6473597d706e 1238 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm 82:6473597d706e 1239 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm 82:6473597d706e 1240 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm 82:6473597d706e 1241 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm 82:6473597d706e 1242 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
bogdanm 82:6473597d706e 1243 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
bogdanm 82:6473597d706e 1244 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
bogdanm 82:6473597d706e 1245 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
bogdanm 82:6473597d706e 1246 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
bogdanm 82:6473597d706e 1247 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 82:6473597d706e 1248 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 82:6473597d706e 1249 #define OB ((OB_TypeDef *) OB_BASE)
bogdanm 82:6473597d706e 1250 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 82:6473597d706e 1251 #define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm 82:6473597d706e 1252 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 82:6473597d706e 1253 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 82:6473597d706e 1254 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 82:6473597d706e 1255 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 82:6473597d706e 1256 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 82:6473597d706e 1257 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 82:6473597d706e 1258 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 82:6473597d706e 1259 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm 82:6473597d706e 1260 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm 82:6473597d706e 1261 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
bogdanm 82:6473597d706e 1262 #define ADC1_2 ((ADC_Common_TypeDef *) ADC1_2_BASE)
bogdanm 82:6473597d706e 1263 #define ADC3_4 ((ADC_Common_TypeDef *) ADC3_4_BASE)
bogdanm 82:6473597d706e 1264 /**
bogdanm 82:6473597d706e 1265 * @}
bogdanm 82:6473597d706e 1266 */
bogdanm 82:6473597d706e 1267
bogdanm 82:6473597d706e 1268 /** @addtogroup Exported_constants
bogdanm 82:6473597d706e 1269 * @{
bogdanm 82:6473597d706e 1270 */
bogdanm 82:6473597d706e 1271
bogdanm 82:6473597d706e 1272 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 82:6473597d706e 1273 * @{
bogdanm 82:6473597d706e 1274 */
bogdanm 82:6473597d706e 1275
bogdanm 82:6473597d706e 1276 /******************************************************************************/
bogdanm 82:6473597d706e 1277 /* Peripheral Registers_Bits_Definition */
bogdanm 82:6473597d706e 1278 /******************************************************************************/
bogdanm 82:6473597d706e 1279 /******************************************************************************/
bogdanm 82:6473597d706e 1280 /* */
bogdanm 82:6473597d706e 1281 /* High Resolution Timer (HRTIM) */
bogdanm 82:6473597d706e 1282 /* */
bogdanm 82:6473597d706e 1283 /******************************************************************************/
bogdanm 82:6473597d706e 1284 /******************** Master Timer control register ***************************/
bogdanm 82:6473597d706e 1285 #define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /*!< Prescaler mask */
bogdanm 82:6473597d706e 1286 #define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< Prescaler bit 0 */
bogdanm 82:6473597d706e 1287 #define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< Prescaler bit 1 */
bogdanm 82:6473597d706e 1288 #define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< Prescaler bit 2 */
bogdanm 82:6473597d706e 1289
bogdanm 82:6473597d706e 1290 #define HRTIM_MCR_CONT ((uint32_t)0x00000008) /*!< Continuous mode */
bogdanm 82:6473597d706e 1291 #define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /*!< Rettrigreable mode */
bogdanm 82:6473597d706e 1292 #define HRTIM_MCR_HALF ((uint32_t)0x00000020) /*!< Half mode */
bogdanm 82:6473597d706e 1293
bogdanm 82:6473597d706e 1294 #define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /*!< Synchronization input master */
bogdanm 82:6473597d706e 1295 #define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /*!< Synchronization input bit 0 */
bogdanm 82:6473597d706e 1296 #define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /*!< Synchronization input bit 1 */
bogdanm 82:6473597d706e 1297 #define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /*!< Synchronization reset master */
bogdanm 82:6473597d706e 1298 #define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /*!< Synchronization start master */
bogdanm 82:6473597d706e 1299 #define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /*!< Synchronization output master */
bogdanm 82:6473597d706e 1300 #define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /*!< Synchronization output bit 0 */
bogdanm 82:6473597d706e 1301 #define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /*!< Synchronization output bit 1 */
bogdanm 82:6473597d706e 1302 #define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /*!< Synchronization source */
bogdanm 82:6473597d706e 1303 #define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /*!< Synchronization source bit 0 */
bogdanm 82:6473597d706e 1304 #define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /*!< Synchronization source bit 1 */
bogdanm 82:6473597d706e 1305
bogdanm 82:6473597d706e 1306 #define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /*!< Master counter enable */
bogdanm 82:6473597d706e 1307 #define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /*!< Timer A counter enable */
bogdanm 82:6473597d706e 1308 #define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /*!< Timer B counter enable */
bogdanm 82:6473597d706e 1309 #define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /*!< Timer C counter enable */
bogdanm 82:6473597d706e 1310 #define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /*!< Timer D counter enable */
bogdanm 82:6473597d706e 1311 #define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /*!< Timer E counter enable */
bogdanm 82:6473597d706e 1312
bogdanm 82:6473597d706e 1313 #define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */
bogdanm 82:6473597d706e 1314 #define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */
bogdanm 82:6473597d706e 1315 #define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */
bogdanm 82:6473597d706e 1316
bogdanm 82:6473597d706e 1317 #define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /*!< Master preload enable */
bogdanm 82:6473597d706e 1318 #define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /*!< Master repetition update */
bogdanm 82:6473597d706e 1319
bogdanm 82:6473597d706e 1320 #define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /*!< Burst DMA update */
bogdanm 82:6473597d706e 1321 #define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /*!< Burst DMA update bit 0*/
bogdanm 82:6473597d706e 1322 #define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /*!< Burst DMA update bit 1 */
bogdanm 82:6473597d706e 1323
bogdanm 82:6473597d706e 1324 /******************** Master Timer Interrupt status register ******************/
bogdanm 82:6473597d706e 1325 #define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag */
bogdanm 82:6473597d706e 1326 #define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag */
bogdanm 82:6473597d706e 1327 #define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag */
bogdanm 82:6473597d706e 1328 #define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag */
bogdanm 82:6473597d706e 1329 #define HRTIM_MISR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag */
bogdanm 82:6473597d706e 1330 #define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag */
bogdanm 82:6473597d706e 1331 #define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag */
bogdanm 82:6473597d706e 1332
bogdanm 82:6473597d706e 1333 /******************** Master Timer Interrupt clear register *******************/
bogdanm 82:6473597d706e 1334 #define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag clear */
bogdanm 82:6473597d706e 1335 #define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag clear */
bogdanm 82:6473597d706e 1336 #define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag clear */
bogdanm 82:6473597d706e 1337 #define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag clear */
bogdanm 82:6473597d706e 1338 #define HRTIM_MICR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag clear */
bogdanm 82:6473597d706e 1339 #define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag clear */
bogdanm 82:6473597d706e 1340 #define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag clear */
bogdanm 82:6473597d706e 1341
bogdanm 82:6473597d706e 1342 /******************** Master Timer DMA/Interrupt enable register **************/
bogdanm 82:6473597d706e 1343 #define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /*!< Master compare 1 interrupt enable */
bogdanm 82:6473597d706e 1344 #define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /*!< Master compare 2 interrupt enable */
bogdanm 82:6473597d706e 1345 #define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /*!< Master compare 3 interrupt enable */
bogdanm 82:6473597d706e 1346 #define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /*!< Master compare 4 interrupt enable */
bogdanm 82:6473597d706e 1347 #define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /*!< Master Repetition interrupt enable */
bogdanm 82:6473597d706e 1348 #define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /*!< Synchronization input interrupt enable */
bogdanm 82:6473597d706e 1349 #define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /*!< Master update interrupt enable */
bogdanm 82:6473597d706e 1350
bogdanm 82:6473597d706e 1351 #define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /*!< Master compare 1 DMA enable */
bogdanm 82:6473597d706e 1352 #define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /*!< Master compare 2 DMA enable */
bogdanm 82:6473597d706e 1353 #define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /*!< Master compare 3 DMA enable */
bogdanm 82:6473597d706e 1354 #define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /*!< Master compare 4 DMA enable */
bogdanm 82:6473597d706e 1355 #define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /*!< Master Repetition DMA enable */
bogdanm 82:6473597d706e 1356 #define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /*!< Synchronization input DMA enable */
bogdanm 82:6473597d706e 1357 #define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /*!< Master update DMA enable */
bogdanm 82:6473597d706e 1358
bogdanm 82:6473597d706e 1359 /******************* Bit definition for HRTIM_MCNTR register ****************/
bogdanm 82:6473597d706e 1360 #define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
bogdanm 82:6473597d706e 1361
bogdanm 82:6473597d706e 1362 /******************* Bit definition for HRTIM_MPER register *****************/
bogdanm 82:6473597d706e 1363 #define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /*!< Period Value */
bogdanm 82:6473597d706e 1364
bogdanm 82:6473597d706e 1365 /******************* Bit definition for HRTIM_MREP register *****************/
bogdanm 82:6473597d706e 1366 #define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /*!<Repetition Value */
bogdanm 82:6473597d706e 1367
bogdanm 82:6473597d706e 1368 /******************* Bit definition for HRTIM_MCMP1R register *****************/
bogdanm 82:6473597d706e 1369 #define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
bogdanm 82:6473597d706e 1370
bogdanm 82:6473597d706e 1371 /******************* Bit definition for HRTIM_MCMP2R register *****************/
bogdanm 82:6473597d706e 1372 #define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
bogdanm 82:6473597d706e 1373
bogdanm 82:6473597d706e 1374 /******************* Bit definition for HRTIM_MCMP3R register *****************/
bogdanm 82:6473597d706e 1375 #define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
bogdanm 82:6473597d706e 1376
bogdanm 82:6473597d706e 1377 /******************* Bit definition for HRTIM_MCMP4R register *****************/
bogdanm 82:6473597d706e 1378 #define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
bogdanm 82:6473597d706e 1379
bogdanm 82:6473597d706e 1380 /******************** Slave control register **********************************/
bogdanm 82:6473597d706e 1381 #define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/
bogdanm 82:6473597d706e 1382 #define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< prescaler bit 0 */
bogdanm 82:6473597d706e 1383 #define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< prescaler bit 1 */
bogdanm 82:6473597d706e 1384 #define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< prescaler bit 2 */
bogdanm 82:6473597d706e 1385
bogdanm 82:6473597d706e 1386 #define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /*!< Slave continuous mode */
bogdanm 82:6473597d706e 1387 #define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /*!< Slave Retrigreable mode */
bogdanm 82:6473597d706e 1388 #define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /*!< Slave Half mode */
bogdanm 82:6473597d706e 1389 #define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /*!< Slave push-pull mode */
bogdanm 82:6473597d706e 1390
bogdanm 82:6473597d706e 1391 #define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /*!< Slave synchronization resets */
bogdanm 82:6473597d706e 1392 #define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /*!< Slave synchronization starts */
bogdanm 82:6473597d706e 1393
bogdanm 82:6473597d706e 1394 #define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /*!< Slave delayed comparator 2 mode mask */
bogdanm 82:6473597d706e 1395 #define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /*!< Slave delayed comparator 2 bit 0 */
bogdanm 82:6473597d706e 1396 #define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /*!< Slave delayed comparator 2 bit 1 */
bogdanm 82:6473597d706e 1397 #define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /*!< Slave delayed comparator 4 mode mask */
bogdanm 82:6473597d706e 1398 #define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /*!< Slave delayed comparator 4 bit 0 */
bogdanm 82:6473597d706e 1399 #define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /*!< Slave delayed comparator 4 bit 1 */
bogdanm 82:6473597d706e 1400
bogdanm 82:6473597d706e 1401 #define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /*!< Slave repetition update */
bogdanm 82:6473597d706e 1402 #define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /*!< Slave reset update */
bogdanm 82:6473597d706e 1403 #define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /*!< Slave Timer A update reserved for TIM A */
bogdanm 82:6473597d706e 1404 #define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /*!< Slave Timer B update reserved for TIM B */
bogdanm 82:6473597d706e 1405 #define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /*!< Slave Timer C update reserved for TIM C */
bogdanm 82:6473597d706e 1406 #define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /*!< Slave Timer D update reserved for TIM D */
bogdanm 82:6473597d706e 1407 #define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /*!< Slave Timer E update reserved for TIM E */
bogdanm 82:6473597d706e 1408 #define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /*!< Master Update */
bogdanm 82:6473597d706e 1409
bogdanm 82:6473597d706e 1410 #define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */
bogdanm 82:6473597d706e 1411 #define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */
bogdanm 82:6473597d706e 1412 #define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */
bogdanm 82:6473597d706e 1413 #define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /*!< Slave preload enable */
bogdanm 82:6473597d706e 1414
bogdanm 82:6473597d706e 1415 #define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /*!< Slave update gating mask */
bogdanm 82:6473597d706e 1416 #define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /*!< Update gating bit 0 */
bogdanm 82:6473597d706e 1417 #define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /*!< Update gating bit 1 */
bogdanm 82:6473597d706e 1418 #define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /*!< Update gating bit 2 */
bogdanm 82:6473597d706e 1419 #define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /*!< Update gating bit 3 */
bogdanm 82:6473597d706e 1420
bogdanm 82:6473597d706e 1421 /******************** Slave Interrupt status register **************************/
bogdanm 82:6473597d706e 1422 #define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt flag */
bogdanm 82:6473597d706e 1423 #define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt flag */
bogdanm 82:6473597d706e 1424 #define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt flag */
bogdanm 82:6473597d706e 1425 #define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt flag */
bogdanm 82:6473597d706e 1426 #define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /*!< Slave repetition interrupt flag */
bogdanm 82:6473597d706e 1427 #define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /*!< Slave update interrupt flag */
bogdanm 82:6473597d706e 1428 #define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt flag */
bogdanm 82:6473597d706e 1429 #define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt flag */
bogdanm 82:6473597d706e 1430 #define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt flag */
bogdanm 82:6473597d706e 1431 #define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt flag */
bogdanm 82:6473597d706e 1432 #define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt flag */
bogdanm 82:6473597d706e 1433 #define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt flag */
bogdanm 82:6473597d706e 1434 #define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /*!< Slave reset interrupt flag */
bogdanm 82:6473597d706e 1435 #define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /*!< Slave output 1 delay protection interrupt flag */
bogdanm 82:6473597d706e 1436 #define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /*!< Slave current push-pull flag */
bogdanm 82:6473597d706e 1437 #define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /*!< Slave idle push-pull flag */
bogdanm 82:6473597d706e 1438 #define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /*!< Slave output 1 state flag */
bogdanm 82:6473597d706e 1439 #define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /*!< Slave output 2 state flag */
bogdanm 82:6473597d706e 1440 #define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /*!< Slave output 1 copy flag */
bogdanm 82:6473597d706e 1441 #define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /*!< Slave output 2 copy flag */
bogdanm 82:6473597d706e 1442
bogdanm 82:6473597d706e 1443 /******************** Slave Interrupt clear register **************************/
bogdanm 82:6473597d706e 1444 #define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /*!< Slave compare 1 clear flag */
bogdanm 82:6473597d706e 1445 #define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /*!< Slave compare 2 clear flag */
bogdanm 82:6473597d706e 1446 #define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /*!< Slave compare 3 clear flag */
bogdanm 82:6473597d706e 1447 #define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /*!< Slave compare 4 clear flag */
bogdanm 82:6473597d706e 1448 #define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /*!< Slave repetition clear flag */
bogdanm 82:6473597d706e 1449 #define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /*!< Slave update clear flag */
bogdanm 82:6473597d706e 1450 #define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /*!< Slave capture 1 clear flag */
bogdanm 82:6473597d706e 1451 #define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /*!< Slave capture 2 clear flag */
bogdanm 82:6473597d706e 1452 #define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /*!< Slave output 1 set clear flag */
bogdanm 82:6473597d706e 1453 #define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /*!< Slave output 1 reset clear flag */
bogdanm 82:6473597d706e 1454 #define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /*!< Slave output 2 set clear flag */
bogdanm 82:6473597d706e 1455 #define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /*!< Slave output 2 reset clear flag */
bogdanm 82:6473597d706e 1456 #define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /*!< Slave reset clear flag */
bogdanm 82:6473597d706e 1457 #define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /*!< Slave output 1 delay protection clear flag */
bogdanm 82:6473597d706e 1458 #define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /*!< Slave output 2 delay protection clear flag */
bogdanm 82:6473597d706e 1459
bogdanm 82:6473597d706e 1460 /******************** Slave DMA/Interrupt enable register *********************/
bogdanm 82:6473597d706e 1461 #define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt enable */
bogdanm 82:6473597d706e 1462 #define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt enable */
bogdanm 82:6473597d706e 1463 #define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt enable */
bogdanm 82:6473597d706e 1464 #define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt enable */
bogdanm 82:6473597d706e 1465 #define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /*!< Slave repetition interrupt enable */
bogdanm 82:6473597d706e 1466 #define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /*!< Slave update interrupt enable */
bogdanm 82:6473597d706e 1467 #define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt enable */
bogdanm 82:6473597d706e 1468 #define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt enable */
bogdanm 82:6473597d706e 1469 #define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt enable */
bogdanm 82:6473597d706e 1470 #define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt enable */
bogdanm 82:6473597d706e 1471 #define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt enable */
bogdanm 82:6473597d706e 1472 #define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt enable */
bogdanm 82:6473597d706e 1473 #define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /*!< Slave reset interrupt enable */
bogdanm 82:6473597d706e 1474 #define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /*!< Slave delay protection interrupt enable */
bogdanm 82:6473597d706e 1475
bogdanm 82:6473597d706e 1476 #define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /*!< Slave compare 1 request enable */
bogdanm 82:6473597d706e 1477 #define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /*!< Slave compare 2 request enable */
bogdanm 82:6473597d706e 1478 #define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /*!< Slave compare 3 request enable */
bogdanm 82:6473597d706e 1479 #define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /*!< Slave compare 4 request enable */
bogdanm 82:6473597d706e 1480 #define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /*!< Slave repetition request enable */
bogdanm 82:6473597d706e 1481 #define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /*!< Slave update request enable */
bogdanm 82:6473597d706e 1482 #define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /*!< Slave capture 1 request enable */
bogdanm 82:6473597d706e 1483 #define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /*!< Slave capture 2 request enable */
bogdanm 82:6473597d706e 1484 #define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /*!< Slave output 1 set request enable */
bogdanm 82:6473597d706e 1485 #define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /*!< Slave output 1 reset request enable */
bogdanm 82:6473597d706e 1486 #define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /*!< Slave output 2 set request enable */
bogdanm 82:6473597d706e 1487 #define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /*!< Slave output 2 reset request enable */
bogdanm 82:6473597d706e 1488 #define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /*!< Slave reset request enable */
bogdanm 82:6473597d706e 1489 #define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /*!< Slave delay protection request enable */
bogdanm 82:6473597d706e 1490
bogdanm 82:6473597d706e 1491 /****************** Bit definition for HRTIM_CNTR register ****************/
bogdanm 82:6473597d706e 1492 #define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /*!< Counter Value */
bogdanm 82:6473597d706e 1493
bogdanm 82:6473597d706e 1494 /******************* Bit definition for HRTIM_PER register *****************/
bogdanm 82:6473597d706e 1495 #define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /*!< Period Value */
bogdanm 82:6473597d706e 1496
bogdanm 82:6473597d706e 1497 /******************* Bit definition for HRTIM_REP register *****************/
bogdanm 82:6473597d706e 1498 #define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /*!< Repetition Value */
bogdanm 82:6473597d706e 1499
bogdanm 82:6473597d706e 1500 /******************* Bit definition for HRTIM_CMP1R register *****************/
bogdanm 82:6473597d706e 1501 #define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 82:6473597d706e 1502
bogdanm 82:6473597d706e 1503 /******************* Bit definition for HRTIM_CMP1CR register *****************/
bogdanm 82:6473597d706e 1504 #define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 82:6473597d706e 1505
bogdanm 82:6473597d706e 1506 /******************* Bit definition for HRTIM_CMP2R register *****************/
bogdanm 82:6473597d706e 1507 #define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 82:6473597d706e 1508
bogdanm 82:6473597d706e 1509 /******************* Bit definition for HRTIM_CMP3R register *****************/
bogdanm 82:6473597d706e 1510 #define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 82:6473597d706e 1511
bogdanm 82:6473597d706e 1512 /******************* Bit definition for HRTIM_CMP4R register *****************/
bogdanm 82:6473597d706e 1513 #define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 82:6473597d706e 1514
bogdanm 82:6473597d706e 1515 /******************* Bit definition for HRTIM_CPT1R register ****************/
bogdanm 82:6473597d706e 1516 #define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */
bogdanm 82:6473597d706e 1517
bogdanm 82:6473597d706e 1518 /******************* Bit definition for HRTIM_CPT2R register ****************/
bogdanm 82:6473597d706e 1519 #define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */
bogdanm 82:6473597d706e 1520
bogdanm 82:6473597d706e 1521 /******************** Bit definition for Slave Deadtime register **************/
bogdanm 82:6473597d706e 1522 #define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /*!< Dead time rising value */
bogdanm 82:6473597d706e 1523 #define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /*!< Dead time rising bit 0 */
bogdanm 82:6473597d706e 1524 #define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /*!< Dead time rising bit 1 */
bogdanm 82:6473597d706e 1525 #define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /*!< Dead time rising bit 2 */
bogdanm 82:6473597d706e 1526 #define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /*!< Dead time rising bit 3 */
bogdanm 82:6473597d706e 1527 #define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /*!< Dead time rising bit 4 */
bogdanm 82:6473597d706e 1528 #define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /*!< Dead time rising bit 5 */
bogdanm 82:6473597d706e 1529 #define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /*!< Dead time rising bit 6 */
bogdanm 82:6473597d706e 1530 #define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /*!< Dead time rising bit 7 */
bogdanm 82:6473597d706e 1531 #define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /*!< Dead time rising bit 8 */
bogdanm 82:6473597d706e 1532 #define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /*!< Sign dead time rising value */
bogdanm 82:6473597d706e 1533 #define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /*!< Dead time prescaler */
bogdanm 82:6473597d706e 1534 #define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /*!< Dead time prescaler bit 0 */
bogdanm 82:6473597d706e 1535 #define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /*!< Dead time prescaler bit 1 */
bogdanm 82:6473597d706e 1536 #define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /*!< Dead time prescaler bit 2 */
bogdanm 82:6473597d706e 1537 #define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /*!< Dead time rising sign lock */
bogdanm 82:6473597d706e 1538 #define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /*!< Dead time rising lock */
bogdanm 82:6473597d706e 1539 #define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /*!< Dead time falling value */
bogdanm 82:6473597d706e 1540 #define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /*!< Dead time falling bit 0 */
bogdanm 82:6473597d706e 1541 #define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /*!< Dead time falling bit 1 */
bogdanm 82:6473597d706e 1542 #define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /*!< Dead time falling bit 2 */
bogdanm 82:6473597d706e 1543 #define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /*!< Dead time falling bit 3 */
bogdanm 82:6473597d706e 1544 #define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /*!< Dead time falling bit 4 */
bogdanm 82:6473597d706e 1545 #define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /*!< Dead time falling bit 5 */
bogdanm 82:6473597d706e 1546 #define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /*!< Dead time falling bit 6 */
bogdanm 82:6473597d706e 1547 #define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /*!< Dead time falling bit 7 */
bogdanm 82:6473597d706e 1548 #define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /*!< Dead time falling bit 8 */
bogdanm 82:6473597d706e 1549 #define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /*!< Sign dead time falling value */
bogdanm 82:6473597d706e 1550 #define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /*!< Dead time falling sign lock */
bogdanm 82:6473597d706e 1551 #define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /*!< Dead time falling lock */
bogdanm 82:6473597d706e 1552
bogdanm 82:6473597d706e 1553 /**** Bit definition for Slave Output 1 set register **************************/
bogdanm 82:6473597d706e 1554 #define HRTIM_SET1R_SST ((uint32_t)0x00000001) /*!< software set trigger */
bogdanm 82:6473597d706e 1555 #define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
bogdanm 82:6473597d706e 1556 #define HRTIM_SET1R_PER ((uint32_t)0x00000004) /*!< Timer A period */
bogdanm 82:6473597d706e 1557 #define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
bogdanm 82:6473597d706e 1558 #define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
bogdanm 82:6473597d706e 1559 #define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
bogdanm 82:6473597d706e 1560 #define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
bogdanm 82:6473597d706e 1561
bogdanm 82:6473597d706e 1562 #define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
bogdanm 82:6473597d706e 1563 #define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
bogdanm 82:6473597d706e 1564 #define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
bogdanm 82:6473597d706e 1565 #define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
bogdanm 82:6473597d706e 1566 #define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
bogdanm 82:6473597d706e 1567
bogdanm 82:6473597d706e 1568 #define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
bogdanm 82:6473597d706e 1569 #define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
bogdanm 82:6473597d706e 1570 #define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
bogdanm 82:6473597d706e 1571 #define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
bogdanm 82:6473597d706e 1572 #define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
bogdanm 82:6473597d706e 1573 #define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
bogdanm 82:6473597d706e 1574 #define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
bogdanm 82:6473597d706e 1575 #define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
bogdanm 82:6473597d706e 1576 #define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
bogdanm 82:6473597d706e 1577
bogdanm 82:6473597d706e 1578 #define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
bogdanm 82:6473597d706e 1579 #define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
bogdanm 82:6473597d706e 1580 #define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
bogdanm 82:6473597d706e 1581 #define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
bogdanm 82:6473597d706e 1582 #define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
bogdanm 82:6473597d706e 1583 #define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
bogdanm 82:6473597d706e 1584 #define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
bogdanm 82:6473597d706e 1585 #define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
bogdanm 82:6473597d706e 1586 #define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
bogdanm 82:6473597d706e 1587 #define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
bogdanm 82:6473597d706e 1588
bogdanm 82:6473597d706e 1589 #define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
bogdanm 82:6473597d706e 1590
bogdanm 82:6473597d706e 1591 /**** Bit definition for Slave Output 1 reset register ************************/
bogdanm 82:6473597d706e 1592 #define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */
bogdanm 82:6473597d706e 1593 #define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
bogdanm 82:6473597d706e 1594 #define HRTIM_RST1R_PER ((uint32_t)0x00000004) /*!< Timer A period */
bogdanm 82:6473597d706e 1595 #define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
bogdanm 82:6473597d706e 1596 #define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
bogdanm 82:6473597d706e 1597 #define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
bogdanm 82:6473597d706e 1598 #define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
bogdanm 82:6473597d706e 1599
bogdanm 82:6473597d706e 1600 #define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
bogdanm 82:6473597d706e 1601 #define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
bogdanm 82:6473597d706e 1602 #define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
bogdanm 82:6473597d706e 1603 #define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
bogdanm 82:6473597d706e 1604 #define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
bogdanm 82:6473597d706e 1605
bogdanm 82:6473597d706e 1606 #define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
bogdanm 82:6473597d706e 1607 #define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
bogdanm 82:6473597d706e 1608 #define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
bogdanm 82:6473597d706e 1609 #define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
bogdanm 82:6473597d706e 1610 #define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
bogdanm 82:6473597d706e 1611 #define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
bogdanm 82:6473597d706e 1612 #define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
bogdanm 82:6473597d706e 1613 #define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
bogdanm 82:6473597d706e 1614 #define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
bogdanm 82:6473597d706e 1615
bogdanm 82:6473597d706e 1616 #define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
bogdanm 82:6473597d706e 1617 #define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
bogdanm 82:6473597d706e 1618 #define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
bogdanm 82:6473597d706e 1619 #define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
bogdanm 82:6473597d706e 1620 #define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
bogdanm 82:6473597d706e 1621 #define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
bogdanm 82:6473597d706e 1622 #define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
bogdanm 82:6473597d706e 1623 #define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
bogdanm 82:6473597d706e 1624 #define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
bogdanm 82:6473597d706e 1625 #define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
bogdanm 82:6473597d706e 1626
bogdanm 82:6473597d706e 1627 #define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
bogdanm 82:6473597d706e 1628
bogdanm 82:6473597d706e 1629
bogdanm 82:6473597d706e 1630 /**** Bit definition for Slave Output 2 set register **************************/
bogdanm 82:6473597d706e 1631 #define HRTIM_SET2R_SST ((uint32_t)0x00000001) /*!< software set trigger */
bogdanm 82:6473597d706e 1632 #define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
bogdanm 82:6473597d706e 1633 #define HRTIM_SET2R_PER ((uint32_t)0x00000004) /*!< Timer A period */
bogdanm 82:6473597d706e 1634 #define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
bogdanm 82:6473597d706e 1635 #define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
bogdanm 82:6473597d706e 1636 #define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
bogdanm 82:6473597d706e 1637 #define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
bogdanm 82:6473597d706e 1638
bogdanm 82:6473597d706e 1639 #define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
bogdanm 82:6473597d706e 1640 #define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
bogdanm 82:6473597d706e 1641 #define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
bogdanm 82:6473597d706e 1642 #define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
bogdanm 82:6473597d706e 1643 #define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
bogdanm 82:6473597d706e 1644
bogdanm 82:6473597d706e 1645 #define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
bogdanm 82:6473597d706e 1646 #define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
bogdanm 82:6473597d706e 1647 #define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
bogdanm 82:6473597d706e 1648 #define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
bogdanm 82:6473597d706e 1649 #define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
bogdanm 82:6473597d706e 1650 #define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
bogdanm 82:6473597d706e 1651 #define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
bogdanm 82:6473597d706e 1652 #define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
bogdanm 82:6473597d706e 1653 #define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
bogdanm 82:6473597d706e 1654
bogdanm 82:6473597d706e 1655 #define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
bogdanm 82:6473597d706e 1656 #define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
bogdanm 82:6473597d706e 1657 #define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
bogdanm 82:6473597d706e 1658 #define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
bogdanm 82:6473597d706e 1659 #define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
bogdanm 82:6473597d706e 1660 #define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
bogdanm 82:6473597d706e 1661 #define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
bogdanm 82:6473597d706e 1662 #define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
bogdanm 82:6473597d706e 1663 #define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
bogdanm 82:6473597d706e 1664 #define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
bogdanm 82:6473597d706e 1665
bogdanm 82:6473597d706e 1666 #define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
bogdanm 82:6473597d706e 1667
bogdanm 82:6473597d706e 1668 /**** Bit definition for Slave Output 2 reset register ************************/
bogdanm 82:6473597d706e 1669 #define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */
bogdanm 82:6473597d706e 1670 #define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
bogdanm 82:6473597d706e 1671 #define HRTIM_RST2R_PER ((uint32_t)0x00000004) /*!< Timer A period */
bogdanm 82:6473597d706e 1672 #define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
bogdanm 82:6473597d706e 1673 #define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
bogdanm 82:6473597d706e 1674 #define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
bogdanm 82:6473597d706e 1675 #define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
bogdanm 82:6473597d706e 1676
bogdanm 82:6473597d706e 1677 #define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
bogdanm 82:6473597d706e 1678 #define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
bogdanm 82:6473597d706e 1679 #define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
bogdanm 82:6473597d706e 1680 #define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
bogdanm 82:6473597d706e 1681 #define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
bogdanm 82:6473597d706e 1682
bogdanm 82:6473597d706e 1683 #define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
bogdanm 82:6473597d706e 1684 #define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
bogdanm 82:6473597d706e 1685 #define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
bogdanm 82:6473597d706e 1686 #define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
bogdanm 82:6473597d706e 1687 #define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
bogdanm 82:6473597d706e 1688 #define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
bogdanm 82:6473597d706e 1689 #define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
bogdanm 82:6473597d706e 1690 #define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
bogdanm 82:6473597d706e 1691 #define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
bogdanm 82:6473597d706e 1692
bogdanm 82:6473597d706e 1693 #define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
bogdanm 82:6473597d706e 1694 #define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
bogdanm 82:6473597d706e 1695 #define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
bogdanm 82:6473597d706e 1696 #define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
bogdanm 82:6473597d706e 1697 #define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
bogdanm 82:6473597d706e 1698 #define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
bogdanm 82:6473597d706e 1699 #define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
bogdanm 82:6473597d706e 1700 #define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
bogdanm 82:6473597d706e 1701 #define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
bogdanm 82:6473597d706e 1702 #define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
bogdanm 82:6473597d706e 1703
bogdanm 82:6473597d706e 1704 #define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
bogdanm 82:6473597d706e 1705
bogdanm 82:6473597d706e 1706 /**** Bit definition for Slave external event filtering register 1 ***********/
bogdanm 82:6473597d706e 1707 #define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /*!< External Event 1 latch */
bogdanm 82:6473597d706e 1708 #define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /*!< External Event 1 filter mask */
bogdanm 82:6473597d706e 1709 #define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /*!< External Event 1 bit 0 */
bogdanm 82:6473597d706e 1710 #define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /*!< External Event 1 bit 1*/
bogdanm 82:6473597d706e 1711 #define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /*!< External Event 1 bit 2 */
bogdanm 82:6473597d706e 1712 #define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /*!< External Event 1 bit 3 */
bogdanm 82:6473597d706e 1713
bogdanm 82:6473597d706e 1714 #define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /*!< External Event 2 latch */
bogdanm 82:6473597d706e 1715 #define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /*!< External Event 2 filter mask */
bogdanm 82:6473597d706e 1716 #define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /*!< External Event 2 bit 0 */
bogdanm 82:6473597d706e 1717 #define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /*!< External Event 2 bit 1*/
bogdanm 82:6473597d706e 1718 #define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /*!< External Event 2 bit 2 */
bogdanm 82:6473597d706e 1719 #define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /*!< External Event 2 bit 3 */
bogdanm 82:6473597d706e 1720
bogdanm 82:6473597d706e 1721 #define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /*!< External Event 3 latch */
bogdanm 82:6473597d706e 1722 #define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /*!< External Event 3 filter mask */
bogdanm 82:6473597d706e 1723 #define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /*!< External Event 3 bit 0 */
bogdanm 82:6473597d706e 1724 #define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /*!< External Event 3 bit 1*/
bogdanm 82:6473597d706e 1725 #define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /*!< External Event 3 bit 2 */
bogdanm 82:6473597d706e 1726 #define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /*!< External Event 3 bit 3 */
bogdanm 82:6473597d706e 1727
bogdanm 82:6473597d706e 1728 #define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /*!< External Event 4 latch */
bogdanm 82:6473597d706e 1729 #define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /*!< External Event 4 filter mask */
bogdanm 82:6473597d706e 1730 #define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /*!< External Event 4 bit 0 */
bogdanm 82:6473597d706e 1731 #define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /*!< External Event 4 bit 1*/
bogdanm 82:6473597d706e 1732 #define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /*!< External Event 4 bit 2 */
bogdanm 82:6473597d706e 1733 #define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /*!< External Event 4 bit 3 */
bogdanm 82:6473597d706e 1734
bogdanm 82:6473597d706e 1735 #define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /*!< External Event 5 latch */
bogdanm 82:6473597d706e 1736 #define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /*!< External Event 5 filter mask */
bogdanm 82:6473597d706e 1737 #define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /*!< External Event 5 bit 0 */
bogdanm 82:6473597d706e 1738 #define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /*!< External Event 5 bit 1*/
bogdanm 82:6473597d706e 1739 #define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /*!< External Event 5 bit 2 */
bogdanm 82:6473597d706e 1740 #define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /*!< External Event 5 bit 3 */
bogdanm 82:6473597d706e 1741
bogdanm 82:6473597d706e 1742 /**** Bit definition for Slave external event filtering register 2 ***********/
bogdanm 82:6473597d706e 1743 #define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /*!< External Event 6 latch */
bogdanm 82:6473597d706e 1744 #define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /*!< External Event 6 filter mask */
bogdanm 82:6473597d706e 1745 #define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /*!< External Event 6 bit 0 */
bogdanm 82:6473597d706e 1746 #define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /*!< External Event 6 bit 1*/
bogdanm 82:6473597d706e 1747 #define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /*!< External Event 6 bit 2 */
bogdanm 82:6473597d706e 1748 #define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /*!< External Event 6 bit 3 */
bogdanm 82:6473597d706e 1749
bogdanm 82:6473597d706e 1750 #define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /*!< External Event 7 latch */
bogdanm 82:6473597d706e 1751 #define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /*!< External Event 7 filter mask */
bogdanm 82:6473597d706e 1752 #define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /*!< External Event 7 bit 0 */
bogdanm 82:6473597d706e 1753 #define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /*!< External Event 7 bit 1*/
bogdanm 82:6473597d706e 1754 #define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /*!< External Event 7 bit 2 */
bogdanm 82:6473597d706e 1755 #define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /*!< External Event 7 bit 3 */
bogdanm 82:6473597d706e 1756
bogdanm 82:6473597d706e 1757 #define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /*!< External Event 8 latch */
bogdanm 82:6473597d706e 1758 #define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /*!< External Event 8 filter mask */
bogdanm 82:6473597d706e 1759 #define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /*!< External Event 8 bit 0 */
bogdanm 82:6473597d706e 1760 #define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /*!< External Event 8 bit 1*/
bogdanm 82:6473597d706e 1761 #define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /*!< External Event 8 bit 2 */
bogdanm 82:6473597d706e 1762 #define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /*!< External Event 8 bit 3 */
bogdanm 82:6473597d706e 1763
bogdanm 82:6473597d706e 1764 #define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /*!< External Event 9 latch */
bogdanm 82:6473597d706e 1765 #define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /*!< External Event 9 filter mask */
bogdanm 82:6473597d706e 1766 #define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /*!< External Event 9 bit 0 */
bogdanm 82:6473597d706e 1767 #define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /*!< External Event 9 bit 1*/
bogdanm 82:6473597d706e 1768 #define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /*!< External Event 9 bit 2 */
bogdanm 82:6473597d706e 1769 #define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /*!< External Event 9 bit 3 */
bogdanm 82:6473597d706e 1770
bogdanm 82:6473597d706e 1771 #define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /*!< External Event 10 latch */
bogdanm 82:6473597d706e 1772 #define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /*!< External Event 10 filter mask */
bogdanm 82:6473597d706e 1773 #define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /*!< External Event 10 bit 0 */
bogdanm 82:6473597d706e 1774 #define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /*!< External Event 10 bit 1*/
bogdanm 82:6473597d706e 1775 #define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /*!< External Event 10 bit 2 */
bogdanm 82:6473597d706e 1776 #define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /*!< External Event 10 bit 3 */
bogdanm 82:6473597d706e 1777
bogdanm 82:6473597d706e 1778 /**** Bit definition for Slave Timer reset register ***************************/
bogdanm 82:6473597d706e 1779 #define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /*!< Timer update */
bogdanm 82:6473597d706e 1780 #define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /*!< Timer compare2 */
bogdanm 82:6473597d706e 1781 #define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /*!< Timer compare4 */
bogdanm 82:6473597d706e 1782
bogdanm 82:6473597d706e 1783 #define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /*!< Master period */
bogdanm 82:6473597d706e 1784 #define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /*!< Master compare1 */
bogdanm 82:6473597d706e 1785 #define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /*!< Master compare2 */
bogdanm 82:6473597d706e 1786 #define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /*!< Master compare3 */
bogdanm 82:6473597d706e 1787 #define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /*!< Master compare4 */
bogdanm 82:6473597d706e 1788
bogdanm 82:6473597d706e 1789 #define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /*!< External event 1 */
bogdanm 82:6473597d706e 1790 #define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /*!< External event 2 */
bogdanm 82:6473597d706e 1791 #define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /*!< External event 3 */
bogdanm 82:6473597d706e 1792 #define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /*!< External event 4 */
bogdanm 82:6473597d706e 1793 #define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /*!< External event 5 */
bogdanm 82:6473597d706e 1794 #define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /*!< External event 6 */
bogdanm 82:6473597d706e 1795 #define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /*!< External event 7 */
bogdanm 82:6473597d706e 1796 #define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /*!< External event 8 */
bogdanm 82:6473597d706e 1797 #define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /*!< External event 9 */
bogdanm 82:6473597d706e 1798 #define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /*!< External event 10 */
bogdanm 82:6473597d706e 1799
bogdanm 82:6473597d706e 1800 #define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /*!< Timer B compare 1 */
bogdanm 82:6473597d706e 1801 #define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /*!< Timer B compare 2 */
bogdanm 82:6473597d706e 1802 #define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /*!< Timer B compare 4 */
bogdanm 82:6473597d706e 1803
bogdanm 82:6473597d706e 1804 #define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
bogdanm 82:6473597d706e 1805 #define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
bogdanm 82:6473597d706e 1806 #define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /*!< Timer C compare 4 */
bogdanm 82:6473597d706e 1807
bogdanm 82:6473597d706e 1808 #define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /*!< Timer D compare 1 */
bogdanm 82:6473597d706e 1809 #define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /*!< Timer D compare 2 */
bogdanm 82:6473597d706e 1810 #define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /*!< Timer D compare 4 */
bogdanm 82:6473597d706e 1811
bogdanm 82:6473597d706e 1812 #define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /*!< Timer E compare 1 */
bogdanm 82:6473597d706e 1813 #define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /*!< Timer E compare 2 */
bogdanm 82:6473597d706e 1814 #define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /*!< Timer E compare 4 */
bogdanm 82:6473597d706e 1815
bogdanm 82:6473597d706e 1816 /**** Bit definition for Slave Timer Chopper register *************************/
bogdanm 82:6473597d706e 1817 #define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /*!< Timer carrier frequency value */
bogdanm 82:6473597d706e 1818 #define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /*!< Timer carrier frequency value bit 0 */
bogdanm 82:6473597d706e 1819 #define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /*!< Timer carrier frequency value bit 1 */
bogdanm 82:6473597d706e 1820 #define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /*!< Timer carrier frequency value bit 2 */
bogdanm 82:6473597d706e 1821 #define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /*!< Timer carrier frequency value bit 3 */
bogdanm 82:6473597d706e 1822
bogdanm 82:6473597d706e 1823 #define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /*!< Timer chopper duty cycle value */
bogdanm 82:6473597d706e 1824 #define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /*!< Timer chopper duty cycle value bit 0 */
bogdanm 82:6473597d706e 1825 #define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /*!< Timer chopper duty cycle value bit 1 */
bogdanm 82:6473597d706e 1826 #define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /*!< Timer chopper duty cycle value bit 2 */
bogdanm 82:6473597d706e 1827
bogdanm 82:6473597d706e 1828 #define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /*!< Timer start pulse width value */
bogdanm 82:6473597d706e 1829 #define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /*!< Timer start pulse width value bit 0 */
bogdanm 82:6473597d706e 1830 #define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /*!< Timer start pulse width value bit 1 */
bogdanm 82:6473597d706e 1831 #define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /*!< Timer start pulse width value bit 2 */
bogdanm 82:6473597d706e 1832 #define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /*!< Timer start pulse width value bit 3 */
bogdanm 82:6473597d706e 1833
bogdanm 82:6473597d706e 1834 /**** Bit definition for Slave Timer Capture 1 control register ***************/
bogdanm 82:6473597d706e 1835 #define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */
bogdanm 82:6473597d706e 1836 #define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */
bogdanm 82:6473597d706e 1837 #define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */
bogdanm 82:6473597d706e 1838 #define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */
bogdanm 82:6473597d706e 1839 #define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */
bogdanm 82:6473597d706e 1840 #define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */
bogdanm 82:6473597d706e 1841 #define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */
bogdanm 82:6473597d706e 1842 #define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */
bogdanm 82:6473597d706e 1843 #define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */
bogdanm 82:6473597d706e 1844 #define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */
bogdanm 82:6473597d706e 1845 #define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */
bogdanm 82:6473597d706e 1846 #define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */
bogdanm 82:6473597d706e 1847
bogdanm 82:6473597d706e 1848 #define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */
bogdanm 82:6473597d706e 1849 #define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */
bogdanm 82:6473597d706e 1850 #define HRTIM_CPT1CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */
bogdanm 82:6473597d706e 1851 #define HRTIM_CPT1CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */
bogdanm 82:6473597d706e 1852
bogdanm 82:6473597d706e 1853 #define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */
bogdanm 82:6473597d706e 1854 #define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */
bogdanm 82:6473597d706e 1855 #define HRTIM_CPT1CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */
bogdanm 82:6473597d706e 1856 #define HRTIM_CPT1CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */
bogdanm 82:6473597d706e 1857
bogdanm 82:6473597d706e 1858 #define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */
bogdanm 82:6473597d706e 1859 #define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */
bogdanm 82:6473597d706e 1860 #define HRTIM_CPT1CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
bogdanm 82:6473597d706e 1861 #define HRTIM_CPT1CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
bogdanm 82:6473597d706e 1862
bogdanm 82:6473597d706e 1863 #define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */
bogdanm 82:6473597d706e 1864 #define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */
bogdanm 82:6473597d706e 1865 #define HRTIM_CPT1CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */
bogdanm 82:6473597d706e 1866 #define HRTIM_CPT1CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */
bogdanm 82:6473597d706e 1867
bogdanm 82:6473597d706e 1868 #define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */
bogdanm 82:6473597d706e 1869 #define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */
bogdanm 82:6473597d706e 1870 #define HRTIM_CPT1CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */
bogdanm 82:6473597d706e 1871 #define HRTIM_CPT1CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */
bogdanm 82:6473597d706e 1872
bogdanm 82:6473597d706e 1873 /**** Bit definition for Slave Timer Capture 2 control register ***************/
bogdanm 82:6473597d706e 1874 #define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */
bogdanm 82:6473597d706e 1875 #define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */
bogdanm 82:6473597d706e 1876 #define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */
bogdanm 82:6473597d706e 1877 #define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */
bogdanm 82:6473597d706e 1878 #define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */
bogdanm 82:6473597d706e 1879 #define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */
bogdanm 82:6473597d706e 1880 #define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */
bogdanm 82:6473597d706e 1881 #define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */
bogdanm 82:6473597d706e 1882 #define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */
bogdanm 82:6473597d706e 1883 #define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */
bogdanm 82:6473597d706e 1884 #define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */
bogdanm 82:6473597d706e 1885 #define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */
bogdanm 82:6473597d706e 1886
bogdanm 82:6473597d706e 1887 #define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */
bogdanm 82:6473597d706e 1888 #define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */
bogdanm 82:6473597d706e 1889 #define HRTIM_CPT2CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */
bogdanm 82:6473597d706e 1890 #define HRTIM_CPT2CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */
bogdanm 82:6473597d706e 1891
bogdanm 82:6473597d706e 1892 #define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */
bogdanm 82:6473597d706e 1893 #define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */
bogdanm 82:6473597d706e 1894 #define HRTIM_CPT2CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */
bogdanm 82:6473597d706e 1895 #define HRTIM_CPT2CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */
bogdanm 82:6473597d706e 1896
bogdanm 82:6473597d706e 1897 #define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */
bogdanm 82:6473597d706e 1898 #define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */
bogdanm 82:6473597d706e 1899 #define HRTIM_CPT2CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
bogdanm 82:6473597d706e 1900 #define HRTIM_CPT2CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
bogdanm 82:6473597d706e 1901
bogdanm 82:6473597d706e 1902 #define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */
bogdanm 82:6473597d706e 1903 #define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */
bogdanm 82:6473597d706e 1904 #define HRTIM_CPT2CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */
bogdanm 82:6473597d706e 1905 #define HRTIM_CPT2CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */
bogdanm 82:6473597d706e 1906
bogdanm 82:6473597d706e 1907 #define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */
bogdanm 82:6473597d706e 1908 #define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */
bogdanm 82:6473597d706e 1909 #define HRTIM_CPT2CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */
bogdanm 82:6473597d706e 1910 #define HRTIM_CPT2CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */
bogdanm 82:6473597d706e 1911
bogdanm 82:6473597d706e 1912 /**** Bit definition for Slave Timer Output register **************************/
bogdanm 82:6473597d706e 1913 #define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /*!< Slave output 1 polarity */
bogdanm 82:6473597d706e 1914 #define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /*!< Slave output 1 idle mode */
bogdanm 82:6473597d706e 1915 #define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /*!< Slave output 1 idle state */
bogdanm 82:6473597d706e 1916 #define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /*!< Slave output 1 fault state */
bogdanm 82:6473597d706e 1917 #define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /*!< Slave output 1 fault state bit 0 */
bogdanm 82:6473597d706e 1918 #define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /*!< Slave output 1 fault state bit 1 */
bogdanm 82:6473597d706e 1919 #define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /*!< Slave output 1 chopper enable */
bogdanm 82:6473597d706e 1920 #define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /*!< Slave output 1 dead time idle */
bogdanm 82:6473597d706e 1921
bogdanm 82:6473597d706e 1922 #define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /*!< Slave output deadtime enable */
bogdanm 82:6473597d706e 1923 #define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /*!< Slave output delay protection enable */
bogdanm 82:6473597d706e 1924 #define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /*!< Slave output delay protection */
bogdanm 82:6473597d706e 1925 #define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /*!< Slave output delay protection bit 0 */
bogdanm 82:6473597d706e 1926 #define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /*!< Slave output delay protection bit 1 */
bogdanm 82:6473597d706e 1927 #define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /*!< Slave output delay protection bit 2 */
bogdanm 82:6473597d706e 1928
bogdanm 82:6473597d706e 1929 #define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /*!< Slave output 2 polarity */
bogdanm 82:6473597d706e 1930 #define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /*!< Slave output 2 idle mode */
bogdanm 82:6473597d706e 1931 #define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /*!< Slave output 2 idle state */
bogdanm 82:6473597d706e 1932 #define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /*!< Slave output 2 fault state */
bogdanm 82:6473597d706e 1933 #define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /*!< Slave output 2 fault state bit 0 */
bogdanm 82:6473597d706e 1934 #define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /*!< Slave output 2 fault state bit 1 */
bogdanm 82:6473597d706e 1935 #define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /*!< Slave output 2 chopper enable */
bogdanm 82:6473597d706e 1936 #define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /*!< Slave output 2 dead time idle */
bogdanm 82:6473597d706e 1937
bogdanm 82:6473597d706e 1938 /**** Bit definition for Slave Timer Fault register ***************************/
bogdanm 82:6473597d706e 1939 #define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /*!< Fault 1 enable */
bogdanm 82:6473597d706e 1940 #define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /*!< Fault 2 enable */
bogdanm 82:6473597d706e 1941 #define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /*!< Fault 3 enable */
bogdanm 82:6473597d706e 1942 #define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /*!< Fault 4 enable */
bogdanm 82:6473597d706e 1943 #define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /*!< Fault 5 enable */
bogdanm 82:6473597d706e 1944 #define HRTIM_FLTR_FLTCLK ((uint32_t)0x80000000) /*!< Fault sources lock */
bogdanm 82:6473597d706e 1945
bogdanm 82:6473597d706e 1946 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
bogdanm 82:6473597d706e 1947 #define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /*!< Master update disable*/
bogdanm 82:6473597d706e 1948 #define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /*!< Timer A update disable*/
bogdanm 82:6473597d706e 1949 #define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /*!< Timer B update disable*/
bogdanm 82:6473597d706e 1950 #define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /*!< Timer C update disable*/
bogdanm 82:6473597d706e 1951 #define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /*!< Timer D update disable*/
bogdanm 82:6473597d706e 1952 #define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /*!< Timer E update disable*/
bogdanm 82:6473597d706e 1953 #define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /*!< ADC Trigger 1 update source */
bogdanm 82:6473597d706e 1954 #define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /*!< ADC Trigger 1 update source bit 0 */
bogdanm 82:6473597d706e 1955 #define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /*!< ADC Trigger 1 update source bit 1 */
bogdanm 82:6473597d706e 1956 #define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /*!< ADC Trigger 1 update source bit 2 */
bogdanm 82:6473597d706e 1957 #define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /*!< ADC Trigger 2 update source */
bogdanm 82:6473597d706e 1958 #define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /*!< ADC Trigger 2 update source bit 0 */
bogdanm 82:6473597d706e 1959 #define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /*!< ADC Trigger 2 update source bit 1 */
bogdanm 82:6473597d706e 1960 #define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /*!< ADC Trigger 2 update source bit 2 */
bogdanm 82:6473597d706e 1961 #define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /*!< ADC Trigger 3 update source */
bogdanm 82:6473597d706e 1962 #define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /*!< ADC Trigger 3 update source bit 0 */
bogdanm 82:6473597d706e 1963 #define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /*!< ADC Trigger 3 update source bit 1 */
bogdanm 82:6473597d706e 1964 #define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 update source bit 2 */
bogdanm 82:6473597d706e 1965 #define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /*!< ADC Trigger 4 update source */
bogdanm 82:6473597d706e 1966 #define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /*!< ADC Trigger 4 update source bit 0 */
bogdanm 82:6473597d706e 1967 #define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /*!< ADC Trigger 4 update source bit 1 */
bogdanm 82:6473597d706e 1968 #define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /*!< ADC Trigger 4 update source bit 2 */
bogdanm 82:6473597d706e 1969
bogdanm 82:6473597d706e 1970 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
bogdanm 82:6473597d706e 1971 #define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /*!< Master software update */
bogdanm 82:6473597d706e 1972 #define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /*!< Timer A software update */
bogdanm 82:6473597d706e 1973 #define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /*!< Timer B software update */
bogdanm 82:6473597d706e 1974 #define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /*!< Timer C software update */
bogdanm 82:6473597d706e 1975 #define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /*!< Timer D software update */
bogdanm 82:6473597d706e 1976 #define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /*!< Timer E software update */
bogdanm 82:6473597d706e 1977 #define HRTIM_CR2_MRST ((uint32_t)0x00000100) /*!< Master count software reset */
bogdanm 82:6473597d706e 1978 #define HRTIM_CR2_TARST ((uint32_t)0x00000200) /*!< Timer A count software reset */
bogdanm 82:6473597d706e 1979 #define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /*!< Timer B count software reset */
bogdanm 82:6473597d706e 1980 #define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /*!< Timer C count software reset */
bogdanm 82:6473597d706e 1981 #define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /*!< Timer D count software reset */
bogdanm 82:6473597d706e 1982 #define HRTIM_CR2_TERST ((uint32_t)0x00002000) /*!< Timer E count software reset */
bogdanm 82:6473597d706e 1983
bogdanm 82:6473597d706e 1984 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
bogdanm 82:6473597d706e 1985 #define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag */
bogdanm 82:6473597d706e 1986 #define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag */
bogdanm 82:6473597d706e 1987 #define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag */
bogdanm 82:6473597d706e 1988 #define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag */
bogdanm 82:6473597d706e 1989 #define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag */
bogdanm 82:6473597d706e 1990 #define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt flag */
bogdanm 82:6473597d706e 1991 #define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt flag */
bogdanm 82:6473597d706e 1992 #define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag */
bogdanm 82:6473597d706e 1993
bogdanm 82:6473597d706e 1994 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
bogdanm 82:6473597d706e 1995 #define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag clear */
bogdanm 82:6473597d706e 1996 #define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag clear */
bogdanm 82:6473597d706e 1997 #define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag clear */
bogdanm 82:6473597d706e 1998 #define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag clear */
bogdanm 82:6473597d706e 1999 #define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag clear */
bogdanm 82:6473597d706e 2000 #define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /*!< System Fault interrupt flag clear */
bogdanm 82:6473597d706e 2001 #define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /*!< DLL ready interrupt flag clear */
bogdanm 82:6473597d706e 2002 #define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag clear */
bogdanm 82:6473597d706e 2003
bogdanm 82:6473597d706e 2004 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
bogdanm 82:6473597d706e 2005 #define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt enable */
bogdanm 82:6473597d706e 2006 #define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt enable */
bogdanm 82:6473597d706e 2007 #define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt enable */
bogdanm 82:6473597d706e 2008 #define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt enable */
bogdanm 82:6473597d706e 2009 #define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt enable */
bogdanm 82:6473597d706e 2010 #define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt enable */
bogdanm 82:6473597d706e 2011 #define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt enable */
bogdanm 82:6473597d706e 2012 #define HRTIM_IER_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt enable */
bogdanm 82:6473597d706e 2013
bogdanm 82:6473597d706e 2014 /**** Bit definition for Common HRTIM Timer output enable register ************/
bogdanm 82:6473597d706e 2015 #define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /*!< Timer A Output 1 enable */
bogdanm 82:6473597d706e 2016 #define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /*!< Timer A Output 2 enable */
bogdanm 82:6473597d706e 2017 #define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /*!< Timer B Output 1 enable */
bogdanm 82:6473597d706e 2018 #define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /*!< Timer B Output 2 enable */
bogdanm 82:6473597d706e 2019 #define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /*!< Timer C Output 1 enable */
bogdanm 82:6473597d706e 2020 #define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /*!< Timer C Output 2 enable */
bogdanm 82:6473597d706e 2021 #define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /*!< Timer D Output 1 enable */
bogdanm 82:6473597d706e 2022 #define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /*!< Timer D Output 2 enable */
bogdanm 82:6473597d706e 2023 #define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /*!< Timer E Output 1 enable */
bogdanm 82:6473597d706e 2024 #define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /*!< Timer E Output 2 enable */
bogdanm 82:6473597d706e 2025
bogdanm 82:6473597d706e 2026 /**** Bit definition for Common HRTIM Timer output disable register ***********/
bogdanm 82:6473597d706e 2027 #define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable */
bogdanm 82:6473597d706e 2028 #define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable */
bogdanm 82:6473597d706e 2029 #define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable */
bogdanm 82:6473597d706e 2030 #define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable */
bogdanm 82:6473597d706e 2031 #define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable */
bogdanm 82:6473597d706e 2032 #define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable */
bogdanm 82:6473597d706e 2033 #define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable */
bogdanm 82:6473597d706e 2034 #define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable */
bogdanm 82:6473597d706e 2035 #define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable */
bogdanm 82:6473597d706e 2036 #define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable */
bogdanm 82:6473597d706e 2037
bogdanm 82:6473597d706e 2038 /**** Bit definition for Common HRTIM Timer output disable status register *****/
bogdanm 82:6473597d706e 2039 #define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable status */
bogdanm 82:6473597d706e 2040 #define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable status */
bogdanm 82:6473597d706e 2041 #define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable status */
bogdanm 82:6473597d706e 2042 #define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable status */
bogdanm 82:6473597d706e 2043 #define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable status */
bogdanm 82:6473597d706e 2044 #define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable status */
bogdanm 82:6473597d706e 2045 #define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable status */
bogdanm 82:6473597d706e 2046 #define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable status */
bogdanm 82:6473597d706e 2047 #define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable status */
bogdanm 82:6473597d706e 2048 #define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable status */
bogdanm 82:6473597d706e 2049
bogdanm 82:6473597d706e 2050 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
bogdanm 82:6473597d706e 2051 #define HRTIM_BMCR_BME ((uint32_t)0x00000001) /*!< Burst mode enable */
bogdanm 82:6473597d706e 2052 #define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /*!< Burst mode operating mode */
bogdanm 82:6473597d706e 2053 #define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /*!< Burst mode clock source */
bogdanm 82:6473597d706e 2054 #define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /*!< Burst mode clock source bit 0 */
bogdanm 82:6473597d706e 2055 #define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /*!< Burst mode clock source bit 1 */
bogdanm 82:6473597d706e 2056 #define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /*!< Burst mode clock source bit 2 */
bogdanm 82:6473597d706e 2057 #define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /*!< Burst mode clock source bit 3 */
bogdanm 82:6473597d706e 2058 #define HRTIM_BMCR_BMPSC ((uint32_t)0x000003C0) /*!< Burst mode prescaler */
bogdanm 82:6473597d706e 2059 #define HRTIM_BMCR_BMPSC_0 ((uint32_t)0x00000040) /*!< Burst mode prescaler bit 0 */
bogdanm 82:6473597d706e 2060 #define HRTIM_BMCR_BMPSC_1 ((uint32_t)0x00000080) /*!< Burst mode prescaler bit 1 */
bogdanm 82:6473597d706e 2061 #define HRTIM_BMCR_BMPSC_2 ((uint32_t)0x00000100) /*!< Burst mode prescaler bit 2 */
bogdanm 82:6473597d706e 2062 #define HRTIM_BMCR_BMPSC_3 ((uint32_t)0x00000200) /*!< Burst mode prescaler bit 3 */
bogdanm 82:6473597d706e 2063 #define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /*!< Burst mode Preload bit */
bogdanm 82:6473597d706e 2064 #define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /*!< Master Timer Burst mode */
bogdanm 82:6473597d706e 2065 #define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /*!< Timer A Burst mode */
bogdanm 82:6473597d706e 2066 #define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /*!< Timer B Burst mode */
bogdanm 82:6473597d706e 2067 #define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /*!< Timer C Burst mode */
bogdanm 82:6473597d706e 2068 #define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /*!< Timer D Burst mode */
bogdanm 82:6473597d706e 2069 #define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /*!< Timer E Burst mode */
bogdanm 82:6473597d706e 2070 #define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /*!< Burst mode status */
bogdanm 82:6473597d706e 2071
bogdanm 82:6473597d706e 2072 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
bogdanm 82:6473597d706e 2073 #define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /*!< Software start */
bogdanm 82:6473597d706e 2074 #define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /*!< Master reset */
bogdanm 82:6473597d706e 2075 #define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /*!< Master repetition */
bogdanm 82:6473597d706e 2076 #define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /*!< Master compare 1 */
bogdanm 82:6473597d706e 2077 #define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /*!< Master compare 2 */
bogdanm 82:6473597d706e 2078 #define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /*!< Master compare 3 */
bogdanm 82:6473597d706e 2079 #define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /*!< Master compare 4 */
bogdanm 82:6473597d706e 2080 #define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /*!< Timer A reset */
bogdanm 82:6473597d706e 2081 #define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /*!< Timer A repetition */
bogdanm 82:6473597d706e 2082 #define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /*!< Timer A compare 1 */
bogdanm 82:6473597d706e 2083 #define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /*!< Timer A compare 2 */
bogdanm 82:6473597d706e 2084 #define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /*!< Timer B reset */
bogdanm 82:6473597d706e 2085 #define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /*!< Timer B repetition */
bogdanm 82:6473597d706e 2086 #define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /*!< Timer B compare 1 */
bogdanm 82:6473597d706e 2087 #define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /*!< Timer B compare 2 */
bogdanm 82:6473597d706e 2088 #define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /*!< Timer C reset */
bogdanm 82:6473597d706e 2089 #define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /*!< Timer C repetition */
bogdanm 82:6473597d706e 2090 #define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /*!< Timer C compare 1 */
bogdanm 82:6473597d706e 2091 #define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /*!< Timer C compare 2 */
bogdanm 82:6473597d706e 2092 #define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /*!< Timer D reset */
bogdanm 82:6473597d706e 2093 #define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /*!< Timer D repetition */
bogdanm 82:6473597d706e 2094 #define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /*!< Timer D compare 1 */
bogdanm 82:6473597d706e 2095 #define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /*!< Timer D compare 2 */
bogdanm 82:6473597d706e 2096 #define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /*!< Timer E reset */
bogdanm 82:6473597d706e 2097 #define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /*!< Timer E repetition */
bogdanm 82:6473597d706e 2098 #define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /*!< Timer E compare 1 */
bogdanm 82:6473597d706e 2099 #define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /*!< Timer E compare 2 */
bogdanm 82:6473597d706e 2100 #define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /*!< Timer A period following External Event7 */
bogdanm 82:6473597d706e 2101 #define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /*!< Timer D period following External Event8 */
bogdanm 82:6473597d706e 2102 #define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /*!< External Event 7 */
bogdanm 82:6473597d706e 2103 #define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /*!< External Event 8 */
bogdanm 82:6473597d706e 2104 #define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /*!< on-chip Event */
bogdanm 82:6473597d706e 2105
bogdanm 82:6473597d706e 2106 /******************* Bit definition for HRTIM_BMCMPR register ***************/
bogdanm 82:6473597d706e 2107 #define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /*!<!<Burst Compare Value */
bogdanm 82:6473597d706e 2108
bogdanm 82:6473597d706e 2109 /******************* Bit definition for HRTIM_BMPER register ****************/
bogdanm 82:6473597d706e 2110 #define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /*!<!<Burst period Value */
bogdanm 82:6473597d706e 2111
bogdanm 82:6473597d706e 2112 /******************* Bit definition for HRTIM_EECR1 register ****************/
bogdanm 82:6473597d706e 2113 #define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /*!< External event 1 source */
bogdanm 82:6473597d706e 2114 #define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /*!< External event 1 source bit 0 */
bogdanm 82:6473597d706e 2115 #define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /*!< External event 1 source bit 1 */
bogdanm 82:6473597d706e 2116 #define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /*!< External event 1 Polarity */
bogdanm 82:6473597d706e 2117 #define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /*!< External event 1 sensitivity */
bogdanm 82:6473597d706e 2118 #define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /*!< External event 1 sensitivity bit 0 */
bogdanm 82:6473597d706e 2119 #define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /*!< External event 1 sensitivity bit 1 */
bogdanm 82:6473597d706e 2120 #define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /*!< External event 1 Fast mode */
bogdanm 82:6473597d706e 2121
bogdanm 82:6473597d706e 2122 #define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /*!< External event 2 source */
bogdanm 82:6473597d706e 2123 #define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /*!< External event 2 source bit 0 */
bogdanm 82:6473597d706e 2124 #define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /*!< External event 2 source bit 1 */
bogdanm 82:6473597d706e 2125 #define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /*!< External event 2 Polarity */
bogdanm 82:6473597d706e 2126 #define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /*!< External event 2 sensitivity */
bogdanm 82:6473597d706e 2127 #define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /*!< External event 2 sensitivity bit 0 */
bogdanm 82:6473597d706e 2128 #define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /*!< External event 2 sensitivity bit 1 */
bogdanm 82:6473597d706e 2129 #define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /*!< External event 2 Fast mode */
bogdanm 82:6473597d706e 2130
bogdanm 82:6473597d706e 2131 #define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /*!< External event 3 source */
bogdanm 82:6473597d706e 2132 #define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /*!< External event 3 source bit 0 */
bogdanm 82:6473597d706e 2133 #define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /*!< External event 3 source bit 1 */
bogdanm 82:6473597d706e 2134 #define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /*!< External event 3 Polarity */
bogdanm 82:6473597d706e 2135 #define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /*!< External event 3 sensitivity */
bogdanm 82:6473597d706e 2136 #define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /*!< External event 3 sensitivity bit 0 */
bogdanm 82:6473597d706e 2137 #define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /*!< External event 3 sensitivity bit 1 */
bogdanm 82:6473597d706e 2138 #define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /*!< External event 3 Fast mode */
bogdanm 82:6473597d706e 2139
bogdanm 82:6473597d706e 2140 #define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /*!< External event 4 source */
bogdanm 82:6473597d706e 2141 #define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /*!< External event 4 source bit 0 */
bogdanm 82:6473597d706e 2142 #define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /*!< External event 4 source bit 1 */
bogdanm 82:6473597d706e 2143 #define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /*!< External event 4 Polarity */
bogdanm 82:6473597d706e 2144 #define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /*!< External event 4 sensitivity */
bogdanm 82:6473597d706e 2145 #define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /*!< External event 4 sensitivity bit 0 */
bogdanm 82:6473597d706e 2146 #define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /*!< External event 4 sensitivity bit 1 */
bogdanm 82:6473597d706e 2147 #define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /*!< External event 4 Fast mode */
bogdanm 82:6473597d706e 2148
bogdanm 82:6473597d706e 2149 #define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /*!< External event 5 source */
bogdanm 82:6473597d706e 2150 #define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /*!< External event 5 source bit 0 */
bogdanm 82:6473597d706e 2151 #define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /*!< External event 5 source bit 1 */
bogdanm 82:6473597d706e 2152 #define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /*!< External event 5 Polarity */
bogdanm 82:6473597d706e 2153 #define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /*!< External event 5 sensitivity */
bogdanm 82:6473597d706e 2154 #define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /*!< External event 5 sensitivity bit 0 */
bogdanm 82:6473597d706e 2155 #define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /*!< External event 5 sensitivity bit 1 */
bogdanm 82:6473597d706e 2156 #define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /*!< External event 5 Fast mode */
bogdanm 82:6473597d706e 2157
bogdanm 82:6473597d706e 2158 /******************* Bit definition for HRTIM_EECR2 register ****************/
bogdanm 82:6473597d706e 2159 #define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /*!< External event 6 source */
bogdanm 82:6473597d706e 2160 #define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /*!< External event 6 source bit 0 */
bogdanm 82:6473597d706e 2161 #define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /*!< External event 6 source bit 1 */
bogdanm 82:6473597d706e 2162 #define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /*!< External event 6 Polarity */
bogdanm 82:6473597d706e 2163 #define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /*!< External event 6 sensitivity */
bogdanm 82:6473597d706e 2164 #define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /*!< External event 6 sensitivity bit 0 */
bogdanm 82:6473597d706e 2165 #define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /*!< External event 6 sensitivity bit 1 */
bogdanm 82:6473597d706e 2166
bogdanm 82:6473597d706e 2167 #define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /*!< External event 7 source */
bogdanm 82:6473597d706e 2168 #define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /*!< External event 7 source bit 0 */
bogdanm 82:6473597d706e 2169 #define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /*!< External event 7 source bit 1 */
bogdanm 82:6473597d706e 2170 #define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /*!< External event 7 Polarity */
bogdanm 82:6473597d706e 2171 #define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /*!< External event 7 sensitivity */
bogdanm 82:6473597d706e 2172 #define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /*!< External event 7 sensitivity bit 0 */
bogdanm 82:6473597d706e 2173 #define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /*!< External event 7 sensitivity bit 1 */
bogdanm 82:6473597d706e 2174
bogdanm 82:6473597d706e 2175 #define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /*!< External event 8 source */
bogdanm 82:6473597d706e 2176 #define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /*!< External event 8 source bit 0 */
bogdanm 82:6473597d706e 2177 #define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /*!< External event 8 source bit 1 */
bogdanm 82:6473597d706e 2178 #define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /*!< External event 8 Polarity */
bogdanm 82:6473597d706e 2179 #define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /*!< External event 8 sensitivity */
bogdanm 82:6473597d706e 2180 #define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /*!< External event 8 sensitivity bit 0 */
bogdanm 82:6473597d706e 2181 #define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /*!< External event 8 sensitivity bit 1 */
bogdanm 82:6473597d706e 2182
bogdanm 82:6473597d706e 2183 #define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /*!< External event 9 source */
bogdanm 82:6473597d706e 2184 #define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /*!< External event 9 source bit 0 */
bogdanm 82:6473597d706e 2185 #define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /*!< External event 9 source bit 1 */
bogdanm 82:6473597d706e 2186 #define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /*!< External event 9 Polarity */
bogdanm 82:6473597d706e 2187 #define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /*!< External event 9 sensitivity */
bogdanm 82:6473597d706e 2188 #define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /*!< External event 9 sensitivity bit 0 */
bogdanm 82:6473597d706e 2189 #define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /*!< External event 9 sensitivity bit 1 */
bogdanm 82:6473597d706e 2190
bogdanm 82:6473597d706e 2191 #define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /*!< External event 10 source */
bogdanm 82:6473597d706e 2192 #define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /*!< External event 10 source bit 0 */
bogdanm 82:6473597d706e 2193 #define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /*!< External event 10 source bit 1 */
bogdanm 82:6473597d706e 2194 #define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /*!< External event 10 Polarity */
bogdanm 82:6473597d706e 2195 #define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /*!< External event 10 sensitivity */
bogdanm 82:6473597d706e 2196 #define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /*!< External event 10 sensitivity bit 0 */
bogdanm 82:6473597d706e 2197 #define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /*!< External event 10 sensitivity bit 1 */
bogdanm 82:6473597d706e 2198
bogdanm 82:6473597d706e 2199 /******************* Bit definition for HRTIM_EECR3 register ****************/
bogdanm 82:6473597d706e 2200 #define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /*!< External event 6 filter */
bogdanm 82:6473597d706e 2201 #define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /*!< External event 6 filter bit 0 */
bogdanm 82:6473597d706e 2202 #define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /*!< External event 6 filter bit 1 */
bogdanm 82:6473597d706e 2203 #define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /*!< External event 6 filter bit 2 */
bogdanm 82:6473597d706e 2204 #define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /*!< External event 6 filter bit 3 */
bogdanm 82:6473597d706e 2205 #define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /*!< External event 7 filter */
bogdanm 82:6473597d706e 2206 #define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /*!< External event 7 filter bit 0 */
bogdanm 82:6473597d706e 2207 #define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /*!< External event 7 filter bit 1 */
bogdanm 82:6473597d706e 2208 #define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /*!< External event 7 filter bit 2 */
bogdanm 82:6473597d706e 2209 #define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /*!< External event 7 filter bit 3 */
bogdanm 82:6473597d706e 2210 #define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /*!< External event 8 filter */
bogdanm 82:6473597d706e 2211 #define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /*!< External event 8 filter bit 0 */
bogdanm 82:6473597d706e 2212 #define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /*!< External event 8 filter bit 1 */
bogdanm 82:6473597d706e 2213 #define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /*!< External event 8 filter bit 2 */
bogdanm 82:6473597d706e 2214 #define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /*!< External event 8 filter bit 3 */
bogdanm 82:6473597d706e 2215 #define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /*!< External event 9 filter */
bogdanm 82:6473597d706e 2216 #define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /*!< External event 9 filter bit 0 */
bogdanm 82:6473597d706e 2217 #define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /*!< External event 9 filter bit 1 */
bogdanm 82:6473597d706e 2218 #define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /*!< External event 9 filter bit 2 */
bogdanm 82:6473597d706e 2219 #define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /*!< External event 9 filter bit 3 */
bogdanm 82:6473597d706e 2220 #define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /*!< External event 10 filter */
bogdanm 82:6473597d706e 2221 #define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /*!< External event 10 filter bit 0 */
bogdanm 82:6473597d706e 2222 #define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /*!< External event 10 filter bit 1 */
bogdanm 82:6473597d706e 2223 #define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /*!< External event 10 filter bit 2 */
bogdanm 82:6473597d706e 2224 #define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /*!< External event 10 filter bit 3 */
bogdanm 82:6473597d706e 2225 #define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /*!< External event sampling clock division */
bogdanm 82:6473597d706e 2226 #define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /*!< External event sampling clock division bit 0 */
bogdanm 82:6473597d706e 2227 #define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /*!< External event sampling clock division bit 1 */
bogdanm 82:6473597d706e 2228
bogdanm 82:6473597d706e 2229 /******************* Bit definition for HRTIM_ADC1R register ****************/
bogdanm 82:6473597d706e 2230 #define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 1 on master compare 1 */
bogdanm 82:6473597d706e 2231 #define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 1 on master compare 2 */
bogdanm 82:6473597d706e 2232 #define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 1 on master compare 3 */
bogdanm 82:6473597d706e 2233 #define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 1 on master compare 4 */
bogdanm 82:6473597d706e 2234 #define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /*!< ADC Trigger 1 on master period */
bogdanm 82:6473597d706e 2235 #define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 1 on external event 1 */
bogdanm 82:6473597d706e 2236 #define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 1 on external event 2 */
bogdanm 82:6473597d706e 2237 #define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 1 on external event 3 */
bogdanm 82:6473597d706e 2238 #define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 1 on external event 4 */
bogdanm 82:6473597d706e 2239 #define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 1 on external event 5 */
bogdanm 82:6473597d706e 2240 #define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 1 on Timer A compare 2 */
bogdanm 82:6473597d706e 2241 #define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 1 on Timer A compare 3 */
bogdanm 82:6473597d706e 2242 #define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 1 on Timer A compare 4 */
bogdanm 82:6473597d706e 2243 #define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 1 on Timer A period */
bogdanm 82:6473597d706e 2244 #define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /*!< ADC Trigger 1 on Timer A reset */
bogdanm 82:6473597d706e 2245 #define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 1 on Timer B compare 2 */
bogdanm 82:6473597d706e 2246 #define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 1 on Timer B compare 3 */
bogdanm 82:6473597d706e 2247 #define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 1 on Timer B compare 4 */
bogdanm 82:6473597d706e 2248 #define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 1 on Timer B period */
bogdanm 82:6473597d706e 2249 #define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 1 on Timer B reset */
bogdanm 82:6473597d706e 2250 #define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 1 on Timer C compare 2 */
bogdanm 82:6473597d706e 2251 #define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 1 on Timer C compare 3 */
bogdanm 82:6473597d706e 2252 #define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 1 on Timer C compare 4 */
bogdanm 82:6473597d706e 2253 #define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 1 on Timer C period */
bogdanm 82:6473597d706e 2254 #define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 1 on Timer D compare 2 */
bogdanm 82:6473597d706e 2255 #define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 1 on Timer D compare 3 */
bogdanm 82:6473597d706e 2256 #define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 1 on Timer D compare 4 */
bogdanm 82:6473597d706e 2257 #define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 1 on Timer D period */
bogdanm 82:6473597d706e 2258 #define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 1 on Timer E compare 2 */
bogdanm 82:6473597d706e 2259 #define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 1 on Timer E compare 3 */
bogdanm 82:6473597d706e 2260 #define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 1 on Timer E compare 4 */
bogdanm 82:6473597d706e 2261 #define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 1 on Timer E period */
bogdanm 82:6473597d706e 2262
bogdanm 82:6473597d706e 2263 /******************* Bit definition for HRTIM_ADC2R register ****************/
bogdanm 82:6473597d706e 2264 #define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 2 on master compare 1 */
bogdanm 82:6473597d706e 2265 #define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 2 on master compare 2 */
bogdanm 82:6473597d706e 2266 #define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 2 on master compare 3 */
bogdanm 82:6473597d706e 2267 #define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 2 on master compare 4 */
bogdanm 82:6473597d706e 2268 #define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /*!< ADC Trigger 2 on master period */
bogdanm 82:6473597d706e 2269 #define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 2 on external event 6 */
bogdanm 82:6473597d706e 2270 #define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 2 on external event 7 */
bogdanm 82:6473597d706e 2271 #define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 2 on external event 8 */
bogdanm 82:6473597d706e 2272 #define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 2 on external event 9 */
bogdanm 82:6473597d706e 2273 #define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 2 on external event 10 */
bogdanm 82:6473597d706e 2274 #define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 2 on Timer A compare 2 */
bogdanm 82:6473597d706e 2275 #define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 2 on Timer A compare 3 */
bogdanm 82:6473597d706e 2276 #define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 2 on Timer A compare 4*/
bogdanm 82:6473597d706e 2277 #define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 2 on Timer A period */
bogdanm 82:6473597d706e 2278 #define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 2 on Timer B compare 2 */
bogdanm 82:6473597d706e 2279 #define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 2 on Timer B compare 3 */
bogdanm 82:6473597d706e 2280 #define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 2 on Timer B compare 4 */
bogdanm 82:6473597d706e 2281 #define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 2 on Timer B period */
bogdanm 82:6473597d706e 2282 #define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 2 on Timer C compare 2 */
bogdanm 82:6473597d706e 2283 #define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 2 on Timer C compare 3 */
bogdanm 82:6473597d706e 2284 #define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 2 on Timer C compare 4 */
bogdanm 82:6473597d706e 2285 #define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 2 on Timer C period */
bogdanm 82:6473597d706e 2286 #define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 2 on Timer C reset */
bogdanm 82:6473597d706e 2287 #define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 2 on Timer D compare 2 */
bogdanm 82:6473597d706e 2288 #define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 2 on Timer D compare 3 */
bogdanm 82:6473597d706e 2289 #define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 2 on Timer D compare 4*/
bogdanm 82:6473597d706e 2290 #define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 2 on Timer D period */
bogdanm 82:6473597d706e 2291 #define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 2 on Timer D reset */
bogdanm 82:6473597d706e 2292 #define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 2 on Timer E compare 2 */
bogdanm 82:6473597d706e 2293 #define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 2 on Timer E compare 3 */
bogdanm 82:6473597d706e 2294 #define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 2 on Timer E compare 4 */
bogdanm 82:6473597d706e 2295 #define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /*!< ADC Trigger 2 on Timer E reset */
bogdanm 82:6473597d706e 2296
bogdanm 82:6473597d706e 2297 /******************* Bit definition for HRTIM_ADC3R register ****************/
bogdanm 82:6473597d706e 2298 #define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 3 on master compare 1 */
bogdanm 82:6473597d706e 2299 #define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 3 on master compare 2 */
bogdanm 82:6473597d706e 2300 #define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 3 on master compare 3 */
bogdanm 82:6473597d706e 2301 #define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 3 on master compare 4 */
bogdanm 82:6473597d706e 2302 #define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /*!< ADC Trigger 3 on master period */
bogdanm 82:6473597d706e 2303 #define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 3 on external event 1 */
bogdanm 82:6473597d706e 2304 #define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 3 on external event 2 */
bogdanm 82:6473597d706e 2305 #define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 3 on external event 3 */
bogdanm 82:6473597d706e 2306 #define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 3 on external event 4 */
bogdanm 82:6473597d706e 2307 #define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 3 on external event 5 */
bogdanm 82:6473597d706e 2308 #define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 3 on Timer A compare 2 */
bogdanm 82:6473597d706e 2309 #define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 3 on Timer A compare 3 */
bogdanm 82:6473597d706e 2310 #define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 3 on Timer A compare 4 */
bogdanm 82:6473597d706e 2311 #define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 3 on Timer A period */
bogdanm 82:6473597d706e 2312 #define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /*!< ADC Trigger 3 on Timer A reset */
bogdanm 82:6473597d706e 2313 #define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 3 on Timer B compare 2 */
bogdanm 82:6473597d706e 2314 #define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 3 on Timer B compare 3 */
bogdanm 82:6473597d706e 2315 #define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 3 on Timer B compare 4 */
bogdanm 82:6473597d706e 2316 #define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 3 on Timer B period */
bogdanm 82:6473597d706e 2317 #define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 3 on Timer B reset */
bogdanm 82:6473597d706e 2318 #define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 3 on Timer C compare 2 */
bogdanm 82:6473597d706e 2319 #define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 3 on Timer C compare 3 */
bogdanm 82:6473597d706e 2320 #define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 3 on Timer C compare 4 */
bogdanm 82:6473597d706e 2321 #define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 3 on Timer C period */
bogdanm 82:6473597d706e 2322 #define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 on Timer D compare 2 */
bogdanm 82:6473597d706e 2323 #define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 3 on Timer D compare 3 */
bogdanm 82:6473597d706e 2324 #define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 3 on Timer D compare 4 */
bogdanm 82:6473597d706e 2325 #define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 3 on Timer D period */
bogdanm 82:6473597d706e 2326 #define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 3 on Timer E compare 2 */
bogdanm 82:6473597d706e 2327 #define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 3 on Timer E compare 3 */
bogdanm 82:6473597d706e 2328 #define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 3 on Timer E compare 4 */
bogdanm 82:6473597d706e 2329 #define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 3 on Timer E period */
bogdanm 82:6473597d706e 2330
bogdanm 82:6473597d706e 2331 /******************* Bit definition for HRTIM_ADC4R register ****************/
bogdanm 82:6473597d706e 2332 #define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 4 on master compare 1 */
bogdanm 82:6473597d706e 2333 #define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 4 on master compare 2 */
bogdanm 82:6473597d706e 2334 #define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 4 on master compare 3 */
bogdanm 82:6473597d706e 2335 #define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 4 on master compare 4 */
bogdanm 82:6473597d706e 2336 #define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /*!< ADC Trigger 4 on master period */
bogdanm 82:6473597d706e 2337 #define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 4 on external event 6 */
bogdanm 82:6473597d706e 2338 #define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 4 on external event 7 */
bogdanm 82:6473597d706e 2339 #define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 4 on external event 8 */
bogdanm 82:6473597d706e 2340 #define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 4 on external event 9 */
bogdanm 82:6473597d706e 2341 #define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 4 on external event 10 */
bogdanm 82:6473597d706e 2342 #define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 4 on Timer A compare 2 */
bogdanm 82:6473597d706e 2343 #define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 4 on Timer A compare 3 */
bogdanm 82:6473597d706e 2344 #define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 4 on Timer A compare 4*/
bogdanm 82:6473597d706e 2345 #define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 4 on Timer A period */
bogdanm 82:6473597d706e 2346 #define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 4 on Timer B compare 2 */
bogdanm 82:6473597d706e 2347 #define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 4 on Timer B compare 3 */
bogdanm 82:6473597d706e 2348 #define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 4 on Timer B compare 4 */
bogdanm 82:6473597d706e 2349 #define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 4 on Timer B period */
bogdanm 82:6473597d706e 2350 #define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 4 on Timer C compare 2 */
bogdanm 82:6473597d706e 2351 #define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 4 on Timer C compare 3 */
bogdanm 82:6473597d706e 2352 #define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 4 on Timer C compare 4 */
bogdanm 82:6473597d706e 2353 #define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 4 on Timer C period */
bogdanm 82:6473597d706e 2354 #define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 4 on Timer C reset */
bogdanm 82:6473597d706e 2355 #define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 4 on Timer D compare 2 */
bogdanm 82:6473597d706e 2356 #define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 4 on Timer D compare 3 */
bogdanm 82:6473597d706e 2357 #define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 4 on Timer D compare 4*/
bogdanm 82:6473597d706e 2358 #define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 4 on Timer D period */
bogdanm 82:6473597d706e 2359 #define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 4 on Timer D reset */
bogdanm 82:6473597d706e 2360 #define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 4 on Timer E compare 2 */
bogdanm 82:6473597d706e 2361 #define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 4 on Timer E compare 3 */
bogdanm 82:6473597d706e 2362 #define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 4 on Timer E compare 4 */
bogdanm 82:6473597d706e 2363 #define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /*!< ADC Trigger 4 on Timer E reset */
bogdanm 82:6473597d706e 2364
bogdanm 82:6473597d706e 2365 /******************* Bit definition for HRTIM_DLLCR register ****************/
bogdanm 82:6473597d706e 2366 #define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /*!< DLL calibration start */
bogdanm 82:6473597d706e 2367 #define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /*!< DLL calibration enable */
bogdanm 82:6473597d706e 2368 #define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /*!< DLL calibration rate */
bogdanm 82:6473597d706e 2369 #define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /*!< DLL calibration rate bit 0 */
bogdanm 82:6473597d706e 2370 #define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /*!< DLL calibration rate bit 1 */
bogdanm 82:6473597d706e 2371
bogdanm 82:6473597d706e 2372 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
bogdanm 82:6473597d706e 2373 #define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /*!< Fault 1 enable */
bogdanm 82:6473597d706e 2374 #define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /*!< Fault 1 polarity */
bogdanm 82:6473597d706e 2375 #define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /*!< Fault 1 source */
bogdanm 82:6473597d706e 2376 #define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /*!< Fault 1 filter */
bogdanm 82:6473597d706e 2377 #define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /*!< Fault 1 filter bit 0 */
bogdanm 82:6473597d706e 2378 #define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /*!< Fault 1 filter bit 1 */
bogdanm 82:6473597d706e 2379 #define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /*!< Fault 1 filter bit 2 */
bogdanm 82:6473597d706e 2380 #define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /*!< Fault 1 filter bit 3 */
bogdanm 82:6473597d706e 2381 #define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /*!< Fault 1 lock */
bogdanm 82:6473597d706e 2382
bogdanm 82:6473597d706e 2383 #define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /*!< Fault 2 enable */
bogdanm 82:6473597d706e 2384 #define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /*!< Fault 2 polarity */
bogdanm 82:6473597d706e 2385 #define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /*!< Fault 2 source */
bogdanm 82:6473597d706e 2386 #define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /*!< Fault 2 filter */
bogdanm 82:6473597d706e 2387 #define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /*!< Fault 2 filter bit 0 */
bogdanm 82:6473597d706e 2388 #define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /*!< Fault 2 filter bit 1 */
bogdanm 82:6473597d706e 2389 #define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /*!< Fault 2 filter bit 2 */
bogdanm 82:6473597d706e 2390 #define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /*!< Fault 2 filter bit 3 */
bogdanm 82:6473597d706e 2391 #define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /*!< Fault 2 lock */
bogdanm 82:6473597d706e 2392
bogdanm 82:6473597d706e 2393 #define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /*!< Fault 3 enable */
bogdanm 82:6473597d706e 2394 #define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /*!< Fault 3 polarity */
bogdanm 82:6473597d706e 2395 #define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /*!< Fault 3 source */
bogdanm 82:6473597d706e 2396 #define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /*!< Fault 3 filter */
bogdanm 82:6473597d706e 2397 #define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /*!< Fault 3 filter bit 0 */
bogdanm 82:6473597d706e 2398 #define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /*!< Fault 3 filter bit 1 */
bogdanm 82:6473597d706e 2399 #define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /*!< Fault 3 filter bit 2 */
bogdanm 82:6473597d706e 2400 #define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /*!< Fault 3 filter bit 3 */
bogdanm 82:6473597d706e 2401 #define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /*!< Fault 3 lock */
bogdanm 82:6473597d706e 2402
bogdanm 82:6473597d706e 2403 #define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /*!< Fault 4 enable */
bogdanm 82:6473597d706e 2404 #define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /*!< Fault 4 polarity */
bogdanm 82:6473597d706e 2405 #define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /*!< Fault 4 source */
bogdanm 82:6473597d706e 2406 #define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /*!< Fault 4 filter */
bogdanm 82:6473597d706e 2407 #define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /*!< Fault 4 filter bit 0 */
bogdanm 82:6473597d706e 2408 #define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /*!< Fault 4 filter bit 1 */
bogdanm 82:6473597d706e 2409 #define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /*!< Fault 4 filter bit 2 */
bogdanm 82:6473597d706e 2410 #define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /*!< Fault 4 filter bit 3 */
bogdanm 82:6473597d706e 2411 #define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /*!< Fault 4 lock */
bogdanm 82:6473597d706e 2412
bogdanm 82:6473597d706e 2413 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
bogdanm 82:6473597d706e 2414 #define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /*!< Fault 5 enable */
bogdanm 82:6473597d706e 2415 #define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /*!< Fault 5 polarity */
bogdanm 82:6473597d706e 2416 #define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /*!< Fault 5 source */
bogdanm 82:6473597d706e 2417 #define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /*!< Fault 5 filter */
bogdanm 82:6473597d706e 2418 #define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /*!< Fault 5 filter bit 0 */
bogdanm 82:6473597d706e 2419 #define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /*!< Fault 5 filter bit 1 */
bogdanm 82:6473597d706e 2420 #define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /*!< Fault 5 filter bit 2 */
bogdanm 82:6473597d706e 2421 #define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /*!< Fault 5 filter bit 3 */
bogdanm 82:6473597d706e 2422 #define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /*!< Fault 5 lock */
bogdanm 82:6473597d706e 2423 #define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /*!< Fault sampling clock division */
bogdanm 82:6473597d706e 2424 #define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /*!< Fault sampling clock division bit 0 */
bogdanm 82:6473597d706e 2425 #define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /*!< Fault sampling clock division bit 1 */
bogdanm 82:6473597d706e 2426
bogdanm 82:6473597d706e 2427 /******************* Bit definition for HRTIM_BDMUPR register ***************/
bogdanm 82:6473597d706e 2428 #define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /*!< MCR register update enable */
bogdanm 82:6473597d706e 2429 #define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /*!< MICR register update enable */
bogdanm 82:6473597d706e 2430 #define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /*!< MDIER register update enable */
bogdanm 82:6473597d706e 2431 #define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /*!< MCNT register update enable */
bogdanm 82:6473597d706e 2432 #define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /*!< MPER register update enable */
bogdanm 82:6473597d706e 2433 #define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /*!< MREP register update enable */
bogdanm 82:6473597d706e 2434 #define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /*!< MCMP1 register update enable */
bogdanm 82:6473597d706e 2435 #define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /*!< MCMP2 register update enable */
bogdanm 82:6473597d706e 2436 #define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /*!< MCMP3 register update enable */
bogdanm 82:6473597d706e 2437 #define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /*!< MPCMP4 register update enable */
bogdanm 82:6473597d706e 2438
bogdanm 82:6473597d706e 2439 /******************* Bit definition for HRTIM_BDTUPR register ***************/
bogdanm 82:6473597d706e 2440 #define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /*!< TIMCR register update enable */
bogdanm 82:6473597d706e 2441 #define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /*!< TIMICR register update enable */
bogdanm 82:6473597d706e 2442 #define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /*!< TIMDIER register update enable */
bogdanm 82:6473597d706e 2443 #define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /*!< TIMCNT register update enable */
bogdanm 82:6473597d706e 2444 #define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /*!< TIMPER register update enable */
bogdanm 82:6473597d706e 2445 #define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /*!< TIMREP register update enable */
bogdanm 82:6473597d706e 2446 #define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /*!< TIMCMP1 register update enable */
bogdanm 82:6473597d706e 2447 #define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /*!< TIMCMP2 register update enable */
bogdanm 82:6473597d706e 2448 #define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /*!< TIMCMP3 register update enable */
bogdanm 82:6473597d706e 2449 #define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /*!< TIMCMP4 register update enable */
bogdanm 82:6473597d706e 2450 #define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /*!< TIMDTR register update enable */
bogdanm 82:6473597d706e 2451 #define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /*!< TIMSET1R register update enable */
bogdanm 82:6473597d706e 2452 #define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /*!< TIMRST1R register update enable */
bogdanm 82:6473597d706e 2453 #define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /*!< TIMSET2R register update enable */
bogdanm 82:6473597d706e 2454 #define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /*!< TIMRST2R register update enable */
bogdanm 82:6473597d706e 2455 #define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /*!< TIMEEFR1 register update enable */
bogdanm 82:6473597d706e 2456 #define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /*!< TIMEEFR2 register update enable */
bogdanm 82:6473597d706e 2457 #define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /*!< TIMRSTR register update enable */
bogdanm 82:6473597d706e 2458 #define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /*!< TIMCHPR register update enable */
bogdanm 82:6473597d706e 2459 #define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /*!< TIMOUTR register update enable */
bogdanm 82:6473597d706e 2460 #define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /*!< TIMFLTR register update enable */
bogdanm 82:6473597d706e 2461
bogdanm 82:6473597d706e 2462 /******************* Bit definition for HRTIM_BDMADR register ***************/
bogdanm 82:6473597d706e 2463 #define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /*!< Burst DMA Data register */
bogdanm 82:6473597d706e 2464
bogdanm 82:6473597d706e 2465 /******************************************************************************/
bogdanm 82:6473597d706e 2466 /* */
bogdanm 82:6473597d706e 2467 /* Analog to Digital Converter SAR (ADC) */
bogdanm 82:6473597d706e 2468 /* */
bogdanm 82:6473597d706e 2469 /******************************************************************************/
bogdanm 82:6473597d706e 2470 /******************** Bit definition for ADC_ISR register ********************/
bogdanm 82:6473597d706e 2471 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
bogdanm 82:6473597d706e 2472 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
bogdanm 82:6473597d706e 2473 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
bogdanm 82:6473597d706e 2474 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
bogdanm 82:6473597d706e 2475 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
bogdanm 82:6473597d706e 2476 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
bogdanm 82:6473597d706e 2477 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
bogdanm 82:6473597d706e 2478 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
bogdanm 82:6473597d706e 2479 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
bogdanm 82:6473597d706e 2480 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
bogdanm 82:6473597d706e 2481 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
bogdanm 82:6473597d706e 2482
bogdanm 82:6473597d706e 2483 /******************** Bit definition for ADC_IER register ********************/
bogdanm 82:6473597d706e 2484 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
bogdanm 82:6473597d706e 2485 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
bogdanm 82:6473597d706e 2486 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
bogdanm 82:6473597d706e 2487 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
bogdanm 82:6473597d706e 2488 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
bogdanm 82:6473597d706e 2489 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
bogdanm 82:6473597d706e 2490 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
bogdanm 82:6473597d706e 2491 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
bogdanm 82:6473597d706e 2492 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
bogdanm 82:6473597d706e 2493 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
bogdanm 82:6473597d706e 2494 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
bogdanm 82:6473597d706e 2495
bogdanm 82:6473597d706e 2496 /******************** Bit definition for ADC_CR register ********************/
bogdanm 82:6473597d706e 2497 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
bogdanm 82:6473597d706e 2498 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
bogdanm 82:6473597d706e 2499 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
bogdanm 82:6473597d706e 2500 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
bogdanm 82:6473597d706e 2501 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
bogdanm 82:6473597d706e 2502 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
bogdanm 82:6473597d706e 2503 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
bogdanm 82:6473597d706e 2504 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
bogdanm 82:6473597d706e 2505 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
bogdanm 82:6473597d706e 2506 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
bogdanm 82:6473597d706e 2507 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
bogdanm 82:6473597d706e 2508
bogdanm 82:6473597d706e 2509 /******************** Bit definition for ADC_CFGR register ********************/
bogdanm 82:6473597d706e 2510 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
bogdanm 82:6473597d706e 2511 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
bogdanm 82:6473597d706e 2512
bogdanm 82:6473597d706e 2513 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
bogdanm 82:6473597d706e 2514 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
bogdanm 82:6473597d706e 2515 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
bogdanm 82:6473597d706e 2516
bogdanm 82:6473597d706e 2517 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignment */
bogdanm 82:6473597d706e 2518
bogdanm 82:6473597d706e 2519 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
bogdanm 82:6473597d706e 2520 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
bogdanm 82:6473597d706e 2521 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
bogdanm 82:6473597d706e 2522 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
bogdanm 82:6473597d706e 2523 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
bogdanm 82:6473597d706e 2524
bogdanm 82:6473597d706e 2525 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
bogdanm 82:6473597d706e 2526 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
bogdanm 82:6473597d706e 2527 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
bogdanm 82:6473597d706e 2528
bogdanm 82:6473597d706e 2529 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
bogdanm 82:6473597d706e 2530 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
bogdanm 82:6473597d706e 2531 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
bogdanm 82:6473597d706e 2532 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
bogdanm 82:6473597d706e 2533
bogdanm 82:6473597d706e 2534 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
bogdanm 82:6473597d706e 2535 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
bogdanm 82:6473597d706e 2536 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
bogdanm 82:6473597d706e 2537 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
bogdanm 82:6473597d706e 2538
bogdanm 82:6473597d706e 2539 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinuous mode on injected channels */
bogdanm 82:6473597d706e 2540 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
bogdanm 82:6473597d706e 2541 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Enable the watchdog 1 on a single channel or on all channels */
bogdanm 82:6473597d706e 2542 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
bogdanm 82:6473597d706e 2543 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
bogdanm 82:6473597d706e 2544 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
bogdanm 82:6473597d706e 2545
bogdanm 82:6473597d706e 2546 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
bogdanm 82:6473597d706e 2547 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
bogdanm 82:6473597d706e 2548 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
bogdanm 82:6473597d706e 2549 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
bogdanm 82:6473597d706e 2550 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
bogdanm 82:6473597d706e 2551 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
bogdanm 82:6473597d706e 2552
bogdanm 82:6473597d706e 2553 /******************** Bit definition for ADC_SMPR1 register ********************/
bogdanm 82:6473597d706e 2554 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
bogdanm 82:6473597d706e 2555 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
bogdanm 82:6473597d706e 2556 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
bogdanm 82:6473597d706e 2557 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
bogdanm 82:6473597d706e 2558
bogdanm 82:6473597d706e 2559 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
bogdanm 82:6473597d706e 2560 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
bogdanm 82:6473597d706e 2561 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
bogdanm 82:6473597d706e 2562 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
bogdanm 82:6473597d706e 2563
bogdanm 82:6473597d706e 2564 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
bogdanm 82:6473597d706e 2565 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
bogdanm 82:6473597d706e 2566 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
bogdanm 82:6473597d706e 2567 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
bogdanm 82:6473597d706e 2568
bogdanm 82:6473597d706e 2569 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
bogdanm 82:6473597d706e 2570 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
bogdanm 82:6473597d706e 2571 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
bogdanm 82:6473597d706e 2572 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
bogdanm 82:6473597d706e 2573
bogdanm 82:6473597d706e 2574 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
bogdanm 82:6473597d706e 2575 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
bogdanm 82:6473597d706e 2576 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
bogdanm 82:6473597d706e 2577 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
bogdanm 82:6473597d706e 2578
bogdanm 82:6473597d706e 2579 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
bogdanm 82:6473597d706e 2580 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
bogdanm 82:6473597d706e 2581 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
bogdanm 82:6473597d706e 2582 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
bogdanm 82:6473597d706e 2583
bogdanm 82:6473597d706e 2584 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
bogdanm 82:6473597d706e 2585 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
bogdanm 82:6473597d706e 2586 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
bogdanm 82:6473597d706e 2587 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
bogdanm 82:6473597d706e 2588
bogdanm 82:6473597d706e 2589 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
bogdanm 82:6473597d706e 2590 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
bogdanm 82:6473597d706e 2591 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
bogdanm 82:6473597d706e 2592 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
bogdanm 82:6473597d706e 2593
bogdanm 82:6473597d706e 2594 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
bogdanm 82:6473597d706e 2595 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
bogdanm 82:6473597d706e 2596 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
bogdanm 82:6473597d706e 2597 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
bogdanm 82:6473597d706e 2598
bogdanm 82:6473597d706e 2599 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
bogdanm 82:6473597d706e 2600 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
bogdanm 82:6473597d706e 2601 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
bogdanm 82:6473597d706e 2602 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
bogdanm 82:6473597d706e 2603
bogdanm 82:6473597d706e 2604 /******************** Bit definition for ADC_SMPR2 register ********************/
bogdanm 82:6473597d706e 2605 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
bogdanm 82:6473597d706e 2606 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
bogdanm 82:6473597d706e 2607 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
bogdanm 82:6473597d706e 2608 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
bogdanm 82:6473597d706e 2609
bogdanm 82:6473597d706e 2610 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
bogdanm 82:6473597d706e 2611 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
bogdanm 82:6473597d706e 2612 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
bogdanm 82:6473597d706e 2613 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
bogdanm 82:6473597d706e 2614
bogdanm 82:6473597d706e 2615 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
bogdanm 82:6473597d706e 2616 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
bogdanm 82:6473597d706e 2617 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
bogdanm 82:6473597d706e 2618 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
bogdanm 82:6473597d706e 2619
bogdanm 82:6473597d706e 2620 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
bogdanm 82:6473597d706e 2621 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
bogdanm 82:6473597d706e 2622 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
bogdanm 82:6473597d706e 2623 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
bogdanm 82:6473597d706e 2624
bogdanm 82:6473597d706e 2625 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
bogdanm 82:6473597d706e 2626 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
bogdanm 82:6473597d706e 2627 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
bogdanm 82:6473597d706e 2628 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
bogdanm 82:6473597d706e 2629
bogdanm 82:6473597d706e 2630 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
bogdanm 82:6473597d706e 2631 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
bogdanm 82:6473597d706e 2632 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
bogdanm 82:6473597d706e 2633 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
bogdanm 82:6473597d706e 2634
bogdanm 82:6473597d706e 2635 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
bogdanm 82:6473597d706e 2636 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
bogdanm 82:6473597d706e 2637 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
bogdanm 82:6473597d706e 2638 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
bogdanm 82:6473597d706e 2639
bogdanm 82:6473597d706e 2640 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
bogdanm 82:6473597d706e 2641 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
bogdanm 82:6473597d706e 2642 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
bogdanm 82:6473597d706e 2643 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
bogdanm 82:6473597d706e 2644
bogdanm 82:6473597d706e 2645 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
bogdanm 82:6473597d706e 2646 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
bogdanm 82:6473597d706e 2647 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
bogdanm 82:6473597d706e 2648 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
bogdanm 82:6473597d706e 2649
bogdanm 82:6473597d706e 2650 /******************** Bit definition for ADC_TR1 register ********************/
bogdanm 82:6473597d706e 2651 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
bogdanm 82:6473597d706e 2652 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
bogdanm 82:6473597d706e 2653 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
bogdanm 82:6473597d706e 2654 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
bogdanm 82:6473597d706e 2655 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
bogdanm 82:6473597d706e 2656 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
bogdanm 82:6473597d706e 2657 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
bogdanm 82:6473597d706e 2658 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
bogdanm 82:6473597d706e 2659 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
bogdanm 82:6473597d706e 2660 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
bogdanm 82:6473597d706e 2661 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
bogdanm 82:6473597d706e 2662 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
bogdanm 82:6473597d706e 2663 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
bogdanm 82:6473597d706e 2664
bogdanm 82:6473597d706e 2665 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
bogdanm 82:6473597d706e 2666 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
bogdanm 82:6473597d706e 2667 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
bogdanm 82:6473597d706e 2668 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
bogdanm 82:6473597d706e 2669 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
bogdanm 82:6473597d706e 2670 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
bogdanm 82:6473597d706e 2671 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
bogdanm 82:6473597d706e 2672 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
bogdanm 82:6473597d706e 2673 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
bogdanm 82:6473597d706e 2674 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
bogdanm 82:6473597d706e 2675 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
bogdanm 82:6473597d706e 2676 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
bogdanm 82:6473597d706e 2677 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
bogdanm 82:6473597d706e 2678
bogdanm 82:6473597d706e 2679 /******************** Bit definition for ADC_TR2 register ********************/
bogdanm 82:6473597d706e 2680 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
bogdanm 82:6473597d706e 2681 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
bogdanm 82:6473597d706e 2682 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
bogdanm 82:6473597d706e 2683 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
bogdanm 82:6473597d706e 2684 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
bogdanm 82:6473597d706e 2685 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
bogdanm 82:6473597d706e 2686 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
bogdanm 82:6473597d706e 2687 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
bogdanm 82:6473597d706e 2688 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
bogdanm 82:6473597d706e 2689
bogdanm 82:6473597d706e 2690 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
bogdanm 82:6473597d706e 2691 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
bogdanm 82:6473597d706e 2692 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
bogdanm 82:6473597d706e 2693 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
bogdanm 82:6473597d706e 2694 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
bogdanm 82:6473597d706e 2695 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
bogdanm 82:6473597d706e 2696 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
bogdanm 82:6473597d706e 2697 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
bogdanm 82:6473597d706e 2698 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
bogdanm 82:6473597d706e 2699
bogdanm 82:6473597d706e 2700 /******************** Bit definition for ADC_TR3 register ********************/
bogdanm 82:6473597d706e 2701 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
bogdanm 82:6473597d706e 2702 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
bogdanm 82:6473597d706e 2703 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
bogdanm 82:6473597d706e 2704 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
bogdanm 82:6473597d706e 2705 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
bogdanm 82:6473597d706e 2706 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
bogdanm 82:6473597d706e 2707 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
bogdanm 82:6473597d706e 2708 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
bogdanm 82:6473597d706e 2709 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
bogdanm 82:6473597d706e 2710
bogdanm 82:6473597d706e 2711 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
bogdanm 82:6473597d706e 2712 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
bogdanm 82:6473597d706e 2713 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
bogdanm 82:6473597d706e 2714 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
bogdanm 82:6473597d706e 2715 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
bogdanm 82:6473597d706e 2716 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
bogdanm 82:6473597d706e 2717 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
bogdanm 82:6473597d706e 2718 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
bogdanm 82:6473597d706e 2719 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
bogdanm 82:6473597d706e 2720
bogdanm 82:6473597d706e 2721 /******************** Bit definition for ADC_SQR1 register ********************/
bogdanm 82:6473597d706e 2722 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence length */
bogdanm 82:6473597d706e 2723 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
bogdanm 82:6473597d706e 2724 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
bogdanm 82:6473597d706e 2725 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
bogdanm 82:6473597d706e 2726 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
bogdanm 82:6473597d706e 2727
bogdanm 82:6473597d706e 2728 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
bogdanm 82:6473597d706e 2729 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
bogdanm 82:6473597d706e 2730 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
bogdanm 82:6473597d706e 2731 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
bogdanm 82:6473597d706e 2732 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
bogdanm 82:6473597d706e 2733 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
bogdanm 82:6473597d706e 2734
bogdanm 82:6473597d706e 2735 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
bogdanm 82:6473597d706e 2736 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
bogdanm 82:6473597d706e 2737 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
bogdanm 82:6473597d706e 2738 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
bogdanm 82:6473597d706e 2739 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
bogdanm 82:6473597d706e 2740 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
bogdanm 82:6473597d706e 2741
bogdanm 82:6473597d706e 2742 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
bogdanm 82:6473597d706e 2743 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
bogdanm 82:6473597d706e 2744 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
bogdanm 82:6473597d706e 2745 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
bogdanm 82:6473597d706e 2746 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
bogdanm 82:6473597d706e 2747 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
bogdanm 82:6473597d706e 2748
bogdanm 82:6473597d706e 2749 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
bogdanm 82:6473597d706e 2750 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
bogdanm 82:6473597d706e 2751 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
bogdanm 82:6473597d706e 2752 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
bogdanm 82:6473597d706e 2753 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
bogdanm 82:6473597d706e 2754 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
bogdanm 82:6473597d706e 2755
bogdanm 82:6473597d706e 2756 /******************** Bit definition for ADC_SQR2 register ********************/
bogdanm 82:6473597d706e 2757 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
bogdanm 82:6473597d706e 2758 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
bogdanm 82:6473597d706e 2759 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
bogdanm 82:6473597d706e 2760 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
bogdanm 82:6473597d706e 2761 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
bogdanm 82:6473597d706e 2762 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
bogdanm 82:6473597d706e 2763
bogdanm 82:6473597d706e 2764 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
bogdanm 82:6473597d706e 2765 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
bogdanm 82:6473597d706e 2766 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
bogdanm 82:6473597d706e 2767 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
bogdanm 82:6473597d706e 2768 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
bogdanm 82:6473597d706e 2769 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
bogdanm 82:6473597d706e 2770
bogdanm 82:6473597d706e 2771 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
bogdanm 82:6473597d706e 2772 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
bogdanm 82:6473597d706e 2773 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
bogdanm 82:6473597d706e 2774 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
bogdanm 82:6473597d706e 2775 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
bogdanm 82:6473597d706e 2776 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
bogdanm 82:6473597d706e 2777
bogdanm 82:6473597d706e 2778 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
bogdanm 82:6473597d706e 2779 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
bogdanm 82:6473597d706e 2780 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
bogdanm 82:6473597d706e 2781 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
bogdanm 82:6473597d706e 2782 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
bogdanm 82:6473597d706e 2783 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
bogdanm 82:6473597d706e 2784
bogdanm 82:6473597d706e 2785 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
bogdanm 82:6473597d706e 2786 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
bogdanm 82:6473597d706e 2787 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
bogdanm 82:6473597d706e 2788 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
bogdanm 82:6473597d706e 2789 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
bogdanm 82:6473597d706e 2790 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
bogdanm 82:6473597d706e 2791
bogdanm 82:6473597d706e 2792 /******************** Bit definition for ADC_SQR3 register ********************/
bogdanm 82:6473597d706e 2793 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
bogdanm 82:6473597d706e 2794 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
bogdanm 82:6473597d706e 2795 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
bogdanm 82:6473597d706e 2796 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
bogdanm 82:6473597d706e 2797 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
bogdanm 82:6473597d706e 2798 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
bogdanm 82:6473597d706e 2799
bogdanm 82:6473597d706e 2800 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
bogdanm 82:6473597d706e 2801 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
bogdanm 82:6473597d706e 2802 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
bogdanm 82:6473597d706e 2803 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
bogdanm 82:6473597d706e 2804 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
bogdanm 82:6473597d706e 2805 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
bogdanm 82:6473597d706e 2806
bogdanm 82:6473597d706e 2807 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
bogdanm 82:6473597d706e 2808 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
bogdanm 82:6473597d706e 2809 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
bogdanm 82:6473597d706e 2810 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
bogdanm 82:6473597d706e 2811 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
bogdanm 82:6473597d706e 2812 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
bogdanm 82:6473597d706e 2813
bogdanm 82:6473597d706e 2814 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
bogdanm 82:6473597d706e 2815 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
bogdanm 82:6473597d706e 2816 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
bogdanm 82:6473597d706e 2817 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
bogdanm 82:6473597d706e 2818 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
bogdanm 82:6473597d706e 2819 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
bogdanm 82:6473597d706e 2820
bogdanm 82:6473597d706e 2821 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
bogdanm 82:6473597d706e 2822 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
bogdanm 82:6473597d706e 2823 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
bogdanm 82:6473597d706e 2824 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
bogdanm 82:6473597d706e 2825 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
bogdanm 82:6473597d706e 2826 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
bogdanm 82:6473597d706e 2827
bogdanm 82:6473597d706e 2828 /******************** Bit definition for ADC_SQR4 register ********************/
bogdanm 82:6473597d706e 2829 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
bogdanm 82:6473597d706e 2830 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
bogdanm 82:6473597d706e 2831 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
bogdanm 82:6473597d706e 2832 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
bogdanm 82:6473597d706e 2833 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
bogdanm 82:6473597d706e 2834 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
bogdanm 82:6473597d706e 2835
bogdanm 82:6473597d706e 2836 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
bogdanm 82:6473597d706e 2837 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
bogdanm 82:6473597d706e 2838 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
bogdanm 82:6473597d706e 2839 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
bogdanm 82:6473597d706e 2840 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
bogdanm 82:6473597d706e 2841 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
bogdanm 82:6473597d706e 2842
bogdanm 82:6473597d706e 2843 /* these defines are maintained for legacy purpose */
bogdanm 82:6473597d706e 2844 #define ADC_SQR3_SQ15 ADC_SQR4_SQ15 /*!< ADC 15th conversion in regular sequence */
bogdanm 82:6473597d706e 2845 #define ADC_SQR3_SQ15_0 ADC_SQR4_SQ15_0 /*!< ADC SQ15 bit 0 */
bogdanm 82:6473597d706e 2846 #define ADC_SQR3_SQ15_1 ADC_SQR4_SQ15_1 /*!< ADC SQ15 bit 1 */
bogdanm 82:6473597d706e 2847 #define ADC_SQR3_SQ15_2 ADC_SQR4_SQ15_2 /*!< ADC SQ15 bit 2 */
bogdanm 82:6473597d706e 2848 #define ADC_SQR3_SQ15_3 ADC_SQR4_SQ15_3 /*!< ADC SQ15 bit 3 */
bogdanm 82:6473597d706e 2849 #define ADC_SQR3_SQ15_4 ADC_SQR4_SQ15_4 /*!< ADC SQ105 bit 4 */
bogdanm 82:6473597d706e 2850
bogdanm 82:6473597d706e 2851 #define ADC_SQR3_SQ16 ADC_SQR4_SQ16 /*!< ADC 16th conversion in regular sequence */
bogdanm 82:6473597d706e 2852 #define ADC_SQR3_SQ16_0 ADC_SQR4_SQ16_0 /*!< ADC SQ16 bit 0 */
bogdanm 82:6473597d706e 2853 #define ADC_SQR3_SQ16_1 ADC_SQR4_SQ16_1 /*!< ADC SQ16 bit 1 */
bogdanm 82:6473597d706e 2854 #define ADC_SQR3_SQ16_2 ADC_SQR4_SQ16_2 /*!< ADC SQ16 bit 2 */
bogdanm 82:6473597d706e 2855 #define ADC_SQR3_SQ16_3 ADC_SQR4_SQ16_3 /*!< ADC SQ16 bit 3 */
bogdanm 82:6473597d706e 2856 #define ADC_SQR3_SQ16_4 ADC_SQR4_SQ16_4 /*!< ADC SQ16 bit 4 */
bogdanm 82:6473597d706e 2857 /******************** Bit definition for ADC_DR register ********************/
bogdanm 82:6473597d706e 2858 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
bogdanm 82:6473597d706e 2859 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
bogdanm 82:6473597d706e 2860 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
bogdanm 82:6473597d706e 2861 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
bogdanm 82:6473597d706e 2862 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
bogdanm 82:6473597d706e 2863 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
bogdanm 82:6473597d706e 2864 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
bogdanm 82:6473597d706e 2865 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
bogdanm 82:6473597d706e 2866 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
bogdanm 82:6473597d706e 2867 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
bogdanm 82:6473597d706e 2868 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
bogdanm 82:6473597d706e 2869 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
bogdanm 82:6473597d706e 2870 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
bogdanm 82:6473597d706e 2871 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
bogdanm 82:6473597d706e 2872 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
bogdanm 82:6473597d706e 2873 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
bogdanm 82:6473597d706e 2874 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
bogdanm 82:6473597d706e 2875
bogdanm 82:6473597d706e 2876 /******************** Bit definition for ADC_JSQR register ********************/
bogdanm 82:6473597d706e 2877 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
bogdanm 82:6473597d706e 2878 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
bogdanm 82:6473597d706e 2879 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
bogdanm 82:6473597d706e 2880
bogdanm 82:6473597d706e 2881 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
bogdanm 82:6473597d706e 2882 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
bogdanm 82:6473597d706e 2883 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
bogdanm 82:6473597d706e 2884 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
bogdanm 82:6473597d706e 2885 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
bogdanm 82:6473597d706e 2886
bogdanm 82:6473597d706e 2887 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
bogdanm 82:6473597d706e 2888 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
bogdanm 82:6473597d706e 2889 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
bogdanm 82:6473597d706e 2890
bogdanm 82:6473597d706e 2891 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
bogdanm 82:6473597d706e 2892 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
bogdanm 82:6473597d706e 2893 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
bogdanm 82:6473597d706e 2894 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
bogdanm 82:6473597d706e 2895 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
bogdanm 82:6473597d706e 2896 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
bogdanm 82:6473597d706e 2897
bogdanm 82:6473597d706e 2898 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
bogdanm 82:6473597d706e 2899 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
bogdanm 82:6473597d706e 2900 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
bogdanm 82:6473597d706e 2901 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
bogdanm 82:6473597d706e 2902 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
bogdanm 82:6473597d706e 2903 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
bogdanm 82:6473597d706e 2904
bogdanm 82:6473597d706e 2905 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
bogdanm 82:6473597d706e 2906 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
bogdanm 82:6473597d706e 2907 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
bogdanm 82:6473597d706e 2908 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
bogdanm 82:6473597d706e 2909 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
bogdanm 82:6473597d706e 2910 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
bogdanm 82:6473597d706e 2911
bogdanm 82:6473597d706e 2912 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
bogdanm 82:6473597d706e 2913 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
bogdanm 82:6473597d706e 2914 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
bogdanm 82:6473597d706e 2915 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
bogdanm 82:6473597d706e 2916 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
bogdanm 82:6473597d706e 2917 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
bogdanm 82:6473597d706e 2918
bogdanm 82:6473597d706e 2919 /******************** Bit definition for ADC_OFR1 register ********************/
bogdanm 82:6473597d706e 2920 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
bogdanm 82:6473597d706e 2921 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
bogdanm 82:6473597d706e 2922 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
bogdanm 82:6473597d706e 2923 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
bogdanm 82:6473597d706e 2924 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
bogdanm 82:6473597d706e 2925 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
bogdanm 82:6473597d706e 2926 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
bogdanm 82:6473597d706e 2927 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
bogdanm 82:6473597d706e 2928 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
bogdanm 82:6473597d706e 2929 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
bogdanm 82:6473597d706e 2930 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
bogdanm 82:6473597d706e 2931 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
bogdanm 82:6473597d706e 2932 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
bogdanm 82:6473597d706e 2933
bogdanm 82:6473597d706e 2934 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
bogdanm 82:6473597d706e 2935 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
bogdanm 82:6473597d706e 2936 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
bogdanm 82:6473597d706e 2937 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
bogdanm 82:6473597d706e 2938 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
bogdanm 82:6473597d706e 2939 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
bogdanm 82:6473597d706e 2940
bogdanm 82:6473597d706e 2941 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
bogdanm 82:6473597d706e 2942
bogdanm 82:6473597d706e 2943 /******************** Bit definition for ADC_OFR2 register ********************/
bogdanm 82:6473597d706e 2944 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
bogdanm 82:6473597d706e 2945 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
bogdanm 82:6473597d706e 2946 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
bogdanm 82:6473597d706e 2947 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
bogdanm 82:6473597d706e 2948 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
bogdanm 82:6473597d706e 2949 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
bogdanm 82:6473597d706e 2950 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
bogdanm 82:6473597d706e 2951 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
bogdanm 82:6473597d706e 2952 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
bogdanm 82:6473597d706e 2953 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
bogdanm 82:6473597d706e 2954 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
bogdanm 82:6473597d706e 2955 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
bogdanm 82:6473597d706e 2956 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
bogdanm 82:6473597d706e 2957
bogdanm 82:6473597d706e 2958 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
bogdanm 82:6473597d706e 2959 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
bogdanm 82:6473597d706e 2960 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
bogdanm 82:6473597d706e 2961 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
bogdanm 82:6473597d706e 2962 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
bogdanm 82:6473597d706e 2963 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
bogdanm 82:6473597d706e 2964
bogdanm 82:6473597d706e 2965 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
bogdanm 82:6473597d706e 2966
bogdanm 82:6473597d706e 2967 /******************** Bit definition for ADC_OFR3 register ********************/
bogdanm 82:6473597d706e 2968 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
bogdanm 82:6473597d706e 2969 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
bogdanm 82:6473597d706e 2970 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
bogdanm 82:6473597d706e 2971 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
bogdanm 82:6473597d706e 2972 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
bogdanm 82:6473597d706e 2973 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
bogdanm 82:6473597d706e 2974 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
bogdanm 82:6473597d706e 2975 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
bogdanm 82:6473597d706e 2976 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
bogdanm 82:6473597d706e 2977 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
bogdanm 82:6473597d706e 2978 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
bogdanm 82:6473597d706e 2979 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
bogdanm 82:6473597d706e 2980 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
bogdanm 82:6473597d706e 2981
bogdanm 82:6473597d706e 2982 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
bogdanm 82:6473597d706e 2983 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
bogdanm 82:6473597d706e 2984 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
bogdanm 82:6473597d706e 2985 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
bogdanm 82:6473597d706e 2986 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
bogdanm 82:6473597d706e 2987 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
bogdanm 82:6473597d706e 2988
bogdanm 82:6473597d706e 2989 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
bogdanm 82:6473597d706e 2990
bogdanm 82:6473597d706e 2991 /******************** Bit definition for ADC_OFR4 register ********************/
bogdanm 82:6473597d706e 2992 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
bogdanm 82:6473597d706e 2993 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
bogdanm 82:6473597d706e 2994 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
bogdanm 82:6473597d706e 2995 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
bogdanm 82:6473597d706e 2996 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
bogdanm 82:6473597d706e 2997 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
bogdanm 82:6473597d706e 2998 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
bogdanm 82:6473597d706e 2999 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
bogdanm 82:6473597d706e 3000 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
bogdanm 82:6473597d706e 3001 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
bogdanm 82:6473597d706e 3002 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
bogdanm 82:6473597d706e 3003 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
bogdanm 82:6473597d706e 3004 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
bogdanm 82:6473597d706e 3005
bogdanm 82:6473597d706e 3006 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
bogdanm 82:6473597d706e 3007 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
bogdanm 82:6473597d706e 3008 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
bogdanm 82:6473597d706e 3009 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
bogdanm 82:6473597d706e 3010 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
bogdanm 82:6473597d706e 3011 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
bogdanm 82:6473597d706e 3012
bogdanm 82:6473597d706e 3013 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
bogdanm 82:6473597d706e 3014
bogdanm 82:6473597d706e 3015 /******************** Bit definition for ADC_JDR1 register ********************/
bogdanm 82:6473597d706e 3016 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
bogdanm 82:6473597d706e 3017 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
bogdanm 82:6473597d706e 3018 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
bogdanm 82:6473597d706e 3019 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
bogdanm 82:6473597d706e 3020 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
bogdanm 82:6473597d706e 3021 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
bogdanm 82:6473597d706e 3022 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
bogdanm 82:6473597d706e 3023 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
bogdanm 82:6473597d706e 3024 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
bogdanm 82:6473597d706e 3025 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
bogdanm 82:6473597d706e 3026 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
bogdanm 82:6473597d706e 3027 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
bogdanm 82:6473597d706e 3028 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
bogdanm 82:6473597d706e 3029 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
bogdanm 82:6473597d706e 3030 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
bogdanm 82:6473597d706e 3031 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
bogdanm 82:6473597d706e 3032 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
bogdanm 82:6473597d706e 3033
bogdanm 82:6473597d706e 3034 /******************** Bit definition for ADC_JDR2 register ********************/
bogdanm 82:6473597d706e 3035 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
bogdanm 82:6473597d706e 3036 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
bogdanm 82:6473597d706e 3037 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
bogdanm 82:6473597d706e 3038 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
bogdanm 82:6473597d706e 3039 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
bogdanm 82:6473597d706e 3040 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
bogdanm 82:6473597d706e 3041 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
bogdanm 82:6473597d706e 3042 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
bogdanm 82:6473597d706e 3043 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
bogdanm 82:6473597d706e 3044 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
bogdanm 82:6473597d706e 3045 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
bogdanm 82:6473597d706e 3046 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
bogdanm 82:6473597d706e 3047 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
bogdanm 82:6473597d706e 3048 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
bogdanm 82:6473597d706e 3049 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
bogdanm 82:6473597d706e 3050 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
bogdanm 82:6473597d706e 3051 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
bogdanm 82:6473597d706e 3052
bogdanm 82:6473597d706e 3053 /******************** Bit definition for ADC_JDR3 register ********************/
bogdanm 82:6473597d706e 3054 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
bogdanm 82:6473597d706e 3055 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
bogdanm 82:6473597d706e 3056 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
bogdanm 82:6473597d706e 3057 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
bogdanm 82:6473597d706e 3058 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
bogdanm 82:6473597d706e 3059 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
bogdanm 82:6473597d706e 3060 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
bogdanm 82:6473597d706e 3061 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
bogdanm 82:6473597d706e 3062 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
bogdanm 82:6473597d706e 3063 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
bogdanm 82:6473597d706e 3064 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
bogdanm 82:6473597d706e 3065 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
bogdanm 82:6473597d706e 3066 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
bogdanm 82:6473597d706e 3067 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
bogdanm 82:6473597d706e 3068 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
bogdanm 82:6473597d706e 3069 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
bogdanm 82:6473597d706e 3070 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
bogdanm 82:6473597d706e 3071
bogdanm 82:6473597d706e 3072 /******************** Bit definition for ADC_JDR4 register ********************/
bogdanm 82:6473597d706e 3073 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
bogdanm 82:6473597d706e 3074 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
bogdanm 82:6473597d706e 3075 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
bogdanm 82:6473597d706e 3076 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
bogdanm 82:6473597d706e 3077 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
bogdanm 82:6473597d706e 3078 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
bogdanm 82:6473597d706e 3079 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
bogdanm 82:6473597d706e 3080 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
bogdanm 82:6473597d706e 3081 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
bogdanm 82:6473597d706e 3082 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
bogdanm 82:6473597d706e 3083 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
bogdanm 82:6473597d706e 3084 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
bogdanm 82:6473597d706e 3085 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
bogdanm 82:6473597d706e 3086 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
bogdanm 82:6473597d706e 3087 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
bogdanm 82:6473597d706e 3088 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
bogdanm 82:6473597d706e 3089 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
bogdanm 82:6473597d706e 3090
bogdanm 82:6473597d706e 3091 /******************** Bit definition for ADC_AWD2CR register ********************/
bogdanm 82:6473597d706e 3092 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
bogdanm 82:6473597d706e 3093 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
bogdanm 82:6473597d706e 3094 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
bogdanm 82:6473597d706e 3095 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
bogdanm 82:6473597d706e 3096 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
bogdanm 82:6473597d706e 3097 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
bogdanm 82:6473597d706e 3098 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
bogdanm 82:6473597d706e 3099 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
bogdanm 82:6473597d706e 3100 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
bogdanm 82:6473597d706e 3101 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
bogdanm 82:6473597d706e 3102 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
bogdanm 82:6473597d706e 3103 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
bogdanm 82:6473597d706e 3104 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
bogdanm 82:6473597d706e 3105 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
bogdanm 82:6473597d706e 3106 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
bogdanm 82:6473597d706e 3107 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
bogdanm 82:6473597d706e 3108 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
bogdanm 82:6473597d706e 3109 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
bogdanm 82:6473597d706e 3110 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
bogdanm 82:6473597d706e 3111
bogdanm 82:6473597d706e 3112 /******************** Bit definition for ADC_AWD3CR register ********************/
bogdanm 82:6473597d706e 3113 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
bogdanm 82:6473597d706e 3114 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
bogdanm 82:6473597d706e 3115 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
bogdanm 82:6473597d706e 3116 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
bogdanm 82:6473597d706e 3117 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
bogdanm 82:6473597d706e 3118 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
bogdanm 82:6473597d706e 3119 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
bogdanm 82:6473597d706e 3120 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
bogdanm 82:6473597d706e 3121 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
bogdanm 82:6473597d706e 3122 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
bogdanm 82:6473597d706e 3123 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
bogdanm 82:6473597d706e 3124 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
bogdanm 82:6473597d706e 3125 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
bogdanm 82:6473597d706e 3126 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
bogdanm 82:6473597d706e 3127 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
bogdanm 82:6473597d706e 3128 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
bogdanm 82:6473597d706e 3129 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
bogdanm 82:6473597d706e 3130 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
bogdanm 82:6473597d706e 3131 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
bogdanm 82:6473597d706e 3132
bogdanm 82:6473597d706e 3133 /******************** Bit definition for ADC_DIFSEL register ********************/
bogdanm 82:6473597d706e 3134 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
bogdanm 82:6473597d706e 3135 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
bogdanm 82:6473597d706e 3136 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
bogdanm 82:6473597d706e 3137 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
bogdanm 82:6473597d706e 3138 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
bogdanm 82:6473597d706e 3139 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
bogdanm 82:6473597d706e 3140 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
bogdanm 82:6473597d706e 3141 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
bogdanm 82:6473597d706e 3142 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
bogdanm 82:6473597d706e 3143 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
bogdanm 82:6473597d706e 3144 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
bogdanm 82:6473597d706e 3145 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
bogdanm 82:6473597d706e 3146 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
bogdanm 82:6473597d706e 3147 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
bogdanm 82:6473597d706e 3148 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
bogdanm 82:6473597d706e 3149 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
bogdanm 82:6473597d706e 3150 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
bogdanm 82:6473597d706e 3151 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
bogdanm 82:6473597d706e 3152 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
bogdanm 82:6473597d706e 3153
bogdanm 82:6473597d706e 3154 /******************** Bit definition for ADC_CALFACT register ********************/
bogdanm 82:6473597d706e 3155 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
bogdanm 82:6473597d706e 3156 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
bogdanm 82:6473597d706e 3157 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
bogdanm 82:6473597d706e 3158 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
bogdanm 82:6473597d706e 3159 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
bogdanm 82:6473597d706e 3160 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
bogdanm 82:6473597d706e 3161 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
bogdanm 82:6473597d706e 3162 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
bogdanm 82:6473597d706e 3163 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
bogdanm 82:6473597d706e 3164 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
bogdanm 82:6473597d706e 3165 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
bogdanm 82:6473597d706e 3166 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
bogdanm 82:6473597d706e 3167 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
bogdanm 82:6473597d706e 3168 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
bogdanm 82:6473597d706e 3169 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
bogdanm 82:6473597d706e 3170 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
bogdanm 82:6473597d706e 3171
bogdanm 82:6473597d706e 3172 /************************* ADC Common registers *****************************/
bogdanm 82:6473597d706e 3173 /******************** Bit definition for ADC12_CSR register ********************/
bogdanm 82:6473597d706e 3174 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
bogdanm 82:6473597d706e 3175 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
bogdanm 82:6473597d706e 3176 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
bogdanm 82:6473597d706e 3177 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
bogdanm 82:6473597d706e 3178 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
bogdanm 82:6473597d706e 3179 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
bogdanm 82:6473597d706e 3180 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
bogdanm 82:6473597d706e 3181 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
bogdanm 82:6473597d706e 3182 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
bogdanm 82:6473597d706e 3183 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
bogdanm 82:6473597d706e 3184 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
bogdanm 82:6473597d706e 3185 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
bogdanm 82:6473597d706e 3186 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
bogdanm 82:6473597d706e 3187 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
bogdanm 82:6473597d706e 3188 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
bogdanm 82:6473597d706e 3189 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
bogdanm 82:6473597d706e 3190 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
bogdanm 82:6473597d706e 3191 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
bogdanm 82:6473597d706e 3192 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
bogdanm 82:6473597d706e 3193 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
bogdanm 82:6473597d706e 3194 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
bogdanm 82:6473597d706e 3195 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
bogdanm 82:6473597d706e 3196
bogdanm 82:6473597d706e 3197 /******************** Bit definition for ADC34_CSR register ********************/
bogdanm 82:6473597d706e 3198 #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
bogdanm 82:6473597d706e 3199 #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
bogdanm 82:6473597d706e 3200 #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
bogdanm 82:6473597d706e 3201 #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
bogdanm 82:6473597d706e 3202 #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
bogdanm 82:6473597d706e 3203 #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
bogdanm 82:6473597d706e 3204 #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
bogdanm 82:6473597d706e 3205 #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
bogdanm 82:6473597d706e 3206 #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
bogdanm 82:6473597d706e 3207 #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
bogdanm 82:6473597d706e 3208 #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
bogdanm 82:6473597d706e 3209 #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
bogdanm 82:6473597d706e 3210 #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
bogdanm 82:6473597d706e 3211 #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
bogdanm 82:6473597d706e 3212 #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
bogdanm 82:6473597d706e 3213 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
bogdanm 82:6473597d706e 3214 #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
bogdanm 82:6473597d706e 3215 #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
bogdanm 82:6473597d706e 3216 #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
bogdanm 82:6473597d706e 3217 #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
bogdanm 82:6473597d706e 3218 #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
bogdanm 82:6473597d706e 3219 #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
bogdanm 82:6473597d706e 3220
bogdanm 82:6473597d706e 3221 /******************** Bit definition for ADC_CCR register ********************/
bogdanm 82:6473597d706e 3222 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
bogdanm 82:6473597d706e 3223 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
bogdanm 82:6473597d706e 3224 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
bogdanm 82:6473597d706e 3225 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
bogdanm 82:6473597d706e 3226 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
bogdanm 82:6473597d706e 3227 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
bogdanm 82:6473597d706e 3228 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
bogdanm 82:6473597d706e 3229 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
bogdanm 82:6473597d706e 3230 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
bogdanm 82:6473597d706e 3231 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
bogdanm 82:6473597d706e 3232 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
bogdanm 82:6473597d706e 3233 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
bogdanm 82:6473597d706e 3234 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
bogdanm 82:6473597d706e 3235 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
bogdanm 82:6473597d706e 3236 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
bogdanm 82:6473597d706e 3237 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
bogdanm 82:6473597d706e 3238 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
bogdanm 82:6473597d706e 3239 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
bogdanm 82:6473597d706e 3240 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
bogdanm 82:6473597d706e 3241 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
bogdanm 82:6473597d706e 3242 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
bogdanm 82:6473597d706e 3243
bogdanm 82:6473597d706e 3244 /******************** Bit definition for ADC_CCR register ********************/
bogdanm 82:6473597d706e 3245 #define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
bogdanm 82:6473597d706e 3246 #define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
bogdanm 82:6473597d706e 3247 #define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
bogdanm 82:6473597d706e 3248 #define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
bogdanm 82:6473597d706e 3249 #define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
bogdanm 82:6473597d706e 3250 #define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
bogdanm 82:6473597d706e 3251
bogdanm 82:6473597d706e 3252 #define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
bogdanm 82:6473597d706e 3253 #define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
bogdanm 82:6473597d706e 3254 #define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
bogdanm 82:6473597d706e 3255 #define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
bogdanm 82:6473597d706e 3256 #define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
bogdanm 82:6473597d706e 3257
bogdanm 82:6473597d706e 3258 #define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
bogdanm 82:6473597d706e 3259 #define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
bogdanm 82:6473597d706e 3260 #define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
bogdanm 82:6473597d706e 3261 #define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
bogdanm 82:6473597d706e 3262
bogdanm 82:6473597d706e 3263 #define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
bogdanm 82:6473597d706e 3264 #define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
bogdanm 82:6473597d706e 3265 #define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
bogdanm 82:6473597d706e 3266
bogdanm 82:6473597d706e 3267 #define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
bogdanm 82:6473597d706e 3268
bogdanm 82:6473597d706e 3269 /******************** Bit definition for ADC_CDR register ********************/
bogdanm 82:6473597d706e 3270 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
bogdanm 82:6473597d706e 3271 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
bogdanm 82:6473597d706e 3272 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
bogdanm 82:6473597d706e 3273 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
bogdanm 82:6473597d706e 3274 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
bogdanm 82:6473597d706e 3275 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
bogdanm 82:6473597d706e 3276 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
bogdanm 82:6473597d706e 3277 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
bogdanm 82:6473597d706e 3278 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
bogdanm 82:6473597d706e 3279 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
bogdanm 82:6473597d706e 3280 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
bogdanm 82:6473597d706e 3281 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
bogdanm 82:6473597d706e 3282 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
bogdanm 82:6473597d706e 3283 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
bogdanm 82:6473597d706e 3284 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
bogdanm 82:6473597d706e 3285 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
bogdanm 82:6473597d706e 3286 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
bogdanm 82:6473597d706e 3287
bogdanm 82:6473597d706e 3288 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
bogdanm 82:6473597d706e 3289 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
bogdanm 82:6473597d706e 3290 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
bogdanm 82:6473597d706e 3291 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
bogdanm 82:6473597d706e 3292 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
bogdanm 82:6473597d706e 3293 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
bogdanm 82:6473597d706e 3294 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
bogdanm 82:6473597d706e 3295 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
bogdanm 82:6473597d706e 3296 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
bogdanm 82:6473597d706e 3297 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
bogdanm 82:6473597d706e 3298 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
bogdanm 82:6473597d706e 3299 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
bogdanm 82:6473597d706e 3300 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
bogdanm 82:6473597d706e 3301 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
bogdanm 82:6473597d706e 3302 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
bogdanm 82:6473597d706e 3303 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
bogdanm 82:6473597d706e 3304 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
bogdanm 82:6473597d706e 3305
bogdanm 82:6473597d706e 3306 /******************** Bit definition for ADC_CDR register ********************/
bogdanm 82:6473597d706e 3307 #define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
bogdanm 82:6473597d706e 3308 #define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
bogdanm 82:6473597d706e 3309 #define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
bogdanm 82:6473597d706e 3310 #define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
bogdanm 82:6473597d706e 3311 #define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
bogdanm 82:6473597d706e 3312 #define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
bogdanm 82:6473597d706e 3313 #define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
bogdanm 82:6473597d706e 3314 #define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
bogdanm 82:6473597d706e 3315 #define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
bogdanm 82:6473597d706e 3316 #define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
bogdanm 82:6473597d706e 3317 #define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
bogdanm 82:6473597d706e 3318 #define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
bogdanm 82:6473597d706e 3319 #define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
bogdanm 82:6473597d706e 3320 #define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
bogdanm 82:6473597d706e 3321 #define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
bogdanm 82:6473597d706e 3322 #define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
bogdanm 82:6473597d706e 3323 #define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
bogdanm 82:6473597d706e 3324
bogdanm 82:6473597d706e 3325 #define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
bogdanm 82:6473597d706e 3326 #define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
bogdanm 82:6473597d706e 3327 #define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
bogdanm 82:6473597d706e 3328 #define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
bogdanm 82:6473597d706e 3329 #define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
bogdanm 82:6473597d706e 3330 #define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
bogdanm 82:6473597d706e 3331 #define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
bogdanm 82:6473597d706e 3332 #define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
bogdanm 82:6473597d706e 3333 #define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
bogdanm 82:6473597d706e 3334 #define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
bogdanm 82:6473597d706e 3335 #define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
bogdanm 82:6473597d706e 3336 #define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
bogdanm 82:6473597d706e 3337 #define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
bogdanm 82:6473597d706e 3338 #define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
bogdanm 82:6473597d706e 3339 #define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
bogdanm 82:6473597d706e 3340 #define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
bogdanm 82:6473597d706e 3341 #define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
bogdanm 82:6473597d706e 3342
bogdanm 82:6473597d706e 3343 /******************************************************************************/
bogdanm 82:6473597d706e 3344 /* */
bogdanm 82:6473597d706e 3345 /* Analog Comparators (COMP) */
bogdanm 82:6473597d706e 3346 /* */
bogdanm 82:6473597d706e 3347 /******************************************************************************/
bogdanm 82:6473597d706e 3348 /********************** Bit definition for COMP1_CSR register ***************/
bogdanm 82:6473597d706e 3349 #define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
bogdanm 82:6473597d706e 3350 #define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
bogdanm 82:6473597d706e 3351 #define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
bogdanm 82:6473597d706e 3352 #define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
bogdanm 82:6473597d706e 3353 #define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
bogdanm 82:6473597d706e 3354 #define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
bogdanm 82:6473597d706e 3355 #define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
bogdanm 82:6473597d706e 3356 #define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
bogdanm 82:6473597d706e 3357 #define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
bogdanm 82:6473597d706e 3358 #define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */
bogdanm 82:6473597d706e 3359 #define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
bogdanm 82:6473597d706e 3360 #define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
bogdanm 82:6473597d706e 3361 #define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
bogdanm 82:6473597d706e 3362 #define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
bogdanm 82:6473597d706e 3363 #define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
bogdanm 82:6473597d706e 3364 #define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
bogdanm 82:6473597d706e 3365 #define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /*!< COMP1 hysteresis */
bogdanm 82:6473597d706e 3366 #define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */
bogdanm 82:6473597d706e 3367 #define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */
bogdanm 82:6473597d706e 3368 #define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
bogdanm 82:6473597d706e 3369 #define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
bogdanm 82:6473597d706e 3370 #define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
bogdanm 82:6473597d706e 3371 #define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
bogdanm 82:6473597d706e 3372 #define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
bogdanm 82:6473597d706e 3373 #define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
bogdanm 82:6473597d706e 3374
bogdanm 82:6473597d706e 3375 /********************** Bit definition for COMP2_CSR register ***************/
bogdanm 82:6473597d706e 3376 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
bogdanm 82:6473597d706e 3377 #define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /*!< COMP2 power mode */
bogdanm 82:6473597d706e 3378 #define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */
bogdanm 82:6473597d706e 3379 #define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */
bogdanm 82:6473597d706e 3380 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /*!< COMP2 inverting input select */
bogdanm 82:6473597d706e 3381 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
bogdanm 82:6473597d706e 3382 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
bogdanm 82:6473597d706e 3383 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
bogdanm 82:6473597d706e 3384 #define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */
bogdanm 82:6473597d706e 3385 #define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /*!< COMP2 window mode enable */
bogdanm 82:6473597d706e 3386 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
bogdanm 82:6473597d706e 3387 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
bogdanm 82:6473597d706e 3388 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
bogdanm 82:6473597d706e 3389 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
bogdanm 82:6473597d706e 3390 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
bogdanm 82:6473597d706e 3391 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
bogdanm 82:6473597d706e 3392 #define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /*!< COMP2 hysteresis */
bogdanm 82:6473597d706e 3393 #define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */
bogdanm 82:6473597d706e 3394 #define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */
bogdanm 82:6473597d706e 3395 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
bogdanm 82:6473597d706e 3396 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
bogdanm 82:6473597d706e 3397 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
bogdanm 82:6473597d706e 3398 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
bogdanm 82:6473597d706e 3399 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
bogdanm 82:6473597d706e 3400 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
bogdanm 82:6473597d706e 3401
bogdanm 82:6473597d706e 3402 /********************** Bit definition for COMP3_CSR register ***************/
bogdanm 82:6473597d706e 3403 #define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
bogdanm 82:6473597d706e 3404 #define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /*!< COMP3 power mode */
bogdanm 82:6473597d706e 3405 #define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */
bogdanm 82:6473597d706e 3406 #define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */
bogdanm 82:6473597d706e 3407 #define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
bogdanm 82:6473597d706e 3408 #define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
bogdanm 82:6473597d706e 3409 #define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
bogdanm 82:6473597d706e 3410 #define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
bogdanm 82:6473597d706e 3411 #define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */
bogdanm 82:6473597d706e 3412 #define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
bogdanm 82:6473597d706e 3413 #define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
bogdanm 82:6473597d706e 3414 #define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
bogdanm 82:6473597d706e 3415 #define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
bogdanm 82:6473597d706e 3416 #define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
bogdanm 82:6473597d706e 3417 #define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
bogdanm 82:6473597d706e 3418 #define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /*!< COMP3 hysteresis */
bogdanm 82:6473597d706e 3419 #define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */
bogdanm 82:6473597d706e 3420 #define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */
bogdanm 82:6473597d706e 3421 #define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
bogdanm 82:6473597d706e 3422 #define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
bogdanm 82:6473597d706e 3423 #define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
bogdanm 82:6473597d706e 3424 #define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
bogdanm 82:6473597d706e 3425 #define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
bogdanm 82:6473597d706e 3426 #define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
bogdanm 82:6473597d706e 3427
bogdanm 82:6473597d706e 3428 /********************** Bit definition for COMP4_CSR register ***************/
bogdanm 82:6473597d706e 3429 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
bogdanm 82:6473597d706e 3430 #define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /*!< COMP4 power mode */
bogdanm 82:6473597d706e 3431 #define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */
bogdanm 82:6473597d706e 3432 #define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */
bogdanm 82:6473597d706e 3433 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /*!< COMP4 inverting input select */
bogdanm 82:6473597d706e 3434 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
bogdanm 82:6473597d706e 3435 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
bogdanm 82:6473597d706e 3436 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
bogdanm 82:6473597d706e 3437 #define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */
bogdanm 82:6473597d706e 3438 #define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /*!< COMP4 window mode enable */
bogdanm 82:6473597d706e 3439 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
bogdanm 82:6473597d706e 3440 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
bogdanm 82:6473597d706e 3441 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
bogdanm 82:6473597d706e 3442 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
bogdanm 82:6473597d706e 3443 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
bogdanm 82:6473597d706e 3444 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
bogdanm 82:6473597d706e 3445 #define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /*!< COMP4 hysteresis */
bogdanm 82:6473597d706e 3446 #define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */
bogdanm 82:6473597d706e 3447 #define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */
bogdanm 82:6473597d706e 3448 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
bogdanm 82:6473597d706e 3449 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
bogdanm 82:6473597d706e 3450 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
bogdanm 82:6473597d706e 3451 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
bogdanm 82:6473597d706e 3452 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
bogdanm 82:6473597d706e 3453 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
bogdanm 82:6473597d706e 3454
bogdanm 82:6473597d706e 3455 /********************** Bit definition for COMP5_CSR register ***************/
bogdanm 82:6473597d706e 3456 #define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
bogdanm 82:6473597d706e 3457 #define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /*!< COMP5 power mode */
bogdanm 82:6473597d706e 3458 #define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */
bogdanm 82:6473597d706e 3459 #define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */
bogdanm 82:6473597d706e 3460 #define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
bogdanm 82:6473597d706e 3461 #define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
bogdanm 82:6473597d706e 3462 #define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
bogdanm 82:6473597d706e 3463 #define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
bogdanm 82:6473597d706e 3464 #define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */
bogdanm 82:6473597d706e 3465 #define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
bogdanm 82:6473597d706e 3466 #define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
bogdanm 82:6473597d706e 3467 #define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
bogdanm 82:6473597d706e 3468 #define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
bogdanm 82:6473597d706e 3469 #define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
bogdanm 82:6473597d706e 3470 #define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
bogdanm 82:6473597d706e 3471 #define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /*!< COMP5 hysteresis */
bogdanm 82:6473597d706e 3472 #define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */
bogdanm 82:6473597d706e 3473 #define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */
bogdanm 82:6473597d706e 3474 #define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
bogdanm 82:6473597d706e 3475 #define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
bogdanm 82:6473597d706e 3476 #define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
bogdanm 82:6473597d706e 3477 #define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
bogdanm 82:6473597d706e 3478 #define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
bogdanm 82:6473597d706e 3479 #define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
bogdanm 82:6473597d706e 3480
bogdanm 82:6473597d706e 3481 /********************** Bit definition for COMP6_CSR register ***************/
bogdanm 82:6473597d706e 3482 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
bogdanm 82:6473597d706e 3483 #define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /*!< COMP6 power mode */
bogdanm 82:6473597d706e 3484 #define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */
bogdanm 82:6473597d706e 3485 #define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */
bogdanm 82:6473597d706e 3486 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /*!< COMP6 inverting input select */
bogdanm 82:6473597d706e 3487 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
bogdanm 82:6473597d706e 3488 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
bogdanm 82:6473597d706e 3489 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
bogdanm 82:6473597d706e 3490 #define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */
bogdanm 82:6473597d706e 3491 #define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /*!< COMP6 window mode enable */
bogdanm 82:6473597d706e 3492 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
bogdanm 82:6473597d706e 3493 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
bogdanm 82:6473597d706e 3494 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
bogdanm 82:6473597d706e 3495 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
bogdanm 82:6473597d706e 3496 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
bogdanm 82:6473597d706e 3497 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
bogdanm 82:6473597d706e 3498 #define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /*!< COMP6 hysteresis */
bogdanm 82:6473597d706e 3499 #define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */
bogdanm 82:6473597d706e 3500 #define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */
bogdanm 82:6473597d706e 3501 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
bogdanm 82:6473597d706e 3502 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
bogdanm 82:6473597d706e 3503 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
bogdanm 82:6473597d706e 3504 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
bogdanm 82:6473597d706e 3505 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
bogdanm 82:6473597d706e 3506 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
bogdanm 82:6473597d706e 3507
bogdanm 82:6473597d706e 3508 /********************** Bit definition for COMP7_CSR register ***************/
bogdanm 82:6473597d706e 3509 #define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
bogdanm 82:6473597d706e 3510 #define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /*!< COMP7 power mode */
bogdanm 82:6473597d706e 3511 #define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */
bogdanm 82:6473597d706e 3512 #define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */
bogdanm 82:6473597d706e 3513 #define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
bogdanm 82:6473597d706e 3514 #define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
bogdanm 82:6473597d706e 3515 #define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
bogdanm 82:6473597d706e 3516 #define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
bogdanm 82:6473597d706e 3517 #define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */
bogdanm 82:6473597d706e 3518 #define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
bogdanm 82:6473597d706e 3519 #define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
bogdanm 82:6473597d706e 3520 #define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
bogdanm 82:6473597d706e 3521 #define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
bogdanm 82:6473597d706e 3522 #define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
bogdanm 82:6473597d706e 3523 #define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
bogdanm 82:6473597d706e 3524 #define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /*!< COMP7 hysteresis */
bogdanm 82:6473597d706e 3525 #define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */
bogdanm 82:6473597d706e 3526 #define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */
bogdanm 82:6473597d706e 3527 #define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
bogdanm 82:6473597d706e 3528 #define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
bogdanm 82:6473597d706e 3529 #define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
bogdanm 82:6473597d706e 3530 #define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
bogdanm 82:6473597d706e 3531 #define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
bogdanm 82:6473597d706e 3532 #define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
bogdanm 82:6473597d706e 3533
bogdanm 82:6473597d706e 3534 /********************** Bit definition for COMP_CSR register ****************/
bogdanm 82:6473597d706e 3535 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
bogdanm 82:6473597d706e 3536 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
bogdanm 82:6473597d706e 3537 #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
bogdanm 82:6473597d706e 3538 #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
bogdanm 82:6473597d706e 3539 #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
bogdanm 82:6473597d706e 3540 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
bogdanm 82:6473597d706e 3541 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
bogdanm 82:6473597d706e 3542 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
bogdanm 82:6473597d706e 3543 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
bogdanm 82:6473597d706e 3544 #define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input select */
bogdanm 82:6473597d706e 3545 #define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */
bogdanm 82:6473597d706e 3546 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
bogdanm 82:6473597d706e 3547 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
bogdanm 82:6473597d706e 3548 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
bogdanm 82:6473597d706e 3549 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
bogdanm 82:6473597d706e 3550 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
bogdanm 82:6473597d706e 3551 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
bogdanm 82:6473597d706e 3552 #define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */
bogdanm 82:6473597d706e 3553 #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */
bogdanm 82:6473597d706e 3554 #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */
bogdanm 82:6473597d706e 3555 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
bogdanm 82:6473597d706e 3556 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
bogdanm 82:6473597d706e 3557 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
bogdanm 82:6473597d706e 3558 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
bogdanm 82:6473597d706e 3559 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
bogdanm 82:6473597d706e 3560 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
bogdanm 82:6473597d706e 3561 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
bogdanm 82:6473597d706e 3562
bogdanm 82:6473597d706e 3563 /******************************************************************************/
bogdanm 82:6473597d706e 3564 /* */
bogdanm 82:6473597d706e 3565 /* Operational Amplifier (OPAMP) */
bogdanm 82:6473597d706e 3566 /* */
bogdanm 82:6473597d706e 3567 /******************************************************************************/
bogdanm 82:6473597d706e 3568 /********************* Bit definition for OPAMP1_CSR register ***************/
bogdanm 82:6473597d706e 3569 #define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
bogdanm 82:6473597d706e 3570 #define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
bogdanm 82:6473597d706e 3571 #define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
bogdanm 82:6473597d706e 3572 #define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 82:6473597d706e 3573 #define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 82:6473597d706e 3574 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
bogdanm 82:6473597d706e 3575 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 82:6473597d706e 3576 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 82:6473597d706e 3577 #define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
bogdanm 82:6473597d706e 3578 #define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
bogdanm 82:6473597d706e 3579 #define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
bogdanm 82:6473597d706e 3580 #define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 82:6473597d706e 3581 #define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 82:6473597d706e 3582 #define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
bogdanm 82:6473597d706e 3583 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
bogdanm 82:6473597d706e 3584 #define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3585 #define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3586 #define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
bogdanm 82:6473597d706e 3587 #define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3588 #define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3589 #define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
bogdanm 82:6473597d706e 3590 #define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
bogdanm 82:6473597d706e 3591 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
bogdanm 82:6473597d706e 3592 #define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
bogdanm 82:6473597d706e 3593 #define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
bogdanm 82:6473597d706e 3594 #define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
bogdanm 82:6473597d706e 3595 #define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
bogdanm 82:6473597d706e 3596 #define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
bogdanm 82:6473597d706e 3597
bogdanm 82:6473597d706e 3598 /********************* Bit definition for OPAMP2_CSR register ***************/
bogdanm 82:6473597d706e 3599 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
bogdanm 82:6473597d706e 3600 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
bogdanm 82:6473597d706e 3601 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
bogdanm 82:6473597d706e 3602 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 82:6473597d706e 3603 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 82:6473597d706e 3604 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
bogdanm 82:6473597d706e 3605 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 82:6473597d706e 3606 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 82:6473597d706e 3607 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
bogdanm 82:6473597d706e 3608 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
bogdanm 82:6473597d706e 3609 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
bogdanm 82:6473597d706e 3610 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 82:6473597d706e 3611 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 82:6473597d706e 3612 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
bogdanm 82:6473597d706e 3613 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
bogdanm 82:6473597d706e 3614 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3615 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3616 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
bogdanm 82:6473597d706e 3617 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3618 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3619 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
bogdanm 82:6473597d706e 3620 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
bogdanm 82:6473597d706e 3621 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
bogdanm 82:6473597d706e 3622 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
bogdanm 82:6473597d706e 3623 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
bogdanm 82:6473597d706e 3624 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
bogdanm 82:6473597d706e 3625 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
bogdanm 82:6473597d706e 3626 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
bogdanm 82:6473597d706e 3627
bogdanm 82:6473597d706e 3628 /********************* Bit definition for OPAMP3_CSR register ***************/
bogdanm 82:6473597d706e 3629 #define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
bogdanm 82:6473597d706e 3630 #define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
bogdanm 82:6473597d706e 3631 #define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
bogdanm 82:6473597d706e 3632 #define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 82:6473597d706e 3633 #define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 82:6473597d706e 3634 #define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
bogdanm 82:6473597d706e 3635 #define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 82:6473597d706e 3636 #define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 82:6473597d706e 3637 #define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
bogdanm 82:6473597d706e 3638 #define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
bogdanm 82:6473597d706e 3639 #define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
bogdanm 82:6473597d706e 3640 #define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 82:6473597d706e 3641 #define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 82:6473597d706e 3642 #define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
bogdanm 82:6473597d706e 3643 #define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
bogdanm 82:6473597d706e 3644 #define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3645 #define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3646 #define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
bogdanm 82:6473597d706e 3647 #define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3648 #define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3649 #define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
bogdanm 82:6473597d706e 3650 #define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
bogdanm 82:6473597d706e 3651 #define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
bogdanm 82:6473597d706e 3652 #define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
bogdanm 82:6473597d706e 3653 #define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
bogdanm 82:6473597d706e 3654 #define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
bogdanm 82:6473597d706e 3655 #define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
bogdanm 82:6473597d706e 3656 #define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
bogdanm 82:6473597d706e 3657
bogdanm 82:6473597d706e 3658 /********************* Bit definition for OPAMP4_CSR register ***************/
bogdanm 82:6473597d706e 3659 #define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
bogdanm 82:6473597d706e 3660 #define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
bogdanm 82:6473597d706e 3661 #define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
bogdanm 82:6473597d706e 3662 #define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 82:6473597d706e 3663 #define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 82:6473597d706e 3664 #define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
bogdanm 82:6473597d706e 3665 #define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 82:6473597d706e 3666 #define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 82:6473597d706e 3667 #define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
bogdanm 82:6473597d706e 3668 #define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
bogdanm 82:6473597d706e 3669 #define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
bogdanm 82:6473597d706e 3670 #define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 82:6473597d706e 3671 #define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 82:6473597d706e 3672 #define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
bogdanm 82:6473597d706e 3673 #define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
bogdanm 82:6473597d706e 3674 #define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3675 #define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3676 #define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
bogdanm 82:6473597d706e 3677 #define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3678 #define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3679 #define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
bogdanm 82:6473597d706e 3680 #define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
bogdanm 82:6473597d706e 3681 #define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
bogdanm 82:6473597d706e 3682 #define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
bogdanm 82:6473597d706e 3683 #define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
bogdanm 82:6473597d706e 3684 #define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
bogdanm 82:6473597d706e 3685 #define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
bogdanm 82:6473597d706e 3686 #define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
bogdanm 82:6473597d706e 3687
bogdanm 82:6473597d706e 3688 /********************* Bit definition for OPAMPx_CSR register ***************/
bogdanm 82:6473597d706e 3689 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
bogdanm 82:6473597d706e 3690 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
bogdanm 82:6473597d706e 3691 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
bogdanm 82:6473597d706e 3692 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 82:6473597d706e 3693 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 82:6473597d706e 3694 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
bogdanm 82:6473597d706e 3695 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 82:6473597d706e 3696 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 82:6473597d706e 3697 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
bogdanm 82:6473597d706e 3698 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
bogdanm 82:6473597d706e 3699 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
bogdanm 82:6473597d706e 3700 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 82:6473597d706e 3701 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 82:6473597d706e 3702 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
bogdanm 82:6473597d706e 3703 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
bogdanm 82:6473597d706e 3704 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3705 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3706 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
bogdanm 82:6473597d706e 3707 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 82:6473597d706e 3708 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 82:6473597d706e 3709 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
bogdanm 82:6473597d706e 3710 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
bogdanm 82:6473597d706e 3711 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
bogdanm 82:6473597d706e 3712 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
bogdanm 82:6473597d706e 3713 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
bogdanm 82:6473597d706e 3714 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
bogdanm 82:6473597d706e 3715 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
bogdanm 82:6473597d706e 3716 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
bogdanm 82:6473597d706e 3717
bogdanm 82:6473597d706e 3718
bogdanm 82:6473597d706e 3719 /******************************************************************************/
bogdanm 82:6473597d706e 3720 /* */
bogdanm 82:6473597d706e 3721 /* Controller Area Network (CAN ) */
bogdanm 82:6473597d706e 3722 /* */
bogdanm 82:6473597d706e 3723 /******************************************************************************/
bogdanm 82:6473597d706e 3724 /*!<CAN control and status registers */
bogdanm 82:6473597d706e 3725 /******************* Bit definition for CAN_MCR register ********************/
bogdanm 82:6473597d706e 3726 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
bogdanm 82:6473597d706e 3727 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
bogdanm 82:6473597d706e 3728 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
bogdanm 82:6473597d706e 3729 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
bogdanm 82:6473597d706e 3730 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
bogdanm 82:6473597d706e 3731 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
bogdanm 82:6473597d706e 3732 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
bogdanm 82:6473597d706e 3733 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
bogdanm 82:6473597d706e 3734 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
bogdanm 82:6473597d706e 3735
bogdanm 82:6473597d706e 3736 /******************* Bit definition for CAN_MSR register ********************/
bogdanm 82:6473597d706e 3737 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
bogdanm 82:6473597d706e 3738 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
bogdanm 82:6473597d706e 3739 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
bogdanm 82:6473597d706e 3740 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
bogdanm 82:6473597d706e 3741 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
bogdanm 82:6473597d706e 3742 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
bogdanm 82:6473597d706e 3743 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
bogdanm 82:6473597d706e 3744 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
bogdanm 82:6473597d706e 3745 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
bogdanm 82:6473597d706e 3746
bogdanm 82:6473597d706e 3747 /******************* Bit definition for CAN_TSR register ********************/
bogdanm 82:6473597d706e 3748 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
bogdanm 82:6473597d706e 3749 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
bogdanm 82:6473597d706e 3750 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
bogdanm 82:6473597d706e 3751 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
bogdanm 82:6473597d706e 3752 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
bogdanm 82:6473597d706e 3753 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
bogdanm 82:6473597d706e 3754 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
bogdanm 82:6473597d706e 3755 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
bogdanm 82:6473597d706e 3756 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
bogdanm 82:6473597d706e 3757 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
bogdanm 82:6473597d706e 3758 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
bogdanm 82:6473597d706e 3759 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
bogdanm 82:6473597d706e 3760 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
bogdanm 82:6473597d706e 3761 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
bogdanm 82:6473597d706e 3762 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
bogdanm 82:6473597d706e 3763 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
bogdanm 82:6473597d706e 3764
bogdanm 82:6473597d706e 3765 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
bogdanm 82:6473597d706e 3766 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
bogdanm 82:6473597d706e 3767 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
bogdanm 82:6473597d706e 3768 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
bogdanm 82:6473597d706e 3769
bogdanm 82:6473597d706e 3770 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
bogdanm 82:6473597d706e 3771 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
bogdanm 82:6473597d706e 3772 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
bogdanm 82:6473597d706e 3773 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
bogdanm 82:6473597d706e 3774
bogdanm 82:6473597d706e 3775 /******************* Bit definition for CAN_RF0R register *******************/
bogdanm 82:6473597d706e 3776 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
bogdanm 82:6473597d706e 3777 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
bogdanm 82:6473597d706e 3778 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
bogdanm 82:6473597d706e 3779 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
bogdanm 82:6473597d706e 3780
bogdanm 82:6473597d706e 3781 /******************* Bit definition for CAN_RF1R register *******************/
bogdanm 82:6473597d706e 3782 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
bogdanm 82:6473597d706e 3783 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
bogdanm 82:6473597d706e 3784 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
bogdanm 82:6473597d706e 3785 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
bogdanm 82:6473597d706e 3786
bogdanm 82:6473597d706e 3787 /******************** Bit definition for CAN_IER register *******************/
bogdanm 82:6473597d706e 3788 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
bogdanm 82:6473597d706e 3789 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 82:6473597d706e 3790 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
bogdanm 82:6473597d706e 3791 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
bogdanm 82:6473597d706e 3792 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 82:6473597d706e 3793 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
bogdanm 82:6473597d706e 3794 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
bogdanm 82:6473597d706e 3795 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
bogdanm 82:6473597d706e 3796 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
bogdanm 82:6473597d706e 3797 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
bogdanm 82:6473597d706e 3798 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
bogdanm 82:6473597d706e 3799 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
bogdanm 82:6473597d706e 3800 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
bogdanm 82:6473597d706e 3801 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
bogdanm 82:6473597d706e 3802
bogdanm 82:6473597d706e 3803 /******************** Bit definition for CAN_ESR register *******************/
bogdanm 82:6473597d706e 3804 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
bogdanm 82:6473597d706e 3805 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
bogdanm 82:6473597d706e 3806 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
bogdanm 82:6473597d706e 3807
bogdanm 82:6473597d706e 3808 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
bogdanm 82:6473597d706e 3809 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 82:6473597d706e 3810 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 82:6473597d706e 3811 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 82:6473597d706e 3812
bogdanm 82:6473597d706e 3813 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
bogdanm 82:6473597d706e 3814 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
bogdanm 82:6473597d706e 3815
bogdanm 82:6473597d706e 3816 /******************* Bit definition for CAN_BTR register ********************/
bogdanm 82:6473597d706e 3817 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
bogdanm 82:6473597d706e 3818 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
bogdanm 82:6473597d706e 3819 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
bogdanm 82:6473597d706e 3820 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
bogdanm 82:6473597d706e 3821 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
bogdanm 82:6473597d706e 3822 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
bogdanm 82:6473597d706e 3823
bogdanm 82:6473597d706e 3824 /*!<Mailbox registers */
bogdanm 82:6473597d706e 3825 /****************** Bit definition for CAN_TI0R register ********************/
bogdanm 82:6473597d706e 3826 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 82:6473597d706e 3827 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 82:6473597d706e 3828 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 82:6473597d706e 3829 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 82:6473597d706e 3830 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 82:6473597d706e 3831
bogdanm 82:6473597d706e 3832 /****************** Bit definition for CAN_TDT0R register *******************/
bogdanm 82:6473597d706e 3833 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 82:6473597d706e 3834 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 82:6473597d706e 3835 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 82:6473597d706e 3836
bogdanm 82:6473597d706e 3837 /****************** Bit definition for CAN_TDL0R register *******************/
bogdanm 82:6473597d706e 3838 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 82:6473597d706e 3839 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 82:6473597d706e 3840 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 82:6473597d706e 3841 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 82:6473597d706e 3842
bogdanm 82:6473597d706e 3843 /****************** Bit definition for CAN_TDH0R register *******************/
bogdanm 82:6473597d706e 3844 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 82:6473597d706e 3845 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 82:6473597d706e 3846 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 82:6473597d706e 3847 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 82:6473597d706e 3848
bogdanm 82:6473597d706e 3849 /******************* Bit definition for CAN_TI1R register *******************/
bogdanm 82:6473597d706e 3850 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 82:6473597d706e 3851 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 82:6473597d706e 3852 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 82:6473597d706e 3853 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 82:6473597d706e 3854 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 82:6473597d706e 3855
bogdanm 82:6473597d706e 3856 /******************* Bit definition for CAN_TDT1R register ******************/
bogdanm 82:6473597d706e 3857 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 82:6473597d706e 3858 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 82:6473597d706e 3859 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 82:6473597d706e 3860
bogdanm 82:6473597d706e 3861 /******************* Bit definition for CAN_TDL1R register ******************/
bogdanm 82:6473597d706e 3862 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 82:6473597d706e 3863 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 82:6473597d706e 3864 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 82:6473597d706e 3865 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 82:6473597d706e 3866
bogdanm 82:6473597d706e 3867 /******************* Bit definition for CAN_TDH1R register ******************/
bogdanm 82:6473597d706e 3868 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 82:6473597d706e 3869 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 82:6473597d706e 3870 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 82:6473597d706e 3871 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 82:6473597d706e 3872
bogdanm 82:6473597d706e 3873 /******************* Bit definition for CAN_TI2R register *******************/
bogdanm 82:6473597d706e 3874 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 82:6473597d706e 3875 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 82:6473597d706e 3876 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 82:6473597d706e 3877 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 82:6473597d706e 3878 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 82:6473597d706e 3879
bogdanm 82:6473597d706e 3880 /******************* Bit definition for CAN_TDT2R register ******************/
bogdanm 82:6473597d706e 3881 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 82:6473597d706e 3882 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 82:6473597d706e 3883 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 82:6473597d706e 3884
bogdanm 82:6473597d706e 3885 /******************* Bit definition for CAN_TDL2R register ******************/
bogdanm 82:6473597d706e 3886 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 82:6473597d706e 3887 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 82:6473597d706e 3888 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 82:6473597d706e 3889 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 82:6473597d706e 3890
bogdanm 82:6473597d706e 3891 /******************* Bit definition for CAN_TDH2R register ******************/
bogdanm 82:6473597d706e 3892 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 82:6473597d706e 3893 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 82:6473597d706e 3894 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 82:6473597d706e 3895 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 82:6473597d706e 3896
bogdanm 82:6473597d706e 3897 /******************* Bit definition for CAN_RI0R register *******************/
bogdanm 82:6473597d706e 3898 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 82:6473597d706e 3899 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 82:6473597d706e 3900 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 82:6473597d706e 3901 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 82:6473597d706e 3902
bogdanm 82:6473597d706e 3903 /******************* Bit definition for CAN_RDT0R register ******************/
bogdanm 82:6473597d706e 3904 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 82:6473597d706e 3905 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 82:6473597d706e 3906 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 82:6473597d706e 3907
bogdanm 82:6473597d706e 3908 /******************* Bit definition for CAN_RDL0R register ******************/
bogdanm 82:6473597d706e 3909 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 82:6473597d706e 3910 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 82:6473597d706e 3911 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 82:6473597d706e 3912 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 82:6473597d706e 3913
bogdanm 82:6473597d706e 3914 /******************* Bit definition for CAN_RDH0R register ******************/
bogdanm 82:6473597d706e 3915 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 82:6473597d706e 3916 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 82:6473597d706e 3917 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 82:6473597d706e 3918 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 82:6473597d706e 3919
bogdanm 82:6473597d706e 3920 /******************* Bit definition for CAN_RI1R register *******************/
bogdanm 82:6473597d706e 3921 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 82:6473597d706e 3922 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 82:6473597d706e 3923 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 82:6473597d706e 3924 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 82:6473597d706e 3925
bogdanm 82:6473597d706e 3926 /******************* Bit definition for CAN_RDT1R register ******************/
bogdanm 82:6473597d706e 3927 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 82:6473597d706e 3928 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 82:6473597d706e 3929 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 82:6473597d706e 3930
bogdanm 82:6473597d706e 3931 /******************* Bit definition for CAN_RDL1R register ******************/
bogdanm 82:6473597d706e 3932 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 82:6473597d706e 3933 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 82:6473597d706e 3934 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 82:6473597d706e 3935 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 82:6473597d706e 3936
bogdanm 82:6473597d706e 3937 /******************* Bit definition for CAN_RDH1R register ******************/
bogdanm 82:6473597d706e 3938 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 82:6473597d706e 3939 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 82:6473597d706e 3940 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 82:6473597d706e 3941 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 82:6473597d706e 3942
bogdanm 82:6473597d706e 3943 /*!<CAN filter registers */
bogdanm 82:6473597d706e 3944 /******************* Bit definition for CAN_FMR register ********************/
bogdanm 82:6473597d706e 3945 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
bogdanm 82:6473597d706e 3946
bogdanm 82:6473597d706e 3947 /******************* Bit definition for CAN_FM1R register *******************/
bogdanm 82:6473597d706e 3948 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
bogdanm 82:6473597d706e 3949 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
bogdanm 82:6473597d706e 3950 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
bogdanm 82:6473597d706e 3951 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
bogdanm 82:6473597d706e 3952 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
bogdanm 82:6473597d706e 3953 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
bogdanm 82:6473597d706e 3954 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
bogdanm 82:6473597d706e 3955 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
bogdanm 82:6473597d706e 3956 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
bogdanm 82:6473597d706e 3957 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
bogdanm 82:6473597d706e 3958 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
bogdanm 82:6473597d706e 3959 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
bogdanm 82:6473597d706e 3960 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
bogdanm 82:6473597d706e 3961 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
bogdanm 82:6473597d706e 3962 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
bogdanm 82:6473597d706e 3963
bogdanm 82:6473597d706e 3964 /******************* Bit definition for CAN_FS1R register *******************/
bogdanm 82:6473597d706e 3965 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
bogdanm 82:6473597d706e 3966 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
bogdanm 82:6473597d706e 3967 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
bogdanm 82:6473597d706e 3968 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
bogdanm 82:6473597d706e 3969 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
bogdanm 82:6473597d706e 3970 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
bogdanm 82:6473597d706e 3971 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
bogdanm 82:6473597d706e 3972 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
bogdanm 82:6473597d706e 3973 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
bogdanm 82:6473597d706e 3974 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
bogdanm 82:6473597d706e 3975 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
bogdanm 82:6473597d706e 3976 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
bogdanm 82:6473597d706e 3977 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
bogdanm 82:6473597d706e 3978 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
bogdanm 82:6473597d706e 3979 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
bogdanm 82:6473597d706e 3980
bogdanm 82:6473597d706e 3981 /****************** Bit definition for CAN_FFA1R register *******************/
bogdanm 82:6473597d706e 3982 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
bogdanm 82:6473597d706e 3983 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
bogdanm 82:6473597d706e 3984 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
bogdanm 82:6473597d706e 3985 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
bogdanm 82:6473597d706e 3986 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
bogdanm 82:6473597d706e 3987 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
bogdanm 82:6473597d706e 3988 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
bogdanm 82:6473597d706e 3989 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
bogdanm 82:6473597d706e 3990 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
bogdanm 82:6473597d706e 3991 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
bogdanm 82:6473597d706e 3992 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
bogdanm 82:6473597d706e 3993 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
bogdanm 82:6473597d706e 3994 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
bogdanm 82:6473597d706e 3995 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
bogdanm 82:6473597d706e 3996 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
bogdanm 82:6473597d706e 3997
bogdanm 82:6473597d706e 3998 /******************* Bit definition for CAN_FA1R register *******************/
bogdanm 82:6473597d706e 3999 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
bogdanm 82:6473597d706e 4000 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
bogdanm 82:6473597d706e 4001 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
bogdanm 82:6473597d706e 4002 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
bogdanm 82:6473597d706e 4003 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
bogdanm 82:6473597d706e 4004 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
bogdanm 82:6473597d706e 4005 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
bogdanm 82:6473597d706e 4006 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
bogdanm 82:6473597d706e 4007 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
bogdanm 82:6473597d706e 4008 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
bogdanm 82:6473597d706e 4009 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
bogdanm 82:6473597d706e 4010 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
bogdanm 82:6473597d706e 4011 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
bogdanm 82:6473597d706e 4012 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
bogdanm 82:6473597d706e 4013 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
bogdanm 82:6473597d706e 4014
bogdanm 82:6473597d706e 4015 /******************* Bit definition for CAN_F0R1 register *******************/
bogdanm 82:6473597d706e 4016 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4017 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4018 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4019 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4020 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4021 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4022 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4023 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4024 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4025 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4026 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4027 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4028 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4029 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4030 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4031 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4032 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4033 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4034 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4035 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4036 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4037 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4038 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4039 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4040 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4041 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4042 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4043 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4044 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4045 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4046 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4047 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4048
bogdanm 82:6473597d706e 4049 /******************* Bit definition for CAN_F1R1 register *******************/
bogdanm 82:6473597d706e 4050 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4051 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4052 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4053 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4054 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4055 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4056 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4057 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4058 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4059 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4060 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4061 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4062 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4063 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4064 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4065 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4066 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4067 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4068 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4069 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4070 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4071 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4072 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4073 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4074 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4075 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4076 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4077 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4078 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4079 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4080 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4081 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4082
bogdanm 82:6473597d706e 4083 /******************* Bit definition for CAN_F2R1 register *******************/
bogdanm 82:6473597d706e 4084 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4085 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4086 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4087 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4088 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4089 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4090 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4091 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4092 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4093 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4094 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4095 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4096 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4097 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4098 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4099 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4100 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4101 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4102 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4103 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4104 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4105 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4106 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4107 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4108 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4109 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4110 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4111 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4112 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4113 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4114 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4115 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4116
bogdanm 82:6473597d706e 4117 /******************* Bit definition for CAN_F3R1 register *******************/
bogdanm 82:6473597d706e 4118 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4119 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4120 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4121 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4122 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4123 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4124 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4125 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4126 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4127 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4128 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4129 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4130 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4131 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4132 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4133 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4134 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4135 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4136 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4137 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4138 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4139 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4140 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4141 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4142 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4143 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4144 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4145 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4146 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4147 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4148 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4149 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4150
bogdanm 82:6473597d706e 4151 /******************* Bit definition for CAN_F4R1 register *******************/
bogdanm 82:6473597d706e 4152 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4153 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4154 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4155 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4156 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4157 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4158 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4159 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4160 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4161 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4162 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4163 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4164 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4165 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4166 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4167 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4168 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4169 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4170 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4171 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4172 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4173 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4174 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4175 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4176 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4177 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4178 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4179 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4180 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4181 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4182 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4183 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4184
bogdanm 82:6473597d706e 4185 /******************* Bit definition for CAN_F5R1 register *******************/
bogdanm 82:6473597d706e 4186 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4187 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4188 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4189 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4190 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4191 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4192 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4193 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4194 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4195 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4196 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4197 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4198 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4199 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4200 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4201 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4202 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4203 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4204 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4205 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4206 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4207 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4208 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4209 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4210 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4211 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4212 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4213 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4214 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4215 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4216 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4217 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4218
bogdanm 82:6473597d706e 4219 /******************* Bit definition for CAN_F6R1 register *******************/
bogdanm 82:6473597d706e 4220 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4221 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4222 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4223 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4224 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4225 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4226 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4227 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4228 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4229 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4230 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4231 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4232 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4233 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4234 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4235 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4236 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4237 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4238 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4239 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4240 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4241 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4242 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4243 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4244 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4245 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4246 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4247 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4248 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4249 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4250 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4251 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4252
bogdanm 82:6473597d706e 4253 /******************* Bit definition for CAN_F7R1 register *******************/
bogdanm 82:6473597d706e 4254 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4255 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4256 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4257 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4258 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4259 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4260 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4261 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4262 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4263 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4264 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4265 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4266 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4267 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4268 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4269 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4270 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4271 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4272 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4273 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4274 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4275 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4276 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4277 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4278 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4279 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4280 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4281 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4282 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4283 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4284 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4285 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4286
bogdanm 82:6473597d706e 4287 /******************* Bit definition for CAN_F8R1 register *******************/
bogdanm 82:6473597d706e 4288 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4289 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4290 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4291 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4292 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4293 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4294 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4295 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4296 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4297 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4298 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4299 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4300 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4301 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4302 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4303 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4304 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4305 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4306 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4307 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4308 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4309 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4310 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4311 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4312 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4313 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4314 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4315 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4316 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4317 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4318 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4319 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4320
bogdanm 82:6473597d706e 4321 /******************* Bit definition for CAN_F9R1 register *******************/
bogdanm 82:6473597d706e 4322 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4323 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4324 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4325 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4326 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4327 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4328 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4329 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4330 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4331 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4332 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4333 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4334 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4335 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4336 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4337 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4338 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4339 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4340 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4341 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4342 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4343 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4344 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4345 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4346 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4347 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4348 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4349 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4350 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4351 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4352 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4353 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4354
bogdanm 82:6473597d706e 4355 /******************* Bit definition for CAN_F10R1 register ******************/
bogdanm 82:6473597d706e 4356 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4357 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4358 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4359 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4360 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4361 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4362 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4363 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4364 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4365 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4366 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4367 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4368 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4369 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4370 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4371 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4372 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4373 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4374 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4375 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4376 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4377 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4378 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4379 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4380 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4381 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4382 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4383 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4384 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4385 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4386 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4387 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4388
bogdanm 82:6473597d706e 4389 /******************* Bit definition for CAN_F11R1 register ******************/
bogdanm 82:6473597d706e 4390 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4391 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4392 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4393 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4394 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4395 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4396 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4397 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4398 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4399 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4400 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4401 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4402 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4403 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4404 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4405 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4406 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4407 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4408 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4409 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4410 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4411 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4412 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4413 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4414 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4415 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4416 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4417 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4418 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4419 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4420 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4421 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4422
bogdanm 82:6473597d706e 4423 /******************* Bit definition for CAN_F12R1 register ******************/
bogdanm 82:6473597d706e 4424 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4425 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4426 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4427 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4428 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4429 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4430 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4431 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4432 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4433 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4434 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4435 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4436 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4437 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4438 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4439 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4440 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4441 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4442 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4443 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4444 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4445 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4446 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4447 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4448 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4449 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4450 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4451 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4452 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4453 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4454 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4455 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4456
bogdanm 82:6473597d706e 4457 /******************* Bit definition for CAN_F13R1 register ******************/
bogdanm 82:6473597d706e 4458 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4459 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4460 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4461 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4462 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4463 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4464 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4465 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4466 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4467 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4468 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4469 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4470 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4471 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4472 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4473 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4474 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4475 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4476 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4477 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4478 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4479 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4480 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4481 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4482 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4483 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4484 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4485 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4486 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4487 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4488 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4489 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4490
bogdanm 82:6473597d706e 4491 /******************* Bit definition for CAN_F0R2 register *******************/
bogdanm 82:6473597d706e 4492 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4493 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4494 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4495 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4496 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4497 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4498 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4499 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4500 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4501 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4502 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4503 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4504 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4505 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4506 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4507 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4508 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4509 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4510 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4511 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4512 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4513 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4514 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4515 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4516 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4517 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4518 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4519 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4520 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4521 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4522 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4523 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4524
bogdanm 82:6473597d706e 4525 /******************* Bit definition for CAN_F1R2 register *******************/
bogdanm 82:6473597d706e 4526 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4527 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4528 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4529 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4530 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4531 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4532 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4533 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4534 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4535 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4536 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4537 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4538 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4539 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4540 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4541 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4542 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4543 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4544 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4545 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4546 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4547 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4548 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4549 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4550 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4551 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4552 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4553 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4554 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4555 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4556 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4557 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4558
bogdanm 82:6473597d706e 4559 /******************* Bit definition for CAN_F2R2 register *******************/
bogdanm 82:6473597d706e 4560 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4561 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4562 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4563 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4564 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4565 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4566 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4567 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4568 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4569 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4570 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4571 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4572 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4573 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4574 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4575 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4576 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4577 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4578 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4579 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4580 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4581 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4582 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4583 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4584 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4585 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4586 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4587 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4588 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4589 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4590 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4591 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4592
bogdanm 82:6473597d706e 4593 /******************* Bit definition for CAN_F3R2 register *******************/
bogdanm 82:6473597d706e 4594 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4595 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4596 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4597 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4598 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4599 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4600 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4601 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4602 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4603 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4604 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4605 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4606 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4607 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4608 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4609 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4610 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4611 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4612 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4613 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4614 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4615 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4616 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4617 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4618 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4619 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4620 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4621 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4622 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4623 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4624 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4625 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4626
bogdanm 82:6473597d706e 4627 /******************* Bit definition for CAN_F4R2 register *******************/
bogdanm 82:6473597d706e 4628 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4629 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4630 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4631 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4632 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4633 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4634 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4635 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4636 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4637 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4638 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4639 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4640 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4641 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4642 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4643 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4644 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4645 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4646 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4647 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4648 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4649 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4650 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4651 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4652 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4653 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4654 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4655 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4656 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4657 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4658 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4659 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4660
bogdanm 82:6473597d706e 4661 /******************* Bit definition for CAN_F5R2 register *******************/
bogdanm 82:6473597d706e 4662 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4663 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4664 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4665 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4666 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4667 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4668 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4669 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4670 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4671 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4672 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4673 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4674 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4675 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4676 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4677 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4678 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4679 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4680 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4681 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4682 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4683 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4684 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4685 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4686 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4687 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4688 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4689 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4690 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4691 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4692 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4693 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4694
bogdanm 82:6473597d706e 4695 /******************* Bit definition for CAN_F6R2 register *******************/
bogdanm 82:6473597d706e 4696 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4697 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4698 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4699 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4700 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4701 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4702 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4703 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4704 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4705 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4706 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4707 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4708 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4709 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4710 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4711 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4712 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4713 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4714 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4715 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4716 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4717 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4718 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4719 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4720 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4721 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4722 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4723 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4724 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4725 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4726 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4727 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4728
bogdanm 82:6473597d706e 4729 /******************* Bit definition for CAN_F7R2 register *******************/
bogdanm 82:6473597d706e 4730 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4731 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4732 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4733 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4734 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4735 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4736 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4737 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4738 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4739 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4740 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4741 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4742 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4743 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4744 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4745 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4746 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4747 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4748 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4749 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4750 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4751 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4752 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4753 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4754 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4755 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4756 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4757 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4758 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4759 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4760 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4761 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4762
bogdanm 82:6473597d706e 4763 /******************* Bit definition for CAN_F8R2 register *******************/
bogdanm 82:6473597d706e 4764 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4765 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4766 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4767 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4768 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4769 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4770 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4771 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4772 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4773 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4774 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4775 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4776 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4777 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4778 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4779 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4780 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4781 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4782 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4783 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4784 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4785 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4786 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4787 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4788 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4789 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4790 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4791 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4792 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4793 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4794 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4795 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4796
bogdanm 82:6473597d706e 4797 /******************* Bit definition for CAN_F9R2 register *******************/
bogdanm 82:6473597d706e 4798 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4799 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4800 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4801 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4802 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4803 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4804 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4805 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4806 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4807 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4808 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4809 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4810 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4811 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4812 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4813 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4814 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4815 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4816 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4817 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4818 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4819 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4820 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4821 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4822 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4823 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4824 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4825 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4826 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4827 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4828 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4829 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4830
bogdanm 82:6473597d706e 4831 /******************* Bit definition for CAN_F10R2 register ******************/
bogdanm 82:6473597d706e 4832 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4833 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4834 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4835 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4836 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4837 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4838 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4839 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4840 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4841 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4842 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4843 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4844 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4845 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4846 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4847 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4848 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4849 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4850 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4851 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4852 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4853 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4854 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4855 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4856 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4857 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4858 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4859 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4860 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4861 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4862 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4863 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4864
bogdanm 82:6473597d706e 4865 /******************* Bit definition for CAN_F11R2 register ******************/
bogdanm 82:6473597d706e 4866 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4867 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4868 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4869 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4870 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4871 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4872 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4873 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4874 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4875 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4876 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4877 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4878 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4879 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4880 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4881 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4882 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4883 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4884 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4885 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4886 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4887 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4888 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4889 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4890 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4891 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4892 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4893 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4894 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4895 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4896 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4897 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4898
bogdanm 82:6473597d706e 4899 /******************* Bit definition for CAN_F12R2 register ******************/
bogdanm 82:6473597d706e 4900 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4901 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4902 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4903 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4904 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4905 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4906 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4907 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4908 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4909 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4910 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4911 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4912 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4913 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4914 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4915 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4916 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4917 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4918 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4919 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4920 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4921 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4922 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4923 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4924 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4925 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4926 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4927 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4928 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4929 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4930 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4931 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4932
bogdanm 82:6473597d706e 4933 /******************* Bit definition for CAN_F13R2 register ******************/
bogdanm 82:6473597d706e 4934 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 82:6473597d706e 4935 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 82:6473597d706e 4936 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 82:6473597d706e 4937 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 82:6473597d706e 4938 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 82:6473597d706e 4939 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 82:6473597d706e 4940 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 82:6473597d706e 4941 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 82:6473597d706e 4942 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 82:6473597d706e 4943 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 82:6473597d706e 4944 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 82:6473597d706e 4945 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 82:6473597d706e 4946 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 82:6473597d706e 4947 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 82:6473597d706e 4948 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 82:6473597d706e 4949 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 82:6473597d706e 4950 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 82:6473597d706e 4951 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 82:6473597d706e 4952 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 82:6473597d706e 4953 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 82:6473597d706e 4954 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 82:6473597d706e 4955 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 82:6473597d706e 4956 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 82:6473597d706e 4957 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 82:6473597d706e 4958 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 82:6473597d706e 4959 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 82:6473597d706e 4960 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 82:6473597d706e 4961 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 82:6473597d706e 4962 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 82:6473597d706e 4963 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 82:6473597d706e 4964 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 82:6473597d706e 4965 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 82:6473597d706e 4966
bogdanm 82:6473597d706e 4967 /******************************************************************************/
bogdanm 82:6473597d706e 4968 /* */
bogdanm 82:6473597d706e 4969 /* CRC calculation unit (CRC) */
bogdanm 82:6473597d706e 4970 /* */
bogdanm 82:6473597d706e 4971 /******************************************************************************/
bogdanm 82:6473597d706e 4972 /******************* Bit definition for CRC_DR register *********************/
bogdanm 82:6473597d706e 4973 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 82:6473597d706e 4974
bogdanm 82:6473597d706e 4975 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 82:6473597d706e 4976 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
bogdanm 82:6473597d706e 4977
bogdanm 82:6473597d706e 4978 /******************** Bit definition for CRC_CR register ********************/
bogdanm 82:6473597d706e 4979 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
bogdanm 82:6473597d706e 4980 #define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
bogdanm 82:6473597d706e 4981 #define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
bogdanm 82:6473597d706e 4982 #define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
bogdanm 82:6473597d706e 4983 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
bogdanm 82:6473597d706e 4984 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 82:6473597d706e 4985 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 82:6473597d706e 4986 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
bogdanm 82:6473597d706e 4987
bogdanm 82:6473597d706e 4988 /******************* Bit definition for CRC_INIT register *******************/
bogdanm 82:6473597d706e 4989 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
bogdanm 82:6473597d706e 4990
bogdanm 82:6473597d706e 4991 /******************* Bit definition for CRC_POL register ********************/
bogdanm 82:6473597d706e 4992 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
bogdanm 82:6473597d706e 4993 /******************************************************************************/
bogdanm 82:6473597d706e 4994 /* */
bogdanm 82:6473597d706e 4995 /* Digital to Analog Converter (DAC) */
bogdanm 82:6473597d706e 4996 /* */
bogdanm 82:6473597d706e 4997 /******************************************************************************/
bogdanm 82:6473597d706e 4998 /******************** Bit definition for DAC_CR register ********************/
bogdanm 82:6473597d706e 4999 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
bogdanm 82:6473597d706e 5000 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
bogdanm 82:6473597d706e 5001 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
bogdanm 82:6473597d706e 5002
bogdanm 82:6473597d706e 5003 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
bogdanm 82:6473597d706e 5004 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 82:6473597d706e 5005 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 82:6473597d706e 5006 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 82:6473597d706e 5007
bogdanm 82:6473597d706e 5008 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
bogdanm 82:6473597d706e 5009 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 82:6473597d706e 5010 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 82:6473597d706e 5011
bogdanm 82:6473597d706e 5012 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
bogdanm 82:6473597d706e 5013 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 82:6473597d706e 5014 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 82:6473597d706e 5015 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 82:6473597d706e 5016 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 82:6473597d706e 5017
bogdanm 82:6473597d706e 5018 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
bogdanm 82:6473597d706e 5019 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
bogdanm 82:6473597d706e 5020 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
bogdanm 82:6473597d706e 5021 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
bogdanm 82:6473597d706e 5022
bogdanm 82:6473597d706e 5023 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
bogdanm 82:6473597d706e 5024 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
bogdanm 82:6473597d706e 5025 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
bogdanm 82:6473597d706e 5026 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
bogdanm 82:6473597d706e 5027
bogdanm 82:6473597d706e 5028 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
bogdanm 82:6473597d706e 5029 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
bogdanm 82:6473597d706e 5030 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
bogdanm 82:6473597d706e 5031
bogdanm 82:6473597d706e 5032 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
bogdanm 82:6473597d706e 5033 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 82:6473597d706e 5034 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 82:6473597d706e 5035 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 82:6473597d706e 5036 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 82:6473597d706e 5037
bogdanm 82:6473597d706e 5038 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
bogdanm 82:6473597d706e 5039
bogdanm 82:6473597d706e 5040 /***************** Bit definition for DAC_SWTRIGR register ******************/
bogdanm 82:6473597d706e 5041 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
bogdanm 82:6473597d706e 5042 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
bogdanm 82:6473597d706e 5043
bogdanm 82:6473597d706e 5044 /***************** Bit definition for DAC_DHR12R1 register ******************/
bogdanm 82:6473597d706e 5045 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 82:6473597d706e 5046
bogdanm 82:6473597d706e 5047 /***************** Bit definition for DAC_DHR12L1 register ******************/
bogdanm 82:6473597d706e 5048 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 82:6473597d706e 5049
bogdanm 82:6473597d706e 5050 /****************** Bit definition for DAC_DHR8R1 register ******************/
bogdanm 82:6473597d706e 5051 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 82:6473597d706e 5052
bogdanm 82:6473597d706e 5053 /***************** Bit definition for DAC_DHR12R2 register ******************/
bogdanm 82:6473597d706e 5054 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 82:6473597d706e 5055
bogdanm 82:6473597d706e 5056 /***************** Bit definition for DAC_DHR12L2 register ******************/
bogdanm 82:6473597d706e 5057 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 82:6473597d706e 5058
bogdanm 82:6473597d706e 5059 /****************** Bit definition for DAC_DHR8R2 register ******************/
bogdanm 82:6473597d706e 5060 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 82:6473597d706e 5061
bogdanm 82:6473597d706e 5062 /***************** Bit definition for DAC_DHR12RD register ******************/
bogdanm 82:6473597d706e 5063 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 82:6473597d706e 5064 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 82:6473597d706e 5065
bogdanm 82:6473597d706e 5066 /***************** Bit definition for DAC_DHR12LD register ******************/
bogdanm 82:6473597d706e 5067 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 82:6473597d706e 5068 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 82:6473597d706e 5069
bogdanm 82:6473597d706e 5070 /****************** Bit definition for DAC_DHR8RD register ******************/
bogdanm 82:6473597d706e 5071 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 82:6473597d706e 5072 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 82:6473597d706e 5073
bogdanm 82:6473597d706e 5074 /******************* Bit definition for DAC_DOR1 register *******************/
bogdanm 82:6473597d706e 5075 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
bogdanm 82:6473597d706e 5076
bogdanm 82:6473597d706e 5077 /******************* Bit definition for DAC_DOR2 register *******************/
bogdanm 82:6473597d706e 5078 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
bogdanm 82:6473597d706e 5079
bogdanm 82:6473597d706e 5080 /******************** Bit definition for DAC_SR register ********************/
bogdanm 82:6473597d706e 5081 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
bogdanm 82:6473597d706e 5082 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
bogdanm 82:6473597d706e 5083
bogdanm 82:6473597d706e 5084 /******************************************************************************/
bogdanm 82:6473597d706e 5085 /* */
bogdanm 82:6473597d706e 5086 /* Debug MCU (DBGMCU) */
bogdanm 82:6473597d706e 5087 /* */
bogdanm 82:6473597d706e 5088 /******************************************************************************/
bogdanm 82:6473597d706e 5089 /******************** Bit definition for DBGMCU_IDCODE register *************/
bogdanm 82:6473597d706e 5090 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
bogdanm 82:6473597d706e 5091 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm 82:6473597d706e 5092
bogdanm 82:6473597d706e 5093 /******************** Bit definition for DBGMCU_CR register *****************/
bogdanm 82:6473597d706e 5094 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5095 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5096 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5097 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5098
bogdanm 82:6473597d706e 5099 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm 82:6473597d706e 5100 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
bogdanm 82:6473597d706e 5101 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
bogdanm 82:6473597d706e 5102
bogdanm 82:6473597d706e 5103 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
bogdanm 82:6473597d706e 5104 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5105 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5106 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5107 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5108 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5109 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5110 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5111 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5112 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 5113 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 5114 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 5115
bogdanm 82:6473597d706e 5116 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
bogdanm 82:6473597d706e 5117 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5118 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5119 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5120 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5121 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5122
bogdanm 82:6473597d706e 5123 /******************************************************************************/
bogdanm 82:6473597d706e 5124 /* */
bogdanm 82:6473597d706e 5125 /* DMA Controller (DMA) */
bogdanm 82:6473597d706e 5126 /* */
bogdanm 82:6473597d706e 5127 /******************************************************************************/
bogdanm 82:6473597d706e 5128 /******************* Bit definition for DMA_ISR register ********************/
bogdanm 82:6473597d706e 5129 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
bogdanm 82:6473597d706e 5130 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
bogdanm 82:6473597d706e 5131 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
bogdanm 82:6473597d706e 5132 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
bogdanm 82:6473597d706e 5133 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
bogdanm 82:6473597d706e 5134 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
bogdanm 82:6473597d706e 5135 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
bogdanm 82:6473597d706e 5136 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
bogdanm 82:6473597d706e 5137 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
bogdanm 82:6473597d706e 5138 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
bogdanm 82:6473597d706e 5139 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
bogdanm 82:6473597d706e 5140 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
bogdanm 82:6473597d706e 5141 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
bogdanm 82:6473597d706e 5142 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
bogdanm 82:6473597d706e 5143 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
bogdanm 82:6473597d706e 5144 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
bogdanm 82:6473597d706e 5145 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
bogdanm 82:6473597d706e 5146 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
bogdanm 82:6473597d706e 5147 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
bogdanm 82:6473597d706e 5148 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
bogdanm 82:6473597d706e 5149 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
bogdanm 82:6473597d706e 5150 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
bogdanm 82:6473597d706e 5151 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
bogdanm 82:6473597d706e 5152 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
bogdanm 82:6473597d706e 5153 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
bogdanm 82:6473597d706e 5154 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
bogdanm 82:6473597d706e 5155 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
bogdanm 82:6473597d706e 5156 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
bogdanm 82:6473597d706e 5157
bogdanm 82:6473597d706e 5158 /******************* Bit definition for DMA_IFCR register *******************/
bogdanm 82:6473597d706e 5159 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
bogdanm 82:6473597d706e 5160 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
bogdanm 82:6473597d706e 5161 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
bogdanm 82:6473597d706e 5162 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
bogdanm 82:6473597d706e 5163 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
bogdanm 82:6473597d706e 5164 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
bogdanm 82:6473597d706e 5165 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
bogdanm 82:6473597d706e 5166 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
bogdanm 82:6473597d706e 5167 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
bogdanm 82:6473597d706e 5168 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
bogdanm 82:6473597d706e 5169 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
bogdanm 82:6473597d706e 5170 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
bogdanm 82:6473597d706e 5171 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
bogdanm 82:6473597d706e 5172 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
bogdanm 82:6473597d706e 5173 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
bogdanm 82:6473597d706e 5174 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
bogdanm 82:6473597d706e 5175 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
bogdanm 82:6473597d706e 5176 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
bogdanm 82:6473597d706e 5177 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
bogdanm 82:6473597d706e 5178 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
bogdanm 82:6473597d706e 5179 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
bogdanm 82:6473597d706e 5180 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
bogdanm 82:6473597d706e 5181 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
bogdanm 82:6473597d706e 5182 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
bogdanm 82:6473597d706e 5183 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
bogdanm 82:6473597d706e 5184 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
bogdanm 82:6473597d706e 5185 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
bogdanm 82:6473597d706e 5186 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
bogdanm 82:6473597d706e 5187
bogdanm 82:6473597d706e 5188 /******************* Bit definition for DMA_CCR register ********************/
bogdanm 82:6473597d706e 5189 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
bogdanm 82:6473597d706e 5190 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
bogdanm 82:6473597d706e 5191 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
bogdanm 82:6473597d706e 5192 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
bogdanm 82:6473597d706e 5193 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
bogdanm 82:6473597d706e 5194 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
bogdanm 82:6473597d706e 5195 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
bogdanm 82:6473597d706e 5196 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
bogdanm 82:6473597d706e 5197
bogdanm 82:6473597d706e 5198 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 82:6473597d706e 5199 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 82:6473597d706e 5200 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 82:6473597d706e 5201
bogdanm 82:6473597d706e 5202 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 82:6473597d706e 5203 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 82:6473597d706e 5204 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 82:6473597d706e 5205
bogdanm 82:6473597d706e 5206 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
bogdanm 82:6473597d706e 5207 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 82:6473597d706e 5208 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 82:6473597d706e 5209
bogdanm 82:6473597d706e 5210 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
bogdanm 82:6473597d706e 5211
bogdanm 82:6473597d706e 5212 /****************** Bit definition for DMA_CNDTR register *******************/
bogdanm 82:6473597d706e 5213 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
bogdanm 82:6473597d706e 5214
bogdanm 82:6473597d706e 5215 /****************** Bit definition for DMA_CPAR register ********************/
bogdanm 82:6473597d706e 5216 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 82:6473597d706e 5217
bogdanm 82:6473597d706e 5218 /****************** Bit definition for DMA_CMAR register ********************/
bogdanm 82:6473597d706e 5219 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 82:6473597d706e 5220
bogdanm 82:6473597d706e 5221 /******************************************************************************/
bogdanm 82:6473597d706e 5222 /* */
bogdanm 82:6473597d706e 5223 /* External Interrupt/Event Controller (EXTI) */
bogdanm 82:6473597d706e 5224 /* */
bogdanm 82:6473597d706e 5225 /******************************************************************************/
bogdanm 82:6473597d706e 5226 /******************* Bit definition for EXTI_IMR register *******************/
bogdanm 82:6473597d706e 5227 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 82:6473597d706e 5228 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 82:6473597d706e 5229 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 82:6473597d706e 5230 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 82:6473597d706e 5231 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 82:6473597d706e 5232 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 82:6473597d706e 5233 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 82:6473597d706e 5234 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 82:6473597d706e 5235 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 82:6473597d706e 5236 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 82:6473597d706e 5237 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 82:6473597d706e 5238 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 82:6473597d706e 5239 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 82:6473597d706e 5240 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 82:6473597d706e 5241 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 82:6473597d706e 5242 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 82:6473597d706e 5243 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 82:6473597d706e 5244 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 82:6473597d706e 5245 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 82:6473597d706e 5246 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 82:6473597d706e 5247 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
bogdanm 82:6473597d706e 5248 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
bogdanm 82:6473597d706e 5249 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
bogdanm 82:6473597d706e 5250 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
bogdanm 82:6473597d706e 5251 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
bogdanm 82:6473597d706e 5252 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
bogdanm 82:6473597d706e 5253 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
bogdanm 82:6473597d706e 5254 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
bogdanm 82:6473597d706e 5255 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
bogdanm 82:6473597d706e 5256
bogdanm 82:6473597d706e 5257 /******************* Bit definition for EXTI_EMR register *******************/
bogdanm 82:6473597d706e 5258 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 82:6473597d706e 5259 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 82:6473597d706e 5260 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 82:6473597d706e 5261 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 82:6473597d706e 5262 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 82:6473597d706e 5263 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 82:6473597d706e 5264 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 82:6473597d706e 5265 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 82:6473597d706e 5266 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 82:6473597d706e 5267 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 82:6473597d706e 5268 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 82:6473597d706e 5269 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 82:6473597d706e 5270 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 82:6473597d706e 5271 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 82:6473597d706e 5272 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 82:6473597d706e 5273 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 82:6473597d706e 5274 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 82:6473597d706e 5275 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 82:6473597d706e 5276 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 82:6473597d706e 5277 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 82:6473597d706e 5278 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
bogdanm 82:6473597d706e 5279 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
bogdanm 82:6473597d706e 5280 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
bogdanm 82:6473597d706e 5281 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
bogdanm 82:6473597d706e 5282 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
bogdanm 82:6473597d706e 5283 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
bogdanm 82:6473597d706e 5284 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
bogdanm 82:6473597d706e 5285 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
bogdanm 82:6473597d706e 5286 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
bogdanm 82:6473597d706e 5287
bogdanm 82:6473597d706e 5288 /****************** Bit definition for EXTI_RTSR register *******************/
bogdanm 82:6473597d706e 5289 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 82:6473597d706e 5290 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 82:6473597d706e 5291 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 82:6473597d706e 5292 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 82:6473597d706e 5293 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 82:6473597d706e 5294 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 82:6473597d706e 5295 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 82:6473597d706e 5296 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 82:6473597d706e 5297 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 82:6473597d706e 5298 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 82:6473597d706e 5299 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 82:6473597d706e 5300 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 82:6473597d706e 5301 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 82:6473597d706e 5302 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 82:6473597d706e 5303 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 82:6473597d706e 5304 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 82:6473597d706e 5305 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 82:6473597d706e 5306 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 82:6473597d706e 5307 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
bogdanm 82:6473597d706e 5308 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 82:6473597d706e 5309 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
bogdanm 82:6473597d706e 5310 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
bogdanm 82:6473597d706e 5311 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
bogdanm 82:6473597d706e 5312 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
bogdanm 82:6473597d706e 5313 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
bogdanm 82:6473597d706e 5314 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
bogdanm 82:6473597d706e 5315 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
bogdanm 82:6473597d706e 5316 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
bogdanm 82:6473597d706e 5317 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
bogdanm 82:6473597d706e 5318
bogdanm 82:6473597d706e 5319 /****************** Bit definition for EXTI_FTSR register *******************/
bogdanm 82:6473597d706e 5320 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 82:6473597d706e 5321 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 82:6473597d706e 5322 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 82:6473597d706e 5323 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 82:6473597d706e 5324 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 82:6473597d706e 5325 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 82:6473597d706e 5326 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 82:6473597d706e 5327 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 82:6473597d706e 5328 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 82:6473597d706e 5329 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 82:6473597d706e 5330 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 82:6473597d706e 5331 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 82:6473597d706e 5332 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 82:6473597d706e 5333 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 82:6473597d706e 5334 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 82:6473597d706e 5335 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 82:6473597d706e 5336 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 82:6473597d706e 5337 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 82:6473597d706e 5338 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
bogdanm 82:6473597d706e 5339 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 82:6473597d706e 5340 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
bogdanm 82:6473597d706e 5341 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
bogdanm 82:6473597d706e 5342 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
bogdanm 82:6473597d706e 5343 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
bogdanm 82:6473597d706e 5344 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
bogdanm 82:6473597d706e 5345 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
bogdanm 82:6473597d706e 5346 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
bogdanm 82:6473597d706e 5347 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
bogdanm 82:6473597d706e 5348 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
bogdanm 82:6473597d706e 5349
bogdanm 82:6473597d706e 5350 /****************** Bit definition for EXTI_SWIER register ******************/
bogdanm 82:6473597d706e 5351 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 82:6473597d706e 5352 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 82:6473597d706e 5353 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 82:6473597d706e 5354 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 82:6473597d706e 5355 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 82:6473597d706e 5356 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 82:6473597d706e 5357 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 82:6473597d706e 5358 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 82:6473597d706e 5359 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 82:6473597d706e 5360 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 82:6473597d706e 5361 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 82:6473597d706e 5362 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 82:6473597d706e 5363 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 82:6473597d706e 5364 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 82:6473597d706e 5365 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 82:6473597d706e 5366 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 82:6473597d706e 5367 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 82:6473597d706e 5368 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 82:6473597d706e 5369 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
bogdanm 82:6473597d706e 5370 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 82:6473597d706e 5371 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
bogdanm 82:6473597d706e 5372 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
bogdanm 82:6473597d706e 5373 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
bogdanm 82:6473597d706e 5374 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
bogdanm 82:6473597d706e 5375 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
bogdanm 82:6473597d706e 5376 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
bogdanm 82:6473597d706e 5377 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
bogdanm 82:6473597d706e 5378 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
bogdanm 82:6473597d706e 5379 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
bogdanm 82:6473597d706e 5380
bogdanm 82:6473597d706e 5381 /******************* Bit definition for EXTI_PR register ********************/
bogdanm 82:6473597d706e 5382 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
bogdanm 82:6473597d706e 5383 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
bogdanm 82:6473597d706e 5384 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
bogdanm 82:6473597d706e 5385 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
bogdanm 82:6473597d706e 5386 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
bogdanm 82:6473597d706e 5387 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
bogdanm 82:6473597d706e 5388 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
bogdanm 82:6473597d706e 5389 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
bogdanm 82:6473597d706e 5390 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
bogdanm 82:6473597d706e 5391 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
bogdanm 82:6473597d706e 5392 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
bogdanm 82:6473597d706e 5393 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
bogdanm 82:6473597d706e 5394 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
bogdanm 82:6473597d706e 5395 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
bogdanm 82:6473597d706e 5396 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
bogdanm 82:6473597d706e 5397 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
bogdanm 82:6473597d706e 5398 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
bogdanm 82:6473597d706e 5399 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
bogdanm 82:6473597d706e 5400 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
bogdanm 82:6473597d706e 5401 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
bogdanm 82:6473597d706e 5402 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
bogdanm 82:6473597d706e 5403 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
bogdanm 82:6473597d706e 5404 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
bogdanm 82:6473597d706e 5405 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
bogdanm 82:6473597d706e 5406 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
bogdanm 82:6473597d706e 5407 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
bogdanm 82:6473597d706e 5408 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
bogdanm 82:6473597d706e 5409 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
bogdanm 82:6473597d706e 5410 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
bogdanm 82:6473597d706e 5411
bogdanm 82:6473597d706e 5412 /******************************************************************************/
bogdanm 82:6473597d706e 5413 /* */
bogdanm 82:6473597d706e 5414 /* FLASH */
bogdanm 82:6473597d706e 5415 /* */
bogdanm 82:6473597d706e 5416 /******************************************************************************/
bogdanm 82:6473597d706e 5417 /******************* Bit definition for FLASH_ACR register ******************/
bogdanm 82:6473597d706e 5418 #define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
bogdanm 82:6473597d706e 5419 #define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /*!< Bit 0 */
bogdanm 82:6473597d706e 5420 #define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /*!< Bit 1 */
bogdanm 82:6473597d706e 5421
bogdanm 82:6473597d706e 5422 #define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */
bogdanm 82:6473597d706e 5423 #define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */
bogdanm 82:6473597d706e 5424 #define FLASH_ACR_PRFTBS ((uint8_t)0x20)
bogdanm 82:6473597d706e 5425
bogdanm 82:6473597d706e 5426 /****************** Bit definition for FLASH_KEYR register ******************/
bogdanm 82:6473597d706e 5427 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
bogdanm 82:6473597d706e 5428
bogdanm 82:6473597d706e 5429 #define RDP_KEY ((uint16_t)0x00A5) /*!< RDP Key */
bogdanm 82:6473597d706e 5430 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
bogdanm 82:6473597d706e 5431 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
bogdanm 82:6473597d706e 5432
bogdanm 82:6473597d706e 5433 /***************** Bit definition for FLASH_OPTKEYR register ****************/
bogdanm 82:6473597d706e 5434 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
bogdanm 82:6473597d706e 5435
bogdanm 82:6473597d706e 5436 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
bogdanm 82:6473597d706e 5437 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
bogdanm 82:6473597d706e 5438
bogdanm 82:6473597d706e 5439 /****************** Bit definition for FLASH_SR register *******************/
bogdanm 82:6473597d706e 5440 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
bogdanm 82:6473597d706e 5441 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
bogdanm 82:6473597d706e 5442 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
bogdanm 82:6473597d706e 5443 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
bogdanm 82:6473597d706e 5444
bogdanm 82:6473597d706e 5445 /******************* Bit definition for FLASH_CR register *******************/
bogdanm 82:6473597d706e 5446 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
bogdanm 82:6473597d706e 5447 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
bogdanm 82:6473597d706e 5448 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
bogdanm 82:6473597d706e 5449 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
bogdanm 82:6473597d706e 5450 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
bogdanm 82:6473597d706e 5451 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
bogdanm 82:6473597d706e 5452 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
bogdanm 82:6473597d706e 5453 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
bogdanm 82:6473597d706e 5454 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
bogdanm 82:6473597d706e 5455 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
bogdanm 82:6473597d706e 5456 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
bogdanm 82:6473597d706e 5457
bogdanm 82:6473597d706e 5458 /******************* Bit definition for FLASH_AR register *******************/
bogdanm 82:6473597d706e 5459 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
bogdanm 82:6473597d706e 5460
bogdanm 82:6473597d706e 5461 /****************** Bit definition for FLASH_OBR register *******************/
bogdanm 82:6473597d706e 5462 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
bogdanm 82:6473597d706e 5463 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
bogdanm 82:6473597d706e 5464 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
bogdanm 82:6473597d706e 5465
bogdanm 82:6473597d706e 5466 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
bogdanm 82:6473597d706e 5467 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
bogdanm 82:6473597d706e 5468 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
bogdanm 82:6473597d706e 5469 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
bogdanm 82:6473597d706e 5470
bogdanm 82:6473597d706e 5471 /****************** Bit definition for FLASH_WRPR register ******************/
bogdanm 82:6473597d706e 5472 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
bogdanm 82:6473597d706e 5473
bogdanm 82:6473597d706e 5474 /*----------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 5475
bogdanm 82:6473597d706e 5476 /****************** Bit definition for OB_RDP register **********************/
bogdanm 82:6473597d706e 5477 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
bogdanm 82:6473597d706e 5478 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
bogdanm 82:6473597d706e 5479
bogdanm 82:6473597d706e 5480 /****************** Bit definition for OB_USER register *********************/
bogdanm 82:6473597d706e 5481 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
bogdanm 82:6473597d706e 5482 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
bogdanm 82:6473597d706e 5483
bogdanm 82:6473597d706e 5484 /****************** Bit definition for FLASH_WRP0 register ******************/
bogdanm 82:6473597d706e 5485 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
bogdanm 82:6473597d706e 5486 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
bogdanm 82:6473597d706e 5487
bogdanm 82:6473597d706e 5488 /****************** Bit definition for FLASH_WRP1 register ******************/
bogdanm 82:6473597d706e 5489 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
bogdanm 82:6473597d706e 5490 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
bogdanm 82:6473597d706e 5491
bogdanm 82:6473597d706e 5492 /****************** Bit definition for FLASH_WRP2 register ******************/
bogdanm 82:6473597d706e 5493 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
bogdanm 82:6473597d706e 5494 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
bogdanm 82:6473597d706e 5495
bogdanm 82:6473597d706e 5496 /****************** Bit definition for FLASH_WRP3 register ******************/
bogdanm 82:6473597d706e 5497 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
bogdanm 82:6473597d706e 5498 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
bogdanm 82:6473597d706e 5499 /******************************************************************************/
bogdanm 82:6473597d706e 5500 /* */
bogdanm 82:6473597d706e 5501 /* General Purpose I/O (GPIO) */
bogdanm 82:6473597d706e 5502 /* */
bogdanm 82:6473597d706e 5503 /******************************************************************************/
bogdanm 82:6473597d706e 5504 /******************* Bit definition for GPIO_MODER register *****************/
bogdanm 82:6473597d706e 5505 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm 82:6473597d706e 5506 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5507 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5508 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm 82:6473597d706e 5509 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5510 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5511 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm 82:6473597d706e 5512 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5513 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5514 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm 82:6473597d706e 5515 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5516 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5517 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm 82:6473597d706e 5518 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5519 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5520 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm 82:6473597d706e 5521 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5522 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5523 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm 82:6473597d706e 5524 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5525 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5526 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm 82:6473597d706e 5527 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5528 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5529 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm 82:6473597d706e 5530 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 5531 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 5532 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm 82:6473597d706e 5533 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 5534 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 5535 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm 82:6473597d706e 5536 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 5537 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 5538 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm 82:6473597d706e 5539 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 5540 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 5541 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm 82:6473597d706e 5542 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 5543 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 5544 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm 82:6473597d706e 5545 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 5546 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 5547 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm 82:6473597d706e 5548 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 5549 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 5550 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm 82:6473597d706e 5551 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm 82:6473597d706e 5552 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm 82:6473597d706e 5553
bogdanm 82:6473597d706e 5554
bogdanm 82:6473597d706e 5555 /****************** Bit definition for GPIO_OTYPER register *****************/
bogdanm 82:6473597d706e 5556 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5557 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5558 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5559 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5560 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5561 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5562 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5563 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5564 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5565 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5566 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5567 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5568 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5569 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5570 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5571 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5572
bogdanm 82:6473597d706e 5573
bogdanm 82:6473597d706e 5574 /**************** Bit definition for GPIO_OSPEEDR register ******************/
bogdanm 82:6473597d706e 5575 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm 82:6473597d706e 5576 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5577 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5578 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm 82:6473597d706e 5579 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5580 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5581 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm 82:6473597d706e 5582 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5583 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5584 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm 82:6473597d706e 5585 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5586 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5587 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm 82:6473597d706e 5588 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5589 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5590 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm 82:6473597d706e 5591 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5592 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5593 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm 82:6473597d706e 5594 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5595 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5596 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm 82:6473597d706e 5597 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5598 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5599 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm 82:6473597d706e 5600 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 5601 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 5602 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm 82:6473597d706e 5603 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 5604 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 5605 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm 82:6473597d706e 5606 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 5607 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 5608 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm 82:6473597d706e 5609 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 5610 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 5611 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm 82:6473597d706e 5612 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 5613 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 5614 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm 82:6473597d706e 5615 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 5616 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 5617 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm 82:6473597d706e 5618 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 5619 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 5620 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm 82:6473597d706e 5621 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm 82:6473597d706e 5622 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm 82:6473597d706e 5623
bogdanm 82:6473597d706e 5624 /******************* Bit definition for GPIO_PUPDR register ******************/
bogdanm 82:6473597d706e 5625 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm 82:6473597d706e 5626 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5627 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5628 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm 82:6473597d706e 5629 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5630 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5631 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm 82:6473597d706e 5632 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5633 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5634 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm 82:6473597d706e 5635 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5636 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5637 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm 82:6473597d706e 5638 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5639 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5640 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm 82:6473597d706e 5641 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5642 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5643 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm 82:6473597d706e 5644 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5645 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5646 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm 82:6473597d706e 5647 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5648 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5649 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm 82:6473597d706e 5650 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 5651 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 5652 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm 82:6473597d706e 5653 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 5654 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 5655 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm 82:6473597d706e 5656 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 5657 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 5658 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm 82:6473597d706e 5659 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 5660 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 5661 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm 82:6473597d706e 5662 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 5663 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 5664 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm 82:6473597d706e 5665 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 5666 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 5667 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm 82:6473597d706e 5668 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 5669 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 5670 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm 82:6473597d706e 5671 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm 82:6473597d706e 5672 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm 82:6473597d706e 5673
bogdanm 82:6473597d706e 5674 /******************* Bit definition for GPIO_IDR register *******************/
bogdanm 82:6473597d706e 5675 #define GPIO_IDR_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5676 #define GPIO_IDR_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5677 #define GPIO_IDR_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5678 #define GPIO_IDR_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5679 #define GPIO_IDR_4 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5680 #define GPIO_IDR_5 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5681 #define GPIO_IDR_6 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5682 #define GPIO_IDR_7 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5683 #define GPIO_IDR_8 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5684 #define GPIO_IDR_9 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5685 #define GPIO_IDR_10 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5686 #define GPIO_IDR_11 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5687 #define GPIO_IDR_12 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5688 #define GPIO_IDR_13 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5689 #define GPIO_IDR_14 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5690 #define GPIO_IDR_15 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5691
bogdanm 82:6473597d706e 5692 /****************** Bit definition for GPIO_ODR register ********************/
bogdanm 82:6473597d706e 5693 #define GPIO_ODR_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5694 #define GPIO_ODR_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5695 #define GPIO_ODR_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5696 #define GPIO_ODR_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5697 #define GPIO_ODR_4 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5698 #define GPIO_ODR_5 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5699 #define GPIO_ODR_6 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5700 #define GPIO_ODR_7 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5701 #define GPIO_ODR_8 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5702 #define GPIO_ODR_9 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5703 #define GPIO_ODR_10 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5704 #define GPIO_ODR_11 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5705 #define GPIO_ODR_12 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5706 #define GPIO_ODR_13 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5707 #define GPIO_ODR_14 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5708 #define GPIO_ODR_15 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5709
bogdanm 82:6473597d706e 5710 /****************** Bit definition for GPIO_BSRR register ********************/
bogdanm 82:6473597d706e 5711 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5712 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5713 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5714 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5715 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5716 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5717 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5718 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5719 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5720 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5721 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5722 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5723 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5724 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5725 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5726 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5727 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 5728 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 5729 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 5730 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 5731 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 5732 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 5733 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 5734 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 5735 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 5736 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 5737 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 5738 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 5739 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 5740 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 5741 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm 82:6473597d706e 5742 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm 82:6473597d706e 5743
bogdanm 82:6473597d706e 5744 /****************** Bit definition for GPIO_LCKR register ********************/
bogdanm 82:6473597d706e 5745 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5746 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5747 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5748 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5749 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5750 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5751 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5752 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5753 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5754 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5755 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5756 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5757 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5758 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5759 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5760 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5761 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 5762
bogdanm 82:6473597d706e 5763 /****************** Bit definition for GPIO_AFRL register ********************/
bogdanm 82:6473597d706e 5764 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
bogdanm 82:6473597d706e 5765 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
bogdanm 82:6473597d706e 5766 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
bogdanm 82:6473597d706e 5767 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
bogdanm 82:6473597d706e 5768 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
bogdanm 82:6473597d706e 5769 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
bogdanm 82:6473597d706e 5770 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
bogdanm 82:6473597d706e 5771 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
bogdanm 82:6473597d706e 5772
bogdanm 82:6473597d706e 5773 /****************** Bit definition for GPIO_AFRH register ********************/
bogdanm 82:6473597d706e 5774 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
bogdanm 82:6473597d706e 5775 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
bogdanm 82:6473597d706e 5776 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
bogdanm 82:6473597d706e 5777 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
bogdanm 82:6473597d706e 5778 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
bogdanm 82:6473597d706e 5779 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
bogdanm 82:6473597d706e 5780 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
bogdanm 82:6473597d706e 5781 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
bogdanm 82:6473597d706e 5782
bogdanm 82:6473597d706e 5783 /****************** Bit definition for GPIO_BRR register *********************/
bogdanm 82:6473597d706e 5784 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5785 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5786 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 5787 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 5788 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 5789 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 5790 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 5791 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 5792 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 5793 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 5794 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 5795 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 5796 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 5797 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 5798 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 5799 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 5800
bogdanm 82:6473597d706e 5801 /******************************************************************************/
bogdanm 82:6473597d706e 5802 /* */
bogdanm 82:6473597d706e 5803 /* Inter-integrated Circuit Interface (I2C) */
bogdanm 82:6473597d706e 5804 /* */
bogdanm 82:6473597d706e 5805 /******************************************************************************/
bogdanm 82:6473597d706e 5806 /******************* Bit definition for I2C_CR1 register *******************/
bogdanm 82:6473597d706e 5807 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
bogdanm 82:6473597d706e 5808 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
bogdanm 82:6473597d706e 5809 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
bogdanm 82:6473597d706e 5810 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
bogdanm 82:6473597d706e 5811 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
bogdanm 82:6473597d706e 5812 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
bogdanm 82:6473597d706e 5813 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
bogdanm 82:6473597d706e 5814 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
bogdanm 82:6473597d706e 5815 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
bogdanm 82:6473597d706e 5816 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
bogdanm 82:6473597d706e 5817 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
bogdanm 82:6473597d706e 5818 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
bogdanm 82:6473597d706e 5819 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
bogdanm 82:6473597d706e 5820 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
bogdanm 82:6473597d706e 5821 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
bogdanm 82:6473597d706e 5822 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
bogdanm 82:6473597d706e 5823 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
bogdanm 82:6473597d706e 5824 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
bogdanm 82:6473597d706e 5825 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
bogdanm 82:6473597d706e 5826 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
bogdanm 82:6473597d706e 5827 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
bogdanm 82:6473597d706e 5828
bogdanm 82:6473597d706e 5829 /****************** Bit definition for I2C_CR2 register ********************/
bogdanm 82:6473597d706e 5830 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
bogdanm 82:6473597d706e 5831 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
bogdanm 82:6473597d706e 5832 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
bogdanm 82:6473597d706e 5833 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
bogdanm 82:6473597d706e 5834 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
bogdanm 82:6473597d706e 5835 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
bogdanm 82:6473597d706e 5836 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
bogdanm 82:6473597d706e 5837 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
bogdanm 82:6473597d706e 5838 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
bogdanm 82:6473597d706e 5839 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
bogdanm 82:6473597d706e 5840 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
bogdanm 82:6473597d706e 5841
bogdanm 82:6473597d706e 5842 /******************* Bit definition for I2C_OAR1 register ******************/
bogdanm 82:6473597d706e 5843 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
bogdanm 82:6473597d706e 5844 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
bogdanm 82:6473597d706e 5845 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
bogdanm 82:6473597d706e 5846
bogdanm 82:6473597d706e 5847 /******************* Bit definition for I2C_OAR2 register *******************/
bogdanm 82:6473597d706e 5848 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
bogdanm 82:6473597d706e 5849 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
bogdanm 82:6473597d706e 5850 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
bogdanm 82:6473597d706e 5851
bogdanm 82:6473597d706e 5852 /******************* Bit definition for I2C_TIMINGR register *****************/
bogdanm 82:6473597d706e 5853 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
bogdanm 82:6473597d706e 5854 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
bogdanm 82:6473597d706e 5855 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
bogdanm 82:6473597d706e 5856 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
bogdanm 82:6473597d706e 5857 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
bogdanm 82:6473597d706e 5858
bogdanm 82:6473597d706e 5859 /******************* Bit definition for I2C_TIMEOUTR register *****************/
bogdanm 82:6473597d706e 5860 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
bogdanm 82:6473597d706e 5861 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
bogdanm 82:6473597d706e 5862 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
bogdanm 82:6473597d706e 5863 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
bogdanm 82:6473597d706e 5864 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
bogdanm 82:6473597d706e 5865
bogdanm 82:6473597d706e 5866 /****************** Bit definition for I2C_ISR register *********************/
bogdanm 82:6473597d706e 5867 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
bogdanm 82:6473597d706e 5868 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
bogdanm 82:6473597d706e 5869 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
bogdanm 82:6473597d706e 5870 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
bogdanm 82:6473597d706e 5871 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
bogdanm 82:6473597d706e 5872 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
bogdanm 82:6473597d706e 5873 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
bogdanm 82:6473597d706e 5874 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
bogdanm 82:6473597d706e 5875 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
bogdanm 82:6473597d706e 5876 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
bogdanm 82:6473597d706e 5877 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
bogdanm 82:6473597d706e 5878 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
bogdanm 82:6473597d706e 5879 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
bogdanm 82:6473597d706e 5880 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
bogdanm 82:6473597d706e 5881 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
bogdanm 82:6473597d706e 5882 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
bogdanm 82:6473597d706e 5883 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
bogdanm 82:6473597d706e 5884
bogdanm 82:6473597d706e 5885 /****************** Bit definition for I2C_ICR register *********************/
bogdanm 82:6473597d706e 5886 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
bogdanm 82:6473597d706e 5887 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
bogdanm 82:6473597d706e 5888 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
bogdanm 82:6473597d706e 5889 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
bogdanm 82:6473597d706e 5890 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
bogdanm 82:6473597d706e 5891 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
bogdanm 82:6473597d706e 5892 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
bogdanm 82:6473597d706e 5893 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
bogdanm 82:6473597d706e 5894 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
bogdanm 82:6473597d706e 5895
bogdanm 82:6473597d706e 5896 /****************** Bit definition for I2C_PECR register ********************/
bogdanm 82:6473597d706e 5897 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
bogdanm 82:6473597d706e 5898
bogdanm 82:6473597d706e 5899 /****************** Bit definition for I2C_RXDR register *********************/
bogdanm 82:6473597d706e 5900 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
bogdanm 82:6473597d706e 5901
bogdanm 82:6473597d706e 5902 /****************** Bit definition for I2C_TXDR register *********************/
bogdanm 82:6473597d706e 5903 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
bogdanm 82:6473597d706e 5904
bogdanm 82:6473597d706e 5905
bogdanm 82:6473597d706e 5906 /******************************************************************************/
bogdanm 82:6473597d706e 5907 /* */
bogdanm 82:6473597d706e 5908 /* Independent WATCHDOG (IWDG) */
bogdanm 82:6473597d706e 5909 /* */
bogdanm 82:6473597d706e 5910 /******************************************************************************/
bogdanm 82:6473597d706e 5911 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 82:6473597d706e 5912 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
bogdanm 82:6473597d706e 5913
bogdanm 82:6473597d706e 5914 /******************* Bit definition for IWDG_PR register ********************/
bogdanm 82:6473597d706e 5915 #define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
bogdanm 82:6473597d706e 5916 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
bogdanm 82:6473597d706e 5917 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
bogdanm 82:6473597d706e 5918 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
bogdanm 82:6473597d706e 5919
bogdanm 82:6473597d706e 5920 /******************* Bit definition for IWDG_RLR register *******************/
bogdanm 82:6473597d706e 5921 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
bogdanm 82:6473597d706e 5922
bogdanm 82:6473597d706e 5923 /******************* Bit definition for IWDG_SR register ********************/
bogdanm 82:6473597d706e 5924 #define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
bogdanm 82:6473597d706e 5925 #define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
bogdanm 82:6473597d706e 5926 #define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */
bogdanm 82:6473597d706e 5927
bogdanm 82:6473597d706e 5928 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 82:6473597d706e 5929 #define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */
bogdanm 82:6473597d706e 5930
bogdanm 82:6473597d706e 5931 /******************************************************************************/
bogdanm 82:6473597d706e 5932 /* */
bogdanm 82:6473597d706e 5933 /* Power Control */
bogdanm 82:6473597d706e 5934 /* */
bogdanm 82:6473597d706e 5935 /******************************************************************************/
bogdanm 82:6473597d706e 5936 /******************** Bit definition for PWR_CR register ********************/
bogdanm 82:6473597d706e 5937 #define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */
bogdanm 82:6473597d706e 5938 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
bogdanm 82:6473597d706e 5939 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
bogdanm 82:6473597d706e 5940 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
bogdanm 82:6473597d706e 5941 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
bogdanm 82:6473597d706e 5942
bogdanm 82:6473597d706e 5943 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 82:6473597d706e 5944 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
bogdanm 82:6473597d706e 5945 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
bogdanm 82:6473597d706e 5946 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
bogdanm 82:6473597d706e 5947
bogdanm 82:6473597d706e 5948 /*!< PVD level configuration */
bogdanm 82:6473597d706e 5949 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
bogdanm 82:6473597d706e 5950 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
bogdanm 82:6473597d706e 5951 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
bogdanm 82:6473597d706e 5952 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
bogdanm 82:6473597d706e 5953 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
bogdanm 82:6473597d706e 5954 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
bogdanm 82:6473597d706e 5955 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
bogdanm 82:6473597d706e 5956 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
bogdanm 82:6473597d706e 5957
bogdanm 82:6473597d706e 5958 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
bogdanm 82:6473597d706e 5959
bogdanm 82:6473597d706e 5960 /******************* Bit definition for PWR_CSR register ********************/
bogdanm 82:6473597d706e 5961 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
bogdanm 82:6473597d706e 5962 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
bogdanm 82:6473597d706e 5963 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
bogdanm 82:6473597d706e 5964 #define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */
bogdanm 82:6473597d706e 5965
bogdanm 82:6473597d706e 5966 #define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
bogdanm 82:6473597d706e 5967 #define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
bogdanm 82:6473597d706e 5968 #define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
bogdanm 82:6473597d706e 5969
bogdanm 82:6473597d706e 5970 /******************************************************************************/
bogdanm 82:6473597d706e 5971 /* */
bogdanm 82:6473597d706e 5972 /* Reset and Clock Control */
bogdanm 82:6473597d706e 5973 /* */
bogdanm 82:6473597d706e 5974 /******************************************************************************/
bogdanm 82:6473597d706e 5975 /******************** Bit definition for RCC_CR register ********************/
bogdanm 82:6473597d706e 5976 #define RCC_CR_HSION ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 5977 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 5978
bogdanm 82:6473597d706e 5979 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
bogdanm 82:6473597d706e 5980 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
bogdanm 82:6473597d706e 5981 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
bogdanm 82:6473597d706e 5982 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
bogdanm 82:6473597d706e 5983 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
bogdanm 82:6473597d706e 5984 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
bogdanm 82:6473597d706e 5985
bogdanm 82:6473597d706e 5986 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
bogdanm 82:6473597d706e 5987 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
bogdanm 82:6473597d706e 5988 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
bogdanm 82:6473597d706e 5989 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
bogdanm 82:6473597d706e 5990 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
bogdanm 82:6473597d706e 5991 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
bogdanm 82:6473597d706e 5992 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
bogdanm 82:6473597d706e 5993 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
bogdanm 82:6473597d706e 5994 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
bogdanm 82:6473597d706e 5995
bogdanm 82:6473597d706e 5996 #define RCC_CR_HSEON ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 5997 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 5998 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 5999 #define RCC_CR_CSSON ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 6000
bogdanm 82:6473597d706e 6001 #define RCC_CR_PLLON ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 6002 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 6003
bogdanm 82:6473597d706e 6004 /******************** Bit definition for RCC_CFGR register ******************/
bogdanm 82:6473597d706e 6005 /*!< SW configuration */
bogdanm 82:6473597d706e 6006 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 82:6473597d706e 6007 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 82:6473597d706e 6008 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 82:6473597d706e 6009
bogdanm 82:6473597d706e 6010 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
bogdanm 82:6473597d706e 6011 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
bogdanm 82:6473597d706e 6012 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
bogdanm 82:6473597d706e 6013
bogdanm 82:6473597d706e 6014 /*!< SWS configuration */
bogdanm 82:6473597d706e 6015 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 82:6473597d706e 6016 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 82:6473597d706e 6017 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 82:6473597d706e 6018
bogdanm 82:6473597d706e 6019 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
bogdanm 82:6473597d706e 6020 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
bogdanm 82:6473597d706e 6021 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
bogdanm 82:6473597d706e 6022
bogdanm 82:6473597d706e 6023 /*!< HPRE configuration */
bogdanm 82:6473597d706e 6024 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 82:6473597d706e 6025 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 82:6473597d706e 6026 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 82:6473597d706e 6027 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 82:6473597d706e 6028 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 82:6473597d706e 6029
bogdanm 82:6473597d706e 6030 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 82:6473597d706e 6031 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 82:6473597d706e 6032 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 82:6473597d706e 6033 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 82:6473597d706e 6034 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 82:6473597d706e 6035 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 82:6473597d706e 6036 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 82:6473597d706e 6037 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 82:6473597d706e 6038 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 82:6473597d706e 6039
bogdanm 82:6473597d706e 6040 /*!< PPRE1 configuration */
bogdanm 82:6473597d706e 6041 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
bogdanm 82:6473597d706e 6042 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 82:6473597d706e 6043 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 82:6473597d706e 6044 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 82:6473597d706e 6045
bogdanm 82:6473597d706e 6046 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 82:6473597d706e 6047 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
bogdanm 82:6473597d706e 6048 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
bogdanm 82:6473597d706e 6049 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
bogdanm 82:6473597d706e 6050 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
bogdanm 82:6473597d706e 6051
bogdanm 82:6473597d706e 6052 /*!< PPRE2 configuration */
bogdanm 82:6473597d706e 6053 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
bogdanm 82:6473597d706e 6054 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
bogdanm 82:6473597d706e 6055 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
bogdanm 82:6473597d706e 6056 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
bogdanm 82:6473597d706e 6057
bogdanm 82:6473597d706e 6058 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 82:6473597d706e 6059 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
bogdanm 82:6473597d706e 6060 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
bogdanm 82:6473597d706e 6061 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
bogdanm 82:6473597d706e 6062 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
bogdanm 82:6473597d706e 6063
bogdanm 82:6473597d706e 6064 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
bogdanm 82:6473597d706e 6065
bogdanm 82:6473597d706e 6066 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
bogdanm 82:6473597d706e 6067
bogdanm 82:6473597d706e 6068 /*!< PLLMUL configuration */
bogdanm 82:6473597d706e 6069 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
bogdanm 82:6473597d706e 6070 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 82:6473597d706e 6071 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 82:6473597d706e 6072 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
bogdanm 82:6473597d706e 6073 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
bogdanm 82:6473597d706e 6074
bogdanm 82:6473597d706e 6075 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
bogdanm 82:6473597d706e 6076 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
bogdanm 82:6473597d706e 6077
bogdanm 82:6473597d706e 6078 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
bogdanm 82:6473597d706e 6079 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
bogdanm 82:6473597d706e 6080
bogdanm 82:6473597d706e 6081 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
bogdanm 82:6473597d706e 6082 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
bogdanm 82:6473597d706e 6083 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
bogdanm 82:6473597d706e 6084 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
bogdanm 82:6473597d706e 6085 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
bogdanm 82:6473597d706e 6086 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
bogdanm 82:6473597d706e 6087 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
bogdanm 82:6473597d706e 6088 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
bogdanm 82:6473597d706e 6089 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
bogdanm 82:6473597d706e 6090 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
bogdanm 82:6473597d706e 6091 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
bogdanm 82:6473597d706e 6092 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
bogdanm 82:6473597d706e 6093 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
bogdanm 82:6473597d706e 6094 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
bogdanm 82:6473597d706e 6095 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
bogdanm 82:6473597d706e 6096
bogdanm 82:6473597d706e 6097 /*!< USB configuration */
bogdanm 82:6473597d706e 6098 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
bogdanm 82:6473597d706e 6099
bogdanm 82:6473597d706e 6100 /*!< I2S configuration */
bogdanm 82:6473597d706e 6101 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
bogdanm 82:6473597d706e 6102
bogdanm 82:6473597d706e 6103 /*!< MCO configuration */
bogdanm 82:6473597d706e 6104 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
bogdanm 82:6473597d706e 6105 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 82:6473597d706e 6106 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 82:6473597d706e 6107 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 82:6473597d706e 6108
bogdanm 82:6473597d706e 6109 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 82:6473597d706e 6110 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
bogdanm 82:6473597d706e 6111 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
bogdanm 82:6473597d706e 6112 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
bogdanm 82:6473597d706e 6113 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
bogdanm 82:6473597d706e 6114 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
bogdanm 82:6473597d706e 6115 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
bogdanm 82:6473597d706e 6116
bogdanm 82:6473597d706e 6117 #define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
bogdanm 82:6473597d706e 6118
bogdanm 82:6473597d706e 6119 #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
bogdanm 82:6473597d706e 6120 #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
bogdanm 82:6473597d706e 6121 #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
bogdanm 82:6473597d706e 6122 #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
bogdanm 82:6473597d706e 6123 #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
bogdanm 82:6473597d706e 6124 #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
bogdanm 82:6473597d706e 6125 #define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
bogdanm 82:6473597d706e 6126 #define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
bogdanm 82:6473597d706e 6127 #define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
bogdanm 82:6473597d706e 6128
bogdanm 82:6473597d706e 6129 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
bogdanm 82:6473597d706e 6130
bogdanm 82:6473597d706e 6131 /********************* Bit definition for RCC_CIR register ********************/
bogdanm 82:6473597d706e 6132 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
bogdanm 82:6473597d706e 6133 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
bogdanm 82:6473597d706e 6134 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
bogdanm 82:6473597d706e 6135 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
bogdanm 82:6473597d706e 6136 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
bogdanm 82:6473597d706e 6137 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
bogdanm 82:6473597d706e 6138 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
bogdanm 82:6473597d706e 6139 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
bogdanm 82:6473597d706e 6140 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
bogdanm 82:6473597d706e 6141 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
bogdanm 82:6473597d706e 6142 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
bogdanm 82:6473597d706e 6143 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
bogdanm 82:6473597d706e 6144 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
bogdanm 82:6473597d706e 6145 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
bogdanm 82:6473597d706e 6146 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
bogdanm 82:6473597d706e 6147 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
bogdanm 82:6473597d706e 6148 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
bogdanm 82:6473597d706e 6149
bogdanm 82:6473597d706e 6150 /****************** Bit definition for RCC_APB2RSTR register *****************/
bogdanm 82:6473597d706e 6151 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
bogdanm 82:6473597d706e 6152 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) /*!< TIM1 reset */
bogdanm 82:6473597d706e 6153 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
bogdanm 82:6473597d706e 6154 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000200) /*!< TIM8 reset */
bogdanm 82:6473597d706e 6155 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
bogdanm 82:6473597d706e 6156 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
bogdanm 82:6473597d706e 6157 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
bogdanm 82:6473597d706e 6158 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
bogdanm 82:6473597d706e 6159 #define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< HRTIM1 reset */
bogdanm 82:6473597d706e 6160
bogdanm 82:6473597d706e 6161 /****************** Bit definition for RCC_APB1RSTR register ******************/
bogdanm 82:6473597d706e 6162 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
bogdanm 82:6473597d706e 6163 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
bogdanm 82:6473597d706e 6164 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
bogdanm 82:6473597d706e 6165 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
bogdanm 82:6473597d706e 6166 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
bogdanm 82:6473597d706e 6167 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
bogdanm 82:6473597d706e 6168 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
bogdanm 82:6473597d706e 6169 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
bogdanm 82:6473597d706e 6170 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
bogdanm 82:6473597d706e 6171 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
bogdanm 82:6473597d706e 6172 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
bogdanm 82:6473597d706e 6173 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
bogdanm 82:6473597d706e 6174 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
bogdanm 82:6473597d706e 6175 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
bogdanm 82:6473597d706e 6176 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
bogdanm 82:6473597d706e 6177 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN reset */
bogdanm 82:6473597d706e 6178 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
bogdanm 82:6473597d706e 6179 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
bogdanm 82:6473597d706e 6180 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
bogdanm 82:6473597d706e 6181 #define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */
bogdanm 82:6473597d706e 6182 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DAC1RST /*!< DAC reset */
bogdanm 82:6473597d706e 6183
bogdanm 82:6473597d706e 6184 /****************** Bit definition for RCC_AHBENR register ******************/
bogdanm 82:6473597d706e 6185 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
bogdanm 82:6473597d706e 6186 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
bogdanm 82:6473597d706e 6187 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
bogdanm 82:6473597d706e 6188 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
bogdanm 82:6473597d706e 6189 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
bogdanm 82:6473597d706e 6190 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
bogdanm 82:6473597d706e 6191 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
bogdanm 82:6473597d706e 6192 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
bogdanm 82:6473597d706e 6193 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
bogdanm 82:6473597d706e 6194 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
bogdanm 82:6473597d706e 6195 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
bogdanm 82:6473597d706e 6196 #define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /*!< TS clock enable */
bogdanm 82:6473597d706e 6197 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
bogdanm 82:6473597d706e 6198 #define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC1/ ADC2 clock enable */
bogdanm 82:6473597d706e 6199
bogdanm 82:6473597d706e 6200 /***************** Bit definition for RCC_APB2ENR register ******************/
bogdanm 82:6473597d706e 6201 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
bogdanm 82:6473597d706e 6202 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
bogdanm 82:6473597d706e 6203 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
bogdanm 82:6473597d706e 6204 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
bogdanm 82:6473597d706e 6205 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
bogdanm 82:6473597d706e 6206 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
bogdanm 82:6473597d706e 6207 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
bogdanm 82:6473597d706e 6208 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
bogdanm 82:6473597d706e 6209 #define RCC_APB2ENR_HRTIM1 ((uint32_t)0x20000000) /*!< HRTIM1 clock enable */
bogdanm 82:6473597d706e 6210
bogdanm 82:6473597d706e 6211 /****************** Bit definition for RCC_APB1ENR register ******************/
bogdanm 82:6473597d706e 6212 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
bogdanm 82:6473597d706e 6213 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
bogdanm 82:6473597d706e 6214 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
bogdanm 82:6473597d706e 6215 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
bogdanm 82:6473597d706e 6216 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
bogdanm 82:6473597d706e 6217 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
bogdanm 82:6473597d706e 6218 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
bogdanm 82:6473597d706e 6219 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
bogdanm 82:6473597d706e 6220 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
bogdanm 82:6473597d706e 6221 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
bogdanm 82:6473597d706e 6222 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
bogdanm 82:6473597d706e 6223 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
bogdanm 82:6473597d706e 6224 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
bogdanm 82:6473597d706e 6225 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
bogdanm 82:6473597d706e 6226 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
bogdanm 82:6473597d706e 6227 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN clock enable */
bogdanm 82:6473597d706e 6228 #define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */
bogdanm 82:6473597d706e 6229 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
bogdanm 82:6473597d706e 6230 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC clock enable */
bogdanm 82:6473597d706e 6231 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
bogdanm 82:6473597d706e 6232 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DAC1EN
bogdanm 82:6473597d706e 6233
bogdanm 82:6473597d706e 6234 /******************** Bit definition for RCC_BDCR register ******************/
bogdanm 82:6473597d706e 6235 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
bogdanm 82:6473597d706e 6236 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
bogdanm 82:6473597d706e 6237 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
bogdanm 82:6473597d706e 6238
bogdanm 82:6473597d706e 6239 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
bogdanm 82:6473597d706e 6240 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 82:6473597d706e 6241 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 82:6473597d706e 6242
bogdanm 82:6473597d706e 6243
bogdanm 82:6473597d706e 6244 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
bogdanm 82:6473597d706e 6245 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 82:6473597d706e 6246 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 82:6473597d706e 6247
bogdanm 82:6473597d706e 6248 /*!< RTC configuration */
bogdanm 82:6473597d706e 6249 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 82:6473597d706e 6250 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
bogdanm 82:6473597d706e 6251 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
bogdanm 82:6473597d706e 6252 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
bogdanm 82:6473597d706e 6253
bogdanm 82:6473597d706e 6254 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
bogdanm 82:6473597d706e 6255 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
bogdanm 82:6473597d706e 6256
bogdanm 82:6473597d706e 6257 /******************** Bit definition for RCC_CSR register *******************/
bogdanm 82:6473597d706e 6258 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
bogdanm 82:6473597d706e 6259 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
bogdanm 82:6473597d706e 6260 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
bogdanm 82:6473597d706e 6261 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
bogdanm 82:6473597d706e 6262 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
bogdanm 82:6473597d706e 6263 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
bogdanm 82:6473597d706e 6264 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
bogdanm 82:6473597d706e 6265 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
bogdanm 82:6473597d706e 6266 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
bogdanm 82:6473597d706e 6267 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
bogdanm 82:6473597d706e 6268
bogdanm 82:6473597d706e 6269 /******************* Bit definition for RCC_AHBRSTR register ****************/
bogdanm 82:6473597d706e 6270 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
bogdanm 82:6473597d706e 6271 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
bogdanm 82:6473597d706e 6272 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
bogdanm 82:6473597d706e 6273 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD reset */
bogdanm 82:6473597d706e 6274 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF reset */
bogdanm 82:6473597d706e 6275 #define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /*!< TS reset */
bogdanm 82:6473597d706e 6276 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) /*!< ADC1 & ADC2 reset */
bogdanm 82:6473597d706e 6277 #define RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) /*!< ADC3 & ADC4 reset */
bogdanm 82:6473597d706e 6278
bogdanm 82:6473597d706e 6279 /******************* Bit definition for RCC_CFGR2 register ******************/
bogdanm 82:6473597d706e 6280 /*!< PREDIV1 configuration */
bogdanm 82:6473597d706e 6281 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
bogdanm 82:6473597d706e 6282 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 82:6473597d706e 6283 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 82:6473597d706e 6284 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 82:6473597d706e 6285 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 82:6473597d706e 6286
bogdanm 82:6473597d706e 6287 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
bogdanm 82:6473597d706e 6288 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
bogdanm 82:6473597d706e 6289 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
bogdanm 82:6473597d706e 6290 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
bogdanm 82:6473597d706e 6291 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
bogdanm 82:6473597d706e 6292 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
bogdanm 82:6473597d706e 6293 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
bogdanm 82:6473597d706e 6294 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
bogdanm 82:6473597d706e 6295 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
bogdanm 82:6473597d706e 6296 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
bogdanm 82:6473597d706e 6297 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
bogdanm 82:6473597d706e 6298 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
bogdanm 82:6473597d706e 6299 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
bogdanm 82:6473597d706e 6300 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
bogdanm 82:6473597d706e 6301 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
bogdanm 82:6473597d706e 6302 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
bogdanm 82:6473597d706e 6303
bogdanm 82:6473597d706e 6304 /*!< ADCPRE12 configuration */
bogdanm 82:6473597d706e 6305 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
bogdanm 82:6473597d706e 6306 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 82:6473597d706e 6307 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 82:6473597d706e 6308 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 82:6473597d706e 6309 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 82:6473597d706e 6310 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
bogdanm 82:6473597d706e 6311
bogdanm 82:6473597d706e 6312 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
bogdanm 82:6473597d706e 6313 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
bogdanm 82:6473597d706e 6314 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
bogdanm 82:6473597d706e 6315 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
bogdanm 82:6473597d706e 6316 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
bogdanm 82:6473597d706e 6317 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
bogdanm 82:6473597d706e 6318 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
bogdanm 82:6473597d706e 6319 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
bogdanm 82:6473597d706e 6320 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
bogdanm 82:6473597d706e 6321 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
bogdanm 82:6473597d706e 6322 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
bogdanm 82:6473597d706e 6323 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
bogdanm 82:6473597d706e 6324 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
bogdanm 82:6473597d706e 6325
bogdanm 82:6473597d706e 6326 /*!< ADCPRE34 configuration */
bogdanm 82:6473597d706e 6327 #define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
bogdanm 82:6473597d706e 6328 #define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 82:6473597d706e 6329 #define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 82:6473597d706e 6330 #define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
bogdanm 82:6473597d706e 6331 #define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
bogdanm 82:6473597d706e 6332 #define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
bogdanm 82:6473597d706e 6333
bogdanm 82:6473597d706e 6334 #define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
bogdanm 82:6473597d706e 6335 #define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
bogdanm 82:6473597d706e 6336 #define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
bogdanm 82:6473597d706e 6337 #define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
bogdanm 82:6473597d706e 6338 #define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
bogdanm 82:6473597d706e 6339 #define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
bogdanm 82:6473597d706e 6340 #define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
bogdanm 82:6473597d706e 6341 #define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
bogdanm 82:6473597d706e 6342 #define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
bogdanm 82:6473597d706e 6343 #define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
bogdanm 82:6473597d706e 6344 #define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
bogdanm 82:6473597d706e 6345 #define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
bogdanm 82:6473597d706e 6346 #define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
bogdanm 82:6473597d706e 6347
bogdanm 82:6473597d706e 6348 /******************* Bit definition for RCC_CFGR3 register ******************/
bogdanm 82:6473597d706e 6349 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
bogdanm 82:6473597d706e 6350 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 82:6473597d706e 6351 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 82:6473597d706e 6352
bogdanm 82:6473597d706e 6353 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
bogdanm 82:6473597d706e 6354 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
bogdanm 82:6473597d706e 6355 #define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
bogdanm 82:6473597d706e 6356 #define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
bogdanm 82:6473597d706e 6357
bogdanm 82:6473597d706e 6358 #define RCC_CFGR3_TIMSW ((uint32_t)0x00002F00) /*!< TIMSW bits */
bogdanm 82:6473597d706e 6359 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
bogdanm 82:6473597d706e 6360 #define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
bogdanm 82:6473597d706e 6361 #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
bogdanm 82:6473597d706e 6362 #define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
bogdanm 82:6473597d706e 6363 #define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
bogdanm 82:6473597d706e 6364
bogdanm 82:6473597d706e 6365 #define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */
bogdanm 82:6473597d706e 6366
bogdanm 82:6473597d706e 6367 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
bogdanm 82:6473597d706e 6368 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 82:6473597d706e 6369 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 82:6473597d706e 6370
bogdanm 82:6473597d706e 6371 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
bogdanm 82:6473597d706e 6372 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 82:6473597d706e 6373 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 82:6473597d706e 6374
bogdanm 82:6473597d706e 6375 #define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
bogdanm 82:6473597d706e 6376 #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 82:6473597d706e 6377 #define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 82:6473597d706e 6378
bogdanm 82:6473597d706e 6379 #define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
bogdanm 82:6473597d706e 6380 #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
bogdanm 82:6473597d706e 6381 #define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
bogdanm 82:6473597d706e 6382
bogdanm 82:6473597d706e 6383 /******************************************************************************/
bogdanm 82:6473597d706e 6384 /* */
bogdanm 82:6473597d706e 6385 /* Real-Time Clock (RTC) */
bogdanm 82:6473597d706e 6386 /* */
bogdanm 82:6473597d706e 6387 /******************************************************************************/
bogdanm 82:6473597d706e 6388 /******************** Bits definition for RTC_TR register *******************/
bogdanm 82:6473597d706e 6389 #define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 6390 #define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm 82:6473597d706e 6391 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 6392 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 6393 #define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm 82:6473597d706e 6394 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 6395 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 6396 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 6397 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 6398 #define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm 82:6473597d706e 6399 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6400 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6401 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6402 #define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm 82:6473597d706e 6403 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6404 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6405 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6406 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6407 #define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm 82:6473597d706e 6408 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6409 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6410 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 6411 #define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm 82:6473597d706e 6412 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6413 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6414 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6415 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6416
bogdanm 82:6473597d706e 6417 /******************** Bits definition for RTC_DR register *******************/
bogdanm 82:6473597d706e 6418 #define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm 82:6473597d706e 6419 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 6420 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 6421 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 6422 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 6423 #define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm 82:6473597d706e 6424 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 6425 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 6426 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 6427 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 6428 #define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm 82:6473597d706e 6429 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6430 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6431 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 6432 #define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6433 #define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm 82:6473597d706e 6434 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6435 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6436 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6437 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6438 #define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm 82:6473597d706e 6439 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6440 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6441 #define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm 82:6473597d706e 6442 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6443 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6444 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6445 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6446
bogdanm 82:6473597d706e 6447 /******************** Bits definition for RTC_CR register *******************/
bogdanm 82:6473597d706e 6448 #define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 6449 #define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm 82:6473597d706e 6450 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 6451 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 6452 #define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 6453 #define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 6454 #define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 6455 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 6456 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 6457 #define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 6458 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6459 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6460 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6461 #define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6462 #define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6463 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6464 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6465 #define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 6466 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6467 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6468 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6469 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm 82:6473597d706e 6470 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6471 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6472 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6473
bogdanm 82:6473597d706e 6474 /******************** Bits definition for RTC_ISR register ******************/
bogdanm 82:6473597d706e 6475 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 6476 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 6477 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6478 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6479 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6480 #define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6481 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6482 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6483 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6484 #define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 6485 #define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 6486 #define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6487 #define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6488 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6489 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6490 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6491 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6492
bogdanm 82:6473597d706e 6493 /******************** Bits definition for RTC_PRER register *****************/
bogdanm 82:6473597d706e 6494 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm 82:6473597d706e 6495 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
bogdanm 82:6473597d706e 6496
bogdanm 82:6473597d706e 6497 /******************** Bits definition for RTC_WUTR register *****************/
bogdanm 82:6473597d706e 6498 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm 82:6473597d706e 6499
bogdanm 82:6473597d706e 6500 /******************** Bits definition for RTC_ALRMAR register ***************/
bogdanm 82:6473597d706e 6501 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm 82:6473597d706e 6502 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm 82:6473597d706e 6503 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm 82:6473597d706e 6504 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 6505 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 6506 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm 82:6473597d706e 6507 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 6508 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 6509 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 6510 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 6511 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 6512 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 6513 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm 82:6473597d706e 6514 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 6515 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 6516 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm 82:6473597d706e 6517 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 6518 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 6519 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 6520 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 6521 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 6522 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm 82:6473597d706e 6523 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6524 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6525 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6526 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm 82:6473597d706e 6527 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6528 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6529 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6530 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6531 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 6532 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm 82:6473597d706e 6533 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6534 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6535 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 6536 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm 82:6473597d706e 6537 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6538 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6539 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6540 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6541
bogdanm 82:6473597d706e 6542 /******************** Bits definition for RTC_ALRMBR register ***************/
bogdanm 82:6473597d706e 6543 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm 82:6473597d706e 6544 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm 82:6473597d706e 6545 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm 82:6473597d706e 6546 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 6547 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 6548 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm 82:6473597d706e 6549 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 6550 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 6551 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 6552 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 6553 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm 82:6473597d706e 6554 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 6555 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm 82:6473597d706e 6556 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 6557 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 6558 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm 82:6473597d706e 6559 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 6560 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 6561 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 6562 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 6563 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 6564 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm 82:6473597d706e 6565 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6566 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6567 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6568 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm 82:6473597d706e 6569 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6570 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6571 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6572 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6573 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 6574 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm 82:6473597d706e 6575 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6576 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6577 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 6578 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm 82:6473597d706e 6579 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6580 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6581 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6582 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6583
bogdanm 82:6473597d706e 6584 /******************** Bits definition for RTC_WPR register ******************/
bogdanm 82:6473597d706e 6585 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm 82:6473597d706e 6586
bogdanm 82:6473597d706e 6587 /******************** Bits definition for RTC_SSR register ******************/
bogdanm 82:6473597d706e 6588 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm 82:6473597d706e 6589
bogdanm 82:6473597d706e 6590 /******************** Bits definition for RTC_SHIFTR register ***************/
bogdanm 82:6473597d706e 6591 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm 82:6473597d706e 6592 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm 82:6473597d706e 6593
bogdanm 82:6473597d706e 6594 /******************** Bits definition for RTC_TSTR register *****************/
bogdanm 82:6473597d706e 6595 #define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm 82:6473597d706e 6596 #define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm 82:6473597d706e 6597 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm 82:6473597d706e 6598 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm 82:6473597d706e 6599 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm 82:6473597d706e 6600 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm 82:6473597d706e 6601 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm 82:6473597d706e 6602 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 6603 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm 82:6473597d706e 6604 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm 82:6473597d706e 6605 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6606 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6607 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6608 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm 82:6473597d706e 6609 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6610 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6611 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6612 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6613 #define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm 82:6473597d706e 6614 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6615 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6616 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 6617 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm 82:6473597d706e 6618 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6619 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6620 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6621 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6622
bogdanm 82:6473597d706e 6623 /******************** Bits definition for RTC_TSDR register *****************/
bogdanm 82:6473597d706e 6624 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm 82:6473597d706e 6625 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6626 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6627 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 6628 #define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6629 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm 82:6473597d706e 6630 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6631 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6632 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6633 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6634 #define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm 82:6473597d706e 6635 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6636 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6637 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm 82:6473597d706e 6638 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6639 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6640 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6641 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6642
bogdanm 82:6473597d706e 6643 /******************** Bits definition for RTC_TSSSR register ****************/
bogdanm 82:6473597d706e 6644 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm 82:6473597d706e 6645
bogdanm 82:6473597d706e 6646 /******************** Bits definition for RTC_CAL register *****************/
bogdanm 82:6473597d706e 6647 #define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 6648 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6649 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6650 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm 82:6473597d706e 6651 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6652 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6653 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6654 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6655 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6656 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6657 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 6658 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 6659 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6660
bogdanm 82:6473597d706e 6661 /******************** Bits definition for RTC_TAFCR register ****************/
bogdanm 82:6473597d706e 6662 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm 82:6473597d706e 6663 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm 82:6473597d706e 6664 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm 82:6473597d706e 6665 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm 82:6473597d706e 6666 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm 82:6473597d706e 6667 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm 82:6473597d706e 6668 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm 82:6473597d706e 6669 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm 82:6473597d706e 6670 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm 82:6473597d706e 6671 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 6672 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm 82:6473597d706e 6673 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 6674 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm 82:6473597d706e 6675 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
bogdanm 82:6473597d706e 6676 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
bogdanm 82:6473597d706e 6677 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm 82:6473597d706e 6678 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm 82:6473597d706e 6679 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm 82:6473597d706e 6680 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm 82:6473597d706e 6681 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm 82:6473597d706e 6682
bogdanm 82:6473597d706e 6683 /******************** Bits definition for RTC_ALRMASSR register *************/
bogdanm 82:6473597d706e 6684 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 82:6473597d706e 6685 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 6686 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 6687 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 6688 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 6689 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm 82:6473597d706e 6690
bogdanm 82:6473597d706e 6691 /******************** Bits definition for RTC_ALRMBSSR register *************/
bogdanm 82:6473597d706e 6692 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 82:6473597d706e 6693 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 82:6473597d706e 6694 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 82:6473597d706e 6695 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 82:6473597d706e 6696 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 82:6473597d706e 6697 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm 82:6473597d706e 6698
bogdanm 82:6473597d706e 6699 /******************** Bits definition for RTC_BKP0R register ****************/
bogdanm 82:6473597d706e 6700 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6701
bogdanm 82:6473597d706e 6702 /******************** Bits definition for RTC_BKP1R register ****************/
bogdanm 82:6473597d706e 6703 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6704
bogdanm 82:6473597d706e 6705 /******************** Bits definition for RTC_BKP2R register ****************/
bogdanm 82:6473597d706e 6706 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6707
bogdanm 82:6473597d706e 6708 /******************** Bits definition for RTC_BKP3R register ****************/
bogdanm 82:6473597d706e 6709 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6710
bogdanm 82:6473597d706e 6711 /******************** Bits definition for RTC_BKP4R register ****************/
bogdanm 82:6473597d706e 6712 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6713
bogdanm 82:6473597d706e 6714 /******************** Bits definition for RTC_BKP5R register ****************/
bogdanm 82:6473597d706e 6715 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6716
bogdanm 82:6473597d706e 6717 /******************** Bits definition for RTC_BKP6R register ****************/
bogdanm 82:6473597d706e 6718 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6719
bogdanm 82:6473597d706e 6720 /******************** Bits definition for RTC_BKP7R register ****************/
bogdanm 82:6473597d706e 6721 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6722
bogdanm 82:6473597d706e 6723 /******************** Bits definition for RTC_BKP8R register ****************/
bogdanm 82:6473597d706e 6724 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6725
bogdanm 82:6473597d706e 6726 /******************** Bits definition for RTC_BKP9R register ****************/
bogdanm 82:6473597d706e 6727 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6728
bogdanm 82:6473597d706e 6729 /******************** Bits definition for RTC_BKP10R register ***************/
bogdanm 82:6473597d706e 6730 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6731
bogdanm 82:6473597d706e 6732 /******************** Bits definition for RTC_BKP11R register ***************/
bogdanm 82:6473597d706e 6733 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6734
bogdanm 82:6473597d706e 6735 /******************** Bits definition for RTC_BKP12R register ***************/
bogdanm 82:6473597d706e 6736 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6737
bogdanm 82:6473597d706e 6738 /******************** Bits definition for RTC_BKP13R register ***************/
bogdanm 82:6473597d706e 6739 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6740
bogdanm 82:6473597d706e 6741 /******************** Bits definition for RTC_BKP14R register ***************/
bogdanm 82:6473597d706e 6742 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6743
bogdanm 82:6473597d706e 6744 /******************** Bits definition for RTC_BKP15R register ***************/
bogdanm 82:6473597d706e 6745 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm 82:6473597d706e 6746
bogdanm 82:6473597d706e 6747 /******************************************************************************/
bogdanm 82:6473597d706e 6748 /* */
bogdanm 82:6473597d706e 6749 /* Serial Peripheral Interface (SPI) */
bogdanm 82:6473597d706e 6750 /* */
bogdanm 82:6473597d706e 6751 /******************************************************************************/
bogdanm 82:6473597d706e 6752 /******************* Bit definition for SPI_CR1 register ********************/
bogdanm 82:6473597d706e 6753 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
bogdanm 82:6473597d706e 6754 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
bogdanm 82:6473597d706e 6755 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
bogdanm 82:6473597d706e 6756
bogdanm 82:6473597d706e 6757 #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
bogdanm 82:6473597d706e 6758 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
bogdanm 82:6473597d706e 6759 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
bogdanm 82:6473597d706e 6760 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
bogdanm 82:6473597d706e 6761
bogdanm 82:6473597d706e 6762 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
bogdanm 82:6473597d706e 6763 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
bogdanm 82:6473597d706e 6764 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
bogdanm 82:6473597d706e 6765 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
bogdanm 82:6473597d706e 6766 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
bogdanm 82:6473597d706e 6767 #define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */
bogdanm 82:6473597d706e 6768 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
bogdanm 82:6473597d706e 6769 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
bogdanm 82:6473597d706e 6770 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
bogdanm 82:6473597d706e 6771 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
bogdanm 82:6473597d706e 6772
bogdanm 82:6473597d706e 6773 /******************* Bit definition for SPI_CR2 register ********************/
bogdanm 82:6473597d706e 6774 #define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */
bogdanm 82:6473597d706e 6775 #define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */
bogdanm 82:6473597d706e 6776 #define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */
bogdanm 82:6473597d706e 6777 #define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */
bogdanm 82:6473597d706e 6778 #define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */
bogdanm 82:6473597d706e 6779 #define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */
bogdanm 82:6473597d706e 6780 #define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */
bogdanm 82:6473597d706e 6781 #define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */
bogdanm 82:6473597d706e 6782
bogdanm 82:6473597d706e 6783 #define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */
bogdanm 82:6473597d706e 6784 #define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */
bogdanm 82:6473597d706e 6785 #define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */
bogdanm 82:6473597d706e 6786 #define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */
bogdanm 82:6473597d706e 6787 #define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */
bogdanm 82:6473597d706e 6788
bogdanm 82:6473597d706e 6789 #define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */
bogdanm 82:6473597d706e 6790 #define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */
bogdanm 82:6473597d706e 6791 #define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */
bogdanm 82:6473597d706e 6792
bogdanm 82:6473597d706e 6793 /******************** Bit definition for SPI_SR register ********************/
bogdanm 82:6473597d706e 6794 #define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */
bogdanm 82:6473597d706e 6795 #define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */
bogdanm 82:6473597d706e 6796 #define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */
bogdanm 82:6473597d706e 6797 #define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */
bogdanm 82:6473597d706e 6798 #define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */
bogdanm 82:6473597d706e 6799 #define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */
bogdanm 82:6473597d706e 6800 #define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */
bogdanm 82:6473597d706e 6801 #define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */
bogdanm 82:6473597d706e 6802 #define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */
bogdanm 82:6473597d706e 6803 #define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */
bogdanm 82:6473597d706e 6804 #define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */
bogdanm 82:6473597d706e 6805 #define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */
bogdanm 82:6473597d706e 6806 #define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */
bogdanm 82:6473597d706e 6807
bogdanm 82:6473597d706e 6808 /******************** Bit definition for SPI_DR register ********************/
bogdanm 82:6473597d706e 6809 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
bogdanm 82:6473597d706e 6810
bogdanm 82:6473597d706e 6811 /******************* Bit definition for SPI_CRCPR register ******************/
bogdanm 82:6473597d706e 6812 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
bogdanm 82:6473597d706e 6813
bogdanm 82:6473597d706e 6814 /****************** Bit definition for SPI_RXCRCR register ******************/
bogdanm 82:6473597d706e 6815 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
bogdanm 82:6473597d706e 6816
bogdanm 82:6473597d706e 6817 /****************** Bit definition for SPI_TXCRCR register ******************/
bogdanm 82:6473597d706e 6818 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
bogdanm 82:6473597d706e 6819
bogdanm 82:6473597d706e 6820 /****************** Bit definition for SPI_I2SCFGR register *****************/
bogdanm 82:6473597d706e 6821 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
bogdanm 82:6473597d706e 6822
bogdanm 82:6473597d706e 6823 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
bogdanm 82:6473597d706e 6824 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
bogdanm 82:6473597d706e 6825 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
bogdanm 82:6473597d706e 6826
bogdanm 82:6473597d706e 6827 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
bogdanm 82:6473597d706e 6828
bogdanm 82:6473597d706e 6829 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
bogdanm 82:6473597d706e 6830 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 82:6473597d706e 6831 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 82:6473597d706e 6832
bogdanm 82:6473597d706e 6833 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
bogdanm 82:6473597d706e 6834
bogdanm 82:6473597d706e 6835 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
bogdanm 82:6473597d706e 6836 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 82:6473597d706e 6837 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 82:6473597d706e 6838
bogdanm 82:6473597d706e 6839 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
bogdanm 82:6473597d706e 6840 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
bogdanm 82:6473597d706e 6841
bogdanm 82:6473597d706e 6842 /****************** Bit definition for SPI_I2SPR register *******************/
bogdanm 82:6473597d706e 6843 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
bogdanm 82:6473597d706e 6844 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
bogdanm 82:6473597d706e 6845 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
bogdanm 82:6473597d706e 6846
bogdanm 82:6473597d706e 6847 /******************************************************************************/
bogdanm 82:6473597d706e 6848 /* */
bogdanm 82:6473597d706e 6849 /* System Configuration(SYSCFG) */
bogdanm 82:6473597d706e 6850 /* */
bogdanm 82:6473597d706e 6851 /******************************************************************************/
bogdanm 82:6473597d706e 6852 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
bogdanm 82:6473597d706e 6853 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
bogdanm 82:6473597d706e 6854 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 82:6473597d706e 6855 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 82:6473597d706e 6856 #define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
bogdanm 82:6473597d706e 6857 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
bogdanm 82:6473597d706e 6858 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
bogdanm 82:6473597d706e 6859 #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
bogdanm 82:6473597d706e 6860 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
bogdanm 82:6473597d706e 6861 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
bogdanm 82:6473597d706e 6862 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
bogdanm 82:6473597d706e 6863 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
bogdanm 82:6473597d706e 6864 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
bogdanm 82:6473597d706e 6865 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
bogdanm 82:6473597d706e 6866 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
bogdanm 82:6473597d706e 6867 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
bogdanm 82:6473597d706e 6868 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
bogdanm 82:6473597d706e 6869 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
bogdanm 82:6473597d706e 6870 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
bogdanm 82:6473597d706e 6871 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
bogdanm 82:6473597d706e 6872 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
bogdanm 82:6473597d706e 6873 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
bogdanm 82:6473597d706e 6874 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
bogdanm 82:6473597d706e 6875 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
bogdanm 82:6473597d706e 6876 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
bogdanm 82:6473597d706e 6877 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
bogdanm 82:6473597d706e 6878 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
bogdanm 82:6473597d706e 6879 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
bogdanm 82:6473597d706e 6880 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
bogdanm 82:6473597d706e 6881 #define SYSCFG_CFGR1_DAC_TRIG_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Old define maintained for legacy purpose */
bogdanm 82:6473597d706e 6882 #define SYSCFG_CFGR1_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /*!< Old define maintained for legacy purpose */
bogdanm 82:6473597d706e 6883 #define SYSCFG_CFGR1_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /*!< Old define maintained for legacy purpose */
bogdanm 82:6473597d706e 6884 /***************** Bit definition for SYSCFG_RCR register *******************/
bogdanm 82:6473597d706e 6885 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
bogdanm 82:6473597d706e 6886 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
bogdanm 82:6473597d706e 6887 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
bogdanm 82:6473597d706e 6888 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
bogdanm 82:6473597d706e 6889 #define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
bogdanm 82:6473597d706e 6890 #define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
bogdanm 82:6473597d706e 6891 #define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
bogdanm 82:6473597d706e 6892 #define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
bogdanm 82:6473597d706e 6893
bogdanm 82:6473597d706e 6894 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
bogdanm 82:6473597d706e 6895 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
bogdanm 82:6473597d706e 6896 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
bogdanm 82:6473597d706e 6897 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
bogdanm 82:6473597d706e 6898 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
bogdanm 82:6473597d706e 6899
bogdanm 82:6473597d706e 6900 /**
bogdanm 82:6473597d706e 6901 * @brief EXTI0 configuration
bogdanm 82:6473597d706e 6902 */
bogdanm 82:6473597d706e 6903 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
bogdanm 82:6473597d706e 6904 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
bogdanm 82:6473597d706e 6905 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
bogdanm 82:6473597d706e 6906 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
bogdanm 82:6473597d706e 6907 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
bogdanm 82:6473597d706e 6908 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
bogdanm 82:6473597d706e 6909
bogdanm 82:6473597d706e 6910 /**
bogdanm 82:6473597d706e 6911 * @brief EXTI1 configuration
bogdanm 82:6473597d706e 6912 */
bogdanm 82:6473597d706e 6913 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
bogdanm 82:6473597d706e 6914 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
bogdanm 82:6473597d706e 6915 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
bogdanm 82:6473597d706e 6916 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
bogdanm 82:6473597d706e 6917 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
bogdanm 82:6473597d706e 6918 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
bogdanm 82:6473597d706e 6919
bogdanm 82:6473597d706e 6920 /**
bogdanm 82:6473597d706e 6921 * @brief EXTI2 configuration
bogdanm 82:6473597d706e 6922 */
bogdanm 82:6473597d706e 6923 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
bogdanm 82:6473597d706e 6924 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
bogdanm 82:6473597d706e 6925 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
bogdanm 82:6473597d706e 6926 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
bogdanm 82:6473597d706e 6927 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
bogdanm 82:6473597d706e 6928 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
bogdanm 82:6473597d706e 6929
bogdanm 82:6473597d706e 6930 /**
bogdanm 82:6473597d706e 6931 * @brief EXTI3 configuration
bogdanm 82:6473597d706e 6932 */
bogdanm 82:6473597d706e 6933 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
bogdanm 82:6473597d706e 6934 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
bogdanm 82:6473597d706e 6935 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
bogdanm 82:6473597d706e 6936 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
bogdanm 82:6473597d706e 6937 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
bogdanm 82:6473597d706e 6938
bogdanm 82:6473597d706e 6939 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
bogdanm 82:6473597d706e 6940 #define SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
bogdanm 82:6473597d706e 6941 #define SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
bogdanm 82:6473597d706e 6942 #define SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
bogdanm 82:6473597d706e 6943 #define SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
bogdanm 82:6473597d706e 6944
bogdanm 82:6473597d706e 6945 /**
bogdanm 82:6473597d706e 6946 * @brief EXTI4 configuration
bogdanm 82:6473597d706e 6947 */
bogdanm 82:6473597d706e 6948 #define SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
bogdanm 82:6473597d706e 6949 #define SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
bogdanm 82:6473597d706e 6950 #define SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
bogdanm 82:6473597d706e 6951 #define SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
bogdanm 82:6473597d706e 6952 #define SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
bogdanm 82:6473597d706e 6953 #define SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
bogdanm 82:6473597d706e 6954
bogdanm 82:6473597d706e 6955 /**
bogdanm 82:6473597d706e 6956 * @brief EXTI5 configuration
bogdanm 82:6473597d706e 6957 */
bogdanm 82:6473597d706e 6958 #define SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
bogdanm 82:6473597d706e 6959 #define SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
bogdanm 82:6473597d706e 6960 #define SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
bogdanm 82:6473597d706e 6961 #define SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
bogdanm 82:6473597d706e 6962 #define SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
bogdanm 82:6473597d706e 6963 #define SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
bogdanm 82:6473597d706e 6964
bogdanm 82:6473597d706e 6965 /**
bogdanm 82:6473597d706e 6966 * @brief EXTI6 configuration
bogdanm 82:6473597d706e 6967 */
bogdanm 82:6473597d706e 6968 #define SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
bogdanm 82:6473597d706e 6969 #define SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
bogdanm 82:6473597d706e 6970 #define SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
bogdanm 82:6473597d706e 6971 #define SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
bogdanm 82:6473597d706e 6972 #define SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
bogdanm 82:6473597d706e 6973 #define SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
bogdanm 82:6473597d706e 6974
bogdanm 82:6473597d706e 6975 /**
bogdanm 82:6473597d706e 6976 * @brief EXTI7 configuration
bogdanm 82:6473597d706e 6977 */
bogdanm 82:6473597d706e 6978 #define SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
bogdanm 82:6473597d706e 6979 #define SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
bogdanm 82:6473597d706e 6980 #define SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
bogdanm 82:6473597d706e 6981 #define SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
bogdanm 82:6473597d706e 6982 #define SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
bogdanm 82:6473597d706e 6983
bogdanm 82:6473597d706e 6984 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
bogdanm 82:6473597d706e 6985 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
bogdanm 82:6473597d706e 6986 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
bogdanm 82:6473597d706e 6987 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
bogdanm 82:6473597d706e 6988 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
bogdanm 82:6473597d706e 6989
bogdanm 82:6473597d706e 6990 /**
bogdanm 82:6473597d706e 6991 * @brief EXTI8 configuration
bogdanm 82:6473597d706e 6992 */
bogdanm 82:6473597d706e 6993 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
bogdanm 82:6473597d706e 6994 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
bogdanm 82:6473597d706e 6995 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
bogdanm 82:6473597d706e 6996 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
bogdanm 82:6473597d706e 6997 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
bogdanm 82:6473597d706e 6998
bogdanm 82:6473597d706e 6999 /**
bogdanm 82:6473597d706e 7000 * @brief EXTI9 configuration
bogdanm 82:6473597d706e 7001 */
bogdanm 82:6473597d706e 7002 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
bogdanm 82:6473597d706e 7003 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
bogdanm 82:6473597d706e 7004 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
bogdanm 82:6473597d706e 7005 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
bogdanm 82:6473597d706e 7006 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
bogdanm 82:6473597d706e 7007 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
bogdanm 82:6473597d706e 7008
bogdanm 82:6473597d706e 7009 /**
bogdanm 82:6473597d706e 7010 * @brief EXTI10 configuration
bogdanm 82:6473597d706e 7011 */
bogdanm 82:6473597d706e 7012 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
bogdanm 82:6473597d706e 7013 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
bogdanm 82:6473597d706e 7014 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
bogdanm 82:6473597d706e 7015 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
bogdanm 82:6473597d706e 7016 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
bogdanm 82:6473597d706e 7017 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
bogdanm 82:6473597d706e 7018
bogdanm 82:6473597d706e 7019 /**
bogdanm 82:6473597d706e 7020 * @brief EXTI11 configuration
bogdanm 82:6473597d706e 7021 */
bogdanm 82:6473597d706e 7022 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
bogdanm 82:6473597d706e 7023 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
bogdanm 82:6473597d706e 7024 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
bogdanm 82:6473597d706e 7025 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
bogdanm 82:6473597d706e 7026 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
bogdanm 82:6473597d706e 7027
bogdanm 82:6473597d706e 7028 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
bogdanm 82:6473597d706e 7029 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
bogdanm 82:6473597d706e 7030 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
bogdanm 82:6473597d706e 7031 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
bogdanm 82:6473597d706e 7032 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
bogdanm 82:6473597d706e 7033
bogdanm 82:6473597d706e 7034 /**
bogdanm 82:6473597d706e 7035 * @brief EXTI12 configuration
bogdanm 82:6473597d706e 7036 */
bogdanm 82:6473597d706e 7037 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
bogdanm 82:6473597d706e 7038 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
bogdanm 82:6473597d706e 7039 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
bogdanm 82:6473597d706e 7040 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
bogdanm 82:6473597d706e 7041 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
bogdanm 82:6473597d706e 7042
bogdanm 82:6473597d706e 7043 /**
bogdanm 82:6473597d706e 7044 * @brief EXTI13 configuration
bogdanm 82:6473597d706e 7045 */
bogdanm 82:6473597d706e 7046 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
bogdanm 82:6473597d706e 7047 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
bogdanm 82:6473597d706e 7048 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
bogdanm 82:6473597d706e 7049 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
bogdanm 82:6473597d706e 7050 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
bogdanm 82:6473597d706e 7051
bogdanm 82:6473597d706e 7052 /**
bogdanm 82:6473597d706e 7053 * @brief EXTI14 configuration
bogdanm 82:6473597d706e 7054 */
bogdanm 82:6473597d706e 7055 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
bogdanm 82:6473597d706e 7056 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
bogdanm 82:6473597d706e 7057 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
bogdanm 82:6473597d706e 7058 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
bogdanm 82:6473597d706e 7059 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
bogdanm 82:6473597d706e 7060
bogdanm 82:6473597d706e 7061 /**
bogdanm 82:6473597d706e 7062 * @brief EXTI15 configuration
bogdanm 82:6473597d706e 7063 */
bogdanm 82:6473597d706e 7064 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
bogdanm 82:6473597d706e 7065 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
bogdanm 82:6473597d706e 7066 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
bogdanm 82:6473597d706e 7067 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
bogdanm 82:6473597d706e 7068 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
bogdanm 82:6473597d706e 7069
bogdanm 82:6473597d706e 7070 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
bogdanm 82:6473597d706e 7071 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
bogdanm 82:6473597d706e 7072 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 */
bogdanm 82:6473597d706e 7073 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 */
bogdanm 82:6473597d706e 7074 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the address parity check on RAM */
bogdanm 82:6473597d706e 7075 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
bogdanm 82:6473597d706e 7076
bogdanm 82:6473597d706e 7077 /***************** Bit definition for SYSCFG_CFGR3 register *****************/
bogdanm 82:6473597d706e 7078 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */
bogdanm 82:6473597d706e 7079 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */
bogdanm 82:6473597d706e 7080 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */
bogdanm 82:6473597d706e 7081 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */
bogdanm 82:6473597d706e 7082 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */
bogdanm 82:6473597d706e 7083 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */
bogdanm 82:6473597d706e 7084 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */
bogdanm 82:6473597d706e 7085 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */
bogdanm 82:6473597d706e 7086 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */
bogdanm 82:6473597d706e 7087 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */
bogdanm 82:6473597d706e 7088 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */
bogdanm 82:6473597d706e 7089 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */
bogdanm 82:6473597d706e 7090 #define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */
bogdanm 82:6473597d706e 7091 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */
bogdanm 82:6473597d706e 7092 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */
bogdanm 82:6473597d706e 7093 #define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /*!< DAC1 TRG3 remap */
bogdanm 82:6473597d706e 7094 #define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /*!< DAC1 TRG5 remap */
bogdanm 82:6473597d706e 7095
bogdanm 82:6473597d706e 7096 /******************************************************************************/
bogdanm 82:6473597d706e 7097 /* */
bogdanm 82:6473597d706e 7098 /* TIM */
bogdanm 82:6473597d706e 7099 /* */
bogdanm 82:6473597d706e 7100 /******************************************************************************/
bogdanm 82:6473597d706e 7101 /******************* Bit definition for TIM_CR1 register ********************/
bogdanm 82:6473597d706e 7102 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
bogdanm 82:6473597d706e 7103 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
bogdanm 82:6473597d706e 7104 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
bogdanm 82:6473597d706e 7105 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
bogdanm 82:6473597d706e 7106 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
bogdanm 82:6473597d706e 7107
bogdanm 82:6473597d706e 7108 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 82:6473597d706e 7109 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
bogdanm 82:6473597d706e 7110 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
bogdanm 82:6473597d706e 7111
bogdanm 82:6473597d706e 7112 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
bogdanm 82:6473597d706e 7113
bogdanm 82:6473597d706e 7114 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
bogdanm 82:6473597d706e 7115 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 82:6473597d706e 7116 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 82:6473597d706e 7117
bogdanm 82:6473597d706e 7118 #define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */
bogdanm 82:6473597d706e 7119
bogdanm 82:6473597d706e 7120 /******************* Bit definition for TIM_CR2 register ********************/
bogdanm 82:6473597d706e 7121 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
bogdanm 82:6473597d706e 7122 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
bogdanm 82:6473597d706e 7123 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
bogdanm 82:6473597d706e 7124
bogdanm 82:6473597d706e 7125 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 82:6473597d706e 7126 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 82:6473597d706e 7127 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 82:6473597d706e 7128 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 82:6473597d706e 7129
bogdanm 82:6473597d706e 7130 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
bogdanm 82:6473597d706e 7131 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
bogdanm 82:6473597d706e 7132 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
bogdanm 82:6473597d706e 7133 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
bogdanm 82:6473597d706e 7134 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
bogdanm 82:6473597d706e 7135 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
bogdanm 82:6473597d706e 7136 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
bogdanm 82:6473597d706e 7137 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 82:6473597d706e 7138 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 82:6473597d706e 7139 #define TIM_CR2_OIS6 ((uint32_t)0x00020000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 82:6473597d706e 7140
bogdanm 82:6473597d706e 7141 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 82:6473597d706e 7142 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 82:6473597d706e 7143 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 82:6473597d706e 7144 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 82:6473597d706e 7145 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 82:6473597d706e 7146
bogdanm 82:6473597d706e 7147 /******************* Bit definition for TIM_SMCR register *******************/
bogdanm 82:6473597d706e 7148 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
bogdanm 82:6473597d706e 7149 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 82:6473597d706e 7150 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 82:6473597d706e 7151 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 82:6473597d706e 7152 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7153
bogdanm 82:6473597d706e 7154 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
bogdanm 82:6473597d706e 7155
bogdanm 82:6473597d706e 7156 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
bogdanm 82:6473597d706e 7157 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 82:6473597d706e 7158 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 82:6473597d706e 7159 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 82:6473597d706e 7160
bogdanm 82:6473597d706e 7161 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
bogdanm 82:6473597d706e 7162
bogdanm 82:6473597d706e 7163 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
bogdanm 82:6473597d706e 7164 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 82:6473597d706e 7165 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 82:6473597d706e 7166 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 82:6473597d706e 7167 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 82:6473597d706e 7168
bogdanm 82:6473597d706e 7169 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
bogdanm 82:6473597d706e 7170 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 82:6473597d706e 7171 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 82:6473597d706e 7172
bogdanm 82:6473597d706e 7173 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
bogdanm 82:6473597d706e 7174 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
bogdanm 82:6473597d706e 7175
bogdanm 82:6473597d706e 7176 /******************* Bit definition for TIM_DIER register *******************/
bogdanm 82:6473597d706e 7177 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
bogdanm 82:6473597d706e 7178 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
bogdanm 82:6473597d706e 7179 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
bogdanm 82:6473597d706e 7180 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
bogdanm 82:6473597d706e 7181 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
bogdanm 82:6473597d706e 7182 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
bogdanm 82:6473597d706e 7183 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
bogdanm 82:6473597d706e 7184 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
bogdanm 82:6473597d706e 7185 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
bogdanm 82:6473597d706e 7186 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
bogdanm 82:6473597d706e 7187 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
bogdanm 82:6473597d706e 7188 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
bogdanm 82:6473597d706e 7189 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
bogdanm 82:6473597d706e 7190 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
bogdanm 82:6473597d706e 7191 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
bogdanm 82:6473597d706e 7192
bogdanm 82:6473597d706e 7193 /******************** Bit definition for TIM_SR register ********************/
bogdanm 82:6473597d706e 7194 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
bogdanm 82:6473597d706e 7195 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
bogdanm 82:6473597d706e 7196 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
bogdanm 82:6473597d706e 7197 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
bogdanm 82:6473597d706e 7198 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
bogdanm 82:6473597d706e 7199 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
bogdanm 82:6473597d706e 7200 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
bogdanm 82:6473597d706e 7201 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
bogdanm 82:6473597d706e 7202 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
bogdanm 82:6473597d706e 7203 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Over capture Flag */
bogdanm 82:6473597d706e 7204 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Over capture Flag */
bogdanm 82:6473597d706e 7205 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Over capture Flag */
bogdanm 82:6473597d706e 7206 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Over capture Flag */
bogdanm 82:6473597d706e 7207 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
bogdanm 82:6473597d706e 7208 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
bogdanm 82:6473597d706e 7209
bogdanm 82:6473597d706e 7210
bogdanm 82:6473597d706e 7211 /******************* Bit definition for TIM_EGR register ********************/
bogdanm 82:6473597d706e 7212 #define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */
bogdanm 82:6473597d706e 7213 #define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */
bogdanm 82:6473597d706e 7214 #define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */
bogdanm 82:6473597d706e 7215 #define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */
bogdanm 82:6473597d706e 7216 #define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */
bogdanm 82:6473597d706e 7217 #define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */
bogdanm 82:6473597d706e 7218 #define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */
bogdanm 82:6473597d706e 7219 #define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */
bogdanm 82:6473597d706e 7220 #define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */
bogdanm 82:6473597d706e 7221
bogdanm 82:6473597d706e 7222
bogdanm 82:6473597d706e 7223 /****************** Bit definition for TIM_CCMR1 register *******************/
bogdanm 82:6473597d706e 7224 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 82:6473597d706e 7225 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 82:6473597d706e 7226 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 82:6473597d706e 7227
bogdanm 82:6473597d706e 7228 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
bogdanm 82:6473597d706e 7229 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
bogdanm 82:6473597d706e 7230
bogdanm 82:6473597d706e 7231 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 82:6473597d706e 7232 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 82:6473597d706e 7233 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 82:6473597d706e 7234 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 82:6473597d706e 7235 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7236
bogdanm 82:6473597d706e 7237 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
bogdanm 82:6473597d706e 7238
bogdanm 82:6473597d706e 7239 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 82:6473597d706e 7240 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 82:6473597d706e 7241 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 82:6473597d706e 7242
bogdanm 82:6473597d706e 7243 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
bogdanm 82:6473597d706e 7244 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
bogdanm 82:6473597d706e 7245
bogdanm 82:6473597d706e 7246 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 82:6473597d706e 7247 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 82:6473597d706e 7248 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 82:6473597d706e 7249 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 82:6473597d706e 7250 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7251
bogdanm 82:6473597d706e 7252 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
bogdanm 82:6473597d706e 7253
bogdanm 82:6473597d706e 7254 /*----------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 7255
bogdanm 82:6473597d706e 7256 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 82:6473597d706e 7257 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 82:6473597d706e 7258 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 82:6473597d706e 7259
bogdanm 82:6473597d706e 7260 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 82:6473597d706e 7261 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 82:6473597d706e 7262 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 82:6473597d706e 7263 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 82:6473597d706e 7264 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 82:6473597d706e 7265
bogdanm 82:6473597d706e 7266 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 82:6473597d706e 7267 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 82:6473597d706e 7268 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 82:6473597d706e 7269
bogdanm 82:6473597d706e 7270 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 82:6473597d706e 7271 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 82:6473597d706e 7272 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 82:6473597d706e 7273 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 82:6473597d706e 7274 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7275
bogdanm 82:6473597d706e 7276 /****************** Bit definition for TIM_CCMR2 register *******************/
bogdanm 82:6473597d706e 7277 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 82:6473597d706e 7278 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 82:6473597d706e 7279 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 82:6473597d706e 7280
bogdanm 82:6473597d706e 7281 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
bogdanm 82:6473597d706e 7282 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
bogdanm 82:6473597d706e 7283
bogdanm 82:6473597d706e 7284 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 82:6473597d706e 7285 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 82:6473597d706e 7286 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 82:6473597d706e 7287 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 82:6473597d706e 7288 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7289
bogdanm 82:6473597d706e 7290 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
bogdanm 82:6473597d706e 7291
bogdanm 82:6473597d706e 7292 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 82:6473597d706e 7293 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 82:6473597d706e 7294 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 82:6473597d706e 7295
bogdanm 82:6473597d706e 7296 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
bogdanm 82:6473597d706e 7297 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
bogdanm 82:6473597d706e 7298
bogdanm 82:6473597d706e 7299 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 82:6473597d706e 7300 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 82:6473597d706e 7301 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 82:6473597d706e 7302 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 82:6473597d706e 7303 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7304
bogdanm 82:6473597d706e 7305 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
bogdanm 82:6473597d706e 7306
bogdanm 82:6473597d706e 7307 /*----------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 7308
bogdanm 82:6473597d706e 7309 #define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 82:6473597d706e 7310 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */
bogdanm 82:6473597d706e 7311 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */
bogdanm 82:6473597d706e 7312
bogdanm 82:6473597d706e 7313 #define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 82:6473597d706e 7314 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */
bogdanm 82:6473597d706e 7315 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */
bogdanm 82:6473597d706e 7316 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */
bogdanm 82:6473597d706e 7317 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */
bogdanm 82:6473597d706e 7318
bogdanm 82:6473597d706e 7319 #define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 82:6473597d706e 7320 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */
bogdanm 82:6473597d706e 7321 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */
bogdanm 82:6473597d706e 7322
bogdanm 82:6473597d706e 7323 #define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 82:6473597d706e 7324 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */
bogdanm 82:6473597d706e 7325 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */
bogdanm 82:6473597d706e 7326 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */
bogdanm 82:6473597d706e 7327 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7328
bogdanm 82:6473597d706e 7329 /******************* Bit definition for TIM_CCER register *******************/
bogdanm 82:6473597d706e 7330 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
bogdanm 82:6473597d706e 7331 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
bogdanm 82:6473597d706e 7332 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
bogdanm 82:6473597d706e 7333 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
bogdanm 82:6473597d706e 7334 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
bogdanm 82:6473597d706e 7335 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
bogdanm 82:6473597d706e 7336 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
bogdanm 82:6473597d706e 7337 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
bogdanm 82:6473597d706e 7338 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
bogdanm 82:6473597d706e 7339 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
bogdanm 82:6473597d706e 7340 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
bogdanm 82:6473597d706e 7341 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
bogdanm 82:6473597d706e 7342 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
bogdanm 82:6473597d706e 7343 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
bogdanm 82:6473597d706e 7344 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 82:6473597d706e 7345 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
bogdanm 82:6473597d706e 7346 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
bogdanm 82:6473597d706e 7347 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
bogdanm 82:6473597d706e 7348 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
bogdanm 82:6473597d706e 7349 /******************* Bit definition for TIM_CNT register ********************/
bogdanm 82:6473597d706e 7350 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
bogdanm 82:6473597d706e 7351 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
bogdanm 82:6473597d706e 7352 /******************* Bit definition for TIM_PSC register ********************/
bogdanm 82:6473597d706e 7353 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
bogdanm 82:6473597d706e 7354
bogdanm 82:6473597d706e 7355 /******************* Bit definition for TIM_ARR register ********************/
bogdanm 82:6473597d706e 7356 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
bogdanm 82:6473597d706e 7357
bogdanm 82:6473597d706e 7358 /******************* Bit definition for TIM_RCR register ********************/
bogdanm 82:6473597d706e 7359 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
bogdanm 82:6473597d706e 7360
bogdanm 82:6473597d706e 7361 /******************* Bit definition for TIM_CCR1 register *******************/
bogdanm 82:6473597d706e 7362 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
bogdanm 82:6473597d706e 7363
bogdanm 82:6473597d706e 7364 /******************* Bit definition for TIM_CCR2 register *******************/
bogdanm 82:6473597d706e 7365 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
bogdanm 82:6473597d706e 7366
bogdanm 82:6473597d706e 7367 /******************* Bit definition for TIM_CCR3 register *******************/
bogdanm 82:6473597d706e 7368 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
bogdanm 82:6473597d706e 7369
bogdanm 82:6473597d706e 7370 /******************* Bit definition for TIM_CCR4 register *******************/
bogdanm 82:6473597d706e 7371 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
bogdanm 82:6473597d706e 7372
bogdanm 82:6473597d706e 7373 /******************* Bit definition for TIM_CCR5 register *******************/
bogdanm 82:6473597d706e 7374 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
bogdanm 82:6473597d706e 7375 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
bogdanm 82:6473597d706e 7376 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
bogdanm 82:6473597d706e 7377 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
bogdanm 82:6473597d706e 7378
bogdanm 82:6473597d706e 7379 /******************* Bit definition for TIM_CCR6 register *******************/
bogdanm 82:6473597d706e 7380 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
bogdanm 82:6473597d706e 7381
bogdanm 82:6473597d706e 7382 /******************* Bit definition for TIM_BDTR register *******************/
bogdanm 82:6473597d706e 7383 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 82:6473597d706e 7384 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 82:6473597d706e 7385 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 82:6473597d706e 7386 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 82:6473597d706e 7387 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 82:6473597d706e 7388 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 82:6473597d706e 7389 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 82:6473597d706e 7390 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 82:6473597d706e 7391 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 82:6473597d706e 7392
bogdanm 82:6473597d706e 7393 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
bogdanm 82:6473597d706e 7394 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 82:6473597d706e 7395 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 82:6473597d706e 7396
bogdanm 82:6473597d706e 7397 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
bogdanm 82:6473597d706e 7398 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
bogdanm 82:6473597d706e 7399 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
bogdanm 82:6473597d706e 7400 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
bogdanm 82:6473597d706e 7401 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
bogdanm 82:6473597d706e 7402 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
bogdanm 82:6473597d706e 7403
bogdanm 82:6473597d706e 7404 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
bogdanm 82:6473597d706e 7405 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
bogdanm 82:6473597d706e 7406
bogdanm 82:6473597d706e 7407 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
bogdanm 82:6473597d706e 7408 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
bogdanm 82:6473597d706e 7409
bogdanm 82:6473597d706e 7410 /******************* Bit definition for TIM_DCR register ********************/
bogdanm 82:6473597d706e 7411 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
bogdanm 82:6473597d706e 7412 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 82:6473597d706e 7413 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 82:6473597d706e 7414 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 82:6473597d706e 7415 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 82:6473597d706e 7416 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
bogdanm 82:6473597d706e 7417
bogdanm 82:6473597d706e 7418 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
bogdanm 82:6473597d706e 7419 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 82:6473597d706e 7420 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 82:6473597d706e 7421 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
bogdanm 82:6473597d706e 7422 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
bogdanm 82:6473597d706e 7423 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
bogdanm 82:6473597d706e 7424
bogdanm 82:6473597d706e 7425 /******************* Bit definition for TIM_DMAR register *******************/
bogdanm 82:6473597d706e 7426 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
bogdanm 82:6473597d706e 7427
bogdanm 82:6473597d706e 7428 /******************* Bit definition for TIM16_OR register *********************/
bogdanm 82:6473597d706e 7429 #define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
bogdanm 82:6473597d706e 7430 #define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
bogdanm 82:6473597d706e 7431 #define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
bogdanm 82:6473597d706e 7432
bogdanm 82:6473597d706e 7433 /******************* Bit definition for TIM1_OR register *********************/
bogdanm 82:6473597d706e 7434 #define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
bogdanm 82:6473597d706e 7435 #define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 82:6473597d706e 7436 #define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 82:6473597d706e 7437 #define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 82:6473597d706e 7438 #define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 82:6473597d706e 7439
bogdanm 82:6473597d706e 7440 /******************* Bit definition for TIM8_OR register *********************/
bogdanm 82:6473597d706e 7441 #define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
bogdanm 82:6473597d706e 7442 #define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 82:6473597d706e 7443 #define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 82:6473597d706e 7444 #define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 82:6473597d706e 7445 #define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 82:6473597d706e 7446
bogdanm 82:6473597d706e 7447 /****************** Bit definition for TIM_CCMR3 register *******************/
bogdanm 82:6473597d706e 7448 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
bogdanm 82:6473597d706e 7449 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
bogdanm 82:6473597d706e 7450
bogdanm 82:6473597d706e 7451 #define TIM_CCMR3_OC5M ((uint32_t)0x00000070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
bogdanm 82:6473597d706e 7452 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 82:6473597d706e 7453 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 82:6473597d706e 7454 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 82:6473597d706e 7455 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7456
bogdanm 82:6473597d706e 7457 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
bogdanm 82:6473597d706e 7458
bogdanm 82:6473597d706e 7459 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
bogdanm 82:6473597d706e 7460 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
bogdanm 82:6473597d706e 7461
bogdanm 82:6473597d706e 7462 #define TIM_CCMR3_OC6M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 82:6473597d706e 7463 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 82:6473597d706e 7464 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 82:6473597d706e 7465 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 82:6473597d706e 7466 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 82:6473597d706e 7467
bogdanm 82:6473597d706e 7468 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
bogdanm 82:6473597d706e 7469
bogdanm 82:6473597d706e 7470 /******************************************************************************/
bogdanm 82:6473597d706e 7471 /* */
bogdanm 82:6473597d706e 7472 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm 82:6473597d706e 7473 /* */
bogdanm 82:6473597d706e 7474 /******************************************************************************/
bogdanm 82:6473597d706e 7475 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 82:6473597d706e 7476 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
bogdanm 82:6473597d706e 7477 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
bogdanm 82:6473597d706e 7478 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
bogdanm 82:6473597d706e 7479 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
bogdanm 82:6473597d706e 7480 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
bogdanm 82:6473597d706e 7481 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
bogdanm 82:6473597d706e 7482 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
bogdanm 82:6473597d706e 7483 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
bogdanm 82:6473597d706e 7484 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
bogdanm 82:6473597d706e 7485 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
bogdanm 82:6473597d706e 7486 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
bogdanm 82:6473597d706e 7487 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
bogdanm 82:6473597d706e 7488 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
bogdanm 82:6473597d706e 7489 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
bogdanm 82:6473597d706e 7490 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
bogdanm 82:6473597d706e 7491 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
bogdanm 82:6473597d706e 7492 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
bogdanm 82:6473597d706e 7493 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 82:6473597d706e 7494 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 82:6473597d706e 7495 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 82:6473597d706e 7496 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 82:6473597d706e 7497 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 82:6473597d706e 7498 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
bogdanm 82:6473597d706e 7499 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 82:6473597d706e 7500 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 82:6473597d706e 7501 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
bogdanm 82:6473597d706e 7502 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
bogdanm 82:6473597d706e 7503 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
bogdanm 82:6473597d706e 7504 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
bogdanm 82:6473597d706e 7505 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
bogdanm 82:6473597d706e 7506
bogdanm 82:6473597d706e 7507 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 82:6473597d706e 7508 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
bogdanm 82:6473597d706e 7509 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
bogdanm 82:6473597d706e 7510 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
bogdanm 82:6473597d706e 7511 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
bogdanm 82:6473597d706e 7512 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
bogdanm 82:6473597d706e 7513 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
bogdanm 82:6473597d706e 7514 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
bogdanm 82:6473597d706e 7515 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
bogdanm 82:6473597d706e 7516 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 82:6473597d706e 7517 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 82:6473597d706e 7518 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
bogdanm 82:6473597d706e 7519 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
bogdanm 82:6473597d706e 7520 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
bogdanm 82:6473597d706e 7521 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
bogdanm 82:6473597d706e 7522 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
bogdanm 82:6473597d706e 7523 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
bogdanm 82:6473597d706e 7524 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
bogdanm 82:6473597d706e 7525 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
bogdanm 82:6473597d706e 7526 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 82:6473597d706e 7527 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 82:6473597d706e 7528 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
bogdanm 82:6473597d706e 7529 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
bogdanm 82:6473597d706e 7530
bogdanm 82:6473597d706e 7531 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 82:6473597d706e 7532 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
bogdanm 82:6473597d706e 7533 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
bogdanm 82:6473597d706e 7534 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
bogdanm 82:6473597d706e 7535 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
bogdanm 82:6473597d706e 7536 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
bogdanm 82:6473597d706e 7537 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
bogdanm 82:6473597d706e 7538 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
bogdanm 82:6473597d706e 7539 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
bogdanm 82:6473597d706e 7540 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
bogdanm 82:6473597d706e 7541 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
bogdanm 82:6473597d706e 7542 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
bogdanm 82:6473597d706e 7543 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
bogdanm 82:6473597d706e 7544 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
bogdanm 82:6473597d706e 7545 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
bogdanm 82:6473597d706e 7546 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
bogdanm 82:6473597d706e 7547 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
bogdanm 82:6473597d706e 7548 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
bogdanm 82:6473597d706e 7549 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 82:6473597d706e 7550 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 82:6473597d706e 7551 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
bogdanm 82:6473597d706e 7552 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
bogdanm 82:6473597d706e 7553 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 82:6473597d706e 7554 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 82:6473597d706e 7555 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
bogdanm 82:6473597d706e 7556
bogdanm 82:6473597d706e 7557 /****************** Bit definition for USART_BRR register *******************/
bogdanm 82:6473597d706e 7558 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
bogdanm 82:6473597d706e 7559 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
bogdanm 82:6473597d706e 7560
bogdanm 82:6473597d706e 7561 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 82:6473597d706e 7562 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
bogdanm 82:6473597d706e 7563 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
bogdanm 82:6473597d706e 7564
bogdanm 82:6473597d706e 7565
bogdanm 82:6473597d706e 7566 /******************* Bit definition for USART_RTOR register *****************/
bogdanm 82:6473597d706e 7567 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
bogdanm 82:6473597d706e 7568 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
bogdanm 82:6473597d706e 7569
bogdanm 82:6473597d706e 7570 /******************* Bit definition for USART_RQR register ******************/
bogdanm 82:6473597d706e 7571 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
bogdanm 82:6473597d706e 7572 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
bogdanm 82:6473597d706e 7573 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
bogdanm 82:6473597d706e 7574 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
bogdanm 82:6473597d706e 7575 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
bogdanm 82:6473597d706e 7576
bogdanm 82:6473597d706e 7577 /******************* Bit definition for USART_ISR register ******************/
bogdanm 82:6473597d706e 7578 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
bogdanm 82:6473597d706e 7579 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
bogdanm 82:6473597d706e 7580 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
bogdanm 82:6473597d706e 7581 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
bogdanm 82:6473597d706e 7582 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
bogdanm 82:6473597d706e 7583 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
bogdanm 82:6473597d706e 7584 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
bogdanm 82:6473597d706e 7585 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
bogdanm 82:6473597d706e 7586 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
bogdanm 82:6473597d706e 7587 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
bogdanm 82:6473597d706e 7588 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
bogdanm 82:6473597d706e 7589 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
bogdanm 82:6473597d706e 7590 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
bogdanm 82:6473597d706e 7591 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
bogdanm 82:6473597d706e 7592 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
bogdanm 82:6473597d706e 7593 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
bogdanm 82:6473597d706e 7594 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
bogdanm 82:6473597d706e 7595 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
bogdanm 82:6473597d706e 7596 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
bogdanm 82:6473597d706e 7597 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
bogdanm 82:6473597d706e 7598 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
bogdanm 82:6473597d706e 7599 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
bogdanm 82:6473597d706e 7600
bogdanm 82:6473597d706e 7601 /******************* Bit definition for USART_ICR register ******************/
bogdanm 82:6473597d706e 7602 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
bogdanm 82:6473597d706e 7603 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
bogdanm 82:6473597d706e 7604 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
bogdanm 82:6473597d706e 7605 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
bogdanm 82:6473597d706e 7606 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
bogdanm 82:6473597d706e 7607 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
bogdanm 82:6473597d706e 7608 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
bogdanm 82:6473597d706e 7609 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
bogdanm 82:6473597d706e 7610 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
bogdanm 82:6473597d706e 7611 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
bogdanm 82:6473597d706e 7612 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
bogdanm 82:6473597d706e 7613 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
bogdanm 82:6473597d706e 7614
bogdanm 82:6473597d706e 7615 /******************* Bit definition for USART_RDR register ******************/
bogdanm 82:6473597d706e 7616 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
bogdanm 82:6473597d706e 7617
bogdanm 82:6473597d706e 7618 /******************* Bit definition for USART_TDR register ******************/
bogdanm 82:6473597d706e 7619 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
bogdanm 82:6473597d706e 7620
bogdanm 82:6473597d706e 7621 /******************************************************************************/
bogdanm 82:6473597d706e 7622 /* */
bogdanm 82:6473597d706e 7623 /* Window WATCHDOG */
bogdanm 82:6473597d706e 7624 /* */
bogdanm 82:6473597d706e 7625 /******************************************************************************/
bogdanm 82:6473597d706e 7626 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 82:6473597d706e 7627 #define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 82:6473597d706e 7628 #define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
bogdanm 82:6473597d706e 7629 #define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
bogdanm 82:6473597d706e 7630 #define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
bogdanm 82:6473597d706e 7631 #define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
bogdanm 82:6473597d706e 7632 #define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
bogdanm 82:6473597d706e 7633 #define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
bogdanm 82:6473597d706e 7634 #define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
bogdanm 82:6473597d706e 7635
bogdanm 82:6473597d706e 7636 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
bogdanm 82:6473597d706e 7637
bogdanm 82:6473597d706e 7638 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 82:6473597d706e 7639 #define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
bogdanm 82:6473597d706e 7640 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 82:6473597d706e 7641 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 82:6473597d706e 7642 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 82:6473597d706e 7643 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 82:6473597d706e 7644 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
bogdanm 82:6473597d706e 7645 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
bogdanm 82:6473597d706e 7646 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
bogdanm 82:6473597d706e 7647
bogdanm 82:6473597d706e 7648 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
bogdanm 82:6473597d706e 7649 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
bogdanm 82:6473597d706e 7650 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
bogdanm 82:6473597d706e 7651
bogdanm 82:6473597d706e 7652 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
bogdanm 82:6473597d706e 7653
bogdanm 82:6473597d706e 7654 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 82:6473597d706e 7655 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
bogdanm 82:6473597d706e 7656
bogdanm 82:6473597d706e 7657 /**
bogdanm 82:6473597d706e 7658 * @}
bogdanm 82:6473597d706e 7659 */
bogdanm 82:6473597d706e 7660
bogdanm 82:6473597d706e 7661 /**
bogdanm 82:6473597d706e 7662 * @}
bogdanm 82:6473597d706e 7663 */
bogdanm 82:6473597d706e 7664
bogdanm 82:6473597d706e 7665 #ifdef USE_STDPERIPH_DRIVER
bogdanm 82:6473597d706e 7666 #include "stm32f30x_conf.h"
bogdanm 82:6473597d706e 7667 #endif /*!< USE_STDPERIPH_DRIVER */
bogdanm 82:6473597d706e 7668
bogdanm 82:6473597d706e 7669 /** @addtogroup Exported_macro
bogdanm 82:6473597d706e 7670 * @{
bogdanm 82:6473597d706e 7671 */
bogdanm 82:6473597d706e 7672
bogdanm 82:6473597d706e 7673 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
bogdanm 82:6473597d706e 7674
bogdanm 82:6473597d706e 7675 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
bogdanm 82:6473597d706e 7676
bogdanm 82:6473597d706e 7677 #define READ_BIT(REG, BIT) ((REG) & (BIT))
bogdanm 82:6473597d706e 7678
bogdanm 82:6473597d706e 7679 #define CLEAR_REG(REG) ((REG) = (0x0))
bogdanm 82:6473597d706e 7680
bogdanm 82:6473597d706e 7681 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
bogdanm 82:6473597d706e 7682
bogdanm 82:6473597d706e 7683 #define READ_REG(REG) ((REG))
bogdanm 82:6473597d706e 7684
bogdanm 82:6473597d706e 7685 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
bogdanm 82:6473597d706e 7686
bogdanm 82:6473597d706e 7687 /**
bogdanm 82:6473597d706e 7688 * @}
bogdanm 82:6473597d706e 7689 */
bogdanm 82:6473597d706e 7690
bogdanm 82:6473597d706e 7691 #ifdef __cplusplus
bogdanm 82:6473597d706e 7692 }
bogdanm 82:6473597d706e 7693 #endif /* __cplusplus */
bogdanm 82:6473597d706e 7694
bogdanm 82:6473597d706e 7695 #endif /* __STM32F30x_H */
bogdanm 82:6473597d706e 7696
bogdanm 82:6473597d706e 7697 /**
bogdanm 82:6473597d706e 7698 * @}
bogdanm 82:6473597d706e 7699 */
bogdanm 82:6473597d706e 7700
bogdanm 82:6473597d706e 7701 /**
bogdanm 82:6473597d706e 7702 * @}
bogdanm 82:6473597d706e 7703 */
bogdanm 82:6473597d706e 7704
bogdanm 82:6473597d706e 7705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/